[llvm] b6e344c - [RISCV] Add Predicates to the XVentanaCondOps isel patterns.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-12-19T19:29:00-08:00
New Revision: b6e344ce91c8796331fca7644eb8c748ac5391ec

URL: https://github.com/llvm/llvm-project/commit/b6e344ce91c8796331fca7644eb8c748ac5391ec
DIFF: https://github.com/llvm/llvm-project/commit/b6e344ce91c8796331fca7644eb8c748ac5391ec.diff

LOG: [RISCV] Add Predicates to the XVentanaCondOps isel patterns.

Missed this in the review of D139394. Not a functional issue because
select only makes it to isel with XVentanaCondOps.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
index b698413d8c188..262df67c370ac 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
@@ -35,6 +35,7 @@ multiclass XVentanaCondops_pats<SDPatternOperator Op, RVInst MI> {
            (MI $rs1, (VT_MASKCN $rs2, $rc))>;
 }
 
+let Predicates = [IsRV64, HasVendorXVentanaCondOps] in {
 // Directly use MASKC/MASKCN in case of any of the operands being 0.
 def: Pat<(select i64:$rc, i64:$rs1, (i64 0)),
          (VT_MASKC $rs1, $rc)>;
@@ -56,3 +57,4 @@ def: Pat<(select i64:$rc, i64:$rs1, (and i64:$rs1, i64:$rs2)),
 // Basic select pattern that selects between 2 registers.
 def: Pat<(select i64:$rc, i64:$rs1, i64:$rs2),
          (OR (VT_MASKC $rs1, $rc), (VT_MASKCN $rs2, $rc))>;
+} // Predicates = [IsRV64, HasVendorXVentanaCondOps]