[llvm] 0dc4bdd - GlobalISel: Enable CSE of G_SELECT

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2022-12-19T21:26:47-05:00
New Revision: 0dc4bdd8887758d6d55337f366c66f41e42a7b97

URL: https://github.com/llvm/llvm-project/commit/0dc4bdd8887758d6d55337f366c66f41e42a7b97
DIFF: https://github.com/llvm/llvm-project/commit/0dc4bdd8887758d6d55337f366c66f41e42a7b97.diff

LOG: GlobalISel: Enable CSE of G_SELECT

Stop trying to delete a select in one combine since it would
be deleting the CSE'd instruction if that happened.

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
    llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
index 6a0d1c33d3e3c..4257fc6f8ae51 100644
--- a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
@@ -61,6 +61,7 @@ bool CSEConfigFull::shouldCSEOpc(unsigned Opc) {
   case TargetOpcode::G_TRUNC:
   case TargetOpcode::G_PTR_ADD:
   case TargetOpcode::G_EXTRACT:
+  case TargetOpcode::G_SELECT:
     return true;
   }
   return false;

diff  --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 5ff3dd26f5fc9..d9ae99f68f36f 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -3262,8 +3262,6 @@ bool CombinerHelper::applyFoldBinOpIntoSelect(MachineInstr &MI,
   }
 
   Builder.buildSelect(Dst, SelectCond, FoldTrue, FoldFalse, MI.getFlags());
-  Observer.erasingInstr(*Select);
-  Select->eraseFromParent();
   MI.eraseFromParent();
 
   return true;

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
index add7816778eb6..b633fff9ae508 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
@@ -938,8 +938,8 @@ body: |
     ; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
     ; CHECK-NEXT: %ten:_(s32) = G_CONSTANT i32 10
     ; CHECK-NEXT: %twenty:_(s32) = G_CONSTANT i32 20
-    ; CHECK-NEXT: %smin:_(s32) = G_SELECT %cond(s1), %ten, %twenty
-    ; CHECK-NEXT: S_ENDPGM 0, implicit %smin(s32)
+    ; CHECK-NEXT: %select:_(s32) = G_SELECT %cond(s1), %ten, %twenty
+    ; CHECK-NEXT: S_ENDPGM 0, implicit %select(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
     %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
@@ -987,8 +987,8 @@ body: |
     ; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
     ; CHECK-NEXT: %ten:_(s32) = G_CONSTANT i32 10
     ; CHECK-NEXT: %twenty:_(s32) = G_CONSTANT i32 20
-    ; CHECK-NEXT: %umin:_(s32) = G_SELECT %cond(s1), %ten, %twenty
-    ; CHECK-NEXT: S_ENDPGM 0, implicit %umin(s32)
+    ; CHECK-NEXT: %select:_(s32) = G_SELECT %cond(s1), %ten, %twenty
+    ; CHECK-NEXT: S_ENDPGM 0, implicit %select(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
     %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero