[llvm] d4f3d82 - [OpenMP][FIX] Ensure to inline `ompx::` functions after the rename in D140334
Johannes Doerfert via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 19 16:42:15 PST 2022
Author: Johannes Doerfert
Date: 2022-12-19T16:41:49-08:00
New Revision: d4f3d8212a063d1f7850809fc3e4864c8b6e54a9
URL: https://github.com/llvm/llvm-project/commit/d4f3d8212a063d1f7850809fc3e4864c8b6e54a9
DIFF: https://github.com/llvm/llvm-project/commit/d4f3d8212a063d1f7850809fc3e4864c8b6e54a9.diff
LOG: [OpenMP][FIX] Ensure to inline `ompx::` functions after the rename in D140334
Added:
Modified:
llvm/lib/Transforms/IPO/OpenMPOpt.cpp
llvm/test/Transforms/OpenMP/attributor_pointer_offset_crash.ll
llvm/test/Transforms/OpenMP/remove_noinline_attributes.ll
llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp
index 46d9deeb45b26..d6cb75ba9364f 100644
--- a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp
+++ b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp
@@ -498,11 +498,11 @@ struct OMPInformationCache : public InformationCache {
}
#include "llvm/Frontend/OpenMP/OMPKinds.def"
- // Remove the `noinline` attribute from `__kmpc`, `_OMP::` and `omp_`
+ // Remove the `noinline` attribute from `__kmpc`, `ompx::` and `omp_`
// functions, except if `optnone` is present.
if (isOpenMPDevice(M)) {
for (Function &F : M) {
- for (StringRef Prefix : {"__kmpc", "_ZN4_OMP", "omp_"})
+ for (StringRef Prefix : {"__kmpc", "_ZN4ompx", "omp_"})
if (F.hasFnAttribute(Attribute::NoInline) &&
F.getName().startswith(Prefix) &&
!F.hasFnAttribute(Attribute::OptimizeNone))
diff --git a/llvm/test/Transforms/OpenMP/attributor_pointer_offset_crash.ll b/llvm/test/Transforms/OpenMP/attributor_pointer_offset_crash.ll
index 080ae279c2a58..05dd79410cbc1 100644
--- a/llvm/test/Transforms/OpenMP/attributor_pointer_offset_crash.ll
+++ b/llvm/test/Transforms/OpenMP/attributor_pointer_offset_crash.ll
@@ -12,12 +12,12 @@ target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:3
define internal i8* @__kmpc_alloc_shared() {
lor.lhs.false.i.i:
- br i1 false, label %_ZN4_OMP5state8lookup32ENS0_9ValueKindEb.exit.i, label %if.then.i44.i.i
+ br i1 false, label %_ZN4ompx5state8lookup32ENS0_9ValueKindEb.exit.i, label %if.then.i44.i.i
if.then.i44.i.i: ; preds = %lor.lhs.false.i.i
- br label %_ZN4_OMP5state8lookup32ENS0_9ValueKindEb.exit.i
+ br label %_ZN4ompx5state8lookup32ENS0_9ValueKindEb.exit.i
-_ZN4_OMP5state8lookup32ENS0_9ValueKindEb.exit.i: ; preds = %if.then.i44.i.i, %lor.lhs.false.i.i
+_ZN4ompx5state8lookup32ENS0_9ValueKindEb.exit.i: ; preds = %if.then.i44.i.i, %lor.lhs.false.i.i
%.pn.i45.i.i = phi i8* [ null, %if.then.i44.i.i ], [ addrspacecast (i8 addrspace(3)* bitcast (%"struct.(anonymous namespace)::TeamStateTy" addrspace(3)* @_ZN12_GLOBAL__N_19TeamStateE to i8 addrspace(3)*) to i8*), %lor.lhs.false.i.i ]
%retval.0.in.i.i.i = getelementptr inbounds i8, i8* %.pn.i45.i.i, i64 4
%retval.0.i46.i.i = bitcast i8* %retval.0.in.i.i.i to i32*
diff --git a/llvm/test/Transforms/OpenMP/remove_noinline_attributes.ll b/llvm/test/Transforms/OpenMP/remove_noinline_attributes.ll
index 9689228a8404f..ecf34f3becb2a 100644
--- a/llvm/test/Transforms/OpenMP/remove_noinline_attributes.ll
+++ b/llvm/test/Transforms/OpenMP/remove_noinline_attributes.ll
@@ -24,9 +24,9 @@ define void @omp_noinline() noinline nounwind {
ret void
}
; _OMP namespace
-define void @_ZN4_OMP_noinline() noinline nounwind {
+define void @_ZN4ompx_noinline() noinline nounwind {
; CHECK: Function Attrs: nounwind
-; CHECK-LABEL: define {{[^@]+}}@_ZN4_OMP_noinline(
+; CHECK-LABEL: define {{[^@]+}}@_ZN4ompx_noinline(
; CHECK-NEXT: call void @unknown()
; CHECK-NEXT: ret void
;
@@ -55,9 +55,9 @@ define void @omp_noinline_optnone() noinline optnone nounwind {
ret void
}
; _OMP namespace
-define void @_ZN4_OMP_noinline_optnone() noinline optnone nounwind {
+define void @_ZN4ompx_noinline_optnone() noinline optnone nounwind {
; CHECK: Function Attrs: noinline nounwind optnone
-; CHECK-LABEL: define {{[^@]+}}@_ZN4_OMP_noinline_optnone(
+; CHECK-LABEL: define {{[^@]+}}@_ZN4ompx_noinline_optnone(
; CHECK-NEXT: call void @unknown()
; CHECK-NEXT: ret void
;
@@ -82,9 +82,9 @@ define void @a_omp_noinline() noinline nounwind {
call void @unknown()
ret void
}
-define void @a__ZN4_OMP_noinline() noinline nounwind {
+define void @a__ZN4ompx_noinline() noinline nounwind {
; CHECK: Function Attrs: noinline nounwind
-; CHECK-LABEL: define {{[^@]+}}@a__ZN4_OMP_noinline(
+; CHECK-LABEL: define {{[^@]+}}@a__ZN4ompx_noinline(
; CHECK-NEXT: call void @unknown()
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll b/llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll
index befff79bf4973..c7c34d342964d 100644
--- a/llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll
+++ b/llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll
@@ -97,7 +97,7 @@ declare void @llvm.assume(i1 noundef) #6
declare void @llvm.amdgcn.s.barrier() #7
; Function Attrs: convergent mustprogress noinline nounwind willreturn
-define internal fastcc void @_ZN4_OMP11synchronize14threadsAlignedEv() unnamed_addr #8 {
+define internal fastcc void @_ZN4ompx11synchronize14threadsAlignedEv() unnamed_addr #8 {
entry:
call void @llvm.amdgcn.s.barrier() #13
ret void
@@ -126,7 +126,7 @@ if.then: ; preds = %entry
%cmp4.i.i.i = icmp ult i32 %2, %9
call void @llvm.assume(i1 %cmp4.i.i.i) #13
%cmp.i.i8 = icmp eq i32 %2, 0
- br i1 %cmp.i.i8, label %if.then.i, label %_ZN4_OMP5state4initEb.exit.critedge
+ br i1 %cmp.i.i8, label %if.then.i, label %_ZN4ompx5state4initEb.exit.critedge
if.then.i: ; preds = %if.then
store i32 1, ptr addrspace(3) @IsSPMDMode, align 4, !tbaa !14
@@ -139,17 +139,17 @@ if.then.i: ; preds = %if.then
store i32 1, ptr addrspace(3) getelementptr inbounds (%"struct.(anonymous namespace)::TeamStateTy", ptr addrspace(3) @_ZN12_GLOBAL__N_19TeamStateE, i32 0, i32 0, i32 5), align 4, !tbaa !27
store i32 1, ptr addrspace(3) getelementptr inbounds (%"struct.(anonymous namespace)::TeamStateTy", ptr addrspace(3) @_ZN12_GLOBAL__N_19TeamStateE, i32 0, i32 1), align 8, !tbaa !28
store ptr null, ptr addrspace(3) getelementptr inbounds (%"struct.(anonymous namespace)::TeamStateTy", ptr addrspace(3) @_ZN12_GLOBAL__N_19TeamStateE, i32 0, i32 2), align 8, !tbaa !29
- br label %_ZN4_OMP5state4initEb.exit
+ br label %_ZN4ompx5state4initEb.exit
-_ZN4_OMP5state4initEb.exit.critedge: ; preds = %if.then
+_ZN4ompx5state4initEb.exit.critedge: ; preds = %if.then
%arrayidx.i.i.c = getelementptr inbounds [1024 x i8], ptr addrspace(3) getelementptr inbounds (%"struct.(anonymous namespace)::SharedMemorySmartStackTy", ptr addrspace(3) @_ZN12_GLOBAL__N_122SharedMemorySmartStackE, i32 0, i32 1, i32 0), i32 0, i32 %2
store i8 0, ptr addrspace(3) %arrayidx.i.i.c, align 1, !tbaa !18
- br label %_ZN4_OMP5state4initEb.exit
+ br label %_ZN4ompx5state4initEb.exit
-_ZN4_OMP5state4initEb.exit: ; preds = %_ZN4_OMP5state4initEb.exit.critedge, %if.then.i
+_ZN4ompx5state4initEb.exit: ; preds = %_ZN4ompx5state4initEb.exit.critedge, %if.then.i
%arrayidx.i = getelementptr inbounds [1024 x ptr], ptr addrspace(3) @_ZN12_GLOBAL__N_112ThreadStatesE, i32 0, i32 %2
store ptr null, ptr addrspace(3) %arrayidx.i, align 8, !tbaa !30
- call fastcc void @_ZN4_OMP11synchronize14threadsAlignedEv() #14
+ call fastcc void @_ZN4ompx11synchronize14threadsAlignedEv() #14
br label %if.end
if.else: ; preds = %entry
@@ -169,7 +169,7 @@ if.else: ; preds = %entry
%sub.i.i.i27 = add nsw i32 %16, -1
%and.i.i.i28 = and i32 %sub.i.i.i27, -64
%cmp.i2.i.i29 = icmp eq i32 %17, %and.i.i.i28
- br i1 %cmp.i2.i.i29, label %if.then.i30, label %_ZN4_OMP5state4initEb.exit55.critedge
+ br i1 %cmp.i2.i.i29, label %if.then.i30, label %_ZN4ompx5state4initEb.exit55.critedge
if.then.i30: ; preds = %if.else
store i32 0, ptr addrspace(3) @IsSPMDMode, align 4, !tbaa !14
@@ -184,19 +184,19 @@ if.then.i30: ; preds = %if.else
store i32 1, ptr addrspace(3) getelementptr inbounds (%"struct.(anonymous namespace)::TeamStateTy", ptr addrspace(3) @_ZN12_GLOBAL__N_19TeamStateE, i32 0, i32 0, i32 5), align 4, !tbaa !27
store i32 1, ptr addrspace(3) getelementptr inbounds (%"struct.(anonymous namespace)::TeamStateTy", ptr addrspace(3) @_ZN12_GLOBAL__N_19TeamStateE, i32 0, i32 1), align 8, !tbaa !28
store ptr null, ptr addrspace(3) getelementptr inbounds (%"struct.(anonymous namespace)::TeamStateTy", ptr addrspace(3) @_ZN12_GLOBAL__N_19TeamStateE, i32 0, i32 2), align 8, !tbaa !29
- br label %_ZN4_OMP5state4initEb.exit55
+ br label %_ZN4ompx5state4initEb.exit55
-_ZN4_OMP5state4initEb.exit55.critedge: ; preds = %if.else
+_ZN4ompx5state4initEb.exit55.critedge: ; preds = %if.else
%arrayidx.i.i46.c = getelementptr inbounds [1024 x i8], ptr addrspace(3) getelementptr inbounds (%"struct.(anonymous namespace)::SharedMemorySmartStackTy", ptr addrspace(3) @_ZN12_GLOBAL__N_122SharedMemorySmartStackE, i32 0, i32 1, i32 0), i32 0, i32 %17
store i8 0, ptr addrspace(3) %arrayidx.i.i46.c, align 1, !tbaa !18
- br label %_ZN4_OMP5state4initEb.exit55
+ br label %_ZN4ompx5state4initEb.exit55
-_ZN4_OMP5state4initEb.exit55: ; preds = %_ZN4_OMP5state4initEb.exit55.critedge, %if.then.i30
+_ZN4ompx5state4initEb.exit55: ; preds = %_ZN4ompx5state4initEb.exit55.critedge, %if.then.i30
%arrayidx.i53 = getelementptr inbounds [1024 x ptr], ptr addrspace(3) @_ZN12_GLOBAL__N_112ThreadStatesE, i32 0, i32 %17
store ptr null, ptr addrspace(3) %arrayidx.i53, align 8, !tbaa !30
br label %if.end
-if.end: ; preds = %_ZN4_OMP5state4initEb.exit55, %_ZN4_OMP5state4initEb.exit
+if.end: ; preds = %_ZN4ompx5state4initEb.exit55, %_ZN4ompx5state4initEb.exit
%18 = call i32 @llvm.amdgcn.workgroup.id.x() #13
%19 = call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #13
%20 = getelementptr i8, ptr addrspace(4) %19, i64 12
@@ -210,9 +210,9 @@ if.end: ; preds = %_ZN4_OMP5state4init
%25 = call i32 @llvm.amdgcn.workitem.id.x() #13
%cmp.i.i.i79 = icmp ult i32 %25, %24
call void @llvm.assume(i1 %cmp.i.i.i79) #13
- br i1 %tobool.not, label %_ZN4_OMP7mapping23isInitialThreadInLevel0Eb.exit, label %_ZN4_OMP7mapping12getBlockSizeEb.exit.i64
+ br i1 %tobool.not, label %_ZN4ompx7mapping23isInitialThreadInLevel0Eb.exit, label %_ZN4ompx7mapping12getBlockSizeEb.exit.i64
-_ZN4_OMP7mapping12getBlockSizeEb.exit.i64: ; preds = %if.end
+_ZN4ompx7mapping12getBlockSizeEb.exit.i64: ; preds = %if.end
%26 = load i32, ptr addrspace(3) @_ZN12_GLOBAL__N_19TeamStateE, align 8
%cmp.i.i.i63 = icmp eq i32 %24, %26
call void @llvm.assume(i1 %cmp.i.i.i63) #13
@@ -239,13 +239,13 @@ _ZN4_OMP7mapping12getBlockSizeEb.exit.i64: ; preds = %if.end
call void @llvm.assume(i1 %tobool.i59.i) #13
br label %_ZN14DebugEntryRAIID2Ev.exit250
-_ZN4_OMP7mapping23isInitialThreadInLevel0Eb.exit: ; preds = %if.end
+_ZN4ompx7mapping23isInitialThreadInLevel0Eb.exit: ; preds = %if.end
%sub.i.i83 = add nsw i32 %24, -1
%and.i.i84 = and i32 %sub.i.i83, -64
%cmp.i2.i = icmp eq i32 %25, %and.i.i84
br i1 %cmp.i2.i, label %_ZN14DebugEntryRAIID2Ev.exit250, label %if.end10
-if.end10: ; preds = %_ZN4_OMP7mapping23isInitialThreadInLevel0Eb.exit
+if.end10: ; preds = %_ZN4ompx7mapping23isInitialThreadInLevel0Eb.exit
%sub.i = add nsw i32 %24, -64
%cmp = icmp ult i32 %25, %sub.i
%or.cond251 = select i1 %UseGenericStateMachine, i1 %cmp, i1 false
@@ -255,8 +255,8 @@ do.body.i: ; preds = %if.end10
call void @llvm.amdgcn.s.barrier() #13
br label %_ZN14DebugEntryRAIID2Ev.exit250
-_ZN14DebugEntryRAIID2Ev.exit250: ; preds = %do.body.i, %if.end10, %_ZN4_OMP7mapping23isInitialThreadInLevel0Eb.exit, %_ZN4_OMP7mapping12getBlockSizeEb.exit.i64
- %retval.0 = phi i32 [ -1, %_ZN4_OMP7mapping12getBlockSizeEb.exit.i64 ], [ -1, %_ZN4_OMP7mapping23isInitialThreadInLevel0Eb.exit ], [ %25, %do.body.i ], [ %25, %if.end10 ]
+_ZN14DebugEntryRAIID2Ev.exit250: ; preds = %do.body.i, %if.end10, %_ZN4ompx7mapping23isInitialThreadInLevel0Eb.exit, %_ZN4ompx7mapping12getBlockSizeEb.exit.i64
+ %retval.0 = phi i32 [ -1, %_ZN4ompx7mapping12getBlockSizeEb.exit.i64 ], [ -1, %_ZN4ompx7mapping23isInitialThreadInLevel0Eb.exit ], [ %25, %do.body.i ], [ %25, %if.end10 ]
ret i32 %retval.0
}
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