[PATCH] D130919: [MRI] isConstantPhysReg should also check if the register is clobbered by a RegMask

[Guozhi Wei via Phabricator via llvm-commits]

Carrot updated this revision to Diff 484094.
Carrot added a comment.

Rebase the code.

The new failed test pr59305.ll is another case that wrong code was generated without this patch.

Several DIV instructions crossing function call to fesetround got CSEd, fesetround is used to change rounding mode, so these DIV instructions may generate different results, they can't be CSEd.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130919/new/

https://reviews.llvm.org/D130919

Files:
  llvm/include/llvm/CodeGen/MachineInstrBuilder.h
  llvm/include/llvm/CodeGen/MachineOperand.h
  llvm/include/llvm/CodeGen/MachineRegisterInfo.h
  llvm/lib/CodeGen/MIRParser/MIParser.cpp
  llvm/lib/CodeGen/MachineOperand.cpp
  llvm/lib/CodeGen/MachineRegisterInfo.cpp
  llvm/lib/CodeGen/RegUsageInfoPropagate.cpp
  llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/lib/Target/X86/X86InstrInfo.h
  llvm/test/CodeGen/AArch64/regmask.ll
  llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
  llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
  llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
  llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
  llvm/test/CodeGen/PowerPC/cse-despite-rounding-mode.ll
  llvm/test/CodeGen/PowerPC/cxx_tlscc64.ll
  llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll
  llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
  llvm/test/CodeGen/X86/2008-10-27-CoalescerBug.ll
  llvm/test/CodeGen/X86/fp-strict-scalar-inttofp-fp16.ll
  llvm/test/CodeGen/X86/half.ll
  llvm/test/CodeGen/X86/pr29112.ll
  llvm/test/CodeGen/X86/pr59305.ll
  llvm/test/CodeGen/X86/sqrt-partial.ll
  llvm/test/CodeGen/X86/sse-intel-ocl.ll
  llvm/test/CodeGen/X86/swifterror.ll
  llvm/tools/llvm-reduce/ReducerWorkItem.cpp
  llvm/unittests/CodeGen/MachineOperandTest.cpp

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