[PATCH] D140319: [RISCV] Match neg (and x, 1) to two shifts to improve codesize

[Philip Reames via Phabricator via llvm-commits]

reames marked 2 inline comments as done.
reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1244
+// is never compressible since rs1 and rd can't be the same register.
+let Predicates = [IsRV64, HasStdExtC] in {
+def : Pat<(XLenVT (sub 0x0, (and_oneuse GPR:$rs, 0x1))),
----------------
jrtc27 wrote:
> reames wrote:
> > This shouldn't be specific to RV64, but my attempts to write a pattern which used ImmSubFromVLen kept failing type inference.  Any suggestions on how to write such a pattern?
> ImmSubFromXLen (XLenVT 1), as the issue is TableGen has no way of knowing that the type of the input is the same as the output, it just sees the input as unconstrained, only the output constrained by its use. Normally that doesn't matter because the input is a pre-existing node whose type is constrained by the pattern being matched.
Thanks!


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140319/new/

https://reviews.llvm.org/D140319