[PATCH] D140324: [SDAG] neg x with one demanded bit is x

[Philip Reames via Phabricator via llvm-commits]

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We have a version of this transform in InstCombine, but surprisingly not in SDAG.

Even more surprisingly, this benefits RISCV, but no other target.  This was surprising enough I double checked my build configuration to make sure all targets were enabled; they appear to be.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140324

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/RISCV/alu64.ll
  llvm/test/CodeGen/RISCV/bittest.ll
  llvm/test/CodeGen/RISCV/forced-atomics.ll
  llvm/test/CodeGen/RISCV/fpclamptosat.ll

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