[llvm] 3a26a65 - [SPIR-V] Disable MachineLateInstrsCleanup pass
Michal Paszkowski via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 19 10:26:50 PST 2022
Author: Michal Paszkowski
Date: 2022-12-19T19:25:33+01:00
New Revision: 3a26a650821dda1892cc47d8c5e87ea4bef6a027
URL: https://github.com/llvm/llvm-project/commit/3a26a650821dda1892cc47d8c5e87ea4bef6a027
DIFF: https://github.com/llvm/llvm-project/commit/3a26a650821dda1892cc47d8c5e87ea4bef6a027.diff
LOG: [SPIR-V] Disable MachineLateInstrsCleanup pass
This patch disables MachineLateInstrsCleanup pass (since it does not
work with virtual registers) and modifies LIT tests to run with -O0.
Differential Revision: https://reviews.llvm.org/D140103
Added:
Modified:
llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
llvm/test/CodeGen/SPIRV/instructions/atomic.ll
llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll
llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll
llvm/test/CodeGen/SPIRV/instructions/fcmp.ll
llvm/test/CodeGen/SPIRV/instructions/float-casts.ll
llvm/test/CodeGen/SPIRV/instructions/icmp.ll
llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll
llvm/test/CodeGen/SPIRV/instructions/ptrcmp.ll
llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
index 1f1aa179634b4..856e54ab47c58 100644
--- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
@@ -124,6 +124,7 @@ void SPIRVPassConfig::addPostRegAlloc() {
disablePass(&PatchableFunctionID);
disablePass(&ShrinkWrapID);
disablePass(&LiveDebugValuesID);
+ disablePass(&MachineLateInstrsCleanupID);
// Do not work with OpPhi.
disablePass(&BranchFolderPassID);
diff --git a/llvm/test/CodeGen/SPIRV/instructions/atomic.ll b/llvm/test/CodeGen/SPIRV/instructions/atomic.ll
index f53facfcaec58..9715504fcc5d3 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/atomic.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/atomic.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
; CHECK-DAG: OpName [[SUB:%.*]] "test_sub"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll b/llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll
index 014a6e41127fa..63c0ae75f5ecd 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
; CHECK-DAG: OpName [[SUB:%.*]] "test_sub"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll b/llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll
index 09f000b4e0d5f..f6a8fe1e6db18 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
; CHECK-DAG: OpName [[SUB:%.*]] "test_sub"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/fcmp.ll b/llvm/test/CodeGen/SPIRV/instructions/fcmp.ll
index d48ee0a1fde53..01d4fc44f83a5 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/fcmp.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/fcmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[UEQ:%.*]] "test_ueq"
; CHECK-DAG: OpName [[OEQ:%.*]] "test_oeq"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/float-casts.ll b/llvm/test/CodeGen/SPIRV/instructions/float-casts.ll
index ae28962fbd3cd..3b311d841623d 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/float-casts.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/float-casts.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[TRUNC32_16:%.*]] "f32tof16"
; CHECK-DAG: OpName [[EXT16_32:%.*]] "f16tof32"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/icmp.ll b/llvm/test/CodeGen/SPIRV/instructions/icmp.ll
index 367b7ff179546..28c14a99d2a08 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/icmp.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/icmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[EQ:%.*]] "test_eq"
; CHECK-DAG: OpName [[NE:%.*]] "test_ne"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll b/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
index f91ec6ecc1582..a84ef3f70c575 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[TRUNC32_16:%.*]] "i32toi16"
; CHECK-DAG: OpName [[TRUNC32_8:%.*]] "i32toi8"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll b/llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll
index 1eb4d97dd2a10..fe900d186a9f7 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll
@@ -1,4 +1,4 @@
-; RUN: llc %s -mtriple=spirv32-unknown-unknown -o - | FileCheck %s
+; RUN: llc -O0 %s -mtriple=spirv32-unknown-unknown -o - | FileCheck %s
declare float @llvm.fabs.f32(float)
declare float @llvm.rint.f32(float)
diff --git a/llvm/test/CodeGen/SPIRV/instructions/ptrcmp.ll b/llvm/test/CodeGen/SPIRV/instructions/ptrcmp.ll
index 4a9501b213cd4..641e2bf0649ce 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/ptrcmp.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/ptrcmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[EQ:%.*]] "test_eq"
; CHECK-DAG: OpName [[NE:%.*]] "test_ne"
diff --git a/llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll b/llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll
index 2c5d528df0fc4..e22e02f76d01d 100644
--- a/llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll
+++ b/llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[SHFv4:%.+]] "shuffle_v4"
; CHECK-DAG: OpName [[INSv4:%.+]] "insert_v4"
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