[llvm] 0d6d05b - [AArch64] Add alias predicate-as-counter register for PFALSE

[via llvm-commits]

Author: Caroline.Concatto at arm.com
Date: 2022-12-19T15:50:24Z
New Revision: 0d6d05bb7628c0a13c3a2d83b3f1a3690f63c7f0

URL: https://github.com/llvm/llvm-project/commit/0d6d05bb7628c0a13c3a2d83b3f1a3690f63c7f0
DIFF: https://github.com/llvm/llvm-project/commit/0d6d05bb7628c0a13c3a2d83b3f1a3690f63c7f0.diff

LOG: [AArch64] Add alias predicate-as-counter register for PFALSE

According to:
https://developer.arm.com/documentation/ddi0602/2022-09/
PFALSE should:
"...an assembler must also accept predicate-as-counter register
name for the destination predicate register."

Differential Revision: https://reviews.llvm.org/D140301

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/SVEInstrFormats.td
    llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
    llvm/test/MC/AArch64/SVE/pfalse.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index afad1b82414ed..e9d09aa664b2e 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -659,6 +659,8 @@ class sve_int_pfalse<bits<6> opc, string asm>
 multiclass sve_int_pfalse<bits<6> opc, string asm> {
   def NAME : sve_int_pfalse<opc, asm>;
 
+  def : InstAlias<"pfalse\t$Pd", (!cast<Instruction>(NAME) PNR8:$Pd), 0>;
+
   def : Pat<(nxv16i1 immAllZerosV), (!cast<Instruction>(NAME))>;
   def : Pat<(nxv8i1 immAllZerosV), (!cast<Instruction>(NAME))>;
   def : Pat<(nxv4i1 immAllZerosV), (!cast<Instruction>(NAME))>;

diff  --git a/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s b/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
index 1a4047d8d80b7..4f2c22c4a8889 100644
--- a/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
@@ -8,3 +8,10 @@ pfalse p15.h
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
 // CHECK-NEXT: pfalse p15.h
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Support until pn15.b
+
+pfalse pn16.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: pfalse pn16.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff  --git a/llvm/test/MC/AArch64/SVE/pfalse.s b/llvm/test/MC/AArch64/SVE/pfalse.s
index 4124da8ac92a0..7ac4d5c44f433 100644
--- a/llvm/test/MC/AArch64/SVE/pfalse.s
+++ b/llvm/test/MC/AArch64/SVE/pfalse.s
@@ -14,3 +14,9 @@ pfalse p15.b
 // CHECK-ENCODING: [0x0f,0xe4,0x18,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: 2518e40f <unknown>
+
+pfalse pn15.b
+// CHECK-INST: pfalse  p15.b
+// CHECK-ENCODING: [0x0f,0xe4,0x18,0x25]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: 2518e40f <unknown>