[PATCH] D140301: [AArch64] Add alias predicate-as-counter register for PFALSE

[Caroline via Phabricator via llvm-commits]

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According to:
https://developer.arm.com/documentation/ddi0602/2022-09/
PFALSE should:
"...an assembler must also accept predicate-as-counter register
name for the destination predicate register."


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140301

Files:
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
  llvm/test/MC/AArch64/SVE/pfalse.s


Index: llvm/test/MC/AArch64/SVE/pfalse.s
===================================================================
--- llvm/test/MC/AArch64/SVE/pfalse.s
+++ llvm/test/MC/AArch64/SVE/pfalse.s
@@ -14,3 +14,9 @@
 // CHECK-ENCODING: [0x0f,0xe4,0x18,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: 2518e40f <unknown>
+
+pfalse pn15.b
+// CHECK-INST: pfalse  p15.b
+// CHECK-ENCODING: [0x0f,0xe4,0x18,0x25]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: 2518e40f <unknown>
Index: llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
+++ llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
@@ -8,3 +8,10 @@
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
 // CHECK-NEXT: pfalse p15.h
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Support until pn15.b
+
+pfalse pn16.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: pfalse pn16.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Index: llvm/lib/Target/AArch64/SVEInstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -659,6 +659,8 @@
 multiclass sve_int_pfalse<bits<6> opc, string asm> {
   def NAME : sve_int_pfalse<opc, asm>;
 
+  def : InstAlias<"pfalse\t$Pd", (!cast<Instruction>(NAME) PNR8:$Pd), 0>;
+
   def : Pat<(nxv16i1 immAllZerosV), (!cast<Instruction>(NAME))>;
   def : Pat<(nxv8i1 immAllZerosV), (!cast<Instruction>(NAME))>;
   def : Pat<(nxv4i1 immAllZerosV), (!cast<Instruction>(NAME))>;


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