[PATCH] D140299: [AMDGPU][GFX11] Correct tied src2 of v_fmac_f16_e64

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

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`src2` was incorrectly defined as `VSrc_f16` but it is tied to dst which is `VGPR_32`. As a result, disassembler failed to decode `src2`. See this bug <https://github.com/llvm/llvm-project/issues/59467> for more information.

This change affects codegen because `v_fmac_f16_e64` are now replaced by `v_fma_f16` when `src2` is not a `VGPR`. See https://github.com/llvm/llvm-project/blob/b5c809acd34c26666489679300eb0b8a8b824aeb/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp#L337


https://reviews.llvm.org/D140299

Files:
  llvm/lib/Target/AMDGPU/VOP2Instructions.td
  llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
  llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt


Index: llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt
===================================================================
--- llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt
+++ llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt
@@ -471,6 +471,12 @@
 # GFX11: v_fmac_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x36,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
 0xff,0x83,0x36,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00
 
+# GFX11: v_fmac_f16_e64 v250, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xfa,0x83,0x36,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+0xfa,0x83,0x36,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00
+
+# GFX11: v_fmac_f16_e64 v255, v1, v2             ; encoding: [0xff,0x00,0x36,0xd5,0x01,0x05,0x02,0x00]
+0xff,0x00,0x36,0xd5,0x01,0x05,0x02,0x00
+
 # GFX11: v_fmac_f32_e64 v5, v1, v2               ; encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x00]
 0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x00
 
Index: llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
+++ llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
@@ -156,7 +156,7 @@
 ; VI-DENORM-DAG:    v_fma_f16 [[MAD:v[0-9]+]], [[X]], 2.0, v{{[0-9]+}}
 ; GFX10-FLUSH-DAG:  v_add_f16_e32 [[MAD:v[0-9]+]], s{{[0-9]+}}, [[MUL2]]
 ; GFX10-DENORM-DAG: v_fma_f16 [[MAD:v[0-9]+]], [[X]], 2.0, s{{[0-9]+}}
-; GFX11-DENORM-DAG: v_fmac_f16_e64 [[MAD:v[0-9]+]], [[X]], 2.0
+; GFX11-DENORM-DAG: v_fma_f16 [[MAD:v[0-9]+]], [[X]], 2.0, s{{[0-9]+}}
 
 ; GCN-DAG: buffer_store_{{short|b16}} [[MUL2]]
 ; GCN-DAG: buffer_store_{{short|b16}} [[MAD]]
Index: llvm/lib/Target/AMDGPU/VOP2Instructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -495,6 +495,8 @@
                      Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
                      getVregSrcForVT_t16<Src2VT>.ret:$src2, // stub argument
                      dpp8:$dpp8, FI:$fi);
+  let Src2Mod = FP32InputMods; // dummy unused modifiers
+  let Src2RC64 = VGPRSrc_32;   // stub argument
 }
 def VOP_MAC_F32 : VOP_MAC <f32>;
 let HasExtDPP = 0, HasExt32BitDPP = 0 in


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