[llvm] 376ab5f - [MIR] Convert some tests to opaque pointers (NFC)

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2022-12-19T12:54:50+01:00
New Revision: 376ab5f413ae9dd2d749a934a087e98e69da600e

URL: https://github.com/llvm/llvm-project/commit/376ab5f413ae9dd2d749a934a087e98e69da600e
DIFF: https://github.com/llvm/llvm-project/commit/376ab5f413ae9dd2d749a934a087e98e69da600e.diff

LOG: [MIR] Convert some tests to opaque pointers (NFC)

Added: 
    

Modified: 
    llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
    llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
    llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll
    llvm/test/CodeGen/MIR/X86/unreachable_block.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
index 58399c3cfe031..3e652170c9707 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
@@ -39,7 +39,7 @@
 ; AFTER-PEI-NEXT: vgprForAGPRCopy: ''
 ; AFTER-PEI-NEXT: sgprForEXECCopy: ''
 ; AFTER-PEI-NEXT: body:
-define amdgpu_kernel void @scavenge_fi(i32 addrspace(1)* %out, i32 %in) #0 {
+define amdgpu_kernel void @scavenge_fi(ptr addrspace(1) %out, i32 %in) #0 {
   %wide.sgpr0 = call <32 x i32>  asm sideeffect "; def $0", "=s" () #0
   %wide.sgpr1 = call <32 x i32>  asm sideeffect "; def $0", "=s" () #0
   %wide.sgpr2 = call <32 x i32>  asm sideeffect "; def $0", "=s" () #0

diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
index c84ecf5989a93..3dc9b8b70db5e 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
@@ -43,8 +43,8 @@
 ; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101'
 ; CHECK-NEXT: body:
 define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
-  %gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0
-  store float 0.0, float addrspace(3)* %gep, align 4
+  %gep = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %arg0
+  store float 0.0, ptr addrspace(3) %gep, align 4
   ret void
 }
 
@@ -84,8 +84,8 @@ define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
 ; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101'
 ; CHECK-NEXT: body:
 define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {
-  %gep = getelementptr inbounds [128 x i32], [128 x i32] addrspace(2)* @gds, i32 0, i32 %arg0
-  atomicrmw add i32 addrspace(2)* %gep, i32 8 seq_cst
+  %gep = getelementptr inbounds [128 x i32], ptr addrspace(2) @gds, i32 0, i32 %arg0
+  atomicrmw add ptr addrspace(2) %gep, i32 8 seq_cst
   ret void
 }
 
@@ -236,13 +236,13 @@ define amdgpu_ps void @high_address_bits() #4 {
 ; CHECK: wwmReservedRegs:
 ; CHECK-NEXT: - '$vgpr2'
 ; CHECK-NEXT: - '$vgpr3'
-define amdgpu_cs void @wwm_reserved_regs(i32 addrspace(1)* %ptr, <4 x i32> inreg %tmp14) {
-  %ld0 = load volatile i32, i32 addrspace(1)* %ptr
-  %ld1 = load volatile i32, i32 addrspace(1)* %ptr
+define amdgpu_cs void @wwm_reserved_regs(ptr addrspace(1) %ptr, <4 x i32> inreg %tmp14) {
+  %ld0 = load volatile i32, ptr addrspace(1) %ptr
+  %ld1 = load volatile i32, ptr addrspace(1) %ptr
   %inactive0 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %ld1, i32 0)
   %inactive1 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %ld0, i32 0)
-  store volatile i32 %inactive0, i32 addrspace(1)* %ptr
-  store volatile i32 %inactive1, i32 addrspace(1)* %ptr
+  store volatile i32 %inactive0, ptr addrspace(1) %ptr
+  store volatile i32 %inactive1, ptr addrspace(1) %ptr
   ret void
 }
 

diff  --git a/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll b/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll
index 9af0dc3367378..f2632d8dc05ac 100644
--- a/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll
+++ b/llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll
@@ -9,7 +9,7 @@
 ; Check that setRegClassOrRegBank.mir has same output.
 
 declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
-define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) {
+define void @add_v4i32_builtin_imm(ptr %a, ptr %c) {
   ; P5600-LABEL: name: add_v4i32_builtin_imm
   ; P5600: bb.1.entry:
   ; P5600:   liveins: $a0, $a1
@@ -20,8 +20,8 @@ define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) {
   ; P5600:   G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
   ; P5600:   RetRA
 entry:
-  %0 = load <4 x i32>, <4 x i32>* %a, align 16
+  %0 = load <4 x i32>, ptr %a, align 16
   %1 = tail call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %0, i32 25)
-  store <4 x i32> %1, <4 x i32>* %c, align 16
+  store <4 x i32> %1, ptr %c, align 16
   ret void
 }

diff  --git a/llvm/test/CodeGen/MIR/X86/unreachable_block.ll b/llvm/test/CodeGen/MIR/X86/unreachable_block.ll
index 4cea0392255c6..396fef0db95bf 100644
--- a/llvm/test/CodeGen/MIR/X86/unreachable_block.ll
+++ b/llvm/test/CodeGen/MIR/X86/unreachable_block.ll
@@ -34,15 +34,15 @@
 ; CHECK-NEXT: successors:
 ; CHECK-NOT: %bb.{{[0-9]+}}.split.true
 ; CHECK-LABEL: bb.{{[0-9]+}}.split.true:
-define void @foo(i32* %bar) {
+define void @foo(ptr %bar) {
   br i1 undef, label %true, label %false
 true:
-  %v = load i32, i32* %bar
+  %v = load i32, ptr %bar
   br label %split.true
 false:
   unreachable
 split.true:
   %vInc = add i32 %v, 1
-  store i32 %vInc, i32* %bar
+  store i32 %vInc, ptr %bar
   ret void
 }