[llvm] bed1c7f - [ARM] Convert some tests to opaque pointers (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 19 03:46:04 PST 2022
Author: Nikita Popov
Date: 2022-12-19T12:45:35+01:00
New Revision: bed1c7f061aa12417aa081e334afdba45767b938
URL: https://github.com/llvm/llvm-project/commit/bed1c7f061aa12417aa081e334afdba45767b938
DIFF: https://github.com/llvm/llvm-project/commit/bed1c7f061aa12417aa081e334afdba45767b938.diff
LOG: [ARM] Convert some tests to opaque pointers (NFC)
Added:
Modified:
llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll
llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll
llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll
llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll
llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll
llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll
llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll
llvm/test/CodeGen/ARM/2007-04-03-PEIBug.ll
llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll
llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll
llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll
llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll
llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll
llvm/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll
llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll
llvm/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll
llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll
llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll
llvm/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll
llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll
llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll
llvm/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll
llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll
llvm/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll
llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll
llvm/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll
llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll
llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll
llvm/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll
llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll
llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll
llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll
llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll
llvm/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll
llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll
llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll
llvm/test/CodeGen/ARM/2009-04-08-FREM.ll
llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll
llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll
llvm/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll
llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll
llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll
llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll
llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll
llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll
llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll
llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll
llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll
llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll
llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll
llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll
llvm/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll
llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll
llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll
llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll
llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll
llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
llvm/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll
llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll
llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll
llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
llvm/test/CodeGen/ARM/2009-09-09-AllOnes.ll
llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
llvm/test/CodeGen/ARM/2009-09-10-postdec.ll
llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll
llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll
llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll
llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll
llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll
llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll
llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll
llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll
llvm/test/CodeGen/ARM/2009-10-16-Scope.ll
llvm/test/CodeGen/ARM/2009-10-27-double-align.ll
llvm/test/CodeGen/ARM/2009-10-30.ll
llvm/test/CodeGen/ARM/2009-11-01-NeonMoves.ll
llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll
llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll
llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll
llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll
llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll
llvm/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll
llvm/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll
llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll
llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll
llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll
llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll
llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll
llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
llvm/test/CodeGen/ARM/2010-05-19-Shuffles.ll
llvm/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll
llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll
llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll
llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll
llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll
llvm/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll
llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
llvm/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll
llvm/test/CodeGen/ARM/2010-08-04-EHCrash.ll
llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll
llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll
llvm/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll
llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll
llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
llvm/test/CodeGen/ARM/2010-12-08-tpsoft.ll
llvm/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll
llvm/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll
llvm/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll
llvm/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll
llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll
llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll
llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
llvm/test/CodeGen/ARM/2011-04-07-schediv.ll
llvm/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll
llvm/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll
llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll
llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll
llvm/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll
llvm/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll
llvm/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll
llvm/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll
llvm/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll
llvm/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
llvm/test/CodeGen/ARM/2011-08-29-SchedCycle.ll
llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll
llvm/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll
llvm/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll
llvm/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll
llvm/test/CodeGen/ARM/2011-10-26-memset-inline.ll
llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll
llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll
llvm/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll
llvm/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll
llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
llvm/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll
llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll
llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll
llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll
llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll
llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll
llvm/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll
llvm/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll
llvm/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll
llvm/test/CodeGen/ARM/2012-04-10-DAGCombine.ll
llvm/test/CodeGen/ARM/2012-04-24-SplitEHCriticalEdge.ll
llvm/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll
llvm/test/CodeGen/ARM/2012-05-29-TailDupBug.ll
llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll
llvm/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll
llvm/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll
llvm/test/CodeGen/ARM/2012-08-09-neon-extload.ll
llvm/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
llvm/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll
llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll
llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll
llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
llvm/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll
llvm/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
llvm/test/CodeGen/ARM/2013-01-21-PR14992.ll
llvm/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
llvm/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll
llvm/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll
llvm/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll
llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll
llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll
llvm/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
llvm/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll
llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll
llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll
llvm/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll
llvm/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll
llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
llvm/test/CodeGen/ARM/2013-10-11-select-stalls.ll
llvm/test/CodeGen/ARM/2013-11-08-inline-asm-neon-array.ll
llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll
llvm/test/CodeGen/ARM/2014-05-14-DwarfEHCrash.ll
llvm/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll
llvm/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll
llvm/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll
llvm/test/CodeGen/ARM/2016-08-24-ARM-LDST-dbginfo-bug.ll
llvm/test/CodeGen/ARM/2018-02-13-PR36079.ll
llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-pic.ll
llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-ropi-rwpi.ll
llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-static.ll
llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll
llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll
llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-pic.ll
llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-ropi-rwpi.ll
llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-static.ll
llvm/test/CodeGen/ARM/MergeConsecutiveStores.ll
llvm/test/CodeGen/ARM/PR15053.ll
llvm/test/CodeGen/ARM/PR35379.ll
llvm/test/CodeGen/ARM/ParallelDSP/complex_dot_prod.ll
llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
llvm/test/CodeGen/ARM/ParallelDSP/pr42729.ll
llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll
llvm/test/CodeGen/ARM/ParallelDSP/smlad1.ll
llvm/test/CodeGen/ARM/ParallelDSP/smlad10.ll
llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll
llvm/test/CodeGen/ARM/ParallelDSP/smlad12.ll
llvm/test/CodeGen/ARM/ParallelDSP/smlad2.ll
llvm/test/CodeGen/ARM/ParallelDSP/smlad3.ll
llvm/test/CodeGen/ARM/ParallelDSP/smlad4.ll
llvm/test/CodeGen/ARM/ParallelDSP/smlad5.ll
llvm/test/CodeGen/ARM/ParallelDSP/smlad8.ll
llvm/test/CodeGen/ARM/ParallelDSP/smlad9.ll
llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll
llvm/test/CodeGen/ARM/ParallelDSP/smlald1.ll
llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll
llvm/test/CodeGen/ARM/ParallelDSP/squaring.ll
llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
llvm/test/CodeGen/ARM/SoftFloatVectorExtract.ll
llvm/test/CodeGen/ARM/Windows/aapcs.ll
llvm/test/CodeGen/ARM/Windows/alloca-no-stack-arg-probe.ll
llvm/test/CodeGen/ARM/Windows/alloca.ll
llvm/test/CodeGen/ARM/Windows/builtin_longjmp.ll
llvm/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll
llvm/test/CodeGen/ARM/Windows/dbzchk.ll
llvm/test/CodeGen/ARM/Windows/dllexport.ll
llvm/test/CodeGen/ARM/Windows/dllimport.ll
llvm/test/CodeGen/ARM/Windows/frame-register.ll
llvm/test/CodeGen/ARM/Windows/global-minsize.ll
llvm/test/CodeGen/ARM/Windows/if-cvt-bundle.ll
llvm/test/CodeGen/ARM/Windows/memset.ll
llvm/test/CodeGen/ARM/Windows/mingw-refptr.ll
llvm/test/CodeGen/ARM/Windows/mov32t-bundling.ll
llvm/test/CodeGen/ARM/Windows/movw-movt-relocations.ll
llvm/test/CodeGen/ARM/Windows/no-aeabi.ll
llvm/test/CodeGen/ARM/Windows/no-frame-register.ll
llvm/test/CodeGen/ARM/Windows/pic.ll
llvm/test/CodeGen/ARM/Windows/read-only-data.ll
llvm/test/CodeGen/ARM/Windows/stack-probe-non-default.ll
llvm/test/CodeGen/ARM/Windows/stack-protector-msvc.ll
llvm/test/CodeGen/ARM/Windows/stack-protector-musttail.ll
llvm/test/CodeGen/ARM/Windows/structors.ll
llvm/test/CodeGen/ARM/Windows/tls.ll
llvm/test/CodeGen/ARM/Windows/vla-cpsr.ll
llvm/test/CodeGen/ARM/Windows/vla.ll
llvm/test/CodeGen/ARM/a15-SD-dep.ll
llvm/test/CodeGen/ARM/a15-partial-update.ll
llvm/test/CodeGen/ARM/add-like-or.ll
llvm/test/CodeGen/ARM/addrmode.ll
llvm/test/CodeGen/ARM/addrspacecast.ll
llvm/test/CodeGen/ARM/addsubo-legalization.ll
llvm/test/CodeGen/ARM/aeabi-read-tp.ll
llvm/test/CodeGen/ARM/alias_align.ll
llvm/test/CodeGen/ARM/alias_store.ll
llvm/test/CodeGen/ARM/aliases.ll
llvm/test/CodeGen/ARM/align-sp-adjustment.ll
llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll
llvm/test/CodeGen/ARM/alloca-align.ll
llvm/test/CodeGen/ARM/alloca.ll
llvm/test/CodeGen/ARM/and-cmpz.ll
llvm/test/CodeGen/ARM/and-load-combine.ll
llvm/test/CodeGen/ARM/and-sext-combine.ll
llvm/test/CodeGen/ARM/apcs-vfp.ll
llvm/test/CodeGen/ARM/arg-copy-elide.ll
llvm/test/CodeGen/ARM/argaddr.ll
llvm/test/CodeGen/ARM/arm-abi-attr.ll
llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
llvm/test/CodeGen/ARM/arm-asm.ll
llvm/test/CodeGen/ARM/arm-bf16-pcs.ll
llvm/test/CodeGen/ARM/arm-eabi.ll
llvm/test/CodeGen/ARM/arm-frame-lowering-no-terminator.ll
llvm/test/CodeGen/ARM/arm-frameaddr.ll
llvm/test/CodeGen/ARM/arm-insert-subvector.ll
llvm/test/CodeGen/ARM/arm-modifier.ll
llvm/test/CodeGen/ARM/arm-negative-stride.ll
llvm/test/CodeGen/ARM/arm-position-independence.ll
llvm/test/CodeGen/ARM/arm-post-indexing-opt.ll
llvm/test/CodeGen/ARM/arm-returnaddr.ll
llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
llvm/test/CodeGen/ARM/arm-storebytesmerge.ll
llvm/test/CodeGen/ARM/arm-ttype-target2.ll
llvm/test/CodeGen/ARM/arm-vld1.ll
llvm/test/CodeGen/ARM/arm-vlddup-update.ll
llvm/test/CodeGen/ARM/arm-vlddup.ll
llvm/test/CodeGen/ARM/arm-vst1.ll
llvm/test/CodeGen/ARM/armv4.ll
llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
llvm/test/CodeGen/ARM/atomic-64bit.ll
llvm/test/CodeGen/ARM/atomic-cmp.ll
llvm/test/CodeGen/ARM/atomic-cmpxchg.ll
llvm/test/CodeGen/ARM/atomic-load-store.ll
llvm/test/CodeGen/ARM/atomic-op.ll
llvm/test/CodeGen/ARM/atomic-ops-m33.ll
llvm/test/CodeGen/ARM/atomic-ops-v8.ll
llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
llvm/test/CodeGen/ARM/atomicrmw_minmax.ll
llvm/test/CodeGen/ARM/available_externally.ll
llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll
llvm/test/CodeGen/ARM/bf16-intrinsics-ld-st.ll
llvm/test/CodeGen/ARM/bf16-shuffle.ll
llvm/test/CodeGen/ARM/bfi-chain-cse-crash.ll
llvm/test/CodeGen/ARM/bfi.ll
llvm/test/CodeGen/ARM/bfloat.ll
llvm/test/CodeGen/ARM/bfx.ll
llvm/test/CodeGen/ARM/big-endian-eh-unwind.ll
llvm/test/CodeGen/ARM/big-endian-neon-bitconv.ll
llvm/test/CodeGen/ARM/big-endian-neon-extend.ll
llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll
llvm/test/CodeGen/ARM/big-endian-neon-trunc-store.ll
llvm/test/CodeGen/ARM/big-endian-ret-f64.ll
llvm/test/CodeGen/ARM/big-endian-vector-caller.ll
llvm/test/CodeGen/ARM/bit-reverse-to-rbit.ll
llvm/test/CodeGen/ARM/branch-on-zero.ll
llvm/test/CodeGen/ARM/bswap16.ll
llvm/test/CodeGen/ARM/bx_fold.ll
llvm/test/CodeGen/ARM/byval-align.ll
llvm/test/CodeGen/ARM/byval_load_align.ll
llvm/test/CodeGen/ARM/cache-intrinsic.ll
llvm/test/CodeGen/ARM/call-tc.ll
llvm/test/CodeGen/ARM/call.ll
llvm/test/CodeGen/ARM/call_nolink.ll
llvm/test/CodeGen/ARM/cfguard-checks.ll
llvm/test/CodeGen/ARM/cfguard-module-flag.ll
llvm/test/CodeGen/ARM/cfi-alignment.ll
llvm/test/CodeGen/ARM/clang-section.ll
llvm/test/CodeGen/ARM/cmp-bool.ll
llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll
llvm/test/CodeGen/ARM/cmpxchg-O0.ll
llvm/test/CodeGen/ARM/cmpxchg-idioms.ll
llvm/test/CodeGen/ARM/cmpxchg-weak.ll
llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
llvm/test/CodeGen/ARM/cmse-clear-float-hard2.ll
llvm/test/CodeGen/ARM/cmse-clear-float-mve.ll
llvm/test/CodeGen/ARM/cmse-clear-float.ll
llvm/test/CodeGen/ARM/cmse-clear.ll
llvm/test/CodeGen/ARM/cmse-clrm-it-block.ll
llvm/test/CodeGen/ARM/cmse-cve-2021-35465-return.ll
llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll
llvm/test/CodeGen/ARM/cmse-errors.ll
llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.ll
llvm/test/CodeGen/ARM/cmse.ll
llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll
llvm/test/CodeGen/ARM/coalesce-subregs.ll
llvm/test/CodeGen/ARM/coff-no-dead-strip.ll
llvm/test/CodeGen/ARM/combine-vmovdrr.ll
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llvm/test/CodeGen/ARM/vector-extend-narrow.ll
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llvm/test/CodeGen/ARM/vector-store.ll
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llvm/test/CodeGen/ARM/vhadd.ll
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llvm/test/CodeGen/ARM/vld-vst-upgrade.ll
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llvm/test/CodeGen/ARM/vld3.ll
llvm/test/CodeGen/ARM/vld4.ll
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llvm/test/CodeGen/ARM/vldlane.ll
llvm/test/CodeGen/ARM/vldm-liveness.ll
llvm/test/CodeGen/ARM/vldm-sched-a9.ll
llvm/test/CodeGen/ARM/vminmax.ll
llvm/test/CodeGen/ARM/vminmaxnm-safe.ll
llvm/test/CodeGen/ARM/vmov.ll
llvm/test/CodeGen/ARM/vmul.ll
llvm/test/CodeGen/ARM/vneg.ll
llvm/test/CodeGen/ARM/vpadal.ll
llvm/test/CodeGen/ARM/vpadd.ll
llvm/test/CodeGen/ARM/vpminmax.ll
llvm/test/CodeGen/ARM/vqadd.ll
llvm/test/CodeGen/ARM/vqdmul.ll
llvm/test/CodeGen/ARM/vqshl.ll
llvm/test/CodeGen/ARM/vqshrn.ll
llvm/test/CodeGen/ARM/vqsub.ll
llvm/test/CodeGen/ARM/vrec.ll
llvm/test/CodeGen/ARM/vrev.ll
llvm/test/CodeGen/ARM/vrint.ll
llvm/test/CodeGen/ARM/vsel-fp16.ll
llvm/test/CodeGen/ARM/vsel.ll
llvm/test/CodeGen/ARM/vselect_imax.ll
llvm/test/CodeGen/ARM/vshift.ll
llvm/test/CodeGen/ARM/vshiftins.ll
llvm/test/CodeGen/ARM/vshl.ll
llvm/test/CodeGen/ARM/vshll.ll
llvm/test/CodeGen/ARM/vshrn.ll
llvm/test/CodeGen/ARM/vsra.ll
llvm/test/CodeGen/ARM/vst1.ll
llvm/test/CodeGen/ARM/vst2.ll
llvm/test/CodeGen/ARM/vst3.ll
llvm/test/CodeGen/ARM/vst4.ll
llvm/test/CodeGen/ARM/vstlane.ll
llvm/test/CodeGen/ARM/vtbl.ll
llvm/test/CodeGen/ARM/vtrn.ll
llvm/test/CodeGen/ARM/vuzp.ll
llvm/test/CodeGen/ARM/vzip.ll
llvm/test/CodeGen/ARM/weak2.ll
llvm/test/CodeGen/ARM/widen-vmovs.ll
llvm/test/CodeGen/ARM/win32-ssp.ll
llvm/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll
llvm/test/CodeGen/ARM/zext-logic-shift-load.ll
llvm/test/CodeGen/ARM/zextload_demandedbits.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll b/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll
index b719f9f4d2354..6dbce9ec068d1 100644
--- a/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll
+++ b/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null
-%struct.layer_data = type { i32, [2048 x i8], i8*, [16 x i8], i32, i8*, i32, i32, [64 x i32], [64 x i32], [64 x i32], [64 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [12 x [64 x i16]] }
- at ld = external global %struct.layer_data* ; <%struct.layer_data**> [#uses=1]
+%struct.layer_data = type { i32, [2048 x i8], ptr, [16 x i8], i32, ptr, i32, i32, [64 x i32], [64 x i32], [64 x i32], [64 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [12 x [64 x i16]] }
+ at ld = external global ptr ; <ptr> [#uses=1]
define void @main() {
entry:
@@ -11,10 +11,10 @@ bb169.i: ; preds = %entry
ret void
cond_true11: ; preds = %entry
- %tmp.i32 = load %struct.layer_data*, %struct.layer_data** @ld ; <%struct.layer_data*> [#uses=2]
- %tmp3.i35 = getelementptr %struct.layer_data, %struct.layer_data* %tmp.i32, i32 0, i32 1, i32 2048; <i8*> [#uses=2]
- %tmp.i36 = getelementptr %struct.layer_data, %struct.layer_data* %tmp.i32, i32 0, i32 2 ; <i8**> [#uses=1]
- store i8* %tmp3.i35, i8** %tmp.i36
- store i8* %tmp3.i35, i8** null
+ %tmp.i32 = load ptr, ptr @ld ; <ptr> [#uses=2]
+ %tmp3.i35 = getelementptr %struct.layer_data, ptr %tmp.i32, i32 0, i32 1, i32 2048; <ptr> [#uses=2]
+ %tmp.i36 = getelementptr %struct.layer_data, ptr %tmp.i32, i32 0, i32 2 ; <ptr> [#uses=1]
+ store ptr %tmp3.i35, ptr %tmp.i36
+ store ptr %tmp3.i35, ptr null
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
index a35ded5b54576..c41921b589eba 100644
--- a/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
+++ b/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
@@ -4,30 +4,30 @@
; The execution domain checking code would translate vmovs to vorr whether or not
; we had NEON instructions. Verify we don't if we're not compiled with NEON.
; DOMAIN-NOT: vorr
- at quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
- at dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
- at A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1]
+ at quant_coef = external global [6 x [4 x [4 x i32]]] ; <ptr> [#uses=1]
+ at dequant_coef = external global [6 x [4 x [4 x i32]]] ; <ptr> [#uses=1]
+ at A = external global [4 x [4 x i32]] ; <ptr> [#uses=1]
; CHECK-LABEL: dct_luma_sp:
-define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) "frame-pointer"="all" {
+define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, ptr %coeff_cost) "frame-pointer"="all" {
entry:
; Make sure to use base-updating stores for saving callee-saved registers.
; CHECK: push
; CHECK-NOT: sub sp
; CHECK: push
- %predicted_block = alloca [4 x [4 x i32]], align 4 ; <[4 x [4 x i32]]*> [#uses=1]
+ %predicted_block = alloca [4 x [4 x i32]], align 4 ; <ptr> [#uses=1]
br label %cond_next489
cond_next489: ; preds = %cond_false, %bb471
- %j.7.in = load i8, i8* null ; <i8> [#uses=1]
- %i.8.in = load i8, i8* null ; <i8> [#uses=1]
+ %j.7.in = load i8, ptr null ; <i8> [#uses=1]
+ %i.8.in = load i8, ptr null ; <i8> [#uses=1]
%i.8 = zext i8 %i.8.in to i32 ; <i32> [#uses=4]
%j.7 = zext i8 %j.7.in to i32 ; <i32> [#uses=4]
- %tmp495 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* %predicted_block, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=2]
- %tmp496 = load i32, i32* %tmp495 ; <i32> [#uses=2]
- %tmp502 = load i32, i32* null ; <i32> [#uses=1]
- %tmp542 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1]
- %tmp543 = load i32, i32* %tmp542 ; <i32> [#uses=1]
+ %tmp495 = getelementptr [4 x [4 x i32]], ptr %predicted_block, i32 0, i32 %i.8, i32 %j.7 ; <ptr> [#uses=2]
+ %tmp496 = load i32, ptr %tmp495 ; <i32> [#uses=2]
+ %tmp502 = load i32, ptr null ; <i32> [#uses=1]
+ %tmp542 = getelementptr [6 x [4 x [4 x i32]]], ptr @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <ptr> [#uses=1]
+ %tmp543 = load i32, ptr %tmp542 ; <i32> [#uses=1]
%tmp548 = ashr i32 0, 0 ; <i32> [#uses=3]
%tmp561 = sub i32 0, %tmp496 ; <i32> [#uses=3]
%abscond563 = icmp sgt i32 %tmp561, -1 ; <i1> [#uses=1]
@@ -39,10 +39,10 @@ cond_next489: ; preds = %cond_false, %bb471
br i1 %tmp579, label %bb712, label %cond_next589
cond_next589: ; preds = %cond_next489
- %tmp605 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @dequant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1]
- %tmp606 = load i32, i32* %tmp605 ; <i32> [#uses=1]
- %tmp612 = load i32, i32* null ; <i32> [#uses=1]
- %tmp629 = load i32, i32* null ; <i32> [#uses=1]
+ %tmp605 = getelementptr [6 x [4 x [4 x i32]]], ptr @dequant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <ptr> [#uses=1]
+ %tmp606 = load i32, ptr %tmp605 ; <i32> [#uses=1]
+ %tmp612 = load i32, ptr null ; <i32> [#uses=1]
+ %tmp629 = load i32, ptr null ; <i32> [#uses=1]
%tmp629a = sitofp i32 %tmp629 to double ; <double> [#uses=1]
%tmp631 = fmul double %tmp629a, 0.000000e+00 ; <double> [#uses=1]
%tmp632 = fadd double 0.000000e+00, %tmp631 ; <double> [#uses=1]
@@ -54,7 +54,7 @@ cond_next589: ; preds = %cond_next489
%tmp660 = sub i32 0, %tmp659 ; <i32> [#uses=1]
%tmp666 = sub i32 %tmp660, %tmp496 ; <i32> [#uses=1]
%tmp667 = sitofp i32 %tmp666 to double ; <double> [#uses=2]
- call void @levrun_linfo_inter( i32 %tmp576, i32 0, i32* null, i32* null )
+ call void @levrun_linfo_inter( i32 %tmp576, i32 0, ptr null, ptr null )
%tmp671 = fmul double %tmp667, %tmp667 ; <double> [#uses=1]
%tmp675 = fadd double %tmp671, 0.000000e+00 ; <double> [#uses=1]
%tmp678 = fcmp oeq double %tmp632, %tmp675 ; <i1> [#uses=1]
@@ -89,9 +89,9 @@ bb737: ; preds = %cond_false689
cond_true740: ; preds = %bb737
%tmp761 = call fastcc i32 @sign( i32 %tmp576, i32 0 ) ; <i32> [#uses=1]
- %tmp780 = load i32, i32* null ; <i32> [#uses=1]
- %tmp785 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* @A, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1]
- %tmp786 = load i32, i32* %tmp785 ; <i32> [#uses=1]
+ %tmp780 = load i32, ptr null ; <i32> [#uses=1]
+ %tmp785 = getelementptr [4 x [4 x i32]], ptr @A, i32 0, i32 %i.8, i32 %j.7 ; <ptr> [#uses=1]
+ %tmp786 = load i32, ptr %tmp785 ; <i32> [#uses=1]
%tmp781 = mul i32 %tmp780, %tmp761 ; <i32> [#uses=1]
%tmp787 = mul i32 %tmp781, %tmp786 ; <i32> [#uses=1]
%tmp789 = shl i32 %tmp787, 0 ; <i32> [#uses=1]
@@ -100,7 +100,7 @@ cond_true740: ; preds = %bb737
cond_next791: ; preds = %cond_true740, %bb737
%ilev.1 = phi i32 [ %tmp790, %cond_true740 ], [ 0, %bb737 ] ; <i32> [#uses=1]
- %tmp796 = load i32, i32* %tmp495 ; <i32> [#uses=1]
+ %tmp796 = load i32, ptr %tmp495 ; <i32> [#uses=1]
%tmp798 = add i32 %tmp796, %ilev.1 ; <i32> [#uses=1]
%tmp812 = mul i32 0, %tmp502 ; <i32> [#uses=0]
%tmp818 = call fastcc i32 @sign( i32 0, i32 %tmp798 ) ; <i32> [#uses=0]
@@ -109,4 +109,4 @@ cond_next791: ; preds = %cond_true740, %bb737
declare i32 @sign(i32, i32)
-declare void @levrun_linfo_inter(i32, i32, i32*, i32*)
+declare void @levrun_linfo_inter(i32, i32, ptr, ptr)
diff --git a/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll b/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll
index 472a345a0d71c..c549553fd399a 100644
--- a/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll
+++ b/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll
@@ -1,13 +1,13 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2
-define fastcc i8* @read_sleb128(i8* %p, i32* %val) {
+define fastcc ptr @read_sleb128(ptr %p, ptr %val) {
br label %bb
bb: ; preds = %bb, %0
- %p_addr.0 = getelementptr i8, i8* %p, i32 0 ; <i8*> [#uses=1]
- %tmp2 = load i8, i8* %p_addr.0 ; <i8> [#uses=2]
+ %p_addr.0 = getelementptr i8, ptr %p, i32 0 ; <ptr> [#uses=1]
+ %tmp2 = load i8, ptr %p_addr.0 ; <i8> [#uses=2]
%tmp4.rec = add i32 0, 1 ; <i32> [#uses=1]
- %tmp4 = getelementptr i8, i8* %p, i32 %tmp4.rec ; <i8*> [#uses=1]
+ %tmp4 = getelementptr i8, ptr %p, i32 %tmp4.rec ; <ptr> [#uses=1]
%tmp56 = zext i8 %tmp2 to i32 ; <i32> [#uses=1]
%tmp7 = and i32 %tmp56, 127 ; <i32> [#uses=1]
%tmp9 = shl i32 %tmp7, 0 ; <i32> [#uses=1]
@@ -16,6 +16,6 @@ bb: ; preds = %bb, %0
br i1 %1, label %bb, label %cond_next28
cond_next28: ; preds = %bb
- store i32 %tmp11, i32* %val
- ret i8* %tmp4
+ store i32 %tmp11, ptr %val
+ ret ptr %tmp4
}
diff --git a/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll b/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll
index a379f63ab8bf5..58158b1b678a7 100644
--- a/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll
+++ b/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll
@@ -2,49 +2,49 @@
; RUN: llc -mtriple arm-apple-darwin -relocation-model pic -mattr=+v6 -filetype asm -o - %s | FileCheck -check-prefix CHECK-R9 %s
; RUN: llc -mtriple arm-apple-darwin -relocation-model pic -mattr=+v6,+reserve-r9 -ifcvt-limit=0 -stats -o /dev/null %s 2>&1 | FileCheck -check-prefix CHECK-ASM-PRINTER %s
-define void @test(i32 %tmp56222, i32 %tmp36224, i32 %tmp46223, i32 %i.0196.0.ph, i32 %tmp8, i32* %tmp1011, i32** %tmp1, i32* %d2.1.out, i32* %d3.1.out, i32* %d0.1.out, i32* %d1.1.out) {
+define void @test(i32 %tmp56222, i32 %tmp36224, i32 %tmp46223, i32 %i.0196.0.ph, i32 %tmp8, ptr %tmp1011, ptr %tmp1, ptr %d2.1.out, ptr %d3.1.out, ptr %d0.1.out, ptr %d1.1.out) {
newFuncRoot:
br label %bb74
bb78.exitStub:
- store i32 %d2.1, i32* %d2.1.out
- store i32 %d3.1, i32* %d3.1.out
- store i32 %d0.1, i32* %d0.1.out
- store i32 %d1.1, i32* %d1.1.out
+ store i32 %d2.1, ptr %d2.1.out
+ store i32 %d3.1, ptr %d3.1.out
+ store i32 %d0.1, ptr %d0.1.out
+ store i32 %d1.1, ptr %d1.1.out
ret void
bb74:
%fp.1.rec = phi i32 [ 0, %newFuncRoot ], [ %tmp71.rec, %bb26 ]
- %fm.1.in = phi i32* [ %tmp71, %bb26 ], [ %tmp1011, %newFuncRoot ]
+ %fm.1.in = phi ptr [ %tmp71, %bb26 ], [ %tmp1011, %newFuncRoot ]
%d0.1 = phi i32 [ %tmp44, %bb26 ], [ 8192, %newFuncRoot ]
%d1.1 = phi i32 [ %tmp54, %bb26 ], [ 8192, %newFuncRoot ]
%d2.1 = phi i32 [ %tmp64, %bb26 ], [ 8192, %newFuncRoot ]
%d3.1 = phi i32 [ %tmp69, %bb26 ], [ 8192, %newFuncRoot ]
- %fm.1 = load i32, i32* %fm.1.in
+ %fm.1 = load i32, ptr %fm.1.in
icmp eq i32 %fp.1.rec, %tmp8
br i1 %0, label %bb78.exitStub, label %bb26
bb26:
- %tmp28 = getelementptr i32*, i32** %tmp1, i32 %fp.1.rec
- %tmp30 = load i32*, i32** %tmp28
- %tmp33 = getelementptr i32, i32* %tmp30, i32 %i.0196.0.ph
- %tmp34 = load i32, i32* %tmp33
- %tmp38 = getelementptr i32, i32* %tmp30, i32 %tmp36224
- %tmp39 = load i32, i32* %tmp38
+ %tmp28 = getelementptr ptr, ptr %tmp1, i32 %fp.1.rec
+ %tmp30 = load ptr, ptr %tmp28
+ %tmp33 = getelementptr i32, ptr %tmp30, i32 %i.0196.0.ph
+ %tmp34 = load i32, ptr %tmp33
+ %tmp38 = getelementptr i32, ptr %tmp30, i32 %tmp36224
+ %tmp39 = load i32, ptr %tmp38
%tmp42 = mul i32 %tmp34, %fm.1
%tmp44 = add i32 %tmp42, %d0.1
- %tmp48 = getelementptr i32, i32* %tmp30, i32 %tmp46223
- %tmp49 = load i32, i32* %tmp48
+ %tmp48 = getelementptr i32, ptr %tmp30, i32 %tmp46223
+ %tmp49 = load i32, ptr %tmp48
%tmp52 = mul i32 %tmp39, %fm.1
%tmp54 = add i32 %tmp52, %d1.1
- %tmp58 = getelementptr i32, i32* %tmp30, i32 %tmp56222
- %tmp59 = load i32, i32* %tmp58
+ %tmp58 = getelementptr i32, ptr %tmp30, i32 %tmp56222
+ %tmp59 = load i32, ptr %tmp58
%tmp62 = mul i32 %tmp49, %fm.1
%tmp64 = add i32 %tmp62, %d2.1
%tmp67 = mul i32 %tmp59, %fm.1
%tmp69 = add i32 %tmp67, %d3.1
%tmp71.rec = add i32 %fp.1.rec, 1
- %tmp71 = getelementptr i32, i32* %tmp1011, i32 %tmp71.rec
+ %tmp71 = getelementptr i32, ptr %tmp1011, i32 %tmp71.rec
br label %bb74
}
diff --git a/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll b/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll
index 7c425961958ca..6ecca2f067207 100644
--- a/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll
+++ b/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll
@@ -3,32 +3,32 @@
%struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32 }
%struct.arm_stack_offsets = type { i32, i32, i32, i32, i32 }
- %struct.c_arg_info = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i8 }
+ %struct.c_arg_info = type { ptr, ptr, ptr, ptr, i8 }
%struct.c_language_function = type { %struct.stmt_tree_s }
%struct.c_switch = type opaque
%struct.eh_status = type opaque
- %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** }
- %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
- %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, i8, i8, i8 }
- %struct.ht_identifier = type { i8*, i32, i32 }
+ %struct.emit_status = type { i32, i32, ptr, ptr, ptr, i32, %struct.location_t, i32, ptr, ptr }
+ %struct.expr_status = type { i32, i32, i32, ptr, ptr, ptr }
+ %struct.function = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, i32, ptr, %struct.CUMULATIVE_ARGS, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i8, i32, i64, ptr, ptr, ptr, ptr, ptr, i32, ptr, i32, i32, ptr, ptr, i32, i32, i32, ptr, i32, i32, i8, i8, ptr, ptr, i32, i32, i32, i32, %struct.location_t, ptr, ptr, i8, i8, i8 }
+ %struct.ht_identifier = type { ptr, i32, i32 }
%struct.initial_value_struct = type opaque
%struct.lang_decl = type { i8 }
- %struct.language_function = type { %struct.c_language_function, %struct.tree_node*, %struct.tree_node*, %struct.c_switch*, %struct.c_arg_info*, i32, i32, i32, i32 }
- %struct.location_t = type { i8*, i32 }
- %struct.machine_function = type { %struct.rtx_def*, i32, i32, i32, %struct.arm_stack_offsets, i32, i32, i32, [14 x %struct.rtx_def*] }
- %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] }
+ %struct.language_function = type { %struct.c_language_function, ptr, ptr, ptr, ptr, i32, i32, i32, i32 }
+ %struct.location_t = type { ptr, i32 }
+ %struct.machine_function = type { ptr, i32, i32, i32, %struct.arm_stack_offsets, i32, i32, i32, [14 x ptr] }
+ %struct.rtvec_def = type { i32, [1 x ptr] }
%struct.rtx_def = type { i16, i8, i8, %struct.u }
- %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
- %struct.stmt_tree_s = type { %struct.tree_node*, i32 }
+ %struct.sequence_stack = type { ptr, ptr, ptr }
+ %struct.stmt_tree_s = type { ptr, i32 }
%struct.temp_slot = type opaque
- %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 }
- %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
+ %struct.tree_common = type { ptr, ptr, ptr, i8, i8, i8, i8, i8 }
+ %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, ptr, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, %struct.tree_decl_u2, ptr, ptr, i64, ptr }
%struct.tree_decl_u1 = type { i64 }
- %struct.tree_decl_u2 = type { %struct.function* }
+ %struct.tree_decl_u2 = type { ptr }
%struct.tree_identifier = type { %struct.tree_common, %struct.ht_identifier }
%struct.tree_node = type { %struct.tree_decl }
%struct.u = type { [1 x i64] }
- %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
+ %struct.var_refs_queue = type { ptr, i32, i32, ptr }
%struct.varasm_status = type opaque
%struct.varray_head_tag = type opaque
%union.tree_ann_d = type opaque
@@ -40,9 +40,8 @@ entry:
%spec.1961.adj = shl i64 %spec.1961, 32 ; <i64> [#uses=1]
%spec.1961.adj.ins = or i64 %spec.1961.adj, 0 ; <i64> [#uses=2]
%tmp10959 = lshr i64 %spec.1961.adj.ins, 32 ; <i64> [#uses=2]
- %tmp1920 = inttoptr i64 %tmp10959 to %struct.tree_common* ; <%struct.tree_common*> [#uses=1]
- %tmp21 = getelementptr %struct.tree_common, %struct.tree_common* %tmp1920, i32 0, i32 3 ; <i8*> [#uses=1]
- %tmp2122 = bitcast i8* %tmp21 to i32* ; <i32*> [#uses=1]
+ %tmp1920 = inttoptr i64 %tmp10959 to ptr ; <ptr> [#uses=1]
+ %tmp21 = getelementptr %struct.tree_common, ptr %tmp1920, i32 0, i32 3 ; <ptr> [#uses=1]
br i1 false, label %cond_next53, label %cond_true
cond_true: ; preds = %entry
@@ -71,7 +70,7 @@ cond_next856: ; preds = %cond_true851
ret void
bb866: ; preds = %cond_true851
- %tmp874 = load i32, i32* %tmp2122 ; <i32> [#uses=1]
+ %tmp874 = load i32, ptr %tmp21 ; <i32> [#uses=1]
%tmp876877 = trunc i32 %tmp874 to i8 ; <i8> [#uses=1]
icmp eq i8 %tmp876877, 1 ; <i1>:0 [#uses=1]
br i1 %0, label %cond_next881, label %cond_true878
@@ -80,10 +79,10 @@ cond_true878: ; preds = %bb866
unreachable
cond_next881: ; preds = %bb866
- %tmp884885 = inttoptr i64 %tmp10959 to %struct.tree_identifier* ; <%struct.tree_identifier*> [#uses=1]
- %tmp887 = getelementptr %struct.tree_identifier, %struct.tree_identifier* %tmp884885, i32 0, i32 1, i32 0 ; <i8**> [#uses=1]
- %tmp888 = load i8*, i8** %tmp887 ; <i8*> [#uses=1]
- tail call void (i32, ...) @error( i32 undef, i8* %tmp888 )
+ %tmp884885 = inttoptr i64 %tmp10959 to ptr ; <ptr> [#uses=1]
+ %tmp887 = getelementptr %struct.tree_identifier, ptr %tmp884885, i32 0, i32 1, i32 0 ; <ptr> [#uses=1]
+ %tmp888 = load ptr, ptr %tmp887 ; <ptr> [#uses=1]
+ tail call void (i32, ...) @error( i32 undef, ptr %tmp888 )
ret void
cond_true918: ; preds = %cond_false841
diff --git a/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll
index 14bb313185bc5..586dffd763ece 100644
--- a/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll
+++ b/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll
@@ -4,16 +4,16 @@
%struct.rtx_def = type { i16, i8, i8, %struct.u }
%struct.u = type { [1 x i64] }
-define fastcc void @find_reloads_address(%struct.rtx_def** %loc) {
+define fastcc void @find_reloads_address(ptr %loc) {
entry:
- %ad_addr = alloca %struct.rtx_def* ; <%struct.rtx_def**> [#uses=2]
+ %ad_addr = alloca ptr ; <ptr> [#uses=2]
br i1 false, label %cond_next416, label %cond_true340
cond_true340: ; preds = %entry
ret void
cond_next416: ; preds = %entry
- %tmp1085 = load %struct.rtx_def*, %struct.rtx_def** %ad_addr ; <%struct.rtx_def*> [#uses=1]
+ %tmp1085 = load ptr, ptr %ad_addr ; <ptr> [#uses=1]
br i1 false, label %bb1084, label %cond_true418
cond_true418: ; preds = %cond_next416
@@ -23,13 +23,12 @@ bb1084: ; preds = %cond_next416
br i1 false, label %cond_true1092, label %cond_next1102
cond_true1092: ; preds = %bb1084
- %tmp1094 = getelementptr %struct.rtx_def, %struct.rtx_def* %tmp1085, i32 0, i32 3 ; <%struct.u*> [#uses=1]
- %tmp10981099 = bitcast %struct.u* %tmp1094 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=2]
- %tmp1101 = load %struct.rtx_def*, %struct.rtx_def** %tmp10981099 ; <%struct.rtx_def*> [#uses=1]
- store %struct.rtx_def* %tmp1101, %struct.rtx_def** %ad_addr
+ %tmp1094 = getelementptr %struct.rtx_def, ptr %tmp1085, i32 0, i32 3 ; <ptr> [#uses=1]
+ %tmp1101 = load ptr, ptr %tmp1094 ; <ptr> [#uses=1]
+ store ptr %tmp1101, ptr %ad_addr
br label %cond_next1102
cond_next1102: ; preds = %cond_true1092, %bb1084
- %loc_addr.0 = phi %struct.rtx_def** [ %tmp10981099, %cond_true1092 ], [ %loc, %bb1084 ] ; <%struct.rtx_def**> [#uses=0]
+ %loc_addr.0 = phi ptr [ %tmp1094, %cond_true1092 ], [ %loc, %bb1084 ] ; <ptr> [#uses=0]
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll
index 8a62669708553..5efa284a356ca 100644
--- a/llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll
+++ b/llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll
@@ -4,30 +4,30 @@
%struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32 }
%struct.arm_stack_offsets = type { i32, i32, i32, i32, i32 }
%struct.eh_status = type opaque
- %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** }
- %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
- %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, i8, i8, i8 }
+ %struct.emit_status = type { i32, i32, ptr, ptr, ptr, i32, %struct.location_t, i32, ptr, ptr }
+ %struct.expr_status = type { i32, i32, i32, ptr, ptr, ptr }
+ %struct.function = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, i32, ptr, %struct.CUMULATIVE_ARGS, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i8, i32, i64, ptr, ptr, ptr, ptr, ptr, i32, ptr, i32, i32, ptr, ptr, i32, i32, i32, ptr, i32, i32, i8, i8, ptr, ptr, i32, i32, i32, i32, %struct.location_t, ptr, ptr, i8, i8, i8 }
%struct.initial_value_struct = type opaque
%struct.lang_decl = type opaque
%struct.language_function = type opaque
- %struct.location_t = type { i8*, i32 }
- %struct.machine_function = type { %struct.rtx_def*, i32, i32, i32, %struct.arm_stack_offsets, i32, i32, i32, [14 x %struct.rtx_def*] }
- %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] }
+ %struct.location_t = type { ptr, i32 }
+ %struct.machine_function = type { ptr, i32, i32, i32, %struct.arm_stack_offsets, i32, i32, i32, [14 x ptr] }
+ %struct.rtvec_def = type { i32, [1 x ptr] }
%struct.rtx_def = type { i16, i8, i8, %struct.u }
- %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
+ %struct.sequence_stack = type { ptr, ptr, ptr }
%struct.temp_slot = type opaque
- %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 }
- %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
+ %struct.tree_common = type { ptr, ptr, ptr, i8, i8, i8, i8, i8 }
+ %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, ptr, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, %struct.tree_decl_u2, ptr, ptr, i64, ptr }
%struct.tree_decl_u1 = type { i64 }
- %struct.tree_decl_u2 = type { %struct.function* }
+ %struct.tree_decl_u2 = type { ptr }
%struct.tree_node = type { %struct.tree_decl }
%struct.u = type { [1 x i64] }
- %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
+ %struct.var_refs_queue = type { ptr, i32, i32, ptr }
%struct.varasm_status = type opaque
- %struct.varray_head_tag = type { i32, i32, i32, i8*, %struct.u }
+ %struct.varray_head_tag = type { i32, i32, i32, ptr, %struct.u }
%union.tree_ann_d = type opaque
- at str469 = external global [42 x i8] ; <[42 x i8]*> [#uses=0]
- at __FUNCTION__.24265 = external global [19 x i8] ; <[19 x i8]*> [#uses=0]
+ at str469 = external global [42 x i8] ; <ptr> [#uses=0]
+ at __FUNCTION__.24265 = external global [19 x i8] ; <ptr> [#uses=0]
declare void @fancy_abort()
diff --git a/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll
index cf913536b3553..4cea5400980ea 100644
--- a/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll
+++ b/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll
@@ -3,36 +3,36 @@
%struct.H_TBL = type { [17 x i8], [256 x i8], i32 }
%struct.Q_TBL = type { [64 x i16], i32 }
%struct.anon = type { [80 x i8] }
- %struct.X_c_coef_ccler = type { void (%struct.X_Y*, i32)*, i32 (%struct.X_Y*, i8***)* }
- %struct.X_c_main_ccler = type { void (%struct.X_Y*, i32)*, void (%struct.X_Y*, i8**, i32*, i32)* }
- %struct.X_c_prep_ccler = type { void (%struct.X_Y*, i32)*, void (%struct.X_Y*, i8**, i32*, i32, i8***, i32*, i32)* }
- %struct.X_color_converter = type { void (%struct.X_Y*)*, void (%struct.X_Y*, i8**, i8***, i32, i32)* }
- %struct.X_common_struct = type { %struct.X_error_mgr*, %struct.X_memory_mgr*, %struct.X_progress_mgr*, i8*, i32, i32 }
- %struct.X_comp_main = type { void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, i32, i32 }
- %struct.X_component_info = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.Q_TBL*, i8* }
- %struct.X_Y = type { %struct.X_error_mgr*, %struct.X_memory_mgr*, %struct.X_progress_mgr*, i8*, i32, i32, %struct.X_destination_mgr*, i32, i32, i32, i32, double, i32, i32, i32, %struct.X_component_info*, [4 x %struct.Q_TBL*], [4 x %struct.H_TBL*], [4 x %struct.H_TBL*], [16 x i8], [16 x i8], [16 x i8], i32, %struct.X_scan_info*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i16, i16, i32, i32, i32, i32, i32, i32, i32, [4 x %struct.X_component_info*], i32, i32, i32, [10 x i32], i32, i32, i32, i32, %struct.X_comp_main*, %struct.X_c_main_ccler*, %struct.X_c_prep_ccler*, %struct.X_c_coef_ccler*, %struct.X_marker_writer*, %struct.X_color_converter*, %struct.X_downssr*, %struct.X_forward_D*, %struct.X_entropy_en*, %struct.X_scan_info*, i32 }
- %struct.X_destination_mgr = type { i8*, i32, void (%struct.X_Y*)*, i32 (%struct.X_Y*)*, void (%struct.X_Y*)* }
- %struct.X_downssr = type { void (%struct.X_Y*)*, void (%struct.X_Y*, i8***, i32, i8***, i32)*, i32 }
- %struct.X_entropy_en = type { void (%struct.X_Y*, i32)*, i32 (%struct.X_Y*, [64 x i16]**)*, void (%struct.X_Y*)* }
- %struct.X_error_mgr = type { void (%struct.X_common_struct*)*, void (%struct.X_common_struct*, i32)*, void (%struct.X_common_struct*)*, void (%struct.X_common_struct*, i8*)*, void (%struct.X_common_struct*)*, i32, %struct.anon, i32, i32, i8**, i32, i8**, i32, i32 }
- %struct.X_forward_D = type { void (%struct.X_Y*)*, void (%struct.X_Y*, %struct.X_component_info*, i8**, [64 x i16]*, i32, i32, i32)* }
- %struct.X_marker_writer = type { void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*, i32, i32)*, void (%struct.X_Y*, i32)* }
- %struct.X_memory_mgr = type { i8* (%struct.X_common_struct*, i32, i32)*, i8* (%struct.X_common_struct*, i32, i32)*, i8** (%struct.X_common_struct*, i32, i32, i32)*, [64 x i16]** (%struct.X_common_struct*, i32, i32, i32)*, %struct.jvirt_sAY_cc* (%struct.X_common_struct*, i32, i32, i32, i32, i32)*, %struct.jvirt_bAY_cc* (%struct.X_common_struct*, i32, i32, i32, i32, i32)*, void (%struct.X_common_struct*)*, i8** (%struct.X_common_struct*, %struct.jvirt_sAY_cc*, i32, i32, i32)*, [64 x i16]** (%struct.X_common_struct*, %struct.jvirt_bAY_cc*, i32, i32, i32)*, void (%struct.X_common_struct*, i32)*, void (%struct.X_common_struct*)*, i32, i32 }
- %struct.X_progress_mgr = type { void (%struct.X_common_struct*)*, i32, i32, i32, i32 }
+ %struct.X_c_coef_ccler = type { ptr, ptr }
+ %struct.X_c_main_ccler = type { ptr, ptr }
+ %struct.X_c_prep_ccler = type { ptr, ptr }
+ %struct.X_color_converter = type { ptr, ptr }
+ %struct.X_common_struct = type { ptr, ptr, ptr, ptr, i32, i32 }
+ %struct.X_comp_main = type { ptr, ptr, ptr, i32, i32 }
+ %struct.X_component_info = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, ptr }
+ %struct.X_Y = type { ptr, ptr, ptr, ptr, i32, i32, ptr, i32, i32, i32, i32, double, i32, i32, i32, ptr, [4 x ptr], [4 x ptr], [4 x ptr], [16 x i8], [16 x i8], [16 x i8], i32, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i16, i16, i32, i32, i32, i32, i32, i32, i32, [4 x ptr], i32, i32, i32, [10 x i32], i32, i32, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32 }
+ %struct.X_destination_mgr = type { ptr, i32, ptr, ptr, ptr }
+ %struct.X_downssr = type { ptr, ptr, i32 }
+ %struct.X_entropy_en = type { ptr, ptr, ptr }
+ %struct.X_error_mgr = type { ptr, ptr, ptr, ptr, ptr, i32, %struct.anon, i32, i32, ptr, i32, ptr, i32, i32 }
+ %struct.X_forward_D = type { ptr, ptr }
+ %struct.X_marker_writer = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr }
+ %struct.X_memory_mgr = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32 }
+ %struct.X_progress_mgr = type { ptr, i32, i32, i32, i32 }
%struct.X_scan_info = type { i32, [4 x i32], i32, i32, i32, i32 }
%struct.jvirt_bAY_cc = type opaque
%struct.jvirt_sAY_cc = type opaque
-define void @test(%struct.X_Y* %cinfo) {
+define void @test(ptr %cinfo) {
entry:
br i1 false, label %bb.preheader, label %return
bb.preheader: ; preds = %entry
- %tbl.014.us = load i32, i32* null ; <i32> [#uses=1]
+ %tbl.014.us = load i32, ptr null ; <i32> [#uses=1]
br i1 false, label %cond_next.us, label %bb
cond_next51.us: ; preds = %cond_next.us, %cond_true33.us.cond_true46.us_crit_edge
- %htblptr.019.1.us = phi %struct.H_TBL** [ %tmp37.us, %cond_true33.us.cond_true46.us_crit_edge ], [ %tmp37.us, %cond_next.us ] ; <%struct.H_TBL**> [#uses=0]
+ %htblptr.019.1.us = phi ptr [ %tmp37.us, %cond_true33.us.cond_true46.us_crit_edge ], [ %tmp37.us, %cond_next.us ] ; <ptr> [#uses=0]
ret void
cond_true33.us.cond_true46.us_crit_edge: ; preds = %cond_next.us
@@ -40,9 +40,9 @@ cond_true33.us.cond_true46.us_crit_edge: ; preds = %cond_next.us
br label %cond_next51.us
cond_next.us: ; preds = %bb.preheader
- %tmp37.us = getelementptr %struct.X_Y, %struct.X_Y* %cinfo, i32 0, i32 17, i32 %tbl.014.us ; <%struct.H_TBL**> [#uses=3]
- %tmp4524.us = load %struct.H_TBL*, %struct.H_TBL** %tmp37.us ; <%struct.H_TBL*> [#uses=1]
- icmp eq %struct.H_TBL* %tmp4524.us, null ; <i1>:0 [#uses=1]
+ %tmp37.us = getelementptr %struct.X_Y, ptr %cinfo, i32 0, i32 17, i32 %tbl.014.us ; <ptr> [#uses=3]
+ %tmp4524.us = load ptr, ptr %tmp37.us ; <ptr> [#uses=1]
+ icmp eq ptr %tmp4524.us, null ; <i1>:0 [#uses=1]
br i1 %0, label %cond_true33.us.cond_true46.us_crit_edge, label %cond_next51.us
bb: ; preds = %bb.preheader
diff --git a/llvm/test/CodeGen/ARM/2007-04-03-PEIBug.ll b/llvm/test/CodeGen/ARM/2007-04-03-PEIBug.ll
index 87863bd3ec15d..d8acdb91be5d8 100644
--- a/llvm/test/CodeGen/ARM/2007-04-03-PEIBug.ll
+++ b/llvm/test/CodeGen/ARM/2007-04-03-PEIBug.ll
@@ -2,10 +2,10 @@
define i32 @foo() {
entry:
- %A = alloca [1123 x i32], align 16 ; <[1123 x i32]*> [#uses=1]
- %B = alloca [3123 x i32], align 16 ; <[3123 x i32]*> [#uses=1]
- %C = alloca [12312 x i32], align 16 ; <[12312 x i32]*> [#uses=1]
- %tmp = call i32 (...) @bar( [3123 x i32]* %B, [1123 x i32]* %A, [12312 x i32]* %C ) ; <i32> [#uses=0]
+ %A = alloca [1123 x i32], align 16 ; <ptr> [#uses=1]
+ %B = alloca [3123 x i32], align 16 ; <ptr> [#uses=1]
+ %C = alloca [12312 x i32], align 16 ; <ptr> [#uses=1]
+ %tmp = call i32 (...) @bar( ptr %B, ptr %A, ptr %C ) ; <i32> [#uses=0]
ret i32 undef
}
diff --git a/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll b/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll
index 1703bdc0228f4..e0143e029d086 100644
--- a/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll
+++ b/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll
@@ -1,25 +1,23 @@
; RUN: llc -mtriple arm-apple-darwin -relocation-model pic -filetype asm -o - %s | FileCheck %s
%struct.B = type { i32 }
-%struct.anon = type { void (%struct.B*)*, i32 }
+%struct.anon = type { ptr, i32 }
@str = internal constant [7 x i8] c"i, %d\0A\00"
@str1 = internal constant [7 x i8] c"j, %d\0A\00"
-define internal void @_ZN1B1iEv(%struct.B* %this) {
+define internal void @_ZN1B1iEv(ptr %this) {
entry:
- %tmp1 = getelementptr %struct.B, %struct.B* %this, i32 0, i32 0
- %tmp2 = load i32, i32* %tmp1
- %tmp4 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([7 x i8], [7 x i8]* @str, i32 0, i32 0), i32 %tmp2)
+ %tmp2 = load i32, ptr %this
+ %tmp4 = tail call i32 (ptr, ...) @printf(ptr @str, i32 %tmp2)
ret void
}
-declare i32 @printf(i8*, ...)
+declare i32 @printf(ptr, ...)
-define internal void @_ZN1B1jEv(%struct.B* %this) {
+define internal void @_ZN1B1jEv(ptr %this) {
entry:
- %tmp1 = getelementptr %struct.B, %struct.B* %this, i32 0, i32 0
- %tmp2 = load i32, i32* %tmp1
- %tmp4 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([7 x i8], [7 x i8]* @str1, i32 0, i32 0), i32 %tmp2)
+ %tmp2 = load i32, ptr %this
+ %tmp4 = tail call i32 (ptr, ...) @printf(ptr @str1, i32 %tmp2)
ret void
}
@@ -28,72 +26,48 @@ entry:
%b.i29 = alloca %struct.B, align 4
%b.i1 = alloca %struct.B, align 4
%b.i = alloca %struct.B, align 4
- %tmp2.i = getelementptr %struct.B, %struct.B* %b.i, i32 0, i32 0
- store i32 4, i32* %tmp2.i
- br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit, label %cond_true.i
+ store i32 4, ptr %b.i
+ br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit, label %cond_true.i
cond_true.i:
- %b2.i = bitcast %struct.B* %b.i to i8*
- %ctg23.i = getelementptr i8, i8* %b2.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)
- %tmp121314.i = bitcast i8* %ctg23.i to i32 (...)***
- %tmp15.i = load i32 (...)**, i32 (...)*** %tmp121314.i
- %tmp151.i = bitcast i32 (...)** %tmp15.i to i8*
- %ctg2.i = getelementptr i8, i8* %tmp151.i, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32)
- %tmp2021.i = bitcast i8* %ctg2.i to i32 (...)**
- %tmp22.i = load i32 (...)*, i32 (...)** %tmp2021.i
- %tmp2223.i = bitcast i32 (...)* %tmp22.i to void (%struct.B*)*
+ %ctg23.i = getelementptr i8, ptr %b.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)
+ %tmp15.i = load ptr, ptr %ctg23.i
+ %ctg2.i = getelementptr i8, ptr %tmp15.i, i32 ptrtoint (ptr @_ZN1B1iEv to i32)
+ %tmp22.i = load ptr, ptr %ctg2.i
br label %_Z3fooiM1BFvvE.exit
_Z3fooiM1BFvvE.exit:
- %iftmp.2.0.i = phi void (%struct.B*)* [ %tmp2223.i, %cond_true.i ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to void (%struct.B*)*), %entry ]
- %b4.i = bitcast %struct.B* %b.i to i8*
- %ctg25.i = getelementptr i8, i8* %b4.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)
- %tmp3031.i = bitcast i8* %ctg25.i to %struct.B*
- call void %iftmp.2.0.i(%struct.B* %tmp3031.i)
- %tmp2.i30 = getelementptr %struct.B, %struct.B* %b.i29, i32 0, i32 0
- store i32 6, i32* %tmp2.i30
- br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit56, label %cond_true.i46
+ %iftmp.2.0.i = phi ptr [ %tmp22.i, %cond_true.i ], [ inttoptr (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to ptr), %entry ]
+ %ctg25.i = getelementptr i8, ptr %b.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)
+ call void %iftmp.2.0.i(ptr %ctg25.i)
+ store i32 6, ptr %b.i29
+ br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (ptr @_ZN1B1jEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit56, label %cond_true.i46
cond_true.i46:
- %b2.i35 = bitcast %struct.B* %b.i29 to i8*
- %ctg23.i36 = getelementptr i8, i8* %b2.i35, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1)
- %tmp121314.i37 = bitcast i8* %ctg23.i36 to i32 (...)***
- %tmp15.i38 = load i32 (...)**, i32 (...)*** %tmp121314.i37
- %tmp151.i41 = bitcast i32 (...)** %tmp15.i38 to i8*
- %ctg2.i42 = getelementptr i8, i8* %tmp151.i41, i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32)
- %tmp2021.i43 = bitcast i8* %ctg2.i42 to i32 (...)**
- %tmp22.i44 = load i32 (...)*, i32 (...)** %tmp2021.i43
- %tmp2223.i45 = bitcast i32 (...)* %tmp22.i44 to void (%struct.B*)*
+ %ctg23.i36 = getelementptr i8, ptr %b.i29, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (ptr @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1)
+ %tmp15.i38 = load ptr, ptr %ctg23.i36
+ %ctg2.i42 = getelementptr i8, ptr %tmp15.i38, i32 ptrtoint (ptr @_ZN1B1jEv to i32)
+ %tmp22.i44 = load ptr, ptr %ctg2.i42
br label %_Z3fooiM1BFvvE.exit56
_Z3fooiM1BFvvE.exit56:
- %iftmp.2.0.i49 = phi void (%struct.B*)* [ %tmp2223.i45, %cond_true.i46 ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to void (%struct.B*)*), %_Z3fooiM1BFvvE.exit ]
- %b4.i53 = bitcast %struct.B* %b.i29 to i8*
- %ctg25.i54 = getelementptr i8, i8* %b4.i53, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1)
- %tmp3031.i55 = bitcast i8* %ctg25.i54 to %struct.B*
- call void %iftmp.2.0.i49(%struct.B* %tmp3031.i55)
- %tmp2.i2 = getelementptr %struct.B, %struct.B* %b.i1, i32 0, i32 0
- store i32 -1, i32* %tmp2.i2
- br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit28, label %cond_true.i18
+ %iftmp.2.0.i49 = phi ptr [ %tmp22.i44, %cond_true.i46 ], [ inttoptr (i32 ptrtoint (ptr @_ZN1B1jEv to i32) to ptr), %_Z3fooiM1BFvvE.exit ]
+ %ctg25.i54 = getelementptr i8, ptr %b.i29, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (ptr @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1)
+ call void %iftmp.2.0.i49(ptr %ctg25.i54)
+ store i32 -1, ptr %b.i1
+ br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit28, label %cond_true.i18
cond_true.i18:
- %b2.i7 = bitcast %struct.B* %b.i1 to i8*
- %ctg23.i8 = getelementptr i8, i8* %b2.i7, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)
- %tmp121314.i9 = bitcast i8* %ctg23.i8 to i32 (...)***
- %tmp15.i10 = load i32 (...)**, i32 (...)*** %tmp121314.i9
- %tmp151.i13 = bitcast i32 (...)** %tmp15.i10 to i8*
- %ctg2.i14 = getelementptr i8, i8* %tmp151.i13, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32)
- %tmp2021.i15 = bitcast i8* %ctg2.i14 to i32 (...)**
- %tmp22.i16 = load i32 (...)*, i32 (...)** %tmp2021.i15
- %tmp2223.i17 = bitcast i32 (...)* %tmp22.i16 to void (%struct.B*)*
+ %ctg23.i8 = getelementptr i8, ptr %b.i1, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)
+ %tmp15.i10 = load ptr, ptr %ctg23.i8
+ %ctg2.i14 = getelementptr i8, ptr %tmp15.i10, i32 ptrtoint (ptr @_ZN1B1iEv to i32)
+ %tmp22.i16 = load ptr, ptr %ctg2.i14
br label %_Z3fooiM1BFvvE.exit28
_Z3fooiM1BFvvE.exit28:
- %iftmp.2.0.i21 = phi void (%struct.B*)* [ %tmp2223.i17, %cond_true.i18 ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to void (%struct.B*)*), %_Z3fooiM1BFvvE.exit56 ]
- %b4.i25 = bitcast %struct.B* %b.i1 to i8*
- %ctg25.i26 = getelementptr i8, i8* %b4.i25, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)
- %tmp3031.i27 = bitcast i8* %ctg25.i26 to %struct.B*
- call void %iftmp.2.0.i21(%struct.B* %tmp3031.i27)
+ %iftmp.2.0.i21 = phi ptr [ %tmp22.i16, %cond_true.i18 ], [ inttoptr (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to ptr), %_Z3fooiM1BFvvE.exit56 ]
+ %ctg25.i26 = getelementptr i8, ptr %b.i1, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (ptr @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1)
+ call void %iftmp.2.0.i21(ptr %ctg25.i26)
ret i32 0
}
diff --git a/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll b/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll
index 05c2ff4f7ca2c..5e817af8058ee 100644
--- a/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll
+++ b/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll
@@ -3,21 +3,21 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "arm-apple-darwin8"
%struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 }
- at search = external global %struct.CHESS_POSITION ; <%struct.CHESS_POSITION*> [#uses=3]
- at file_mask = external global [8 x i64] ; <[8 x i64]*> [#uses=1]
- at rank_mask.1.b = external global i1 ; <i1*> [#uses=1]
+ at search = external global %struct.CHESS_POSITION ; <ptr> [#uses=3]
+ at file_mask = external global [8 x i64] ; <ptr> [#uses=1]
+ at rank_mask.1.b = external global i1 ; <ptr> [#uses=1]
define fastcc void @EvaluateDevelopment() {
entry:
- %tmp7 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 7) ; <i64> [#uses=1]
- %tmp50 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 0) ; <i64> [#uses=1]
- %tmp52 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 1) ; <i64> [#uses=1]
+ %tmp7 = load i64, ptr getelementptr (%struct.CHESS_POSITION, ptr @search, i32 0, i32 7) ; <i64> [#uses=1]
+ %tmp50 = load i64, ptr @search ; <i64> [#uses=1]
+ %tmp52 = load i64, ptr getelementptr (%struct.CHESS_POSITION, ptr @search, i32 0, i32 1) ; <i64> [#uses=1]
%tmp53 = or i64 %tmp52, %tmp50 ; <i64> [#uses=1]
- %tmp57.b = load i1, i1* @rank_mask.1.b ; <i1> [#uses=1]
+ %tmp57.b = load i1, ptr @rank_mask.1.b ; <i1> [#uses=1]
%tmp57 = select i1 %tmp57.b, i64 71776119061217280, i64 0 ; <i64> [#uses=1]
%tmp58 = and i64 %tmp57, %tmp7 ; <i64> [#uses=1]
%tmp59 = lshr i64 %tmp58, 8 ; <i64> [#uses=1]
- %tmp63 = load i64, i64* getelementptr ([8 x i64], [8 x i64]* @file_mask, i32 0, i32 4) ; <i64> [#uses=1]
+ %tmp63 = load i64, ptr getelementptr ([8 x i64], ptr @file_mask, i32 0, i32 4) ; <i64> [#uses=1]
%tmp64 = or i64 %tmp63, 0 ; <i64> [#uses=1]
%tmp65 = and i64 %tmp59, %tmp53 ; <i64> [#uses=1]
%tmp66 = and i64 %tmp65, %tmp64 ; <i64> [#uses=1]
diff --git a/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll b/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll
index 50573b457c377..fc349bfb8c8e0 100644
--- a/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll
+++ b/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll
@@ -1,20 +1,20 @@
; RUN: llc < %s -mtriple=arm-apple-darwin
%struct.Connection = type { i32, [10 x i8], i32 }
- %struct.IntChunk = type { %struct.cppobjtype, i32, i32*, i32 }
- %struct.Point = type { i8*, %struct.cppobjtype, i16 (%struct.Point*) *, i16 (%struct.Point*) *, double (%struct.Point*)*, double (%struct.Point*)* }
- %struct.RefPoint = type { %struct.Point*, %struct.cppobjtype }
- %struct.ShortArray = type { %struct.cppobjtype, i32, i16* }
- %struct.TestObj = type { i8*, %struct.cppobjtype, i8, [32 x i8], i8*, i8**, i16, i16, i32, i32, i32, i32, float, double, %struct.cppobjtype, i32, i16*, i16**, i8**, i32, %struct.XyPoint, [3 x %struct.Connection], %struct.Point*, %struct.XyPoint*, i32, i8*, i8*, i16*, %struct.ShortArray, %struct.IntChunk, %struct.cppobjtype, %struct.cppobjtype, %struct.RefPoint, i32, %struct.cppobjtype, %struct.cppobjtype }
+ %struct.IntChunk = type { %struct.cppobjtype, i32, ptr, i32 }
+ %struct.Point = type { ptr, %struct.cppobjtype, ptr, ptr, ptr, ptr }
+ %struct.RefPoint = type { ptr, %struct.cppobjtype }
+ %struct.ShortArray = type { %struct.cppobjtype, i32, ptr }
+ %struct.TestObj = type { ptr, %struct.cppobjtype, i8, [32 x i8], ptr, ptr, i16, i16, i32, i32, i32, i32, float, double, %struct.cppobjtype, i32, ptr, ptr, ptr, i32, %struct.XyPoint, [3 x %struct.Connection], ptr, ptr, i32, ptr, ptr, ptr, %struct.ShortArray, %struct.IntChunk, %struct.cppobjtype, %struct.cppobjtype, %struct.RefPoint, i32, %struct.cppobjtype, %struct.cppobjtype }
%struct.XyPoint = type { i16, i16 }
%struct.cppobjtype = type { i32, i16, i16 }
- at Msg = external global [256 x i8] ; <[256 x i8]*> [#uses=1]
- at .str53615 = external constant [48 x i8] ; <[48 x i8]*> [#uses=1]
- at FirstTime.4637.b = external global i1 ; <i1*> [#uses=1]
+ at Msg = external global [256 x i8] ; <ptr> [#uses=1]
+ at .str53615 = external constant [48 x i8] ; <ptr> [#uses=1]
+ at FirstTime.4637.b = external global i1 ; <ptr> [#uses=1]
-define fastcc void @Draw7(i32 %Option, i32* %Status) {
+define fastcc void @Draw7(i32 %Option, ptr %Status) {
entry:
- %tmp115.b = load i1, i1* @FirstTime.4637.b ; <i1> [#uses=1]
+ %tmp115.b = load i1, ptr @FirstTime.4637.b ; <i1> [#uses=1]
br i1 %tmp115.b, label %cond_next239, label %cond_next.i
cond_next.i: ; preds = %entry
@@ -88,19 +88,19 @@ cond_next1267: ; preds = %cond_next1235
br i1 %tmp1148, label %cond_next1275, label %cond_true1272
cond_true1272: ; preds = %cond_next1267
- %tmp1273 = load %struct.TestObj*, %struct.TestObj** null ; <%struct.TestObj*> [#uses=2]
- %tmp2930.i = ptrtoint %struct.TestObj* %tmp1273 to i32 ; <i32> [#uses=1]
+ %tmp1273 = load ptr, ptr null ; <ptr> [#uses=2]
+ %tmp2930.i = ptrtoint ptr %tmp1273 to i32 ; <i32> [#uses=1]
%tmp42.i348 = sub i32 0, %tmp2930.i ; <i32> [#uses=1]
- %tmp45.i = getelementptr %struct.TestObj, %struct.TestObj* %tmp1273, i32 0, i32 0 ; <i8**> [#uses=2]
- %tmp48.i = load i8*, i8** %tmp45.i ; <i8*> [#uses=1]
- %tmp50.i350 = call i32 (i8*, i8*, ...) @sprintf( i8* getelementptr ([256 x i8], [256 x i8]* @Msg, i32 0, i32 0), i8* getelementptr ([48 x i8], [48 x i8]* @.str53615, i32 0, i32 0), i8* null, i8** %tmp45.i, i8* %tmp48.i ) ; <i32> [#uses=0]
+ %tmp45.i = getelementptr %struct.TestObj, ptr %tmp1273, i32 0, i32 0 ; <ptr> [#uses=2]
+ %tmp48.i = load ptr, ptr %tmp45.i ; <ptr> [#uses=1]
+ %tmp50.i350 = call i32 (ptr, ptr, ...) @sprintf( ptr @Msg, ptr @.str53615, ptr null, ptr %tmp45.i, ptr %tmp48.i ) ; <i32> [#uses=0]
br i1 false, label %cond_true.i632.i, label %Ut_TraceMsg.exit648.i
cond_true.i632.i: ; preds = %cond_true1272
ret void
Ut_TraceMsg.exit648.i: ; preds = %cond_true1272
- %tmp57.i = getelementptr i8, i8* null, i32 %tmp42.i348 ; <i8*> [#uses=0]
+ %tmp57.i = getelementptr i8, ptr null, i32 %tmp42.i348 ; <ptr> [#uses=0]
ret void
cond_next1275: ; preds = %cond_next1267
@@ -110,4 +110,4 @@ bb1326: ; preds = %cond_next315, %cond_next253
ret void
}
-declare i32 @sprintf(i8*, i8*, ...)
+declare i32 @sprintf(ptr, ptr, ...)
diff --git a/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll b/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll
index f49c805469a04..ac50bdfaf78ce 100644
--- a/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll
+++ b/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll
@@ -12,12 +12,12 @@ target triple = "arm-apple-darwin8"
define i32 @f(i32 %i, i32 %q) {
entry:
- %i_addr = alloca i32 ; <i32*> [#uses=2]
- %q_addr = alloca i32 ; <i32*> [#uses=2]
- %retval = alloca i32, align 4 ; <i32*> [#uses=1]
- store i32 %i, i32* %i_addr
- store i32 %q, i32* %q_addr
- %tmp = load i32, i32* %i_addr ; <i32> [#uses=1]
+ %i_addr = alloca i32 ; <ptr> [#uses=2]
+ %q_addr = alloca i32 ; <ptr> [#uses=2]
+ %retval = alloca i32, align 4 ; <ptr> [#uses=1]
+ store i32 %i, ptr %i_addr
+ store i32 %q, ptr %q_addr
+ %tmp = load i32, ptr %i_addr ; <i32> [#uses=1]
%tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1]
%tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1]
%toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1]
@@ -34,7 +34,7 @@ cond_false: ; preds = %entry
br label %cond_next
cond_next: ; preds = %cond_false, %cond_true
- %tmp7 = load i32, i32* %q_addr ; <i32> [#uses=1]
+ %tmp7 = load i32, ptr %q_addr ; <i32> [#uses=1]
%tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1]
%tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1]
%toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1]
@@ -55,7 +55,7 @@ cond_next18: ; preds = %cond_false15, %cond_true11
br label %return
return: ; preds = %cond_next18
- %retval20 = load i32, i32* %retval ; <i32> [#uses=1]
+ %retval20 = load i32, ptr %retval ; <i32> [#uses=1]
ret i32 %retval20
}
diff --git a/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll b/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll
index 21e2169aca335..f9804c204c59c 100644
--- a/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll
+++ b/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll
@@ -14,12 +14,12 @@ target triple = "arm-apple-darwin8"
define i32 @f(i32 %i, i32 %q) {
entry:
- %i_addr = alloca i32 ; <i32*> [#uses=2]
- %q_addr = alloca i32 ; <i32*> [#uses=2]
- %retval = alloca i32, align 4 ; <i32*> [#uses=1]
- store i32 %i, i32* %i_addr
- store i32 %q, i32* %q_addr
- %tmp = load i32, i32* %i_addr ; <i32> [#uses=1]
+ %i_addr = alloca i32 ; <ptr> [#uses=2]
+ %q_addr = alloca i32 ; <ptr> [#uses=2]
+ %retval = alloca i32, align 4 ; <ptr> [#uses=1]
+ store i32 %i, ptr %i_addr
+ store i32 %q, ptr %q_addr
+ %tmp = load i32, ptr %i_addr ; <i32> [#uses=1]
%tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1]
%tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1]
%toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1]
@@ -28,7 +28,7 @@ entry:
cond_true: ; preds = %entry
%tmp3 = call i32 (...) @bar( ) ; <i32> [#uses=0]
%tmp4 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
- %tmp7 = load i32, i32* %q_addr ; <i32> [#uses=1]
+ %tmp7 = load i32, ptr %q_addr ; <i32> [#uses=1]
%tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1]
%tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1]
%toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1]
@@ -37,7 +37,7 @@ cond_true: ; preds = %entry
cond_false: ; preds = %entry
%tmp5 = call i32 (...) @foo( ) ; <i32> [#uses=0]
%tmp6 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
- %tmp27 = load i32, i32* %q_addr ; <i32> [#uses=1]
+ %tmp27 = load i32, ptr %q_addr ; <i32> [#uses=1]
%tmp28 = icmp ne i32 %tmp27, 0 ; <i1> [#uses=1]
%tmp289 = zext i1 %tmp28 to i8 ; <i8> [#uses=1]
%toBool210 = icmp ne i8 %tmp289, 0 ; <i1> [#uses=1]
@@ -58,7 +58,7 @@ cond_next18: ; preds = %cond_false15, %cond_true11
br label %return
return: ; preds = %cond_next18
- %retval20 = load i32, i32* %retval ; <i32> [#uses=1]
+ %retval20 = load i32, ptr %retval ; <i32> [#uses=1]
ret i32 %retval20
}
diff --git a/llvm/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll
index 78e132e1ecce4..18510c4343aa5 100644
--- a/llvm/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll
+++ b/llvm/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll
@@ -1,17 +1,17 @@
; RUN: llc < %s -mtriple=arm-linux-gnueabi
; PR1406
- %struct.AVClass = type { i8*, i8* (i8*)*, %struct.AVOption* }
- %struct.AVCodec = type { i8*, i32, i32, i32, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32, i8*)*, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32*, i8*, i32)*, i32, %struct.AVCodec*, void (%struct.AVCodecContext*)*, %struct.AVRational*, i32* }
- %struct.AVCodecContext = type { %struct.AVClass*, i32, i32, i32, i32, i32, i8*, i32, %struct.AVRational, i32, i32, i32, i32, i32, void (%struct.AVCodecContext*, %struct.AVFrame*, i32*, i32, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, float, float, i32, i32, i32, i32, float, i32, i32, i32, %struct.AVCodec*, i8*, i32, i32, void (%struct.AVCodecContext*, i8*, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, [32 x i8], i32, i32, i32, i32, i32, i32, i32, float, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, void (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i8*, i8*, float, float, i32, %struct.RcOverride*, i32, i8*, i32, i32, i32, float, float, float, float, i32, float, float, float, float, float, i32, i32, i32, i32*, i32, i32, i32, i32, %struct.AVRational, %struct.AVFrame*, i32, i32, [4 x i64], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32*)*, i32, i32, i32, i32, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i16*, i16*, i32, i32, i32, i32, %struct.AVPaletteControl*, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32 (%struct.AVCodecContext*, i8*)*, i8**, i32*, i32)*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64 }
- %struct.AVFrame = type { [4 x i8*], [4 x i32], [4 x i8*], i32, i32, i64, i32, i32, i32, i32, i32, i8*, i32, i8*, [2 x [2 x i16]*], i32*, i8, i8*, [4 x i64], i32, i32, i32, i32, i32, %struct.AVPanScan*, i32, i32, i16*, [2 x i8*] }
+ %struct.AVClass = type { ptr, ptr, ptr }
+ %struct.AVCodec = type { ptr, i32, i32, i32, ptr, ptr, ptr, ptr, i32, ptr, ptr, ptr, ptr }
+ %struct.AVCodecContext = type { ptr, i32, i32, i32, i32, i32, ptr, i32, %struct.AVRational, i32, i32, i32, i32, i32, ptr, i32, i32, i32, i32, i32, i32, i32, float, float, i32, i32, i32, i32, float, i32, i32, i32, ptr, ptr, i32, i32, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, [32 x i8], i32, i32, i32, i32, i32, i32, i32, float, i32, ptr, ptr, i32, i32, i32, i32, ptr, ptr, float, float, i32, ptr, i32, ptr, i32, i32, i32, float, float, float, float, i32, float, float, float, float, float, i32, i32, i32, ptr, i32, i32, i32, i32, %struct.AVRational, ptr, i32, i32, [4 x i64], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, i32, i32, i32, i32, i32, i32, ptr, i32, i32, i32, i32, i32, i32, ptr, ptr, i32, i32, i32, i32, ptr, i32, ptr, i32, i32, i32, i32, i32, i32, i32, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64 }
+ %struct.AVFrame = type { [4 x ptr], [4 x i32], [4 x ptr], i32, i32, i64, i32, i32, i32, i32, i32, ptr, i32, ptr, [2 x ptr], ptr, i8, ptr, [4 x i64], i32, i32, i32, i32, i32, ptr, i32, i32, ptr, [2 x ptr] }
%struct.AVOption = type opaque
%struct.AVPaletteControl = type { i32, [256 x i32] }
%struct.AVPanScan = type { i32, i32, i32, [3 x [2 x i16]] }
%struct.AVRational = type { i32, i32 }
%struct.RcOverride = type { i32, i32, i32, float }
-define i32 @decode_init(%struct.AVCodecContext* %avctx) {
+define i32 @decode_init(ptr %avctx) {
entry:
br i1 false, label %bb, label %cond_next789
@@ -21,8 +21,8 @@ bb: ; preds = %bb, %entry
bb59: ; preds = %bb
%tmp68 = sdiv i64 0, 0 ; <i64> [#uses=1]
%tmp6869 = trunc i64 %tmp68 to i32 ; <i32> [#uses=2]
- %tmp81 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, $1, lsl $5\0A\09", "=&r,=*&r,r,r,i,i"( i32* elementtype( i32) null, i32 %tmp6869, i32 13316085, i32 23, i32 9 ) ; <i32> [#uses=0]
- %tmp90 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, $1, lsl $5\0A\09", "=&r,=*&r,r,r,i,i"( i32* elementtype( i32) null, i32 %tmp6869, i32 10568984, i32 23, i32 9 ) ; <i32> [#uses=0]
+ %tmp81 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, $1, lsl $5\0A\09", "=&r,=*&r,r,r,i,i"( ptr elementtype( i32) null, i32 %tmp6869, i32 13316085, i32 23, i32 9 ) ; <i32> [#uses=0]
+ %tmp90 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, $1, lsl $5\0A\09", "=&r,=*&r,r,r,i,i"( ptr elementtype( i32) null, i32 %tmp6869, i32 10568984, i32 23, i32 9 ) ; <i32> [#uses=0]
unreachable
cond_next789: ; preds = %entry
diff --git a/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll b/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll
index 7669a03c969a3..7fa6dd3ebec3a 100644
--- a/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll
+++ b/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll
@@ -23,12 +23,12 @@ target triple = "arm-apple-darwin8"
define i32 @f(i32 %i, i32 %q) {
entry:
- %i_addr = alloca i32 ; <i32*> [#uses=2]
- %q_addr = alloca i32 ; <i32*> [#uses=2]
- %retval = alloca i32, align 4 ; <i32*> [#uses=1]
- store i32 %i, i32* %i_addr
- store i32 %q, i32* %q_addr
- %tmp = load i32, i32* %i_addr ; <i32> [#uses=1]
+ %i_addr = alloca i32 ; <ptr> [#uses=2]
+ %q_addr = alloca i32 ; <ptr> [#uses=2]
+ %retval = alloca i32, align 4 ; <ptr> [#uses=1]
+ store i32 %i, ptr %i_addr
+ store i32 %q, ptr %q_addr
+ %tmp = load i32, ptr %i_addr ; <i32> [#uses=1]
%tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1]
%tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1]
%toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1]
@@ -37,7 +37,7 @@ entry:
cond_true: ; preds = %entry
%tmp3 = call i32 (...) @bar( ) ; <i32> [#uses=0]
%tmp4 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
- %tmp7 = load i32, i32* %q_addr ; <i32> [#uses=1]
+ %tmp7 = load i32, ptr %q_addr ; <i32> [#uses=1]
%tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1]
%tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1]
%toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1]
@@ -46,7 +46,7 @@ cond_true: ; preds = %entry
cond_false: ; preds = %entry
%tmp5 = call i32 (...) @foo( ) ; <i32> [#uses=0]
%tmp6 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
- %tmp27 = load i32, i32* %q_addr ; <i32> [#uses=1]
+ %tmp27 = load i32, ptr %q_addr ; <i32> [#uses=1]
%tmp28 = icmp ne i32 %tmp27, 0 ; <i1> [#uses=1]
%tmp289 = zext i1 %tmp28 to i8 ; <i8> [#uses=1]
%toBool210 = icmp ne i8 %tmp289, 0 ; <i1> [#uses=1]
@@ -67,7 +67,7 @@ cond_next18: ; preds = %cond_false15, %cond_true11
br label %return
return: ; preds = %cond_next18
- %retval20 = load i32, i32* %retval ; <i32> [#uses=1]
+ %retval20 = load i32, ptr %retval ; <i32> [#uses=1]
ret i32 %retval20
}
diff --git a/llvm/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll b/llvm/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll
index e0b28e874b900..0b5f2cd39dae7 100644
--- a/llvm/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll
+++ b/llvm/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll
@@ -1,15 +1,15 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
- %struct.shape_edge_t = type { %struct.shape_edge_t*, %struct.shape_edge_t*, i32, i32, i32, i32 }
- %struct.shape_path_t = type { %struct.shape_edge_t*, %struct.shape_edge_t*, i32, i32, i32, i32, i32, i32 }
- %struct.shape_pool_t = type { i8* (%struct.shape_pool_t*, i8*, i32)*, i8* (%struct.shape_pool_t*, i32)*, void (%struct.shape_pool_t*, i8*)* }
+ %struct.shape_edge_t = type { ptr, ptr, i32, i32, i32, i32 }
+ %struct.shape_path_t = type { ptr, ptr, i32, i32, i32, i32, i32, i32 }
+ %struct.shape_pool_t = type { ptr, ptr, ptr }
-define %struct.shape_path_t* @shape_path_alloc(%struct.shape_pool_t* %pool, i32* %shape) {
+define ptr @shape_path_alloc(ptr %pool, ptr %shape) {
entry:
br i1 false, label %cond_false, label %bb45
bb45: ; preds = %entry
- ret %struct.shape_path_t* null
+ ret ptr null
cond_false: ; preds = %entry
br i1 false, label %bb140, label %bb174
@@ -17,12 +17,12 @@ cond_false: ; preds = %entry
bb140: ; preds = %bb140, %cond_false
%indvar = phi i32 [ 0, %cond_false ], [ %indvar.next, %bb140 ] ; <i32> [#uses=2]
%edge.230.0.rec = shl i32 %indvar, 1 ; <i32> [#uses=3]
- %edge.230.0 = getelementptr %struct.shape_edge_t, %struct.shape_edge_t* null, i32 %edge.230.0.rec ; <%struct.shape_edge_t*> [#uses=1]
+ %edge.230.0 = getelementptr %struct.shape_edge_t, ptr null, i32 %edge.230.0.rec ; <ptr> [#uses=1]
%edge.230.0.sum6970 = or i32 %edge.230.0.rec, 1 ; <i32> [#uses=2]
- %tmp154 = getelementptr %struct.shape_edge_t, %struct.shape_edge_t* null, i32 %edge.230.0.sum6970 ; <%struct.shape_edge_t*> [#uses=1]
- %tmp11.i5 = getelementptr %struct.shape_edge_t, %struct.shape_edge_t* null, i32 %edge.230.0.sum6970, i32 0 ; <%struct.shape_edge_t**> [#uses=1]
- store %struct.shape_edge_t* %edge.230.0, %struct.shape_edge_t** %tmp11.i5
- store %struct.shape_edge_t* %tmp154, %struct.shape_edge_t** null
+ %tmp154 = getelementptr %struct.shape_edge_t, ptr null, i32 %edge.230.0.sum6970 ; <ptr> [#uses=1]
+ %tmp11.i5 = getelementptr %struct.shape_edge_t, ptr null, i32 %edge.230.0.sum6970, i32 0 ; <ptr> [#uses=1]
+ store ptr %edge.230.0, ptr %tmp11.i5
+ store ptr %tmp154, ptr null
%tmp16254.0.rec = add i32 %edge.230.0.rec, 2 ; <i32> [#uses=1]
%xp.350.sum = add i32 0, %tmp16254.0.rec ; <i32> [#uses=1]
%tmp168 = icmp slt i32 %xp.350.sum, 0 ; <i1> [#uses=1]
@@ -30,7 +30,7 @@ bb140: ; preds = %bb140, %cond_false
br i1 %tmp168, label %bb140, label %bb174
bb174: ; preds = %bb140, %cond_false
- ret %struct.shape_path_t* null
+ ret ptr null
}
; CHECK-NOT: str{{.*}}!
diff --git a/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll b/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll
index 76b6221d02229..547bb72d91cc0 100644
--- a/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll
+++ b/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll
@@ -1,14 +1,14 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -mattr=+v6
; PR1609
- %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.FILE = type { ptr, i32, i32, i16, i16, %struct.__sbuf, i32, ptr, ptr, ptr, ptr, ptr, %struct.__sbuf, ptr, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
%struct.__sFILEX = type opaque
- %struct.__sbuf = type { i8*, i32 }
- at _C_nextcmd = external global i32 ; <i32*> [#uses=2]
- at _C_cmds = external global [100 x i8*] ; <[100 x i8*]*> [#uses=2]
- at .str44 = external constant [2 x i8] ; <[2 x i8]*> [#uses=1]
+ %struct.__sbuf = type { ptr, i32 }
+ at _C_nextcmd = external global i32 ; <ptr> [#uses=2]
+ at _C_cmds = external global [100 x ptr] ; <ptr> [#uses=2]
+ at .str44 = external constant [2 x i8] ; <ptr> [#uses=1]
-define i32 @main(i32 %argc, i8** %argv) {
+define i32 @main(i32 %argc, ptr %argv) {
entry:
br label %cond_next212.i
@@ -44,27 +44,27 @@ bb102.i: ; preds = %cond_next212.i
br i1 false, label %cond_true110.i, label %cond_next123.i
cond_true110.i: ; preds = %bb102.i
- %tmp116.i = getelementptr i8*, i8** %argv_addr.2321.0.i, i32 2 ; <i8**> [#uses=1]
- %tmp117.i = load i8*, i8** %tmp116.i ; <i8*> [#uses=1]
- %tmp126425.i = call %struct.FILE* @fopen( i8* %tmp117.i, i8* getelementptr ([2 x i8], [2 x i8]* @.str44, i32 0, i32 0) ) ; <%struct.FILE*> [#uses=0]
+ %tmp116.i = getelementptr ptr, ptr %argv_addr.2321.0.i, i32 2 ; <ptr> [#uses=1]
+ %tmp117.i = load ptr, ptr %tmp116.i ; <ptr> [#uses=1]
+ %tmp126425.i = call ptr @fopen( ptr %tmp117.i, ptr @.str44 ) ; <ptr> [#uses=0]
ret i32 0
cond_next123.i: ; preds = %bb102.i
- %tmp122.i = getelementptr i8, i8* %tmp215.i, i32 2 ; <i8*> [#uses=0]
+ %tmp122.i = getelementptr i8, ptr %tmp215.i, i32 2 ; <ptr> [#uses=0]
ret i32 0
bb162.i: ; preds = %cond_next212.i
ret i32 0
C_addcmd.exit120.i: ; preds = %cond_next212.i
- %tmp3.i.i.i.i105.i = call i8* @calloc( i32 15, i32 1 ) ; <i8*> [#uses=1]
- %tmp1.i108.i = getelementptr [100 x i8*], [100 x i8*]* @_C_cmds, i32 0, i32 0 ; <i8**> [#uses=1]
- store i8* %tmp3.i.i.i.i105.i, i8** %tmp1.i108.i, align 4
- %tmp.i91.i = load i32, i32* @_C_nextcmd, align 4 ; <i32> [#uses=1]
- store i32 0, i32* @_C_nextcmd, align 4
- %tmp3.i.i.i.i95.i = call i8* @calloc( i32 15, i32 1 ) ; <i8*> [#uses=1]
- %tmp1.i98.i = getelementptr [100 x i8*], [100 x i8*]* @_C_cmds, i32 0, i32 %tmp.i91.i ; <i8**> [#uses=1]
- store i8* %tmp3.i.i.i.i95.i, i8** %tmp1.i98.i, align 4
+ %tmp3.i.i.i.i105.i = call ptr @calloc( i32 15, i32 1 ) ; <ptr> [#uses=1]
+ %tmp1.i108.i = getelementptr [100 x ptr], ptr @_C_cmds, i32 0, i32 0 ; <ptr> [#uses=1]
+ store ptr %tmp3.i.i.i.i105.i, ptr %tmp1.i108.i, align 4
+ %tmp.i91.i = load i32, ptr @_C_nextcmd, align 4 ; <i32> [#uses=1]
+ store i32 0, ptr @_C_nextcmd, align 4
+ %tmp3.i.i.i.i95.i = call ptr @calloc( i32 15, i32 1 ) ; <ptr> [#uses=1]
+ %tmp1.i98.i = getelementptr [100 x ptr], ptr @_C_cmds, i32 0, i32 %tmp.i91.i ; <ptr> [#uses=1]
+ store ptr %tmp3.i.i.i.i95.i, ptr %tmp1.i98.i, align 4
br label %cond_next212.i
bb174.i: ; preds = %cond_next212.i
@@ -75,10 +75,10 @@ bb192.i: ; preds = %cond_next212.i
cond_next212.i: ; preds = %cond_next212.i, %cond_next212.i, %cond_next212.i, %cond_next212.i, %bb192.i, %C_addcmd.exit120.i, %bb30.i, %bb21.i, %entry
%max_d.3 = phi i32 [ -1, %entry ], [ %max_d.3, %bb30.i ], [ %max_d.3, %bb21.i ], [ %max_d.3, %C_addcmd.exit120.i ], [ 0, %bb192.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ] ; <i32> [#uses=7]
- %argv_addr.2321.0.i = phi i8** [ %argv, %entry ], [ %tmp214.i, %bb192.i ], [ %tmp214.i, %C_addcmd.exit120.i ], [ %tmp214.i, %bb30.i ], [ %tmp214.i, %bb21.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ] ; <i8**> [#uses=2]
+ %argv_addr.2321.0.i = phi ptr [ %argv, %entry ], [ %tmp214.i, %bb192.i ], [ %tmp214.i, %C_addcmd.exit120.i ], [ %tmp214.i, %bb30.i ], [ %tmp214.i, %bb21.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ] ; <ptr> [#uses=2]
%argc_addr.2358.0.i = phi i32 [ %argc, %entry ], [ %tmp205399.i, %bb30.i ], [ 0, %bb21.i ], [ 0, %C_addcmd.exit120.i ], [ 0, %bb192.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ] ; <i32> [#uses=1]
- %tmp214.i = getelementptr i8*, i8** %argv_addr.2321.0.i, i32 1 ; <i8**> [#uses=9]
- %tmp215.i = load i8*, i8** %tmp214.i ; <i8*> [#uses=1]
+ %tmp214.i = getelementptr ptr, ptr %argv_addr.2321.0.i, i32 1 ; <ptr> [#uses=9]
+ %tmp215.i = load ptr, ptr %tmp214.i ; <ptr> [#uses=1]
%tmp1314.i = sext i8 0 to i32 ; <i32> [#uses=1]
switch i32 %tmp1314.i, label %bb192.i [
i32 76, label %C_addcmd.exit120.i
@@ -101,6 +101,6 @@ cond_next212.i: ; preds = %cond_next212.i, %cond_next212.i, %cond_next212.i, %c
]
}
-declare %struct.FILE* @fopen(i8*, i8*)
+declare ptr @fopen(ptr, ptr)
-declare i8* @calloc(i32, i32)
+declare ptr @calloc(i32, i32)
diff --git a/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll b/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll
index 989410552f3f0..4d9b7c6891d72 100644
--- a/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll
+++ b/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll
@@ -1,19 +1,19 @@
; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=fast -optimize-regalloc=0
; PR1925
- %struct.encode_aux_nearestmatch = type { i32*, i32*, i32*, i32*, i32, i32 }
- %struct.encode_aux_pigeonhole = type { float, float, i32, i32, i32*, i32, i32*, i32*, i32* }
- %struct.encode_aux_threshmatch = type { float*, i32*, i32, i32 }
- %struct.oggpack_buffer = type { i32, i32, i8*, i8*, i32 }
- %struct.static_codebook = type { i32, i32, i32*, i32, i32, i32, i32, i32, i32*, %struct.encode_aux_nearestmatch*, %struct.encode_aux_threshmatch*, %struct.encode_aux_pigeonhole*, i32 }
+ %struct.encode_aux_nearestmatch = type { ptr, ptr, ptr, ptr, i32, i32 }
+ %struct.encode_aux_pigeonhole = type { float, float, i32, i32, ptr, i32, ptr, ptr, ptr }
+ %struct.encode_aux_threshmatch = type { ptr, ptr, i32, i32 }
+ %struct.oggpack_buffer = type { i32, i32, ptr, ptr, i32 }
+ %struct.static_codebook = type { i32, i32, ptr, i32, i32, i32, i32, i32, ptr, ptr, ptr, ptr, i32 }
-define i32 @vorbis_staticbook_pack(%struct.static_codebook* %c, %struct.oggpack_buffer* %opb) {
+define i32 @vorbis_staticbook_pack(ptr %c, ptr %opb) {
entry:
- %opb_addr = alloca %struct.oggpack_buffer* ; <%struct.oggpack_buffer**> [#uses=1]
- %tmp1 = load %struct.oggpack_buffer*, %struct.oggpack_buffer** %opb_addr, align 4 ; <%struct.oggpack_buffer*> [#uses=1]
- call void @oggpack_write( %struct.oggpack_buffer* %tmp1, i32 5653314, i32 24 ) nounwind
- call void @oggpack_write( %struct.oggpack_buffer* null, i32 0, i32 24 ) nounwind
+ %opb_addr = alloca ptr ; <ptr> [#uses=1]
+ %tmp1 = load ptr, ptr %opb_addr, align 4 ; <ptr> [#uses=1]
+ call void @oggpack_write( ptr %tmp1, i32 5653314, i32 24 ) nounwind
+ call void @oggpack_write( ptr null, i32 0, i32 24 ) nounwind
unreachable
}
-declare void @oggpack_write(%struct.oggpack_buffer*, i32, i32)
+declare void @oggpack_write(ptr, i32, i32)
diff --git a/llvm/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll b/llvm/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll
index 03b473a4658a6..d22a3e53b3c89 100644
--- a/llvm/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll
+++ b/llvm/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll
@@ -2,20 +2,20 @@
; PR1925
%"struct.kc::impl_Ccode_option" = type { %"struct.kc::impl_abstract_phylum" }
- %"struct.kc::impl_ID" = type { %"struct.kc::impl_abstract_phylum", %"struct.kc::impl_Ccode_option"*, %"struct.kc::impl_casestring__Str"*, i32, %"struct.kc::impl_casestring__Str"* }
- %"struct.kc::impl_abstract_phylum" = type { i32 (...)** }
- %"struct.kc::impl_casestring__Str" = type { %"struct.kc::impl_abstract_phylum", i8* }
+ %"struct.kc::impl_ID" = type { %"struct.kc::impl_abstract_phylum", ptr, ptr, i32, ptr }
+ %"struct.kc::impl_abstract_phylum" = type { ptr }
+ %"struct.kc::impl_casestring__Str" = type { %"struct.kc::impl_abstract_phylum", ptr }
-define %"struct.kc::impl_ID"* @_ZN2kc18f_typeofunpsubtermEPNS_15impl_unpsubtermEPNS_7impl_IDE(%"struct.kc::impl_Ccode_option"* %a_unpsubterm, %"struct.kc::impl_ID"* %a_operator) {
+define ptr @_ZN2kc18f_typeofunpsubtermEPNS_15impl_unpsubtermEPNS_7impl_IDE(ptr %a_unpsubterm, ptr %a_operator) {
entry:
- %tmp8 = getelementptr %"struct.kc::impl_Ccode_option", %"struct.kc::impl_Ccode_option"* %a_unpsubterm, i32 0, i32 0, i32 0 ; <i32 (...)***> [#uses=0]
+ %tmp8 = getelementptr %"struct.kc::impl_Ccode_option", ptr %a_unpsubterm, i32 0, i32 0, i32 0 ; <ptr> [#uses=0]
br i1 false, label %bb41, label %bb55
bb41: ; preds = %entry
- ret %"struct.kc::impl_ID"* null
+ ret ptr null
bb55: ; preds = %entry
- %tmp67 = tail call i32 null( %"struct.kc::impl_abstract_phylum"* null ) ; <i32> [#uses=0]
- %tmp97 = tail call i32 null( %"struct.kc::impl_abstract_phylum"* null ) ; <i32> [#uses=0]
- ret %"struct.kc::impl_ID"* null
+ %tmp67 = tail call i32 null( ptr null ) ; <i32> [#uses=0]
+ %tmp97 = tail call i32 null( ptr null ) ; <i32> [#uses=0]
+ ret ptr null
}
diff --git a/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll b/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll
index b0a50a49a76d3..04f4e6945c0df 100644
--- a/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll
+++ b/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll
@@ -1,10 +1,10 @@
; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s
-define i32 @main(i32 %argc, i8** %argv) {
+define i32 @main(i32 %argc, ptr %argv) {
entry:
br label %bb1
bb1: ; preds = %entry
- %tmp3.i.i = load i8, i8* null, align 1 ; <i8> [#uses=1]
+ %tmp3.i.i = load i8, ptr null, align 1 ; <i8> [#uses=1]
%tmp4.i.i = icmp slt i8 %tmp3.i.i, 0 ; <i1> [#uses=1]
br i1 %tmp4.i.i, label %bb2, label %bb3
bb2: ; preds = %bb1
diff --git a/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll
index 753f9e3d1331c..80812a395995c 100644
--- a/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll
+++ b/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2
- at accum = external global { double, double } ; <{ double, double }*> [#uses=1]
- at .str = external constant [4 x i8] ; <[4 x i8]*> [#uses=1]
+ at accum = external global { double, double } ; <ptr> [#uses=1]
+ at .str = external constant [4 x i8] ; <ptr> [#uses=1]
define i32 @main() {
entry:
@@ -11,10 +11,10 @@ bb74.i: ; preds = %bb88.i, %bb74.i, %entry
bb88.i: ; preds = %bb74.i
br i1 false, label %mandel.exit, label %bb74.i
mandel.exit: ; preds = %bb88.i
- %tmp2 = load volatile double, double* getelementptr ({ double, double }, { double, double }* @accum, i32 0, i32 0), align 8 ; <double> [#uses=1]
+ %tmp2 = load volatile double, ptr getelementptr ({ double, double }, ptr @accum, i32 0, i32 0), align 8 ; <double> [#uses=1]
%tmp23 = fptosi double %tmp2 to i32 ; <i32> [#uses=1]
- %tmp5 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %tmp23 ) ; <i32> [#uses=0]
+ %tmp5 = tail call i32 (ptr, ...) @printf( ptr @.str, i32 %tmp23 ) ; <i32> [#uses=0]
ret i32 0
}
-declare i32 @printf(i8*, ...)
+declare i32 @printf(ptr, ...)
diff --git a/llvm/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll
index 4b1aa19ef0673..02e1cee13448e 100644
--- a/llvm/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll
+++ b/llvm/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll
@@ -1,10 +1,10 @@
; RUN: llc < %s -mtriple=arm-apple-darwin
- at numBinsY = external global i32 ; <i32*> [#uses=1]
+ at numBinsY = external global i32 ; <ptr> [#uses=1]
declare double @pow(double, double)
-define void @main(i32 %argc, i8** %argv) noreturn nounwind {
+define void @main(i32 %argc, ptr %argv) noreturn nounwind {
entry:
br i1 false, label %bb34.outer.i.i.i, label %cond_false674
bb34.outer.i.i.i: ; preds = %entry
@@ -25,18 +25,18 @@ bb248.i.i.i: ; preds = %bb220.i.i.i
cond_false256.i.i.i: ; preds = %bb248.i.i.i
ret void
bb300.i.i.i: ; preds = %bb248.i.i.i
- store i32 undef, i32* @numBinsY, align 4
+ store i32 undef, ptr @numBinsY, align 4
ret void
cond_false674: ; preds = %entry
ret void
}
- %struct.anon = type { %struct.rnode*, %struct.rnode* }
- %struct.ch_set = type { { i8, i8 }*, %struct.ch_set* }
- %struct.pat_list = type { i32, %struct.pat_list* }
- %struct.rnode = type { i16, { %struct.anon }, i16, %struct.pat_list*, %struct.pat_list* }
+ %struct.anon = type { ptr, ptr }
+ %struct.ch_set = type { ptr, ptr }
+ %struct.pat_list = type { i32, ptr }
+ %struct.rnode = type { i16, { %struct.anon }, i16, ptr, ptr }
-define fastcc { i16, %struct.rnode* }* @get_token(i8** %s) nounwind {
+define fastcc ptr @get_token(ptr %s) nounwind {
entry:
br i1 false, label %bb42, label %bb78
bb42: ; preds = %entry
@@ -44,20 +44,19 @@ bb42: ; preds = %entry
bb17.i: ; preds = %cond_next119.i
br i1 false, label %cond_true53.i, label %cond_false99.i
cond_true53.i: ; preds = %bb17.i
- ret { i16, %struct.rnode* }* null
+ ret ptr null
cond_false99.i: ; preds = %bb17.i
- %malloccall = tail call i8* @malloc(i32 trunc (i64 mul nuw (i64 ptrtoint (i1** getelementptr (i1*, i1** null, i32 1) to i64), i64 2) to i32))
- %tmp106.i = bitcast i8* %malloccall to %struct.ch_set*
+ %malloccall = tail call ptr @malloc(i32 trunc (i64 mul nuw (i64 ptrtoint (ptr getelementptr (ptr, ptr null, i32 1) to i64), i64 2) to i32))
br i1 false, label %bb126.i, label %cond_next119.i
cond_next119.i: ; preds = %cond_false99.i, %bb42
- %curr_ptr.0.reg2mem.0.i = phi %struct.ch_set* [ %tmp106.i, %cond_false99.i ], [ null, %bb42 ] ; <%struct.ch_set*> [#uses=2]
- %prev_ptr.0.reg2mem.0.i = phi %struct.ch_set* [ %curr_ptr.0.reg2mem.0.i, %cond_false99.i ], [ undef, %bb42 ] ; <%struct.ch_set*> [#uses=1]
+ %curr_ptr.0.reg2mem.0.i = phi ptr [ %malloccall, %cond_false99.i ], [ null, %bb42 ] ; <ptr> [#uses=2]
+ %prev_ptr.0.reg2mem.0.i = phi ptr [ %curr_ptr.0.reg2mem.0.i, %cond_false99.i ], [ undef, %bb42 ] ; <ptr> [#uses=1]
br i1 false, label %bb126.i, label %bb17.i
bb126.i: ; preds = %cond_next119.i, %cond_false99.i
- %prev_ptr.0.reg2mem.1.i = phi %struct.ch_set* [ %prev_ptr.0.reg2mem.0.i, %cond_next119.i ], [ %curr_ptr.0.reg2mem.0.i, %cond_false99.i ] ; <%struct.ch_set*> [#uses=0]
- ret { i16, %struct.rnode* }* null
+ %prev_ptr.0.reg2mem.1.i = phi ptr [ %prev_ptr.0.reg2mem.0.i, %cond_next119.i ], [ %curr_ptr.0.reg2mem.0.i, %cond_false99.i ] ; <ptr> [#uses=0]
+ ret ptr null
bb78: ; preds = %entry
- ret { i16, %struct.rnode* }* null
+ ret ptr null
}
-declare noalias i8* @malloc(i32)
+declare noalias ptr @malloc(i32)
diff --git a/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll
index 1ededa3c38773..9c87fa2563a09 100644
--- a/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll
+++ b/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll
@@ -1,30 +1,30 @@
; RUN: llc < %s -mtriple=arm-apple-darwin
%struct.CONTENTBOX = type { i32, i32, i32, i32, i32 }
- %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.FILE = type { ptr, i32, i32, i16, i16, %struct.__sbuf, i32, ptr, ptr, ptr, ptr, ptr, %struct.__sbuf, ptr, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
%struct.LOCBOX = type { i32, i32, i32, i32 }
%struct.SIDEBOX = type { i32, i32 }
%struct.UNCOMBOX = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.__sFILEX = type opaque
- %struct.__sbuf = type { i8*, i32 }
- %struct.cellbox = type { i8*, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, double, double, double, double, double, i32, i32, %struct.CONTENTBOX*, %struct.UNCOMBOX*, [8 x %struct.tilebox*], %struct.SIDEBOX* }
- %struct.termbox = type { %struct.termbox*, i32, i32, i32, i32, i32 }
- %struct.tilebox = type { %struct.tilebox*, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.termbox*, %struct.LOCBOX* }
- at .str127 = external constant [2 x i8] ; <[2 x i8]*> [#uses=1]
- at .str584 = external constant [5 x i8] ; <[5 x i8]*> [#uses=1]
- at .str8115 = external constant [9 x i8] ; <[9 x i8]*> [#uses=1]
+ %struct.__sbuf = type { ptr, i32 }
+ %struct.cellbox = type { ptr, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, double, double, double, double, double, i32, i32, ptr, ptr, [8 x ptr], ptr }
+ %struct.termbox = type { ptr, i32, i32, i32, i32, i32 }
+ %struct.tilebox = type { ptr, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, ptr }
+ at .str127 = external constant [2 x i8] ; <ptr> [#uses=1]
+ at .str584 = external constant [5 x i8] ; <ptr> [#uses=1]
+ at .str8115 = external constant [9 x i8] ; <ptr> [#uses=1]
-declare %struct.FILE* @fopen(i8*, i8*)
+declare ptr @fopen(ptr, ptr)
-declare i32 @strcmp(i8*, i8*)
+declare i32 @strcmp(ptr, ptr)
-declare i32 @fscanf(%struct.FILE*, i8*, ...)
+declare i32 @fscanf(ptr, ptr, ...)
-define void @main(i32 %argc, i8** %argv) noreturn {
+define void @main(i32 %argc, ptr %argv) noreturn {
entry:
br i1 false, label %cond_next48, label %cond_false674
cond_next48: ; preds = %entry
- %tmp61 = call %struct.FILE* @fopen( i8* null, i8* getelementptr ([2 x i8], [2 x i8]* @.str127, i32 0, i32 0) ) ; <%struct.FILE*> [#uses=2]
+ %tmp61 = call ptr @fopen( ptr null, ptr @.str127 ) ; <ptr> [#uses=2]
br i1 false, label %bb220.i.i.i, label %bb62.preheader.i.i.i
bb62.preheader.i.i.i: ; preds = %cond_next48
ret void
@@ -53,11 +53,11 @@ bb177.i393.i: ; preds = %bb40.i.i
bb192.i.i: ; preds = %bb177.i393.i
ret void
cond_false373.i.i: ; preds = %bb.i350.i
- %tmp376.i.i = call i32 @strcmp( i8* null, i8* getelementptr ([9 x i8], [9 x i8]* @.str8115, i32 0, i32 0) ) ; <i32> [#uses=0]
+ %tmp376.i.i = call i32 @strcmp( ptr null, ptr @.str8115 ) ; <i32> [#uses=0]
br i1 false, label %cond_true380.i.i, label %cond_next602.i.i
cond_true380.i.i: ; preds = %cond_false373.i.i
%tmp394.i418.i = add i32 %cell.0.i.i, 1 ; <i32> [#uses=1]
- %tmp397.i420.i = load %struct.cellbox*, %struct.cellbox** null, align 4 ; <%struct.cellbox*> [#uses=1]
+ %tmp397.i420.i = load ptr, ptr null, align 4 ; <ptr> [#uses=1]
br label %bb398.i.i
bb398.i.i: ; preds = %bb398.i.i, %cond_true380.i.i
br i1 false, label %bb414.i.i, label %bb398.i.i
@@ -73,10 +73,10 @@ bb609.i.i: ; preds = %cond_next602.i.i
br label %bb620.i.i
bb620.i.i: ; preds = %bb620.i.i, %bb609.i.i
%indvar166.i465.i = phi i32 [ %indvar.next167.i.i, %bb620.i.i ], [ 0, %bb609.i.i ] ; <i32> [#uses=1]
- %tmp640.i.i = call i32 (%struct.FILE*, i8*, ...) @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8], [5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; <i32> [#uses=0]
- %tmp648.i.i = load i32, i32* null, align 4 ; <i32> [#uses=1]
+ %tmp640.i.i = call i32 (ptr, ptr, ...) @fscanf( ptr %tmp61, ptr @.str584, ptr null ) ; <i32> [#uses=0]
+ %tmp648.i.i = load i32, ptr null, align 4 ; <i32> [#uses=1]
%tmp650.i468.i = icmp sgt i32 0, %tmp648.i.i ; <i1> [#uses=1]
- %tmp624.i469.i = call i32 (%struct.FILE*, i8*, ...) @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8], [5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; <i32> [#uses=0]
+ %tmp624.i469.i = call i32 (ptr, ptr, ...) @fscanf( ptr %tmp61, ptr @.str584, ptr null ) ; <i32> [#uses=0]
%indvar.next167.i.i = add i32 %indvar166.i465.i, 1 ; <i32> [#uses=1]
br i1 %tmp650.i468.i, label %bb653.i.i.loopexit, label %bb620.i.i
bb653.i.i.loopexit: ; preds = %bb620.i.i
@@ -90,7 +90,7 @@ bb894.i.i: ; preds = %bb894.loopexit.i.i, %bb653.i.i.loopexit, %bb581.i.i, %bb1
%pinctr.0.i.i = phi i32 [ 0, %bb894.loopexit.i.i ], [ %tmp642.i466.i, %bb653.i.i.loopexit ], [ %pinctr.0.i.i, %bb177.i393.i ], [ %pinctr.0.i.i, %bb581.i.i ] ; <i32> [#uses=2]
%soft.0.i.i = phi i32 [ undef, %bb894.loopexit.i.i ], [ %soft.0.i.i, %bb653.i.i.loopexit ], [ 0, %bb177.i393.i ], [ 1, %bb581.i.i ] ; <i32> [#uses=1]
%cell.0.i.i = phi i32 [ 0, %bb894.loopexit.i.i ], [ %cell.0.i.i, %bb653.i.i.loopexit ], [ 0, %bb177.i393.i ], [ %tmp394.i418.i, %bb581.i.i ] ; <i32> [#uses=2]
- %ptr.0.i.i = phi %struct.cellbox* [ undef, %bb894.loopexit.i.i ], [ %ptr.0.i.i, %bb653.i.i.loopexit ], [ null, %bb177.i393.i ], [ %tmp397.i420.i, %bb581.i.i ] ; <%struct.cellbox*> [#uses=1]
+ %ptr.0.i.i = phi ptr [ undef, %bb894.loopexit.i.i ], [ %ptr.0.i.i, %bb653.i.i.loopexit ], [ null, %bb177.i393.i ], [ %tmp397.i420.i, %bb581.i.i ] ; <ptr> [#uses=1]
br i1 false, label %bb.i350.i, label %bb902.i502.i
bb902.i502.i: ; preds = %bb894.i.i
ret void
@@ -100,15 +100,15 @@ cond_false674: ; preds = %entry
%struct.III_psy_xmin = type { [22 x double], [13 x [3 x double]] }
%struct.III_scalefac_t = type { [22 x i32], [13 x [3 x i32]] }
- %struct.gr_info = type { i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32*, [4 x i32] }
- %struct.lame_global_flags = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, float, float, float, float, i32, i32, i32, i32, i32, i32, i32, i32 }
- at scalefac_band.1 = external global [14 x i32] ; <[14 x i32]*> [#uses=2]
+ %struct.gr_info = type { i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, [4 x i32] }
+ %struct.lame_global_flags = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, ptr, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, float, float, float, float, i32, i32, i32, i32, i32, i32, i32, i32 }
+ at scalefac_band.1 = external global [14 x i32] ; <ptr> [#uses=2]
-declare fastcc i32 @init_outer_loop(%struct.lame_global_flags*, double*, %struct.gr_info*)
+declare fastcc i32 @init_outer_loop(ptr, ptr, ptr)
-define fastcc void @outer_loop(%struct.lame_global_flags* %gfp, double* %xr, i32 %targ_bits, double* %best_noise, %struct.III_psy_xmin* %l3_xmin, i32* %l3_enc, %struct.III_scalefac_t* %scalefac, %struct.gr_info* %cod_info, i32 %ch) {
+define fastcc void @outer_loop(ptr %gfp, ptr %xr, i32 %targ_bits, ptr %best_noise, ptr %l3_xmin, ptr %l3_enc, ptr %scalefac, ptr %cod_info, i32 %ch) {
entry:
- %cod_info.182 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 1 ; <i32*> [#uses=1]
+ %cod_info.182 = getelementptr %struct.gr_info, ptr %cod_info, i32 0, i32 1 ; <ptr> [#uses=1]
br label %bb
bb: ; preds = %bb226, %entry
%save_cod_info.1.1 = phi i32 [ undef, %entry ], [ %save_cod_info.1.1, %bb226 ] ; <i32> [#uses=2]
@@ -126,7 +126,7 @@ cond_true163: ; preds = %cond_next144
bb.i53: ; preds = %cond_true163
ret void
bb34.i: ; preds = %cond_true163
- %tmp37.i55 = load i32, i32* null, align 4 ; <i32> [#uses=1]
+ %tmp37.i55 = load i32, ptr null, align 4 ; <i32> [#uses=1]
br i1 false, label %bb65.preheader.i, label %bb78.i
bb65.preheader.i: ; preds = %bb34.i
br label %bb65.outer.us.i
@@ -148,16 +148,16 @@ bb226.backedge.i: ; preds = %cond_next215.i, %bb151.i
bb155.i: ; preds = %cond_next215.i, %bb151.i
%indvar90.i = phi i32 [ %indvar.next91.i, %cond_next215.i ], [ 0, %bb151.i ] ; <i32> [#uses=2]
%sfb.3.reg2mem.0.i = add i32 %indvar90.i, %tmp37.i55 ; <i32> [#uses=4]
- %tmp161.i = getelementptr [4 x [21 x double]], [4 x [21 x double]]* null, i32 0, i32 %tmp15747.i, i32 %sfb.3.reg2mem.0.i ; <double*> [#uses=1]
- %tmp162.i74 = load double, double* %tmp161.i, align 4 ; <double> [#uses=0]
+ %tmp161.i = getelementptr [4 x [21 x double]], ptr null, i32 0, i32 %tmp15747.i, i32 %sfb.3.reg2mem.0.i ; <ptr> [#uses=1]
+ %tmp162.i74 = load double, ptr %tmp161.i, align 4 ; <double> [#uses=0]
br i1 false, label %cond_true167.i, label %cond_next215.i
cond_true167.i: ; preds = %bb155.i
- %tmp173.i = getelementptr %struct.III_scalefac_t, %struct.III_scalefac_t* null, i32 0, i32 1, i32 %sfb.3.reg2mem.0.i, i32 %i.154.i ; <i32*> [#uses=1]
- store i32 0, i32* %tmp173.i, align 4
- %tmp182.1.i = getelementptr [14 x i32], [14 x i32]* @scalefac_band.1, i32 0, i32 %sfb.3.reg2mem.0.i ; <i32*> [#uses=0]
+ %tmp173.i = getelementptr %struct.III_scalefac_t, ptr null, i32 0, i32 1, i32 %sfb.3.reg2mem.0.i, i32 %i.154.i ; <ptr> [#uses=1]
+ store i32 0, ptr %tmp173.i, align 4
+ %tmp182.1.i = getelementptr [14 x i32], ptr @scalefac_band.1, i32 0, i32 %sfb.3.reg2mem.0.i ; <ptr> [#uses=0]
%tmp185.i78 = add i32 %sfb.3.reg2mem.0.i, 1 ; <i32> [#uses=1]
- %tmp187.1.i = getelementptr [14 x i32], [14 x i32]* @scalefac_band.1, i32 0, i32 %tmp185.i78 ; <i32*> [#uses=1]
- %tmp188.i = load i32, i32* %tmp187.1.i, align 4 ; <i32> [#uses=1]
+ %tmp187.1.i = getelementptr [14 x i32], ptr @scalefac_band.1, i32 0, i32 %tmp185.i78 ; <ptr> [#uses=1]
+ %tmp188.i = load i32, ptr %tmp187.1.i, align 4 ; <i32> [#uses=1]
%tmp21153.i = icmp slt i32 0, %tmp188.i ; <i1> [#uses=1]
br i1 %tmp21153.i, label %bb190.preheader.i, label %cond_next215.i
bb190.preheader.i: ; preds = %cond_true167.i
@@ -179,23 +179,23 @@ cond_next205: ; preds = %bb19.i, %cond_next144
cond_true210: ; preds = %cond_next205
br i1 false, label %bb226, label %cond_true217
cond_true217: ; preds = %cond_true210
- %tmp221 = call fastcc i32 @init_outer_loop( %struct.lame_global_flags* %gfp, double* %xr, %struct.gr_info* %cod_info ) ; <i32> [#uses=0]
+ %tmp221 = call fastcc i32 @init_outer_loop( ptr %gfp, ptr %xr, ptr %cod_info ) ; <i32> [#uses=0]
ret void
bb226: ; preds = %cond_true210, %cond_next205
br i1 false, label %bb231, label %bb
bb231: ; preds = %bb226
- store i32 %save_cod_info.1.1, i32* %cod_info.182
+ store i32 %save_cod_info.1.1, ptr %cod_info.182
ret void
}
-define fastcc void @outer_loop2(%struct.lame_global_flags* %gfp, double* %xr, i32 %targ_bits, double* %best_noise, %struct.III_psy_xmin* %l3_xmin, i32* %l3_enc, %struct.III_scalefac_t* %scalefac, %struct.gr_info* %cod_info, i32 %ch) {
+define fastcc void @outer_loop2(ptr %gfp, ptr %xr, i32 %targ_bits, ptr %best_noise, ptr %l3_xmin, ptr %l3_enc, ptr %scalefac, ptr %cod_info, i32 %ch) {
entry:
- %cod_info.20128.1 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 20, i32 1 ; <i32*> [#uses=1]
- %cod_info.20128.2 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 20, i32 2 ; <i32*> [#uses=1]
- %cod_info.20128.3 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 20, i32 3 ; <i32*> [#uses=1]
+ %cod_info.20128.1 = getelementptr %struct.gr_info, ptr %cod_info, i32 0, i32 20, i32 1 ; <ptr> [#uses=1]
+ %cod_info.20128.2 = getelementptr %struct.gr_info, ptr %cod_info, i32 0, i32 20, i32 2 ; <ptr> [#uses=1]
+ %cod_info.20128.3 = getelementptr %struct.gr_info, ptr %cod_info, i32 0, i32 20, i32 3 ; <ptr> [#uses=1]
br label %bb
bb: ; preds = %bb226, %entry
- %save_cod_info.19.1 = phi i32* [ undef, %entry ], [ %save_cod_info.19.0, %bb226 ] ; <i32*> [#uses=1]
+ %save_cod_info.19.1 = phi ptr [ undef, %entry ], [ %save_cod_info.19.0, %bb226 ] ; <ptr> [#uses=1]
%save_cod_info.0.1 = phi i32 [ undef, %entry ], [ %save_cod_info.0.0, %bb226 ] ; <i32> [#uses=1]
br i1 false, label %cond_next144, label %cond_false
cond_false: ; preds = %bb
@@ -215,7 +215,7 @@ cond_next104: ; preds = %inner_loop.exit
cond_false110: ; preds = %cond_next104
ret void
cond_next144: ; preds = %cond_next104, %bb
- %save_cod_info.19.0 = phi i32* [ %save_cod_info.19.1, %bb ], [ null, %cond_next104 ] ; <i32*> [#uses=1]
+ %save_cod_info.19.0 = phi ptr [ %save_cod_info.19.1, %bb ], [ null, %cond_next104 ] ; <ptr> [#uses=1]
%save_cod_info.4.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1]
%save_cod_info.3.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1]
%save_cod_info.2.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1]
@@ -224,7 +224,7 @@ cond_next144: ; preds = %cond_next104, %bb
%over.1 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1]
%best_over.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1]
%notdone.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1]
- %tmp147 = load i32, i32* null, align 4 ; <i32> [#uses=1]
+ %tmp147 = load i32, ptr null, align 4 ; <i32> [#uses=1]
%tmp148 = icmp eq i32 %tmp147, 0 ; <i1> [#uses=1]
%tmp153 = icmp eq i32 %over.1, 0 ; <i1> [#uses=1]
%bothcond = and i1 %tmp148, %tmp153 ; <i1> [#uses=1]
@@ -240,14 +240,14 @@ bb226: ; preds = %cond_next205
%tmp228 = icmp eq i32 %notdone.2, 0 ; <i1> [#uses=1]
br i1 %tmp228, label %bb231, label %bb
bb231: ; preds = %bb226
- store i32 %save_cod_info.1.0, i32* null
- store i32 %save_cod_info.2.0, i32* null
- store i32 %save_cod_info.3.0, i32* null
- store i32 %save_cod_info.4.0, i32* null
- store i32 0, i32* %cod_info.20128.1
- store i32 0, i32* %cod_info.20128.2
- store i32 0, i32* %cod_info.20128.3
+ store i32 %save_cod_info.1.0, ptr null
+ store i32 %save_cod_info.2.0, ptr null
+ store i32 %save_cod_info.3.0, ptr null
+ store i32 %save_cod_info.4.0, ptr null
+ store i32 0, ptr %cod_info.20128.1
+ store i32 0, ptr %cod_info.20128.2
+ store i32 0, ptr %cod_info.20128.3
%tmp244245 = sitofp i32 %best_over.0 to double ; <double> [#uses=1]
- store double %tmp244245, double* %best_noise, align 4
+ store double %tmp244245, ptr %best_noise, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll b/llvm/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll
index 33bd4def5b495..1eeced4ba775d 100644
--- a/llvm/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll
+++ b/llvm/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=arm-apple-darwin
-declare void @foo(i8*, i8*, i32, i32, i32, i32, i32, i32, i32)
+declare void @foo(ptr, ptr, i32, i32, i32, i32, i32, i32, i32)
define void @t() nounwind {
br label %1
@@ -29,7 +29,7 @@ bb4498.i: ; preds = %bb4411.i
]
bb4501.i: ; preds = %bb4498.i
%sfComp4077.1.reg2mem.0.i = phi i32 [ %sfComp4077.1.i, %bb4498.i ] ; <i32> [#uses=1]
- call void @foo( i8* null, i8* null, i32 %sfComp4077.1.reg2mem.0.i, i32 0, i32 8, i32 0, i32 0, i32 0, i32 0 ) nounwind
+ call void @foo( ptr null, ptr null, i32 %sfComp4077.1.reg2mem.0.i, i32 0, i32 8, i32 0, i32 0, i32 0, i32 0 ) nounwind
br i1 false, label %UnifiedReturnBlock.i, label %bb4517.i
bb4517.i: ; preds = %bb4501.i
br label %t.exit
diff --git a/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll b/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll
index 85ef8302a18ab..e90f7cf49fb95 100644
--- a/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll
+++ b/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll
@@ -1,19 +1,19 @@
; RUN: llc < %s -mtriple=arm-apple-darwin
%struct.BiContextType = type { i16, i8, i32 }
- %struct.Bitstream = type { i32, i32, i8, i32, i32, i8, i8, i32, i32, i8*, i32 }
- %struct.DataPartition = type { %struct.Bitstream*, %struct.EncodingEnvironment, %struct.EncodingEnvironment }
- %struct.DecRefPicMarking_t = type { i32, i32, i32, i32, i32, %struct.DecRefPicMarking_t* }
- %struct.EncodingEnvironment = type { i32, i32, i32, i32, i32, i8*, i32*, i32, i32 }
- %struct.ImageParameters = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8**, i8**, i32, i32***, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [9 x [16 x [16 x i16]]], [5 x [16 x [16 x i16]]], [9 x [8 x [8 x i16]]], [2 x [4 x [16 x [16 x i16]]]], [16 x [16 x i16]], [16 x [16 x i32]], i32****, i32***, i32***, i32***, i32****, i32****, %struct.Picture*, %struct.Slice*, %struct.Macroblock*, i32*, i32*, i32, i32, i32, i32, [4 x [4 x i32]], i32, i32, i32, i32, i32, double, i32, i32, i32, i32, i16******, i16******, i16******, i16******, [15 x i16], i32, i32, i32, i32, i32, i32, i32, i32, [6 x [32 x i32]], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [1 x i32], i32, i32, [2 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.DecRefPicMarking_t*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, double**, double***, i32***, double**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x [2 x i32]], [2 x i32], i32, i32, i16, i32, i32, i32, i32, i32 }
- %struct.Macroblock = type { i32, i32, i32, [2 x i32], i32, [8 x i32], %struct.Macroblock*, %struct.Macroblock*, i32, [2 x [4 x [4 x [2 x i32]]]], [16 x i8], [16 x i8], i32, i64, [4 x i32], [4 x i32], i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, double, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.Bitstream = type { i32, i32, i8, i32, i32, i8, i8, i32, i32, ptr, i32 }
+ %struct.DataPartition = type { ptr, %struct.EncodingEnvironment, %struct.EncodingEnvironment }
+ %struct.DecRefPicMarking_t = type { i32, i32, i32, i32, i32, ptr }
+ %struct.EncodingEnvironment = type { i32, i32, i32, i32, i32, ptr, ptr, i32, i32 }
+ %struct.ImageParameters = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, ptr, i32, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [9 x [16 x [16 x i16]]], [5 x [16 x [16 x i16]]], [9 x [8 x [8 x i16]]], [2 x [4 x [16 x [16 x i16]]]], [16 x [16 x i16]], [16 x [16 x i32]], ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, i32, [4 x [4 x i32]], i32, i32, i32, i32, i32, double, i32, i32, i32, i32, ptr, ptr, ptr, ptr, [15 x i16], i32, i32, i32, i32, i32, i32, i32, i32, [6 x [32 x i32]], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [1 x i32], i32, i32, [2 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, ptr, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x [2 x i32]], [2 x i32], i32, i32, i16, i32, i32, i32, i32, i32 }
+ %struct.Macroblock = type { i32, i32, i32, [2 x i32], i32, [8 x i32], ptr, ptr, i32, [2 x [4 x [4 x [2 x i32]]]], [16 x i8], [16 x i8], i32, i64, [4 x i32], [4 x i32], i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, double, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.MotionInfoContexts = type { [3 x [11 x %struct.BiContextType]], [2 x [9 x %struct.BiContextType]], [2 x [10 x %struct.BiContextType]], [2 x [6 x %struct.BiContextType]], [4 x %struct.BiContextType], [4 x %struct.BiContextType], [3 x %struct.BiContextType] }
- %struct.Picture = type { i32, i32, [100 x %struct.Slice*], i32, float, float, float }
- %struct.Slice = type { i32, i32, i32, i32, i32, i32, %struct.DataPartition*, %struct.MotionInfoContexts*, %struct.TextureInfoContexts*, i32, i32*, i32*, i32*, i32, i32*, i32*, i32*, i32 (i32)*, [3 x [2 x i32]] }
+ %struct.Picture = type { i32, i32, [100 x ptr], i32, float, float, float }
+ %struct.Slice = type { i32, i32, i32, i32, i32, i32, ptr, ptr, ptr, i32, ptr, ptr, ptr, i32, ptr, ptr, ptr, ptr, [3 x [2 x i32]] }
%struct.TextureInfoContexts = type { [2 x %struct.BiContextType], [4 x %struct.BiContextType], [3 x [4 x %struct.BiContextType]], [10 x [4 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]], [10 x [5 x %struct.BiContextType]], [10 x [5 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]] }
- at images = external global %struct.ImageParameters ; <%struct.ImageParameters*> [#uses=2]
+ at images = external global %struct.ImageParameters ; <ptr> [#uses=2]
-declare i8* @calloc(i32, i32)
+declare ptr @calloc(i32, i32)
define fastcc void @init_global_buffers() nounwind {
entry:
@@ -21,16 +21,16 @@ entry:
br i1 false, label %init_orig_buffers.exit, label %cond_true.i29
cond_true.i29: ; preds = %entry
- %tmp17.i = load i32, i32* getelementptr (%struct.ImageParameters, %struct.ImageParameters* @images, i32 0, i32 20), align 8 ; <i32> [#uses=1]
- %tmp20.i27 = load i32, i32* getelementptr (%struct.ImageParameters, %struct.ImageParameters* @images, i32 0, i32 16), align 8 ; <i32> [#uses=1]
+ %tmp17.i = load i32, ptr getelementptr (%struct.ImageParameters, ptr @images, i32 0, i32 20), align 8 ; <i32> [#uses=1]
+ %tmp20.i27 = load i32, ptr getelementptr (%struct.ImageParameters, ptr @images, i32 0, i32 16), align 8 ; <i32> [#uses=1]
%tmp8.i.i = select i1 false, i32 1, i32 0 ; <i32> [#uses=1]
br label %bb.i8.us.i
bb.i8.us.i: ; preds = %get_mem2Dpel.exit.i.us.i, %cond_true.i29
%j.04.i.us.i = phi i32 [ %indvar.next39.i, %get_mem2Dpel.exit.i.us.i ], [ 0, %cond_true.i29 ] ; <i32> [#uses=2]
- %tmp13.i.us.i = getelementptr i16**, i16*** null, i32 %j.04.i.us.i ; <i16***> [#uses=0]
- %tmp15.i.i.us.i = tail call i8* @calloc( i32 0, i32 2 ) ; <i8*> [#uses=0]
- store i16* null, i16** null, align 4
+ %tmp13.i.us.i = getelementptr ptr, ptr null, i32 %j.04.i.us.i ; <ptr> [#uses=0]
+ %tmp15.i.i.us.i = tail call ptr @calloc( i32 0, i32 2 ) ; <ptr> [#uses=0]
+ store ptr null, ptr null, align 4
br label %bb.i.i.us.i
get_mem2Dpel.exit.i.us.i: ; preds = %bb.i.i.us.i
diff --git a/llvm/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll
index 3d69e4fefbc27..bd43756086073 100644
--- a/llvm/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll
+++ b/llvm/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll
@@ -1,16 +1,16 @@
; RUN: llc < %s -mtriple=arm-apple-darwin
- %struct.Decoders = type { i32**, i16***, i16****, i16***, i16**, i8**, i8** }
- at decoders = external global %struct.Decoders ; <%struct.Decoders*> [#uses=1]
+ %struct.Decoders = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr }
+ at decoders = external global %struct.Decoders ; <ptr> [#uses=1]
-declare i8* @calloc(i32, i32)
+declare ptr @calloc(i32, i32)
-declare fastcc i32 @get_mem2Dint(i32***, i32, i32)
+declare fastcc i32 @get_mem2Dint(ptr, i32, i32)
define fastcc void @init_global_buffers() nounwind {
entry:
- %tmp151 = tail call fastcc i32 @get_mem2Dint( i32*** getelementptr (%struct.Decoders, %struct.Decoders* @decoders, i32 0, i32 0), i32 16, i32 16 ) ; <i32> [#uses=1]
- %tmp158 = tail call i8* @calloc( i32 0, i32 4 ) ; <i8*> [#uses=0]
+ %tmp151 = tail call fastcc i32 @get_mem2Dint( ptr @decoders, i32 16, i32 16 ) ; <i32> [#uses=1]
+ %tmp158 = tail call ptr @calloc( i32 0, i32 4 ) ; <ptr> [#uses=0]
br i1 false, label %cond_true166, label %bb190.preheader
bb190.preheader: ; preds = %entry
diff --git a/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll b/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll
index cf98d7f91df06..5d014954f2859 100644
--- a/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll
+++ b/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll
@@ -1,9 +1,9 @@
; RUN: llc -mtriple=arm-eabi %s -o /dev/null
; PR2589
-define void @main({ i32 }*) {
+define void @main(ptr) {
entry:
- %sret1 = alloca { i32 } ; <{ i32 }*> [#uses=1]
- load { i32 }, { i32 }* %sret1 ; <{ i32 }>:1 [#uses=0]
+ %sret1 = alloca { i32 } ; <ptr> [#uses=1]
+ load { i32 }, ptr %sret1 ; <{ i32 }>:1 [#uses=0]
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll b/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll
index 99f3052114fd5..af0658f87c3a8 100644
--- a/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll
+++ b/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll
@@ -1,14 +1,14 @@
; RUN: llc -mtriple arm-apple-darwin -mattr=+v6 -relocation-model pic -filetype asm -o - %s | FileCheck %s
-%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
-%struct.__gcov_var = type { %struct.FILE*, i32, i32, i32, i32, i32, i32, [1025 x i32] }
+%struct.FILE = type { ptr, i32, i32, i16, i16, %struct.__sbuf, i32, ptr, ptr, ptr, ptr, ptr, %struct.__sbuf, ptr, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+%struct.__gcov_var = type { ptr, i32, i32, i32, i32, i32, i32, [1025 x i32] }
%struct.__sFILEX = type opaque
-%struct.__sbuf = type { i8*, i32 }
+%struct.__sbuf = type { ptr, i32 }
@__gcov_var = common global %struct.__gcov_var zeroinitializer
define i32 @__gcov_close() nounwind {
entry:
- load i32, i32* getelementptr (%struct.__gcov_var, %struct.__gcov_var* @__gcov_var, i32 0, i32 5), align 4
+ load i32, ptr getelementptr (%struct.__gcov_var, ptr @__gcov_var, i32 0, i32 5), align 4
ret i32 %0
}
diff --git a/llvm/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll b/llvm/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll
index d3bc3e1663bcf..ec9fd5a244856 100644
--- a/llvm/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll
+++ b/llvm/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll
@@ -8,10 +8,10 @@ bb24: ; preds = %entry
br label %bb39
bb33.thread: ; preds = %entry
- %0 = alloca i8, i32 0 ; <i8*> [#uses=1]
+ %0 = alloca i8, i32 0 ; <ptr> [#uses=1]
br label %bb39
bb39: ; preds = %bb33.thread, %bb24
- %.reg2mem.0 = phi i8* [ %0, %bb33.thread ], [ null, %bb24 ] ; <i8*> [#uses=0]
+ %.reg2mem.0 = phi ptr [ %0, %bb33.thread ], [ null, %bb24 ] ; <ptr> [#uses=0]
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll b/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll
index bdb47fcc6ae3c..8063e0fd67135 100644
--- a/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll
+++ b/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll
@@ -5,17 +5,17 @@ target triple = "arm-apple-darwin9"
%struct.FIRST_UNION = type { %struct.FILE_POS }
%struct.FOURTH_UNION = type { %struct.STYLE }
%struct.GAP = type { i8, i8, i16 }
- %struct.LIST = type { %struct.rec*, %struct.rec* }
+ %struct.LIST = type { ptr, ptr }
%struct.SECOND_UNION = type { { i16, i8, i8 } }
%struct.STYLE = type { { %struct.GAP }, { %struct.GAP }, i16, i16, i32 }
%struct.THIRD_UNION = type { { [2 x i32], [2 x i32] } }
- %struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, %struct.rec*, { %struct.rec* }, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i32 }
+ %struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, ptr, { ptr }, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32 }
%struct.rec = type { %struct.head_type }
- at no_file_pos = external global %struct.FILE_POS ; <%struct.FILE_POS*> [#uses=1]
-@"\01LC13423" = external constant [23 x i8] ; <[23 x i8]*> [#uses=1]
-@"\01LC18972" = external constant [13 x i8] ; <[13 x i8]*> [#uses=1]
+ at no_file_pos = external global %struct.FILE_POS ; <ptr> [#uses=1]
+@"\01LC13423" = external constant [23 x i8] ; <ptr> [#uses=1]
+@"\01LC18972" = external constant [13 x i8] ; <ptr> [#uses=1]
-define fastcc void @FlushGalley(%struct.rec* %hd) nounwind {
+define fastcc void @FlushGalley(ptr %hd) nounwind {
entry:
br label %RESUME
@@ -77,25 +77,25 @@ bb131: ; preds = %bb122
br label %bb396
bb244: ; preds = %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122
- %0 = icmp eq %struct.rec* %stop_link.3, null ; <i1> [#uses=1]
+ %0 = icmp eq ptr %stop_link.3, null ; <i1> [#uses=1]
br i1 %0, label %bb435, label %bb433
bb394: ; preds = %bb122
- call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...) @Error(i32 1, i32 3, i8* getelementptr ([23 x i8], [23 x i8]* @"\01LC13423", i32 0, i32 0), i32 0, %struct.FILE_POS* @no_file_pos, i8* getelementptr ([13 x i8], [13 x i8]* @"\01LC18972", i32 0, i32 0), i8* null) nounwind
+ call void (i32, i32, ptr, i32, ptr, ...) @Error(i32 1, i32 3, ptr @"\01LC13423", i32 0, ptr @no_file_pos, ptr @"\01LC18972", ptr null) nounwind
br label %bb396
bb396: ; preds = %bb394, %bb131, %bb122, %bb122, %bb122, %bb122, %RESUME
- %stop_link.3 = phi %struct.rec* [ null, %RESUME ], [ %stop_link.3, %bb394 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %link.1, %bb131 ] ; <%struct.rec*> [#uses=7]
+ %stop_link.3 = phi ptr [ null, %RESUME ], [ %stop_link.3, %bb394 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %link.1, %bb131 ] ; <ptr> [#uses=7]
%headers_seen.1 = phi i32 [ 0, %RESUME ], [ %headers_seen.1, %bb394 ], [ 1, %bb122 ], [ 1, %bb122 ], [ 1, %bb122 ], [ 1, %bb122 ], [ %headers_seen.1, %bb131 ] ; <i32> [#uses=2]
- %link.1 = load %struct.rec*, %struct.rec** null ; <%struct.rec*> [#uses=2]
- %1 = icmp eq %struct.rec* %link.1, %hd ; <i1> [#uses=1]
+ %link.1 = load ptr, ptr null ; <ptr> [#uses=2]
+ %1 = icmp eq ptr %link.1, %hd ; <i1> [#uses=1]
br i1 %1, label %bb398, label %bb122
bb398: ; preds = %bb396
unreachable
bb433: ; preds = %bb244
- call fastcc void @Promote(%struct.rec* %hd, %struct.rec* %stop_link.3, %struct.rec* null, i32 1) nounwind
+ call fastcc void @Promote(ptr %hd, ptr %stop_link.3, ptr null, i32 1) nounwind
br label %bb435
bb435: ; preds = %bb433, %bb244
@@ -105,13 +105,13 @@ bb491: ; preds = %bb435
br label %bb499
bb499: ; preds = %bb499, %bb491, %bb435
- %2 = icmp eq %struct.rec* null, null ; <i1> [#uses=1]
+ %2 = icmp eq ptr null, null ; <i1> [#uses=1]
br i1 %2, label %bb520.preheader, label %bb499
bb520.preheader: ; preds = %bb499
br label %RESUME
}
-declare fastcc void @Promote(%struct.rec*, %struct.rec*, %struct.rec* nocapture, i32) nounwind
+declare fastcc void @Promote(ptr, ptr, ptr nocapture, i32) nounwind
-declare void @Error(i32, i32, i8*, i32, %struct.FILE_POS*, ...) nounwind
+declare void @Error(i32, i32, ptr, i32, ptr, ...) nounwind
diff --git a/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll b/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll
index a14589fa47d8f..e4b8bfd5cebec 100644
--- a/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll
+++ b/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll
@@ -3,18 +3,18 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-s0:0:64-f80:32:32"
target triple = "arm-elf"
-define i32 @main(i8*) nounwind {
+define i32 @main(ptr) nounwind {
entry:
- %ap = alloca i8* ; <i8**> [#uses=2]
- store i8* %0, i8** %ap
- %retval = alloca i32 ; <i32*> [#uses=2]
- store i32 0, i32* %retval
- %tmp = alloca float ; <float*> [#uses=1]
- %1 = va_arg i8** %ap, float ; <float> [#uses=1]
- store float %1, float* %tmp
+ %ap = alloca ptr ; <ptr> [#uses=2]
+ store ptr %0, ptr %ap
+ %retval = alloca i32 ; <ptr> [#uses=2]
+ store i32 0, ptr %retval
+ %tmp = alloca float ; <ptr> [#uses=1]
+ %1 = va_arg ptr %ap, float ; <float> [#uses=1]
+ store float %1, ptr %tmp
br label %return
return: ; preds = %entry
- %2 = load i32, i32* %retval ; <i32> [#uses=1]
+ %2 = load i32, ptr %retval ; <i32> [#uses=1]
ret i32 %2
}
diff --git a/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll b/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll
index 1584a88c76308..61014ec8dbc9d 100644
--- a/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll
+++ b/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll
@@ -1,12 +1,12 @@
; RUN: llc < %s -mattr=+v6,+vfp2
target triple = "arm-apple-darwin9"
- at a = external global double ; <double*> [#uses=1]
- at N = external global double ; <double*> [#uses=1]
+ at a = external global double ; <ptr> [#uses=1]
+ at N = external global double ; <ptr> [#uses=1]
declare double @llvm.exp.f64(double) nounwind readonly
-define fastcc void @findratio(double* nocapture %res1, double* nocapture %res2) nounwind {
+define fastcc void @findratio(ptr nocapture %res1, ptr nocapture %res2) nounwind {
bb.thread:
br label %bb52
@@ -28,12 +28,12 @@ bb53: ; preds = %bb52
br i1 %phitmp, label %bb55, label %bb52
bb55: ; preds = %bb53
- %4 = load double, double* @a, align 4 ; <double> [#uses=10]
+ %4 = load double, ptr @a, align 4 ; <double> [#uses=10]
%5 = fadd double %4, 0.000000e+00 ; <double> [#uses=16]
%6 = fcmp ogt double %k.4, 0.000000e+00 ; <i1> [#uses=1]
%.pn404 = fmul double %4, %4 ; <double> [#uses=4]
%.pn402 = fmul double %5, %5 ; <double> [#uses=5]
- %.pn165.in = load double, double* @N ; <double> [#uses=5]
+ %.pn165.in = load double, ptr @N ; <double> [#uses=5]
%.pn198 = fmul double 0.000000e+00, %5 ; <double> [#uses=1]
%.pn185 = fsub double -0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
%.pn147 = fsub double -0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
diff --git a/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll b/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll
index 62a9aa23f29f9..9acdb2a4dbf43 100644
--- a/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll
+++ b/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll
@@ -2,7 +2,7 @@
; rdar://6653182
-%struct.ggBRDF = type { i32 (...)** }
+%struct.ggBRDF = type { ptr }
%struct.ggPoint2 = type { [2 x double] }
%struct.ggPoint3 = type { [3 x double] }
%struct.ggSpectrum = type { [8 x float] }
@@ -17,7 +17,7 @@ declare double @sin(double) nounwind readonly
declare double @acos(double) nounwind readonly
-define i32 @_ZNK34mrDiffuseSolidAngleSphereLuminaire18selectVisiblePointERK8ggPoint3RK9ggVector3RK8ggPoint2dRS0_Rd(%struct.mrDiffuseCosineSphereLuminaire* nocapture %this, %struct.ggPoint3* nocapture %x, %struct.ggPoint3* nocapture %unnamed_arg, %struct.ggPoint2* nocapture %uv, double %unnamed_arg2, %struct.ggPoint3* nocapture %on_light, double* nocapture %invProb) nounwind {
+define i32 @_ZNK34mrDiffuseSolidAngleSphereLuminaire18selectVisiblePointERK8ggPoint3RK9ggVector3RK8ggPoint2dRS0_Rd(ptr nocapture %this, ptr nocapture %x, ptr nocapture %unnamed_arg, ptr nocapture %uv, double %unnamed_arg2, ptr nocapture %on_light, ptr nocapture %invProb) nounwind {
entry:
%0 = call double @llvm.sqrt.f64(double 0.000000e+00) nounwind
%1 = fcmp ult double 0.000000e+00, %0
@@ -42,7 +42,7 @@ bb3: ; preds = %entry
%17 = fdiv double %16, %0
%18 = fadd double 0.000000e+00, %17
%19 = call double @acos(double %18) nounwind readonly
- %20 = load double, double* null, align 4
+ %20 = load double, ptr null, align 4
%21 = fmul double %20, 0x401921FB54442D18
%22 = call double @sin(double %19) nounwind readonly
%23 = fmul double %22, 0.000000e+00
@@ -58,22 +58,21 @@ bb3: ; preds = %entry
%33 = fadd double %30, 0.000000e+00
%34 = fadd double %31, 0.000000e+00
%35 = fadd double %32, 0.000000e+00
- %36 = bitcast %struct.ggPoint3* %x to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 null, i8* align 4 %36, i32 24, i1 false)
- store double %33, double* null, align 8
+ call void @llvm.memcpy.p0.p0.i32(ptr align 4 null, ptr align 4 %x, i32 24, i1 false)
+ store double %33, ptr null, align 8
br i1 false, label %_Z20ggRaySphereIntersectRK6ggRay3RK8ggSphereddRd.exit, label %bb5.i.i.i
bb5.i.i.i: ; preds = %bb3
unreachable
_Z20ggRaySphereIntersectRK6ggRay3RK8ggSphereddRd.exit: ; preds = %bb3
- %37 = fsub double %13, 0.000000e+00
- %38 = fsub double -0.000000e+00, %34
- %39 = fsub double -0.000000e+00, %35
+ %36 = fsub double %13, 0.000000e+00
+ %37 = fsub double -0.000000e+00, %34
+ %38 = fsub double -0.000000e+00, %35
ret i32 1
bb7: ; preds = %entry
ret i32 0
}
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
diff --git a/llvm/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll b/llvm/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll
index a9d5480e72c92..3937f9e9ac87b 100644
--- a/llvm/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll
+++ b/llvm/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll
@@ -4,10 +4,9 @@
%struct.node_t = type { %struct.hit_t, %struct.hit_t, i32 }
%struct.v_t = type { double, double, double }
-define fastcc %struct.node_t* @_ZL6createP6node_tii3v_tS1_d(%struct.node_t* %n, i32 %lvl, i32 %dist, i64 %c.0.0, i64 %c.0.1, i64 %c.0.2, i64 %d.0.0, i64 %d.0.1, i64 %d.0.2, double %r) nounwind {
+define fastcc ptr @_ZL6createP6node_tii3v_tS1_d(ptr %n, i32 %lvl, i32 %dist, i64 %c.0.0, i64 %c.0.1, i64 %c.0.2, i64 %d.0.0, i64 %d.0.1, i64 %d.0.2, double %r) nounwind {
entry:
- %0 = getelementptr %struct.node_t, %struct.node_t* %n, i32 0, i32 1 ; <%struct.hit_t*> [#uses=1]
- %1 = bitcast %struct.hit_t* %0 to i256* ; <i256*> [#uses=1]
- store i256 0, i256* %1, align 4
+ %0 = getelementptr %struct.node_t, ptr %n, i32 0, i32 1 ; <ptr> [#uses=1]
+ store i256 0, ptr %0, align 4
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll b/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll
index bc7dbd4f69531..1ab71b214ca7d 100644
--- a/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll
+++ b/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll
@@ -2,20 +2,20 @@
define i32 @_swilseek(i32) nounwind {
entry:
- %ptr = alloca i32 ; <i32*> [#uses=2]
- store i32 %0, i32* %ptr
- %retval = alloca i32 ; <i32*> [#uses=2]
- store i32 0, i32* %retval
- %res = alloca i32 ; <i32*> [#uses=0]
- %fh = alloca i32 ; <i32*> [#uses=1]
- %1 = load i32, i32* %fh ; <i32> [#uses=1]
- %2 = load i32, i32* %ptr ; <i32> [#uses=1]
+ %ptr = alloca i32 ; <ptr> [#uses=2]
+ store i32 %0, ptr %ptr
+ %retval = alloca i32 ; <ptr> [#uses=2]
+ store i32 0, ptr %retval
+ %res = alloca i32 ; <ptr> [#uses=0]
+ %fh = alloca i32 ; <ptr> [#uses=1]
+ %1 = load i32, ptr %fh ; <i32> [#uses=1]
+ %2 = load i32, ptr %ptr ; <i32> [#uses=1]
%3 = call i32 asm "mov r0, $2; mov r1, $3; swi ${1:a}; mov $0, r0", "=r,i,r,r,~{r0},~{r1}"(i32 107, i32 %1, i32 %2) nounwind ; <i32> [#uses=1]
- store i32 %3, i32* %retval
+ store i32 %3, ptr %retval
br label %return
return: ; preds = %entry
- %4 = load i32, i32* %retval ; <i32> [#uses=1]
+ %4 = load i32, ptr %retval ; <i32> [#uses=1]
ret i32 %4
}
diff --git a/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll b/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll
index edeae9b88bcec..8a8ab54d12548 100644
--- a/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll
+++ b/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll
@@ -1,18 +1,18 @@
; RUN: llc -mtriple=arm-eabi %s -o /dev/null
; PR3795
-define fastcc void @_D3foo3fooFAriZv({ i32, { double, double }* } %d_arg, i32 %x_arg) {
+define fastcc void @_D3foo3fooFAriZv({ i32, ptr } %d_arg, i32 %x_arg) {
entry:
- %d = alloca { i32, { double, double }* } ; <{ i32, { double, double }* }*> [#uses=2]
- %x = alloca i32 ; <i32*> [#uses=2]
- %b = alloca { double, double } ; <{ double, double }*> [#uses=1]
- store { i32, { double, double }* } %d_arg, { i32, { double, double }* }* %d
- store i32 %x_arg, i32* %x
- %tmp = load i32, i32* %x ; <i32> [#uses=1]
- %tmp1 = getelementptr { i32, { double, double }* }, { i32, { double, double }* }* %d, i32 0, i32 1 ; <{ double, double }**> [#uses=1]
- %.ptr = load { double, double }*, { double, double }** %tmp1 ; <{ double, double }*> [#uses=1]
- %tmp2 = getelementptr { double, double }, { double, double }* %.ptr, i32 %tmp ; <{ double, double }*> [#uses=1]
- %tmp3 = load { double, double }, { double, double }* %tmp2 ; <{ double, double }> [#uses=1]
- store { double, double } %tmp3, { double, double }* %b
+ %d = alloca { i32, ptr } ; <ptr> [#uses=2]
+ %x = alloca i32 ; <ptr> [#uses=2]
+ %b = alloca { double, double } ; <ptr> [#uses=1]
+ store { i32, ptr } %d_arg, ptr %d
+ store i32 %x_arg, ptr %x
+ %tmp = load i32, ptr %x ; <i32> [#uses=1]
+ %tmp1 = getelementptr { i32, ptr }, ptr %d, i32 0, i32 1 ; <ptr> [#uses=1]
+ %.ptr = load ptr, ptr %tmp1 ; <ptr> [#uses=1]
+ %tmp2 = getelementptr { double, double }, ptr %.ptr, i32 %tmp ; <ptr> [#uses=1]
+ %tmp3 = load { double, double }, ptr %tmp2 ; <{ double, double }> [#uses=1]
+ store { double, double } %tmp3, ptr %b
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2009-04-08-FREM.ll b/llvm/test/CodeGen/ARM/2009-04-08-FREM.ll
index e0f9485888d9e..d7dca8e57b599 100644
--- a/llvm/test/CodeGen/ARM/2009-04-08-FREM.ll
+++ b/llvm/test/CodeGen/ARM/2009-04-08-FREM.ll
@@ -1,9 +1,9 @@
; RUN: llc -mtriple=arm-eabi %s -o /dev/null
-declare i32 @printf(i8*, ...)
+declare i32 @printf(ptr, ...)
define i32 @main() {
%rem_r = frem double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
- %1 = call i32 (i8*, ...) @printf(i8* null, double %rem_r) ; <i32> [#uses=0]
+ %1 = call i32 (ptr, ...) @printf(ptr null, double %rem_r) ; <i32> [#uses=0]
ret i32 0
}
diff --git a/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll b/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
index 949e1072b2b6c..a5f2ec2593e3c 100644
--- a/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
+++ b/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
@@ -1,11 +1,11 @@
; RUN: llc -mtriple=arm-eabi %s -o /dev/null
-define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>* %CONST) {
+define void @execute_shader(ptr %OUT, ptr %IN, ptr %CONST) {
entry:
- %input2 = load <4 x float>, <4 x float>* null, align 16 ; <<4 x float>> [#uses=2]
+ %input2 = load <4 x float>, ptr null, align 16 ; <<4 x float>> [#uses=2]
%shuffle7 = shufflevector <4 x float> %input2, <4 x float> <float 0.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00>, <4 x i32> <i32 2, i32 2, i32 2, i32 2> ; <<4 x float>> [#uses=1]
%mul1 = fmul <4 x float> %shuffle7, zeroinitializer ; <<4 x float>> [#uses=1]
%add2 = fadd <4 x float> %mul1, %input2 ; <<4 x float>> [#uses=1]
- store <4 x float> %add2, <4 x float>* null, align 16
+ store <4 x float> %add2, ptr null, align 16
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll b/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll
index f2532d798f834..cd512eb10cdca 100644
--- a/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll
+++ b/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll
@@ -3,10 +3,10 @@
define void @foo(...) nounwind {
entry:
- %rr = alloca i32 ; <i32*> [#uses=2]
- %0 = load i32, i32* %rr ; <i32> [#uses=1]
+ %rr = alloca i32 ; <ptr> [#uses=2]
+ %0 = load i32, ptr %rr ; <i32> [#uses=1]
%1 = call i32 asm "nop", "=r,0"(i32 %0) nounwind ; <i32> [#uses=1]
- store i32 %1, i32* %rr
+ store i32 %1, ptr %rr
br label %return
return: ; preds = %entry
diff --git a/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll b/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll
index c50aa4a018be4..99ab064ef9217 100644
--- a/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll
+++ b/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll
@@ -1,11 +1,11 @@
; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi -mattr=+v6
; PR4166
- %"byte[]" = type { i32, i8* }
+ %"byte[]" = type { i32, ptr }
%tango.time.Time.Time = type { i64 }
define fastcc void @t() {
entry:
- %tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval(%tango.time.Time.Time) null) ; <i1> [#uses=0]
+ %tmp28 = call fastcc i1 null(ptr null, %"byte[]" undef, %"byte[]" undef, ptr byval(%tango.time.Time.Time) null) ; <i1> [#uses=0]
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll b/llvm/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll
index ac641f99dbf9e..bd48dcf8e0889 100644
--- a/llvm/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll
+++ b/llvm/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll
@@ -1,12 +1,12 @@
; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=fast
; PR4100
- at .str = external constant [30 x i8] ; <[30 x i8]*> [#uses=1]
+ at .str = external constant [30 x i8] ; <ptr> [#uses=1]
define i16 @fn16(i16 %arg0.0, <2 x i16> %arg1, i16 %arg2.0) nounwind {
entry:
- store <2 x i16> %arg1, <2 x i16>* null
- %0 = call i32 (i8*, ...) @printf(i8* getelementptr ([30 x i8], [30 x i8]* @.str, i32 0, i32 0), i32 0) nounwind ; <i32> [#uses=0]
+ store <2 x i16> %arg1, ptr null
+ %0 = call i32 (ptr, ...) @printf(ptr @.str, i32 0) nounwind ; <i32> [#uses=0]
ret i16 0
}
-declare i32 @printf(i8*, ...) nounwind
+declare i32 @printf(ptr, ...) nounwind
diff --git a/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll b/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll
index ae005dbf4b136..a07af6afba31c 100644
--- a/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll
+++ b/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll
@@ -1,17 +1,17 @@
; RUN: llc -mtriple=arm-eabi %s -o /dev/null
- %struct.List = type { %struct.List*, i32 }
- at Node5 = external constant %struct.List ; <%struct.List*> [#uses=1]
-@"\01LC" = external constant [7 x i8] ; <[7 x i8]*> [#uses=1]
+ %struct.List = type { ptr, i32 }
+ at Node5 = external constant %struct.List ; <ptr> [#uses=1]
+@"\01LC" = external constant [7 x i8] ; <ptr> [#uses=1]
define i32 @main() nounwind {
entry:
br label %bb
bb: ; preds = %bb3, %entry
- %CurL.02 = phi %struct.List* [ @Node5, %entry ], [ %2, %bb3 ] ; <%struct.List*> [#uses=1]
- %PrevL.01 = phi %struct.List* [ null, %entry ], [ %CurL.02, %bb3 ] ; <%struct.List*> [#uses=1]
- %0 = icmp eq %struct.List* %PrevL.01, null ; <i1> [#uses=1]
+ %CurL.02 = phi ptr [ @Node5, %entry ], [ %2, %bb3 ] ; <ptr> [#uses=1]
+ %PrevL.01 = phi ptr [ null, %entry ], [ %CurL.02, %bb3 ] ; <ptr> [#uses=1]
+ %0 = icmp eq ptr %PrevL.01, null ; <i1> [#uses=1]
br i1 %0, label %bb3, label %bb1
bb1: ; preds = %bb
@@ -19,13 +19,13 @@ bb1: ; preds = %bb
bb3: ; preds = %bb1, %bb
%iftmp.0.0 = phi i32 [ 0, %bb1 ], [ -1, %bb ] ; <i32> [#uses=1]
- %1 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([7 x i8], [7 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 %iftmp.0.0) nounwind ; <i32> [#uses=0]
- %2 = load %struct.List*, %struct.List** null, align 4 ; <%struct.List*> [#uses=2]
- %phitmp = icmp eq %struct.List* %2, null ; <i1> [#uses=1]
+ %1 = tail call i32 (ptr, ...) @printf(ptr @"\01LC", i32 0, i32 %iftmp.0.0) nounwind ; <i32> [#uses=0]
+ %2 = load ptr, ptr null, align 4 ; <ptr> [#uses=2]
+ %phitmp = icmp eq ptr %2, null ; <i1> [#uses=1]
br i1 %phitmp, label %bb5, label %bb
bb5: ; preds = %bb3
ret i32 0
}
-declare i32 @printf(i8* nocapture, ...) nounwind
+declare i32 @printf(ptr nocapture, ...) nounwind
diff --git a/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll b/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll
index 2672aa317ba1a..ae57c3a7dc557 100644
--- a/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll
+++ b/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll
@@ -1,8 +1,8 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
; PR4091
-define void @foo(i32 %i, i32* %p) nounwind {
+define void @foo(i32 %i, ptr %p) nounwind {
;CHECK: swp r2, r0, [r1]
- %asmtmp = call i32 asm sideeffect "swp $0, $2, $3", "=&r,=*m,r,*m,~{memory}"(i32* elementtype(i32) %p, i32 %i, i32* elementtype(i32) %p) nounwind
+ %asmtmp = call i32 asm sideeffect "swp $0, $2, $3", "=&r,=*m,r,*m,~{memory}"(ptr elementtype(i32) %p, i32 %i, ptr elementtype(i32) %p) nounwind
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll b/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll
index 7bbb8090c8491..391cbb1fb09e6 100644
--- a/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll
+++ b/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll
@@ -1,8 +1,8 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -mattr=+v6,+vfp2
-@"\01LC" = external constant [15 x i8] ; <[15 x i8]*> [#uses=1]
+@"\01LC" = external constant [15 x i8] ; <ptr> [#uses=1]
-declare i32 @printf(i8* nocapture, ...) nounwind
+declare i32 @printf(ptr nocapture, ...) nounwind
define i32 @main() nounwind {
entry:
@@ -57,6 +57,6 @@ Fft.exit.i: ; preds = %bb7.i.i
br i1 undef, label %bb5.i, label %bb1.outer2.i.i.outer
bb5.i: ; preds = %Fft.exit.i
- %0 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([15 x i8], [15 x i8]* @"\01LC", i32 0, i32 0), double undef, double undef) nounwind ; <i32> [#uses=0]
+ %0 = tail call i32 (ptr, ...) @printf(ptr @"\01LC", double undef, double undef) nounwind ; <i32> [#uses=0]
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll b/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll
index 17beb3c259471..b03bfd519b937 100644
--- a/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll
+++ b/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll
@@ -1,16 +1,16 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6
%struct.anon = type { i16, i16 }
- %struct.cab_archive = type { i32, i16, i16, i16, i16, i8, %struct.cab_folder*, %struct.cab_file* }
- %struct.cab_file = type { i32, i16, i64, i8*, i32, i32, i32, %struct.cab_folder*, %struct.cab_file*, %struct.cab_archive*, %struct.cab_state* }
- %struct.cab_folder = type { i16, i16, %struct.cab_archive*, i64, %struct.cab_folder* }
- %struct.cab_state = type { i8*, i8*, [38912 x i8], i16, i16, i8*, i16 }
- %struct.qtm_model = type { i32, i32, %struct.anon* }
- %struct.qtm_stream = type { i32, i32, i8, i8*, i32, i32, i32, i16, i16, i16, i8, i32, i8*, i8*, i8*, i8*, i8*, i32, i32, i8, [42 x i32], [42 x i8], [27 x i8], [27 x i8], %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [25 x %struct.anon], [37 x %struct.anon], [43 x %struct.anon], [28 x %struct.anon], [8 x %struct.anon], %struct.cab_file*, i32 (%struct.cab_file*, i8*, i32)* }
+ %struct.cab_archive = type { i32, i16, i16, i16, i16, i8, ptr, ptr }
+ %struct.cab_file = type { i32, i16, i64, ptr, i32, i32, i32, ptr, ptr, ptr, ptr }
+ %struct.cab_folder = type { i16, i16, ptr, i64, ptr }
+ %struct.cab_state = type { ptr, ptr, [38912 x i8], i16, i16, ptr, i16 }
+ %struct.qtm_model = type { i32, i32, ptr }
+ %struct.qtm_stream = type { i32, i32, i8, ptr, i32, i32, i32, i16, i16, i16, i8, i32, ptr, ptr, ptr, ptr, ptr, i32, i32, i8, [42 x i32], [42 x i8], [27 x i8], [27 x i8], %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [25 x %struct.anon], [37 x %struct.anon], [43 x %struct.anon], [28 x %struct.anon], [8 x %struct.anon], ptr, ptr }
-declare fastcc i32 @qtm_read_input(%struct.qtm_stream* nocapture) nounwind
+declare fastcc i32 @qtm_read_input(ptr nocapture) nounwind
-define fastcc i32 @qtm_decompress(%struct.qtm_stream* %qtm, i64 %out_bytes) nounwind {
+define fastcc i32 @qtm_decompress(ptr %qtm, i64 %out_bytes) nounwind {
entry:
br i1 undef, label %bb245, label %bb3
@@ -136,7 +136,7 @@ bb138: ; preds = %bb77
br label %bb141
bb139: ; preds = %bb141
- %scevgep441442881 = load i16, i16* undef ; <i16> [#uses=1]
+ %scevgep441442881 = load i16, ptr undef ; <i16> [#uses=1]
%1 = icmp ugt i16 %scevgep441442881, %0 ; <i1> [#uses=1]
br i1 %1, label %bb141, label %bb142
@@ -225,7 +225,7 @@ bb187: ; preds = %bb195
br i1 undef, label %bb193, label %bb189
bb189: ; preds = %bb187
- %2 = tail call fastcc i32 @qtm_read_input(%struct.qtm_stream* %qtm) nounwind ; <i32> [#uses=0]
+ %2 = tail call fastcc i32 @qtm_read_input(ptr %qtm) nounwind ; <i32> [#uses=0]
ret i32 undef
bb193: ; preds = %bb187
diff --git a/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll
index a0f903b0bdf56..07bdff382e971 100644
--- a/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll
+++ b/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll
@@ -2,23 +2,23 @@
%struct.term = type { i32, i32, i32 }
-declare fastcc i8* @memory_Malloc(i32) nounwind
+declare fastcc ptr @memory_Malloc(i32) nounwind
-define fastcc %struct.term* @t1() nounwind {
+define fastcc ptr @t1() nounwind {
entry:
br i1 undef, label %bb, label %bb1
bb: ; preds = %entry
- ret %struct.term* undef
+ ret ptr undef
bb1: ; preds = %entry
- %0 = tail call fastcc i8* @memory_Malloc(i32 12) nounwind ; <i8*> [#uses=0]
- %1 = tail call fastcc i8* @memory_Malloc(i32 12) nounwind ; <i8*> [#uses=0]
- ret %struct.term* undef
+ %0 = tail call fastcc ptr @memory_Malloc(i32 12) nounwind ; <ptr> [#uses=0]
+ %1 = tail call fastcc ptr @memory_Malloc(i32 12) nounwind ; <ptr> [#uses=0]
+ ret ptr undef
}
-define i32 @t2(i32 %argc, i8** nocapture %argv) nounwind {
+define i32 @t2(i32 %argc, ptr nocapture %argv) nounwind {
entry:
br label %bb6.i8
@@ -30,10 +30,10 @@ bb.i.i9: ; preds = %bb6.i8
memory_CalculateRealBlockSize1374.exit.i: ; preds = %bb.i.i9, %bb6.i8
%0 = phi i32 [ undef, %bb.i.i9 ], [ undef, %bb6.i8 ] ; <i32> [#uses=2]
- store i32 %0, i32* undef, align 4
+ store i32 %0, ptr undef, align 4
%1 = urem i32 8184, %0 ; <i32> [#uses=1]
%2 = sub i32 8188, %1 ; <i32> [#uses=1]
- store i32 %2, i32* undef, align 4
+ store i32 %2, ptr undef, align 4
br i1 undef, label %memory_Init.exit, label %bb6.i8
memory_Init.exit: ; preds = %memory_CalculateRealBlockSize1374.exit.i
diff --git a/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll b/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll
index 4ab54c2e8faf8..ebff4c2f663ee 100644
--- a/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll
+++ b/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll
@@ -3,11 +3,11 @@
%struct.rtunion = type { i64 }
%struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] }
-define void @simplify_unary_real(i8* nocapture %p) nounwind {
+define void @simplify_unary_real(ptr nocapture %p) nounwind {
entry:
- %tmp121 = load i64, i64* null, align 4 ; <i64> [#uses=1]
- %0 = getelementptr %struct.rtx_def, %struct.rtx_def* null, i32 0, i32 3, i32 3, i32 0 ; <i64*> [#uses=1]
- %tmp122 = load i64, i64* %0, align 4 ; <i64> [#uses=1]
+ %tmp121 = load i64, ptr null, align 4 ; <i64> [#uses=1]
+ %0 = getelementptr %struct.rtx_def, ptr null, i32 0, i32 3, i32 3, i32 0 ; <ptr> [#uses=1]
+ %tmp122 = load i64, ptr %0, align 4 ; <i64> [#uses=1]
%1 = zext i64 undef to i192 ; <i192> [#uses=2]
%2 = zext i64 %tmp121 to i192 ; <i192> [#uses=1]
%3 = shl i192 %2, 64 ; <i192> [#uses=2]
diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll
index a0e44ed86e0b3..52e47334dbc22 100644
--- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll
+++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll
@@ -1,18 +1,18 @@
; RUN: llc < %s -mtriple=armv6-apple-darwin9
- at nn = external global i32 ; <i32*> [#uses=1]
- at al_len = external global i32 ; <i32*> [#uses=2]
- at no_mat = external global i32 ; <i32*> [#uses=2]
- at no_mis = external global i32 ; <i32*> [#uses=2]
-@"\01LC12" = external constant [29 x i8], align 1 ; <[29 x i8]*> [#uses=1]
-@"\01LC16" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1]
-@"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1]
+ at nn = external global i32 ; <ptr> [#uses=1]
+ at al_len = external global i32 ; <ptr> [#uses=2]
+ at no_mat = external global i32 ; <ptr> [#uses=2]
+ at no_mis = external global i32 ; <ptr> [#uses=2]
+@"\01LC12" = external constant [29 x i8], align 1 ; <ptr> [#uses=1]
+@"\01LC16" = external constant [33 x i8], align 1 ; <ptr> [#uses=1]
+@"\01LC17" = external constant [47 x i8], align 1 ; <ptr> [#uses=1]
-declare i32 @printf(i8* nocapture, ...) nounwind
+declare i32 @printf(ptr nocapture, ...) nounwind
-declare void @
diff (i8*, i8*, i32, i32, i32, i32) nounwind
+declare void @
diff (ptr, ptr, i32, i32, i32, i32) nounwind
-define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
+define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
entry:
br i1 undef, label %bb5, label %bb
@@ -35,26 +35,26 @@ bb10: ; preds = %bb9
unreachable
bb11: ; preds = %bb9
- %0 = load i32, i32* undef, align 4 ; <i32> [#uses=2]
+ %0 = load i32, ptr undef, align 4 ; <i32> [#uses=2]
%1 = add i32 %0, 1 ; <i32> [#uses=2]
- store i32 %1, i32* undef, align 4
- %2 = load i32, i32* undef, align 4 ; <i32> [#uses=1]
- store i32 %2, i32* @nn, align 4
- store i32 0, i32* @al_len, align 4
- store i32 0, i32* @no_mat, align 4
- store i32 0, i32* @no_mis, align 4
- %3 = getelementptr i8, i8* %B, i32 %0 ; <i8*> [#uses=1]
- tail call void @
diff (i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind
+ store i32 %1, ptr undef, align 4
+ %2 = load i32, ptr undef, align 4 ; <i32> [#uses=1]
+ store i32 %2, ptr @nn, align 4
+ store i32 0, ptr @al_len, align 4
+ store i32 0, ptr @no_mat, align 4
+ store i32 0, ptr @no_mis, align 4
+ %3 = getelementptr i8, ptr %B, i32 %0 ; <ptr> [#uses=1]
+ tail call void @
diff (ptr undef, ptr %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind
%4 = sitofp i32 undef to double ; <double> [#uses=1]
%5 = fdiv double %4, 1.000000e+01 ; <double> [#uses=1]
- %6 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([29 x i8], [29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; <i32> [#uses=0]
- %7 = load i32, i32* @al_len, align 4 ; <i32> [#uses=1]
- %8 = load i32, i32* @no_mat, align 4 ; <i32> [#uses=1]
- %9 = load i32, i32* @no_mis, align 4 ; <i32> [#uses=1]
+ %6 = tail call i32 (ptr, ...) @printf(ptr @"\01LC12", double %5) nounwind ; <i32> [#uses=0]
+ %7 = load i32, ptr @al_len, align 4 ; <i32> [#uses=1]
+ %8 = load i32, ptr @no_mat, align 4 ; <i32> [#uses=1]
+ %9 = load i32, ptr @no_mis, align 4 ; <i32> [#uses=1]
%10 = sub i32 %7, %8 ; <i32> [#uses=1]
%11 = sub i32 %10, %9 ; <i32> [#uses=1]
- %12 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; <i32> [#uses=0]
- %13 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([47 x i8], [47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0]
+ %12 = tail call i32 (ptr, ...) @printf(ptr @"\01LC16", i32 %11) nounwind ; <i32> [#uses=0]
+ %13 = tail call i32 (ptr, ...) @printf(ptr @"\01LC17", i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0]
br i1 undef, label %bb15, label %bb12
bb12: ; preds = %bb11
diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll
index d47d968ce3a87..b23030ec57711 100644
--- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll
+++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll
@@ -1,16 +1,16 @@
; RUN: llc < %s -mtriple=armv6-apple-darwin9
- at no_mat = external global i32 ; <i32*> [#uses=1]
- at no_mis = external global i32 ; <i32*> [#uses=2]
-@"\01LC11" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1]
-@"\01LC15" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1]
-@"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1]
+ at no_mat = external global i32 ; <ptr> [#uses=1]
+ at no_mis = external global i32 ; <ptr> [#uses=2]
+@"\01LC11" = external constant [33 x i8], align 1 ; <ptr> [#uses=1]
+@"\01LC15" = external constant [33 x i8], align 1 ; <ptr> [#uses=1]
+@"\01LC17" = external constant [47 x i8], align 1 ; <ptr> [#uses=1]
-declare i32 @printf(i8* nocapture, ...) nounwind
+declare i32 @printf(ptr nocapture, ...) nounwind
-declare void @
diff (i8*, i8*, i32, i32, i32, i32) nounwind
+declare void @
diff (ptr, ptr, i32, i32, i32, i32) nounwind
-define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
+define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
entry:
br i1 undef, label %bb5, label %bb
@@ -33,19 +33,19 @@ bb10: ; preds = %bb9
unreachable
bb11: ; preds = %bb9
- %0 = load i32, i32* undef, align 4 ; <i32> [#uses=3]
+ %0 = load i32, ptr undef, align 4 ; <i32> [#uses=3]
%1 = add i32 %0, 1 ; <i32> [#uses=2]
- store i32 %1, i32* undef, align 4
- %2 = load i32, i32* undef, align 4 ; <i32> [#uses=2]
+ store i32 %1, ptr undef, align 4
+ %2 = load i32, ptr undef, align 4 ; <i32> [#uses=2]
%3 = sub i32 %2, %0 ; <i32> [#uses=1]
- store i32 0, i32* @no_mat, align 4
- store i32 0, i32* @no_mis, align 4
- %4 = getelementptr i8, i8* %B, i32 %0 ; <i8*> [#uses=1]
- tail call void @
diff (i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind
- %5 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; <i32> [#uses=0]
- %6 = load i32, i32* @no_mis, align 4 ; <i32> [#uses=1]
- %7 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; <i32> [#uses=0]
- %8 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([47 x i8], [47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0]
+ store i32 0, ptr @no_mat, align 4
+ store i32 0, ptr @no_mis, align 4
+ %4 = getelementptr i8, ptr %B, i32 %0 ; <ptr> [#uses=1]
+ tail call void @
diff (ptr undef, ptr %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind
+ %5 = tail call i32 (ptr, ...) @printf(ptr @"\01LC11", i32 %tmp13) nounwind ; <i32> [#uses=0]
+ %6 = load i32, ptr @no_mis, align 4 ; <i32> [#uses=1]
+ %7 = tail call i32 (ptr, ...) @printf(ptr @"\01LC15", i32 %6) nounwind ; <i32> [#uses=0]
+ %8 = tail call i32 (ptr, ...) @printf(ptr @"\01LC17", i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0]
br i1 undef, label %bb15, label %bb12
bb12: ; preds = %bb11
diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll
index d71744a28910d..727db4a322fbf 100644
--- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll
+++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll
@@ -1,8 +1,8 @@
; RUN: llc < %s -mtriple=armv6-apple-darwin9
- at JJ = external global i32* ; <i32**> [#uses=1]
+ at JJ = external global ptr ; <ptr> [#uses=1]
-define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
+define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
entry:
br i1 undef, label %bb5, label %bb
@@ -28,7 +28,7 @@ bb11: ; preds = %bb9
br i1 undef, label %bb15, label %bb12
bb12: ; preds = %bb11
- %0 = load i32*, i32** @JJ, align 4 ; <i32*> [#uses=1]
+ %0 = load ptr, ptr @JJ, align 4 ; <ptr> [#uses=1]
br label %bb228.i
bb74.i: ; preds = %bb228.i
@@ -84,22 +84,22 @@ bb167.i: ; preds = %bb163.i
bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
%fi.5.i = phi i32 [ undef, %bb167.i ], [ %ci.910.i, %bb158.i ], [ undef, %bb160.i ], [ %ci.910.i, %bb161.i ], [ undef, %bb163.i ] ; <i32> [#uses=1]
%fj.4.i = phi i32 [ undef, %bb167.i ], [ undef, %bb158.i ], [ %fj.515.i, %bb160.i ], [ undef, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2]
- %scevgep88.i = getelementptr i32, i32* null, i32 %i.121.i ; <i32*> [#uses=3]
- %4 = load i32, i32* %scevgep88.i, align 4 ; <i32> [#uses=2]
- %scevgep89.i = getelementptr i32, i32* %0, i32 %i.121.i ; <i32*> [#uses=3]
- %5 = load i32, i32* %scevgep89.i, align 4 ; <i32> [#uses=1]
+ %scevgep88.i = getelementptr i32, ptr null, i32 %i.121.i ; <ptr> [#uses=3]
+ %4 = load i32, ptr %scevgep88.i, align 4 ; <i32> [#uses=2]
+ %scevgep89.i = getelementptr i32, ptr %0, i32 %i.121.i ; <ptr> [#uses=3]
+ %5 = load i32, ptr %scevgep89.i, align 4 ; <i32> [#uses=1]
%ci.10.i = select i1 undef, i32 %pi.316.i, i32 %i.121.i ; <i32> [#uses=0]
%cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef ; <i32> [#uses=0]
%6 = icmp slt i32 undef, 0 ; <i1> [#uses=3]
%ci.12.i = select i1 %6, i32 %fi.5.i, i32 %4 ; <i32> [#uses=2]
%cj.11.i100 = select i1 %6, i32 %fj.4.i, i32 %5 ; <i32> [#uses=1]
%c.14.i = select i1 %6, i32 0, i32 undef ; <i32> [#uses=2]
- store i32 %c.14.i, i32* undef, align 4
- %7 = load i32, i32* %scevgep88.i, align 4 ; <i32> [#uses=1]
- %8 = load i32, i32* %scevgep89.i, align 4 ; <i32> [#uses=1]
- store i32 %ci.12.i, i32* %scevgep88.i, align 4
- store i32 %cj.11.i100, i32* %scevgep89.i, align 4
- store i32 %4, i32* undef, align 4
+ store i32 %c.14.i, ptr undef, align 4
+ %7 = load i32, ptr %scevgep88.i, align 4 ; <i32> [#uses=1]
+ %8 = load i32, ptr %scevgep89.i, align 4 ; <i32> [#uses=1]
+ store i32 %ci.12.i, ptr %scevgep88.i, align 4
+ store i32 %cj.11.i100, ptr %scevgep89.i, align 4
+ store i32 %4, ptr undef, align 4
br i1 undef, label %bb211.i, label %bb218.i
bb211.i: ; preds = %bb168.i
diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll
index 04cbc27aac25c..601e0da365394 100644
--- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll
+++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll
@@ -1,14 +1,14 @@
; RUN: llc < %s -mtriple=armv6-apple-darwin9
- at r = external global i32 ; <i32*> [#uses=1]
- at qr = external global i32 ; <i32*> [#uses=1]
- at II = external global i32* ; <i32**> [#uses=1]
- at no_mis = external global i32 ; <i32*> [#uses=1]
- at name1 = external global i8* ; <i8**> [#uses=1]
+ at r = external global i32 ; <ptr> [#uses=1]
+ at qr = external global i32 ; <ptr> [#uses=1]
+ at II = external global ptr ; <ptr> [#uses=1]
+ at no_mis = external global i32 ; <ptr> [#uses=1]
+ at name1 = external global ptr ; <ptr> [#uses=1]
-declare void @
diff (i8*, i8*, i32, i32, i32, i32) nounwind
+declare void @
diff (ptr, ptr, i32, i32, i32, i32) nounwind
-define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
+define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
entry:
br i1 undef, label %bb5, label %bb
@@ -22,7 +22,7 @@ bb6: ; preds = %bb6, %bb5
br i1 undef, label %bb8, label %bb6
bb8: ; preds = %bb6, %bb5
- %0 = load i8*, i8** @name1, align 4 ; <i8*> [#uses=0]
+ %0 = load ptr, ptr @name1, align 4 ; <ptr> [#uses=0]
br label %bb15
bb9: ; preds = %bb15
@@ -32,16 +32,16 @@ bb10: ; preds = %bb9
unreachable
bb11: ; preds = %bb9
- store i32 0, i32* @no_mis, align 4
- %1 = getelementptr i8, i8* %A, i32 0 ; <i8*> [#uses=1]
- %2 = getelementptr i8, i8* %B, i32 0 ; <i8*> [#uses=1]
- tail call void @
diff (i8* %1, i8* %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind
+ store i32 0, ptr @no_mis, align 4
+ %1 = getelementptr i8, ptr %A, i32 0 ; <ptr> [#uses=1]
+ %2 = getelementptr i8, ptr %B, i32 0 ; <ptr> [#uses=1]
+ tail call void @
diff (ptr %1, ptr %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind
br i1 undef, label %bb15, label %bb12
bb12: ; preds = %bb11
- %3 = load i32*, i32** @II, align 4 ; <i32*> [#uses=1]
- %4 = load i32, i32* @r, align 4 ; <i32> [#uses=1]
- %5 = load i32, i32* @qr, align 4 ; <i32> [#uses=1]
+ %3 = load ptr, ptr @II, align 4 ; <ptr> [#uses=1]
+ %4 = load i32, ptr @r, align 4 ; <i32> [#uses=1]
+ %5 = load i32, ptr @qr, align 4 ; <i32> [#uses=1]
br label %bb228.i
bb74.i: ; preds = %bb228.i
@@ -95,12 +95,12 @@ bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
%fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; <i32> [#uses=2]
%fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2]
%f.5.i = phi i32 [ %7, %bb167.i ], [ %8, %bb158.i ], [ %7, %bb160.i ], [ %7, %bb161.i ], [ %7, %bb163.i ] ; <i32> [#uses=2]
- %scevgep88.i = getelementptr i32, i32* %3, i32 undef ; <i32*> [#uses=1]
+ %scevgep88.i = getelementptr i32, ptr %3, i32 undef ; <ptr> [#uses=1]
%ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; <i32> [#uses=0]
%ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; <i32> [#uses=1]
%cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; <i32> [#uses=1]
%c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1]
- %10 = load i32, i32* %scevgep88.i, align 4 ; <i32> [#uses=1]
+ %10 = load i32, ptr %scevgep88.i, align 4 ; <i32> [#uses=1]
br i1 undef, label %bb211.i, label %bb218.i
bb211.i: ; preds = %bb168.i
@@ -110,8 +110,8 @@ bb218.i: ; preds = %bb211.i, %bb168.i
br i1 undef, label %bb220.i, label %bb158.i
bb220.i: ; preds = %bb218.i, %bb153.i
- %11 = getelementptr i32, i32* null, i32 %6 ; <i32*> [#uses=1]
- store i32 undef, i32* %11, align 4
+ %11 = getelementptr i32, ptr null, i32 %6 ; <ptr> [#uses=1]
+ store i32 undef, ptr %11, align 4
br i1 undef, label %bb221.i, label %bb228.i
bb221.i: ; preds = %bb220.i
diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
index 4306210bc5a3a..bfed01b20ccaf 100644
--- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
+++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
@@ -1,8 +1,8 @@
; RUN: llc < %s -mtriple=armv6-apple-darwin9
- at XX = external global i32* ; <i32**> [#uses=1]
+ at XX = external global ptr ; <ptr> [#uses=1]
-define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
+define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
entry:
br i1 undef, label %bb5, label %bb
@@ -28,7 +28,7 @@ bb11: ; preds = %bb9
br i1 undef, label %bb15, label %bb12
bb12: ; preds = %bb11
- %0 = load i32*, i32** @XX, align 4 ; <i32*> [#uses=0]
+ %0 = load ptr, ptr @XX, align 4 ; <ptr> [#uses=0]
br label %bb228.i
bb74.i: ; preds = %bb228.i
@@ -72,8 +72,8 @@ bb167.i: ; preds = %bb163.i
bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
%f.5.i = phi i32 [ %1, %bb167.i ], [ %2, %bb158.i ], [ %1, %bb160.i ], [ %1, %bb161.i ], [ %1, %bb163.i ] ; <i32> [#uses=1]
%c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1]
- store i32 %c.14.i, i32* undef, align 4
- store i32 undef, i32* null, align 4
+ store i32 %c.14.i, ptr undef, align 4
+ store i32 undef, ptr null, align 4
br i1 undef, label %bb211.i, label %bb218.i
bb211.i: ; preds = %bb168.i
diff --git a/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll b/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll
index 730d3a302ae27..9e5ad950a98c2 100644
--- a/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll
+++ b/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll
@@ -1,10 +1,10 @@
; RUN: llc < %s -mtriple=armv6-apple-darwin9
- at qr = external global i32 ; <i32*> [#uses=1]
- at II = external global i32* ; <i32**> [#uses=1]
- at JJ = external global i32* ; <i32**> [#uses=1]
+ at qr = external global i32 ; <ptr> [#uses=1]
+ at II = external global ptr ; <ptr> [#uses=1]
+ at JJ = external global ptr ; <ptr> [#uses=1]
-define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
+define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
entry:
br i1 undef, label %bb5, label %bb
@@ -30,9 +30,9 @@ bb11: ; preds = %bb9
br i1 undef, label %bb15, label %bb12
bb12: ; preds = %bb11
- %0 = load i32*, i32** @II, align 4 ; <i32*> [#uses=1]
- %1 = load i32*, i32** @JJ, align 4 ; <i32*> [#uses=1]
- %2 = load i32, i32* @qr, align 4 ; <i32> [#uses=1]
+ %0 = load ptr, ptr @II, align 4 ; <ptr> [#uses=1]
+ %1 = load ptr, ptr @JJ, align 4 ; <ptr> [#uses=1]
+ %2 = load i32, ptr @qr, align 4 ; <i32> [#uses=1]
br label %bb228.i
bb74.i: ; preds = %bb228.i
@@ -90,17 +90,17 @@ bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
%fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; <i32> [#uses=2]
%fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2]
%f.5.i = phi i32 [ %3, %bb167.i ], [ %4, %bb158.i ], [ %3, %bb160.i ], [ %3, %bb161.i ], [ %3, %bb163.i ] ; <i32> [#uses=2]
- %scevgep88.i = getelementptr i32, i32* %0, i32 undef ; <i32*> [#uses=2]
- %scevgep89.i = getelementptr i32, i32* %1, i32 undef ; <i32*> [#uses=2]
+ %scevgep88.i = getelementptr i32, ptr %0, i32 undef ; <ptr> [#uses=2]
+ %scevgep89.i = getelementptr i32, ptr %1, i32 undef ; <ptr> [#uses=2]
%ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; <i32> [#uses=0]
%cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef ; <i32> [#uses=0]
%ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; <i32> [#uses=2]
%cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; <i32> [#uses=2]
%c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1]
- %6 = load i32, i32* %scevgep88.i, align 4 ; <i32> [#uses=1]
- %7 = load i32, i32* %scevgep89.i, align 4 ; <i32> [#uses=1]
- store i32 %ci.12.i, i32* %scevgep88.i, align 4
- store i32 %cj.11.i100, i32* %scevgep89.i, align 4
+ %6 = load i32, ptr %scevgep88.i, align 4 ; <i32> [#uses=1]
+ %7 = load i32, ptr %scevgep89.i, align 4 ; <i32> [#uses=1]
+ store i32 %ci.12.i, ptr %scevgep88.i, align 4
+ store i32 %cj.11.i100, ptr %scevgep89.i, align 4
br i1 undef, label %bb211.i, label %bb218.i
bb211.i: ; preds = %bb168.i
diff --git a/llvm/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll b/llvm/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll
index 3cef0aa546a5a..a52b3fa3f900f 100644
--- a/llvm/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll
+++ b/llvm/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null
-define void @test(i8* %x) nounwind {
+define void @test(ptr %x) nounwind {
entry:
- call void asm sideeffect "pld\09${0:a}", "r,~{cc}"(i8* %x) nounwind
+ call void asm sideeffect "pld\09${0:a}", "r,~{cc}"(ptr %x) nounwind
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll
index d746b104baf8e..3da7c470b2de2 100644
--- a/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll
+++ b/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll
@@ -1,14 +1,14 @@
; RUN: llc < %s -mtriple=armv6-apple-darwin10
- %struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* }
- %struct.cli_ac_node = type { i8, i8, %struct.cli_ac_patt*, %struct.cli_ac_node**, %struct.cli_ac_node* }
- %struct.cli_ac_patt = type { i16*, i16*, i16, i16, i8, i32, i32, i8*, i8*, i32, i16, i16, i16, i16, %struct.cli_ac_alt**, i8, i16, %struct.cli_ac_patt*, %struct.cli_ac_patt* }
- %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 }
- %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 }
+ %struct.cli_ac_alt = type { i8, ptr, i16, i16, ptr }
+ %struct.cli_ac_node = type { i8, i8, ptr, ptr, ptr }
+ %struct.cli_ac_patt = type { ptr, ptr, i16, i16, i8, i32, i32, ptr, ptr, i32, i16, i16, i16, i16, ptr, i8, i16, ptr, ptr }
+ %struct.cli_bm_patt = type { ptr, ptr, i16, i16, ptr, ptr, i8, ptr, i16 }
+ %struct.cli_matcher = type { i16, i8, ptr, ptr, ptr, i32, i8, i8, ptr, ptr, ptr, i32, i32, i32 }
-declare i32 @strlen(i8* nocapture) nounwind readonly
+declare i32 @strlen(ptr nocapture) nounwind readonly
-define i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind {
+define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target) nounwind {
entry:
br i1 undef, label %bb126, label %bb1
@@ -19,7 +19,7 @@ cli_calloc.exit.thread: ; preds = %bb1
ret i32 -114
cli_calloc.exit: ; preds = %bb1
- store i16 %parts, i16* undef, align 4
+ store i16 %parts, ptr undef, align 4
br i1 undef, label %bb52, label %bb4
bb4: ; preds = %cli_calloc.exit
@@ -83,10 +83,10 @@ bb45: ; preds = %bb43.preheader, %cli_calloc.exit54
br i1 undef, label %cli_calloc.exit70.thread, label %cli_calloc.exit70
bb52: ; preds = %cli_calloc.exit
- %0 = load i16, i16* undef, align 4 ; <i16> [#uses=1]
+ %0 = load i16, ptr undef, align 4 ; <i16> [#uses=1]
%1 = icmp eq i16 %0, 0 ; <i1> [#uses=1]
- %iftmp.20.0 = select i1 %1, i8* %hexsig, i8* null ; <i8*> [#uses=1]
- %2 = tail call i32 @strlen(i8* %iftmp.20.0) nounwind readonly ; <i32> [#uses=0]
+ %iftmp.20.0 = select i1 %1, ptr %hexsig, ptr null ; <ptr> [#uses=1]
+ %2 = tail call i32 @strlen(ptr %iftmp.20.0) nounwind readonly ; <i32> [#uses=0]
unreachable
bb126: ; preds = %entry
diff --git a/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll b/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
index 156fd8843bcf6..e2a284813ebc1 100644
--- a/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
+++ b/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
@@ -1,12 +1,12 @@
; RUN: llc -mtriple=arm-eabi %s -o /dev/null
- %struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* }
- %struct.cli_ac_node = type { i8, i8, %struct.cli_ac_patt*, %struct.cli_ac_node**, %struct.cli_ac_node* }
- %struct.cli_ac_patt = type { i16*, i16*, i16, i16, i8, i32, i32, i8*, i8*, i32, i16, i16, i16, i16, %struct.cli_ac_alt**, i8, i16, %struct.cli_ac_patt*, %struct.cli_ac_patt* }
- %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 }
- %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 }
+ %struct.cli_ac_alt = type { i8, ptr, i16, i16, ptr }
+ %struct.cli_ac_node = type { i8, i8, ptr, ptr, ptr }
+ %struct.cli_ac_patt = type { ptr, ptr, i16, i16, i8, i32, i32, ptr, ptr, i32, i16, i16, i16, i16, ptr, i8, i16, ptr, ptr }
+ %struct.cli_bm_patt = type { ptr, ptr, i16, i16, ptr, ptr, i8, ptr, i16 }
+ %struct.cli_matcher = type { i16, i8, ptr, ptr, ptr, i32, i8, i8, ptr, ptr, ptr, i32, i32, i32 }
-define i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind {
+define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target) nounwind {
entry:
br i1 undef, label %bb126, label %bb1
@@ -65,15 +65,14 @@ bb18: ; preds = %bb18, %bb.nph
br i1 undef, label %bb18, label %bb22
bb22: ; preds = %bb18, %bb17
- %0 = getelementptr i8, i8* null, i32 10 ; <i8*> [#uses=1]
- %1 = bitcast i8* %0 to i16* ; <i16*> [#uses=1]
- %2 = load i16, i16* %1, align 2 ; <i16> [#uses=1]
- %3 = add i16 %2, 1 ; <i16> [#uses=1]
- %4 = zext i16 %3 to i32 ; <i32> [#uses=1]
- %5 = mul i32 %4, 3 ; <i32> [#uses=1]
- %6 = add i32 %5, -1 ; <i32> [#uses=1]
- %7 = icmp eq i32 %6, undef ; <i1> [#uses=1]
- br i1 %7, label %bb25, label %bb43.preheader
+ %0 = getelementptr i8, ptr null, i32 10 ; <ptr> [#uses=1]
+ %1 = load i16, ptr %0, align 2 ; <i16> [#uses=1]
+ %2 = add i16 %1, 1 ; <i16> [#uses=1]
+ %3 = zext i16 %2 to i32 ; <i32> [#uses=1]
+ %4 = mul i32 %3, 3 ; <i32> [#uses=1]
+ %5 = add i32 %4, -1 ; <i32> [#uses=1]
+ %6 = icmp eq i32 %5, undef ; <i1> [#uses=1]
+ br i1 %6, label %bb25, label %bb43.preheader
bb43.preheader: ; preds = %bb22
br i1 undef, label %bb28, label %bb45
diff --git a/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll b/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll
index 01591c80362da..c44681ab13084 100644
--- a/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll
+++ b/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll
@@ -1,10 +1,10 @@
; RUN: llc < %s -mtriple=armv7-apple-darwin10 -mattr=+vfp3
- at a = external global double ; <double*> [#uses=1]
+ at a = external global double ; <ptr> [#uses=1]
declare double @llvm.exp.f64(double) nounwind readonly
-define void @findratio(double* nocapture %res1, double* nocapture %res2) nounwind {
+define void @findratio(ptr nocapture %res1, ptr nocapture %res2) nounwind {
entry:
br label %bb
@@ -12,7 +12,7 @@ bb: ; preds = %bb, %entry
br i1 undef, label %bb28, label %bb
bb28: ; preds = %bb
- %0 = load double, double* @a, align 4 ; <double> [#uses=2]
+ %0 = load double, ptr @a, align 4 ; <double> [#uses=2]
%1 = fadd double %0, undef ; <double> [#uses=2]
br i1 undef, label %bb59, label %bb60
diff --git a/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll b/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
index 8ead42d82c7c6..b87f4f86d67de 100644
--- a/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
+++ b/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
@@ -6,24 +6,24 @@ target triple = "armv7-apple-darwin9"
define <4 x i32> @scale(<4 x i32> %v, i32 %f) nounwind {
entry:
- %v_addr = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
- %f_addr = alloca i32 ; <i32*> [#uses=2]
- %retval = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
- %0 = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
+ %v_addr = alloca <4 x i32> ; <ptr> [#uses=2]
+ %f_addr = alloca i32 ; <ptr> [#uses=2]
+ %retval = alloca <4 x i32> ; <ptr> [#uses=2]
+ %0 = alloca <4 x i32> ; <ptr> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
- store <4 x i32> %v, <4 x i32>* %v_addr
- store i32 %f, i32* %f_addr
- %1 = load <4 x i32>, <4 x i32>* %v_addr, align 16 ; <<4 x i32>> [#uses=1]
- %2 = load i32, i32* %f_addr, align 4 ; <i32> [#uses=1]
+ store <4 x i32> %v, ptr %v_addr
+ store i32 %f, ptr %f_addr
+ %1 = load <4 x i32>, ptr %v_addr, align 16 ; <<4 x i32>> [#uses=1]
+ %2 = load i32, ptr %f_addr, align 4 ; <i32> [#uses=1]
%3 = insertelement <4 x i32> undef, i32 %2, i32 0 ; <<4 x i32>> [#uses=1]
%4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>> [#uses=1]
%5 = mul <4 x i32> %1, %4 ; <<4 x i32>> [#uses=1]
- store <4 x i32> %5, <4 x i32>* %0, align 16
- %6 = load <4 x i32>, <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1]
- store <4 x i32> %6, <4 x i32>* %retval, align 16
+ store <4 x i32> %5, ptr %0, align 16
+ %6 = load <4 x i32>, ptr %0, align 16 ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %6, ptr %retval, align 16
br label %return
return: ; preds = %entry
- %retval1 = load <4 x i32>, <4 x i32>* %retval ; <<4 x i32>> [#uses=1]
+ %retval1 = load <4 x i32>, ptr %retval ; <<4 x i32>> [#uses=1]
ret <4 x i32> %retval1
}
diff --git a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll
index 30975225c3eda..22fe8ea7a4774 100644
--- a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll
+++ b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll
@@ -4,7 +4,7 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv6-elf"
-define i32 @file_read_actor(i32* nocapture %desc, i32* %page, i32 %offset, i32 %size) nounwind optsize {
+define i32 @file_read_actor(ptr nocapture %desc, ptr %page, i32 %offset, i32 %size) nounwind optsize {
entry:
br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i
@@ -26,8 +26,8 @@ bb2: ; preds = %fault_in_pages_writeable.exit
unreachable
bb3: ; preds = %fault_in_pages_writeable.exit
- %1 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; <i32> [#uses=0]
+ %1 = tail call i32 @__copy_to_user(ptr undef, ptr undef, i32 undef) nounwind ; <i32> [#uses=0]
unreachable
}
-declare i32 @__copy_to_user(i8*, i8*, i32)
+declare i32 @__copy_to_user(ptr, ptr, i32)
diff --git a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll
index d666f12b86a40..9ee9ec48b03a5 100644
--- a/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll
+++ b/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll
@@ -18,8 +18,8 @@ bb2: ; preds = %fault_in_pages_writeable.exit
unreachable
bb3: ; preds = %fault_in_pages_writeable.exit
- %2 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; <i32> [#uses=0]
+ %2 = tail call i32 @__copy_to_user(ptr undef, ptr undef, i32 undef) nounwind ; <i32> [#uses=0]
unreachable
}
-declare i32 @__copy_to_user(i8*, i8*, i32)
+declare i32 @__copy_to_user(ptr, ptr, i32)
diff --git a/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll b/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
index a5e9692a0082d..a23100a36eff1 100644
--- a/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
+++ b/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
@@ -4,9 +4,9 @@
; Inline asm is allowed to contain operands "=&r", "0".
%struct.device_dma_parameters = type { i32, i32 }
-%struct.iovec = type { i8*, i32 }
+%struct.iovec = type { ptr, i32 }
-define i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize {
+define i32 @generic_segment_checks(ptr nocapture %iov, ptr nocapture %nr_segs, ptr nocapture %count, i32 %access_flags) nounwind optsize {
entry:
br label %bb8
@@ -14,7 +14,7 @@ bb: ; preds = %bb8
br i1 undef, label %bb10, label %bb2
bb2: ; preds = %bb
- %asmtmp = tail call %struct.device_dma_parameters asm "adds $1, $2, $3; sbcccs $1, $1, $0; movcc $0, #0", "=&r,=&r,r,Ir,0,~{cc}"(i8* undef, i32 undef, i32 0) nounwind; <%struct.device_dma_parameters> [#uses=1]
+ %asmtmp = tail call %struct.device_dma_parameters asm "adds $1, $2, $3; sbcccs $1, $1, $0; movcc $0, #0", "=&r,=&r,r,Ir,0,~{cc}"(ptr undef, i32 undef, i32 0) nounwind; <%struct.device_dma_parameters> [#uses=1]
%asmresult = extractvalue %struct.device_dma_parameters %asmtmp, 0; <i32> [#uses=1]
%0 = icmp eq i32 %asmresult, 0 ; <i1> [#uses=1]
br i1 %0, label %bb7, label %bb4
@@ -28,13 +28,13 @@ bb7: ; preds = %bb2
bb8: ; preds = %bb7, %entry
%2 = phi i32 [ 0, %entry ], [ %1, %bb7 ] ; <i32> [#uses=3]
- %scevgep22 = getelementptr %struct.iovec, %struct.iovec* %iov, i32 %2, i32 0; <i8**> [#uses=0]
- %3 = load i32, i32* %nr_segs, align 4 ; <i32> [#uses=1]
+ %scevgep22 = getelementptr %struct.iovec, ptr %iov, i32 %2, i32 0; <ptr> [#uses=0]
+ %3 = load i32, ptr %nr_segs, align 4 ; <i32> [#uses=1]
%4 = icmp ult i32 %2, %3 ; <i1> [#uses=1]
br i1 %4, label %bb, label %bb9
bb9: ; preds = %bb8, %bb4
- store i32 undef, i32* %count, align 4
+ store i32 undef, ptr %count, align 4
ret i32 0
bb10: ; preds = %bb4, %bb
diff --git a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
index dea582968e957..c759fb07ed113 100644
--- a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
+++ b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
@@ -4,23 +4,23 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv7-apple-darwin9"
-%struct.tree = type { i32, double, double, %struct.tree*, %struct.tree*, %struct.tree*, %struct.tree* }
- at g = common global %struct.tree* null
+%struct.tree = type { i32, double, double, ptr, ptr, ptr, ptr }
+ at g = common global ptr null
-define %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind {
+define ptr @tsp(ptr %t, i32 %nproc) nounwind {
entry:
- %t.idx51.val.i = load double, double* null ; <double> [#uses=1]
+ %t.idx51.val.i = load double, ptr null ; <double> [#uses=1]
br i1 undef, label %bb4.i, label %bb.i
bb.i: ; preds = %entry
unreachable
bb4.i: ; preds = %entry
- %0 = load %struct.tree*, %struct.tree** @g, align 4 ; <%struct.tree*> [#uses=2]
- %.idx45.i = getelementptr %struct.tree, %struct.tree* %0, i32 0, i32 1 ; <double*> [#uses=1]
- %.idx45.val.i = load double, double* %.idx45.i ; <double> [#uses=1]
- %.idx46.i = getelementptr %struct.tree, %struct.tree* %0, i32 0, i32 2 ; <double*> [#uses=1]
- %.idx46.val.i = load double, double* %.idx46.i ; <double> [#uses=1]
+ %0 = load ptr, ptr @g, align 4 ; <ptr> [#uses=2]
+ %.idx45.i = getelementptr %struct.tree, ptr %0, i32 0, i32 1 ; <ptr> [#uses=1]
+ %.idx45.val.i = load double, ptr %.idx45.i ; <double> [#uses=1]
+ %.idx46.i = getelementptr %struct.tree, ptr %0, i32 0, i32 2 ; <ptr> [#uses=1]
+ %.idx46.val.i = load double, ptr %.idx46.i ; <double> [#uses=1]
%1 = fsub double 0.000000e+00, %.idx45.val.i ; <double> [#uses=2]
%2 = fmul double %1, %1 ; <double> [#uses=1]
%3 = fsub double %t.idx51.val.i, %.idx46.val.i ; <double> [#uses=2]
diff --git a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
index 4aa46d0000ced..9aad73c771ad5 100644
--- a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
+++ b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
@@ -4,14 +4,14 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv7-apple-darwin9"
-%struct.anon = type { [3 x double], double, %struct.node*, [64 x %struct.bnode*], [64 x %struct.bnode*] }
-%struct.bnode = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, %struct.bnode*, %struct.bnode* }
+%struct.anon = type { [3 x double], double, ptr, [64 x ptr], [64 x ptr] }
+%struct.bnode = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, ptr, ptr }
%struct.icstruct = type { [3 x i32], i16 }
%struct.node = type { i16, double, [3 x double], i32, i32 }
declare double @floor(double) nounwind readnone
-define void @intcoord(%struct.icstruct* noalias nocapture sret(%struct.icstruct) %agg.result, i1 %a, double %b) {
+define void @intcoord(ptr noalias nocapture sret(%struct.icstruct) %agg.result, i1 %a, double %b) {
entry:
br i1 %a, label %bb3, label %bb1
@@ -32,7 +32,7 @@ bb9: ; preds = %bb7
br label %bb11
bb11: ; preds = %bb9, %bb7
- %1 = getelementptr %struct.icstruct, %struct.icstruct* %agg.result, i32 0, i32 0, i32 0 ; <i32*> [#uses=1]
- store i32 0, i32* %1
+ %1 = getelementptr %struct.icstruct, ptr %agg.result, i32 0, i32 0, i32 0 ; <ptr> [#uses=1]
+ store i32 0, ptr %1
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
index b7a252beefbda..88fcae29c09fa 100644
--- a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
+++ b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
@@ -5,29 +5,28 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f3
target triple = "armv7-apple-darwin9"
%struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List }
-%struct.List = type { %struct.List*, %struct.Patient*, %struct.List* }
-%struct.Patient = type { i32, i32, i32, %struct.Village* }
-%struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 }
+%struct.List = type { ptr, ptr, ptr }
+%struct.Patient = type { i32, i32, i32, ptr }
+%struct.Village = type { [4 x ptr], ptr, %struct.List, %struct.Hosp, i32, i32 }
-define %struct.Village* @alloc_tree(i32 %level, i32 %label, %struct.Village* %back, i1 %p) nounwind {
+define ptr @alloc_tree(i32 %level, i32 %label, ptr %back, i1 %p) nounwind {
entry:
br i1 %p, label %bb8, label %bb1
bb1: ; preds = %entry
- %malloccall = tail call i8* @malloc(i32 ptrtoint (%struct.Village* getelementptr (%struct.Village, %struct.Village* null, i32 1) to i32))
- %0 = bitcast i8* %malloccall to %struct.Village*
+ %malloccall = tail call ptr @malloc(i32 ptrtoint (ptr getelementptr (%struct.Village, ptr null, i32 1) to i32))
%exp2 = call double @ldexp(double 1.000000e+00, i32 %level) nounwind ; <double> [#uses=1]
%.c = fptosi double %exp2 to i32 ; <i32> [#uses=1]
- store i32 %.c, i32* null
- %1 = getelementptr %struct.Village, %struct.Village* %0, i32 0, i32 3, i32 6, i32 0 ; <%struct.List**> [#uses=1]
- store %struct.List* null, %struct.List** %1
- %2 = getelementptr %struct.Village, %struct.Village* %0, i32 0, i32 3, i32 6, i32 2 ; <%struct.List**> [#uses=1]
- store %struct.List* null, %struct.List** %2
- ret %struct.Village* %0
+ store i32 %.c, ptr null
+ %0 = getelementptr %struct.Village, ptr %malloccall, i32 0, i32 3, i32 6, i32 0 ; <ptr> [#uses=1]
+ store ptr null, ptr %0
+ %1 = getelementptr %struct.Village, ptr %malloccall, i32 0, i32 3, i32 6, i32 2 ; <ptr> [#uses=1]
+ store ptr null, ptr %1
+ ret ptr %malloccall
bb8: ; preds = %entry
- ret %struct.Village* null
+ ret ptr null
}
declare double @ldexp(double, i32)
-declare noalias i8* @malloc(i32)
+declare noalias ptr @malloc(i32)
diff --git a/llvm/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll b/llvm/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll
index 773f7c71e3b94..c9ac8f0e8032e 100644
--- a/llvm/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll
+++ b/llvm/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll
@@ -6,12 +6,12 @@ target triple = "thumbv7-elf"
%bar = type { float, float, float }
%baz = type { i32, [16 x %bar], [16 x float], [16 x i32], i8 }
%foo = type { <4 x float> }
-%quux = type { i32 (...)**, %baz*, i32 }
+%quux = type { ptr, ptr, i32 }
%quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo }
declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-define void @_ZN6squish10ClusterFit9Compress3EPv(%quuz* %this, i8* %block) {
+define void @_ZN6squish10ClusterFit9Compress3EPv(ptr %this, ptr %block) {
entry:
%0 = lshr <4 x i32> zeroinitializer, <i32 31, i32 31, i32 31, i32 31>
%1 = shufflevector <4 x i32> %0, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
diff --git a/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll b/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll
index d3e8340808447..8b0743ad390c1 100644
--- a/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll
+++ b/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll
@@ -6,10 +6,10 @@ target triple = "thumbv7-elf"
%bar = type { float, float, float }
%baz = type { i32, [16 x %bar], [16 x float], [16 x i32], i8 }
%foo = type { <4 x float> }
-%quux = type { i32 (...)**, %baz*, i32 }
+%quux = type { ptr, ptr, i32 }
%quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo }
-define void @aaaa(%quuz* %this, i8* %block) {
+define void @aaaa(ptr %this, ptr %block) {
entry:
br i1 undef, label %bb.nph269, label %bb201
diff --git a/llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll b/llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll
index 54db3a8b9016f..73859a8be5758 100644
--- a/llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll
+++ b/llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll
@@ -7,85 +7,81 @@
; CHECK: [[LSDA_LABEL]]:
; CHECK: .byte 255 @ @LPStart Encoding = omit
-%struct.A = type { i32* }
+%struct.A = type { ptr }
-define void @"\01-[MyFunction Name:]"() personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
+define void @"\01-[MyFunction Name:]"() personality ptr @__gxx_personality_sj0 {
entry:
%save_filt.1 = alloca i32
- %save_eptr.0 = alloca i8*
+ %save_eptr.0 = alloca ptr
%a = alloca %struct.A
- %eh_exception = alloca i8*
+ %eh_exception = alloca ptr
%eh_selector = alloca i32
%"alloca point" = bitcast i32 0 to i32
- call void @_ZN1AC1Ev(%struct.A* %a)
+ call void @_ZN1AC1Ev(ptr %a)
invoke void @_Z3barv()
to label %invcont unwind label %lpad
invcont: ; preds = %entry
- call void @_ZN1AD1Ev(%struct.A* %a) nounwind
+ call void @_ZN1AD1Ev(ptr %a) nounwind
br label %return
bb: ; preds = %ppad
- %eh_select = load i32, i32* %eh_selector
- store i32 %eh_select, i32* %save_filt.1, align 4
- %eh_value = load i8*, i8** %eh_exception
- store i8* %eh_value, i8** %save_eptr.0, align 4
- call void @_ZN1AD1Ev(%struct.A* %a) nounwind
- %0 = load i8*, i8** %save_eptr.0, align 4
- store i8* %0, i8** %eh_exception, align 4
- %1 = load i32, i32* %save_filt.1, align 4
- store i32 %1, i32* %eh_selector, align 4
+ %eh_select = load i32, ptr %eh_selector
+ store i32 %eh_select, ptr %save_filt.1, align 4
+ %eh_value = load ptr, ptr %eh_exception
+ store ptr %eh_value, ptr %save_eptr.0, align 4
+ call void @_ZN1AD1Ev(ptr %a) nounwind
+ %0 = load ptr, ptr %save_eptr.0, align 4
+ store ptr %0, ptr %eh_exception, align 4
+ %1 = load i32, ptr %save_filt.1, align 4
+ store i32 %1, ptr %eh_selector, align 4
br label %Unwind
return: ; preds = %invcont
ret void
lpad: ; preds = %entry
- %exn = landingpad {i8*, i32}
+ %exn = landingpad {ptr, i32}
cleanup
- %eh_ptr = extractvalue {i8*, i32} %exn, 0
- store i8* %eh_ptr, i8** %eh_exception
- %eh_select2 = extractvalue {i8*, i32} %exn, 1
- store i32 %eh_select2, i32* %eh_selector
+ %eh_ptr = extractvalue {ptr, i32} %exn, 0
+ store ptr %eh_ptr, ptr %eh_exception
+ %eh_select2 = extractvalue {ptr, i32} %exn, 1
+ store i32 %eh_select2, ptr %eh_selector
br label %ppad
ppad: ; preds = %lpad
br label %bb
Unwind: ; preds = %bb
- %eh_ptr3 = load i8*, i8** %eh_exception
- call void @_Unwind_SjLj_Resume(i8* %eh_ptr3)
+ %eh_ptr3 = load ptr, ptr %eh_exception
+ call void @_Unwind_SjLj_Resume(ptr %eh_ptr3)
unreachable
}
-define linkonce_odr void @_ZN1AC1Ev(%struct.A* %this) {
+define linkonce_odr void @_ZN1AC1Ev(ptr %this) {
entry:
- %this_addr = alloca %struct.A*
+ %this_addr = alloca ptr
%"alloca point" = bitcast i32 0 to i32
- store %struct.A* %this, %struct.A** %this_addr
- %0 = call i8* @_Znwm(i32 4)
- %1 = bitcast i8* %0 to i32*
- %2 = load %struct.A*, %struct.A** %this_addr, align 4
- %3 = getelementptr inbounds %struct.A, %struct.A* %2, i32 0, i32 0
- store i32* %1, i32** %3, align 4
+ store ptr %this, ptr %this_addr
+ %0 = call ptr @_Znwm(i32 4)
+ %1 = load ptr, ptr %this_addr, align 4
+ store ptr %0, ptr %1, align 4
br label %return
return: ; preds = %entry
ret void
}
-declare i8* @_Znwm(i32)
+declare ptr @_Znwm(i32)
-define linkonce_odr void @_ZN1AD1Ev(%struct.A* %this) nounwind {
+define linkonce_odr void @_ZN1AD1Ev(ptr %this) nounwind {
entry:
- %this_addr = alloca %struct.A*
+ %this_addr = alloca ptr
%"alloca point" = bitcast i32 0 to i32
- store %struct.A* %this, %struct.A** %this_addr
- %0 = load %struct.A*, %struct.A** %this_addr, align 4
- %1 = getelementptr inbounds %struct.A, %struct.A* %0, i32 0, i32 0
- %2 = load i32*, i32** %1, align 4
- %3 = bitcast i32* %2 to i8*
- call void @_ZdlPv(i8* %3) nounwind
+ store ptr %this, ptr %this_addr
+ %0 = load ptr, ptr %this_addr, align 4
+ %1 = load ptr, ptr %0, align 4
+ call void @_ZdlPv(ptr %1) nounwind
br label %bb
bb: ; preds = %entry
@@ -95,12 +91,12 @@ return: ; preds = %bb
ret void
}
-declare void @_ZdlPv(i8*) nounwind
+declare void @_ZdlPv(ptr) nounwind
declare void @_Z3barv()
-declare i32 @llvm.eh.typeid.for(i8*) nounwind
+declare i32 @llvm.eh.typeid.for(ptr) nounwind
declare i32 @__gxx_personality_sj0(...)
-declare void @_Unwind_SjLj_Resume(i8*)
+declare void @_Unwind_SjLj_Resume(ptr)
diff --git a/llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll b/llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
index a6d128d9e0ce6..45e0108f253c9 100644
--- a/llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
+++ b/llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
@@ -1,10 +1,10 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
; pr4843
-define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind {
+define <4 x i16> @v2regbug(ptr %B) nounwind {
;CHECK-LABEL: v2regbug:
;CHECK: vzip.16
- %tmp1 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %B
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32><i32 0, i32 0, i32 1, i32 1>
ret <4 x i16> %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/2009-09-09-AllOnes.ll b/llvm/test/CodeGen/ARM/2009-09-09-AllOnes.ll
index 8522a779a42c4..318f9549bae7f 100644
--- a/llvm/test/CodeGen/ARM/2009-09-09-AllOnes.ll
+++ b/llvm/test/CodeGen/ARM/2009-09-09-AllOnes.ll
@@ -5,6 +5,6 @@ target triple = "thumbv7-elf"
define void @foo() {
entry:
%0 = insertelement <4 x i32> undef, i32 -1, i32 3
- store <4 x i32> %0, <4 x i32>* undef, align 16
+ store <4 x i32> %0, ptr undef, align 16
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll b/llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
index 3117b809e30a4..d6405a25b75c3 100644
--- a/llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
+++ b/llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
@@ -1,16 +1,16 @@
; RUN: llc -O1 -mattr=+vfp2 -mtriple=arm-linux-gnueabi < %s | FileCheck %s
; pr4939
-define void @test(double* %x, double* %y) nounwind {
- %1 = load double, double* %x
- %2 = load double, double* %y
+define void @test(ptr %x, ptr %y) nounwind {
+ %1 = load double, ptr %x
+ %2 = load double, ptr %y
%3 = fsub double -0.000000e+00, %1
%4 = fcmp ugt double %2, %3
br i1 %4, label %bb1, label %bb2
bb1:
;CHECK: vstrhi
- store double %1, double* %y
+ store double %1, ptr %y
br label %bb2
bb2:
diff --git a/llvm/test/CodeGen/ARM/2009-09-10-postdec.ll b/llvm/test/CodeGen/ARM/2009-09-10-postdec.ll
index 66ffe6a1a0fbf..8a27eca41f1ff 100644
--- a/llvm/test/CodeGen/ARM/2009-09-10-postdec.ll
+++ b/llvm/test/CodeGen/ARM/2009-09-10-postdec.ll
@@ -1,11 +1,11 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
; Radar 7213850
-define i32 @test(i8* %d, i32 %x, i32 %y) nounwind {
- %1 = ptrtoint i8* %d to i32
+define i32 @test(ptr %d, i32 %x, i32 %y) nounwind {
+ %1 = ptrtoint ptr %d to i32
;CHECK: sub
%2 = sub i32 %x, %1
%3 = add nsw i32 %2, %y
- store i8 0, i8* %d, align 1
+ store i8 0, ptr %d, align 1
ret i32 %3
}
diff --git a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll
index de927a8f8b662..b701c00ca50b1 100644
--- a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll
+++ b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll
@@ -11,12 +11,12 @@ target triple = "armv7-eabi"
declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
-define arm_aapcs_vfpcc i8 @foo(%struct.fr* nocapture %this, %struct.obb* %box) nounwind {
+define arm_aapcs_vfpcc i8 @foo(ptr nocapture %this, ptr %box) nounwind {
entry:
- %val.i.i = load <4 x float>, <4 x float>* undef ; <<4 x float>> [#uses=1]
- %val2.i.i = load <4 x float>, <4 x float>* null ; <<4 x float>> [#uses=1]
- %elt3.i.i = getelementptr inbounds %struct.obb, %struct.obb* %box, i32 0, i32 0, i32 2, i32 0 ; <<4 x float>*> [#uses=1]
- %val4.i.i = load <4 x float>, <4 x float>* %elt3.i.i ; <<4 x float>> [#uses=1]
+ %val.i.i = load <4 x float>, ptr undef ; <<4 x float>> [#uses=1]
+ %val2.i.i = load <4 x float>, ptr null ; <<4 x float>> [#uses=1]
+ %elt3.i.i = getelementptr inbounds %struct.obb, ptr %box, i32 0, i32 0, i32 2, i32 0 ; <ptr> [#uses=1]
+ %val4.i.i = load <4 x float>, ptr %elt3.i.i ; <<4 x float>> [#uses=1]
%0 = shufflevector <2 x float> undef, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
%1 = fadd <4 x float> undef, zeroinitializer ; <<4 x float>> [#uses=1]
br label %bb33
diff --git a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll
index b8a1479fd34c9..c57965fc6eb67 100644
--- a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll
+++ b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll
@@ -1,28 +1,28 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a9 %s -o /dev/null
-define arm_aapcs_vfpcc <4 x float> @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind {
- %1 = ptrtoint i8* %pBuffer to i32
+define arm_aapcs_vfpcc <4 x float> @foo(ptr nocapture %pBuffer, i32 %numItems) nounwind {
+ %1 = ptrtoint ptr %pBuffer to i32
- %lsr.iv2641 = inttoptr i32 %1 to float*
+ %lsr.iv2641 = inttoptr i32 %1 to ptr
%tmp29 = add i32 %1, 4
- %tmp2930 = inttoptr i32 %tmp29 to float*
+ %tmp2930 = inttoptr i32 %tmp29 to ptr
%tmp31 = add i32 %1, 8
- %tmp3132 = inttoptr i32 %tmp31 to float*
+ %tmp3132 = inttoptr i32 %tmp31 to ptr
%tmp33 = add i32 %1, 12
- %tmp3334 = inttoptr i32 %tmp33 to float*
+ %tmp3334 = inttoptr i32 %tmp33 to ptr
%tmp35 = add i32 %1, 16
- %tmp3536 = inttoptr i32 %tmp35 to float*
+ %tmp3536 = inttoptr i32 %tmp35 to ptr
%tmp37 = add i32 %1, 20
- %tmp3738 = inttoptr i32 %tmp37 to float*
+ %tmp3738 = inttoptr i32 %tmp37 to ptr
%tmp39 = add i32 %1, 24
- %tmp3940 = inttoptr i32 %tmp39 to float*
- %2 = load float, float* %lsr.iv2641, align 4
- %3 = load float, float* %tmp2930, align 4
- %4 = load float, float* %tmp3132, align 4
- %5 = load float, float* %tmp3334, align 4
- %6 = load float, float* %tmp3536, align 4
- %7 = load float, float* %tmp3738, align 4
- %8 = load float, float* %tmp3940, align 4
+ %tmp3940 = inttoptr i32 %tmp39 to ptr
+ %2 = load float, ptr %lsr.iv2641, align 4
+ %3 = load float, ptr %tmp2930, align 4
+ %4 = load float, ptr %tmp3132, align 4
+ %5 = load float, ptr %tmp3334, align 4
+ %6 = load float, ptr %tmp3536, align 4
+ %7 = load float, ptr %tmp3738, align 4
+ %8 = load float, ptr %tmp3940, align 4
%9 = insertelement <4 x float> undef, float %6, i32 0
%10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> zeroinitializer
%11 = insertelement <4 x float> %10, float %7, i32 1
diff --git a/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll b/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll
index 980f8ce6fa1b2..a024627ef8435 100644
--- a/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll
+++ b/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll
@@ -2,7 +2,7 @@
; PR4986
-define arm_aapcs_vfpcc void @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind {
+define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems) nounwind {
entry:
br i1 undef, label %return, label %bb.preheader
@@ -16,14 +16,14 @@ bb: ; preds = %bb, %bb.preheader
%3 = insertelement <4 x float> %2, float undef, i32 3 ; <<4 x float>> [#uses=1]
%4 = fmul <4 x float> undef, %3 ; <<4 x float>> [#uses=1]
%5 = extractelement <4 x float> %4, i32 3 ; <float> [#uses=1]
- store float %5, float* undef, align 4
+ store float %5, ptr undef, align 4
br i1 undef, label %return, label %bb
return: ; preds = %bb, %entry
ret void
}
-define arm_aapcs_vfpcc <4 x float> @bar(i8* nocapture %pBuffer, i32 %numItems) nounwind {
+define arm_aapcs_vfpcc <4 x float> @bar(ptr nocapture %pBuffer, i32 %numItems) nounwind {
%1 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
%2 = insertelement <4 x float> %1, float undef, i32 1 ; <<4 x float>> [#uses=1]
%3 = insertelement <4 x float> %2, float undef, i32 2 ; <<4 x float>> [#uses=1]
diff --git a/llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll b/llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll
index eec0afcb89401..5728a6109b0f7 100644
--- a/llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll
+++ b/llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll
@@ -5,10 +5,10 @@
%bar = type { <4 x float> }
%foo = type { %bar, %bar, %bar, %bar }
-declare arm_aapcs_vfpcc <4 x float> @bbb(%bar*) nounwind
+declare arm_aapcs_vfpcc <4 x float> @bbb(ptr) nounwind
-define arm_aapcs_vfpcc void @aaa(%foo* noalias sret(%foo) %agg.result, %foo* %tfrm) nounwind {
+define arm_aapcs_vfpcc void @aaa(ptr noalias sret(%foo) %agg.result, ptr %tfrm) nounwind {
entry:
- %0 = call arm_aapcs_vfpcc <4 x float> @bbb(%bar* undef) nounwind ; <<4 x float>> [#uses=0]
+ %0 = call arm_aapcs_vfpcc <4 x float> @bbb(ptr undef) nounwind ; <<4 x float>> [#uses=0]
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll b/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll
index 30931a2ffb66d..0ef744bba56e2 100644
--- a/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll
+++ b/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll
@@ -5,17 +5,17 @@
%bar = type { %foo, %foo }
%foo = type { <4 x float> }
-declare arm_aapcs_vfpcc float @aaa(%foo* nocapture) nounwind readonly
+declare arm_aapcs_vfpcc float @aaa(ptr nocapture) nounwind readonly
-declare arm_aapcs_vfpcc %bar* @bbb(%bar*, <4 x float>, <4 x float>) nounwind
+declare arm_aapcs_vfpcc ptr @bbb(ptr, <4 x float>, <4 x float>) nounwind
-define arm_aapcs_vfpcc void @ccc(i8* nocapture %pBuffer, i32 %numItems) nounwind {
+define arm_aapcs_vfpcc void @ccc(ptr nocapture %pBuffer, i32 %numItems) nounwind {
entry:
br i1 undef, label %return, label %bb.nph
bb.nph: ; preds = %entry
- %0 = call arm_aapcs_vfpcc %bar* @bbb(%bar* undef, <4 x float> undef, <4 x float> undef) nounwind ; <%bar*> [#uses=0]
- %1 = call arm_aapcs_vfpcc float @aaa(%foo* undef) nounwind ; <float> [#uses=0]
+ %0 = call arm_aapcs_vfpcc ptr @bbb(ptr undef, <4 x float> undef, <4 x float> undef) nounwind ; <ptr> [#uses=0]
+ %1 = call arm_aapcs_vfpcc float @aaa(ptr undef) nounwind ; <float> [#uses=0]
unreachable
return: ; preds = %entry
diff --git a/llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll b/llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll
index 4bbd047056438..de5e8bd7e7b4d 100644
--- a/llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll
+++ b/llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll
@@ -5,17 +5,17 @@
%struct.1 = type { %struct.4, %struct.4 }
%struct.4 = type { <4 x float> }
-define arm_aapcs_vfpcc %struct.1* @hhh3(%struct.1* %this, <4 x float> %lenation.0, <4 x float> %legalation.0) nounwind {
+define arm_aapcs_vfpcc ptr @hhh3(ptr %this, <4 x float> %lenation.0, <4 x float> %legalation.0) nounwind {
entry:
- %0 = call arm_aapcs_vfpcc %struct.4* @sss1(%struct.4* undef, float 0.000000e+00) nounwind ; <%struct.4*> [#uses=0]
- %1 = call arm_aapcs_vfpcc %struct.4* @qqq1(%struct.4* null, float 5.000000e-01) nounwind ; <%struct.4*> [#uses=0]
- %val92 = load <4 x float>, <4 x float>* null ; <<4 x float>> [#uses=1]
- %2 = call arm_aapcs_vfpcc %struct.4* @zzz2(%struct.4* undef, <4 x float> %val92) nounwind ; <%struct.4*> [#uses=0]
- ret %struct.1* %this
+ %0 = call arm_aapcs_vfpcc ptr @sss1(ptr undef, float 0.000000e+00) nounwind ; <ptr> [#uses=0]
+ %1 = call arm_aapcs_vfpcc ptr @qqq1(ptr null, float 5.000000e-01) nounwind ; <ptr> [#uses=0]
+ %val92 = load <4 x float>, ptr null ; <<4 x float>> [#uses=1]
+ %2 = call arm_aapcs_vfpcc ptr @zzz2(ptr undef, <4 x float> %val92) nounwind ; <ptr> [#uses=0]
+ ret ptr %this
}
-declare arm_aapcs_vfpcc %struct.4* @qqq1(%struct.4*, float) nounwind
+declare arm_aapcs_vfpcc ptr @qqq1(ptr, float) nounwind
-declare arm_aapcs_vfpcc %struct.4* @sss1(%struct.4*, float) nounwind
+declare arm_aapcs_vfpcc ptr @sss1(ptr, float) nounwind
-declare arm_aapcs_vfpcc %struct.4* @zzz2(%struct.4*, <4 x float>) nounwind
+declare arm_aapcs_vfpcc ptr @zzz2(ptr, <4 x float>) nounwind
diff --git a/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll b/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll
index 4502542809f75..5767cbbc20fb2 100644
--- a/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll
+++ b/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll
@@ -3,13 +3,13 @@
define void @test_vget_lanep16() nounwind {
entry:
- %arg0_poly16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1]
- %out_poly16_t = alloca i16 ; <i16*> [#uses=1]
+ %arg0_poly16x4_t = alloca <4 x i16> ; <ptr> [#uses=1]
+ %out_poly16_t = alloca i16 ; <ptr> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
; CHECK: vldr
- %0 = load <4 x i16>, <4 x i16>* %arg0_poly16x4_t, align 8 ; <<4 x i16>> [#uses=1]
+ %0 = load <4 x i16>, ptr %arg0_poly16x4_t, align 8 ; <<4 x i16>> [#uses=1]
%1 = extractelement <4 x i16> %0, i32 1 ; <i16> [#uses=1]
- store i16 %1, i16* %out_poly16_t, align 2
+ store i16 %1, ptr %out_poly16_t, align 2
br label %return
return: ; preds = %entry
diff --git a/llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll b/llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
index 8bf73e924b7ca..a813f3afd8bab 100644
--- a/llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
+++ b/llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
@@ -3,7 +3,7 @@
%0 = type { double, double }
-define void @foo(%0* noalias nocapture sret(%0) %agg.result, double %x.0, double %y.0) nounwind {
+define void @foo(ptr noalias nocapture sret(%0) %agg.result, double %x.0, double %y.0) nounwind {
; CHECK-LABEL: foo:
; CHECK: bl __aeabi_dadd
; CHECK-NOT: strd
@@ -11,9 +11,9 @@ define void @foo(%0* noalias nocapture sret(%0) %agg.result, double %x.0, double
%x76 = fmul double %y.0, 0.000000e+00 ; <double> [#uses=1]
%x77 = fadd double %y.0, 0.000000e+00 ; <double> [#uses=1]
%tmpr = fadd double %x.0, %x76 ; <double> [#uses=1]
- %agg.result.0 = getelementptr %0, %0* %agg.result, i32 0, i32 0 ; <double*> [#uses=1]
- store double %tmpr, double* %agg.result.0, align 8
- %agg.result.1 = getelementptr %0, %0* %agg.result, i32 0, i32 1 ; <double*> [#uses=1]
- store double %x77, double* %agg.result.1, align 8
+ %agg.result.0 = getelementptr %0, ptr %agg.result, i32 0, i32 0 ; <ptr> [#uses=1]
+ store double %tmpr, ptr %agg.result.0, align 8
+ %agg.result.1 = getelementptr %0, ptr %agg.result, i32 0, i32 1 ; <ptr> [#uses=1]
+ store double %x77, ptr %agg.result.1, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll b/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll
index 641036f684b95..484ad93bebeab 100644
--- a/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll
+++ b/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll
@@ -1,13 +1,13 @@
; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 -enable-unsafe-fp-math < %s
; PR5367
-define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(i8* nocapture %pBuffer, i32 %numItems) nounwind {
+define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(ptr nocapture %pBuffer, i32 %numItems) nounwind {
entry:
br i1 undef, label %return, label %bb
bb: ; preds = %bb, %entry
- %0 = load float, float* undef, align 4 ; <float> [#uses=1]
- %1 = load float, float* null, align 4 ; <float> [#uses=1]
+ %0 = load float, ptr undef, align 4 ; <float> [#uses=1]
+ %1 = load float, ptr null, align 4 ; <float> [#uses=1]
%2 = insertelement <4 x float> undef, float undef, i32 1 ; <<4 x float>> [#uses=1]
%3 = insertelement <4 x float> %2, float %1, i32 2 ; <<4 x float>> [#uses=2]
%4 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1]
@@ -50,10 +50,10 @@ bb: ; preds = %bb, %entry
%41 = fadd <4 x float> %40, zeroinitializer ; <<4 x float>> [#uses=1]
%42 = shufflevector <4 x float> undef, <4 x float> %41, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1]
%43 = fmul <4 x float> %42, %31 ; <<4 x float>> [#uses=1]
- store float undef, float* undef, align 4
- store float 0.000000e+00, float* null, align 4
+ store float undef, ptr undef, align 4
+ store float 0.000000e+00, ptr null, align 4
%44 = extractelement <4 x float> %43, i32 1 ; <float> [#uses=1]
- store float %44, float* undef, align 4
+ store float %44, ptr undef, align 4
br i1 undef, label %return, label %bb
return: ; preds = %bb, %entry
diff --git a/llvm/test/CodeGen/ARM/2009-10-16-Scope.ll b/llvm/test/CodeGen/ARM/2009-10-16-Scope.ll
index 3e687322de4fe..c01f3bf352b18 100644
--- a/llvm/test/CodeGen/ARM/2009-10-16-Scope.ll
+++ b/llvm/test/CodeGen/ARM/2009-10-16-Scope.ll
@@ -5,12 +5,12 @@
define void @bar() nounwind ssp {
entry:
- %count_ = alloca i32, align 4 ; <i32*> [#uses=2]
+ %count_ = alloca i32, align 4 ; <ptr> [#uses=2]
br label %do.body, !dbg !0
do.body: ; preds = %entry
- call void @llvm.dbg.declare(metadata i32* %count_, metadata !4, metadata !DIExpression()), !dbg !DILocation(scope: !5)
- %conv = ptrtoint i32* %count_ to i32, !dbg !0 ; <i32> [#uses=1]
+ call void @llvm.dbg.declare(metadata ptr %count_, metadata !4, metadata !DIExpression()), !dbg !DILocation(scope: !5)
+ %conv = ptrtoint ptr %count_ to i32, !dbg !0 ; <i32> [#uses=1]
%call = call i32 @foo(i32 %conv) ssp, !dbg !0 ; <i32> [#uses=0]
br label %do.end, !dbg !0
diff --git a/llvm/test/CodeGen/ARM/2009-10-27-double-align.ll b/llvm/test/CodeGen/ARM/2009-10-27-double-align.ll
index 98a89a07af6f3..8bdd97bdc36a7 100644
--- a/llvm/test/CodeGen/ARM/2009-10-27-double-align.ll
+++ b/llvm/test/CodeGen/ARM/2009-10-27-double-align.ll
@@ -10,8 +10,8 @@ entry:
;NOREGALLOC: [sp]
;REGALLOC: [sp]
;REGALLOC: [sp, #12]
- tail call void (i8*, ...) @f(i8* getelementptr ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00)
+ tail call void (ptr, ...) @f(ptr @.str, i32 1, double 2.000000e+00, i32 3, double 4.000000e+00)
ret void
}
-declare void @f(i8*, ...)
+declare void @f(ptr, ...)
diff --git a/llvm/test/CodeGen/ARM/2009-10-30.ll b/llvm/test/CodeGen/ARM/2009-10-30.ll
index e46ab1eb2ab93..39aeb2690f050 100644
--- a/llvm/test/CodeGen/ARM/2009-10-30.ll
+++ b/llvm/test/CodeGen/ARM/2009-10-30.ll
@@ -8,10 +8,9 @@ entry:
;CHECK: add r{{[0-9]+}}, sp, #8
;CHECK: str r{{[0-9]+}}, [sp], #4
;CHECK: bx lr
- %ap = alloca i8*, align 4
- %ap1 = bitcast i8** %ap to i8*
- call void @llvm.va_start(i8* %ap1)
+ %ap = alloca ptr, align 4
+ call void @llvm.va_start(ptr %ap)
ret void
}
-declare void @llvm.va_start(i8*) nounwind
+declare void @llvm.va_start(ptr) nounwind
diff --git a/llvm/test/CodeGen/ARM/2009-11-01-NeonMoves.ll b/llvm/test/CodeGen/ARM/2009-11-01-NeonMoves.ll
index abc815bb8a8b8..7c11d9a884835 100644
--- a/llvm/test/CodeGen/ARM/2009-11-01-NeonMoves.ll
+++ b/llvm/test/CodeGen/ARM/2009-11-01-NeonMoves.ll
@@ -5,12 +5,12 @@ target triple = "armv7-eabi"
%foo = type { <4 x float> }
-define arm_aapcs_vfpcc void @bar(%foo* noalias sret(%foo) %agg.result, <4 x float> %quat.0) nounwind {
+define arm_aapcs_vfpcc void @bar(ptr noalias sret(%foo) %agg.result, <4 x float> %quat.0) nounwind {
entry:
- %quat_addr = alloca %foo, align 16 ; <%foo*> [#uses=2]
- %0 = getelementptr inbounds %foo, %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1]
- store <4 x float> %quat.0, <4 x float>* %0
- %1 = call arm_aapcs_vfpcc <4 x float> @quux(%foo* %quat_addr) nounwind ; <<4 x float>> [#uses=3]
+ %quat_addr = alloca %foo, align 16 ; <ptr> [#uses=2]
+ %0 = getelementptr inbounds %foo, ptr %quat_addr, i32 0, i32 0 ; <ptr> [#uses=1]
+ store <4 x float> %quat.0, ptr %0
+ %1 = call arm_aapcs_vfpcc <4 x float> @quux(ptr %quat_addr) nounwind ; <<4 x float>> [#uses=3]
%2 = fmul <4 x float> %1, %1 ; <<4 x float>> [#uses=2]
%3 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
%4 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
@@ -25,13 +25,13 @@ entry:
%10 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %9, <4 x float> %7) nounwind ; <<4 x float>> [#uses=1]
%11 = fmul <4 x float> %10, %8 ; <<4 x float>> [#uses=1]
%12 = fmul <4 x float> %11, %1 ; <<4 x float>> [#uses=1]
- %13 = call arm_aapcs_vfpcc %foo* @baz(%foo* %agg.result, <4 x float> %12) nounwind ; <%foo*> [#uses=0]
+ %13 = call arm_aapcs_vfpcc ptr @baz(ptr %agg.result, <4 x float> %12) nounwind ; <ptr> [#uses=0]
ret void
}
-declare arm_aapcs_vfpcc %foo* @baz(%foo*, <4 x float>) nounwind
+declare arm_aapcs_vfpcc ptr @baz(ptr, <4 x float>) nounwind
-declare arm_aapcs_vfpcc <4 x float> @quux(%foo* nocapture) nounwind readonly
+declare arm_aapcs_vfpcc <4 x float> @quux(ptr nocapture) nounwind readonly
declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
diff --git a/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll b/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll
index 154cd65e4ec1b..ff182aeb9cbf5 100644
--- a/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll
+++ b/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll
@@ -2,18 +2,18 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv7-eabi"
-define arm_aapcs_vfpcc void @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind {
+define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems) nounwind {
entry:
br i1 undef, label %return, label %bb
bb: ; preds = %bb, %entry
; CHECK: vld1.16 {d16[], d17[]}
- %0 = load i16, i16* undef, align 2
+ %0 = load i16, ptr undef, align 2
%1 = insertelement <8 x i16> undef, i16 %0, i32 2
%2 = insertelement <8 x i16> %1, i16 undef, i32 3
%3 = mul <8 x i16> %2, %2
%4 = extractelement <8 x i16> %3, i32 2
- store i16 %4, i16* undef, align 2
+ store i16 %4, ptr undef, align 2
br i1 undef, label %return, label %bb
return: ; preds = %bb, %entry
diff --git a/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll b/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
index c4d03479a2ba5..4a23448a0aaed 100644
--- a/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
+++ b/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
@@ -6,7 +6,7 @@ target triple = "armv7-eabi"
define arm_aapcs_vfpcc void @foo() {
entry:
- %0 = load float, float* null, align 4 ; <float> [#uses=2]
+ %0 = load float, ptr null, align 4 ; <float> [#uses=2]
%1 = fmul float %0, %0 ; <float> [#uses=2]
%2 = fmul float 0.000000e+00, %1 ; <float> [#uses=2]
%3 = fmul float %0, %1 ; <float> [#uses=1]
@@ -18,7 +18,7 @@ entry:
%7 = fsub float %2, %2 ; <float> [#uses=1]
%8 = fsub float 0.000000e+00, %7 ; <float> [#uses=3]
%9 = fadd float %2, %2 ; <float> [#uses=3]
- %10 = load float, float* undef, align 8 ; <float> [#uses=3]
+ %10 = load float, ptr undef, align 8 ; <float> [#uses=3]
%11 = fmul float %8, %10 ; <float> [#uses=1]
%12 = fadd float %11, %11 ; <float> [#uses=2]
%13 = fmul float %12, %12 ; <float> [#uses=1]
@@ -30,10 +30,10 @@ entry:
%19 = fadd float %18, 0.000000e+00 ; <float> [#uses=1]
%20 = fmul float %10, %10 ; <float> [#uses=1]
%21 = fadd float %19, %20 ; <float> [#uses=1]
- %22 = load float, float* undef, align 8 ; <float> [#uses=1]
+ %22 = load float, ptr undef, align 8 ; <float> [#uses=1]
%23 = fmul float %5, %22 ; <float> [#uses=1]
%24 = fadd float %23, %23 ; <float> [#uses=1]
- %25 = load float, float* undef, align 8 ; <float> [#uses=2]
+ %25 = load float, ptr undef, align 8 ; <float> [#uses=2]
%26 = fmul float %8, %25 ; <float> [#uses=1]
%27 = fadd float %24, %26 ; <float> [#uses=1]
%28 = fmul float %9, %25 ; <float> [#uses=1]
@@ -49,18 +49,18 @@ entry:
%38 = fadd float %36, %37 ; <float> [#uses=1]
%39 = fmul float %38, %38 ; <float> [#uses=1]
%40 = fadd float %38, %39 ; <float> [#uses=1]
- store float %12, float* undef, align 8
- store float %17, float* undef, align 4
- store float %21, float* undef, align 8
- store float %27, float* undef, align 8
- store float %29, float* undef, align 4
- store float %31, float* undef, align 8
- store float %40, float* undef, align 8
- store float %12, float* null, align 8
+ store float %12, ptr undef, align 8
+ store float %17, ptr undef, align 4
+ store float %21, ptr undef, align 8
+ store float %27, ptr undef, align 8
+ store float %29, ptr undef, align 4
+ store float %31, ptr undef, align 8
+ store float %40, ptr undef, align 8
+ store float %12, ptr null, align 8
%41 = fmul float %17, %17 ; <float> [#uses=1]
%42 = fadd float %41, %41 ; <float> [#uses=1]
%43 = fmul float %35, %35 ; <float> [#uses=1]
%44 = fadd float %42, %43 ; <float> [#uses=1]
- store float %44, float* null, align 4
+ store float %44, ptr null, align 4
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll b/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll
index efc4be11581cf..f6ee605c026ea 100644
--- a/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll
+++ b/llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll
@@ -5,16 +5,16 @@
%pln = type { %vec, float }
%vec = type { [4 x float] }
-define arm_aapcs_vfpcc float @aaa(%vec* nocapture %ustart, %vec* nocapture %udir, %vec* nocapture %vstart, %vec* nocapture %vdir, %vec* %upoint, %vec* %vpoint) {
+define arm_aapcs_vfpcc float @aaa(ptr nocapture %ustart, ptr nocapture %udir, ptr nocapture %vstart, ptr nocapture %vdir, ptr %upoint, ptr %vpoint) {
entry:
br i1 undef, label %bb81, label %bb48
bb48: ; preds = %entry
- %0 = call arm_aapcs_vfpcc %0 @bbb(%pln* undef, %vec* %vstart, %vec* undef) nounwind ; <%0> [#uses=0]
+ %0 = call arm_aapcs_vfpcc %0 @bbb(ptr undef, ptr %vstart, ptr undef) nounwind ; <%0> [#uses=0]
ret float 0.000000e+00
bb81: ; preds = %entry
ret float 0.000000e+00
}
-declare arm_aapcs_vfpcc %0 @bbb(%pln* nocapture, %vec* nocapture, %vec* nocapture) nounwind
+declare arm_aapcs_vfpcc %0 @bbb(ptr nocapture, ptr nocapture, ptr nocapture) nounwind
diff --git a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll
index 07e910b3e07b6..92efbbd7d469c 100644
--- a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll
+++ b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll
@@ -1,23 +1,23 @@
; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
; PR5411
-%bar = type { %quad, float, float, [3 x %quux*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 }
-%baz = type { %bar*, i32 }
+%bar = type { %quad, float, float, [3 x ptr], [3 x ptr], [2 x ptr], [3 x i8], i8 }
+%baz = type { ptr, i32 }
%foo = type { i8, %quuz, %quad, float, [64 x %quux], [128 x %bar], i32, %baz, %baz }
%quad = type { [4 x float] }
%quux = type { %quad, %quad }
-%quuz = type { [4 x %quux*], [4 x float], i32 }
+%quuz = type { [4 x ptr], [4 x float], i32 }
-define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quux* %a, %quux* %b, %quux* %c, i8 zeroext %forced) {
+define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) {
entry:
br i1 undef, label %bb85, label %bb
bb: ; preds = %entry
- %0 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 2 ; <float*> [#uses=2]
- %1 = load float, float* undef, align 4 ; <float> [#uses=1]
+ %0 = getelementptr inbounds %bar, ptr null, i32 0, i32 0, i32 0, i32 2 ; <ptr> [#uses=2]
+ %1 = load float, ptr undef, align 4 ; <float> [#uses=1]
%2 = fsub float 0.000000e+00, undef ; <float> [#uses=2]
%3 = fmul float 0.000000e+00, undef ; <float> [#uses=1]
- %4 = load float, float* %0, align 4 ; <float> [#uses=3]
+ %4 = load float, ptr %0, align 4 ; <float> [#uses=3]
%5 = fmul float %4, %2 ; <float> [#uses=1]
%6 = fsub float %3, %5 ; <float> [#uses=1]
%7 = fmul float %4, undef ; <float> [#uses=1]
@@ -32,11 +32,11 @@ bb: ; preds = %entry
%16 = fadd float %14, %15 ; <float> [#uses=1]
%17 = select i1 undef, float undef, float %16 ; <float> [#uses=1]
%18 = fdiv float %17, 0.000000e+00 ; <float> [#uses=1]
- store float %18, float* undef, align 4
+ store float %18, ptr undef, align 4
%19 = fmul float %4, undef ; <float> [#uses=1]
- store float %19, float* %0, align 4
- ret %bar* null
+ store float %19, ptr %0, align 4
+ ret ptr null
bb85: ; preds = %entry
- ret %bar* null
+ ret ptr null
}
diff --git a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll
index 9eddcf71cb3b4..f5f065b43a8e9 100644
--- a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll
+++ b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll
@@ -1,14 +1,14 @@
; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
; PR5412
-%bar = type { %quad, float, float, [3 x %quuz*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 }
-%baz = type { %bar*, i32 }
+%bar = type { %quad, float, float, [3 x ptr], [3 x ptr], [2 x ptr], [3 x i8], i8 }
+%baz = type { ptr, i32 }
%foo = type { i8, %quux, %quad, float, [64 x %quuz], [128 x %bar], i32, %baz, %baz }
%quad = type { [4 x float] }
-%quux = type { [4 x %quuz*], [4 x float], i32 }
+%quux = type { [4 x ptr], [4 x float], i32 }
%quuz = type { %quad, %quad }
-define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quuz* %a, %quuz* %b, %quuz* %c, i8 zeroext %forced) {
+define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) {
entry:
br i1 undef, label %bb85, label %bb
@@ -19,22 +19,22 @@ bb2.i: ; preds = %bb
br label %bb3.i
bb3.i: ; preds = %bb2.i, %bb
- %0 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=0]
+ %0 = getelementptr inbounds %quuz, ptr %a, i32 0, i32 1, i32 0, i32 0 ; <ptr> [#uses=0]
%1 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
- %2 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=2]
- %3 = load float, float* %2, align 4 ; <float> [#uses=1]
- %4 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
+ %2 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 1 ; <ptr> [#uses=2]
+ %3 = load float, ptr %2, align 4 ; <float> [#uses=1]
+ %4 = getelementptr inbounds %quuz, ptr %a, i32 0, i32 1, i32 0, i32 1 ; <ptr> [#uses=1]
%5 = fsub float %3, undef ; <float> [#uses=2]
- %6 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=2]
- %7 = load float, float* %6, align 4 ; <float> [#uses=1]
+ %6 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 2 ; <ptr> [#uses=2]
+ %7 = load float, ptr %6, align 4 ; <float> [#uses=1]
%8 = fsub float %7, undef ; <float> [#uses=1]
- %9 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=2]
- %10 = load float, float* %9, align 4 ; <float> [#uses=1]
+ %9 = getelementptr inbounds %quuz, ptr %c, i32 0, i32 1, i32 0, i32 0 ; <ptr> [#uses=2]
+ %10 = load float, ptr %9, align 4 ; <float> [#uses=1]
%11 = fsub float %10, undef ; <float> [#uses=2]
- %12 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=2]
- %13 = load float, float* %12, align 4 ; <float> [#uses=1]
+ %12 = getelementptr inbounds %quuz, ptr %c, i32 0, i32 1, i32 0, i32 1 ; <ptr> [#uses=2]
+ %13 = load float, ptr %12, align 4 ; <float> [#uses=1]
%14 = fsub float %13, undef ; <float> [#uses=1]
- %15 = load float, float* undef, align 4 ; <float> [#uses=1]
+ %15 = load float, ptr undef, align 4 ; <float> [#uses=1]
%16 = fsub float %15, undef ; <float> [#uses=1]
%17 = fmul float %5, %16 ; <float> [#uses=1]
%18 = fsub float %17, 0.000000e+00 ; <float> [#uses=5]
@@ -43,20 +43,20 @@ bb3.i: ; preds = %bb2.i, %bb
%21 = fmul float %1, %14 ; <float> [#uses=1]
%22 = fmul float %5, %11 ; <float> [#uses=1]
%23 = fsub float %21, %22 ; <float> [#uses=2]
- store float %18, float* undef
- %24 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 1 ; <float*> [#uses=2]
- store float %20, float* %24
- store float %23, float* undef
- %25 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 3 ; <float*> [#uses=0]
+ store float %18, ptr undef
+ %24 = getelementptr inbounds %bar, ptr null, i32 0, i32 0, i32 0, i32 1 ; <ptr> [#uses=2]
+ store float %20, ptr %24
+ store float %23, ptr undef
+ %25 = getelementptr inbounds %bar, ptr null, i32 0, i32 0, i32 0, i32 3 ; <ptr> [#uses=0]
%26 = fmul float %18, %18 ; <float> [#uses=1]
%27 = fadd float %26, undef ; <float> [#uses=1]
%28 = fadd float %27, undef ; <float> [#uses=1]
%29 = call arm_aapcs_vfpcc float @sqrtf(float %28) readnone ; <float> [#uses=1]
- %30 = load float, float* null, align 4 ; <float> [#uses=2]
- %31 = load float, float* %4, align 4 ; <float> [#uses=2]
- %32 = load float, float* %2, align 4 ; <float> [#uses=2]
- %33 = load float, float* null, align 4 ; <float> [#uses=3]
- %34 = load float, float* %6, align 4 ; <float> [#uses=2]
+ %30 = load float, ptr null, align 4 ; <float> [#uses=2]
+ %31 = load float, ptr %4, align 4 ; <float> [#uses=2]
+ %32 = load float, ptr %2, align 4 ; <float> [#uses=2]
+ %33 = load float, ptr null, align 4 ; <float> [#uses=3]
+ %34 = load float, ptr %6, align 4 ; <float> [#uses=2]
%35 = fsub float %33, %34 ; <float> [#uses=2]
%36 = fmul float %20, %35 ; <float> [#uses=1]
%37 = fsub float %36, undef ; <float> [#uses=1]
@@ -71,12 +71,12 @@ bb3.i: ; preds = %bb2.i, %bb
%46 = fadd float %44, %45 ; <float> [#uses=1]
%47 = fmul float %33, %43 ; <float> [#uses=1]
%48 = fadd float %46, %47 ; <float> [#uses=2]
- %49 = load float, float* %9, align 4 ; <float> [#uses=2]
+ %49 = load float, ptr %9, align 4 ; <float> [#uses=2]
%50 = fsub float %30, %49 ; <float> [#uses=1]
- %51 = load float, float* %12, align 4 ; <float> [#uses=3]
+ %51 = load float, ptr %12, align 4 ; <float> [#uses=3]
%52 = fsub float %32, %51 ; <float> [#uses=2]
- %53 = load float, float* undef, align 4 ; <float> [#uses=2]
- %54 = load float, float* %24, align 4 ; <float> [#uses=2]
+ %53 = load float, ptr undef, align 4 ; <float> [#uses=2]
+ %54 = load float, ptr %24, align 4 ; <float> [#uses=2]
%55 = fmul float %54, undef ; <float> [#uses=1]
%56 = fmul float undef, %52 ; <float> [#uses=1]
%57 = fsub float %55, %56 ; <float> [#uses=1]
@@ -93,7 +93,7 @@ bb3.i: ; preds = %bb2.i, %bb
%68 = fsub float %51, %31 ; <float> [#uses=1]
%69 = fsub float %53, %33 ; <float> [#uses=1]
%70 = fmul float undef, %67 ; <float> [#uses=1]
- %71 = load float, float* undef, align 4 ; <float> [#uses=2]
+ %71 = load float, ptr undef, align 4 ; <float> [#uses=2]
%72 = fmul float %71, %69 ; <float> [#uses=1]
%73 = fsub float %70, %72 ; <float> [#uses=1]
%74 = fmul float %71, %68 ; <float> [#uses=1]
@@ -107,17 +107,17 @@ bb3.i: ; preds = %bb2.i, %bb
%iftmp.164.0 = select i1 undef, float %29, float 1.000000e+00 ; <float> [#uses=1]
%82 = fdiv float %81, %iftmp.164.0 ; <float> [#uses=1]
%iftmp.165.0 = select i1 undef, float %82, float 0.000000e+00 ; <float> [#uses=1]
- store float %iftmp.165.0, float* undef, align 4
+ store float %iftmp.165.0, ptr undef, align 4
br i1 false, label %bb4.i97, label %ccc.exit98
bb4.i97: ; preds = %bb3.i
br label %ccc.exit98
ccc.exit98: ; preds = %bb4.i97, %bb3.i
- ret %bar* null
+ ret ptr null
bb85: ; preds = %entry
- ret %bar* null
+ ret ptr null
}
declare arm_aapcs_vfpcc float @sqrtf(float) readnone
diff --git a/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll b/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll
index 8a14804dcf85c..9c773ca8d613c 100644
--- a/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll
+++ b/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll
@@ -2,16 +2,16 @@
; PR5412
; rdar://7384107
-%bar = type { %quad, float, float, [3 x %quuz*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 }
-%baz = type { %bar*, i32 }
+%bar = type { %quad, float, float, [3 x ptr], [3 x ptr], [2 x ptr], [3 x i8], i8 }
+%baz = type { ptr, i32 }
%foo = type { i8, %quux, %quad, float, [64 x %quuz], [128 x %bar], i32, %baz, %baz }
%quad = type { [4 x float] }
-%quux = type { [4 x %quuz*], [4 x float], i32 }
+%quux = type { [4 x ptr], [4 x float], i32 }
%quuz = type { %quad, %quad }
-define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quuz* %a, %quuz* %b, %quuz* %c, i8 zeroext %forced) {
+define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) {
entry:
- %0 = load %bar*, %bar** undef, align 4 ; <%bar*> [#uses=2]
+ %0 = load ptr, ptr undef, align 4 ; <ptr> [#uses=2]
br i1 false, label %bb85, label %bb
bb: ; preds = %entry
@@ -21,13 +21,13 @@ bb2.i: ; preds = %bb
br label %bb3.i
bb3.i: ; preds = %bb2.i, %bb
- %1 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1]
+ %1 = getelementptr inbounds %quuz, ptr %a, i32 0, i32 1, i32 0, i32 0 ; <ptr> [#uses=1]
%2 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
- %3 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
- %4 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=1]
+ %3 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 1 ; <ptr> [#uses=1]
+ %4 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 2 ; <ptr> [#uses=1]
%5 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
- %6 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1]
- %7 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
+ %6 = getelementptr inbounds %quuz, ptr %c, i32 0, i32 1, i32 0, i32 0 ; <ptr> [#uses=1]
+ %7 = getelementptr inbounds %quuz, ptr %c, i32 0, i32 1, i32 0, i32 1 ; <ptr> [#uses=1]
%8 = fsub float undef, undef ; <float> [#uses=1]
%9 = fmul float 0.000000e+00, %8 ; <float> [#uses=1]
%10 = fmul float %5, 0.000000e+00 ; <float> [#uses=1]
@@ -35,18 +35,18 @@ bb3.i: ; preds = %bb2.i, %bb
%12 = fmul float %2, 0.000000e+00 ; <float> [#uses=1]
%13 = fmul float 0.000000e+00, undef ; <float> [#uses=1]
%14 = fsub float %12, %13 ; <float> [#uses=2]
- store float %14, float* undef
- %15 = getelementptr inbounds %bar, %bar* %0, i32 0, i32 0, i32 0, i32 3 ; <float*> [#uses=1]
- store float 0.000000e+00, float* %15
+ store float %14, ptr undef
+ %15 = getelementptr inbounds %bar, ptr %0, i32 0, i32 0, i32 0, i32 3 ; <ptr> [#uses=1]
+ store float 0.000000e+00, ptr %15
%16 = fmul float %11, %11 ; <float> [#uses=1]
%17 = fadd float %16, 0.000000e+00 ; <float> [#uses=1]
%18 = fadd float %17, undef ; <float> [#uses=1]
%19 = call arm_aapcs_vfpcc float @sqrtf(float %18) readnone ; <float> [#uses=2]
%20 = fcmp ogt float %19, 0x3F1A36E2E0000000 ; <i1> [#uses=1]
- %21 = load float, float* %1, align 4 ; <float> [#uses=2]
- %22 = load float, float* %3, align 4 ; <float> [#uses=2]
- %23 = load float, float* undef, align 4 ; <float> [#uses=2]
- %24 = load float, float* %4, align 4 ; <float> [#uses=2]
+ %21 = load float, ptr %1, align 4 ; <float> [#uses=2]
+ %22 = load float, ptr %3, align 4 ; <float> [#uses=2]
+ %23 = load float, ptr undef, align 4 ; <float> [#uses=2]
+ %24 = load float, ptr %4, align 4 ; <float> [#uses=2]
%25 = fsub float %23, %24 ; <float> [#uses=2]
%26 = fmul float 0.000000e+00, %25 ; <float> [#uses=1]
%27 = fsub float %26, undef ; <float> [#uses=1]
@@ -59,11 +59,11 @@ bb3.i: ; preds = %bb2.i, %bb
%34 = fadd float %32, %33 ; <float> [#uses=1]
%35 = fmul float %23, %31 ; <float> [#uses=1]
%36 = fadd float %34, %35 ; <float> [#uses=1]
- %37 = load float, float* %6, align 4 ; <float> [#uses=2]
- %38 = load float, float* %7, align 4 ; <float> [#uses=2]
+ %37 = load float, ptr %6, align 4 ; <float> [#uses=2]
+ %38 = load float, ptr %7, align 4 ; <float> [#uses=2]
%39 = fsub float %22, %38 ; <float> [#uses=2]
- %40 = load float, float* undef, align 4 ; <float> [#uses=1]
- %41 = load float, float* null, align 4 ; <float> [#uses=2]
+ %40 = load float, ptr undef, align 4 ; <float> [#uses=1]
+ %41 = load float, ptr null, align 4 ; <float> [#uses=2]
%42 = fmul float %41, undef ; <float> [#uses=1]
%43 = fmul float undef, %39 ; <float> [#uses=1]
%44 = fsub float %42, %43 ; <float> [#uses=1]
@@ -80,7 +80,7 @@ bb3.i: ; preds = %bb2.i, %bb
%55 = fmul float undef, undef ; <float> [#uses=1]
%56 = fsub float %54, %55 ; <float> [#uses=1]
%57 = fmul float undef, %53 ; <float> [#uses=1]
- %58 = load float, float* undef, align 4 ; <float> [#uses=2]
+ %58 = load float, ptr undef, align 4 ; <float> [#uses=2]
%59 = fmul float %58, undef ; <float> [#uses=1]
%60 = fsub float %57, %59 ; <float> [#uses=1]
%61 = fmul float %58, undef ; <float> [#uses=1]
@@ -95,19 +95,19 @@ bb3.i: ; preds = %bb2.i, %bb
%70 = select i1 undef, float %69, float %68 ; <float> [#uses=1]
%iftmp.164.0 = select i1 %20, float %19, float 1.000000e+00 ; <float> [#uses=1]
%71 = fdiv float %70, %iftmp.164.0 ; <float> [#uses=1]
- store float %71, float* null, align 4
- %72 = icmp eq %bar* null, %0 ; <i1> [#uses=1]
+ store float %71, ptr null, align 4
+ %72 = icmp eq ptr null, %0 ; <i1> [#uses=1]
br i1 %72, label %bb4.i97, label %ccc.exit98
bb4.i97: ; preds = %bb3.i
- %73 = load %bar*, %bar** undef, align 4 ; <%bar*> [#uses=0]
+ %73 = load ptr, ptr undef, align 4 ; <ptr> [#uses=0]
br label %ccc.exit98
ccc.exit98: ; preds = %bb4.i97, %bb3.i
- ret %bar* null
+ ret ptr null
bb85: ; preds = %entry
- ret %bar* null
+ ret ptr null
}
declare arm_aapcs_vfpcc float @sqrtf(float) readnone
diff --git a/llvm/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll b/llvm/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll
index efe74cfd13875..a25114b71a96d 100644
--- a/llvm/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll
+++ b/llvm/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll
@@ -1,13 +1,13 @@
; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
; PR5614
-%"als" = type { i32 (...)** }
+%"als" = type { ptr }
%"av" = type { %"als" }
-%"c" = type { %"lsm", %"Vec3", %"av"*, float, i8, float, %"lsm", i8, %"Vec3", %"Vec3", %"Vec3", float, float, float, %"Vec3", %"Vec3" }
+%"c" = type { %"lsm", %"Vec3", ptr, float, i8, float, %"lsm", i8, %"Vec3", %"Vec3", %"Vec3", float, float, float, %"Vec3", %"Vec3" }
%"lsm" = type { %"als", %"Vec3", %"Vec3", %"Vec3", %"Vec3" }
%"Vec3" = type { float, float, float }
-define arm_aapcs_vfpcc void @foo(%"c"* %this, %"Vec3"* nocapture %adjustment) {
+define arm_aapcs_vfpcc void @foo(ptr %this, ptr nocapture %adjustment) {
entry:
switch i32 undef, label %return [
i32 1, label %bb
@@ -21,10 +21,10 @@ bb: ; preds = %entry
ret void
bb31: ; preds = %entry
- %0 = call arm_aapcs_vfpcc %"Vec3" undef(%"lsm"* undef) ; <%"Vec3"> [#uses=1]
+ %0 = call arm_aapcs_vfpcc %"Vec3" undef(ptr undef) ; <%"Vec3"> [#uses=1]
%mrv_gr69 = extractvalue %"Vec3" %0, 1 ; <float> [#uses=1]
%1 = fsub float %mrv_gr69, undef ; <float> [#uses=1]
- store float %1, float* undef, align 4
+ store float %1, ptr undef, align 4
ret void
bb72: ; preds = %entry
diff --git a/llvm/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll b/llvm/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll
index be9dcffedcd44..c7418af52fd7e 100644
--- a/llvm/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll
+++ b/llvm/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll
@@ -6,28 +6,27 @@ target triple = "armv7-apple-darwin10"
%struct.int16x8_t = type { <8 x i16> }
%struct.int16x8x2_t = type { [2 x %struct.int16x8_t] }
-define void @t(%struct.int16x8x2_t* noalias nocapture sret(%struct.int16x8x2_t) %agg.result, <8 x i16> %tmp.0, %struct.int16x8x2_t* nocapture %dst) nounwind {
+define void @t(ptr noalias nocapture sret(%struct.int16x8x2_t) %agg.result, <8 x i16> %tmp.0, ptr nocapture %dst) nounwind {
entry:
;CHECK: vtrn.16
%0 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
%1 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
- %agg.result1218.0 = getelementptr %struct.int16x8x2_t, %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 0, i32 0 ; <<8 x i16>*>
- store <8 x i16> %0, <8 x i16>* %agg.result1218.0, align 16
- %agg.result12.1.0 = getelementptr %struct.int16x8x2_t, %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 1, i32 0 ; <<8 x i16>*>
- store <8 x i16> %1, <8 x i16>* %agg.result12.1.0, align 16
+ %agg.result1218.0 = getelementptr %struct.int16x8x2_t, ptr %agg.result, i32 0, i32 0, i32 0, i32 0 ; <ptr>
+ store <8 x i16> %0, ptr %agg.result1218.0, align 16
+ %agg.result12.1.0 = getelementptr %struct.int16x8x2_t, ptr %agg.result, i32 0, i32 0, i32 1, i32 0 ; <ptr>
+ store <8 x i16> %1, ptr %agg.result12.1.0, align 16
ret void
}
; Radar 8290937: Ignore undef shuffle indices.
; CHECK: t2
; CHECK: vtrn.16
-define void @t2(%struct.int16x8x2_t* nocapture %ptr, <4 x i16> %a.0, <4 x i16> %b.0) nounwind {
+define void @t2(ptr nocapture %ptr, <4 x i16> %a.0, <4 x i16> %b.0) nounwind {
entry:
%0 = shufflevector <4 x i16> %a.0, <4 x i16> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 undef, i32 undef, i32 undef, i32 undef>
%1 = shufflevector <4 x i16> %a.0, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
- %ptr26.0 = getelementptr inbounds %struct.int16x8x2_t, %struct.int16x8x2_t* %ptr, i32 0, i32 0, i32 0, i32 0
- store <8 x i16> %0, <8 x i16>* %ptr26.0, align 16
- %ptr20.1.0 = getelementptr inbounds %struct.int16x8x2_t, %struct.int16x8x2_t* %ptr, i32 0, i32 0, i32 1, i32 0
- store <8 x i16> %1, <8 x i16>* %ptr20.1.0, align 16
+ store <8 x i16> %0, ptr %ptr, align 16
+ %ptr20.1.0 = getelementptr inbounds %struct.int16x8x2_t, ptr %ptr, i32 0, i32 0, i32 1, i32 0
+ store <8 x i16> %1, ptr %ptr20.1.0, align 16
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll b/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll
index d21b488bb3a0e..c44850bbd554e 100644
--- a/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll
+++ b/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi
-define void @"java.lang.String::getChars"([84 x i8]* %method, i32 %base_pc, [788 x i8]* %thread) {
- %1 = load i32, i32* undef ; <i32> [#uses=1]
+define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread) {
+ %1 = load i32, ptr undef ; <i32> [#uses=1]
%2 = sub i32 %1, 48 ; <i32> [#uses=1]
br i1 undef, label %stack_overflow, label %no_overflow
@@ -9,14 +9,13 @@ stack_overflow: ; preds = %0
unreachable
no_overflow: ; preds = %0
- %frame = inttoptr i32 %2 to [17 x i32]* ; <[17 x i32]*> [#uses=4]
- %3 = load i32, i32* undef ; <i32> [#uses=1]
- %4 = load i32, i32* null ; <i32> [#uses=1]
- %5 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 13 ; <i32*> [#uses=1]
- %6 = bitcast i32* %5 to [8 x i8]** ; <[8 x i8]**> [#uses=1]
- %7 = load [8 x i8]*, [8 x i8]** %6 ; <[8 x i8]*> [#uses=1]
- %8 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 12 ; <i32*> [#uses=1]
- %9 = load i32, i32* %8 ; <i32> [#uses=1]
+ %frame = inttoptr i32 %2 to ptr ; <ptr> [#uses=4]
+ %3 = load i32, ptr undef ; <i32> [#uses=1]
+ %4 = load i32, ptr null ; <i32> [#uses=1]
+ %5 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 13 ; <ptr> [#uses=1]
+ %6 = load ptr, ptr %5 ; <ptr> [#uses=1]
+ %7 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 12 ; <ptr> [#uses=1]
+ %8 = load i32, ptr %7 ; <i32> [#uses=1]
br i1 undef, label %bci_13, label %bci_4
bci_13: ; preds = %no_overflow
@@ -26,26 +25,23 @@ bci_30: ; preds = %bci_13
br i1 undef, label %bci_46, label %bci_35
bci_46: ; preds = %bci_30
- %10 = sub i32 %4, %3 ; <i32> [#uses=1]
- %11 = load [8 x i8]*, [8 x i8]** null ; <[8 x i8]*> [#uses=1]
- %callee = bitcast [8 x i8]* %11 to [84 x i8]* ; <[84 x i8]*> [#uses=1]
- %12 = bitcast i8* undef to i32* ; <i32*> [#uses=1]
- %base_pc7 = load i32, i32* %12 ; <i32> [#uses=2]
- %13 = add i32 %base_pc7, 0 ; <i32> [#uses=1]
- %14 = inttoptr i32 %13 to void ([84 x i8]*, i32, [788 x i8]*)** ; <void ([84 x i8]*, i32, [788 x i8]*)**> [#uses=1]
- %entry_point = load void ([84 x i8]*, i32, [788 x i8]*)*, void ([84 x i8]*, i32, [788 x i8]*)** %14 ; <void ([84 x i8]*, i32, [788 x i8]*)*> [#uses=1]
- %15 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 1 ; <i32*> [#uses=1]
- %16 = ptrtoint i32* %15 to i32 ; <i32> [#uses=1]
- %stack_pointer_addr9 = bitcast i8* undef to i32* ; <i32*> [#uses=1]
- store i32 %16, i32* %stack_pointer_addr9
- %17 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 2 ; <i32*> [#uses=1]
- store i32 %9, i32* %17
- store i32 %10, i32* undef
- store [84 x i8]* %method, [84 x i8]** undef
- %18 = add i32 %base_pc, 20 ; <i32> [#uses=1]
- store i32 %18, i32* undef
- store [8 x i8]* %7, [8 x i8]** undef
- call void %entry_point([84 x i8]* %callee, i32 %base_pc7, [788 x i8]* %thread)
+ %9 = sub i32 %4, %3 ; <i32> [#uses=1]
+ %10 = load ptr, ptr null ; <ptr> [#uses=1]
+ %base_pc7 = load i32, ptr undef ; <i32> [#uses=2]
+ %11 = add i32 %base_pc7, 0 ; <i32> [#uses=1]
+ %12 = inttoptr i32 %11 to ptr ; <ptr> [#uses=1]
+ %entry_point = load ptr, ptr %12 ; <ptr> [#uses=1]
+ %13 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 1 ; <ptr> [#uses=1]
+ %14 = ptrtoint ptr %13 to i32 ; <i32> [#uses=1]
+ store i32 %14, ptr undef
+ %15 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 2 ; <ptr> [#uses=1]
+ store i32 %8, ptr %15
+ store i32 %9, ptr undef
+ store ptr %method, ptr undef
+ %16 = add i32 %base_pc, 20 ; <i32> [#uses=1]
+ store i32 %16, ptr undef
+ store ptr %6, ptr undef
+ call void %entry_point(ptr %10, i32 %base_pc7, ptr %thread)
br i1 undef, label %no_exception, label %exception
exception: ; preds = %bci_46
diff --git a/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll b/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll
index a1923ec2c3e08..fe4e3478ffd3a 100644
--- a/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll
+++ b/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll
@@ -1,6 +1,6 @@
; RUN: llc -mtriple=arm-eabi %s -o /dev/null
-define void @"java.lang.String::getChars"([84 x i8]* %method, i32 %base_pc, [788 x i8]* %thread) {
+define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread) {
%1 = sub i32 undef, 48 ; <i32> [#uses=1]
br i1 undef, label %stack_overflow, label %no_overflow
@@ -8,11 +8,11 @@ stack_overflow: ; preds = %0
unreachable
no_overflow: ; preds = %0
- %frame = inttoptr i32 %1 to [17 x i32]* ; <[17 x i32]*> [#uses=4]
- %2 = load i32, i32* null ; <i32> [#uses=2]
- %3 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 14 ; <i32*> [#uses=1]
- %4 = load i32, i32* %3 ; <i32> [#uses=2]
- %5 = load [8 x i8]*, [8 x i8]** undef ; <[8 x i8]*> [#uses=2]
+ %frame = inttoptr i32 %1 to ptr ; <ptr> [#uses=4]
+ %2 = load i32, ptr null ; <i32> [#uses=2]
+ %3 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 14 ; <ptr> [#uses=1]
+ %4 = load i32, ptr %3 ; <i32> [#uses=2]
+ %5 = load ptr, ptr undef ; <ptr> [#uses=2]
br i1 undef, label %bci_13, label %bci_4
bci_13: ; preds = %no_overflow
@@ -23,7 +23,7 @@ bci_30: ; preds = %bci_13
br i1 %6, label %bci_46, label %bci_35
bci_46: ; preds = %bci_30
- store [84 x i8]* %method, [84 x i8]** undef
+ store ptr %method, ptr undef
br i1 false, label %no_exception, label %exception
exception: ; preds = %bci_46
@@ -33,22 +33,21 @@ no_exception: ; preds = %bci_46
ret void
bci_35: ; preds = %bci_30
- %7 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 15 ; <i32*> [#uses=1]
- store i32 %2, i32* %7
- %8 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 14 ; <i32*> [#uses=1]
- store i32 %4, i32* %8
- %9 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 13 ; <i32*> [#uses=1]
- %10 = bitcast i32* %9 to [8 x i8]** ; <[8 x i8]**> [#uses=1]
- store [8 x i8]* %5, [8 x i8]** %10
- call void inttoptr (i32 13839116 to void ([788 x i8]*, i32)*)([788 x i8]* %thread, i32 7)
+ %7 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 15 ; <ptr> [#uses=1]
+ store i32 %2, ptr %7
+ %8 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 14 ; <ptr> [#uses=1]
+ store i32 %4, ptr %8
+ %9 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 13 ; <ptr> [#uses=1]
+ store ptr %5, ptr %9
+ call void inttoptr (i32 13839116 to ptr)(ptr %thread, i32 7)
ret void
bci_21: ; preds = %bci_13
ret void
bci_4: ; preds = %no_overflow
- store [8 x i8]* %5, [8 x i8]** undef
- store i32 undef, i32* undef
- call void inttoptr (i32 13839116 to void ([788 x i8]*, i32)*)([788 x i8]* %thread, i32 7)
+ store ptr %5, ptr undef
+ store i32 undef, ptr undef
+ call void inttoptr (i32 13839116 to ptr)(ptr %thread, i32 7)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll b/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll
index ceef0830fd2e9..1426d91b4b030 100644
--- a/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll
+++ b/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o /dev/null
; rdar://7770501 : Don't crash on SELECT and SELECT_CC with NEON vector values.
-define void @vDSP_FFT16_copv(float* nocapture %O, float* nocapture %I, i32 %Direction) nounwind {
+define void @vDSP_FFT16_copv(ptr nocapture %O, ptr nocapture %I, i32 %Direction) nounwind {
entry:
%.22 = select i1 undef, <4 x float> undef, <4 x float> zeroinitializer ; <<4 x float>> [#uses=1]
%0 = fadd <4 x float> undef, %.22 ; <<4 x float>> [#uses=1]
diff --git a/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll b/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll
index 5f5489a1ca74f..7ad9cb18e5de1 100644
--- a/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll
+++ b/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll
@@ -9,8 +9,8 @@ target triple = "arm-pc-linux-gnu"
%struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 }
- at search = external global %struct.CHESS_POSITION ; <%struct.CHESS_POSITION*> [#uses=1]
- at bishop_mobility_rr45 = external global [64 x [256 x i32]] ; <[64 x [256 x i32]]*> [#uses=1]
+ at search = external global %struct.CHESS_POSITION ; <ptr> [#uses=1]
+ at bishop_mobility_rr45 = external global [64 x [256 x i32]] ; <ptr> [#uses=1]
declare fastcc i32 @FirstOne()
@@ -82,17 +82,17 @@ cond_true1369.preheader: ; preds = %cond_true1254
ret void
bb1567: ; preds = %cond_true1254
- %tmp1591 = load i64, i64* getelementptr inbounds (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 4) ; <i64> [#uses=1]
+ %tmp1591 = load i64, ptr getelementptr inbounds (%struct.CHESS_POSITION, ptr @search, i32 0, i32 4) ; <i64> [#uses=1]
%tmp1572 = tail call fastcc i32 @FirstOne() ; <i32> [#uses=1]
- %tmp1594 = load i32, i32* undef ; <i32> [#uses=1]
+ %tmp1594 = load i32, ptr undef ; <i32> [#uses=1]
%tmp1594.upgrd.5 = trunc i32 %tmp1594 to i8 ; <i8> [#uses=1]
%shift.upgrd.6 = zext i8 %tmp1594.upgrd.5 to i64 ; <i64> [#uses=1]
%tmp1595 = lshr i64 %tmp1591, %shift.upgrd.6 ; <i64> [#uses=1]
%tmp1595.upgrd.7 = trunc i64 %tmp1595 to i32 ; <i32> [#uses=1]
%tmp1596 = and i32 %tmp1595.upgrd.7, 255 ; <i32> [#uses=1]
%gep.upgrd.8 = zext i32 %tmp1596 to i64 ; <i64> [#uses=1]
- %tmp1598 = getelementptr [64 x [256 x i32]], [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; <i32*> [#uses=1]
- %tmp1599 = load i32, i32* %tmp1598 ; <i32> [#uses=1]
+ %tmp1598 = getelementptr [64 x [256 x i32]], ptr @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; <ptr> [#uses=1]
+ %tmp1599 = load i32, ptr %tmp1598 ; <i32> [#uses=1]
%tmp1602 = sub i32 0, %tmp1599 ; <i32> [#uses=1]
br i1 undef, label %cond_next1637, label %cond_true1607
diff --git a/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll b/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll
index deb588403265e..ea1457374f68a 100644
--- a/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll
+++ b/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll
@@ -8,23 +8,23 @@ target triple = "armv6-apple-darwin"
%struct.q = type { i32, i32 }
- at .str = external constant [1 x i8] ; <[1 x i8]*> [#uses=1]
+ at .str = external constant [1 x i8] ; <ptr> [#uses=1]
-define void @yy(%struct.q* %qq) nounwind {
+define void @yy(ptr %qq) nounwind {
entry:
- %vla6 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1]
- %vla10 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1]
- %vla14 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1]
- %vla18 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1]
- %tmp21 = load i32, i32* undef ; <i32> [#uses=1]
+ %vla6 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1]
+ %vla10 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1]
+ %vla14 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1]
+ %vla18 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1]
+ %tmp21 = load i32, ptr undef ; <i32> [#uses=1]
%0 = mul i32 1, %tmp21 ; <i32> [#uses=1]
- %vla22 = alloca i8, i32 %0, align 1 ; <i8*> [#uses=1]
- call void (...) @zz(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1)
+ %vla22 = alloca i8, i32 %0, align 1 ; <ptr> [#uses=1]
+ call void (...) @zz(ptr @.str, i32 2, i32 1)
br i1 undef, label %if.then, label %if.end36
if.then: ; preds = %entry
- %call = call i32 (...) @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; <i32> [#uses=0]
- %call35 = call i32 (...) @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; <i32> [#uses=0]
+ %call = call i32 (...) @x(ptr undef, ptr undef, ptr %vla6, ptr %vla10, i32 undef) ; <i32> [#uses=0]
+ %call35 = call i32 (...) @x(ptr undef, ptr %vla14, ptr %vla18, ptr %vla22, i32 undef) ; <i32> [#uses=0]
unreachable
if.end36: ; preds = %entry
diff --git a/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
index f0b7141b5c7a2..87ed82e83ecf8 100644
--- a/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
+++ b/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
@@ -4,7 +4,7 @@
%struct.foo = type { i64, i64 }
-define zeroext i8 @t(%struct.foo* %this, i1 %tst) noreturn optsize {
+define zeroext i8 @t(ptr %this, i1 %tst) noreturn optsize {
entry:
; ARM-LABEL: t:
; ARM-DAG: mov r[[ADDR:[0-9]+]], #8
@@ -16,12 +16,12 @@ entry:
; THUMB-DAG: movs [[VAL:r[0-9]+]], #0
; THUMB-NOT: str {{[a-z0-9]+}}, [{{[a-z0-9]+}}], {{[a-z0-9]+}}
; THUMB: str [[VAL]], [r[[ADDR]]]
- %0 = getelementptr inbounds %struct.foo, %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1]
- store i32 0, i32* inttoptr (i32 8 to i32*), align 8
+ %0 = getelementptr inbounds %struct.foo, ptr %this, i32 0, i32 1 ; <ptr> [#uses=1]
+ store i32 0, ptr inttoptr (i32 8 to ptr), align 8
br i1 %tst, label %bb.nph96, label %bb3
bb3: ; preds = %entry
- %1 = load i64, i64* %0, align 4 ; <i64> [#uses=0]
+ %1 = load i64, ptr %0, align 4 ; <i64> [#uses=0]
ret i8 42
bb.nph96: ; preds = %entry
diff --git a/llvm/test/CodeGen/ARM/2010-05-19-Shuffles.ll b/llvm/test/CodeGen/ARM/2010-05-19-Shuffles.ll
index 94d0f4abfb7e6..77d576322151e 100644
--- a/llvm/test/CodeGen/ARM/2010-05-19-Shuffles.ll
+++ b/llvm/test/CodeGen/ARM/2010-05-19-Shuffles.ll
@@ -13,9 +13,9 @@ define <8 x i8> @f2(<8 x i8> %x) nounwind {
ret <8 x i8> %y
}
-define void @f3(<4 x i64>* %xp) nounwind {
- %x = load <4 x i64>, <4 x i64>* %xp
+define void @f3(ptr %xp) nounwind {
+ %x = load <4 x i64>, ptr %xp
%y = shufflevector <4 x i64> %x, <4 x i64> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 1>
- store <4 x i64> %y, <4 x i64>* %xp
+ store <4 x i64> %y, ptr %xp
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll b/llvm/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll
index 171b6d2bcc5c9..0746ff22085cb 100644
--- a/llvm/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll
+++ b/llvm/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll
@@ -1,36 +1,36 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon -O0 -optimize-regalloc -regalloc=basic %s -o /dev/null
; This test would crash the rewriter when trying to handle a spill after one of
-; the @llvm.arm.neon.vld3.v8i8.p0i8 defined three parts of a register.
+; the @llvm.arm.neon.vld3.v8i8.p0 defined three parts of a register.
%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
-declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8*, i32) nounwind readonly
+declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr, i32) nounwind readonly
-declare void @llvm.arm.neon.vst3.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst3.p0.v8i8(ptr, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind
-define <8 x i8> @t3(i8* %A1, i8* %A2, i8* %A3, i8* %A4, i8* %A5, i8* %A6, i8* %A7, i8* %A8, i8* %B) nounwind {
- %tmp1b = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A2, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
+define <8 x i8> @t3(ptr %A1, ptr %A2, ptr %A3, ptr %A4, ptr %A5, ptr %A6, ptr %A7, ptr %A8, ptr %B) nounwind {
+ %tmp1b = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A2, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
%tmp2b = extractvalue %struct.__neon_int8x8x3_t %tmp1b, 0 ; <<8 x i8>> [#uses=1]
%tmp4b = extractvalue %struct.__neon_int8x8x3_t %tmp1b, 1 ; <<8 x i8>> [#uses=1]
- %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
+ %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
%tmp2d = extractvalue %struct.__neon_int8x8x3_t %tmp1d, 0 ; <<8 x i8>> [#uses=1]
%tmp4d = extractvalue %struct.__neon_int8x8x3_t %tmp1d, 1 ; <<8 x i8>> [#uses=1]
- %tmp1e = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A5, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
+ %tmp1e = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A5, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
%tmp2e = extractvalue %struct.__neon_int8x8x3_t %tmp1e, 0 ; <<8 x i8>> [#uses=1]
- %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
+ %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
%tmp2f = extractvalue %struct.__neon_int8x8x3_t %tmp1f, 0 ; <<8 x i8>> [#uses=1]
- %tmp1g = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A7, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
+ %tmp1g = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A7, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
%tmp2g = extractvalue %struct.__neon_int8x8x3_t %tmp1g, 0 ; <<8 x i8>> [#uses=1]
%tmp4g = extractvalue %struct.__neon_int8x8x3_t %tmp1g, 1 ; <<8 x i8>> [#uses=1]
- %tmp1h = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A8, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
+ %tmp1h = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A8, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
%tmp2h = extractvalue %struct.__neon_int8x8x3_t %tmp1h, 0 ; <<8 x i8>> [#uses=1]
%tmp3h = extractvalue %struct.__neon_int8x8x3_t %tmp1h, 2 ; <<8 x i8>> [#uses=1]
%tmp2bd = add <8 x i8> %tmp2b, %tmp2d ; <<8 x i8>> [#uses=1]
%tmp4bd = add <8 x i8> %tmp4b, %tmp4d ; <<8 x i8>> [#uses=1]
%tmp2abcd = mul <8 x i8> undef, %tmp2bd ; <<8 x i8>> [#uses=1]
%tmp4abcd = mul <8 x i8> undef, %tmp4bd ; <<8 x i8>> [#uses=2]
- call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %A1, <8 x i8> %tmp4abcd, <8 x i8> zeroinitializer, <8 x i8> %tmp2abcd, i32 1)
+ call void @llvm.arm.neon.vst3.p0.v8i8(ptr %A1, <8 x i8> %tmp4abcd, <8 x i8> zeroinitializer, <8 x i8> %tmp2abcd, i32 1)
%tmp2ef = sub <8 x i8> %tmp2e, %tmp2f ; <<8 x i8>> [#uses=1]
%tmp2gh = sub <8 x i8> %tmp2g, %tmp2h ; <<8 x i8>> [#uses=1]
%tmp3gh = sub <8 x i8> zeroinitializer, %tmp3h ; <<8 x i8>> [#uses=1]
@@ -38,8 +38,8 @@ define <8 x i8> @t3(i8* %A1, i8* %A2, i8* %A3, i8* %A4, i8* %A5, i8* %A6, i8* %A
%tmp2efgh = mul <8 x i8> %tmp2ef, %tmp2gh ; <<8 x i8>> [#uses=1]
%tmp3efgh = mul <8 x i8> undef, %tmp3gh ; <<8 x i8>> [#uses=1]
%tmp4efgh = mul <8 x i8> %tmp4ef, undef ; <<8 x i8>> [#uses=2]
- call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %A2, <8 x i8> %tmp4efgh, <8 x i8> %tmp3efgh, <8 x i8> %tmp2efgh, i32 1)
+ call void @llvm.arm.neon.vst3.p0.v8i8(ptr %A2, <8 x i8> %tmp4efgh, <8 x i8> %tmp3efgh, <8 x i8> %tmp2efgh, i32 1)
%tmp4 = sub <8 x i8> %tmp4efgh, %tmp4abcd ; <<8 x i8>> [#uses=1]
- tail call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %B, <8 x i8> zeroinitializer, <8 x i8> undef, <8 x i8> undef, i32 1)
+ tail call void @llvm.arm.neon.vst3.p0.v8i8(ptr %B, <8 x i8> zeroinitializer, <8 x i8> undef, <8 x i8> undef, i32 1)
ret <8 x i8> %tmp4
}
diff --git a/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll b/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll
index c6c0e2caee420..e9cea62f586ba 100644
--- a/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll
+++ b/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll
@@ -1,43 +1,42 @@
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
; Radar 7872877
-define void @test(float* %fltp, i32 %packedValue, float* %table) nounwind {
+define void @test(ptr %fltp, i32 %packedValue, ptr %table) nounwind {
entry:
- %0 = load float, float* %fltp
+ %0 = load float, ptr %fltp
%1 = insertelement <4 x float> undef, float %0, i32 0
%2 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> zeroinitializer
%3 = shl i32 %packedValue, 16
%4 = ashr i32 %3, 30
%.sum = add i32 %4, 4
- %5 = getelementptr inbounds float, float* %table, i32 %.sum
+ %5 = getelementptr inbounds float, ptr %table, i32 %.sum
;CHECK: vldr s
- %6 = load float, float* %5, align 4
+ %6 = load float, ptr %5, align 4
%tmp11 = insertelement <4 x float> undef, float %6, i32 0
%7 = shl i32 %packedValue, 18
%8 = ashr i32 %7, 30
%.sum12 = add i32 %8, 4
- %9 = getelementptr inbounds float, float* %table, i32 %.sum12
+ %9 = getelementptr inbounds float, ptr %table, i32 %.sum12
;CHECK: vldr s
- %10 = load float, float* %9, align 4
+ %10 = load float, ptr %9, align 4
%tmp9 = insertelement <4 x float> %tmp11, float %10, i32 1
%11 = shl i32 %packedValue, 20
%12 = ashr i32 %11, 30
%.sum13 = add i32 %12, 4
- %13 = getelementptr inbounds float, float* %table, i32 %.sum13
+ %13 = getelementptr inbounds float, ptr %table, i32 %.sum13
;CHECK: vldr s
- %14 = load float, float* %13, align 4
+ %14 = load float, ptr %13, align 4
%tmp7 = insertelement <4 x float> %tmp9, float %14, i32 2
%15 = shl i32 %packedValue, 22
%16 = ashr i32 %15, 30
%.sum14 = add i32 %16, 4
- %17 = getelementptr inbounds float, float* %table, i32 %.sum14
+ %17 = getelementptr inbounds float, ptr %table, i32 %.sum14
;CHECK: vldr s
- %18 = load float, float* %17, align 4
+ %18 = load float, ptr %17, align 4
%tmp5 = insertelement <4 x float> %tmp7, float %18, i32 3
%19 = fmul <4 x float> %tmp5, %2
- %20 = bitcast float* %fltp to i8*
- tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %20, <4 x float> %19, i32 1)
+ tail call void @llvm.arm.neon.vst1.p0.v4f32(ptr %fltp, <4 x float> %19, i32 1)
ret void
}
-declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v4f32(ptr, <4 x float>, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll b/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll
index 1deb98631a4f6..b72c307955958 100644
--- a/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll
+++ b/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll
@@ -3,17 +3,16 @@
%struct.__int8x8x2_t = type { [2 x <8 x i8>] }
-define void @foo(%struct.__int8x8x2_t* nocapture %a, i8* %b) nounwind {
+define void @foo(ptr nocapture %a, ptr %b) nounwind {
entry:
- %0 = bitcast %struct.__int8x8x2_t* %a to i128* ; <i128*> [#uses=1]
- %srcval = load i128, i128* %0, align 8 ; <i128> [#uses=2]
+ %srcval = load i128, ptr %a, align 8 ; <i128> [#uses=2]
%tmp6 = trunc i128 %srcval to i64 ; <i64> [#uses=1]
%tmp8 = lshr i128 %srcval, 64 ; <i128> [#uses=1]
%tmp9 = trunc i128 %tmp8 to i64 ; <i64> [#uses=1]
%tmp16.i = bitcast i64 %tmp6 to <8 x i8> ; <<8 x i8>> [#uses=1]
%tmp20.i = bitcast i64 %tmp9 to <8 x i8> ; <<8 x i8>> [#uses=1]
- tail call void @llvm.arm.neon.vst2.p0i8.v8i8(i8* %b, <8 x i8> %tmp16.i, <8 x i8> %tmp20.i, i32 1) nounwind
+ tail call void @llvm.arm.neon.vst2.p0.v8i8(ptr %b, <8 x i8> %tmp16.i, <8 x i8> %tmp20.i, i32 1) nounwind
ret void
}
-declare void @llvm.arm.neon.vst2.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst2.p0.v8i8(ptr, <8 x i8>, <8 x i8>, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll b/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll
index 6f55ac0580543..7bf577b5b7c8d 100644
--- a/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll
+++ b/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll
@@ -2,26 +2,26 @@
; PR7421
%struct.CONTENTBOX = type { i32, i32, i32, i32, i32 }
-%struct.FILE = type { i8* }
-%struct.tilebox = type { %struct.tilebox*, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+%struct.FILE = type { ptr }
+%struct.tilebox = type { ptr, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.UNCOMBOX = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
-%struct.cellbox = type { i8*, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, double, double, double, double, double, i32, i32, %struct.CONTENTBOX*, %struct.UNCOMBOX*, [8 x %struct.tilebox*] }
-%struct.termbox = type { %struct.termbox*, i32, i32, i32, i32, i32 }
+%struct.cellbox = type { ptr, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, double, double, double, double, double, i32, i32, ptr, ptr, [8 x ptr] }
+%struct.termbox = type { ptr, i32, i32, i32, i32, i32 }
- at .str2708 = external constant [14 x i8], align 4 ; <[14 x i8]*> [#uses=1]
+ at .str2708 = external constant [14 x i8], align 4 ; <ptr> [#uses=1]
-define void @TW_oldinput(%struct.FILE* nocapture %fp) nounwind {
+define void @TW_oldinput(ptr nocapture %fp) nounwind {
entry:
- %xcenter = alloca i32, align 4 ; <i32*> [#uses=2]
- %0 = call i32 (%struct.FILE*, i8*, ...) @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1]
+ %xcenter = alloca i32, align 4 ; <ptr> [#uses=2]
+ %0 = call i32 (ptr, ptr, ...) @fscanf(ptr %fp, ptr @.str2708, ptr undef, ptr undef, ptr %xcenter, ptr null) nounwind ; <i32> [#uses=1]
%1 = icmp eq i32 %0, 4 ; <i1> [#uses=1]
br i1 %1, label %bb, label %return
bb: ; preds = %bb445, %entry
- %2 = load %struct.cellbox*, %struct.cellbox** undef, align 4 ; <%struct.cellbox*> [#uses=2]
- %3 = getelementptr inbounds %struct.cellbox, %struct.cellbox* %2, i32 0, i32 3 ; <i32*> [#uses=1]
- store i32 undef, i32* %3, align 4
- %4 = load i32, i32* undef, align 4 ; <i32> [#uses=3]
+ %2 = load ptr, ptr undef, align 4 ; <ptr> [#uses=2]
+ %3 = getelementptr inbounds %struct.cellbox, ptr %2, i32 0, i32 3 ; <ptr> [#uses=1]
+ store i32 undef, ptr %3, align 4
+ %4 = load i32, ptr undef, align 4 ; <i32> [#uses=3]
%5 = icmp eq i32 undef, 1 ; <i1> [#uses=1]
br i1 %5, label %bb10, label %bb445
@@ -29,12 +29,12 @@ bb10: ; preds = %bb
br i1 undef, label %bb11, label %bb445
bb11: ; preds = %bb10
- %6 = load %struct.tilebox*, %struct.tilebox** undef, align 4 ; <%struct.tilebox*> [#uses=3]
- %7 = load %struct.termbox*, %struct.termbox** null, align 4 ; <%struct.termbox*> [#uses=1]
- %8 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %6, i32 0, i32 13 ; <i32*> [#uses=1]
- %9 = load i32, i32* %8, align 4 ; <i32> [#uses=3]
- %10 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %6, i32 0, i32 15 ; <i32*> [#uses=1]
- %11 = load i32, i32* %10, align 4 ; <i32> [#uses=1]
+ %6 = load ptr, ptr undef, align 4 ; <ptr> [#uses=3]
+ %7 = load ptr, ptr null, align 4 ; <ptr> [#uses=1]
+ %8 = getelementptr inbounds %struct.tilebox, ptr %6, i32 0, i32 13 ; <ptr> [#uses=1]
+ %9 = load i32, ptr %8, align 4 ; <i32> [#uses=3]
+ %10 = getelementptr inbounds %struct.tilebox, ptr %6, i32 0, i32 15 ; <ptr> [#uses=1]
+ %11 = load i32, ptr %10, align 4 ; <i32> [#uses=1]
br i1 false, label %bb12, label %bb13
bb12: ; preds = %bb11
@@ -57,7 +57,7 @@ bb21: ; preds = %bb13
%18 = zext i1 %not.460 to i32 ; <i32> [#uses=1]
%iftmp.42.0 = add i32 %16, %iftmp.41.0.neg ; <i32> [#uses=1]
%19 = add i32 %iftmp.42.0, %18 ; <i32> [#uses=1]
- store i32 %19, i32* undef, align 4
+ store i32 %19, ptr undef, align 4
%20 = sub nsw i32 0, %9 ; <i32> [#uses=1]
%21 = sitofp i32 %20 to double ; <double> [#uses=1]
%22 = fdiv double %21, 0.000000e+00 ; <double> [#uses=2]
@@ -67,34 +67,34 @@ bb21: ; preds = %bb13
%25 = zext i1 %not.461 to i32 ; <i32> [#uses=1]
%iftmp.43.0 = add i32 %23, %iftmp.41.0.neg ; <i32> [#uses=1]
%26 = add i32 %iftmp.43.0, %25 ; <i32> [#uses=1]
- %27 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %6, i32 0, i32 10 ; <i32*> [#uses=1]
- store i32 %26, i32* %27, align 4
+ %27 = getelementptr inbounds %struct.tilebox, ptr %6, i32 0, i32 10 ; <ptr> [#uses=1]
+ store i32 %26, ptr %27, align 4
%28 = fptosi double undef to i32 ; <i32> [#uses=1]
%iftmp.45.0 = add i32 %28, %iftmp.40.0.neg ; <i32> [#uses=1]
%29 = add i32 %iftmp.45.0, 0 ; <i32> [#uses=1]
- store i32 %29, i32* undef, align 4
+ store i32 %29, ptr undef, align 4
br label %bb43.loopexit
bb36: ; preds = %bb43.loopexit, %bb36
- %termptr.0478 = phi %struct.termbox* [ %42, %bb36 ], [ %7, %bb43.loopexit ] ; <%struct.termbox*> [#uses=1]
- %30 = load i32, i32* undef, align 4 ; <i32> [#uses=1]
+ %termptr.0478 = phi ptr [ %42, %bb36 ], [ %7, %bb43.loopexit ] ; <ptr> [#uses=1]
+ %30 = load i32, ptr undef, align 4 ; <i32> [#uses=1]
%31 = sub nsw i32 %30, %9 ; <i32> [#uses=1]
%32 = sitofp i32 %31 to double ; <double> [#uses=1]
%33 = fdiv double %32, 0.000000e+00 ; <double> [#uses=1]
%34 = fptosi double %33 to i32 ; <i32> [#uses=1]
%iftmp.46.0 = add i32 %34, %iftmp.41.0.neg ; <i32> [#uses=1]
%35 = add i32 %iftmp.46.0, 0 ; <i32> [#uses=1]
- store i32 %35, i32* undef, align 4
+ store i32 %35, ptr undef, align 4
%36 = sub nsw i32 0, %11 ; <i32> [#uses=1]
%37 = sitofp i32 %36 to double ; <double> [#uses=1]
%38 = fmul double %37, 0.000000e+00 ; <double> [#uses=1]
%39 = fptosi double %38 to i32 ; <i32> [#uses=1]
%iftmp.47.0 = add i32 %39, %iftmp.40.0.neg ; <i32> [#uses=1]
%40 = add i32 %iftmp.47.0, 0 ; <i32> [#uses=1]
- store i32 %40, i32* undef, align 4
- %41 = getelementptr inbounds %struct.termbox, %struct.termbox* %termptr.0478, i32 0, i32 0 ; <%struct.termbox**> [#uses=1]
- %42 = load %struct.termbox*, %struct.termbox** %41, align 4 ; <%struct.termbox*> [#uses=2]
- %43 = icmp eq %struct.termbox* %42, null ; <i1> [#uses=1]
+ store i32 %40, ptr undef, align 4
+ %41 = getelementptr inbounds %struct.termbox, ptr %termptr.0478, i32 0, i32 0 ; <ptr> [#uses=1]
+ %42 = load ptr, ptr %41, align 4 ; <ptr> [#uses=2]
+ %43 = icmp eq ptr %42, null ; <i1> [#uses=1]
br i1 %43, label %bb52.loopexit, label %bb36
bb43.loopexit: ; preds = %bb21, %bb13
@@ -127,17 +127,17 @@ bb248: ; preds = %bb322, %bb.nph485
br i1 %45, label %bb322, label %bb249
bb249: ; preds = %bb248
- %46 = getelementptr inbounds %struct.cellbox, %struct.cellbox* %2, i32 0, i32 21, i32 undef ; <%struct.tilebox**> [#uses=1]
- %47 = load %struct.tilebox*, %struct.tilebox** %46, align 4 ; <%struct.tilebox*> [#uses=1]
- %48 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %47, i32 0, i32 11 ; <i32*> [#uses=1]
- store i32 undef, i32* %48, align 4
+ %46 = getelementptr inbounds %struct.cellbox, ptr %2, i32 0, i32 21, i32 undef ; <ptr> [#uses=1]
+ %47 = load ptr, ptr %46, align 4 ; <ptr> [#uses=1]
+ %48 = getelementptr inbounds %struct.tilebox, ptr %47, i32 0, i32 11 ; <ptr> [#uses=1]
+ store i32 undef, ptr %48, align 4
unreachable
bb322: ; preds = %bb248
br i1 undef, label %bb248, label %bb445
bb445: ; preds = %bb322, %bb10, %bb
- %49 = call i32 (%struct.FILE*, i8*, ...) @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1]
+ %49 = call i32 (ptr, ptr, ...) @fscanf(ptr %fp, ptr @.str2708, ptr undef, ptr undef, ptr %xcenter, ptr null) nounwind ; <i32> [#uses=1]
%50 = icmp eq i32 %49, 4 ; <i1> [#uses=1]
br i1 %50, label %bb, label %return
@@ -145,4 +145,4 @@ return: ; preds = %bb445, %entry
ret void
}
-declare i32 @fscanf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind
+declare i32 @fscanf(ptr nocapture, ptr nocapture, ...) nounwind
diff --git a/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll b/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll
index a1dcdd6283deb..938787af96244 100644
--- a/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll
+++ b/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll
@@ -2,116 +2,110 @@
; PR 7433
; XFAIL: *
-%0 = type { i8*, i8* }
-%1 = type { i8*, i8*, i8* }
+%0 = type { ptr, ptr }
+%1 = type { ptr, ptr, ptr }
%"class.llvm::Record" = type { i32, %"class.std::basic_string", %"class.llvm::SMLoc", %"class.std::vector", %"class.std::vector", %"class.std::vector" }
-%"class.llvm::RecordVal" = type { %"class.std::basic_string", %"struct.llvm::Init"*, i32, %"struct.llvm::Init"* }
-%"class.llvm::SMLoc" = type { i8* }
+%"class.llvm::RecordVal" = type { %"class.std::basic_string", ptr, i32, ptr }
+%"class.llvm::SMLoc" = type { ptr }
%"class.llvm::StringInit" = type { [8 x i8], %"class.std::basic_string" }
%"class.std::basic_string" = type { %"class.llvm::SMLoc" }
%"class.std::vector" = type { [12 x i8] }
-%"struct.llvm::Init" = type { i32 (...)** }
+%"struct.llvm::Init" = type { ptr }
- at _ZTIN4llvm5RecTyE = external constant %0 ; <%0*> [#uses=1]
- at _ZTIN4llvm4InitE = external constant %0 ; <%0*> [#uses=1]
- at _ZTIN4llvm11RecordRecTyE = external constant %1 ; <%1*> [#uses=1]
- at .str8 = external constant [47 x i8] ; <[47 x i8]*> [#uses=1]
- at _ZTIN4llvm9UnsetInitE = external constant %1 ; <%1*> [#uses=1]
- at .str51 = external constant [45 x i8] ; <[45 x i8]*> [#uses=1]
- at __PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs = external constant [116 x i8] ; <[116 x i8]*> [#uses=1]
+ at _ZTIN4llvm5RecTyE = external constant %0 ; <ptr> [#uses=1]
+ at _ZTIN4llvm4InitE = external constant %0 ; <ptr> [#uses=1]
+ at _ZTIN4llvm11RecordRecTyE = external constant %1 ; <ptr> [#uses=1]
+ at .str8 = external constant [47 x i8] ; <ptr> [#uses=1]
+ at _ZTIN4llvm9UnsetInitE = external constant %1 ; <ptr> [#uses=1]
+ at .str51 = external constant [45 x i8] ; <ptr> [#uses=1]
+ at __PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs = external constant [116 x i8] ; <ptr> [#uses=1]
- at _ZN4llvm9RecordValC1ERKSsPNS_5RecTyEj = alias void (%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32), void (%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32)* @_ZN4llvm9RecordValC2ERKSsPNS_5RecTyEj ; <void (%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32)*> [#uses=0]
+ at _ZN4llvm9RecordValC1ERKSsPNS_5RecTyEj = alias void (ptr, ptr, ptr, i32), ptr @_ZN4llvm9RecordValC2ERKSsPNS_5RecTyEj ; <ptr> [#uses=0]
-declare i8* @__dynamic_cast(i8*, i8*, i8*, i32)
+declare ptr @__dynamic_cast(ptr, ptr, ptr, i32)
-declare void @__assert_fail(i8*, i8*, i32, i8*) noreturn
+declare void @__assert_fail(ptr, ptr, i32, ptr) noreturn
-declare void @_ZN4llvm9RecordValC2ERKSsPNS_5RecTyEj(%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32) align 2
+declare void @_ZN4llvm9RecordValC2ERKSsPNS_5RecTyEj(ptr, ptr, ptr, i32) align 2
-define %"struct.llvm::Init"* @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs(%"class.llvm::StringInit"* %this, %"class.llvm::Record"* %R, %"class.llvm::RecordVal"* %RV, %"class.std::basic_string"* %FieldName) align 2 {
+define ptr @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs(ptr %this, ptr %R, ptr %RV, ptr %FieldName) align 2 {
;CHECK: ldmia sp!, {r4, r5, r6, r7, r8, lr}
;CHECK: bx r12 @ TAILCALL
entry:
- %.loc = alloca i32 ; <i32*> [#uses=2]
- %tmp.i = getelementptr inbounds %"class.llvm::StringInit", %"class.llvm::StringInit"* %this, i32 0, i32 0, i32 4 ; <i8*> [#uses=1]
- %0 = bitcast i8* %tmp.i to %"struct.llvm::Init"** ; <%"struct.llvm::Init"**> [#uses=1]
- %tmp2.i = load %"struct.llvm::Init"*, %"struct.llvm::Init"** %0 ; <%"struct.llvm::Init"*> [#uses=2]
- %1 = icmp eq %"struct.llvm::Init"* %tmp2.i, null ; <i1> [#uses=1]
- br i1 %1, label %entry.return_crit_edge, label %tmpbb
+ %.loc = alloca i32 ; <ptr> [#uses=2]
+ %tmp.i = getelementptr inbounds %"class.llvm::StringInit", ptr %this, i32 0, i32 0, i32 4 ; <ptr> [#uses=1]
+ %tmp2.i = load ptr, ptr %tmp.i ; <ptr> [#uses=2]
+ %0 = icmp eq ptr %tmp2.i, null ; <i1> [#uses=1]
+ br i1 %0, label %entry.return_crit_edge, label %tmpbb
entry.return_crit_edge: ; preds = %entry
br label %return
tmpbb: ; preds = %entry
- %2 = bitcast %"struct.llvm::Init"* %tmp2.i to i8* ; <i8*> [#uses=1]
- %3 = tail call i8* @__dynamic_cast(i8* %2, i8* bitcast (%0* @_ZTIN4llvm5RecTyE to i8*), i8* bitcast (%1* @_ZTIN4llvm11RecordRecTyE to i8*), i32 -1) ; <i8*> [#uses=1]
- %phitmp = icmp eq i8* %3, null ; <i1> [#uses=1]
+ %1 = tail call ptr @__dynamic_cast(ptr %tmp2.i, ptr @_ZTIN4llvm5RecTyE, ptr @_ZTIN4llvm11RecordRecTyE, i32 -1) ; <ptr> [#uses=1]
+ %phitmp = icmp eq ptr %1, null ; <i1> [#uses=1]
br i1 %phitmp, label %.return_crit_edge, label %if.then
.return_crit_edge: ; preds = %tmpbb
br label %return
if.then: ; preds = %tmpbb
- %tmp2.i.i.i.i = getelementptr inbounds %"class.llvm::StringInit", %"class.llvm::StringInit"* %this, i32 0, i32 1, i32 0, i32 0 ; <i8**> [#uses=1]
- %tmp3.i.i.i.i = load i8*, i8** %tmp2.i.i.i.i ; <i8*> [#uses=2]
- %arrayidx.i.i.i.i = getelementptr inbounds i8, i8* %tmp3.i.i.i.i, i32 -12 ; <i8*> [#uses=1]
- %tmp.i.i.i = bitcast i8* %arrayidx.i.i.i.i to i32* ; <i32*> [#uses=1]
- %tmp2.i.i.i = load i32, i32* %tmp.i.i.i ; <i32> [#uses=1]
- %tmp.i5 = getelementptr inbounds %"class.llvm::Record", %"class.llvm::Record"* %R, i32 0, i32 4 ; <%"class.std::vector"*> [#uses=1]
- %tmp2.i.i = getelementptr inbounds %"class.llvm::Record", %"class.llvm::Record"* %R, i32 0, i32 4, i32 0, i32 4 ; <i8*> [#uses=1]
- %4 = bitcast i8* %tmp2.i.i to %"class.llvm::RecordVal"** ; <%"class.llvm::RecordVal"**> [#uses=1]
- %tmp3.i.i6 = load %"class.llvm::RecordVal"*, %"class.llvm::RecordVal"** %4 ; <%"class.llvm::RecordVal"*> [#uses=1]
- %tmp5.i.i = bitcast %"class.std::vector"* %tmp.i5 to %"class.llvm::RecordVal"** ; <%"class.llvm::RecordVal"**> [#uses=1]
- %tmp6.i.i = load %"class.llvm::RecordVal"*, %"class.llvm::RecordVal"** %tmp5.i.i ; <%"class.llvm::RecordVal"*> [#uses=5]
- %sub.ptr.lhs.cast.i.i = ptrtoint %"class.llvm::RecordVal"* %tmp3.i.i6 to i32 ; <i32> [#uses=1]
- %sub.ptr.rhs.cast.i.i = ptrtoint %"class.llvm::RecordVal"* %tmp6.i.i to i32 ; <i32> [#uses=1]
+ %tmp2.i.i.i.i = getelementptr inbounds %"class.llvm::StringInit", ptr %this, i32 0, i32 1, i32 0, i32 0 ; <ptr> [#uses=1]
+ %tmp3.i.i.i.i = load ptr, ptr %tmp2.i.i.i.i ; <ptr> [#uses=2]
+ %arrayidx.i.i.i.i = getelementptr inbounds i8, ptr %tmp3.i.i.i.i, i32 -12 ; <ptr> [#uses=1]
+ %tmp2.i.i.i = load i32, ptr %arrayidx.i.i.i.i ; <i32> [#uses=1]
+ %tmp.i5 = getelementptr inbounds %"class.llvm::Record", ptr %R, i32 0, i32 4 ; <ptr> [#uses=1]
+ %tmp2.i.i = getelementptr inbounds %"class.llvm::Record", ptr %R, i32 0, i32 4, i32 0, i32 4 ; <ptr> [#uses=1]
+ %tmp3.i.i6 = load ptr, ptr %tmp2.i.i ; <ptr> [#uses=1]
+ %tmp6.i.i = load ptr, ptr %tmp.i5 ; <ptr> [#uses=5]
+ %sub.ptr.lhs.cast.i.i = ptrtoint ptr %tmp3.i.i6 to i32 ; <i32> [#uses=1]
+ %sub.ptr.rhs.cast.i.i = ptrtoint ptr %tmp6.i.i to i32 ; <i32> [#uses=1]
%sub.ptr.sub.i.i = sub i32 %sub.ptr.lhs.cast.i.i, %sub.ptr.rhs.cast.i.i ; <i32> [#uses=1]
%sub.ptr.div.i.i = ashr i32 %sub.ptr.sub.i.i, 4 ; <i32> [#uses=1]
br label %codeRepl
codeRepl: ; preds = %if.then
- %targetBlock = call i1 @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs_for.cond.i(i32 %sub.ptr.div.i.i, %"class.llvm::RecordVal"* %tmp6.i.i, i32 %tmp2.i.i.i, i8* %tmp3.i.i.i.i, i32* %.loc) ; <i1> [#uses=1]
- %.reload = load i32, i32* %.loc ; <i32> [#uses=3]
+ %targetBlock = call i1 @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs_for.cond.i(i32 %sub.ptr.div.i.i, ptr %tmp6.i.i, i32 %tmp2.i.i.i, ptr %tmp3.i.i.i.i, ptr %.loc) ; <i1> [#uses=1]
+ %.reload = load i32, ptr %.loc ; <i32> [#uses=3]
br i1 %targetBlock, label %for.cond.i.return_crit_edge, label %_ZN4llvm6Record8getValueENS_9StringRefE.exit
for.cond.i.return_crit_edge: ; preds = %codeRepl
br label %return
_ZN4llvm6Record8getValueENS_9StringRefE.exit: ; preds = %codeRepl
- %add.ptr.i.i = getelementptr inbounds %"class.llvm::RecordVal", %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload ; <%"class.llvm::RecordVal"*> [#uses=2]
- %tobool5 = icmp eq %"class.llvm::RecordVal"* %add.ptr.i.i, null ; <i1> [#uses=1]
+ %add.ptr.i.i = getelementptr inbounds %"class.llvm::RecordVal", ptr %tmp6.i.i, i32 %.reload ; <ptr> [#uses=2]
+ %tobool5 = icmp eq ptr %add.ptr.i.i, null ; <i1> [#uses=1]
br i1 %tobool5, label %_ZN4llvm6Record8getValueENS_9StringRefE.exit.return_crit_edge, label %if.then6
_ZN4llvm6Record8getValueENS_9StringRefE.exit.return_crit_edge: ; preds = %_ZN4llvm6Record8getValueENS_9StringRefE.exit
br label %return
if.then6: ; preds = %_ZN4llvm6Record8getValueENS_9StringRefE.exit
- %cmp = icmp eq %"class.llvm::RecordVal"* %add.ptr.i.i, %RV ; <i1> [#uses=1]
+ %cmp = icmp eq ptr %add.ptr.i.i, %RV ; <i1> [#uses=1]
br i1 %cmp, label %if.then6.if.end_crit_edge, label %land.lhs.true
if.then6.if.end_crit_edge: ; preds = %if.then6
br label %if.end
land.lhs.true: ; preds = %if.then6
- %tobool10 = icmp eq %"class.llvm::RecordVal"* %RV, null ; <i1> [#uses=1]
+ %tobool10 = icmp eq ptr %RV, null ; <i1> [#uses=1]
br i1 %tobool10, label %lor.lhs.false, label %land.lhs.true.return_crit_edge
land.lhs.true.return_crit_edge: ; preds = %land.lhs.true
br label %return
lor.lhs.false: ; preds = %land.lhs.true
- %tmp.i3 = getelementptr inbounds %"class.llvm::RecordVal", %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1]
- %tmp2.i4 = load %"struct.llvm::Init"*, %"struct.llvm::Init"** %tmp.i3 ; <%"struct.llvm::Init"*> [#uses=2]
- %5 = icmp eq %"struct.llvm::Init"* %tmp2.i4, null ; <i1> [#uses=1]
- br i1 %5, label %lor.lhs.false.if.end_crit_edge, label %tmpbb1
+ %tmp.i3 = getelementptr inbounds %"class.llvm::RecordVal", ptr %tmp6.i.i, i32 %.reload, i32 3 ; <ptr> [#uses=1]
+ %tmp2.i4 = load ptr, ptr %tmp.i3 ; <ptr> [#uses=2]
+ %2 = icmp eq ptr %tmp2.i4, null ; <i1> [#uses=1]
+ br i1 %2, label %lor.lhs.false.if.end_crit_edge, label %tmpbb1
lor.lhs.false.if.end_crit_edge: ; preds = %lor.lhs.false
br label %if.end
tmpbb1: ; preds = %lor.lhs.false
- %6 = bitcast %"struct.llvm::Init"* %tmp2.i4 to i8* ; <i8*> [#uses=1]
- %7 = tail call i8* @__dynamic_cast(i8* %6, i8* bitcast (%0* @_ZTIN4llvm4InitE to i8*), i8* bitcast (%1* @_ZTIN4llvm9UnsetInitE to i8*), i32 -1) ; <i8*> [#uses=1]
- %phitmp32 = icmp eq i8* %7, null ; <i1> [#uses=1]
+ %3 = tail call ptr @__dynamic_cast(ptr %tmp2.i4, ptr @_ZTIN4llvm4InitE, ptr @_ZTIN4llvm9UnsetInitE, i32 -1) ; <ptr> [#uses=1]
+ %phitmp32 = icmp eq ptr %3, null ; <i1> [#uses=1]
br i1 %phitmp32, label %.if.end_crit_edge, label %.return_crit_edge1
.return_crit_edge1: ; preds = %tmpbb1
@@ -121,26 +115,24 @@ tmpbb1: ; preds = %lor.lhs.false
br label %if.end
if.end: ; preds = %.if.end_crit_edge, %lor.lhs.false.if.end_crit_edge, %if.then6.if.end_crit_edge
- %tmp.i1 = getelementptr inbounds %"class.llvm::RecordVal", %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1]
- %tmp2.i2 = load %"struct.llvm::Init"*, %"struct.llvm::Init"** %tmp.i1 ; <%"struct.llvm::Init"*> [#uses=3]
- %8 = bitcast %"class.llvm::StringInit"* %this to %"struct.llvm::Init"* ; <%"struct.llvm::Init"*> [#uses=1]
- %cmp19 = icmp eq %"struct.llvm::Init"* %tmp2.i2, %8 ; <i1> [#uses=1]
+ %tmp.i1 = getelementptr inbounds %"class.llvm::RecordVal", ptr %tmp6.i.i, i32 %.reload, i32 3 ; <ptr> [#uses=1]
+ %tmp2.i2 = load ptr, ptr %tmp.i1 ; <ptr> [#uses=3]
+ %cmp19 = icmp eq ptr %tmp2.i2, %this ; <i1> [#uses=1]
br i1 %cmp19, label %cond.false, label %cond.end
cond.false: ; preds = %if.end
- tail call void @__assert_fail(i8* getelementptr inbounds ([45 x i8], [45 x i8]* @.str51, i32 0, i32 0), i8* getelementptr inbounds ([47 x i8], [47 x i8]* @.str8, i32 0, i32 0), i32 1141, i8* getelementptr inbounds ([116 x i8], [116 x i8]* @__PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs, i32 0, i32 0)) noreturn
+ tail call void @__assert_fail(ptr @.str51, ptr @.str8, i32 1141, ptr @__PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs) noreturn
unreachable
cond.end: ; preds = %if.end
- %9 = bitcast %"struct.llvm::Init"* %tmp2.i2 to %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)***> [#uses=1]
- %10 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**, %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** %9 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1]
- %vfn = getelementptr inbounds %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*, %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %10, i32 8 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1]
- %11 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*, %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %vfn ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*> [#uses=1]
- %call25 = tail call %"struct.llvm::Init"* %11(%"struct.llvm::Init"* %tmp2.i2, %"class.llvm::Record"* %R, %"class.llvm::RecordVal"* %RV, %"class.std::basic_string"* %FieldName) ; <%"struct.llvm::Init"*> [#uses=1]
- ret %"struct.llvm::Init"* %call25
+ %4 = load ptr, ptr %tmp2.i2 ; <ptr> [#uses=1]
+ %vfn = getelementptr inbounds ptr, ptr %4, i32 8 ; <ptr> [#uses=1]
+ %5 = load ptr, ptr %vfn ; <ptr> [#uses=1]
+ %call25 = tail call ptr %5(ptr %tmp2.i2, ptr %R, ptr %RV, ptr %FieldName) ; <ptr> [#uses=1]
+ ret ptr %call25
return: ; preds = %.return_crit_edge1, %land.lhs.true.return_crit_edge, %_ZN4llvm6Record8getValueENS_9StringRefE.exit.return_crit_edge, %for.cond.i.return_crit_edge, %.return_crit_edge, %entry.return_crit_edge
- ret %"struct.llvm::Init"* null
+ ret ptr null
}
-declare i1 @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs_for.cond.i(i32, %"class.llvm::RecordVal"*, i32, i8*, i32*)
+declare i1 @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs_for.cond.i(i32, ptr, i32, ptr, ptr)
diff --git a/llvm/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll b/llvm/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll
index 9ffb68cdeac84..0973d17d3c47b 100644
--- a/llvm/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll
+++ b/llvm/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll
@@ -7,11 +7,11 @@ target triple = "thumbv7-apple-darwin3.0.0-iphoneos"
@length = common global i32 0, align 4, !dbg !0
; Function Attrs: nounwind optsize
-define void @x0(i8* nocapture %buf, i32 %nbytes) #0 {
+define void @x0(ptr nocapture %buf, i32 %nbytes) #0 {
entry:
- tail call void @llvm.dbg.value(metadata i8* %buf, metadata !8, metadata !14), !dbg !15
+ tail call void @llvm.dbg.value(metadata ptr %buf, metadata !8, metadata !14), !dbg !15
tail call void @llvm.dbg.value(metadata i32 %nbytes, metadata !16, metadata !14), !dbg !18
- %tmp = load i32, i32* @length, !dbg !19
+ %tmp = load i32, ptr @length, !dbg !19
%cmp = icmp eq i32 %tmp, -1, !dbg !19
%cmp.not = xor i1 %cmp, true
%cmp3 = icmp ult i32 %tmp, %nbytes, !dbg !19
@@ -24,7 +24,7 @@ entry:
while.cond: ; preds = %while.body, %entry
%0 = phi i32 [ 0, %entry ], [ %inc, %while.body ]
- %buf.addr.0 = getelementptr i8, i8* %buf, i32 %0
+ %buf.addr.0 = getelementptr i8, ptr %buf, i32 %0
%cmp7 = icmp ult i32 %0, %nbytes.addr.0, !dbg !23
br i1 %cmp7, label %land.rhs, label %while.end, !dbg !23
@@ -35,7 +35,7 @@ land.rhs: ; preds = %while.cond
while.body: ; preds = %land.rhs
%conv = trunc i32 %call to i8, !dbg !24
- store i8 %conv, i8* %buf.addr.0, !dbg !24
+ store i8 %conv, ptr %buf.addr.0, !dbg !24
%inc = add i32 %0, 1, !dbg !26
br label %while.cond, !dbg !27
diff --git a/llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll b/llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
index c0b94134bec9d..ede148b73c412 100644
--- a/llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
+++ b/llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
@@ -14,12 +14,12 @@ target triple = "thumbv7-apple-darwin10"
; CHECK-NOT: vld1.64 {d16, d17}
; CHECK: vmov.f64
-define i32 @test(i8* %arg) nounwind {
+define i32 @test(ptr %arg) nounwind {
entry:
- %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8* %arg, i32 1)
+ %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0(ptr %arg, i32 1)
%1 = shufflevector <2 x i64> undef, <2 x i64> %0, <2 x i32> <i32 1, i32 2>
- store <2 x i64> %1, <2 x i64>* undef, align 16
+ store <2 x i64> %1, ptr undef, align 16
ret i32 undef
}
-declare <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8*, i32) nounwind readonly
+declare <2 x i64> @llvm.arm.neon.vld1.v2i64.p0(ptr, i32) nounwind readonly
diff --git a/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll b/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
index 03362a8e51f91..47f5eb253d757 100644
--- a/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
+++ b/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
@@ -1,15 +1,15 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o /dev/null
- at .str271 = external constant [21 x i8], align 4 ; <[21 x i8]*> [#uses=1]
- at llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32, i8**)* @main to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+ at .str271 = external constant [21 x i8], align 4 ; <ptr> [#uses=1]
+ at llvm.used = appending global [1 x ptr] [ptr @main], section "llvm.metadata" ; <ptr> [#uses=0]
-define i32 @main(i32 %argc, i8** %argv) nounwind {
+define i32 @main(i32 %argc, ptr %argv) nounwind {
entry:
%0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2> ; <<2 x i64>> [#uses=1]
- store <2 x i64> %0, <2 x i64>* undef, align 16
- %val4723 = load <8 x i16>, <8 x i16>* undef ; <<8 x i16>> [#uses=1]
- call void @PrintShortX(i8* getelementptr inbounds ([21 x i8], [21 x i8]* @.str271, i32 0, i32 0), <8 x i16> %val4723, i32 0) nounwind
+ store <2 x i64> %0, ptr undef, align 16
+ %val4723 = load <8 x i16>, ptr undef ; <<8 x i16>> [#uses=1]
+ call void @PrintShortX(ptr @.str271, <8 x i16> %val4723, i32 0) nounwind
ret i32 undef
}
-declare void @PrintShortX(i8*, <8 x i16>, i32) nounwind
+declare void @PrintShortX(ptr, <8 x i16>, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll b/llvm/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll
index a876d998e7502..31b255eb58118 100644
--- a/llvm/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll
+++ b/llvm/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll
@@ -3,92 +3,91 @@
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
target triple = "thumbv7-apple-darwin10.0.0"
-%0 = type { i8*, i8* }
+%0 = type { ptr, ptr }
%struct.A = type { i32 }
- at d = internal global i32 0, align 4 ; <i32*> [#uses=6]
- at _ZTVN10__cxxabiv117__class_type_infoE = external global i8* ; <i8**> [#uses=1]
- at _ZTS1A = internal constant [3 x i8] c"1A\00" ; <[3 x i8]*> [#uses=1]
- at _ZTI1A = internal constant %0 { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i32 2) to i8*), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @_ZTS1A, i32 0, i32 0) } ; <%0*> [#uses=1]
- at .str2 = private constant [18 x i8] c"c == %d, d == %d\0A\00" ; <[18 x i8]*> [#uses=1]
- at .str3 = private constant [16 x i8] c"A(const A&) %d\0A\00" ; <[16 x i8]*> [#uses=1]
- at .str4 = private constant [9 x i8] c"~A() %d\0A\00" ; <[9 x i8]*> [#uses=1]
- at .str5 = private constant [8 x i8] c"A() %d\0A\00" ; <[8 x i8]*> [#uses=1]
- at str = internal constant [14 x i8] c"Throwing 1...\00" ; <[14 x i8]*> [#uses=1]
- at str1 = internal constant [8 x i8] c"Caught.\00" ; <[8 x i8]*> [#uses=1]
+ at d = internal global i32 0, align 4 ; <ptr> [#uses=6]
+ at _ZTVN10__cxxabiv117__class_type_infoE = external global ptr ; <ptr> [#uses=1]
+ at _ZTS1A = internal constant [3 x i8] c"1A\00" ; <ptr> [#uses=1]
+ at _ZTI1A = internal constant %0 { ptr getelementptr inbounds (ptr, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i32 2), ptr @_ZTS1A } ; <ptr> [#uses=1]
+ at .str2 = private constant [18 x i8] c"c == %d, d == %d\0A\00" ; <ptr> [#uses=1]
+ at .str3 = private constant [16 x i8] c"A(const A&) %d\0A\00" ; <ptr> [#uses=1]
+ at .str4 = private constant [9 x i8] c"~A() %d\0A\00" ; <ptr> [#uses=1]
+ at .str5 = private constant [8 x i8] c"A() %d\0A\00" ; <ptr> [#uses=1]
+ at str = internal constant [14 x i8] c"Throwing 1...\00" ; <ptr> [#uses=1]
+ at str1 = internal constant [8 x i8] c"Caught.\00" ; <ptr> [#uses=1]
-declare i32 @printf(i8* nocapture, ...) nounwind
+declare i32 @printf(ptr nocapture, ...) nounwind
-declare i8* @__cxa_allocate_exception(i32)
+declare ptr @__cxa_allocate_exception(i32)
declare i32 @__gxx_personality_sj0(...)
-declare i32 @llvm.eh.typeid.for(i8*) nounwind
+declare i32 @llvm.eh.typeid.for(ptr) nounwind
-declare void @_Unwind_SjLj_Resume(i8*)
+declare void @_Unwind_SjLj_Resume(ptr)
-define internal void @_ZN1AD1Ev(%struct.A* nocapture %this) nounwind ssp align 2 {
+define internal void @_ZN1AD1Ev(ptr nocapture %this) nounwind ssp align 2 {
entry:
- %tmp.i = getelementptr inbounds %struct.A, %struct.A* %this, i32 0, i32 0 ; <i32*> [#uses=1]
- %tmp2.i = load i32, i32* %tmp.i ; <i32> [#uses=1]
- %call.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str4, i32 0, i32 0), i32 %tmp2.i) nounwind ; <i32> [#uses=0]
- %tmp3.i = load i32, i32* @d ; <i32> [#uses=1]
+ %tmp.i = getelementptr inbounds %struct.A, ptr %this, i32 0, i32 0 ; <ptr> [#uses=1]
+ %tmp2.i = load i32, ptr %tmp.i ; <i32> [#uses=1]
+ %call.i = tail call i32 (ptr, ...) @printf(ptr @.str4, i32 %tmp2.i) nounwind ; <i32> [#uses=0]
+ %tmp3.i = load i32, ptr @d ; <i32> [#uses=1]
%inc.i = add nsw i32 %tmp3.i, 1 ; <i32> [#uses=1]
- store i32 %inc.i, i32* @d
+ store i32 %inc.i, ptr @d
ret void
}
-declare void @__cxa_throw(i8*, i8*, i8*)
+declare void @__cxa_throw(ptr, ptr, ptr)
-define i32 @main() ssp personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
+define i32 @main() ssp personality ptr @__gxx_personality_sj0 {
entry:
- %puts.i = tail call i32 @puts(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @str, i32 0, i32 0)) ; <i32> [#uses=0]
- %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind ; <i8*> [#uses=2]
- %tmp2.i.i.i = bitcast i8* %exception.i to i32* ; <i32*> [#uses=1]
- store i32 1, i32* %tmp2.i.i.i
- %call.i.i.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str5, i32 0, i32 0), i32 1) nounwind ; <i32> [#uses=0]
- invoke void @__cxa_throw(i8* %exception.i, i8* bitcast (%0* @_ZTI1A to i8*), i8* bitcast (void (%struct.A*)* @_ZN1AD1Ev to i8*)) noreturn
+ %puts.i = tail call i32 @puts(ptr @str) ; <i32> [#uses=0]
+ %exception.i = tail call ptr @__cxa_allocate_exception(i32 4) nounwind ; <ptr> [#uses=2]
+ store i32 1, ptr %exception.i
+ %call.i.i.i = tail call i32 (ptr, ...) @printf(ptr @.str5, i32 1) nounwind ; <i32> [#uses=0]
+ invoke void @__cxa_throw(ptr %exception.i, ptr @_ZTI1A, ptr @_ZN1AD1Ev) noreturn
to label %.noexc unwind label %lpad
.noexc: ; preds = %entry
unreachable
try.cont: ; preds = %lpad
- %0 = tail call i8* @__cxa_get_exception_ptr(i8* %exn) nounwind ; <i8*> [#uses=0]
- %call.i.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str3, i32 0, i32 0), i32 2) nounwind ; <i32> [#uses=0]
- %1 = tail call i8* @__cxa_begin_catch(i8* %exn) nounwind ; <i8*> [#uses=0]
- %puts = tail call i32 @puts(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @str1, i32 0, i32 0)) ; <i32> [#uses=0]
- %call.i.i3 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str4, i32 0, i32 0), i32 2) nounwind ; <i32> [#uses=0]
- %tmp3.i.i = load i32, i32* @d ; <i32> [#uses=1]
+ %0 = tail call ptr @__cxa_get_exception_ptr(ptr %exn) nounwind ; <ptr> [#uses=0]
+ %call.i.i = tail call i32 (ptr, ...) @printf(ptr @.str3, i32 2) nounwind ; <i32> [#uses=0]
+ %1 = tail call ptr @__cxa_begin_catch(ptr %exn) nounwind ; <ptr> [#uses=0]
+ %puts = tail call i32 @puts(ptr @str1) ; <i32> [#uses=0]
+ %call.i.i3 = tail call i32 (ptr, ...) @printf(ptr @.str4, i32 2) nounwind ; <i32> [#uses=0]
+ %tmp3.i.i = load i32, ptr @d ; <i32> [#uses=1]
%inc.i.i4 = add nsw i32 %tmp3.i.i, 1 ; <i32> [#uses=1]
- store i32 %inc.i.i4, i32* @d
+ store i32 %inc.i.i4, ptr @d
tail call void @__cxa_end_catch()
- %tmp13 = load i32, i32* @d ; <i32> [#uses=1]
- %call14 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str2, i32 0, i32 0), i32 2, i32 %tmp13) ; <i32> [#uses=0]
- %tmp16 = load i32, i32* @d ; <i32> [#uses=1]
+ %tmp13 = load i32, ptr @d ; <i32> [#uses=1]
+ %call14 = tail call i32 (ptr, ...) @printf(ptr @.str2, i32 2, i32 %tmp13) ; <i32> [#uses=0]
+ %tmp16 = load i32, ptr @d ; <i32> [#uses=1]
%cmp = icmp ne i32 %tmp16, 2 ; <i1> [#uses=1]
%conv = zext i1 %cmp to i32 ; <i32> [#uses=1]
ret i32 %conv
lpad: ; preds = %entry
- %exn.ptr = landingpad { i8*, i32 }
- catch i8* bitcast (%0* @_ZTI1A to i8*)
- catch i8* null
- %exn = extractvalue { i8*, i32 } %exn.ptr, 0
- %eh.selector = extractvalue { i8*, i32 } %exn.ptr, 1
- %2 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (%0* @_ZTI1A to i8*)) nounwind ; <i32> [#uses=1]
+ %exn.ptr = landingpad { ptr, i32 }
+ catch ptr @_ZTI1A
+ catch ptr null
+ %exn = extractvalue { ptr, i32 } %exn.ptr, 0
+ %eh.selector = extractvalue { ptr, i32 } %exn.ptr, 1
+ %2 = tail call i32 @llvm.eh.typeid.for(ptr @_ZTI1A) nounwind ; <i32> [#uses=1]
%3 = icmp eq i32 %eh.selector, %2 ; <i1> [#uses=1]
br i1 %3, label %try.cont, label %eh.resume
eh.resume: ; preds = %lpad
- tail call void @_Unwind_SjLj_Resume(i8* %exn) noreturn
+ tail call void @_Unwind_SjLj_Resume(ptr %exn) noreturn
unreachable
}
-declare i8* @__cxa_get_exception_ptr(i8*)
+declare ptr @__cxa_get_exception_ptr(ptr)
-declare i8* @__cxa_begin_catch(i8*)
+declare ptr @__cxa_begin_catch(ptr)
declare void @__cxa_end_catch()
-declare i32 @puts(i8* nocapture) nounwind
+declare i32 @puts(ptr nocapture) nounwind
diff --git a/llvm/test/CodeGen/ARM/2010-08-04-EHCrash.ll b/llvm/test/CodeGen/ARM/2010-08-04-EHCrash.ll
index 69482cc8b35bc..3f5f581229d6f 100644
--- a/llvm/test/CodeGen/ARM/2010-08-04-EHCrash.ll
+++ b/llvm/test/CodeGen/ARM/2010-08-04-EHCrash.ll
@@ -1,29 +1,29 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10
; <rdar://problem/8264008>
-define linkonce_odr arm_apcscc void @func1() personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
+define linkonce_odr arm_apcscc void @func1() personality ptr @__gxx_personality_sj0 {
entry:
- %save_filt.936 = alloca i32 ; <i32*> [#uses=2]
- %save_eptr.935 = alloca i8* ; <i8**> [#uses=2]
- %eh_exception = alloca i8* ; <i8**> [#uses=5]
- %eh_selector = alloca i32 ; <i32*> [#uses=3]
+ %save_filt.936 = alloca i32 ; <ptr> [#uses=2]
+ %save_eptr.935 = alloca ptr ; <ptr> [#uses=2]
+ %eh_exception = alloca ptr ; <ptr> [#uses=5]
+ %eh_selector = alloca i32 ; <ptr> [#uses=3]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
call arm_apcscc void @func2()
br label %return
bb: ; No predecessors!
- %eh_select = load i32, i32* %eh_selector ; <i32> [#uses=1]
- store i32 %eh_select, i32* %save_filt.936, align 4
- %eh_value = load i8*, i8** %eh_exception ; <i8*> [#uses=1]
- store i8* %eh_value, i8** %save_eptr.935, align 4
+ %eh_select = load i32, ptr %eh_selector ; <i32> [#uses=1]
+ store i32 %eh_select, ptr %save_filt.936, align 4
+ %eh_value = load ptr, ptr %eh_exception ; <ptr> [#uses=1]
+ store ptr %eh_value, ptr %save_eptr.935, align 4
invoke arm_apcscc void @func3()
to label %invcont unwind label %lpad
invcont: ; preds = %bb
- %tmp6 = load i8*, i8** %save_eptr.935, align 4 ; <i8*> [#uses=1]
- store i8* %tmp6, i8** %eh_exception, align 4
- %tmp7 = load i32, i32* %save_filt.936, align 4 ; <i32> [#uses=1]
- store i32 %tmp7, i32* %eh_selector, align 4
+ %tmp6 = load ptr, ptr %save_eptr.935, align 4 ; <ptr> [#uses=1]
+ store ptr %tmp6, ptr %eh_exception, align 4
+ %tmp7 = load i32, ptr %save_filt.936, align 4 ; <i32> [#uses=1]
+ store i32 %tmp7, ptr %eh_selector, align 4
br label %Unwind
bb12: ; preds = %ppad
@@ -34,21 +34,21 @@ return: ; preds = %entry
ret void
lpad: ; preds = %bb
- %eh_ptr = landingpad { i8*, i32 }
+ %eh_ptr = landingpad { ptr, i32 }
cleanup
- %exn = extractvalue { i8*, i32 } %eh_ptr, 0
- store i8* %exn, i8** %eh_exception
- %eh_ptr13 = load i8*, i8** %eh_exception ; <i8*> [#uses=1]
- %eh_select14 = extractvalue { i8*, i32 } %eh_ptr, 1
- store i32 %eh_select14, i32* %eh_selector
+ %exn = extractvalue { ptr, i32 } %eh_ptr, 0
+ store ptr %exn, ptr %eh_exception
+ %eh_ptr13 = load ptr, ptr %eh_exception ; <ptr> [#uses=1]
+ %eh_select14 = extractvalue { ptr, i32 } %eh_ptr, 1
+ store i32 %eh_select14, ptr %eh_selector
br label %ppad
ppad:
br label %bb12
Unwind:
- %eh_ptr15 = load i8*, i8** %eh_exception
- call arm_apcscc void @_Unwind_SjLj_Resume(i8* %eh_ptr15)
+ %eh_ptr15 = load ptr, ptr %eh_exception
+ call arm_apcscc void @_Unwind_SjLj_Resume(ptr %eh_ptr15)
unreachable
}
@@ -56,7 +56,7 @@ declare arm_apcscc void @func2()
declare arm_apcscc void @_ZSt9terminatev() noreturn nounwind
-declare arm_apcscc void @_Unwind_SjLj_Resume(i8*)
+declare arm_apcscc void @_Unwind_SjLj_Resume(ptr)
declare arm_apcscc void @func3()
diff --git a/llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll
index 662a78c4dfa65..fafe022c5f298 100644
--- a/llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll
+++ b/llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll
@@ -3,28 +3,28 @@
; CHECK: @ DW_OP_breg
-%struct.SVal = type { i8*, i32 }
+%struct.SVal = type { ptr, i32 }
-define i32 @_Z3fooi4SVal(i32 %i, %struct.SVal* noalias %location) #0 !dbg !4 {
+define i32 @_Z3fooi4SVal(i32 %i, ptr noalias %location) #0 !dbg !4 {
entry:
%"alloca point" = bitcast i32 0 to i32
br label %realentry
realentry:
call void @llvm.dbg.value(metadata i32 %i, metadata !21, metadata !DIExpression()), !dbg !22
- call void @llvm.dbg.value(metadata %struct.SVal* %location, metadata !23, metadata !DIExpression()), !dbg !22
+ call void @llvm.dbg.value(metadata ptr %location, metadata !23, metadata !DIExpression()), !dbg !22
%tmp = icmp ne i32 %i, 0, !dbg !25
br i1 %tmp, label %bb, label %bb1, !dbg !25
bb: ; preds = %entry
- %tmp1 = getelementptr inbounds %struct.SVal, %struct.SVal* %location, i32 0, i32 1, !dbg !27
- %tmp2 = load i32, i32* %tmp1, align 8, !dbg !27
+ %tmp1 = getelementptr inbounds %struct.SVal, ptr %location, i32 0, i32 1, !dbg !27
+ %tmp2 = load i32, ptr %tmp1, align 8, !dbg !27
%tmp3 = add i32 %tmp2, %i, !dbg !27
br label %bb2, !dbg !27
bb1: ; preds = %entry
- %tmp4 = getelementptr inbounds %struct.SVal, %struct.SVal* %location, i32 0, i32 1, !dbg !28
- %tmp5 = load i32, i32* %tmp4, align 8, !dbg !28
+ %tmp4 = getelementptr inbounds %struct.SVal, ptr %location, i32 0, i32 1, !dbg !28
+ %tmp5 = load i32, ptr %tmp4, align 8, !dbg !28
%tmp6 = sub i32 %tmp5, 1, !dbg !28
br label %bb2, !dbg !28
diff --git a/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll b/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll
index d2820918626ad..9354ff39ec2c9 100644
--- a/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll
+++ b/llvm/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll
@@ -1,8 +1,8 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10
-declare noalias i8* @malloc(i32) nounwind
+declare noalias ptr @malloc(i32) nounwind
-define internal void @gl_DrawPixels(i32 %width, i32 %height, i32 %format, i32 %type, i8* %pixels) nounwind {
+define internal void @gl_DrawPixels(i32 %width, i32 %height, i32 %format, i32 %type, ptr %pixels) nounwind {
entry:
br i1 undef, label %bb3.i, label %bb3
@@ -49,7 +49,7 @@ bb4.i18: ; preds = %bb3.i17
%not..i = icmp ne i32 %1, 0
%2 = zext i1 %not..i to i32
%storemerge2.i = add i32 0, %2
- %3 = call noalias i8* @malloc(i32 %storemerge2.i) nounwind
+ %3 = call noalias ptr @malloc(i32 %storemerge2.i) nounwind
br i1 undef, label %bb3.i9, label %bb9.i
bb9.i: ; preds = %bb4.i18
diff --git a/llvm/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll b/llvm/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll
index e7e0580179c47..f5762cb1566af 100644
--- a/llvm/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll
+++ b/llvm/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll
@@ -10,7 +10,7 @@
define i32 @test(i32 %x) {
entry:
- %0 = tail call signext i16 undef(i32* undef)
+ %0 = tail call signext i16 undef(ptr undef)
switch i32 %x, label %bb3 [
i32 0, label %bb4
i32 1, label %bb1
diff --git a/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll b/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll
index 09428ce9c3396..209bcec1843bb 100644
--- a/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll
+++ b/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll
@@ -13,7 +13,7 @@ target triple = "armv7-eabi"
%0 = type { i32, i32 }
-define void @foo(i32* %in) nounwind {
+define void @foo(ptr %in) nounwind {
entry:
br label %bb.i
@@ -34,34 +34,34 @@ bb28.i: ; preds = %bb28.i, %bb27.i
presymmetry.exit: ; preds = %bb28.i
%tmp175387 = or i32 undef, 12
- %scevgep101.i = getelementptr i32, i32* %in, i32 undef
+ %scevgep101.i = getelementptr i32, ptr %in, i32 undef
%tmp189401 = or i32 undef, 7
- %scevgep97.i = getelementptr i32, i32* %in, i32 undef
+ %scevgep97.i = getelementptr i32, ptr %in, i32 undef
%tmp198410 = or i32 undef, 1
- %scevgep.i48 = getelementptr i32, i32* %in, i32 undef
- %0 = load i32, i32* %scevgep.i48, align 4
+ %scevgep.i48 = getelementptr i32, ptr %in, i32 undef
+ %0 = load i32, ptr %scevgep.i48, align 4
%1 = add nsw i32 %0, 0
- store i32 %1, i32* undef, align 4
+ store i32 %1, ptr undef, align 4
%asmtmp.i.i33.i.i.i = tail call %0 asm "smull\09$0, $1, $2, $3", "=&r,=&r,%r,r,~{cc}"(i32 undef, i32 1518500250) nounwind
%asmresult1.i.i34.i.i.i = extractvalue %0 %asmtmp.i.i33.i.i.i, 1
%2 = shl i32 %asmresult1.i.i34.i.i.i, 1
- %3 = load i32, i32* null, align 4
- %4 = load i32, i32* undef, align 4
+ %3 = load i32, ptr null, align 4
+ %4 = load i32, ptr undef, align 4
%5 = sub nsw i32 %3, %4
- %6 = load i32, i32* undef, align 4
- %7 = load i32, i32* null, align 4
+ %6 = load i32, ptr undef, align 4
+ %7 = load i32, ptr null, align 4
%8 = sub nsw i32 %6, %7
- %9 = load i32, i32* %scevgep97.i, align 4
- %10 = load i32, i32* undef, align 4
+ %9 = load i32, ptr %scevgep97.i, align 4
+ %10 = load i32, ptr undef, align 4
%11 = sub nsw i32 %9, %10
- %12 = load i32, i32* null, align 4
- %13 = load i32, i32* %scevgep101.i, align 4
+ %12 = load i32, ptr null, align 4
+ %13 = load i32, ptr %scevgep101.i, align 4
%14 = sub nsw i32 %12, %13
- %15 = load i32, i32* %scevgep.i48, align 4
- %16 = load i32, i32* null, align 4
+ %15 = load i32, ptr %scevgep.i48, align 4
+ %16 = load i32, ptr null, align 4
%17 = add nsw i32 %16, %15
%18 = sub nsw i32 %15, %16
- %19 = load i32, i32* undef, align 4
+ %19 = load i32, ptr undef, align 4
%20 = add nsw i32 %19, %2
%21 = sub nsw i32 %19, %2
%22 = add nsw i32 %14, %5
@@ -69,16 +69,16 @@ presymmetry.exit: ; preds = %bb28.i
%24 = add nsw i32 %11, %8
%25 = sub nsw i32 %8, %11
%26 = add nsw i32 %21, %23
- store i32 %26, i32* %scevgep.i48, align 4
+ store i32 %26, ptr %scevgep.i48, align 4
%27 = sub nsw i32 %25, %18
- store i32 %27, i32* null, align 4
+ store i32 %27, ptr null, align 4
%28 = sub nsw i32 %23, %21
- store i32 %28, i32* undef, align 4
+ store i32 %28, ptr undef, align 4
%29 = add nsw i32 %18, %25
- store i32 %29, i32* undef, align 4
+ store i32 %29, ptr undef, align 4
%30 = add nsw i32 %17, %22
- store i32 %30, i32* %scevgep101.i, align 4
+ store i32 %30, ptr %scevgep101.i, align 4
%31 = add nsw i32 %20, %24
- store i32 %31, i32* null, align 4
+ store i32 %31, ptr null, align 4
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll b/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
index 4b89ea32536d5..ff1e769600d38 100644
--- a/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
+++ b/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
; rdar://8690640
-define i32* @t(i32* %x) nounwind "frame-pointer"="all" {
+define ptr @t(ptr %x) nounwind "frame-pointer"="all" {
entry:
; CHECK-LABEL: t:
; CHECK: push
@@ -12,10 +12,10 @@ entry:
; CHECK: bl _foo
; CHECK: pop {r7, pc}
- %0 = tail call i32* @foo(i32* %x) nounwind
- %1 = tail call i32* @foo(i32* %0) nounwind
- %2 = tail call i32* @foo(i32* %1) nounwind
- ret i32* %2
+ %0 = tail call ptr @foo(ptr %x) nounwind
+ %1 = tail call ptr @foo(ptr %0) nounwind
+ %2 = tail call ptr @foo(ptr %1) nounwind
+ ret ptr %2
}
-declare i32* @foo(i32*)
+declare ptr @foo(ptr)
diff --git a/llvm/test/CodeGen/ARM/2010-12-08-tpsoft.ll b/llvm/test/CodeGen/ARM/2010-12-08-tpsoft.ll
index 2df9fb76b9747..652b53b738063 100644
--- a/llvm/test/CodeGen/ARM/2010-12-08-tpsoft.ll
+++ b/llvm/test/CodeGen/ARM/2010-12-08-tpsoft.ll
@@ -12,14 +12,14 @@
define arm_aapcs_vfpcc i32 @main() nounwind {
entry:
- %0 = load i32, i32* @i, align 4
+ %0 = load i32, ptr @i, align 4
switch i32 %0, label %bb2 [
i32 12, label %bb
i32 13, label %bb1
]
bb: ; preds = %entry
- %1 = tail call arm_aapcs_vfpcc i32 @foo(i8* @a) nounwind
+ %1 = tail call arm_aapcs_vfpcc i32 @foo(ptr @a) nounwind
ret i32 %1
; ELFASM: bl __aeabi_read_tp
@@ -34,13 +34,13 @@ bb: ; preds = %entry
bb1: ; preds = %entry
- %2 = tail call arm_aapcs_vfpcc i32 @bar(i32* bitcast ([10 x i8]* @b to i32*)) nounwind
+ %2 = tail call arm_aapcs_vfpcc i32 @bar(ptr @b) nounwind
ret i32 %2
bb2: ; preds = %entry
ret i32 -1
}
-declare arm_aapcs_vfpcc i32 @foo(i8*)
+declare arm_aapcs_vfpcc i32 @foo(ptr)
-declare arm_aapcs_vfpcc i32 @bar(i32*)
+declare arm_aapcs_vfpcc i32 @bar(ptr)
diff --git a/llvm/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll b/llvm/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll
index ccebe2a003cdf..34122e62cc070 100644
--- a/llvm/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll
+++ b/llvm/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll
@@ -26,9 +26,9 @@
; OBJ-NEXT: Section: .bss
define i32 @main(i32 %argc) nounwind {
- %1 = load i32, i32* @sum, align 4
- %2 = getelementptr [80 x i8], [80 x i8]* @array00, i32 0, i32 %argc
- %3 = load i8, i8* %2
+ %1 = load i32, ptr @sum, align 4
+ %2 = getelementptr [80 x i8], ptr @array00, i32 0, i32 %argc
+ %3 = load i8, ptr %2
%4 = zext i8 %3 to i32
%5 = add i32 %1, %4
ret i32 %5
diff --git a/llvm/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll b/llvm/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll
index 783c82eb88b7d..ca2a7aa54ca84 100644
--- a/llvm/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll
+++ b/llvm/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll
@@ -9,7 +9,6 @@ entry:
br label %bb
bb:
- %p.2 = getelementptr [8096 x i8], [8096 x i8]* %buf, i32 0, i32 0
- store i8 undef, i8* %p.2, align 1
+ store i8 undef, ptr %buf, align 1
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/llvm/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll
index c65c64dfc6791..57c5316796be1 100644
--- a/llvm/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll
+++ b/llvm/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll
@@ -22,9 +22,9 @@ target triple = "thumbv7-apple-darwin10"
define zeroext i8 @get1(i8 zeroext %a) #0 !dbg !16 {
entry:
tail call void @llvm.dbg.value(metadata i8 %a, metadata !20, metadata !23), !dbg !24
- %0 = load i8, i8* @x1, align 4, !dbg !24
+ %0 = load i8, ptr @x1, align 4, !dbg !24
tail call void @llvm.dbg.value(metadata i8 %0, metadata !21, metadata !23), !dbg !24
- store i8 %a, i8* @x1, align 4, !dbg !24
+ store i8 %a, ptr @x1, align 4, !dbg !24
ret i8 %0, !dbg !25
}
@@ -35,9 +35,9 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) #1
define zeroext i8 @get2(i8 zeroext %a) #0 !dbg !26 {
entry:
tail call void @llvm.dbg.value(metadata i8 %a, metadata !28, metadata !23), !dbg !31
- %0 = load i8, i8* @x2, align 4, !dbg !31
+ %0 = load i8, ptr @x2, align 4, !dbg !31
tail call void @llvm.dbg.value(metadata i8 %0, metadata !29, metadata !23), !dbg !31
- store i8 %a, i8* @x2, align 4, !dbg !31
+ store i8 %a, ptr @x2, align 4, !dbg !31
ret i8 %0, !dbg !32
}
@@ -46,9 +46,9 @@ entry:
define zeroext i8 @get3(i8 zeroext %a) #0 !dbg !33 {
entry:
tail call void @llvm.dbg.value(metadata i8 %a, metadata !35, metadata !23), !dbg !38
- %0 = load i8, i8* @x3, align 4, !dbg !38
+ %0 = load i8, ptr @x3, align 4, !dbg !38
tail call void @llvm.dbg.value(metadata i8 %0, metadata !36, metadata !23), !dbg !38
- store i8 %a, i8* @x3, align 4, !dbg !38
+ store i8 %a, ptr @x3, align 4, !dbg !38
ret i8 %0, !dbg !39
}
@@ -57,9 +57,9 @@ entry:
define zeroext i8 @get4(i8 zeroext %a) #0 !dbg !40 {
entry:
tail call void @llvm.dbg.value(metadata i8 %a, metadata !42, metadata !23), !dbg !45
- %0 = load i8, i8* @x4, align 4, !dbg !45
+ %0 = load i8, ptr @x4, align 4, !dbg !45
tail call void @llvm.dbg.value(metadata i8 %0, metadata !43, metadata !23), !dbg !45
- store i8 %a, i8* @x4, align 4, !dbg !45
+ store i8 %a, ptr @x4, align 4, !dbg !45
ret i8 %0, !dbg !46
}
@@ -68,9 +68,9 @@ entry:
define zeroext i8 @get5(i8 zeroext %a) #0 !dbg !47 {
entry:
tail call void @llvm.dbg.value(metadata i8 %a, metadata !49, metadata !23), !dbg !52
- %0 = load i8, i8* @x5, align 4, !dbg !52
+ %0 = load i8, ptr @x5, align 4, !dbg !52
tail call void @llvm.dbg.value(metadata i8 %0, metadata !50, metadata !23), !dbg !52
- store i8 %a, i8* @x5, align 4, !dbg !52
+ store i8 %a, ptr @x5, align 4, !dbg !52
ret i8 %0, !dbg !53
}
diff --git a/llvm/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll b/llvm/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll
index 730f3050d1159..793a60f36e229 100644
--- a/llvm/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll
+++ b/llvm/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll
@@ -7,7 +7,7 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32"
target triple = "armv6-apple-darwin10"
-define void @ptoa(i1 %tst, i8* %p8, i8 %val8) nounwind {
+define void @ptoa(i1 %tst, ptr %p8, i8 %val8) nounwind {
entry:
br i1 false, label %bb3, label %bb
@@ -15,108 +15,107 @@ bb: ; preds = %entry
br label %bb3
bb3: ; preds = %bb, %entry
- %0 = call noalias i8* @malloc() nounwind
+ %0 = call noalias ptr @malloc() nounwind
br i1 %tst, label %bb46, label %bb8
bb8: ; preds = %bb3
- %1 = getelementptr inbounds i8, i8* %0, i32 0
- store volatile i8 0, i8* %1, align 1
- %2 = call i32 @ptou() nounwind
+ store volatile i8 0, ptr %0, align 1
+ %1 = call i32 @ptou() nounwind
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
- %3 = udiv i32 %2, 10
- %4 = urem i32 %3, 10
- %5 = icmp ult i32 %4, 10
- %6 = trunc i32 %4 to i8
- %7 = or i8 %6, 48
- %8 = add i8 %6, 87
- %iftmp.5.0.1 = select i1 %5, i8 %7, i8 %8
- store volatile i8 %iftmp.5.0.1, i8* %p8, align 1
+ %2 = udiv i32 %1, 10
+ %3 = urem i32 %2, 10
+ %4 = icmp ult i32 %3, 10
+ %5 = trunc i32 %3 to i8
+ %6 = or i8 %5, 48
+ %7 = add i8 %5, 87
+ %iftmp.5.0.1 = select i1 %4, i8 %6, i8 %7
+ store volatile i8 %iftmp.5.0.1, ptr %p8, align 1
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
- %9 = udiv i32 %2, 100
- %10 = urem i32 %9, 10
- %11 = icmp ult i32 %10, 10
- %12 = trunc i32 %10 to i8
- %13 = or i8 %12, 48
- %14 = add i8 %12, 87
- %iftmp.5.0.2 = select i1 %11, i8 %13, i8 %14
- store volatile i8 %iftmp.5.0.2, i8* %p8, align 1
+ %8 = udiv i32 %1, 100
+ %9 = urem i32 %8, 10
+ %10 = icmp ult i32 %9, 10
+ %11 = trunc i32 %9 to i8
+ %12 = or i8 %11, 48
+ %13 = add i8 %11, 87
+ %iftmp.5.0.2 = select i1 %10, i8 %12, i8 %13
+ store volatile i8 %iftmp.5.0.2, ptr %p8, align 1
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
- %15 = udiv i32 %2, 10000
- %16 = urem i32 %15, 10
- %17 = icmp ult i32 %16, 10
- %18 = trunc i32 %16 to i8
- %19 = or i8 %18, 48
- %20 = add i8 %18, 87
- %iftmp.5.0.4 = select i1 %17, i8 %19, i8 %20
- store volatile i8 %iftmp.5.0.4, i8* null, align 1
+ %14 = udiv i32 %1, 10000
+ %15 = urem i32 %14, 10
+ %16 = icmp ult i32 %15, 10
+ %17 = trunc i32 %15 to i8
+ %18 = or i8 %17, 48
+ %19 = add i8 %17, 87
+ %iftmp.5.0.4 = select i1 %16, i8 %18, i8 %19
+ store volatile i8 %iftmp.5.0.4, ptr null, align 1
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
- %21 = udiv i32 %2, 100000
- %22 = urem i32 %21, 10
- %23 = icmp ult i32 %22, 10
- %iftmp.5.0.5 = select i1 %23, i8 0, i8 %val8
- store volatile i8 %iftmp.5.0.5, i8* %p8, align 1
+ %20 = udiv i32 %1, 100000
+ %21 = urem i32 %20, 10
+ %22 = icmp ult i32 %21, 10
+ %iftmp.5.0.5 = select i1 %22, i8 0, i8 %val8
+ store volatile i8 %iftmp.5.0.5, ptr %p8, align 1
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
- %24 = udiv i32 %2, 1000000
- %25 = urem i32 %24, 10
- %26 = icmp ult i32 %25, 10
- %27 = trunc i32 %25 to i8
- %28 = or i8 %27, 48
- %29 = add i8 %27, 87
- %iftmp.5.0.6 = select i1 %26, i8 %28, i8 %29
- store volatile i8 %iftmp.5.0.6, i8* %p8, align 1
+ %23 = udiv i32 %1, 1000000
+ %24 = urem i32 %23, 10
+ %25 = icmp ult i32 %24, 10
+ %26 = trunc i32 %24 to i8
+ %27 = or i8 %26, 48
+ %28 = add i8 %26, 87
+ %iftmp.5.0.6 = select i1 %25, i8 %27, i8 %28
+ store volatile i8 %iftmp.5.0.6, ptr %p8, align 1
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
- %30 = udiv i32 %2, 10000000
- %31 = urem i32 %30, 10
- %32 = icmp ult i32 %31, 10
- %33 = trunc i32 %31 to i8
- %34 = or i8 %33, 48
- %35 = add i8 %33, 87
- %iftmp.5.0.7 = select i1 %32, i8 %34, i8 %35
- store volatile i8 %iftmp.5.0.7, i8* %p8, align 1
- %36 = udiv i32 %2, 100000000
- %37 = urem i32 %36, 10
- %38 = icmp ult i32 %37, 10
- %39 = trunc i32 %37 to i8
- %40 = or i8 %39, 48
- %41 = add i8 %39, 87
- %iftmp.5.0.8 = select i1 %38, i8 %40, i8 %41
- store volatile i8 %iftmp.5.0.8, i8* null, align 1
+ %29 = udiv i32 %1, 10000000
+ %30 = urem i32 %29, 10
+ %31 = icmp ult i32 %30, 10
+ %32 = trunc i32 %30 to i8
+ %33 = or i8 %32, 48
+ %34 = add i8 %32, 87
+ %iftmp.5.0.7 = select i1 %31, i8 %33, i8 %34
+ store volatile i8 %iftmp.5.0.7, ptr %p8, align 1
+ %35 = udiv i32 %1, 100000000
+ %36 = urem i32 %35, 10
+ %37 = icmp ult i32 %36, 10
+ %38 = trunc i32 %36 to i8
+ %39 = or i8 %38, 48
+ %40 = add i8 %38, 87
+ %iftmp.5.0.8 = select i1 %37, i8 %39, i8 %40
+ store volatile i8 %iftmp.5.0.8, ptr null, align 1
br label %bb46
bb46: ; preds = %bb3
ret void
}
-declare noalias i8* @malloc() nounwind
+declare noalias ptr @malloc() nounwind
declare i32 @ptou()
diff --git a/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll b/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll
index e96641bf6671f..1515b06b620bd 100644
--- a/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll
+++ b/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll
@@ -8,7 +8,7 @@ target triple = "armv5e-none-linux-gnueabi"
define hidden fastcc void @storeAtts() nounwind {
entry:
- %.SV116 = alloca i8**
+ %.SV116 = alloca ptr
br i1 undef, label %meshBB520, label %meshBB464
bb15: ; preds = %meshBB424
@@ -39,22 +39,22 @@ bb134: ; preds = %bb131
unreachable
bb135: ; preds = %meshBB396
- %uriHash.1.phi.load = load i32, i32* undef
- %.load120 = load i8**, i8*** %.SV116
- %.phi24 = load i8, i8* null
- %.phi26 = load i8*, i8** null
- store i8 %.phi24, i8* %.phi26, align 1
- %0 = getelementptr inbounds i8, i8* %.phi26, i32 1
- store i8* %0, i8** %.load120, align 4
+ %uriHash.1.phi.load = load i32, ptr undef
+ %.load120 = load ptr, ptr %.SV116
+ %.phi24 = load i8, ptr null
+ %.phi26 = load ptr, ptr null
+ store i8 %.phi24, ptr %.phi26, align 1
+ %0 = getelementptr inbounds i8, ptr %.phi26, i32 1
+ store ptr %0, ptr %.load120, align 4
; CHECK: mul [[REGISTER:lr|r[0-9]+]],
; CHECK-NOT: [[REGISTER]],
; CHECK: {{(lr|r[0-9]+)$}}
%1 = mul i32 %uriHash.1.phi.load, 1000003
%2 = xor i32 0, %1
- store i32 %2, i32* null
- %3 = load i8, i8* null, align 1
+ store i32 %2, ptr null
+ %3 = load i8, ptr null, align 1
%4 = icmp eq i8 %3, 0
- store i8* %0, i8** undef
+ store ptr %0, ptr undef
br i1 %4, label %meshBB472, label %bb131
bb212: ; preds = %meshBB540
diff --git a/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll b/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll
index b33b333b299d0..2ff19c7975f12 100644
--- a/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll
+++ b/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll
@@ -2,12 +2,12 @@
; rdar://9117613
-%struct.mo = type { i32, %struct.mo_pops* }
-%struct.mo_pops = type { void (%struct.mo*)*, void (%struct.mo*)*, i32 (%struct.mo*, i32*, i32)*, i32 (%struct.mo*)*, i32 (%struct.mo*, i64, i32, i32, i32*, i64, i32)*, i32 (%struct.mo*, i64, i32, i64*, i32*, i32, i32, i32)*, i32 (%struct.mo*, i64, i32)*, i32 (%struct.mo*, i64, i64, i32)*, i32 (%struct.mo*, i64, i64, i32)*, i32 (%struct.mo*, i32)*, i32 (%struct.mo*)*, i32 (%struct.mo*, i32)*, i8* }
-%struct.ui = type { %struct.mo*, i32*, i32, i32*, i32*, i64, i32*, i32*, i32* }
+%struct.mo = type { i32, ptr }
+%struct.mo_pops = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }
+%struct.ui = type { ptr, ptr, i32, ptr, ptr, i64, ptr, ptr, ptr }
-define internal fastcc i32 @t(i32* %vp, i32 %withfsize, i64 %filesize) nounwind {
+define internal fastcc i32 @t(ptr %vp, i32 %withfsize, i64 %filesize) nounwind {
entry:
br i1 undef, label %bb1, label %bb
@@ -15,13 +15,12 @@ bb: ; preds = %entry
unreachable
bb1: ; preds = %entry
- %0 = call %struct.ui* @vn_pp_to_ui(i32* undef) nounwind
- call void @llvm.memset.p0i8.i32(i8* align 4 undef, i8 0, i32 40, i1 false)
- %1 = getelementptr inbounds %struct.ui, %struct.ui* %0, i32 0, i32 0
- store %struct.mo* undef, %struct.mo** %1, align 4
- %2 = getelementptr inbounds %struct.ui, %struct.ui* %0, i32 0, i32 5
- %3 = load i64, i64* %2, align 4
- %4 = call i32 @mo_create_nnm(%struct.mo* undef, i64 %3, i32** undef) nounwind
+ %0 = call ptr @vn_pp_to_ui(ptr undef) nounwind
+ call void @llvm.memset.p0.i32(ptr align 4 undef, i8 0, i32 40, i1 false)
+ store ptr undef, ptr %0, align 4
+ %1 = getelementptr inbounds %struct.ui, ptr %0, i32 0, i32 5
+ %2 = load i64, ptr %1, align 4
+ %3 = call i32 @mo_create_nnm(ptr undef, i64 %2, ptr undef) nounwind
br i1 undef, label %bb3, label %bb2
bb2: ; preds = %bb1
@@ -31,17 +30,17 @@ bb3: ; preds = %bb1
br i1 undef, label %bb4, label %bb6
bb4: ; preds = %bb3
- %5 = call i32 @vn_size(i32* %vp, i64* %2, i32* undef) nounwind
+ %4 = call i32 @vn_size(ptr %vp, ptr %1, ptr undef) nounwind
unreachable
bb6: ; preds = %bb3
ret i32 0
}
-declare %struct.ui* @vn_pp_to_ui(i32*)
+declare ptr @vn_pp_to_ui(ptr)
-declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) nounwind
+declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) nounwind
-declare i32 @mo_create_nnm(%struct.mo*, i64, i32**)
+declare i32 @mo_create_nnm(ptr, i64, ptr)
-declare i32 @vn_size(i32*, i64*, i32*)
+declare i32 @vn_size(ptr, ptr, ptr)
diff --git a/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll b/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
index b526b8c3075d5..44ae16339499a 100644
--- a/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
+++ b/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
@@ -18,11 +18,11 @@ for.body.lr.ph:
for.body: ; preds = %_Z14printIsNotZeroi.exit17.for.body_crit_edge, %for.body.lr.ph
%tmp3 = phi i1 [ false, %for.body.lr.ph ], [ %phitmp27, %_Z14printIsNotZeroi.exit17.for.body_crit_edge ]
%i.022 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %_Z14printIsNotZeroi.exit17.for.body_crit_edge ]
- %x = getelementptr %struct.Outer, %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 0
- %y = getelementptr %struct.Outer, %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 1
+ %x = getelementptr %struct.Outer, ptr @oStruct, i32 0, i32 1, i32 %i.022, i32 0
+ %y = getelementptr %struct.Outer, ptr @oStruct, i32 0, i32 1, i32 %i.022, i32 1
%inc = add i32 %i.022, 1
- %tmp8 = load i32, i32* %x, align 4
- %tmp11 = load i32, i32* %y, align 4
+ %tmp8 = load i32, ptr %x, align 4
+ %tmp11 = load i32, ptr %y, align 4
%mul = mul nsw i32 %tmp11, %tmp8
%tobool.i14 = icmp eq i32 %mul, 0
br i1 %tobool.i14, label %_Z14printIsNotZeroi.exit17, label %if.then.i16
@@ -34,8 +34,8 @@ _Z14printIsNotZeroi.exit17: ; preds = %_Z14printIsNotZeroi
br label %_Z14printIsNotZeroi.exit17.for.body_crit_edge
_Z14printIsNotZeroi.exit17.for.body_crit_edge: ; preds = %_Z14printIsNotZeroi.exit17
- %b.phi.trans.insert = getelementptr %struct.Outer, %struct.Outer* @oStruct, i32 0, i32 1, i32 %inc, i32 3
- %tmp3.pre = load i8, i8* %b.phi.trans.insert, align 1
+ %b.phi.trans.insert = getelementptr %struct.Outer, ptr @oStruct, i32 0, i32 1, i32 %inc, i32 3
+ %tmp3.pre = load i8, ptr %b.phi.trans.insert, align 1
%phitmp27 = icmp eq i8 %val8, 0
br label %for.body
diff --git a/llvm/test/CodeGen/ARM/2011-04-07-schediv.ll b/llvm/test/CodeGen/ARM/2011-04-07-schediv.ll
index 7f603157c5d3f..2dde043207f5c 100644
--- a/llvm/test/CodeGen/ARM/2011-04-07-schediv.ll
+++ b/llvm/test/CodeGen/ARM/2011-04-07-schediv.ll
@@ -4,9 +4,8 @@
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32"
target triple = "thumbv7-apple-darwin10"
-define void @t(i32 %src_width, float* nocapture %src_copy_start, float* nocapture %dst_copy_start, i32 %src_copy_start_index) nounwind optsize {
+define void @t(i32 %src_width, ptr nocapture %src_copy_start, ptr nocapture %dst_copy_start, i32 %src_copy_start_index) nounwind optsize {
entry:
- %src_copy_start6 = bitcast float* %src_copy_start to i8*
%0 = icmp eq i32 %src_width, 0
br i1 %0, label %return, label %bb
@@ -18,11 +17,10 @@ entry:
bb: ; preds = %entry, %bb
%j.05 = phi i32 [ %2, %bb ], [ 0, %entry ]
%tmp = mul i32 %j.05, %src_copy_start_index
- %uglygep = getelementptr i8, i8* %src_copy_start6, i32 %tmp
- %src_copy_start_addr.04 = bitcast i8* %uglygep to float*
- %dst_copy_start_addr.03 = getelementptr float, float* %dst_copy_start, i32 %j.05
- %1 = load float, float* %src_copy_start_addr.04, align 4
- store float %1, float* %dst_copy_start_addr.03, align 4
+ %uglygep = getelementptr i8, ptr %src_copy_start, i32 %tmp
+ %dst_copy_start_addr.03 = getelementptr float, ptr %dst_copy_start, i32 %j.05
+ %1 = load float, ptr %uglygep, align 4
+ store float %1, ptr %dst_copy_start_addr.03, align 4
%2 = add i32 %j.05, 1
%exitcond = icmp eq i32 %2, %src_width
br i1 %exitcond, label %return, label %bb
diff --git a/llvm/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll b/llvm/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll
index 54fc9b049b8e9..ad743fde20a12 100644
--- a/llvm/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll
+++ b/llvm/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll
@@ -3,7 +3,7 @@
; Overly aggressive LICM simply adds copies of constants
; rdar://9266679
-define zeroext i1 @t(i32* nocapture %A, i32 %size, i32 %value) nounwind readonly ssp {
+define zeroext i1 @t(ptr nocapture %A, i32 %size, i32 %value) nounwind readonly ssp {
; CHECK-LABEL: t:
entry:
br label %for.cond
@@ -18,8 +18,8 @@ for.body:
; CHECK: mov{{.*}} r{{[0-9]+}}, #{{[01]}}
; CHECK: mov{{.*}} r{{[0-9]+}}, #{{[01]}}
; CHECK-NOT: mov r{{[0-9]+}}, #{{[01]}}
- %arrayidx = getelementptr i32, i32* %A, i32 %0
- %tmp4 = load i32, i32* %arrayidx, align 4
+ %arrayidx = getelementptr i32, ptr %A, i32 %0
+ %tmp4 = load i32, ptr %arrayidx, align 4
%cmp6 = icmp eq i32 %tmp4, %value
br i1 %cmp6, label %return, label %for.inc
diff --git a/llvm/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll b/llvm/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll
index 8ad654fc8f9d0..0fbe7da66fe7f 100644
--- a/llvm/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll
+++ b/llvm/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll
@@ -7,7 +7,7 @@ target triple = "thumbv7-apple-darwin10.0.0"
define void @_Z8TestCasev() nounwind ssp {
entry:
%a = alloca float, align 4
- %tmp = load float, float* %a, align 4
+ %tmp = load float, ptr %a, align 4
call void asm sideeffect "", "w,~{s0},~{s16}"(float %tmp) nounwind, !srcloc !0
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll b/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll
index 3c5579acf6aec..f5134d8d1b5ce 100644
--- a/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll
+++ b/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll
@@ -4,10 +4,10 @@
; more callee-saved registers and introduce copies.
; rdar://9329627
-%struct.FF = type { i32 (i32*)*, i32 (i32*, i32*, i32, i32, i32, i32)*, i32 (i32, i32, i8*)*, void ()*, i32 (i32, i8*, i32*)*, i32 ()* }
-%struct.BD = type { %struct.BD*, i32, i32, i32, i32, i64, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i64, i32)*, [16 x i8], i64, i64 }
+%struct.FF = type { ptr, ptr, ptr, ptr, ptr, ptr }
+%struct.BD = type { ptr, i32, i32, i32, i32, i64, ptr, ptr, ptr, ptr, ptr, [16 x i8], i64, i64 }
- at FuncPtr = external hidden unnamed_addr global %struct.FF*
+ at FuncPtr = external hidden unnamed_addr global ptr
@.str1 = external hidden unnamed_addr constant [6 x i8], align 4
@G = external unnamed_addr global i32
@.str2 = external hidden unnamed_addr constant [58 x i8], align 4
@@ -21,8 +21,8 @@ entry:
%block_size = alloca i32, align 4
%block_count = alloca i32, align 4
%index_cache = alloca i32, align 4
- store i32 0, i32* %index_cache, align 4
- %tmp = load i32, i32* @G, align 4
+ store i32 0, ptr %index_cache, align 4
+ %tmp = load i32, ptr @G, align 4
%tmp1 = call i32 @bar(i32 0, i32 0, i32 %tmp) nounwind
switch i32 %tmp1, label %bb8 [
i32 0, label %bb
@@ -31,7 +31,7 @@ entry:
]
bb:
- %tmp2 = load i32, i32* @G, align 4
+ %tmp2 = load i32, ptr @G, align 4
%tmp4 = icmp eq i32 %tmp2, 0
br i1 %tmp4, label %bb1, label %bb8
@@ -41,14 +41,14 @@ bb1:
; CHECK: bl _Get
; CHECK: umull
; CHECK: bl _foo
- %tmp5 = load i32, i32* %block_size, align 4
- %tmp6 = load i32, i32* %block_count, align 4
- %tmp7 = call %struct.FF* @Get() nounwind
- store %struct.FF* %tmp7, %struct.FF** @FuncPtr, align 4
+ %tmp5 = load i32, ptr %block_size, align 4
+ %tmp6 = load i32, ptr %block_count, align 4
+ %tmp7 = call ptr @Get() nounwind
+ store ptr %tmp7, ptr @FuncPtr, align 4
%tmp10 = zext i32 %tmp6 to i64
%tmp11 = zext i32 %tmp5 to i64
%tmp12 = mul nsw i64 %tmp10, %tmp11
- %tmp13 = call i32 @foo(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), i64 %tmp12, i32 %tmp5) nounwind
+ %tmp13 = call i32 @foo(ptr @.str1, i64 %tmp12, i32 %tmp5) nounwind
br label %bb8
bb4:
@@ -61,10 +61,10 @@ bb8:
ret i32 -1
}
-declare i32 @printf(i8*, ...)
+declare i32 @printf(ptr, ...)
-declare %struct.FF* @Get()
+declare ptr @Get()
-declare i32 @foo(i8*, i64, i32)
+declare i32 @foo(ptr, i64, i32)
declare i32 @bar(i32, i32, i32)
diff --git a/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll b/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll
index 0741049cffdd3..5996db7db79a4 100644
--- a/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll
+++ b/llvm/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll
@@ -41,11 +41,11 @@ if.then115:
br i1 undef, label %if.else163, label %if.else145
if.else145:
- %call150 = call fastcc %struct.hc* @foo(%struct.hc* undef, i32 34865152) optsize
+ %call150 = call fastcc ptr @foo(ptr undef, i32 34865152) optsize
br label %while.body172
if.else163:
- %call168 = call fastcc %struct.hc* @foo(%struct.hc* undef, i32 34078720) optsize
+ %call168 = call fastcc ptr @foo(ptr undef, i32 34078720) optsize
br label %while.body172
while.body172:
@@ -55,5 +55,5 @@ if.else173:
ret i32 -1
}
-declare hidden fastcc %struct.hc* @foo(%struct.hc* nocapture, i32) nounwind optsize
+declare hidden fastcc ptr @foo(ptr nocapture, i32) nounwind optsize
diff --git a/llvm/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll b/llvm/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll
index 26b2a6efeebec..397fc27aec4c0 100644
--- a/llvm/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll
+++ b/llvm/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll
@@ -4,7 +4,7 @@
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
target triple = "thumbv7-apple-darwin"
-define void @func() unnamed_addr align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
+define void @func() unnamed_addr align 2 personality ptr @__gxx_personality_sj0 {
entry:
br label %for.cond
@@ -36,14 +36,14 @@ for.cond.backedge:
br label %for.cond
lpad:
- %exn = landingpad { i8*, i32 }
- catch i8* null
+ %exn = landingpad { ptr, i32 }
+ catch ptr null
invoke void @foo()
to label %eh.resume unwind label %terminate.lpad
lpad26:
- %exn27 = landingpad { i8*, i32 }
- catch i8* null
+ %exn27 = landingpad { ptr, i32 }
+ catch ptr null
invoke void @foo()
to label %eh.resume unwind label %terminate.lpad
@@ -58,18 +58,18 @@ call8.i.i.i.noexc:
ret void
lpad44:
- %exn45 = landingpad { i8*, i32 }
- catch i8* null
+ %exn45 = landingpad { ptr, i32 }
+ catch ptr null
invoke void @foo()
to label %eh.resume unwind label %terminate.lpad
eh.resume:
- %exn.slot.0 = phi { i8*, i32 } [ %exn27, %lpad26 ], [ %exn, %lpad ], [ %exn45, %lpad44 ]
- resume { i8*, i32 } %exn.slot.0
+ %exn.slot.0 = phi { ptr, i32 } [ %exn27, %lpad26 ], [ %exn, %lpad ], [ %exn45, %lpad44 ]
+ resume { ptr, i32 } %exn.slot.0
terminate.lpad:
- %exn51 = landingpad { i8*, i32 }
- catch i8* null
+ %exn51 = landingpad { ptr, i32 }
+ catch ptr null
tail call void @_ZSt9terminatev() noreturn nounwind
unreachable
}
@@ -78,7 +78,7 @@ declare void @foo()
declare i32 @__gxx_personality_sj0(...)
-declare void @_Unwind_SjLj_Resume_or_Rethrow(i8*)
+declare void @_Unwind_SjLj_Resume_or_Rethrow(ptr)
declare void @_ZSt9terminatev()
diff --git a/llvm/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll b/llvm/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll
index b2557b7165db8..40f626f51db89 100644
--- a/llvm/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll
+++ b/llvm/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll
@@ -4,26 +4,26 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-
target triple = "thumbv7-apple-darwin10"
%struct._RuneCharClass = type { [14 x i8], i32 }
-%struct._RuneEntry = type { i32, i32, i32, i32* }
-%struct._RuneLocale = type { [8 x i8], [32 x i8], i32 (i8*, i32, i8**)*, i32 (i32, i8*, i32, i8**)*, i32, [256 x i32], [256 x i32], [256 x i32], %struct._RuneRange, %struct._RuneRange, %struct._RuneRange, i8*, i32, i32, %struct._RuneCharClass* }
-%struct._RuneRange = type { i32, %struct._RuneEntry* }
+%struct._RuneEntry = type { i32, i32, i32, ptr }
+%struct._RuneLocale = type { [8 x i8], [32 x i8], ptr, ptr, i32, [256 x i32], [256 x i32], [256 x i32], %struct._RuneRange, %struct._RuneRange, %struct._RuneRange, ptr, i32, i32, ptr }
+%struct._RuneRange = type { i32, ptr }
%struct.__collate_st_chain_pri = type { [10 x i32], [2 x i32] }
%struct.__collate_st_char_pri = type { [2 x i32] }
%struct.__collate_st_info = type { [2 x i8], i8, i8, [2 x i32], [2 x i32], i32, i32 }
%struct.__collate_st_large_char_pri = type { i32, %struct.__collate_st_char_pri }
%struct.__collate_st_subst = type { i32, [10 x i32] }
-%struct.__xlocale_st_collate = type { i32, void (i8*)*, [32 x i8], %struct.__collate_st_info, [2 x %struct.__collate_st_subst*], %struct.__collate_st_chain_pri*, %struct.__collate_st_large_char_pri*, [256 x %struct.__collate_st_char_pri] }
-%struct.__xlocale_st_messages = type { i32, void (i8*)*, i8*, %struct.lc_messages_T }
-%struct.__xlocale_st_monetary = type { i32, void (i8*)*, i8*, %struct.lc_monetary_T }
-%struct.__xlocale_st_numeric = type { i32, void (i8*)*, i8*, %struct.lc_numeric_T }
-%struct.__xlocale_st_runelocale = type { i32, void (i8*)*, [32 x i8], i32, i32, i32 (i32*, i8*, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32 (%union.__mbstate_t*, %struct._xlocale*)*, i32 (i32*, i8**, i32, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32 (i8*, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32 (i8*, i32**, i32, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32, %struct._RuneLocale }
-%struct.__xlocale_st_time = type { i32, void (i8*)*, i8*, %struct.lc_time_T }
-%struct._xlocale = type { i32, void (i8*)*, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, i32, i64, i8, i8, i8, i8, i8, i8, i8, i8, i8, %struct.__xlocale_st_collate*, %struct.__xlocale_st_runelocale*, %struct.__xlocale_st_messages*, %struct.__xlocale_st_monetary*, %struct.__xlocale_st_numeric*, %struct._xlocale*, %struct.__xlocale_st_time*, %struct.lconv }
-%struct.lc_messages_T = type { i8*, i8*, i8*, i8* }
-%struct.lc_monetary_T = type { i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8* }
-%struct.lc_numeric_T = type { i8*, i8*, i8* }
-%struct.lc_time_T = type { [12 x i8*], [12 x i8*], [7 x i8*], [7 x i8*], i8*, i8*, i8*, i8*, i8*, i8*, [12 x i8*], i8*, i8* }
-%struct.lconv = type { i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
+%struct.__xlocale_st_collate = type { i32, ptr, [32 x i8], %struct.__collate_st_info, [2 x ptr], ptr, ptr, [256 x %struct.__collate_st_char_pri] }
+%struct.__xlocale_st_messages = type { i32, ptr, ptr, %struct.lc_messages_T }
+%struct.__xlocale_st_monetary = type { i32, ptr, ptr, %struct.lc_monetary_T }
+%struct.__xlocale_st_numeric = type { i32, ptr, ptr, %struct.lc_numeric_T }
+%struct.__xlocale_st_runelocale = type { i32, ptr, [32 x i8], i32, i32, ptr, ptr, ptr, ptr, ptr, i32, %struct._RuneLocale }
+%struct.__xlocale_st_time = type { i32, ptr, ptr, %struct.lc_time_T }
+%struct._xlocale = type { i32, ptr, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, i32, i64, i8, i8, i8, i8, i8, i8, i8, i8, i8, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %struct.lconv }
+%struct.lc_messages_T = type { ptr, ptr, ptr, ptr }
+%struct.lc_monetary_T = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }
+%struct.lc_numeric_T = type { ptr, ptr, ptr }
+%struct.lc_time_T = type { [12 x ptr], [12 x ptr], [7 x ptr], [7 x ptr], ptr, ptr, ptr, ptr, ptr, ptr, [12 x ptr], ptr, ptr }
+%struct.lconv = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
%union.__mbstate_t = type { i64, [120 x i8] }
@"\01_fnmatch.initial" = external constant %union.__mbstate_t, align 4
@@ -31,10 +31,10 @@ target triple = "thumbv7-apple-darwin10"
; CHECK: _fnmatch
; CHECK: bl _fnmatch1
-define i32 @"\01_fnmatch"(i8* %pattern, i8* %string, i32 %flags) nounwind optsize {
+define i32 @"\01_fnmatch"(ptr %pattern, ptr %string, i32 %flags) nounwind optsize {
entry:
- %call4 = tail call i32 @fnmatch1(i8* %pattern, i8* %string, i8* %string, i32 %flags, %union.__mbstate_t* byval(%union.__mbstate_t) @"\01_fnmatch.initial", %union.__mbstate_t* byval(%union.__mbstate_t) @"\01_fnmatch.initial", %struct._xlocale* undef, i32 64) optsize
+ %call4 = tail call i32 @fnmatch1(ptr %pattern, ptr %string, ptr %string, i32 %flags, ptr byval(%union.__mbstate_t) @"\01_fnmatch.initial", ptr byval(%union.__mbstate_t) @"\01_fnmatch.initial", ptr undef, i32 64) optsize
ret i32 %call4
}
-declare i32 @fnmatch1(i8*, i8*, i8*, i32, %union.__mbstate_t* byval(%union.__mbstate_t), %union.__mbstate_t* byval(%union.__mbstate_t), %struct._xlocale*, i32) nounwind optsize
+declare i32 @fnmatch1(ptr, ptr, ptr, i32, ptr byval(%union.__mbstate_t), ptr byval(%union.__mbstate_t), ptr, i32) nounwind optsize
diff --git a/llvm/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll b/llvm/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll
index aa83b7e2fa820..089df7c2c0229 100644
--- a/llvm/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll
+++ b/llvm/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll
@@ -16,10 +16,10 @@ target triple = "thumbv7-apple-ios5.0"
; CHECK: add sp, #12
; CHECK: b.w _puts
-define void @f(i8* %s, %struct.A* nocapture byval(%struct.A) %a) nounwind optsize {
+define void @f(ptr %s, ptr nocapture byval(%struct.A) %a) nounwind optsize {
entry:
- %puts = tail call i32 @puts(i8* %s)
+ %puts = tail call i32 @puts(ptr %s)
ret void
}
-declare i32 @puts(i8* nocapture) nounwind
+declare i32 @puts(ptr nocapture) nounwind
diff --git a/llvm/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll b/llvm/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll
index aac8f7b3a026b..bf9e6f47ed947 100644
--- a/llvm/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll
+++ b/llvm/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll
@@ -3,7 +3,7 @@
@prev = external global [0 x i16]
@max_lazy_match = internal unnamed_addr global i32 0, align 4
- at read_buf = external global i32 (i8*, i32)*
+ at read_buf = external global ptr
@window = external global [0 x i8]
@lookahead = internal unnamed_addr global i32 0, align 4
@eofile.b = internal unnamed_addr global i32 0
diff --git a/llvm/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/llvm/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll
index f7cdc83d0d949..ceec112ffe823 100644
--- a/llvm/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll
+++ b/llvm/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll
@@ -21,9 +21,9 @@ target triple = "thumbv7-apple-macosx10.7.0"
; Function Attrs: nounwind optsize ssp
define i32 @get1(i32 %a) #0 !dbg !10 {
tail call void @llvm.dbg.value(metadata i32 %a, metadata !14, metadata !17), !dbg !18
- %1 = load i32, i32* @x1, align 4, !dbg !19
+ %1 = load i32, ptr @x1, align 4, !dbg !19
tail call void @llvm.dbg.value(metadata i32 %1, metadata !15, metadata !17), !dbg !19
- store i32 %a, i32* @x1, align 4, !dbg !19
+ store i32 %a, ptr @x1, align 4, !dbg !19
ret i32 %1, !dbg !19
}
@@ -31,9 +31,9 @@ define i32 @get1(i32 %a) #0 !dbg !10 {
define i32 @get2(i32 %a) #0 !dbg !20 {
tail call void @llvm.dbg.value(metadata i32 %a, metadata !22, metadata !17), !dbg !25
- %1 = load i32, i32* @x2, align 4, !dbg !26
+ %1 = load i32, ptr @x2, align 4, !dbg !26
tail call void @llvm.dbg.value(metadata i32 %1, metadata !23, metadata !17), !dbg !26
- store i32 %a, i32* @x2, align 4, !dbg !26
+ store i32 %a, ptr @x2, align 4, !dbg !26
ret i32 %1, !dbg !26
}
@@ -41,9 +41,9 @@ define i32 @get2(i32 %a) #0 !dbg !20 {
define i32 @get3(i32 %a) #0 !dbg !27 {
tail call void @llvm.dbg.value(metadata i32 %a, metadata !29, metadata !17), !dbg !32
- %1 = load i32, i32* @x3, align 4, !dbg !33
+ %1 = load i32, ptr @x3, align 4, !dbg !33
tail call void @llvm.dbg.value(metadata i32 %1, metadata !30, metadata !17), !dbg !33
- store i32 %a, i32* @x3, align 4, !dbg !33
+ store i32 %a, ptr @x3, align 4, !dbg !33
ret i32 %1, !dbg !33
}
@@ -51,9 +51,9 @@ define i32 @get3(i32 %a) #0 !dbg !27 {
define i32 @get4(i32 %a) #0 !dbg !34 {
tail call void @llvm.dbg.value(metadata i32 %a, metadata !36, metadata !17), !dbg !39
- %1 = load i32, i32* @x4, align 4, !dbg !40
+ %1 = load i32, ptr @x4, align 4, !dbg !40
tail call void @llvm.dbg.value(metadata i32 %1, metadata !37, metadata !17), !dbg !40
- store i32 %a, i32* @x4, align 4, !dbg !40
+ store i32 %a, ptr @x4, align 4, !dbg !40
ret i32 %1, !dbg !40
}
@@ -61,9 +61,9 @@ define i32 @get4(i32 %a) #0 !dbg !34 {
define i32 @get5(i32 %a) #0 !dbg !41 {
tail call void @llvm.dbg.value(metadata i32 %a, metadata !43, metadata !17), !dbg !46
- %1 = load i32, i32* @x5, align 4, !dbg !47
+ %1 = load i32, ptr @x5, align 4, !dbg !47
tail call void @llvm.dbg.value(metadata i32 %1, metadata !44, metadata !17), !dbg !47
- store i32 %a, i32* @x5, align 4, !dbg !47
+ store i32 %a, ptr @x5, align 4, !dbg !47
ret i32 %1, !dbg !47
}
diff --git a/llvm/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll b/llvm/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
index d702af7c0c708..cebf96e56eedb 100644
--- a/llvm/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
+++ b/llvm/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
@@ -4,9 +4,9 @@
define void @test_vmovqqqq_pseudo() nounwind ssp {
entry:
- %vld3_lane = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16.p0i8(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> zeroinitializer, i32 7, i32 2)
- store { <8 x i16>, <8 x i16>, <8 x i16> } %vld3_lane, { <8 x i16>, <8 x i16>, <8 x i16> }* undef
+ %vld3_lane = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16.p0(ptr undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> zeroinitializer, i32 7, i32 2)
+ store { <8 x i16>, <8 x i16>, <8 x i16> } %vld3_lane, ptr undef
ret void
}
-declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16.p0i8(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
+declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16.p0(ptr, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
diff --git a/llvm/test/CodeGen/ARM/2011-08-29-SchedCycle.ll b/llvm/test/CodeGen/ARM/2011-08-29-SchedCycle.ll
index fb8454479508e..52324436baad2 100644
--- a/llvm/test/CodeGen/ARM/2011-08-29-SchedCycle.ll
+++ b/llvm/test/CodeGen/ARM/2011-08-29-SchedCycle.ll
@@ -32,14 +32,14 @@
define void @t() nounwind {
entry:
- %tmp = load i64, i64* undef, align 4
+ %tmp = load i64, ptr undef, align 4
%tmp5 = udiv i64 %tmp, 30
%tmp13 = and i64 %tmp5, 64739244643450880
%tmp16 = sub i64 0, %tmp13
%tmp19 = and i64 %tmp16, 63
%tmp20 = urem i64 %tmp19, 3
%tmp22 = and i64 %tmp16, -272346829004752
- store i64 %tmp22, i64* undef, align 4
- store i64 %tmp20, i64* undef, align 4
+ store i64 %tmp22, ptr undef, align 4
+ store i64 %tmp20, ptr undef, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll b/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll
index d9b38b5e5735c..c31e8462f49de 100644
--- a/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll
+++ b/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll
@@ -17,14 +17,14 @@ bb25.lr.ph: ; preds = %entry
bb.i: ; preds = %bb5.i
%1 = shl nsw i32 %k_addr.0.i, 1
%.sum8.i = add i32 %1, -1
- %2 = getelementptr inbounds [256 x i32], [256 x i32]* %heap, i32 0, i32 %.sum8.i
- %3 = load i32, i32* %2, align 4
+ %2 = getelementptr inbounds [256 x i32], ptr %heap, i32 0, i32 %.sum8.i
+ %3 = load i32, ptr %2, align 4
br i1 false, label %bb5.i, label %bb4.i
bb4.i: ; preds = %bb.i
%.sum10.i = add i32 %k_addr.0.i, -1
- %4 = getelementptr inbounds [256 x i32], [256 x i32]* %heap, i32 0, i32 %.sum10.i
- store i32 %3, i32* %4, align 4
+ %4 = getelementptr inbounds [256 x i32], ptr %heap, i32 0, i32 %.sum10.i
+ store i32 %3, ptr %4, align 4
br label %bb5.i
bb5.i: ; preds = %bb5.i, %bb4.i, %bb.i, %bb25.lr.ph
diff --git a/llvm/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll b/llvm/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
index 2561af707d755..c22ab937a0792 100644
--- a/llvm/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
+++ b/llvm/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
@@ -11,13 +11,13 @@ target triple = "armv7-none-linux-gnueabi"
@z2 = common global <4 x i16> zeroinitializer
define void @f() {
- %1 = load <3 x i16>, <3 x i16>* @x1
- %2 = load <3 x i16>, <3 x i16>* @y1
+ %1 = load <3 x i16>, ptr @x1
+ %2 = load <3 x i16>, ptr @y1
%3 = sdiv <3 x i16> %1, %2
- store <3 x i16> %3, <3 x i16>* @z1
- %4 = load <4 x i16>, <4 x i16>* @x2
- %5 = load <4 x i16>, <4 x i16>* @y2
+ store <3 x i16> %3, ptr @z1
+ %4 = load <4 x i16>, ptr @x2
+ %5 = load <4 x i16>, ptr @y2
%6 = sdiv <4 x i16> %4, %5
- store <4 x i16> %6, <4 x i16>* @z2
+ store <4 x i16> %6, ptr @z2
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll b/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll
index a0205fcdd348d..4309d9408aaa7 100644
--- a/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll
+++ b/llvm/test/CodeGen/ARM/2011-09-19-cpsr.ll
@@ -8,9 +8,9 @@
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32"
target triple = "thumbv7-apple-ios4.0.0"
-declare i8* @__memset_chk(i8*, i32, i32, i32) nounwind
+declare ptr @__memset_chk(ptr, i32, i32, i32) nounwind
-define hidden fastcc i32 @sqlite3VdbeExec(i32* %p) nounwind {
+define hidden fastcc i32 @sqlite3VdbeExec(ptr %p) nounwind {
entry:
br label %sqlite3VarintLen.exit7424
@@ -40,7 +40,7 @@ for.body2377: ; preds = %for.body2355
%conv2385 = trunc i64 %sub2384 to i32
%len.0.i = select i1 undef, i32 %conv2385, i32 undef
%sub.i7384 = sub nsw i32 %len.0.i, 0
- %call.i.i7385 = call i8* @__memset_chk(i8* undef, i32 0, i32 %sub.i7384, i32 undef) nounwind
+ %call.i.i7385 = call ptr @__memset_chk(ptr undef, i32 0, i32 %sub.i7384, i32 undef) nounwind
unreachable
too_big: ; preds = %sqlite3VarintLen.exit
diff --git a/llvm/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll b/llvm/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll
index 53e3bed538313..f2edd262a6323 100644
--- a/llvm/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll
+++ b/llvm/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll
@@ -4,7 +4,7 @@
; ARM target specific dag combine created a cycle in DAG.
define void @t() nounwind ssp {
- %1 = load i64, i64* undef, align 4
+ %1 = load i64, ptr undef, align 4
%2 = shl i32 5, 0
%3 = zext i32 %2 to i64
%4 = and i64 %1, %3
diff --git a/llvm/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll b/llvm/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll
index 6f6624d1bbc7c..4463e63085b82 100644
--- a/llvm/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll
+++ b/llvm/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll
@@ -2,20 +2,16 @@
target triple = "armv6-none-linux-gnueabi"
-define void @sample_test(i8* %.T0348, i16* nocapture %sourceA, i16* nocapture %destValues) {
+define void @sample_test(ptr %.T0348, ptr nocapture %sourceA, ptr nocapture %destValues) {
L.entry:
- %0 = call i32 (...) @get_index(i8* %.T0348, i32 0)
- %1 = bitcast i16* %destValues to i8*
- %2 = mul i32 %0, 6
- %3 = getelementptr i8, i8* %1, i32 %2
- %4 = bitcast i8* %3 to <3 x i16>*
- %5 = load <3 x i16>, <3 x i16>* %4, align 1
- %6 = bitcast i16* %sourceA to i8*
- %7 = getelementptr i8, i8* %6, i32 %2
- %8 = bitcast i8* %7 to <3 x i16>*
- %9 = load <3 x i16>, <3 x i16>* %8, align 1
- %10 = or <3 x i16> %9, %5
- store <3 x i16> %10, <3 x i16>* %4, align 1
+ %0 = call i32 (...) @get_index(ptr %.T0348, i32 0)
+ %1 = mul i32 %0, 6
+ %2 = getelementptr i8, ptr %destValues, i32 %1
+ %3 = load <3 x i16>, ptr %2, align 1
+ %4 = getelementptr i8, ptr %sourceA, i32 %1
+ %5 = load <3 x i16>, ptr %4, align 1
+ %6 = or <3 x i16> %5, %3
+ store <3 x i16> %6, ptr %2, align 1
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2011-10-26-memset-inline.ll b/llvm/test/CodeGen/ARM/2011-10-26-memset-inline.ll
index 8d6ce34c26d99..b4f368e1c00e4 100644
--- a/llvm/test/CodeGen/ARM/2011-10-26-memset-inline.ll
+++ b/llvm/test/CodeGen/ARM/2011-10-26-memset-inline.ll
@@ -12,10 +12,10 @@ target triple = "thumbv7-apple-ios5.0.0"
; CHECK-GENERIC-NEXT: strb
; CHECK-UNALIGNED: strb
; CHECK-UNALIGNED: str
-define void @foo(i8* nocapture %c) nounwind optsize {
+define void @foo(ptr nocapture %c) nounwind optsize {
entry:
- call void @llvm.memset.p0i8.i64(i8* %c, i8 -1, i64 5, i1 false)
+ call void @llvm.memset.p0.i64(ptr %c, i8 -1, i64 5, i1 false)
ret void
}
-declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind
+declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind
diff --git a/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll b/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
index 7024a653b6c9f..b394f8194aac2 100644
--- a/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
+++ b/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
@@ -3,10 +3,10 @@
; Trigger multiple NEON stores.
; CHECK: vst1.64
; CHECK: vst1.64
-define void @f_0_40(i8* nocapture %c) nounwind optsize {
+define void @f_0_40(ptr nocapture %c) nounwind optsize {
entry:
- call void @llvm.memset.p0i8.i64(i8* align 16 %c, i8 0, i64 40, i1 false)
+ call void @llvm.memset.p0.i64(ptr align 16 %c, i8 0, i64 40, i1 false)
ret void
}
-declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind
+declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind
diff --git a/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll b/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
index e7059716c49be..473a4924f7960 100644
--- a/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
+++ b/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
@@ -7,18 +7,18 @@
define void @test_neon_vector_add_2xi8() nounwind {
; CHECK-LABEL: test_neon_vector_add_2xi8:
- %1 = load <2 x i8>, <2 x i8>* @i8_src1
- %2 = load <2 x i8>, <2 x i8>* @i8_src2
+ %1 = load <2 x i8>, ptr @i8_src1
+ %2 = load <2 x i8>, ptr @i8_src2
%3 = add <2 x i8> %1, %2
- store <2 x i8> %3, <2 x i8>* @i8_res
+ store <2 x i8> %3, ptr @i8_res
ret void
}
define void @test_neon_ld_st_volatile_with_ashr_2xi8() {
; CHECK-LABEL: test_neon_ld_st_volatile_with_ashr_2xi8:
- %1 = load volatile <2 x i8>, <2 x i8>* @i8_src1
- %2 = load volatile <2 x i8>, <2 x i8>* @i8_src2
+ %1 = load volatile <2 x i8>, ptr @i8_src1
+ %2 = load volatile <2 x i8>, ptr @i8_src2
%3 = ashr <2 x i8> %1, %2
- store volatile <2 x i8> %3, <2 x i8>* @i8_res
+ store volatile <2 x i8> %3, ptr @i8_res
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll b/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll
index 6dc9d4b7025d9..1fc43c3257e91 100644
--- a/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll
+++ b/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll
@@ -8,8 +8,8 @@ declare <2 x i16> @foo_v2i16(<2 x i16>) nounwind
define void @test_neon_call_return_v2i16() {
; CHECK-LABEL: test_neon_call_return_v2i16:
- %1 = load <2 x i16>, <2 x i16>* @src1_v2i16
+ %1 = load <2 x i16>, ptr @src1_v2i16
%2 = call <2 x i16> @foo_v2i16(<2 x i16> %1) nounwind
- store <2 x i16> %2, <2 x i16>* @res_v2i16
+ store <2 x i16> %2, ptr @res_v2i16
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll b/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll
index 1da93bdd7c947..4289838528794 100644
--- a/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll
+++ b/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll
@@ -1,37 +1,37 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <2 x i32> @test1(<2 x double>* %A) {
+define <2 x i32> @test1(ptr %A) {
; CHECK: test1
; CHECK: vcvt.s32.f64
; CHECK: vcvt.s32.f64
- %tmp1 = load <2 x double>, <2 x double>* %A
+ %tmp1 = load <2 x double>, ptr %A
%tmp2 = fptosi <2 x double> %tmp1 to <2 x i32>
ret <2 x i32> %tmp2
}
-define <2 x i32> @test2(<2 x double>* %A) {
+define <2 x i32> @test2(ptr %A) {
; CHECK: test2
; CHECK: vcvt.u32.f64
; CHECK: vcvt.u32.f64
- %tmp1 = load <2 x double>, <2 x double>* %A
+ %tmp1 = load <2 x double>, ptr %A
%tmp2 = fptoui <2 x double> %tmp1 to <2 x i32>
ret <2 x i32> %tmp2
}
-define <2 x double> @test3(<2 x i32>* %A) {
+define <2 x double> @test3(ptr %A) {
; CHECK: test3
; CHECK: vcvt.f64.s32
; CHECK: vcvt.f64.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = sitofp <2 x i32> %tmp1 to <2 x double>
ret <2 x double> %tmp2
}
-define <2 x double> @test4(<2 x i32>* %A) {
+define <2 x double> @test4(ptr %A) {
; CHECK: test4
; CHECK: vcvt.f64.u32
; CHECK: vcvt.f64.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = uitofp <2 x i32> %tmp1 to <2 x double>
ret <2 x double> %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll b/llvm/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll
index 38fc3bcd8873e..89c1cebd404cb 100644
--- a/llvm/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll
+++ b/llvm/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll
@@ -15,45 +15,45 @@ target triple = "thumbv7-apple-ios"
%struct.Transform_Struct.0.11.12.17.43.46.56.58.60 = type { [4 x [4 x double]] }
-define void @Compute_Axis_Rotation_Transform(%struct.Transform_Struct.0.11.12.17.43.46.56.58.60* nocapture %transform, double* nocapture %V1, double %angle) nounwind {
+define void @Compute_Axis_Rotation_Transform(ptr nocapture %transform, ptr nocapture %V1, double %angle) nounwind {
entry:
- store double 1.000000e+00, double* null, align 4
- %arrayidx5.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 1
- store double 0.000000e+00, double* %arrayidx5.1.i, align 4
- %arrayidx5.2.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 2
- store double 0.000000e+00, double* %arrayidx5.2.i, align 4
- %arrayidx5.114.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 0
- store double 0.000000e+00, double* %arrayidx5.114.i, align 4
- %arrayidx5.1.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 1
- store double 1.000000e+00, double* %arrayidx5.1.1.i, align 4
- store double 0.000000e+00, double* null, align 4
- store double 1.000000e+00, double* null, align 4
- store double 0.000000e+00, double* null, align 4
+ store double 1.000000e+00, ptr null, align 4
+ %arrayidx5.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, ptr %transform, i32 0, i32 0, i32 0, i32 1
+ store double 0.000000e+00, ptr %arrayidx5.1.i, align 4
+ %arrayidx5.2.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, ptr %transform, i32 0, i32 0, i32 0, i32 2
+ store double 0.000000e+00, ptr %arrayidx5.2.i, align 4
+ %arrayidx5.114.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, ptr %transform, i32 0, i32 0, i32 1, i32 0
+ store double 0.000000e+00, ptr %arrayidx5.114.i, align 4
+ %arrayidx5.1.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, ptr %transform, i32 0, i32 0, i32 1, i32 1
+ store double 1.000000e+00, ptr %arrayidx5.1.1.i, align 4
+ store double 0.000000e+00, ptr null, align 4
+ store double 1.000000e+00, ptr null, align 4
+ store double 0.000000e+00, ptr null, align 4
%call = tail call double @cos(double %angle) nounwind readnone
%call1 = tail call double @sin(double %angle) nounwind readnone
- %0 = load double, double* %V1, align 4
- %arrayidx2 = getelementptr inbounds double, double* %V1, i32 1
- %1 = load double, double* %arrayidx2, align 4
+ %0 = load double, ptr %V1, align 4
+ %arrayidx2 = getelementptr inbounds double, ptr %V1, i32 1
+ %1 = load double, ptr %arrayidx2, align 4
%mul = fmul double %0, %1
%sub = fsub double 1.000000e+00, %call
%mul3 = fmul double %mul, %sub
- %2 = load double, double* undef, align 4
+ %2 = load double, ptr undef, align 4
%mul5 = fmul double %2, %call1
%add = fadd double %mul3, %mul5
- store double %add, double* %arrayidx5.1.i, align 4
- %3 = load double, double* %V1, align 4
+ store double %add, ptr %arrayidx5.1.i, align 4
+ %3 = load double, ptr %V1, align 4
%mul11 = fmul double %3, undef
%mul13 = fmul double %mul11, %sub
- %4 = load double, double* %arrayidx2, align 4
+ %4 = load double, ptr %arrayidx2, align 4
%mul15 = fmul double %4, %call1
%sub16 = fsub double %mul13, %mul15
- store double %sub16, double* %arrayidx5.2.i, align 4
- %5 = load double, double* %V1, align 4
- %6 = load double, double* %arrayidx2, align 4
+ store double %sub16, ptr %arrayidx5.2.i, align 4
+ %5 = load double, ptr %V1, align 4
+ %6 = load double, ptr %arrayidx2, align 4
%mul22 = fmul double %5, %6
%mul24 = fmul double %mul22, %sub
%sub27 = fsub double %mul24, undef
- store double %sub27, double* %arrayidx5.114.i, align 4
+ store double %sub27, ptr %arrayidx5.114.i, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll b/llvm/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll
index d820d688fde93..01648486489cd 100644
--- a/llvm/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll
+++ b/llvm/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll
@@ -15,14 +15,14 @@ define hidden void @foo() {
; CHECK: ldr.w
; CHECK-NOT: ldm
entry:
- %tmp13 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 0), align 1
- %tmp15 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 1), align 1
- %tmp17 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 2), align 1
- %tmp19 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 3), align 1
- %tmp = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 0), align 1
- %tmp3 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 1), align 1
- %tmp4 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 2), align 1
- %tmp5 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 3), align 1
+ %tmp13 = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 1, i32 0, i32 0), align 1
+ %tmp15 = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 1, i32 0, i32 1), align 1
+ %tmp17 = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 1, i32 0, i32 2), align 1
+ %tmp19 = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 1, i32 0, i32 3), align 1
+ %tmp = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 2, i32 0, i32 0), align 1
+ %tmp3 = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 2, i32 0, i32 1), align 1
+ %tmp4 = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 2, i32 0, i32 2), align 1
+ %tmp5 = load i32, ptr getelementptr inbounds (%struct.InformationBlock, ptr @infoBlock, i32 0, i32 2, i32 0, i32 3), align 1
%insert21 = insertvalue [4 x i32] undef, i32 %tmp13, 0
%insert23 = insertvalue [4 x i32] %insert21, i32 %tmp15, 1
%insert25 = insertvalue [4 x i32] %insert23, i32 %tmp17, 2
diff --git a/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll b/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
index 274f7bd4fb314..e14e598086249 100644
--- a/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
+++ b/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
@@ -2,7 +2,7 @@
@A = global <4 x float> <float 0., float 1., float 2., float 3.>
-define void @test_sqrt(<4 x float>* %X) nounwind {
+define void @test_sqrt(ptr %X) nounwind {
; CHECK-LABEL: test_sqrt:
@@ -16,16 +16,16 @@ define void @test_sqrt(<4 x float>* %X) nounwind {
; CHECK: vst1.64 {{.*}}
L.entry:
- %0 = load <4 x float>, <4 x float>* @A, align 16
+ %0 = load <4 x float>, ptr @A, align 16
%1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0)
- store <4 x float> %1, <4 x float>* %X, align 16
+ store <4 x float> %1, ptr %X, align 16
ret void
}
declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly
-define void @test_cos(<4 x float>* %X) nounwind {
+define void @test_cos(ptr %X) nounwind {
; CHECK-LABEL: test_cos:
@@ -48,15 +48,15 @@ define void @test_cos(<4 x float>* %X) nounwind {
; CHECK: vst1.64
L.entry:
- %0 = load <4 x float>, <4 x float>* @A, align 16
+ %0 = load <4 x float>, ptr @A, align 16
%1 = call <4 x float> @llvm.cos.v4f32(<4 x float> %0)
- store <4 x float> %1, <4 x float>* %X, align 16
+ store <4 x float> %1, ptr %X, align 16
ret void
}
declare <4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly
-define void @test_exp(<4 x float>* %X) nounwind {
+define void @test_exp(ptr %X) nounwind {
; CHECK-LABEL: test_exp:
@@ -79,15 +79,15 @@ define void @test_exp(<4 x float>* %X) nounwind {
; CHECK: vst1.64
L.entry:
- %0 = load <4 x float>, <4 x float>* @A, align 16
+ %0 = load <4 x float>, ptr @A, align 16
%1 = call <4 x float> @llvm.exp.v4f32(<4 x float> %0)
- store <4 x float> %1, <4 x float>* %X, align 16
+ store <4 x float> %1, ptr %X, align 16
ret void
}
declare <4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly
-define void @test_exp2(<4 x float>* %X) nounwind {
+define void @test_exp2(ptr %X) nounwind {
; CHECK-LABEL: test_exp2:
@@ -110,15 +110,15 @@ define void @test_exp2(<4 x float>* %X) nounwind {
; CHECK: vst1.64
L.entry:
- %0 = load <4 x float>, <4 x float>* @A, align 16
+ %0 = load <4 x float>, ptr @A, align 16
%1 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %0)
- store <4 x float> %1, <4 x float>* %X, align 16
+ store <4 x float> %1, ptr %X, align 16
ret void
}
declare <4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly
-define void @test_log10(<4 x float>* %X) nounwind {
+define void @test_log10(ptr %X) nounwind {
; CHECK-LABEL: test_log10:
@@ -141,15 +141,15 @@ define void @test_log10(<4 x float>* %X) nounwind {
; CHECK: vst1.64
L.entry:
- %0 = load <4 x float>, <4 x float>* @A, align 16
+ %0 = load <4 x float>, ptr @A, align 16
%1 = call <4 x float> @llvm.log10.v4f32(<4 x float> %0)
- store <4 x float> %1, <4 x float>* %X, align 16
+ store <4 x float> %1, ptr %X, align 16
ret void
}
declare <4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonly
-define void @test_log(<4 x float>* %X) nounwind {
+define void @test_log(ptr %X) nounwind {
; CHECK-LABEL: test_log:
@@ -172,15 +172,15 @@ define void @test_log(<4 x float>* %X) nounwind {
; CHECK: vst1.64
L.entry:
- %0 = load <4 x float>, <4 x float>* @A, align 16
+ %0 = load <4 x float>, ptr @A, align 16
%1 = call <4 x float> @llvm.log.v4f32(<4 x float> %0)
- store <4 x float> %1, <4 x float>* %X, align 16
+ store <4 x float> %1, ptr %X, align 16
ret void
}
declare <4 x float> @llvm.log.v4f32(<4 x float>) nounwind readonly
-define void @test_log2(<4 x float>* %X) nounwind {
+define void @test_log2(ptr %X) nounwind {
; CHECK-LABEL: test_log2:
@@ -203,16 +203,16 @@ define void @test_log2(<4 x float>* %X) nounwind {
; CHECK: vst1.64
L.entry:
- %0 = load <4 x float>, <4 x float>* @A, align 16
+ %0 = load <4 x float>, ptr @A, align 16
%1 = call <4 x float> @llvm.log2.v4f32(<4 x float> %0)
- store <4 x float> %1, <4 x float>* %X, align 16
+ store <4 x float> %1, ptr %X, align 16
ret void
}
declare <4 x float> @llvm.log2.v4f32(<4 x float>) nounwind readonly
-define void @test_pow(<4 x float>* %X) nounwind {
+define void @test_pow(ptr %X) nounwind {
; CHECK-LABEL: test_pow:
@@ -236,17 +236,17 @@ define void @test_pow(<4 x float>* %X) nounwind {
L.entry:
- %0 = load <4 x float>, <4 x float>* @A, align 16
+ %0 = load <4 x float>, ptr @A, align 16
%1 = call <4 x float> @llvm.pow.v4f32(<4 x float> %0, <4 x float> <float 2., float 2., float 2., float 2.>)
- store <4 x float> %1, <4 x float>* %X, align 16
+ store <4 x float> %1, ptr %X, align 16
ret void
}
declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) nounwind readonly
-define void @test_powi(<4 x float>* %X) nounwind {
+define void @test_powi(ptr %X) nounwind {
; CHECK-LABEL: test_powi:
@@ -259,17 +259,17 @@ define void @test_powi(<4 x float>* %X) nounwind {
L.entry:
- %0 = load <4 x float>, <4 x float>* @A, align 16
+ %0 = load <4 x float>, ptr @A, align 16
%1 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> %0, i32 2)
- store <4 x float> %1, <4 x float>* %X, align 16
+ store <4 x float> %1, ptr %X, align 16
ret void
}
declare <4 x float> @llvm.powi.v4f32.i32(<4 x float>, i32) nounwind readonly
-define void @test_sin(<4 x float>* %X) nounwind {
+define void @test_sin(ptr %X) nounwind {
; CHECK-LABEL: test_sin:
@@ -292,15 +292,15 @@ define void @test_sin(<4 x float>* %X) nounwind {
; CHECK: vst1.64
L.entry:
- %0 = load <4 x float>, <4 x float>* @A, align 16
+ %0 = load <4 x float>, ptr @A, align 16
%1 = call <4 x float> @llvm.sin.v4f32(<4 x float> %0)
- store <4 x float> %1, <4 x float>* %X, align 16
+ store <4 x float> %1, ptr %X, align 16
ret void
}
declare <4 x float> @llvm.sin.v4f32(<4 x float>) nounwind readonly
-define void @test_floor(<4 x float>* %X) nounwind {
+define void @test_floor(ptr %X) nounwind {
; CHECK-LABEL: test_floor:
@@ -323,9 +323,9 @@ define void @test_floor(<4 x float>* %X) nounwind {
; CHECK: vst1.64
L.entry:
- %0 = load <4 x float>, <4 x float>* @A, align 16
+ %0 = load <4 x float>, ptr @A, align 16
%1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0)
- store <4 x float> %1, <4 x float>* %X, align 16
+ store <4 x float> %1, ptr %X, align 16
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll b/llvm/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll
index 0d324404d7bea..16ea46f8a1c2a 100644
--- a/llvm/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll
+++ b/llvm/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll
@@ -8,9 +8,9 @@ target triple = "thumbv7-apple-darwin10"
@x2 = internal global i64 12
define i64 @f() {
- %ax = load i32, i32* @x1
+ %ax = load i32, ptr @x1
%a = zext i32 %ax to i64
- %b = load i64, i64* @x2
+ %b = load i64, ptr @x2
%c = add i64 %a, %b
ret i64 %c
}
diff --git a/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll b/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll
index 88019f450e366..de71e9e6271e4 100644
--- a/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll
+++ b/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll
@@ -16,14 +16,14 @@ for.cond: ; preds = %for.body, %entry
for.body: ; preds = %for.cond
%cond0 = icmp ne i32 %arg1, 42
%v.5 = select i1 %cond0, i32 undef, i32 0
- %0 = load i8, i8* undef, align 1
+ %0 = load i8, ptr undef, align 1
%conv88 = zext i8 %0 to i32
%sub89 = sub nsw i32 0, %conv88
%cond1 = icmp ne i32 %arg1, 23
%v.8 = select i1 %cond1, i32 undef, i32 %sub89
- %1 = load i8, i8* null, align 1
+ %1 = load i8, ptr null, align 1
%conv108 = zext i8 %1 to i32
- %2 = load i8, i8* undef, align 1
+ %2 = load i8, ptr undef, align 1
%conv110 = zext i8 %2 to i32
%sub111 = sub nsw i32 %conv108, %conv110
%cmp112 = icmp slt i32 %sub111, 0
diff --git a/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll b/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll
index b00cc51d9842d..6728b9d4584c2 100644
--- a/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll
+++ b/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll
@@ -6,50 +6,49 @@
; CHECK: push {r4, r5, r6, r7, lr}
%0 = type opaque
-%struct.NSConstantString = type { i32*, i32, i8*, i32 }
+%struct.NSConstantString = type { ptr, i32, ptr, i32 }
-define i32 @asdf(i32 %a, i32 %b, i8** %c, i8* %d) personality i8* bitcast (i32 (...)* @__objc_personality_v0 to i8*) {
+define i32 @asdf(i32 %a, i32 %b, ptr %c, ptr %d) personality ptr @__objc_personality_v0 {
bb:
%tmp = alloca i32, align 4
%tmp1 = alloca i32, align 4
- %tmp2 = alloca i8*, align 4
+ %tmp2 = alloca ptr, align 4
%tmp3 = alloca i1
- %myException = alloca %0*, align 4
- %tmp4 = alloca i8*
+ %myException = alloca ptr, align 4
+ %tmp4 = alloca ptr
%tmp5 = alloca i32
- %exception = alloca %0*, align 4
- store i32 %a, i32* %tmp, align 4
- store i32 %b, i32* %tmp1, align 4
- store i8* %d, i8** %tmp2, align 4
- store i1 false, i1* %tmp3
- %tmp7 = load i8*, i8** %c
- %tmp10 = invoke %0* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %0* (i8*, i8*, %0*)*)(i8* %tmp7, i8* %d, %0* null)
+ %exception = alloca ptr, align 4
+ store i32 %a, ptr %tmp, align 4
+ store i32 %b, ptr %tmp1, align 4
+ store ptr %d, ptr %tmp2, align 4
+ store i1 false, ptr %tmp3
+ %tmp7 = load ptr, ptr %c
+ %tmp10 = invoke ptr @objc_msgSend(ptr %tmp7, ptr %d, ptr null)
to label %bb11 unwind label %bb15
bb11: ; preds = %bb
- store %0* %tmp10, %0** %myException, align 4
- %tmp12 = load %0*, %0** %myException, align 4
- %tmp13 = bitcast %0* %tmp12 to i8*
- invoke void @objc_exception_throw(i8* %tmp13) noreturn
+ store ptr %tmp10, ptr %myException, align 4
+ %tmp12 = load ptr, ptr %myException, align 4
+ invoke void @objc_exception_throw(ptr %tmp12) noreturn
to label %bb14 unwind label %bb15
bb14: ; preds = %bb11
unreachable
bb15: ; preds = %bb11, %bb
- %tmp16 = landingpad { i8*, i32 }
- catch i8* null
- %tmp17 = extractvalue { i8*, i32 } %tmp16, 0
- store i8* %tmp17, i8** %tmp4
- %tmp18 = extractvalue { i8*, i32 } %tmp16, 1
- store i32 %tmp18, i32* %tmp5
- store i1 true, i1* %tmp3
+ %tmp16 = landingpad { ptr, i32 }
+ catch ptr null
+ %tmp17 = extractvalue { ptr, i32 } %tmp16, 0
+ store ptr %tmp17, ptr %tmp4
+ %tmp18 = extractvalue { ptr, i32 } %tmp16, 1
+ store i32 %tmp18, ptr %tmp5
+ store i1 true, ptr %tmp3
br label %bb56
bb56:
unreachable
}
-declare i8* @objc_msgSend(i8*, i8*, ...) nonlazybind
+declare ptr @objc_msgSend(ptr, ptr, ...) nonlazybind
declare i32 @__objc_personality_v0(...)
-declare void @objc_exception_throw(i8*)
+declare void @objc_exception_throw(ptr)
diff --git a/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll b/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll
index 3f827f8e702f8..0fe855eea57f7 100644
--- a/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll
+++ b/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll
@@ -3,7 +3,7 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7-none-linux-gnueabi"
-define arm_aapcs_vfpcc void @foo(i8* nocapture %arg) nounwind uwtable align 2 {
+define arm_aapcs_vfpcc void @foo(ptr nocapture %arg) nounwind uwtable align 2 {
bb:
br i1 undef, label %bb1, label %bb2
@@ -18,7 +18,7 @@ bb3: ; preds = %bb4, %bb2
br i1 %tmp, label %bb4, label %bb67
bb4: ; preds = %bb3
- %tmp5 = load <4 x i32>, <4 x i32>* undef, align 16
+ %tmp5 = load <4 x i32>, ptr undef, align 16
%tmp6 = and <4 x i32> %tmp5, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>
%tmp7 = or <4 x i32> %tmp6, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
%tmp8 = bitcast <4 x i32> %tmp7 to <4 x float>
@@ -36,14 +36,14 @@ bb4: ; preds = %bb3
%tmp20 = fmul <4 x float> %tmp19, %tmp18
%tmp21 = fmul <4 x float> %tmp20, zeroinitializer
%tmp22 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp21, <4 x float> undef) nounwind
- call arm_aapcs_vfpcc void @bar(i8* null, i8* undef, <4 x i32>* undef, [2 x i64] zeroinitializer) nounwind
+ call arm_aapcs_vfpcc void @bar(ptr null, ptr undef, ptr undef, [2 x i64] zeroinitializer) nounwind
%tmp23 = bitcast <4 x float> %tmp22 to i128
%tmp24 = trunc i128 %tmp23 to i64
%tmp25 = insertvalue [2 x i64] undef, i64 %tmp24, 0
%tmp26 = insertvalue [2 x i64] %tmp25, i64 0, 1
- %tmp27 = load float, float* undef, align 4
+ %tmp27 = load float, ptr undef, align 4
%tmp28 = insertelement <4 x float> undef, float %tmp27, i32 3
- %tmp29 = load <4 x i32>, <4 x i32>* undef, align 16
+ %tmp29 = load <4 x i32>, ptr undef, align 16
%tmp30 = and <4 x i32> %tmp29, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>
%tmp31 = or <4 x i32> %tmp30, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
%tmp32 = bitcast <4 x i32> %tmp31 to <4 x float>
@@ -51,11 +51,11 @@ bb4: ; preds = %bb3
%tmp34 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> undef, <4 x float> %tmp28) nounwind
%tmp35 = fmul <4 x float> %tmp34, undef
%tmp36 = fmul <4 x float> %tmp35, undef
- %tmp37 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind
- %tmp38 = load float, float* undef, align 4
+ %tmp37 = call arm_aapcs_vfpcc ptr undef(ptr undef) nounwind
+ %tmp38 = load float, ptr undef, align 4
%tmp39 = insertelement <2 x float> undef, float %tmp38, i32 0
- %tmp40 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind
- %tmp41 = load float, float* undef, align 4
+ %tmp40 = call arm_aapcs_vfpcc ptr undef(ptr undef) nounwind
+ %tmp41 = load float, ptr undef, align 4
%tmp42 = insertelement <4 x float> undef, float %tmp41, i32 3
%tmp43 = shufflevector <2 x float> %tmp39, <2 x float> undef, <4 x i32> zeroinitializer
%tmp44 = fmul <4 x float> %tmp33, %tmp43
@@ -63,11 +63,11 @@ bb4: ; preds = %bb3
%tmp46 = fsub <4 x float> %tmp45, undef
%tmp47 = fmul <4 x float> %tmp46, %tmp36
%tmp48 = fadd <4 x float> undef, %tmp47
- %tmp49 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind
- %tmp50 = load float, float* undef, align 4
+ %tmp49 = call arm_aapcs_vfpcc ptr undef(ptr undef) nounwind
+ %tmp50 = load float, ptr undef, align 4
%tmp51 = insertelement <4 x float> undef, float %tmp50, i32 3
- %tmp52 = call arm_aapcs_vfpcc float* null(i8* undef) nounwind
- %tmp54 = load float, float* %tmp52, align 4
+ %tmp52 = call arm_aapcs_vfpcc ptr null(ptr undef) nounwind
+ %tmp54 = load float, ptr %tmp52, align 4
%tmp55 = insertelement <4 x float> undef, float %tmp54, i32 3
%tmp56 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %tmp22
%tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounwind
@@ -76,23 +76,23 @@ bb4: ; preds = %bb3
%tmp60 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %tmp58
%tmp61 = fmul <4 x float> %tmp59, %tmp60
%tmp62 = fadd <4 x float> %tmp48, %tmp61
- call arm_aapcs_vfpcc void @baz(i8* undef, i8* undef, [2 x i64] %tmp26, <4 x i32>* undef)
+ call arm_aapcs_vfpcc void @baz(ptr undef, ptr undef, [2 x i64] %tmp26, ptr undef)
%tmp63 = bitcast <4 x float> %tmp62 to i128
%tmp64 = lshr i128 %tmp63, 64
%tmp65 = trunc i128 %tmp64 to i64
%tmp66 = insertvalue [2 x i64] zeroinitializer, i64 %tmp65, 1
- call arm_aapcs_vfpcc void @quux(i8* undef, i8* undef, [2 x i64] undef, i8* undef, [2 x i64] %tmp66, i8* undef, i8* undef, [2 x i64] %tmp26, [2 x i64] %tmp15, <4 x i32>* undef)
+ call arm_aapcs_vfpcc void @quux(ptr undef, ptr undef, [2 x i64] undef, ptr undef, [2 x i64] %tmp66, ptr undef, ptr undef, [2 x i64] %tmp26, [2 x i64] %tmp15, ptr undef)
br label %bb3
bb67: ; preds = %bb3
ret void
}
-declare arm_aapcs_vfpcc void @bar(i8*, i8*, <4 x i32>*, [2 x i64])
+declare arm_aapcs_vfpcc void @bar(ptr, ptr, ptr, [2 x i64])
-declare arm_aapcs_vfpcc void @baz(i8*, i8* nocapture, [2 x i64], <4 x i32>* nocapture) nounwind uwtable inlinehint align 2
+declare arm_aapcs_vfpcc void @baz(ptr, ptr nocapture, [2 x i64], ptr nocapture) nounwind uwtable inlinehint align 2
-declare arm_aapcs_vfpcc void @quux(i8*, i8*, [2 x i64], i8* nocapture, [2 x i64], i8* nocapture, i8* nocapture, [2 x i64], [2 x i64], <4 x i32>* nocapture) nounwind uwtable inlinehint align 2
+declare arm_aapcs_vfpcc void @quux(ptr, ptr, [2 x i64], ptr nocapture, [2 x i64], ptr nocapture, ptr nocapture, [2 x i64], [2 x i64], ptr nocapture) nounwind uwtable inlinehint align 2
declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
diff --git a/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll b/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll
index f622ceb584e6e..c01a35ad65887 100644
--- a/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll
+++ b/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll
@@ -5,9 +5,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
target triple = "armv7-none-linux-eabi"
; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE.
-define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 {
+define arm_aapcs_vfpcc void @foo(ptr nocapture %arg, ptr %arg1) nounwind align 2 {
bb:
- %tmp = load <2 x float>, <2 x float>* undef, align 8
+ %tmp = load <2 x float>, ptr undef, align 8
%tmp2 = extractelement <2 x float> %tmp, i32 0
%tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0
%tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1
@@ -25,7 +25,7 @@ bb:
%tmp16 = shufflevector <2 x i64> %tmp15, <2 x i64> undef, <1 x i32> zeroinitializer
%tmp17 = bitcast <1 x i64> %tmp16 to <2 x float>
%tmp18 = extractelement <2 x float> %tmp17, i32 0
- tail call arm_aapcs_vfpcc void @bar(i8* undef, float %tmp18, float undef, float 0.000000e+00) nounwind
+ tail call arm_aapcs_vfpcc void @bar(ptr undef, float %tmp18, float undef, float 0.000000e+00) nounwind
%tmp19 = bitcast <4 x float> %tmp10 to <2 x i64>
%tmp20 = shufflevector <2 x i64> %tmp19, <2 x i64> undef, <1 x i32> zeroinitializer
%tmp21 = bitcast <1 x i64> %tmp20 to <2 x float>
@@ -34,7 +34,7 @@ bb:
%tmp24 = shufflevector <2 x i64> %tmp23, <2 x i64> undef, <1 x i32> zeroinitializer
%tmp25 = bitcast <1 x i64> %tmp24 to <2 x float>
%tmp26 = extractelement <2 x float> %tmp25, i32 0
- tail call arm_aapcs_vfpcc void @bar(i8* undef, float undef, float %tmp26, float 0.000000e+00) nounwind
+ tail call arm_aapcs_vfpcc void @bar(ptr undef, float undef, float %tmp26, float 0.000000e+00) nounwind
ret void
}
@@ -52,8 +52,8 @@ cond.end295: ; preds = %entry
%shuffle.i35.i.i = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer
%shuffle.i34.i.i = shufflevector <1 x i64> %shuffle.i36.i.i, <1 x i64> %shuffle.i35.i.i, <2 x i32> <i32 0, i32 1>
%2 = bitcast <2 x i64> %shuffle.i34.i.i to <4 x float>
- tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* undef, <4 x float> %0, i32 4) nounwind
- tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* undef, <4 x float> %2, i32 4) nounwind
+ tail call void @llvm.arm.neon.vst1.p0.v4f32(ptr undef, <4 x float> %0, i32 4) nounwind
+ tail call void @llvm.arm.neon.vst1.p0.v4f32(ptr undef, <4 x float> %2, i32 4) nounwind
unreachable
for.end: ; preds = %entry
@@ -61,12 +61,12 @@ for.end: ; preds = %entry
}
; Check that pseudo-expansion preserves <undef> flags.
-define void @foo3(i8* %p) nounwind ssp {
+define void @foo3(ptr %p) nounwind ssp {
entry:
- tail call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %p, <4 x float> undef, <4 x float> undef, i32 4)
+ tail call void @llvm.arm.neon.vst2.p0.v4f32(ptr %p, <4 x float> undef, <4 x float> undef, i32 4)
ret void
}
-declare arm_aapcs_vfpcc void @bar(i8*, float, float, float)
-declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind
-declare void @llvm.arm.neon.vst2.p0i8.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind
+declare arm_aapcs_vfpcc void @bar(ptr, float, float, float)
+declare void @llvm.arm.neon.vst1.p0.v4f32(ptr, <4 x float>, i32) nounwind
+declare void @llvm.arm.neon.vst2.p0.v4f32(ptr, <4 x float>, <4 x float>, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll b/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll
index 0ee79086e9fff..e0f554cf6e056 100644
--- a/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll
+++ b/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll
@@ -6,7 +6,7 @@ target triple = "armv7-none-linux-gnueabi"
; This test case exercises the MachineCopyPropagation pass by disabling the
; RegisterCoalescer.
-define arm_aapcs_vfpcc void @foo(i8* %arg) nounwind uwtable align 2 {
+define arm_aapcs_vfpcc void @foo(ptr %arg) nounwind uwtable align 2 {
bb:
br i1 undef, label %bb1, label %bb2
@@ -56,9 +56,9 @@ bb3: ; preds = %bb2
%tmp39 = shufflevector <2 x i64> %tmp38, <2 x i64> undef, <1 x i32> zeroinitializer
%tmp40 = bitcast <1 x i64> %tmp39 to <2 x float>
%tmp41 = shufflevector <2 x float> %tmp40, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
- %tmp42 = load <4 x float>, <4 x float>* null, align 16
+ %tmp42 = load <4 x float>, ptr null, align 16
%tmp43 = fmul <4 x float> %tmp42, %tmp41
- %tmp44 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp44 = load <4 x float>, ptr undef, align 16
%tmp45 = fadd <4 x float> undef, %tmp43
%tmp46 = fadd <4 x float> undef, %tmp45
%tmp47 = bitcast <4 x float> %tmp36 to <2 x i64>
@@ -76,8 +76,8 @@ bb3: ; preds = %bb2
%tmp59 = fmul <4 x float> undef, %tmp58
%tmp60 = fadd <4 x float> %tmp59, undef
%tmp61 = fadd <4 x float> %tmp60, zeroinitializer
- %tmp62 = load void (i8*, i8*)*, void (i8*, i8*)** undef, align 4
- call arm_aapcs_vfpcc void %tmp62(i8* sret(i8) undef, i8* undef) nounwind
+ %tmp62 = load ptr, ptr undef, align 4
+ call arm_aapcs_vfpcc void %tmp62(ptr sret(i8) undef, ptr undef) nounwind
%tmp63 = bitcast <4 x float> %tmp46 to i128
%tmp64 = bitcast <4 x float> %tmp54 to i128
%tmp65 = bitcast <4 x float> %tmp61 to i128
@@ -93,10 +93,9 @@ bb3: ; preds = %bb2
%tmp75 = insertvalue [8 x i64] %tmp74, i64 undef, 5
%tmp76 = insertvalue [8 x i64] %tmp75, i64 undef, 6
%tmp77 = insertvalue [8 x i64] %tmp76, i64 undef, 7
- call arm_aapcs_vfpcc void @bar(i8* sret(i8) null, [8 x i64] %tmp77) nounwind
- %tmp78 = call arm_aapcs_vfpcc i8* null(i8* null) nounwind
- %tmp79 = bitcast i8* %tmp78 to i512*
- %tmp80 = load i512, i512* %tmp79, align 16
+ call arm_aapcs_vfpcc void @bar(ptr sret(i8) null, [8 x i64] %tmp77) nounwind
+ %tmp78 = call arm_aapcs_vfpcc ptr null(ptr null) nounwind
+ %tmp80 = load i512, ptr %tmp78, align 16
%tmp81 = lshr i512 %tmp80, 128
%tmp82 = trunc i512 %tmp80 to i128
%tmp83 = trunc i512 %tmp81 to i128
@@ -108,11 +107,11 @@ bb3: ; preds = %bb2
%tmp89 = fmul <4 x float> undef, %tmp88
%tmp90 = fadd <4 x float> %tmp89, undef
%tmp91 = fadd <4 x float> undef, %tmp90
- store <4 x float> %tmp91, <4 x float>* undef, align 16
+ store <4 x float> %tmp91, ptr undef, align 16
unreachable
bb92: ; preds = %bb2
ret void
}
-declare arm_aapcs_vfpcc void @bar(i8* noalias nocapture sret(i8), [8 x i64]) nounwind uwtable inlinehint
+declare arm_aapcs_vfpcc void @bar(ptr noalias nocapture sret(i8), [8 x i64]) nounwind uwtable inlinehint
diff --git a/llvm/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll b/llvm/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll
index b0411384b96ae..3838bceb458f3 100644
--- a/llvm/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll
+++ b/llvm/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll
@@ -10,7 +10,7 @@ target triple = "armv7-none-linux-gnueabi"
@foo = external global %0, align 16
define arm_aapcs_vfpcc void @bar(float, i1 zeroext, i1 zeroext) nounwind {
- %4 = load <4 x float>, <4 x float>* getelementptr inbounds (%0, %0* @foo, i32 0, i32 0), align 16
+ %4 = load <4 x float>, ptr @foo, align 16
%5 = extractelement <4 x float> %4, i32 0
%6 = extractelement <4 x float> %4, i32 1
%7 = extractelement <4 x float> %4, i32 2
@@ -18,9 +18,9 @@ define arm_aapcs_vfpcc void @bar(float, i1 zeroext, i1 zeroext) nounwind {
%9 = insertelement <4 x float> %8, float %6, i32 1
%10 = insertelement <4 x float> %9, float %7, i32 2
%11 = insertelement <4 x float> %10, float 0.000000e+00, i32 3
- store <4 x float> %11, <4 x float>* undef, align 16
- call arm_aapcs_vfpcc void @baz(%1* undef, float 0.000000e+00) nounwind
+ store <4 x float> %11, ptr undef, align 16
+ call arm_aapcs_vfpcc void @baz(ptr undef, float 0.000000e+00) nounwind
ret void
}
-declare arm_aapcs_vfpcc void @baz(%1*, float)
+declare arm_aapcs_vfpcc void @baz(ptr, float)
diff --git a/llvm/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll b/llvm/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll
index 6fb760c4bcc7e..6e8f1f2208e2b 100644
--- a/llvm/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll
+++ b/llvm/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll
@@ -4,12 +4,12 @@
; DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) to
; (i16 load $addr+c*sizeof(i16)). It should have issued an extload instead. i.e.
; (i32 extload $addr+c*sizeof(i16)
-define void @test_hi_short3(<3 x i16> * nocapture %srcA, <2 x i16> * nocapture %dst) nounwind {
+define void @test_hi_short3(ptr nocapture %srcA, ptr nocapture %dst) nounwind {
entry:
; CHECK: vst1.32
- %0 = load <3 x i16> , <3 x i16> * %srcA, align 8
+ %0 = load <3 x i16> , ptr %srcA, align 8
%1 = shufflevector <3 x i16> %0, <3 x i16> undef, <2 x i32> <i32 2, i32 undef>
- store <2 x i16> %1, <2 x i16> * %dst, align 4
+ store <2 x i16> %1, ptr %dst, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll b/llvm/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll
index 0843fdc4e75e9..d55f269c1aa78 100644
--- a/llvm/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll
+++ b/llvm/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll
@@ -9,11 +9,11 @@ define arm_aapcs_vfpcc void @foo() nounwind align 2 {
; <label>:1 ; preds = %0
%2 = shufflevector <1 x i64> zeroinitializer, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
%3 = bitcast <2 x i64> %2 to <4 x float>
- store <4 x float> zeroinitializer, <4 x float>* undef, align 16
- store <4 x float> zeroinitializer, <4 x float>* undef, align 16
- store <4 x float> %3, <4 x float>* undef, align 16
+ store <4 x float> zeroinitializer, ptr undef, align 16
+ store <4 x float> zeroinitializer, ptr undef, align 16
+ store <4 x float> %3, ptr undef, align 16
%4 = insertelement <4 x float> %3, float 8.000000e+00, i32 2
- store <4 x float> %4, <4 x float>* undef, align 16
+ store <4 x float> %4, ptr undef, align 16
unreachable
; <label>:5 ; preds = %0
diff --git a/llvm/test/CodeGen/ARM/2012-04-10-DAGCombine.ll b/llvm/test/CodeGen/ARM/2012-04-10-DAGCombine.ll
index 9b71be23b7ebc..80c1968c85743 100644
--- a/llvm/test/CodeGen/ARM/2012-04-10-DAGCombine.ll
+++ b/llvm/test/CodeGen/ARM/2012-04-10-DAGCombine.ll
@@ -20,7 +20,7 @@ bb5: ; preds = %bb4
%tmp15 = shufflevector <2 x float> %tmp14, <2 x float> undef, <4 x i32> zeroinitializer
%tmp16 = fmul <4 x float> zeroinitializer, %tmp15
%tmp17 = fadd <4 x float> %tmp16, %arg
- store <4 x float> %tmp17, <4 x float>* undef, align 8
+ store <4 x float> %tmp17, ptr undef, align 8
br label %bb18
bb18: ; preds = %bb5, %bb4
diff --git a/llvm/test/CodeGen/ARM/2012-04-24-SplitEHCriticalEdge.ll b/llvm/test/CodeGen/ARM/2012-04-24-SplitEHCriticalEdge.ll
index 4ddc7284f58e5..919b2863b1169 100644
--- a/llvm/test/CodeGen/ARM/2012-04-24-SplitEHCriticalEdge.ll
+++ b/llvm/test/CodeGen/ARM/2012-04-24-SplitEHCriticalEdge.ll
@@ -4,39 +4,39 @@
; rdar://11300144
%0 = type opaque
-%class.FunctionInterpreter.3.15.31 = type { %class.Parser.1.13.29, %class.Parser.1.13.29*, %struct.ParserVariable.2.14.30*, i32 }
-%class.Parser.1.13.29 = type { i32 (...)**, %class.Parser.1.13.29* }
+%class.FunctionInterpreter.3.15.31 = type { %class.Parser.1.13.29, ptr, ptr, i32 }
+%class.Parser.1.13.29 = type { ptr, ptr }
%struct.ParserVariable.2.14.30 = type opaque
%struct.ParseErrorMsg.0.12.28 = type { i32, i32, i32 }
- at _ZTI13ParseErrorMsg = external hidden unnamed_addr constant { i8*, i8* }
+ at _ZTI13ParseErrorMsg = external hidden unnamed_addr constant { ptr, ptr }
@"OBJC_IVAR_$_MUMathExpressionDoubleBased.mInterpreter" = external hidden global i32, section "__DATA, __objc_ivar", align 4
-@"\01L_OBJC_SELECTOR_REFERENCES_14" = external hidden global i8*, section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
+@"\01L_OBJC_SELECTOR_REFERENCES_14" = external hidden global ptr, section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
-declare i8* @objc_msgSend(i8*, i8*, ...)
+declare ptr @objc_msgSend(ptr, ptr, ...)
-declare i32 @llvm.eh.typeid.for(i8*) nounwind readnone
+declare i32 @llvm.eh.typeid.for(ptr) nounwind readnone
-declare i8* @__cxa_begin_catch(i8*)
+declare ptr @__cxa_begin_catch(ptr)
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
declare void @__cxa_end_catch()
declare void @_ZSt9terminatev()
-define hidden double @t(%0* %self, i8* nocapture %_cmd) optsize ssp personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
+define hidden double @t(ptr %self, ptr nocapture %_cmd) optsize ssp personality ptr @__gxx_personality_sj0 {
entry:
- %call = invoke double undef(%class.FunctionInterpreter.3.15.31* undef) optsize
+ %call = invoke double undef(ptr undef) optsize
to label %try.cont unwind label %lpad
lpad: ; preds = %entry
- %0 = landingpad { i8*, i32 }
- catch i8* bitcast ({ i8*, i8* }* @_ZTI13ParseErrorMsg to i8*)
+ %0 = landingpad { ptr, i32 }
+ catch ptr @_ZTI13ParseErrorMsg
br i1 undef, label %catch, label %eh.resume
catch: ; preds = %lpad
- invoke void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %struct.ParseErrorMsg.0.12.28*)*)(i8* undef, i8* undef, %struct.ParseErrorMsg.0.12.28* undef) optsize
+ invoke void @objc_msgSend(ptr undef, ptr undef, ptr undef) optsize
to label %invoke.cont2 unwind label %lpad1
invoke.cont2: ; preds = %catch
@@ -47,17 +47,17 @@ try.cont: ; preds = %invoke.cont2, %entr
ret double %value.0
lpad1: ; preds = %catch
- %1 = landingpad { i8*, i32 }
+ %1 = landingpad { ptr, i32 }
cleanup
invoke void @__cxa_end_catch()
to label %eh.resume unwind label %terminate.lpad
eh.resume: ; preds = %lpad1, %lpad
- resume { i8*, i32 } undef
+ resume { ptr, i32 } undef
terminate.lpad: ; preds = %lpad1
- %2 = landingpad { i8*, i32 }
- catch i8* null
+ %2 = landingpad { ptr, i32 }
+ catch ptr null
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll b/llvm/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll
index 606af47a3d8ee..cf0beeff223e8 100644
--- a/llvm/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll
+++ b/llvm/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll
@@ -1,14 +1,13 @@
; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s
; <rdar://problem/10451892>
-define void @f(i32 %x, i32* %p) nounwind ssp {
+define void @f(i32 %x, ptr %p) nounwind ssp {
entry:
; CHECK-NOT: vdup.32
%vecinit.i = insertelement <2 x i32> undef, i32 %x, i32 0
%vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %x, i32 1
- %0 = bitcast i32* %p to i8*
- tail call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %0, <2 x i32> %vecinit1.i, i32 4)
+ tail call void @llvm.arm.neon.vst1.p0.v2i32(ptr %p, <2 x i32> %vecinit1.i, i32 4)
ret void
}
-declare void @llvm.arm.neon.vst1.p0i8.v2i32(i8*, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v2i32(ptr, <2 x i32>, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/2012-05-29-TailDupBug.ll b/llvm/test/CodeGen/ARM/2012-05-29-TailDupBug.ll
index 1a57f04f64582..ab3d26d322126 100644
--- a/llvm/test/CodeGen/ARM/2012-05-29-TailDupBug.ll
+++ b/llvm/test/CodeGen/ARM/2012-05-29-TailDupBug.ll
@@ -5,7 +5,7 @@
%struct.__CFString.2 = type opaque
-declare void @CFRelease(i8*)
+declare void @CFRelease(ptr)
define hidden fastcc i32 @t() ssp {
entry:
@@ -108,7 +108,7 @@ for.cond57.preheader.i: ; preds = %for.cond16.preheade
br label %cleanup.i
for.body18.i: ; preds = %for.cond16.preheader.i
- store i16 0, i16* undef, align 2
+ store i16 0, ptr undef, align 2
br label %while.body.i
while.body.i: ; preds = %while.body.i, %for.body18.i
@@ -119,17 +119,16 @@ cleanup.i: ; preds = %for.cond57.preheade
__CFHyphenationGetHyphensForString.exit: ; preds = %cleanup.i, %if.then50
%retval.1.i = phi i32 [ 0, %cleanup.i ], [ -1, %if.then50 ]
- %phitmp = bitcast %struct.__CFString.2* null to i8*
br label %if.end68
cleanup.thread: ; preds = %if.end35, %land.lhs.true, %if.end20.i, %if.then4.i
- call void @llvm.stackrestore(i8* null)
+ call void @llvm.stackrestore(ptr null)
br label %return
if.end68: ; preds = %__CFHyphenationGetHyphensForString.exit, %__CFHyphenationPullTokenizer.exit
%hyphenCount.2 = phi i32 [ %retval.1.i, %__CFHyphenationGetHyphensForString.exit ], [ 0, %__CFHyphenationPullTokenizer.exit ]
- %_token.1 = phi i8* [ %phitmp, %__CFHyphenationGetHyphensForString.exit ], [ undef, %__CFHyphenationPullTokenizer.exit ]
- call void @CFRelease(i8* %_token.1)
+ %_token.1 = phi ptr [ null, %__CFHyphenationGetHyphensForString.exit ], [ undef, %__CFHyphenationPullTokenizer.exit ]
+ call void @CFRelease(ptr %_token.1)
br label %return
return: ; preds = %if.end68, %cleanup.thread, %CFStringIsHyphenationAvailableForLocale.exit, %entry
@@ -137,4 +136,4 @@ return: ; preds = %if.end68, %cleanup.
ret i32 %retval.1
}
-declare void @llvm.stackrestore(i8*) nounwind
+declare void @llvm.stackrestore(ptr) nounwind
diff --git a/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll b/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll
index 208cf8db99c33..78ac5e6b44fd6 100644
--- a/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll
+++ b/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll
@@ -24,16 +24,16 @@
; CHECK: SU(2): Ord Latency=1
; CHECK-NOT: SU({{.*}}): Ord
; CHECK: Successors:
-define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind {
+define i32 @f1(ptr nocapture %p1, ptr nocapture %p2) nounwind {
entry:
- store volatile i32 65540, i32* %p1, align 4
- %0 = load volatile i32, i32* %p2, align 4
+ store volatile i32 65540, ptr %p1, align 4
+ %0 = load volatile i32, ptr %p2, align 4
ret i32 %0
}
-define i32 @f2(i32* nocapture %p1, i32* nocapture %p2) nounwind {
+define i32 @f2(ptr nocapture %p1, ptr nocapture %p2) nounwind {
entry:
- store i32 65540, i32* %p1, align 4
- %0 = load i32, i32* %p2, align 4
+ store i32 65540, ptr %p1, align 4
+ %0 = load i32, ptr %p2, align 4
ret i32 %0
}
diff --git a/llvm/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll b/llvm/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll
index 6e0b828ad24f8..feae57b4b812e 100644
--- a/llvm/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll
+++ b/llvm/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll
@@ -129,7 +129,7 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable
%45 = fmul <4 x float> undef, undef
%46 = fmul <4 x float> %45, %43
%47 = fmul <4 x float> undef, %44
- %48 = load <4 x float>, <4 x float>* undef, align 8
+ %48 = load <4 x float>, ptr undef, align 8
%49 = bitcast <4 x float> %48 to <2 x i64>
%50 = shufflevector <2 x i64> %49, <2 x i64> undef, <1 x i32> <i32 1>
%51 = bitcast <1 x i64> %50 to <2 x float>
@@ -145,10 +145,10 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable
%61 = fmul <4 x float> %59, %60
%62 = fmul <4 x float> %61, <float 6.000000e+01, float 6.000000e+01, float 6.000000e+01, float 6.000000e+01>
%63 = fadd <4 x float> %47, %62
- store <4 x float> %46, <4 x float>* undef, align 8
- call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind
- call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind
- store <4 x float> %63, <4 x float>* undef, align 8
+ store <4 x float> %46, ptr undef, align 8
+ call arm_aapcs_vfpcc void @bar(ptr undef, float 0.000000e+00) nounwind
+ call arm_aapcs_vfpcc void @bar(ptr undef, float 0.000000e+00) nounwind
+ store <4 x float> %63, ptr undef, align 8
unreachable
; <label>:64 ; preds = %41, %40
@@ -167,6 +167,6 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable
ret void
}
-declare arm_aapcs_vfpcc void @bar(%0*, float)
+declare arm_aapcs_vfpcc void @bar(ptr, float)
!0 = !{!"branch_weights", i32 64, i32 4}
diff --git a/llvm/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll b/llvm/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll
index 576dff4d001e5..130cbe6d99ca2 100644
--- a/llvm/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll
+++ b/llvm/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll
@@ -6,7 +6,7 @@ target triple = "armv7-none-linux-gnueabi"
define void @test_hi_char8() noinline {
entry:
- %0 = load <4 x i8>, <4 x i8>* undef, align 1
- store <4 x i8> %0, <4 x i8>* null, align 4
+ %0 = load <4 x i8>, ptr undef, align 1
+ store <4 x i8> %0, ptr null, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2012-08-09-neon-extload.ll b/llvm/test/CodeGen/ARM/2012-08-09-neon-extload.ll
index 285a431a6ecf6..aaf80097fb447 100644
--- a/llvm/test/CodeGen/ARM/2012-08-09-neon-extload.ll
+++ b/llvm/test/CodeGen/ARM/2012-08-09-neon-extload.ll
@@ -14,10 +14,10 @@
define void @test_v2i8tov2i32() {
; CHECK-LABEL: test_v2i8tov2i32:
- %i8val = load <2 x i8>, <2 x i8>* @var_v2i8
+ %i8val = load <2 x i8>, ptr @var_v2i8
%i32val = sext <2 x i8> %i8val to <2 x i32>
- store <2 x i32> %i32val, <2 x i32>* @var_v2i32
+ store <2 x i32> %i32val, ptr @var_v2i32
; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:16]
; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}}
@@ -28,17 +28,17 @@ define void @test_v2i8tov2i32() {
define void @test_v2i8tov2i64() {
; CHECK-LABEL: test_v2i8tov2i64:
- %i8val = load <2 x i8>, <2 x i8>* @var_v2i8
+ %i8val = load <2 x i8>, ptr @var_v2i8
%i64val = sext <2 x i8> %i8val to <2 x i64>
- store <2 x i64> %i64val, <2 x i64>* @var_v2i64
+ store <2 x i64> %i64val, ptr @var_v2i64
; CHECK: vld1.16 {d{{[0-9]+}}[0]}, [{{r[0-9]+}}:16]
; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}}
; CHECK: vmovl.s32 {{q[0-9]+}}, {{d[0-9]+}}
; %i64val = sext <2 x i8> %i8val to <2 x i64>
-; store <2 x i64> %i64val, <2 x i64>* @var_v2i64
+; store <2 x i64> %i64val, ptr @var_v2i64
ret void
}
@@ -46,10 +46,10 @@ define void @test_v2i8tov2i64() {
define void @test_v4i8tov4i16() {
; CHECK-LABEL: test_v4i8tov4i16:
- %i8val = load <4 x i8>, <4 x i8>* @var_v4i8
+ %i8val = load <4 x i8>, ptr @var_v4i8
%i16val = sext <4 x i8> %i8val to <4 x i16>
- store <4 x i16> %i16val, <4 x i16>* @var_v4i16
+ store <4 x i16> %i16val, ptr @var_v4i16
; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
; CHECK-NOT: vmovl.s16
@@ -61,10 +61,10 @@ define void @test_v4i8tov4i16() {
define void @test_v4i8tov4i32() {
; CHECK-LABEL: test_v4i8tov4i32:
- %i8val = load <4 x i8>, <4 x i8>* @var_v4i8
+ %i8val = load <4 x i8>, ptr @var_v4i8
%i16val = sext <4 x i8> %i8val to <4 x i32>
- store <4 x i32> %i16val, <4 x i32>* @var_v4i32
+ store <4 x i32> %i16val, ptr @var_v4i32
; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}}
@@ -75,10 +75,10 @@ define void @test_v4i8tov4i32() {
define void @test_v2i16tov2i32() {
; CHECK-LABEL: test_v2i16tov2i32:
- %i16val = load <2 x i16>, <2 x i16>* @var_v2i16
+ %i16val = load <2 x i16>, ptr @var_v2i16
%i32val = sext <2 x i16> %i16val to <2 x i32>
- store <2 x i32> %i32val, <2 x i32>* @var_v2i32
+ store <2 x i32> %i32val, ptr @var_v2i32
; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
; CHECK-NOT: vmovl
@@ -90,10 +90,10 @@ define void @test_v2i16tov2i32() {
define void @test_v2i16tov2i64() {
; CHECK-LABEL: test_v2i16tov2i64:
- %i16val = load <2 x i16>, <2 x i16>* @var_v2i16
+ %i16val = load <2 x i16>, ptr @var_v2i16
%i64val = sext <2 x i16> %i16val to <2 x i64>
- store <2 x i64> %i64val, <2 x i64>* @var_v2i64
+ store <2 x i64> %i64val, ptr @var_v2i64
; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
; CHECK: vmovl.s32 {{q[0-9]+}}, d[[LOAD]]
diff --git a/llvm/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll b/llvm/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
index 3a851d68f0a4f..1725c40e6e98b 100644
--- a/llvm/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
+++ b/llvm/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
@@ -12,40 +12,40 @@
; Vector x Constant
; v4i8
;
-define void @sextload_v4i8_c(<4 x i8>* %v) nounwind {
+define void @sextload_v4i8_c(ptr %v) nounwind {
;CHECK-LABEL: sextload_v4i8_c:
entry:
- %0 = load <4 x i8>, <4 x i8>* %v, align 8
+ %0 = load <4 x i8>, ptr %v, align 8
%v0 = sext <4 x i8> %0 to <4 x i32>
;CHECK: vmull
%v1 = mul <4 x i32> %v0, <i32 3, i32 3, i32 3, i32 3>
- store <4 x i32> %v1, <4 x i32>* undef, align 8
+ store <4 x i32> %v1, ptr undef, align 8
ret void;
}
; v2i8
;
-define void @sextload_v2i8_c(<2 x i8>* %v) nounwind {
+define void @sextload_v2i8_c(ptr %v) nounwind {
;CHECK-LABEL: sextload_v2i8_c:
entry:
- %0 = load <2 x i8>, <2 x i8>* %v, align 8
+ %0 = load <2 x i8>, ptr %v, align 8
%v0 = sext <2 x i8> %0 to <2 x i64>
;CHECK: vmull
%v1 = mul <2 x i64> %v0, <i64 3, i64 3>
- store <2 x i64> %v1, <2 x i64>* undef, align 8
+ store <2 x i64> %v1, ptr undef, align 8
ret void;
}
; v2i16
;
-define void @sextload_v2i16_c(<2 x i16>* %v) nounwind {
+define void @sextload_v2i16_c(ptr %v) nounwind {
;CHECK-LABEL: sextload_v2i16_c:
entry:
- %0 = load <2 x i16>, <2 x i16>* %v, align 8
+ %0 = load <2 x i16>, ptr %v, align 8
%v0 = sext <2 x i16> %0 to <2 x i64>
;CHECK: vmull
%v1 = mul <2 x i64> %v0, <i64 3, i64 3>
- store <2 x i64> %v1, <2 x i64>* undef, align 8
+ store <2 x i64> %v1, ptr undef, align 8
ret void;
}
@@ -53,49 +53,49 @@ entry:
; Vector x Vector
; v4i8
;
-define void @sextload_v4i8_v(<4 x i8>* %v, <4 x i8>* %p) nounwind {
+define void @sextload_v4i8_v(ptr %v, ptr %p) nounwind {
;CHECK-LABEL: sextload_v4i8_v:
entry:
- %0 = load <4 x i8>, <4 x i8>* %v, align 8
+ %0 = load <4 x i8>, ptr %v, align 8
%v0 = sext <4 x i8> %0 to <4 x i32>
- %1 = load <4 x i8>, <4 x i8>* %p, align 8
+ %1 = load <4 x i8>, ptr %p, align 8
%v2 = sext <4 x i8> %1 to <4 x i32>
;CHECK: vmull
%v1 = mul <4 x i32> %v0, %v2
- store <4 x i32> %v1, <4 x i32>* undef, align 8
+ store <4 x i32> %v1, ptr undef, align 8
ret void;
}
; v2i8
;
-define void @sextload_v2i8_v(<2 x i8>* %v, <2 x i8>* %p) nounwind {
+define void @sextload_v2i8_v(ptr %v, ptr %p) nounwind {
;CHECK-LABEL: sextload_v2i8_v:
entry:
- %0 = load <2 x i8>, <2 x i8>* %v, align 8
+ %0 = load <2 x i8>, ptr %v, align 8
%v0 = sext <2 x i8> %0 to <2 x i64>
- %1 = load <2 x i8>, <2 x i8>* %p, align 8
+ %1 = load <2 x i8>, ptr %p, align 8
%v2 = sext <2 x i8> %1 to <2 x i64>
;CHECK: vmull
%v1 = mul <2 x i64> %v0, %v2
- store <2 x i64> %v1, <2 x i64>* undef, align 8
+ store <2 x i64> %v1, ptr undef, align 8
ret void;
}
; v2i16
;
-define void @sextload_v2i16_v(<2 x i16>* %v, <2 x i16>* %p) nounwind {
+define void @sextload_v2i16_v(ptr %v, ptr %p) nounwind {
;CHECK-LABEL: sextload_v2i16_v:
entry:
- %0 = load <2 x i16>, <2 x i16>* %v, align 8
+ %0 = load <2 x i16>, ptr %v, align 8
%v0 = sext <2 x i16> %0 to <2 x i64>
- %1 = load <2 x i16>, <2 x i16>* %p, align 8
+ %1 = load <2 x i16>, ptr %p, align 8
%v2 = sext <2 x i16> %1 to <2 x i64>
;CHECK: vmull
%v1 = mul <2 x i64> %v0, %v2
- store <2 x i64> %v1, <2 x i64>* undef, align 8
+ store <2 x i64> %v1, ptr undef, align 8
ret void;
}
@@ -103,48 +103,48 @@ entry:
; Vector(small) x Vector(big)
; v4i8 x v4i16
;
-define void @sextload_v4i8_vs(<4 x i8>* %v, <4 x i16>* %p) nounwind {
+define void @sextload_v4i8_vs(ptr %v, ptr %p) nounwind {
;CHECK-LABEL: sextload_v4i8_vs:
entry:
- %0 = load <4 x i8>, <4 x i8>* %v, align 8
+ %0 = load <4 x i8>, ptr %v, align 8
%v0 = sext <4 x i8> %0 to <4 x i32>
- %1 = load <4 x i16>, <4 x i16>* %p, align 8
+ %1 = load <4 x i16>, ptr %p, align 8
%v2 = sext <4 x i16> %1 to <4 x i32>
;CHECK: vmull
%v1 = mul <4 x i32> %v0, %v2
- store <4 x i32> %v1, <4 x i32>* undef, align 8
+ store <4 x i32> %v1, ptr undef, align 8
ret void;
}
; v2i8
; v2i8 x v2i16
-define void @sextload_v2i8_vs(<2 x i8>* %v, <2 x i16>* %p) nounwind {
+define void @sextload_v2i8_vs(ptr %v, ptr %p) nounwind {
;CHECK-LABEL: sextload_v2i8_vs:
entry:
- %0 = load <2 x i8>, <2 x i8>* %v, align 8
+ %0 = load <2 x i8>, ptr %v, align 8
%v0 = sext <2 x i8> %0 to <2 x i64>
- %1 = load <2 x i16>, <2 x i16>* %p, align 8
+ %1 = load <2 x i16>, ptr %p, align 8
%v2 = sext <2 x i16> %1 to <2 x i64>
;CHECK: vmull
%v1 = mul <2 x i64> %v0, %v2
- store <2 x i64> %v1, <2 x i64>* undef, align 8
+ store <2 x i64> %v1, ptr undef, align 8
ret void;
}
; v2i16
; v2i16 x v2i32
-define void @sextload_v2i16_vs(<2 x i16>* %v, <2 x i32>* %p) nounwind {
+define void @sextload_v2i16_vs(ptr %v, ptr %p) nounwind {
;CHECK-LABEL: sextload_v2i16_vs:
entry:
- %0 = load <2 x i16>, <2 x i16>* %v, align 8
+ %0 = load <2 x i16>, ptr %v, align 8
%v0 = sext <2 x i16> %0 to <2 x i64>
- %1 = load <2 x i32>, <2 x i32>* %p, align 8
+ %1 = load <2 x i32>, ptr %p, align 8
%v2 = sext <2 x i32> %1 to <2 x i64>
;CHECK: vmull
%v1 = mul <2 x i64> %v0, %v2
- store <2 x i64> %v1, <2 x i64>* undef, align 8
+ store <2 x i64> %v1, ptr undef, align 8
ret void;
}
diff --git a/llvm/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll b/llvm/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll
index c1ce60f6b98ed..6eb8fe3588f3a 100644
--- a/llvm/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll
+++ b/llvm/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll
@@ -5,33 +5,33 @@
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
target triple = "thumbv7-apple-ios5.1.0"
-declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8*, i32) nounwind readonly
+declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0(ptr, i32) nounwind readonly
-declare void @llvm.arm.neon.vst1.p0i8.v16i8(i8*, <16 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v16i8(ptr, <16 x i8>, i32) nounwind
-define void @findEdges(i8*) nounwind ssp {
+define void @findEdges(ptr) nounwind ssp {
%2 = icmp sgt i32 undef, 0
br i1 %2, label %5, label %3
; <label>:3 ; preds = %5, %1
- %4 = phi i8* [ %0, %1 ], [ %19, %5 ]
+ %4 = phi ptr [ %0, %1 ], [ %19, %5 ]
ret void
; <label>:5 ; preds = %5, %1
- %6 = phi i8* [ %19, %5 ], [ %0, %1 ]
- %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* null, i32 1)
+ %6 = phi ptr [ %19, %5 ], [ %0, %1 ]
+ %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0(ptr null, i32 1)
%8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %7, 0
- %9 = getelementptr inbounds i8, i8* null, i32 3
- %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %9, i32 1)
+ %9 = getelementptr inbounds i8, ptr null, i32 3
+ %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0(ptr %9, i32 1)
%11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %10, 2
- %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %6, i32 1)
+ %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0(ptr %6, i32 1)
%13 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 0
%14 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 1
- %15 = getelementptr inbounds i8, i8* %6, i32 3
- %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %15, i32 1)
+ %15 = getelementptr inbounds i8, ptr %6, i32 3
+ %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0(ptr %15, i32 1)
%17 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 1
%18 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 2
- %19 = getelementptr inbounds i8, i8* %6, i32 48
+ %19 = getelementptr inbounds i8, ptr %6, i32 48
%20 = bitcast <16 x i8> %13 to <2 x i64>
%21 = bitcast <16 x i8> %8 to <2 x i64>
%22 = bitcast <16 x i8> %14 to <2 x i64>
@@ -111,7 +111,7 @@ define void @findEdges(i8*) nounwind ssp {
%96 = bitcast <8 x i8> %94 to <1 x i64>
%97 = shufflevector <1 x i64> %95, <1 x i64> %96, <2 x i32> <i32 0, i32 1>
%98 = bitcast <2 x i64> %97 to <16 x i8>
- tail call void @llvm.arm.neon.vst1.p0i8.v16i8(i8* null, <16 x i8> %98, i32 1)
+ tail call void @llvm.arm.neon.vst1.p0.v16i8(ptr null, <16 x i8> %98, i32 1)
%99 = icmp slt i32 undef, undef
br i1 %99, label %5, label %3
}
diff --git a/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll b/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll
index 53860ea1b0b90..97c4c5c1b6460 100644
--- a/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll
+++ b/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll
@@ -4,7 +4,7 @@
; CHECK: non-trivial scalar-to-vector conversion, possible invalid constraint for vector type
define void @f() nounwind ssp {
- %1 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } asm "vldm $4, { ${0:q}, ${1:q}, ${2:q}, ${3:q} }", "=r,=r,=r,=r,r"(i64* undef) nounwind, !srcloc !0
+ %1 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } asm "vldm $4, { ${0:q}, ${1:q}, ${2:q}, ${3:q} }", "=r,=r,=r,=r,r"(ptr undef) nounwind, !srcloc !0
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll b/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll
index a928543d7cf2f..d5b542b85d516 100644
--- a/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll
+++ b/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll
@@ -4,8 +4,8 @@
; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type
; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type
-define hidden void @f(i32* %corr, i32 %order) nounwind ssp {
- tail call void asm sideeffect "vst1.s32 { ${1:q}, ${2:q} }, [$0]", "r,{q0},{q1}"(i32* %corr, <2 x i64>* undef, i32 %order) nounwind, !srcloc !0
+define hidden void @f(ptr %corr, i32 %order) nounwind ssp {
+ tail call void asm sideeffect "vst1.s32 { ${1:q}, ${2:q} }, [$0]", "r,{q0},{q1}"(ptr %corr, ptr undef, i32 %order) nounwind, !srcloc !0
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll b/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
index 3e9fac8b03f81..d29d589a1945c 100644
--- a/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
+++ b/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
@@ -4,8 +4,8 @@
%struct_t = type { double, double, double }
@static_val = constant %struct_t { double 1.0, double 2.0, double 3.0 }
-declare void @llvm.va_start(i8*) nounwind
-declare void @llvm.va_end(i8*) nounwind
+declare void @llvm.va_start(ptr) nounwind
+declare void @llvm.va_end(ptr) nounwind
; CHECK-LABEL: test_byval_8_bytes_alignment:
define void @test_byval_8_bytes_alignment(i32 %i, ...) {
@@ -13,14 +13,13 @@ entry:
; CHECK: sub sp, sp, #16
; CHECK: add r0, sp, #4
; CHECK: stmib sp, {r1, r2, r3}
- %g = alloca i8*
- %g1 = bitcast i8** %g to i8*
- call void @llvm.va_start(i8* %g1)
+ %g = alloca ptr
+ call void @llvm.va_start(ptr %g)
; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
; CHECK: bic [[REG]], [[REG]], #7
- %0 = va_arg i8** %g, double
- call void @llvm.va_end(i8* %g1)
+ %0 = va_arg ptr %g, double
+ call void @llvm.va_end(ptr %g)
ret void
}
@@ -33,7 +32,7 @@ entry:
; CHECK: movw r0, #555
define i32 @main() {
entry:
- call void (i32, ...) @test_byval_8_bytes_alignment(i32 555, %struct_t* byval(%struct_t) @static_val)
+ call void (i32, ...) @test_byval_8_bytes_alignment(i32 555, ptr byval(%struct_t) @static_val)
ret i32 0
}
@@ -44,10 +43,9 @@ declare void @f(double);
; CHECK-DAG: str r3, [sp, #12]
; CHECK-DAG: str r2, [sp, #8]
; CHECK-NOT: str r1
-define void @test_byval_8_bytes_alignment_fixed_arg(i32 %n1, %struct_t* byval(%struct_t) %val) nounwind {
+define void @test_byval_8_bytes_alignment_fixed_arg(i32 %n1, ptr byval(%struct_t) %val) nounwind {
entry:
- %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0
- %0 = load double, double* %a
+ %0 = load double, ptr %val
call void (double) @f(double %0)
ret void
}
@@ -60,6 +58,6 @@ entry:
; CHECK: movw r0, #555
define i32 @main_fixed_arg() {
entry:
- call void (i32, %struct_t*) @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval(%struct_t) @static_val)
+ call void (i32, ptr) @test_byval_8_bytes_alignment_fixed_arg(i32 555, ptr byval(%struct_t) @static_val)
ret i32 0
}
diff --git a/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll b/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
index 3ac6f6879a4f4..afa20a733a304 100644
--- a/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
+++ b/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
@@ -4,16 +4,15 @@
%struct_t = type { double, double, double }
@static_val = constant %struct_t { double 1.0, double 2.0, double 3.0 }
-declare i32 @printf(i8*, ...)
+declare i32 @printf(ptr, ...)
; CHECK-LABEL: test_byval_usage_scheduling:
; CHECK-DAG: str r3, [sp, #12]
; CHECK-DAG: str r2, [sp, #8]
; CHECK: vldr d16, [sp, #8]
-define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, %struct_t* byval(%struct_t) %val) nounwind {
+define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, ptr byval(%struct_t) %val) nounwind {
entry:
- %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0
- %0 = load double, double* %a
- %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), double %0)
+ %0 = load double, ptr %val
+ %call = call i32 (ptr, ...) @printf(ptr @.str, double %0)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll b/llvm/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll
index b06da52973d35..2edd8b3f4fbcb 100644
--- a/llvm/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll
+++ b/llvm/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll
@@ -4,13 +4,13 @@
%my_struct_t = type { i8, i8, i8, i8, i8 }
@main.val = private unnamed_addr constant %my_struct_t { i8 1, i8 2, i8 3, i8 4, i8 5 }
-declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval(%my_struct_t) %val);
+declare void @f(i32 %n1, i32 %n2, i32 %n3, ptr byval(%my_struct_t) %val);
; CHECK-LABEL: main:
define i32 @main() nounwind {
entry:
; CHECK: ldrb {{(r[0-9]+)}}, {{(\[r[0-9]+\])}}, #1
- call void @f(i32 555, i32 555, i32 555, %my_struct_t* byval(%my_struct_t) @main.val)
+ call void @f(i32 555, i32 555, i32 555, ptr byval(%my_struct_t) @main.val)
ret i32 0
}
diff --git a/llvm/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll b/llvm/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
index a1c2bede04ae7..a2a5a464571d3 100644
--- a/llvm/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
+++ b/llvm/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
@@ -3,10 +3,10 @@
%struct.s = type { [4 x i32] }
@v = constant %struct.s zeroinitializer;
-declare void @f(%struct.s* %p);
+declare void @f(ptr %p);
; CHECK-LABEL: t:
-define void @t(i32 %a, %struct.s* byval(%struct.s) %s) nounwind {
+define void @t(i32 %a, ptr byval(%struct.s) %s) nounwind {
entry:
; Here we need to only check proper start address of restored %s argument.
@@ -17,7 +17,7 @@ entry:
; CHECK: stm r0, {r1, r2, r3}
; CHECK: add r0, sp, #12
; CHECK-NEXT: bl f
- call void @f(%struct.s* %s)
+ call void @f(ptr %s)
ret void
}
@@ -25,6 +25,6 @@ entry:
define void @caller() {
; CHECK: ldm r{{[0-9]+}}, {r1, r2, r3}
- call void @t(i32 0, %struct.s* byval(%struct.s) @v);
+ call void @t(i32 0, ptr byval(%struct.s) @v);
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2013-01-21-PR14992.ll b/llvm/test/CodeGen/ARM/2013-01-21-PR14992.ll
index 4c1f2a741e476..7e57153fc6be9 100644
--- a/llvm/test/CodeGen/ARM/2013-01-21-PR14992.ll
+++ b/llvm/test/CodeGen/ARM/2013-01-21-PR14992.ll
@@ -4,21 +4,21 @@
;EXPECTED-LABEL: foo:
;CHECK-LABEL: foo:
-define i32 @foo(i32* %a) nounwind optsize {
+define i32 @foo(ptr %a) nounwind optsize {
entry:
- %0 = load i32, i32* %a, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %a, i32 1
- %1 = load i32, i32* %arrayidx1, align 4
- %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 2
- %2 = load i32, i32* %arrayidx2, align 4
- %add.ptr = getelementptr inbounds i32, i32* %a, i32 3
+ %0 = load i32, ptr %a, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %a, i32 1
+ %1 = load i32, ptr %arrayidx1, align 4
+ %arrayidx2 = getelementptr inbounds i32, ptr %a, i32 2
+ %2 = load i32, ptr %arrayidx2, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %a, i32 3
;Make sure we do not have a duplicated register in the front of the reg list
;EXPECTED: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], {{r[0-9]+}},
;CHECK-NOT: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], [[REG]],
- tail call void @bar(i32* %add.ptr) nounwind optsize
+ tail call void @bar(ptr %add.ptr) nounwind optsize
%add = add nsw i32 %1, %0
%add3 = add nsw i32 %add, %2
ret i32 %add3
}
-declare void @bar(i32*) optsize
+declare void @bar(ptr) optsize
diff --git a/llvm/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll b/llvm/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
index 6d26c04445f26..8669935bd95db 100644
--- a/llvm/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
+++ b/llvm/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
@@ -47,27 +47,27 @@
%artz = type { i32 }
@static_val = constant %artz { i32 777 }
-declare void @fooUseParam(%artz* )
+declare void @fooUseParam(ptr )
-define void @foo(%artz* byval(%artz) %s) {
- call void @fooUseParam(%artz* %s)
+define void @foo(ptr byval(%artz) %s) {
+ call void @fooUseParam(ptr %s)
ret void
}
-define void @foo2(%artz* byval(%artz) %s, i32 %p, %artz* byval(%artz) %s2) {
- call void @fooUseParam(%artz* %s)
- call void @fooUseParam(%artz* %s2)
+define void @foo2(ptr byval(%artz) %s, i32 %p, ptr byval(%artz) %s2) {
+ call void @fooUseParam(ptr %s)
+ call void @fooUseParam(ptr %s2)
ret void
}
define void @doFoo() {
- call void @foo(%artz* byval(%artz) @static_val)
+ call void @foo(ptr byval(%artz) @static_val)
ret void
}
define void @doFoo2() {
- call void @foo2(%artz* byval(%artz) @static_val, i32 0, %artz* byval(%artz) @static_val)
+ call void @foo2(ptr byval(%artz) @static_val, i32 0, ptr byval(%artz) @static_val)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll b/llvm/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll
index 91e0114773020..d60fe8080dc00 100644
--- a/llvm/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll
+++ b/llvm/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll
@@ -18,7 +18,7 @@
%struct_t = type { i32, i32, i32, i32 }
@static_val = constant %struct_t { i32 777, i32 888, i32 999, i32 1000 }
-declare void @fooUseStruct(%struct_t*)
+declare void @fooUseStruct(ptr)
define void @foo2(double %p0, ; --> D0
double %p1, ; --> D1
@@ -30,14 +30,14 @@ define void @foo2(double %p0, ; --> D0
double %p7, ; --> D7
double %p8, ; --> Stack
i32 %p9, ; --> R0
- %struct_t* byval(%struct_t) %p10) ; --> Stack+8
+ ptr byval(%struct_t) %p10) ; --> Stack+8
{
entry:
;CHECK: push {r7, lr}
;CHECK-NOT: stm
;CHECK: add r0, sp, #16
;CHECK: bl fooUseStruct
- call void @fooUseStruct(%struct_t* %p10)
+ call void @fooUseStruct(ptr %p10)
ret void
}
@@ -55,7 +55,7 @@ entry:
double 23.7, ; --> D7
double 23.8, ; --> Stack
i32 43, ; --> R0, not Stack+8
- %struct_t* byval(%struct_t) @static_val) ; --> Stack+8, not R1
+ ptr byval(%struct_t) @static_val) ; --> Stack+8, not R1
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll b/llvm/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll
index 6c8b0ff2de19b..e24d6ee2be155 100644
--- a/llvm/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll
+++ b/llvm/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll
@@ -2,16 +2,16 @@
; PR14824. The test is presented by Jiangning Liu. If the ld/st optimization algorithm is changed, this test case may fail.
; Also if the machine code for ld/st optimizor is changed, this test case may fail. If so, remove this test.
-define void @sample_test(<8 x i64> * %secondSource, <8 x i64> * %source, <8 x i64> * %dest) nounwind {
+define void @sample_test(ptr %secondSource, ptr %source, ptr %dest) nounwind {
; CHECK: sample_test
; CHECK-NOT: vldmia
; CHECK: add
entry:
; Load %source
- %s0 = load <8 x i64> , <8 x i64> * %source, align 64
- %arrayidx64 = getelementptr inbounds <8 x i64>, <8 x i64> * %source, i32 6
- %s120 = load <8 x i64> , <8 x i64> * %arrayidx64, align 64
+ %s0 = load <8 x i64> , ptr %source, align 64
+ %arrayidx64 = getelementptr inbounds <8 x i64>, ptr %source, i32 6
+ %s120 = load <8 x i64> , ptr %arrayidx64, align 64
%s122 = bitcast <8 x i64> %s120 to i512
%data.i.i677.48.extract.shift = lshr i512 %s122, 384
%data.i.i677.48.extract.trunc = trunc i512 %data.i.i677.48.extract.shift to i64
@@ -33,9 +33,9 @@ entry:
%s130 = insertelement <8 x i64> %s129, i64 %data.i.i677.56.extract.trunc, i32 7
; Load %secondSource
- %s1 = load <8 x i64> , <8 x i64> * %secondSource, align 64
- %arrayidx67 = getelementptr inbounds <8 x i64>, <8 x i64> * %secondSource, i32 6
- %s121 = load <8 x i64> , <8 x i64> * %arrayidx67, align 64
+ %s1 = load <8 x i64> , ptr %secondSource, align 64
+ %arrayidx67 = getelementptr inbounds <8 x i64>, ptr %secondSource, i32 6
+ %s121 = load <8 x i64> , ptr %arrayidx67, align 64
%s131 = bitcast <8 x i64> %s121 to i512
%data.i1.i676.48.extract.shift = lshr i512 %s131, 384
%data.i1.i676.48.extract.trunc = trunc i512 %data.i1.i676.48.extract.shift to i64
@@ -61,10 +61,10 @@ entry:
%vecinit35.i.i700 = shufflevector <8 x i64> %vecinit28.i.i699, <8 x i64> %s139, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 13, i32 undef, i32 undef>
%vecinit42.i.i701 = shufflevector <8 x i64> %vecinit35.i.i700, <8 x i64> %s139, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 14, i32 undef>
%vecinit49.i.i702 = shufflevector <8 x i64> %vecinit42.i.i701, <8 x i64> %s130, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15>
- %arrayidx72 = getelementptr inbounds <8 x i64>, <8 x i64> * %dest, i32 6
- store <8 x i64> %vecinit49.i.i702, <8 x i64> * %arrayidx72, align 64
- %arrayidx78 = getelementptr inbounds <8 x i64>, <8 x i64> * %secondSource, i32 7
- %s141 = load <8 x i64> , <8 x i64> * %arrayidx78, align 64
+ %arrayidx72 = getelementptr inbounds <8 x i64>, ptr %dest, i32 6
+ store <8 x i64> %vecinit49.i.i702, ptr %arrayidx72, align 64
+ %arrayidx78 = getelementptr inbounds <8 x i64>, ptr %secondSource, i32 7
+ %s141 = load <8 x i64> , ptr %arrayidx78, align 64
%s151 = bitcast <8 x i64> %s141 to i512
%data.i1.i649.32.extract.shift = lshr i512 %s151, 256
%data.i1.i649.32.extract.trunc = trunc i512 %data.i1.i649.32.extract.shift to i64
@@ -76,7 +76,7 @@ entry:
%data.i1.i649.8.extract.shift = lshr i512 %s151, 64
%data.i1.i649.8.extract.trunc = trunc i512 %data.i1.i649.8.extract.shift to i64
%s155 = insertelement <8 x i64> %s154, i64 %data.i1.i649.8.extract.trunc, i32 3
- %arrayidx83 = getelementptr inbounds <8 x i64>, <8 x i64> * %dest, i32 7
- store <8 x i64> %s155, <8 x i64> * %arrayidx83, align 64
+ %arrayidx83 = getelementptr inbounds <8 x i64>, ptr %dest, i32 7
+ store <8 x i64> %s155, ptr %arrayidx83, align 64
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll b/llvm/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll
index d18dbd2db9b40..d4947015b0d31 100644
--- a/llvm/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll
+++ b/llvm/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll
@@ -14,8 +14,8 @@ define void @printfn(i32 %a, i16 signext %b, double %C, i8 signext %E) {
entry:
%conv = sext i16 %b to i32
%conv1 = sext i8 %E to i32
- %call = tail call i32 (i8*, ...) @printf(
- i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), ; --> R0
+ %call = tail call i32 (ptr, ...) @printf(
+ ptr @.str, ; --> R0
i32 %a, ; --> R1
i32 %conv, ; --> R2
double %C, ; --> SP, NCRN := R4
@@ -24,5 +24,5 @@ entry:
ret void
}
-declare i32 @printf(i8* nocapture, ...)
+declare i32 @printf(ptr nocapture, ...)
diff --git a/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll b/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll
index d6de8c9587c1d..bf461038081c8 100644
--- a/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll
+++ b/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll
@@ -5,7 +5,7 @@
%st_t = type { i32, i32 }
@static_val = constant %st_t { i32 777, i32 888}
-declare void @fooUseStruct(%st_t*)
+declare void @fooUseStruct(ptr)
define void @foo(double %vfp0, ; --> D0, NSAA=SP
double %vfp1, ; --> D1, NSAA=SP
@@ -17,7 +17,7 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP
double %vfp7, ; --> D7, NSAA=SP
double %vfp8, ; --> SP, NSAA=SP+8 (!)
i32 %p0, ; --> R0, NSAA=SP+8
- %st_t* byval(%st_t) %p1, ; --> R1, R2, NSAA=SP+8
+ ptr byval(%st_t) %p1, ; --> R1, R2, NSAA=SP+8
i32 %p2, ; --> R3, NSAA=SP+8
i32 %p3) #0 { ; --> SP+4, NSAA=SP+12
entry:
@@ -27,7 +27,7 @@ entry:
;CHECK: add r0, sp, #12
;CHECK: strd r1, r2, [sp, #12]
;CHECK: bl fooUseStruct
- call void @fooUseStruct(%st_t* %p1)
+ call void @fooUseStruct(ptr %p1)
ret void
}
@@ -42,7 +42,7 @@ entry:
double 23.6,
double 23.7,
double 23.8,
- i32 0, %st_t* byval(%st_t) @static_val, i32 1, i32 2)
+ i32 0, ptr byval(%st_t) @static_val, i32 1, i32 2)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll b/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll
index d2e3fef51c32f..acf9073740158 100644
--- a/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll
+++ b/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll
@@ -15,7 +15,7 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP
double %vfp7, ; --> D7, NSAA=SP
double %vfp8, ; --> SP, NSAA=SP+8 (!)
i32 %p0, ; --> R0, NSAA=SP+8
- %st_t* byval(%st_t) %p1, ; --> SP+8, 4 words NSAA=SP+24
+ ptr byval(%st_t) %p1, ; --> SP+8, 4 words NSAA=SP+24
i32 %p2) #0 { ; --> SP+24, NSAA=SP+24
entry:
@@ -39,7 +39,7 @@ entry:
double 23.6,
double 23.7,
double 23.8,
- i32 0, %st_t* byval(%st_t) @static_val, i32 1)
+ i32 0, ptr byval(%st_t) @static_val, i32 1)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll b/llvm/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
index 1402075cce86d..344bb15d2a8b8 100644
--- a/llvm/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
+++ b/llvm/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=thumbv8 | FileCheck -check-prefix=CHECK-V8 %s
; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it | FileCheck -check-prefix=CHECK-RESTRICT-IT %s
-define i32 @t1(i32 %a, i32 %b, i8** %retaddr) {
+define i32 @t1(i32 %a, i32 %b, ptr %retaddr) {
; CHECK-LABEL: t1:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r3, LCPI0_0
@@ -58,7 +58,7 @@ define i32 @t1(i32 %a, i32 %b, i8** %retaddr) {
; CHECK-RESTRICT-IT-NEXT: @ %bb.2:
; CHECK-RESTRICT-IT-NEXT: .LCPI0_0:
; CHECK-RESTRICT-IT-NEXT: .long .Ltmp0
- store i8* blockaddress(@t1, %cond_true), i8** %retaddr
+ store ptr blockaddress(@t1, %cond_true), ptr %retaddr
%tmp2 = icmp eq i32 %a, 0
br i1 %tmp2, label %cond_false, label %cond_true
@@ -71,7 +71,7 @@ cond_false:
ret i32 %tmp7
}
-define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d, i8** %retaddr) {
+define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d, ptr %retaddr) {
; CHECK-LABEL: t2:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr.w r9, [sp]
@@ -145,7 +145,7 @@ define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d, i8** %retaddr) {
; CHECK-RESTRICT-IT-NEXT: @ %bb.4:
; CHECK-RESTRICT-IT-NEXT: .LCPI1_0:
; CHECK-RESTRICT-IT-NEXT: .long .Ltmp1
- store i8* blockaddress(@t2, %cond_true), i8** %retaddr
+ store ptr blockaddress(@t2, %cond_true), ptr %retaddr
%tmp2 = icmp sgt i32 %c, 10
%tmp5 = icmp slt i32 %d, 4
%tmp8 = and i1 %tmp5, %tmp2
@@ -161,7 +161,7 @@ UnifiedReturnBlock:
ret i32 %tmp13
}
-define hidden fastcc void @t3(i8** %retaddr, i1 %tst, i8* %p8) {
+define hidden fastcc void @t3(ptr %retaddr, i1 %tst, ptr %p8) {
; CHECK-LABEL: t3:
; CHECK: @ %bb.0: @ %bb
; CHECK-NEXT: ldr r1, LCPI2_0
@@ -202,7 +202,7 @@ define hidden fastcc void @t3(i8** %retaddr, i1 %tst, i8* %p8) {
; CHECK-RESTRICT-IT-NEXT: .LCPI2_0:
; CHECK-RESTRICT-IT-NEXT: .long .Ltmp2
bb:
- store i8* blockaddress(@t3, %KBBlockZero_return_1), i8** %retaddr
+ store ptr blockaddress(@t3, %KBBlockZero_return_1), ptr %retaddr
br i1 %tst, label %bb77, label %bb7.i
bb7.i: ; preds = %bb35
@@ -224,11 +224,11 @@ bb6.i350: ; preds = %bb2.i
br label %bb2.i
KBBlockZero.exit: ; preds = %bb2.i
- indirectbr i8* %p8, [label %KBBlockZero_return_1, label %KBBlockZero_return_0]
+ indirectbr ptr %p8, [label %KBBlockZero_return_1, label %KBBlockZero_return_0]
}
- at foo = global i32 ()* null
-define i32 @t4(i32 %x, i32 ()* %p_foo) {
+ at foo = global ptr null
+define i32 @t4(i32 %x, ptr %p_foo) {
; CHECK-LABEL: t4:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push {r4, lr}
diff --git a/llvm/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll b/llvm/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll
index aabbfae8b879b..f7500bd5bda48 100644
--- a/llvm/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll
+++ b/llvm/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll
@@ -1,52 +1,52 @@
; RUN: llc -mtriple=thumb-eabi -mattr=+v7,+thumb2 %s -o - | FileCheck %s
-define i8 @f1(i8* %call1, i8* %call3, i32 %h, i32 %w, i32 %Width) {
+define i8 @f1(ptr %call1, ptr %call3, i32 %h, i32 %w, i32 %Width) {
; CHECK: f1:
entry:
%mul17 = mul nsw i32 %Width, %h
%add = add nsw i32 %mul17, %w
%sub19 = sub i32 %add, %Width
%sub20 = add i32 %sub19, -1
- %arrayidx21 = getelementptr inbounds i8, i8* %call1, i32 %sub20
- %0 = load i8, i8* %arrayidx21, align 1
+ %arrayidx21 = getelementptr inbounds i8, ptr %call1, i32 %sub20
+ %0 = load i8, ptr %arrayidx21, align 1
%conv22 = zext i8 %0 to i32
- %arrayidx25 = getelementptr inbounds i8, i8* %call1, i32 %sub19
- %1 = load i8, i8* %arrayidx25, align 1
+ %arrayidx25 = getelementptr inbounds i8, ptr %call1, i32 %sub19
+ %1 = load i8, ptr %arrayidx25, align 1
%conv26 = zext i8 %1 to i32
%mul23189 = add i32 %conv26, %conv22
%add30 = add i32 %sub19, 1
- %arrayidx31 = getelementptr inbounds i8, i8* %call1, i32 %add30
- %2 = load i8, i8* %arrayidx31, align 1
+ %arrayidx31 = getelementptr inbounds i8, ptr %call1, i32 %add30
+ %2 = load i8, ptr %arrayidx31, align 1
%conv32 = zext i8 %2 to i32
; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1]
; CHECK-NEXT: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #1]
%add28190 = add i32 %mul23189, %conv32
%sub35 = add i32 %add, -1
- %arrayidx36 = getelementptr inbounds i8, i8* %call1, i32 %sub35
- %3 = load i8, i8* %arrayidx36, align 1
+ %arrayidx36 = getelementptr inbounds i8, ptr %call1, i32 %sub35
+ %3 = load i8, ptr %arrayidx36, align 1
%conv37 = zext i8 %3 to i32
%add34191 = add i32 %add28190, %conv37
- %arrayidx40 = getelementptr inbounds i8, i8* %call1, i32 %add
- %4 = load i8, i8* %arrayidx40, align 1
+ %arrayidx40 = getelementptr inbounds i8, ptr %call1, i32 %add
+ %4 = load i8, ptr %arrayidx40, align 1
%conv41 = zext i8 %4 to i32
%mul42 = mul nsw i32 %conv41, 255
%add44 = add i32 %add, 1
- %arrayidx45 = getelementptr inbounds i8, i8* %call1, i32 %add44
- %5 = load i8, i8* %arrayidx45, align 1
+ %arrayidx45 = getelementptr inbounds i8, ptr %call1, i32 %add44
+ %5 = load i8, ptr %arrayidx45, align 1
%conv46 = zext i8 %5 to i32
; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1]
; CHECK-NEXT: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #1]
%add49 = add i32 %add, %Width
%sub50 = add i32 %add49, -1
- %arrayidx51 = getelementptr inbounds i8, i8* %call1, i32 %sub50
- %6 = load i8, i8* %arrayidx51, align 1
+ %arrayidx51 = getelementptr inbounds i8, ptr %call1, i32 %sub50
+ %6 = load i8, ptr %arrayidx51, align 1
%conv52 = zext i8 %6 to i32
- %arrayidx56 = getelementptr inbounds i8, i8* %call1, i32 %add49
- %7 = load i8, i8* %arrayidx56, align 1
+ %arrayidx56 = getelementptr inbounds i8, ptr %call1, i32 %add49
+ %7 = load i8, ptr %arrayidx56, align 1
%conv57 = zext i8 %7 to i32
%add61 = add i32 %add49, 1
- %arrayidx62 = getelementptr inbounds i8, i8* %call1, i32 %add61
- %8 = load i8, i8* %arrayidx62, align 1
+ %arrayidx62 = getelementptr inbounds i8, ptr %call1, i32 %add61
+ %8 = load i8, ptr %arrayidx62, align 1
%conv63 = zext i8 %8 to i32
; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1]
; CHECK-NEXT: ldrb{{[.w]*}} r{{[0-9]*}}, [r{{[0-9]*}}, #1]
@@ -58,7 +58,7 @@ entry:
%add65 = add i32 %tmp196, %mul42
%9 = lshr i32 %add65, 8
%conv68 = trunc i32 %9 to i8
- %arrayidx69 = getelementptr inbounds i8, i8* %call3, i32 %add
- store i8 %conv68, i8* %arrayidx69, align 1
+ %arrayidx69 = getelementptr inbounds i8, ptr %call3, i32 %add
+ store i8 %conv68, ptr %arrayidx69, align 1
ret i8 %conv68
}
diff --git a/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll b/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll
index 353fade4992d6..d8e22f4f5312a 100644
--- a/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll
+++ b/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll
@@ -5,8 +5,8 @@
define void @check227(
i32 %b,
- %struct.S227* byval(%struct.S227) nocapture %arg0,
- %struct.S227* %arg1) {
+ ptr byval(%struct.S227) nocapture %arg0,
+ ptr %arg1) {
; b --> R0
; arg0 --> [R1, R2, R3, SP+0 .. SP+188)
; arg1 --> SP+188
@@ -24,7 +24,7 @@ entry:
;CHECK: pop {r11, lr}
;CHECK: add sp, sp, #12
- %0 = ptrtoint %struct.S227* %arg1 to i32
+ %0 = ptrtoint ptr %arg1 to i32
tail call void @useInt(i32 %0)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll b/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll
index 0f9273ded6bf0..0c5d22984b99e 100644
--- a/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll
+++ b/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll
@@ -4,8 +4,8 @@
%struct4bytes = type { i32 }
%struct20bytes = type { i32, i32, i32, i32, i32 }
-define void @foo(%struct4bytes* byval(%struct4bytes) %p0, ; --> R0
- %struct20bytes* byval(%struct20bytes) %p1 ; --> R1,R2,R3, [SP+0 .. SP+8)
+define void @foo(ptr byval(%struct4bytes) %p0, ; --> R0
+ ptr byval(%struct20bytes) %p1 ; --> R1,R2,R3, [SP+0 .. SP+8)
) {
;CHECK: sub sp, sp, #16
;CHECK: push {r11, lr}
@@ -16,7 +16,7 @@ define void @foo(%struct4bytes* byval(%struct4bytes) %p0, ; --> R0
;CHECK: pop {r11, lr}
;CHECK: add sp, sp, #16
- %1 = ptrtoint %struct20bytes* %p1 to i32
+ %1 = ptrtoint ptr %p1 to i32
tail call void @useInt(i32 %1)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll b/llvm/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll
index 617271264b4fe..3a2087b36246d 100644
--- a/llvm/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll
+++ b/llvm/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll
@@ -9,8 +9,8 @@
define arm_aapcscc void @f2(i8 signext %a) #0 {
entry:
%a.addr = alloca i8, align 1
- store i8 %a, i8* %a.addr, align 1
- %0 = load i8, i8* %a.addr, align 1
+ store i8 %a, ptr %a.addr, align 1
+ %0 = load i8, ptr %a.addr, align 1
%conv = sext i8 %0 to i32
%shr = ashr i32 %conv, 56
%conv1 = trunc i32 %shr to i8
diff --git a/llvm/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll b/llvm/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll
index e5059edf0c4dd..9003ac0104ec7 100644
--- a/llvm/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll
+++ b/llvm/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll
@@ -7,24 +7,24 @@ target triple = "armv4t--linux-gnueabihf"
%big_struct1 = type { [516 x i32] }
;CHECK-LABEL: f:
-define void @f(%big_struct0* %p0, %big_struct1* %p1) {
+define void @f(ptr %p0, ptr %p1) {
;CHECK: sub sp, sp, #8
;CHECK: sub sp, sp, #2048
;CHECK: bl callme0
- call void @callme0(%big_struct0* byval(%big_struct0) %p0)
+ call void @callme0(ptr byval(%big_struct0) %p0)
;CHECK: add sp, sp, #8
;CHECK: add sp, sp, #2048
;CHECK: sub sp, sp, #2048
;CHECK: bl callme1
- call void @callme1(%big_struct1* byval(%big_struct1) %p1)
+ call void @callme1(ptr byval(%big_struct1) %p1)
;CHECK: add sp, sp, #2048
ret void
}
-declare void @callme0(%big_struct0* byval(%big_struct0))
-declare void @callme1(%big_struct1* byval(%big_struct1))
+declare void @callme0(ptr byval(%big_struct0))
+declare void @callme1(ptr byval(%big_struct1))
diff --git a/llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll b/llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
index 4ddf669ede19f..59a774aa13f7b 100644
--- a/llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
+++ b/llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
@@ -15,13 +15,13 @@ entry:
; CHECK: vorr q8, q8, q9
; CHECK: vst1.32 {d16, d17}, [r0]
vector.body:
- %wide.load = load <4 x i32>, <4 x i32>* undef, align 4
+ %wide.load = load <4 x i32>, ptr undef, align 4
%0 = and <4 x i32> %wide.load, <i32 -16711936, i32 -16711936, i32 -16711936, i32 -16711936>
%1 = sub <4 x i32> %wide.load, zeroinitializer
%2 = and <4 x i32> %1, <i32 16711680, i32 16711680, i32 16711680, i32 16711680>
%3 = or <4 x i32> %0, <i32 1, i32 2, i32 3, i32 4>
%4 = or <4 x i32> %3, %2
- store <4 x i32> %4, <4 x i32>* undef, align 4
+ store <4 x i32> %4, ptr undef, align 4
br label %vector.body
for.end:
diff --git a/llvm/test/CodeGen/ARM/2013-10-11-select-stalls.ll b/llvm/test/CodeGen/ARM/2013-10-11-select-stalls.ll
index 2c15c1a943bad..686ff38104912 100644
--- a/llvm/test/CodeGen/ARM/2013-10-11-select-stalls.ll
+++ b/llvm/test/CodeGen/ARM/2013-10-11-select-stalls.ll
@@ -8,14 +8,14 @@
; test.
; CHECK-NOT: Number of pipeline stalls
-define <16 x i8> @multiselect(i32 %avail, i8* %foo, i8* %bar) {
+define <16 x i8> @multiselect(i32 %avail, ptr %foo, ptr %bar) {
entry:
- %vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %foo, i32 1)
- %vld2 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %bar, i32 1)
+ %vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr %foo, i32 1)
+ %vld2 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr %bar, i32 1)
%and = and i32 %avail, 3
%tobool = icmp eq i32 %and, 0
%retv = select i1 %tobool, <16 x i8> %vld1, <16 x i8> %vld2
ret <16 x i8> %retv
}
-declare <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* , i32 )
+declare <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr , i32 )
diff --git a/llvm/test/CodeGen/ARM/2013-11-08-inline-asm-neon-array.ll b/llvm/test/CodeGen/ARM/2013-11-08-inline-asm-neon-array.ll
index 2c5f00e15ba0f..33a7e2ae04c54 100644
--- a/llvm/test/CodeGen/ARM/2013-11-08-inline-asm-neon-array.ll
+++ b/llvm/test/CodeGen/ARM/2013-11-08-inline-asm-neon-array.ll
@@ -9,7 +9,7 @@ target triple = "armv7--"
define void @foo() #0 {
%vsrc = alloca %struct.uint8x8x4_t, align 8
%ptr = alloca i8;
- %1 = call i8* asm sideeffect "vld4.u8 ${0:h}, [$1], $2", "=*w,=r,r,1"(%struct.uint8x8x4_t* elementtype(%struct.uint8x8x4_t) %vsrc, i32 0, i8* %ptr)
+ %1 = call ptr asm sideeffect "vld4.u8 ${0:h}, [$1], $2", "=*w,=r,r,1"(ptr elementtype(%struct.uint8x8x4_t) %vsrc, i32 0, ptr %ptr)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll b/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
index 5f4bb4bc1983a..b8b9a55755afc 100644
--- a/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
+++ b/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon -print-before=post-RA-sched %s -o - 2>&1 \
; RUN: | FileCheck %s
-define void @vst(i8* %m, [4 x i64] %v) {
+define void @vst(ptr %m, [4 x i64] %v) {
entry:
; CHECK: vst:
; CHECK: VST1d64Q killed $r{{[0-9]+}}, 8, $d{{[0-9]+}}, 14, $noreg, implicit killed $q{{[0-9]+}}_q{{[0-9]+}}
@@ -27,7 +27,7 @@ entry:
%n0 = insertelement <2 x i64> undef, i64 %tmp0, i32 0
%n1 = insertelement <2 x i64> %n0, i64 %tmp1, i32 1
- call void @llvm.arm.neon.vst4.p0i8.v1i64(i8* %m, <1 x i64> %s0, <1 x i64> %s1, <1 x i64> %s2, <1 x i64> %s3, i32 8)
+ call void @llvm.arm.neon.vst4.p0.v1i64(ptr %m, <1 x i64> %s0, <1 x i64> %s1, <1 x i64> %s2, <1 x i64> %s3, i32 8)
call void @bar(<2 x i64> %n1)
@@ -35,22 +35,22 @@ entry:
}
%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
-define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
+define <8 x i8> @vtbx4(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK: vtbx4:
; CHECK: VTBX4 {{.*}}, 14, $noreg, implicit $q{{[0-9]+}}_q{{[0-9]+}}
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load %struct.__neon_int8x8x4_t, ptr %B
%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
%tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
- %tmp7 = load <8 x i8>, <8 x i8>* %C
+ %tmp7 = load <8 x i8>, ptr %C
%tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
call void @bar2(%struct.__neon_int8x8x4_t %tmp2, <8 x i8> %tmp8)
ret <8 x i8> %tmp8
}
-declare void @llvm.arm.neon.vst4.p0i8.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32)
+declare void @llvm.arm.neon.vst4.p0.v1i64(ptr, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32)
declare <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
declare void @bar2(%struct.__neon_int8x8x4_t, <8 x i8>)
declare void @bar(<2 x i64> %arg)
diff --git a/llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll b/llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll
index f9d24ad1ad444..4242343ae67bf 100644
--- a/llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll
+++ b/llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll
@@ -4,14 +4,14 @@
%struct8bytes8align = type { i64 }
%struct12bytes = type { i32, i32, i32 }
-declare void @useIntPtr(%struct4bytes*)
+declare void @useIntPtr(ptr)
declare void @useLong(i64)
-declare void @usePtr(%struct8bytes8align*)
+declare void @usePtr(ptr)
; a -> r0
; b -> r1..r3
; c -> sp+0..sp+7
-define void @foo1(i32 %a, %struct12bytes* byval(%struct12bytes) %b, i64 %c) {
+define void @foo1(i32 %a, ptr byval(%struct12bytes) %b, i64 %c) {
; CHECK-LABEL: foo1
; CHECK: sub sp, sp, #12
; CHECK: push {r11, lr}
@@ -30,7 +30,7 @@ define void @foo1(i32 %a, %struct12bytes* byval(%struct12bytes) %b, i64 %c) {
; a -> r0
; b -> r2..r3
-define void @foo2(i32 %a, %struct8bytes8align* byval(%struct8bytes8align) %b) {
+define void @foo2(i32 %a, ptr byval(%struct8bytes8align) %b) {
; CHECK-LABEL: foo2
; CHECK: sub sp, sp, #8
; CHECK: push {r11, lr}
@@ -41,13 +41,13 @@ define void @foo2(i32 %a, %struct8bytes8align* byval(%struct8bytes8align) %b) {
; CHECK: pop {r11, lr}
; CHECK: add sp, sp, #8
- call void @usePtr(%struct8bytes8align* %b)
+ call void @usePtr(ptr %b)
ret void
}
; a -> r0..r1
; b -> r2
-define void @foo3(%struct8bytes8align* byval(%struct8bytes8align) %a, %struct4bytes* byval(%struct4bytes) %b) {
+define void @foo3(ptr byval(%struct8bytes8align) %a, ptr byval(%struct4bytes) %b) {
; CHECK-LABEL: foo3
; CHECK: sub sp, sp, #16
; CHECK: push {r11, lr}
@@ -58,13 +58,13 @@ define void @foo3(%struct8bytes8align* byval(%struct8bytes8align) %a, %struct4by
; CHECK: pop {r11, lr}
; CHECK: add sp, sp, #16
- call void @usePtr(%struct8bytes8align* %a)
+ call void @usePtr(ptr %a)
ret void
}
; a -> r0
; b -> r2..r3
-define void @foo4(%struct4bytes* byval(%struct4bytes) %a, %struct8bytes8align* byval(%struct8bytes8align) %b) {
+define void @foo4(ptr byval(%struct4bytes) %a, ptr byval(%struct8bytes8align) %b) {
; CHECK-LABEL: foo4
; CHECK: sub sp, sp, #16
; CHECK: push {r11, lr}
@@ -77,14 +77,14 @@ define void @foo4(%struct4bytes* byval(%struct4bytes) %a, %struct8bytes8align* b
; CHECK: add sp, sp, #16
; CHECK: mov pc, lr
- call void @usePtr(%struct8bytes8align* %b)
+ call void @usePtr(ptr %b)
ret void
}
; a -> r0..r1
; b -> r2
; c -> r3
-define void @foo5(%struct8bytes8align* byval(%struct8bytes8align) %a, %struct4bytes* byval(%struct4bytes) %b, %struct4bytes* byval(%struct4bytes) %c) {
+define void @foo5(ptr byval(%struct8bytes8align) %a, ptr byval(%struct4bytes) %b, ptr byval(%struct4bytes) %c) {
; CHECK-LABEL: foo5
; CHECK: sub sp, sp, #16
; CHECK: push {r11, lr}
@@ -96,13 +96,13 @@ define void @foo5(%struct8bytes8align* byval(%struct8bytes8align) %a, %struct4by
; CHECK: add sp, sp, #16
; CHECK: mov pc, lr
- call void @usePtr(%struct8bytes8align* %a)
+ call void @usePtr(ptr %a)
ret void
}
; a..c -> r0..r2
; d -> sp+0..sp+7
-define void @foo6(i32 %a, i32 %b, i32 %c, %struct8bytes8align* byval(%struct8bytes8align) %d) {
+define void @foo6(i32 %a, i32 %b, i32 %c, ptr byval(%struct8bytes8align) %d) {
; CHECK-LABEL: foo6
; CHECK: push {r11, lr}
; CHECK: add r0, sp, #8
@@ -110,6 +110,6 @@ define void @foo6(i32 %a, i32 %b, i32 %c, %struct8bytes8align* byval(%struct8byt
; CHECK: pop {r11, lr}
; CHECK: mov pc, lr
- call void @usePtr(%struct8bytes8align* %d)
+ call void @usePtr(ptr %d)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/2014-05-14-DwarfEHCrash.ll b/llvm/test/CodeGen/ARM/2014-05-14-DwarfEHCrash.ll
index 58f1f45643203..96639ed420782 100644
--- a/llvm/test/CodeGen/ARM/2014-05-14-DwarfEHCrash.ll
+++ b/llvm/test/CodeGen/ARM/2014-05-14-DwarfEHCrash.ll
@@ -6,24 +6,24 @@
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"
target triple = "armv4t--linux-androideabi"
- at _ZTIi = external constant i8*
+ at _ZTIi = external constant ptr
-define void @_Z3fn2v() #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+define void @_Z3fn2v() #0 personality ptr @__gxx_personality_v0 {
entry:
invoke void @_Z3fn1v()
to label %try.cont unwind label %lpad
lpad: ; preds = %entry
- %0 = landingpad { i8*, i32 }
- catch i8* bitcast (i8** @_ZTIi to i8*)
- %1 = extractvalue { i8*, i32 } %0, 1
- %2 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) #2
+ %0 = landingpad { ptr, i32 }
+ catch ptr @_ZTIi
+ %1 = extractvalue { ptr, i32 } %0, 1
+ %2 = tail call i32 @llvm.eh.typeid.for(ptr @_ZTIi) #2
%matches = icmp eq i32 %1, %2
br i1 %matches, label %catch, label %eh.resume
catch: ; preds = %lpad
- %3 = extractvalue { i8*, i32 } %0, 0
- %4 = tail call i8* @__cxa_begin_catch(i8* %3) #2
+ %3 = extractvalue { ptr, i32 } %0, 0
+ %4 = tail call ptr @__cxa_begin_catch(ptr %3) #2
tail call void @__cxa_end_catch() #2
br label %try.cont
@@ -31,7 +31,7 @@ try.cont: ; preds = %entry, %catch
ret void
eh.resume: ; preds = %lpad
- resume { i8*, i32 } %0
+ resume { ptr, i32 } %0
}
declare void @_Z3fn1v() #0
@@ -39,9 +39,9 @@ declare void @_Z3fn1v() #0
declare i32 @__gxx_personality_v0(...)
; Function Attrs: nounwind readnone
-declare i32 @llvm.eh.typeid.for(i8*) #1
+declare i32 @llvm.eh.typeid.for(ptr) #1
-declare i8* @__cxa_begin_catch(i8*)
+declare ptr @__cxa_begin_catch(ptr)
declare void @__cxa_end_catch()
diff --git a/llvm/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll b/llvm/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll
index 1abc40f2c16e2..e9133ee7adaf2 100644
--- a/llvm/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll
+++ b/llvm/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll
@@ -3,31 +3,31 @@
; Check that we don't create an unpredictable STR instruction,
; e.g. str r0, [r0], #4
-define i32* @earlyclobber-str-post(i32* %addr) nounwind {
+define ptr @earlyclobber-str-post(ptr %addr) nounwind {
; CHECK-LABEL: earlyclobber-str-post
; CHECK-NOT: str r[[REG:[0-9]+]], [r[[REG]]], #4
- %val = ptrtoint i32* %addr to i32
- store i32 %val, i32* %addr
- %new = getelementptr i32, i32* %addr, i32 1
- ret i32* %new
+ %val = ptrtoint ptr %addr to i32
+ store i32 %val, ptr %addr
+ %new = getelementptr i32, ptr %addr, i32 1
+ ret ptr %new
}
-define i16* @earlyclobber-strh-post(i16* %addr) nounwind {
+define ptr @earlyclobber-strh-post(ptr %addr) nounwind {
; CHECK-LABEL: earlyclobber-strh-post
; CHECK-NOT: strh r[[REG:[0-9]+]], [r[[REG]]], #2
- %val = ptrtoint i16* %addr to i32
+ %val = ptrtoint ptr %addr to i32
%tr = trunc i32 %val to i16
- store i16 %tr, i16* %addr
- %new = getelementptr i16, i16* %addr, i32 1
- ret i16* %new
+ store i16 %tr, ptr %addr
+ %new = getelementptr i16, ptr %addr, i32 1
+ ret ptr %new
}
-define i8* @earlyclobber-strb-post(i8* %addr) nounwind {
+define ptr @earlyclobber-strb-post(ptr %addr) nounwind {
; CHECK-LABEL: earlyclobber-strb-post
; CHECK-NOT: strb r[[REG:[0-9]+]], [r[[REG]]], #1
- %val = ptrtoint i8* %addr to i32
+ %val = ptrtoint ptr %addr to i32
%tr = trunc i32 %val to i8
- store i8 %tr, i8* %addr
- %new = getelementptr i8, i8* %addr, i32 1
- ret i8* %new
+ store i8 %tr, ptr %addr
+ %new = getelementptr i8, ptr %addr, i32 1
+ ret ptr %new
}
diff --git a/llvm/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll b/llvm/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll
index 2efd91f503e5d..d531dacb67458 100644
--- a/llvm/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll
+++ b/llvm/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll
@@ -2,20 +2,20 @@
; RUN: llc -mtriple=thumbv6m-none--eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V6M
; CHECK-LABEL: test1
-define i32 @test1(i32* %p) {
+define i32 @test1(ptr %p) {
; Offsets less than 8 can be generated in a single add
; CHECK: adds [[NEWBASE:r[0-9]]], r0, #4
- %1 = getelementptr inbounds i32, i32* %p, i32 1
- %2 = getelementptr inbounds i32, i32* %p, i32 2
- %3 = getelementptr inbounds i32, i32* %p, i32 3
- %4 = getelementptr inbounds i32, i32* %p, i32 4
+ %1 = getelementptr inbounds i32, ptr %p, i32 1
+ %2 = getelementptr inbounds i32, ptr %p, i32 2
+ %3 = getelementptr inbounds i32, ptr %p, i32 3
+ %4 = getelementptr inbounds i32, ptr %p, i32 4
; CHECK-NEXT: ldm [[NEWBASE]],
- %5 = load i32, i32* %1, align 4
- %6 = load i32, i32* %2, align 4
- %7 = load i32, i32* %3, align 4
- %8 = load i32, i32* %4, align 4
+ %5 = load i32, ptr %1, align 4
+ %6 = load i32, ptr %2, align 4
+ %7 = load i32, ptr %3, align 4
+ %8 = load i32, ptr %4, align 4
%9 = add nsw i32 %5, %6
%10 = add nsw i32 %9, %7
@@ -24,22 +24,22 @@ define i32 @test1(i32* %p) {
}
; CHECK-LABEL: test2
-define i32 @test2(i32* %p) {
+define i32 @test2(ptr %p) {
; Offsets >=8 require a mov and an add
; CHECK-V4T: movs [[NEWBASE:r[0-9]]], r0
; CHECK-V6M: mov [[NEWBASE:r[0-9]]], r0
; CHECK-NEXT: adds [[NEWBASE]], #8
- %1 = getelementptr inbounds i32, i32* %p, i32 2
- %2 = getelementptr inbounds i32, i32* %p, i32 3
- %3 = getelementptr inbounds i32, i32* %p, i32 4
- %4 = getelementptr inbounds i32, i32* %p, i32 5
+ %1 = getelementptr inbounds i32, ptr %p, i32 2
+ %2 = getelementptr inbounds i32, ptr %p, i32 3
+ %3 = getelementptr inbounds i32, ptr %p, i32 4
+ %4 = getelementptr inbounds i32, ptr %p, i32 5
; CHECK-NEXT: ldm [[NEWBASE]],
- %5 = load i32, i32* %1, align 4
- %6 = load i32, i32* %2, align 4
- %7 = load i32, i32* %3, align 4
- %8 = load i32, i32* %4, align 4
+ %5 = load i32, ptr %1, align 4
+ %6 = load i32, ptr %2, align 4
+ %7 = load i32, ptr %3, align 4
+ %8 = load i32, ptr %4, align 4
%9 = add nsw i32 %5, %6
%10 = add nsw i32 %9, %7
diff --git a/llvm/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll
index 8e11d5921af02..cb8d83241a4a7 100644
--- a/llvm/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll
+++ b/llvm/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll
@@ -6,44 +6,44 @@
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n8:16:32-S64"
target triple = "thumbv7--linux-android"
-%struct.r = type { i32 (...)**, [10 x [9 x float]], [10 x [9 x float]], [101 x [9 x float]], [101 x [9 x float]], i32, i32, i32, i32, i32, [8 x [2 x i32]], [432 x float], [432 x i32], [10 x i8*], [10 x i8*], [10 x i32], [10 x i32], [10 x i32], [10 x i32], [10 x i32], [10 x i32], i32, i32, i32, i32, float, float, i32, i32, [9 x float], float*, float }
+%struct.r = type { ptr, [10 x [9 x float]], [10 x [9 x float]], [101 x [9 x float]], [101 x [9 x float]], i32, i32, i32, i32, i32, [8 x [2 x i32]], [432 x float], [432 x i32], [10 x ptr], [10 x ptr], [10 x i32], [10 x i32], [10 x i32], [10 x i32], [10 x i32], [10 x i32], i32, i32, i32, i32, float, float, i32, i32, [9 x float], ptr, float }
-define void @foo(%struct.r* %this, float* %srcR, float* %srcC, float* %tempPntsX, float* %tY, float* %ms, float* %sX, float* %sY, i32* dereferenceable(4) %num, float* %tm, i32 %SR, i32 %lev, i8* %tdata, i32 %siW, i32 %pyw, i32 %pyh, i8* %sdata) #0 align 2 {
+define void @foo(ptr %this, ptr %srcR, ptr %srcC, ptr %tempPntsX, ptr %tY, ptr %ms, ptr %sX, ptr %sY, ptr dereferenceable(4) %num, ptr %tm, i32 %SR, i32 %lev, ptr %tdata, i32 %siW, i32 %pyw, i32 %pyh, ptr %sdata) #0 align 2 {
entry:
%sFV = alloca [49 x float], align 4
%tFV = alloca [49 x float], align 4
%TIM = alloca [9 x float], align 4
%sort_tmp = alloca [432 x float], align 4
%msDiffs = alloca [432 x float], align 4
- %TM.sroa.0.0.copyload = load float, float* %tm, align 4
- %TM.sroa.8.0.copyload = load float, float* null, align 4
- %TM.sroa.9.0..sroa_idx813 = getelementptr inbounds float, float* %tm, i32 6
- %TM.sroa.9.0.copyload = load float, float* %TM.sroa.9.0..sroa_idx813, align 4
- %TM.sroa.11.0.copyload = load float, float* undef, align 4
+ %TM.sroa.0.0.copyload = load float, ptr %tm, align 4
+ %TM.sroa.8.0.copyload = load float, ptr null, align 4
+ %TM.sroa.9.0..sroa_idx813 = getelementptr inbounds float, ptr %tm, i32 6
+ %TM.sroa.9.0.copyload = load float, ptr %TM.sroa.9.0..sroa_idx813, align 4
+ %TM.sroa.11.0.copyload = load float, ptr undef, align 4
br i1 undef, label %for.body.lr.ph, label %if.then343
for.body.lr.ph: ; preds = %entry
- %arrayidx8 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 0
- %arrayidx12 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 6
- %arrayidx15 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 4
- %arrayidx20 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 7
- %arrayidx24 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 0
- %arrayidx28 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 6
- %arrayidx32 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 4
- %arrayidx36 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 7
- %arrayidx84 = getelementptr inbounds [9 x float], [9 x float]* %TIM, i32 0, i32 6
- %arrayidx92 = getelementptr inbounds [9 x float], [9 x float]* %TIM, i32 0, i32 7
+ %arrayidx8 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 1, i32 %lev, i32 0
+ %arrayidx12 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 1, i32 %lev, i32 6
+ %arrayidx15 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 1, i32 %lev, i32 4
+ %arrayidx20 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 1, i32 %lev, i32 7
+ %arrayidx24 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 2, i32 %lev, i32 0
+ %arrayidx28 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 2, i32 %lev, i32 6
+ %arrayidx32 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 2, i32 %lev, i32 4
+ %arrayidx36 = getelementptr inbounds %struct.r, ptr %this, i32 0, i32 2, i32 %lev, i32 7
+ %arrayidx84 = getelementptr inbounds [9 x float], ptr %TIM, i32 0, i32 6
+ %arrayidx92 = getelementptr inbounds [9 x float], ptr %TIM, i32 0, i32 7
%add116 = add nsw i32 %pyh, 15
br label %for.body
for.body: ; preds = %for.cond.cleanup40, %for.body.lr.ph
- %arrayidx.phi = phi float* [ %sX, %for.body.lr.ph ], [ %arrayidx.inc, %for.cond.cleanup40 ]
- %arrayidx4.phi = phi float* [ %sY, %for.body.lr.ph ], [ %arrayidx4.inc, %for.cond.cleanup40 ]
- %0 = load float, float* %arrayidx.phi, align 4
- %1 = load float, float* %arrayidx4.phi, align 4
- %2 = load float, float* %arrayidx12, align 4
+ %arrayidx.phi = phi ptr [ %sX, %for.body.lr.ph ], [ %arrayidx.inc, %for.cond.cleanup40 ]
+ %arrayidx4.phi = phi ptr [ %sY, %for.body.lr.ph ], [ %arrayidx4.inc, %for.cond.cleanup40 ]
+ %0 = load float, ptr %arrayidx.phi, align 4
+ %1 = load float, ptr %arrayidx4.phi, align 4
+ %2 = load float, ptr %arrayidx12, align 4
%add = fadd fast float 0.000000e+00, %2
- %3 = load float, float* %arrayidx20, align 4
+ %3 = load float, ptr %arrayidx20, align 4
%add21 = fadd fast float 0.000000e+00, %3
%mul3.i = fmul fast float %add21, %TM.sroa.8.0.copyload
%add.i = fadd fast float 0.000000e+00, %TM.sroa.11.0.copyload
@@ -52,23 +52,23 @@ for.body: ; preds = %for.cond.cleanup40, %for.body.lr.ph
%mul8.i = fmul fast float %add, %TM.sroa.0.0.copyload
%add11.i = fadd fast float %mul8.i, %TM.sroa.9.0.copyload
%add13.i = fadd fast float %add11.i, 0.000000e+00
- %4 = load float, float* %arrayidx24, align 4
+ %4 = load float, ptr %arrayidx24, align 4
%mul14.i = fmul fast float %add13.i, %4
%mul25 = fmul fast float %mul14.i, %conv6.i
%add29 = fadd fast float %mul25, 0.000000e+00
- %arrayidx.inc = getelementptr float, float* %arrayidx.phi, i32 1
- %arrayidx4.inc = getelementptr float, float* %arrayidx4.phi, i32 1
+ %arrayidx.inc = getelementptr float, ptr %arrayidx.phi, i32 1
+ %arrayidx4.inc = getelementptr float, ptr %arrayidx4.phi, i32 1
%conv64.1 = sitofp i32 undef to float
%conv64.6 = sitofp i32 undef to float
br label %for.body41
for.cond.cleanup40: ; preds = %for.body41
- %call = call fast float undef(%struct.r* nonnull %this, float* undef, i32 49)
+ %call = call fast float undef(ptr nonnull %this, ptr undef, i32 49)
br label %for.body
for.body41: ; preds = %for.cond.cleanup56.for.body41_crit_edge, %for.body
%5 = phi float [ 0.000000e+00, %for.body ], [ %.pre, %for.cond.cleanup56.for.body41_crit_edge ]
- %sFVData.0840 = phi float* [ undef, %for.body ], [ undef, %for.cond.cleanup56.for.body41_crit_edge ]
+ %sFVData.0840 = phi ptr [ undef, %for.body ], [ undef, %for.cond.cleanup56.for.body41_crit_edge ]
%dx.0838 = phi i32 [ -3, %for.body ], [ undef, %for.cond.cleanup56.for.body41_crit_edge ]
%conv42 = sitofp i32 %dx.0838 to float
%add43 = fadd fast float %conv42, %add29
@@ -82,36 +82,36 @@ for.body41: ; preds = %for.cond.cleanup56.for.body41_crit_edg
%cmp132 = icmp sgt i32 undef, -16
%cond137 = select i1 %cmp132, i32 undef, i32 -16
%cond153 = select i1 undef, i32 %cond137, i32 undef
- %add.ptr = getelementptr inbounds i8, i8* %sdata, i32 %cond153
+ %add.ptr = getelementptr inbounds i8, ptr %sdata, i32 %cond153
%mul154 = mul nsw i32 %cond.add116, %siW
- %add.ptr155 = getelementptr inbounds i8, i8* %add.ptr, i32 %mul154
- %6 = load i8, i8* %add.ptr155, align 1
+ %add.ptr155 = getelementptr inbounds i8, ptr %add.ptr, i32 %mul154
+ %6 = load i8, ptr %add.ptr155, align 1
%conv157 = uitofp i8 %6 to float
- %incdec.ptr = getelementptr inbounds float, float* %sFVData.0840, i32 1
- store float %conv157, float* %sFVData.0840, align 4
- %7 = load float, float* %arrayidx15, align 4
+ %incdec.ptr = getelementptr inbounds float, ptr %sFVData.0840, i32 1
+ store float %conv157, ptr %sFVData.0840, align 4
+ %7 = load float, ptr %arrayidx15, align 4
%mul65.1 = fmul fast float %7, %conv64.1
- %8 = load float, float* %arrayidx20, align 4
+ %8 = load float, ptr %arrayidx20, align 4
%add69.1 = fadd fast float %mul65.1, %8
%conv78.1 = fdiv fast float 1.000000e+00, 0.000000e+00
- %9 = load float, float* undef, align 4
+ %9 = load float, ptr undef, align 4
%mul80.1 = fmul fast float %9, %add53
- %10 = load float, float* undef, align 4
+ %10 = load float, ptr undef, align 4
%mul82.1 = fmul fast float %10, %add69.1
%add83.1 = fadd fast float %mul82.1, %mul80.1
- %11 = load float, float* %arrayidx84, align 4
+ %11 = load float, ptr %arrayidx84, align 4
%add85.1 = fadd fast float %add83.1, %11
%mul86.1 = fmul fast float %add85.1, %conv78.1
- %12 = load float, float* %arrayidx92, align 4
+ %12 = load float, ptr %arrayidx92, align 4
%add93.1 = fadd fast float 0.000000e+00, %12
%mul94.1 = fmul fast float %add93.1, %conv78.1
- %13 = load float, float* %arrayidx24, align 4
+ %13 = load float, ptr %arrayidx24, align 4
%mul98.1 = fmul fast float %mul86.1, %13
- %14 = load float, float* %arrayidx28, align 4
+ %14 = load float, ptr %arrayidx28, align 4
%add102.1 = fadd fast float %mul98.1, %14
- %15 = load float, float* %arrayidx32, align 4
+ %15 = load float, ptr %arrayidx32, align 4
%mul106.1 = fmul fast float %mul94.1, %15
- %16 = load float, float* %arrayidx36, align 4
+ %16 = load float, ptr %arrayidx36, align 4
%add110.1 = fadd fast float %mul106.1, %16
%conv111.1 = fptosi float %add102.1 to i32
%conv112.1 = fptosi float %add110.1 to i32
@@ -119,45 +119,43 @@ for.body41: ; preds = %for.cond.cleanup56.for.body41_crit_edg
%cond.add116.1 = select i1 undef, i32 %cond.1, i32 %add116
%cond137.1 = select i1 undef, i32 %conv112.1, i32 -16
%cond153.1 = select i1 undef, i32 %cond137.1, i32 undef
- %add.ptr.1 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.1
+ %add.ptr.1 = getelementptr inbounds i8, ptr %sdata, i32 %cond153.1
%mul154.1 = mul nsw i32 %cond.add116.1, %siW
- %add.ptr155.1 = getelementptr inbounds i8, i8* %add.ptr.1, i32 %mul154.1
- %17 = load i8, i8* %add.ptr155.1, align 1
+ %add.ptr155.1 = getelementptr inbounds i8, ptr %add.ptr.1, i32 %mul154.1
+ %17 = load i8, ptr %add.ptr155.1, align 1
%conv157.1 = uitofp i8 %17 to float
- %incdec.ptr.1 = getelementptr inbounds float, float* %sFVData.0840, i32 2
- store float %conv157.1, float* %incdec.ptr, align 4
+ %incdec.ptr.1 = getelementptr inbounds float, ptr %sFVData.0840, i32 2
+ store float %conv157.1, ptr %incdec.ptr, align 4
%conv112.2 = fptosi float undef to i32
%cond137.2 = select i1 undef, i32 %conv112.2, i32 -16
%cond153.2 = select i1 undef, i32 %cond137.2, i32 undef
- %add.ptr.2 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.2
- %add.ptr155.2 = getelementptr inbounds i8, i8* %add.ptr.2, i32 0
- %18 = load i8, i8* %add.ptr155.2, align 1
+ %add.ptr.2 = getelementptr inbounds i8, ptr %sdata, i32 %cond153.2
+ %18 = load i8, ptr %add.ptr.2, align 1
%conv157.2 = uitofp i8 %18 to float
- %incdec.ptr.2 = getelementptr inbounds float, float* %sFVData.0840, i32 3
- store float %conv157.2, float* %incdec.ptr.1, align 4
+ %incdec.ptr.2 = getelementptr inbounds float, ptr %sFVData.0840, i32 3
+ store float %conv157.2, ptr %incdec.ptr.1, align 4
%cmp132.3 = icmp sgt i32 undef, -16
%cond137.3 = select i1 %cmp132.3, i32 undef, i32 -16
%cond153.3 = select i1 undef, i32 %cond137.3, i32 undef
- %add.ptr.3 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.3
- %add.ptr155.3 = getelementptr inbounds i8, i8* %add.ptr.3, i32 0
- %19 = load i8, i8* %add.ptr155.3, align 1
+ %add.ptr.3 = getelementptr inbounds i8, ptr %sdata, i32 %cond153.3
+ %19 = load i8, ptr %add.ptr.3, align 1
%conv157.3 = uitofp i8 %19 to float
- store float %conv157.3, float* %incdec.ptr.2, align 4
- %incdec.ptr.5 = getelementptr inbounds float, float* %sFVData.0840, i32 6
- %20 = load float, float* %arrayidx15, align 4
+ store float %conv157.3, ptr %incdec.ptr.2, align 4
+ %incdec.ptr.5 = getelementptr inbounds float, ptr %sFVData.0840, i32 6
+ %20 = load float, ptr %arrayidx15, align 4
%mul65.6 = fmul fast float %20, %conv64.6
- %21 = load float, float* %arrayidx20, align 4
+ %21 = load float, ptr %arrayidx20, align 4
%add69.6 = fadd fast float %mul65.6, %21
%conv78.6 = fdiv fast float 1.000000e+00, 0.000000e+00
- %22 = load float, float* undef, align 4
+ %22 = load float, ptr undef, align 4
%mul82.6 = fmul fast float %22, %add69.6
%add83.6 = fadd fast float %mul82.6, 0.000000e+00
- %23 = load float, float* %arrayidx84, align 4
+ %23 = load float, ptr %arrayidx84, align 4
%add85.6 = fadd fast float %add83.6, %23
%mul86.6 = fmul fast float %add85.6, %conv78.6
- %24 = load float, float* %arrayidx24, align 4
+ %24 = load float, ptr %arrayidx24, align 4
%mul98.6 = fmul fast float %mul86.6, %24
- %25 = load float, float* %arrayidx28, align 4
+ %25 = load float, ptr %arrayidx28, align 4
%add102.6 = fadd fast float %mul98.6, %25
%conv111.6 = fptosi float %add102.6 to i32
%conv112.6 = fptosi float undef to i32
@@ -166,17 +164,17 @@ for.body41: ; preds = %for.cond.cleanup56.for.body41_crit_edg
%cmp132.6 = icmp sgt i32 %conv112.6, -16
%cond137.6 = select i1 %cmp132.6, i32 %conv112.6, i32 -16
%cond153.6 = select i1 undef, i32 %cond137.6, i32 undef
- %add.ptr.6 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.6
+ %add.ptr.6 = getelementptr inbounds i8, ptr %sdata, i32 %cond153.6
%mul154.6 = mul nsw i32 %cond.add116.6, %siW
- %add.ptr155.6 = getelementptr inbounds i8, i8* %add.ptr.6, i32 %mul154.6
- %26 = load i8, i8* %add.ptr155.6, align 1
+ %add.ptr155.6 = getelementptr inbounds i8, ptr %add.ptr.6, i32 %mul154.6
+ %26 = load i8, ptr %add.ptr155.6, align 1
%conv157.6 = uitofp i8 %26 to float
- store float %conv157.6, float* %incdec.ptr.5, align 4
+ store float %conv157.6, ptr %incdec.ptr.5, align 4
%exitcond874 = icmp eq i32 %dx.0838, 3
br i1 %exitcond874, label %for.cond.cleanup40, label %for.cond.cleanup56.for.body41_crit_edge
for.cond.cleanup56.for.body41_crit_edge: ; preds = %for.body41
- %.pre = load float, float* %arrayidx8, align 4
+ %.pre = load float, ptr %arrayidx8, align 4
br label %for.body41
if.then343: ; preds = %entry
diff --git a/llvm/test/CodeGen/ARM/2016-08-24-ARM-LDST-dbginfo-bug.ll b/llvm/test/CodeGen/ARM/2016-08-24-ARM-LDST-dbginfo-bug.ll
index 10a657c2afc2a..8668bcf05c4f4 100644
--- a/llvm/test/CodeGen/ARM/2016-08-24-ARM-LDST-dbginfo-bug.ll
+++ b/llvm/test/CodeGen/ARM/2016-08-24-ARM-LDST-dbginfo-bug.ll
@@ -2,27 +2,26 @@
; When using -Oz and -g, this code generated an abort in the ARM load/store optimizer.
-%struct.s = type { %struct.s* }
+%struct.s = type { ptr }
; Function Attrs: minsize nounwind optsize readonly
-define %struct.s* @s_idx(%struct.s* readonly %xl) local_unnamed_addr #0 !dbg !8 {
+define ptr @s_idx(ptr readonly %xl) local_unnamed_addr #0 !dbg !8 {
entry:
- tail call void @llvm.dbg.value(metadata %struct.s* %xl, metadata !17, metadata !18), !dbg !19
+ tail call void @llvm.dbg.value(metadata ptr %xl, metadata !17, metadata !18), !dbg !19
br label %while.cond, !dbg !20
while.cond: ; preds = %while.body, %entry
- %xl.addr.0 = phi %struct.s* [ %xl, %entry ], [ %0, %while.body ]
- %tobool = icmp eq %struct.s* %xl.addr.0, null
+ %xl.addr.0 = phi ptr [ %xl, %entry ], [ %0, %while.body ]
+ %tobool = icmp eq ptr %xl.addr.0, null
br i1 %tobool, label %while.end, label %while.body
while.body: ; preds = %while.cond
- %next = getelementptr inbounds %struct.s, %struct.s* %xl.addr.0, i32 0, i32 0
- %0 = load %struct.s*, %struct.s** %next, align 4
- tail call void @llvm.dbg.value(metadata %struct.s* %0, metadata !17, metadata !18), !dbg !19
+ %0 = load ptr, ptr %xl.addr.0, align 4
+ tail call void @llvm.dbg.value(metadata ptr %0, metadata !17, metadata !18), !dbg !19
br label %while.cond
while.end: ; preds = %while.cond
- ret %struct.s* null
+ ret ptr null
}
; Function Attrs: nounwind readnone
diff --git a/llvm/test/CodeGen/ARM/2018-02-13-PR36079.ll b/llvm/test/CodeGen/ARM/2018-02-13-PR36079.ll
index 04585b194ddff..da6aa117ef413 100644
--- a/llvm/test/CodeGen/ARM/2018-02-13-PR36079.ll
+++ b/llvm/test/CodeGen/ARM/2018-02-13-PR36079.ll
@@ -5,13 +5,13 @@
define void @foo() local_unnamed_addr nounwind norecurse {
entry:
- %0 = load <4 x i32>, <4 x i32>* bitcast ([4 x i32]* @c to <4 x i32>*), align 4
+ %0 = load <4 x i32>, ptr @c, align 4
%1 = and <4 x i32> %0,
<i32 1,
- i32 zext (i1 icmp ne (i32* getelementptr inbounds ([4 x i32], [4 x i32]* @c, i32 0, i32 1), i32* @d) to i32),
- i32 zext (i1 icmp ne (i32* getelementptr inbounds ([4 x i32], [4 x i32]* @c, i32 0, i32 2), i32* @d) to i32),
- i32 zext (i1 icmp ne (i32* getelementptr inbounds ([4 x i32], [4 x i32]* @c, i32 0, i32 3), i32* @d) to i32)>
- store <4 x i32> %1, <4 x i32>* bitcast ([4 x i32]* @c to <4 x i32>*), align 4
+ i32 zext (i1 icmp ne (ptr getelementptr inbounds ([4 x i32], ptr @c, i32 0, i32 1), ptr @d) to i32),
+ i32 zext (i1 icmp ne (ptr getelementptr inbounds ([4 x i32], ptr @c, i32 0, i32 2), ptr @d) to i32),
+ i32 zext (i1 icmp ne (ptr getelementptr inbounds ([4 x i32], ptr @c, i32 0, i32 3), ptr @d) to i32)>
+ store <4 x i32> %1, ptr @c, align 4
ret void
; CHECK-NOT: mvnne
; CHECK: movne r{{[0-9]+}}, #1
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
index b50460a647530..290b5b8a298f9 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
@@ -4,7 +4,7 @@
; RUN: llc -mtriple arm-unknown -mattr=+v5t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=V5T
; RUN: llc -mtriple thumb-unknown -mattr=+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=THUMB
-define arm_aapcscc void @test_indirect_call(void() *%fptr) {
+define arm_aapcscc void @test_indirect_call(ptr %fptr) {
; NOV4T-LABEL: name: test_indirect_call
; NOV4T: bb.1.entry:
; NOV4T: liveins: $r0
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
index f7e58c4355172..411cf78b621f8 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
@@ -238,17 +238,17 @@ entry:
ret i16 %p5
}
-define i16 @test_ptr_arg(i16* %p) {
+define i16 @test_ptr_arg(ptr %p) {
; CHECK-LABEL: name: test_ptr_arg
; CHECK: liveins: $r0
; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY $r0
; CHECK: [[VREGV:%[0-9]+]]:_(s16) = G_LOAD [[VREGP]](p0){{.*}}load (s16)
entry:
- %v = load i16, i16* %p
+ %v = load i16, ptr %p
ret i16 %v
}
-define i32* @test_ptr_ret(i32** %p) {
+define ptr @test_ptr_ret(ptr %p) {
; Test pointer returns and pointer-to-pointer arguments
; CHECK-LABEL: name: test_ptr_ret
; CHECK: liveins: $r0
@@ -257,11 +257,11 @@ define i32* @test_ptr_ret(i32** %p) {
; CHECK: $r0 = COPY [[VREGV]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
- %v = load i32*, i32** %p
- ret i32* %v
+ %v = load ptr, ptr %p
+ ret ptr %v
}
-define i32 @test_ptr_arg_on_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32* %p) {
+define i32 @test_ptr_arg_on_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, ptr %p) {
; CHECK-LABEL: name: test_ptr_arg_on_stack
; CHECK: fixedStack:
; CHECK: id: [[P:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
@@ -272,7 +272,7 @@ define i32 @test_ptr_arg_on_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32* %p) {
; CHECK: $r0 = COPY [[VREGV]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
- %v = load i32, i32* %p
+ %v = load i32, ptr %p
ret i32 %v
}
@@ -554,7 +554,7 @@ define i32 @test_constantstruct_v2s32_s32_s32() {
ret i32 %elt
}
-define void @test_load_store_struct({i32, i32} *%addr) {
+define void @test_load_store_struct(ptr %addr) {
; Make sure the IRTranslator doesn't use an unnecessarily large GEP index type
; when breaking up loads and stores of aggregates.
; CHECK-LABEL: name: test_load_store_struct
@@ -566,7 +566,7 @@ define void @test_load_store_struct({i32, i32} *%addr) {
; CHECK-DAG: G_STORE [[VAL1]](s32), [[ADDR1]](p0) :: (store (s32) into %ir.addr)
; CHECK-DAG: [[ADDR3:%[0-9]+]]:_(p0) = COPY [[ADDR2]]
; CHECK-DAG: G_STORE [[VAL2]](s32), [[ADDR3]](p0) :: (store (s32) into %ir.addr + 4)
- %val = load {i32, i32}, {i32, i32} *%addr, align 4
- store {i32, i32} %val, {i32, i32} *%addr, align 4
+ %val = load {i32, i32}, ptr %addr, align 4
+ store {i32, i32} %val, ptr %addr, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-pic.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-pic.ll
index 389ae7933c7e1..80d687ba0f53d 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-pic.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-pic.ll
@@ -22,7 +22,7 @@ define i32 @test_internal_global() {
; DARWIN-MOVT-NOT: .long _internal_global
entry:
- %v = load i32, i32* @internal_global
+ %v = load i32, ptr @internal_global
ret i32 %v
}
@@ -46,7 +46,7 @@ define i32 @test_external_global() {
; DARWIN-NOMOVT: .long L_external_global$non_lazy_ptr-([[ANCHOR]]+8)
; DARWIN-NOMOVT-NOT: .long L_external_global
entry:
- %v = load i32, i32* @external_global
+ %v = load i32, ptr @external_global
ret i32 %v
}
@@ -69,7 +69,7 @@ define i32 @test_internal_constant() {
; DARWIN-MOVT-NOT: .long _internal_constant
entry:
- %v = load i32, i32* @internal_constant
+ %v = load i32, ptr @internal_constant
ret i32 %v
}
@@ -93,7 +93,7 @@ define i32 @test_external_constant() {
; DARWIN-NOMOVT: .long L_external_constant$non_lazy_ptr-([[ANCHOR]]+8)
; DARWIN-NOMOVT-NOT: .long L_external_constant
entry:
- %v = load i32, i32* @external_constant
+ %v = load i32, ptr @external_constant
ret i32 %v
}
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-ropi-rwpi.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-ropi-rwpi.ll
index f52fb769c1ef7..3c0777bd9c39d 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-ropi-rwpi.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-ropi-rwpi.ll
@@ -25,7 +25,7 @@ define i32 @test_internal_global() {
; RWPI-NOMOVT: [[LABEL]]:
; RWPI-NOMOVT-NEXT: .long internal_global(sbrel)
entry:
- %v = load i32, i32* @internal_global
+ %v = load i32, ptr @internal_global
ret i32 %v
}
@@ -49,7 +49,7 @@ define i32 @test_external_global() {
; RWPI-NOMOVT: [[LABEL]]:
; RWPI-NOMOVT-NEXT: .long external_global(sbrel)
entry:
- %v = load i32, i32* @external_global
+ %v = load i32, ptr @external_global
ret i32 %v
}
@@ -75,7 +75,7 @@ define i32 @test_internal_constant() {
; RO-DEFAULT-NOMOVT: [[LABEL]]:
; RO-DEFAULT-NOMOVT-NEXT: .long internal_constant
entry:
- %v = load i32, i32* @internal_constant
+ %v = load i32, ptr @internal_constant
ret i32 %v
}
@@ -101,7 +101,7 @@ define i32 @test_external_constant() {
; RO-DEFAULT-NOMOVT: [[LABEL]]:
; RO-DEFAULT-NOMOVT: .long external_constant
entry:
- %v = load i32, i32* @external_constant
+ %v = load i32, ptr @external_constant
ret i32 %v
}
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-static.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-static.ll
index 745b9a249e7bb..8ebab12726028 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-static.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-static.ll
@@ -20,7 +20,7 @@ define i32 @test_internal_global() {
; DARWIN-NOMOVT-NEXT: .long _internal_global
entry:
- %v = load i32, i32* @internal_global
+ %v = load i32, ptr @internal_global
ret i32 %v
}
@@ -40,7 +40,7 @@ define i32 @test_external_global() {
; DARWIN-NOMOVT: [[LABEL]]:
; DARWIN-NOMOVT: .long _external_global
entry:
- %v = load i32, i32* @external_global
+ %v = load i32, ptr @external_global
ret i32 %v
}
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll
index b7ded75d5da3c..2161b40ee9393 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll
@@ -52,7 +52,7 @@ entry:
ret i16 %x
}
-define void @test_trunc_i32_i16(i32 %v, i16 *%p) {
+define void @test_trunc_i32_i16(i32 %v, ptr %p) {
; CHECK-LABEL: test_trunc_i32_i16:
; The trunc doesn't result in any instructions, but we
; expect the store to be explicitly 16-bit.
@@ -60,11 +60,11 @@ define void @test_trunc_i32_i16(i32 %v, i16 *%p) {
; CHECK: bx lr
entry:
%v16 = trunc i32 %v to i16
- store i16 %v16, i16 *%p
+ store i16 %v16, ptr %p
ret void
}
-define void @test_trunc_i32_i8(i32 %v, i8 *%p) {
+define void @test_trunc_i32_i8(i32 %v, ptr %p) {
; CHECK-LABEL: test_trunc_i32_i8:
; The trunc doesn't result in any instructions, but we
; expect the store to be explicitly 8-bit.
@@ -72,7 +72,7 @@ define void @test_trunc_i32_i8(i32 %v, i8 *%p) {
; CHECK: bx lr
entry:
%v8 = trunc i32 %v to i8
- store i8 %v8, i8 *%p
+ store i8 %v8, ptr %p
ret void
}
@@ -293,33 +293,33 @@ entry:
ret i8 %sum
}
-define i32 @test_ptr_arg_in_reg(i32* %p) {
+define i32 @test_ptr_arg_in_reg(ptr %p) {
; CHECK-LABEL: test_ptr_arg_in_reg:
; CHECK: ldr r0, [r0]
; CHECK: bx lr
entry:
- %v = load i32, i32* %p
+ %v = load i32, ptr %p
ret i32 %v
}
-define i32 @test_ptr_arg_on_stack(i32 %f0, i32 %f1, i32 %f2, i32 %f3, i32* %p) {
+define i32 @test_ptr_arg_on_stack(i32 %f0, i32 %f1, i32 %f2, i32 %f3, ptr %p) {
; CHECK-LABEL: test_ptr_arg_on_stack:
; CHECK: mov r0, sp
; CHECK: ldr r0, [r0]
; CHECK: ldr r0, [r0]
; CHECK: bx lr
entry:
- %v = load i32, i32* %p
+ %v = load i32, ptr %p
ret i32 %v
}
-define i8* @test_ptr_ret(i8** %p) {
+define ptr @test_ptr_ret(ptr %p) {
; CHECK-LABEL: test_ptr_ret:
; CHECK: ldr r0, [r0]
; CHECK: bx lr
entry:
- %v = load i8*, i8** %p
- ret i8* %v
+ %v = load ptr, ptr %p
+ ret ptr %v
}
define arm_aapcs_vfpcc float @test_float_hard(float %f0, float %f1) {
@@ -377,7 +377,7 @@ entry:
ret i32 %r
}
-define arm_aapcscc i32 @test_cmp_ptr_neq(double *%a, double *%b) {
+define arm_aapcscc i32 @test_cmp_ptr_neq(ptr %a, ptr %b) {
; CHECK-LABEL: test_cmp_ptr_neq:
; CHECK: mov [[V:r[0-9]+]], #0
; CHECK: cmp r0, r1
@@ -385,7 +385,7 @@ define arm_aapcscc i32 @test_cmp_ptr_neq(double *%a, double *%b) {
; CHECK: and r0, [[V]], #1
; CHECK: bx lr
entry:
- %v = icmp ne double * %a, %b
+ %v = icmp ne ptr %a, %b
%r = zext i1 %v to i32
ret i32 %r
}
@@ -413,14 +413,14 @@ entry:
ret i32 %r
}
-define arm_aapcscc i32* @test_select_ptr(i32* %a, i32* %b, i1 %cond) {
+define arm_aapcscc ptr @test_select_ptr(ptr %a, ptr %b, i1 %cond) {
; CHECK-LABEL: test_select_ptr
; CHECK: tst r2, #1
; CHECK: moveq r0, r1
; CHECK: bx lr
entry:
- %r = select i1 %cond, i32* %a, i32* %b
- ret i32* %r
+ %r = select i1 %cond, ptr %a, ptr %b
+ ret ptr %r
}
define arm_aapcscc void @test_br() {
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
index 268c3ccc623da..e8cd182196b62 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
@@ -2,9 +2,9 @@
; RUN: llc -O0 -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -global-isel-abort=0 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM -check-prefix=BIG
; RUN: llc -O0 -mtriple thumb-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE -check-prefix=THUMB
-declare arm_aapcscc i32* @simple_reg_params_target(i32, i32*)
+declare arm_aapcscc ptr @simple_reg_params_target(i32, ptr)
-define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) {
+define arm_aapcscc ptr @test_call_simple_reg_params(ptr %a, i32 %b) {
; CHECK-LABEL: name: test_call_simple_reg_params
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1
@@ -19,13 +19,13 @@ define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) {
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
- %r = notail call arm_aapcscc i32 *@simple_reg_params_target(i32 %b, i32 *%a)
- ret i32 *%r
+ %r = notail call arm_aapcscc ptr @simple_reg_params_target(i32 %b, ptr %a)
+ ret ptr %r
}
-declare arm_aapcscc i32* @simple_stack_params_target(i32, i32*, i32, i32*, i32, i32*)
+declare arm_aapcscc ptr @simple_stack_params_target(i32, ptr, i32, ptr, i32, ptr)
-define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) {
+define arm_aapcscc ptr @test_call_simple_stack_params(ptr %a, i32 %b) {
; CHECK-LABEL: name: test_call_simple_stack_params
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1
@@ -50,8 +50,8 @@ define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) {
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
- %r = notail call arm_aapcscc i32 *@simple_stack_params_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a)
- ret i32 *%r
+ %r = notail call arm_aapcscc ptr @simple_stack_params_target(i32 %b, ptr %a, i32 %b, ptr %a, i32 %b, ptr %a)
+ ret ptr %r
}
declare arm_aapcscc signext i16 @ext_target(i8 signext, i8 zeroext, i16 signext, i16 zeroext, i8 signext, i8 zeroext, i16 signext, i16 zeroext, i1 zeroext)
@@ -403,9 +403,9 @@ entry:
ret [4 x float] %r
}
-declare arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr)
+declare arm_aapcscc [2 x ptr] @tough_arrays_target([6 x [4 x i32]] %arr)
-define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) {
+define arm_aapcscc [2 x ptr] @test_tough_arrays([6 x [4 x i32]] %arr) {
; CHECK-LABEL: name: test_tough_arrays
; CHECK: fixedStack:
; The parameters live in separate stack locations, one for each element that
@@ -446,8 +446,8 @@ define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) {
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
entry:
- %r = notail call arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr)
- ret [2 x i32*] %r
+ %r = notail call arm_aapcscc [2 x ptr] @tough_arrays_target([6 x [4 x i32]] %arr)
+ ret [2 x ptr] %r
}
declare arm_aapcscc {i32, i32} @structs_target({i32, i32})
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll
index d4ad3b5ebdc64..8e354dcd47549 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll
@@ -8,41 +8,41 @@
; be unsupported on the ARM target. It should progressively shrink in size.
define <4 x i32> @test_int_vectors(<4 x i32> %a, <4 x i32> %b) {
-; CHECK: remark: {{.*}} unable to lower arguments: <4 x i32> (<4 x i32>, <4 x i32>)*
+; CHECK: remark: {{.*}} unable to lower arguments: ptr
; CHECK-LABEL: warning: Instruction selection used fallback path for test_int_vectors
%res = add <4 x i32> %a, %b
ret <4 x i32> %res
}
define <4 x float> @test_float_vectors(<4 x float> %a, <4 x float> %b) {
-; CHECK: remark: {{.*}} unable to lower arguments: <4 x float> (<4 x float>, <4 x float>)*
+; CHECK: remark: {{.*}} unable to lower arguments: ptr
; CHECK-LABEL: warning: Instruction selection used fallback path for test_float_vectors
%res = fadd <4 x float> %a, %b
ret <4 x float> %res
}
define i64 @test_i64(i64 %a, i64 %b) {
-; CHECK: remark: {{.*}} unable to lower arguments: i64 (i64, i64)*
+; CHECK: remark: {{.*}} unable to lower arguments: ptr
; CHECK-LABEL: warning: Instruction selection used fallback path for test_i64
%res = add i64 %a, %b
ret i64 %res
}
define void @test_i64_arr([1 x i64] %a) {
-; CHECK: remark: {{.*}} unable to lower arguments: void ([1 x i64])*
+; CHECK: remark: {{.*}} unable to lower arguments: ptr
; CHECK-LABEL: warning: Instruction selection used fallback path for test_i64_arr
ret void
}
define i128 @test_i128(i128 %a, i128 %b) {
-; CHECK: remark: {{.*}} unable to lower arguments: i128 (i128, i128)*
+; CHECK: remark: {{.*}} unable to lower arguments: ptr
; CHECK-LABEL: warning: Instruction selection used fallback path for test_i128
%res = add i128 %a, %b
ret i128 %res
}
define i17 @test_funny_ints(i17 %a, i17 %b) {
-; CHECK: remark: {{.*}} unable to lower arguments: i17 (i17, i17)*
+; CHECK: remark: {{.*}} unable to lower arguments: ptr
; CHECK-LABEL: warning: Instruction selection used fallback path for test_funny_ints
%res = add i17 %a, %b
ret i17 %res
@@ -75,10 +75,10 @@ define %large.struct @test_large_struct_return() {
ret %large.struct %r
}
-%mixed.struct = type {i32*, float, i32}
+%mixed.struct = type {ptr, float, i32}
define %mixed.struct @test_mixed_struct(%mixed.struct %x) {
-; CHECK: remark: {{.*}} unable to lower arguments: %mixed.struct (%mixed.struct)*
+; CHECK: remark: {{.*}} unable to lower arguments: ptr
; CHECK-LABEL: warning: Instruction selection used fallback path for test_mixed_struct
ret %mixed.struct %x
}
@@ -86,19 +86,19 @@ define %mixed.struct @test_mixed_struct(%mixed.struct %x) {
%bad.element.type = type {i24, i24}
define void @test_bad_element_struct(%bad.element.type %x) {
-; CHECK: remark: {{.*}} unable to lower arguments: void (%bad.element.type)*
+; CHECK: remark: {{.*}} unable to lower arguments: ptr
; CHECK-LABEL: warning: Instruction selection used fallback path for test_bad_element_struct
ret void
}
define void @test_vararg_definition(i32 %a, ...) {
-; CHECK: remark: {{.*}} unable to lower arguments: void (i32, ...)*
+; CHECK: remark: {{.*}} unable to lower arguments: ptr
; CHECK-LABEL: warning: Instruction selection used fallback path for test_vararg_definition
ret void
}
define i32 @test_thumb(i32 %a) #0 {
-; CHECK: remark: {{.*}} unable to lower arguments: i32 (i32)*
+; CHECK: remark: {{.*}} unable to lower arguments: ptr
; CHECK-LABEL: warning: Instruction selection used fallback path for test_thumb
ret i32 %a
}
@@ -116,22 +116,22 @@ define i32 @test_thread_local_global() {
; RWPI-LABEL: warning: Instruction selection used fallback path for test_thread_local_global
; ROPI-RWPI: remark: {{.*}} cannot select: {{.*}} G_GLOBAL_VALUE
; ROPI-RWPI-LABEL: warning: Instruction selection used fallback path for test_thread_local_global
- %v = load i32, i32* @thread_local_global
+ %v = load i32, ptr @thread_local_global
ret i32 %v
}
%byval.class = type { i32 }
-define void @test_byval_arg(%byval.class* byval(%byval.class) %x) {
-; CHECK: remark: {{.*}} unable to lower arguments: void (%byval.class*)*
+define void @test_byval_arg(ptr byval(%byval.class) %x) {
+; CHECK: remark: {{.*}} unable to lower arguments: ptr
; CHECK-LABEL: warning: Instruction selection used fallback path for test_byval
ret void
}
-define void @test_byval_param(%byval.class* %x) {
+define void @test_byval_param(ptr %x) {
; CHECK: remark: {{.*}} unable to translate instruction: call
; CHECK-LABEL: warning: Instruction selection used fallback path for test_byval_param
- call void @test_byval_arg(%byval.class* byval(%byval.class) %x)
+ call void @test_byval_arg(ptr byval(%byval.class) %x)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll b/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
index 0b75d67327368..daae1b7a094e7 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
@@ -3,7 +3,7 @@
declare arm_aapcscc i32 @int_varargs_target(i32, ...)
-define arm_aapcscc i32 @test_call_to_varargs_with_ints(i32 *%a, i32 %b) {
+define arm_aapcscc i32 @test_call_to_varargs_with_ints(ptr %a, i32 %b) {
; CHECK-LABEL: name: test_call_to_varargs_with_ints
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1
@@ -28,7 +28,7 @@ define arm_aapcscc i32 @test_call_to_varargs_with_ints(i32 *%a, i32 %b) {
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
- %r = notail call arm_aapcscc i32(i32, ...) @int_varargs_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a)
+ %r = notail call arm_aapcscc i32(i32, ...) @int_varargs_target(i32 %b, ptr %a, i32 %b, ptr %a, i32 %b, ptr %a)
ret i32 %r
}
@@ -80,7 +80,7 @@ entry:
ret float %r
}
-define arm_aapcs_vfpcc float @test_indirect_call_to_varargs(float (float, double, ...) *%fptr, float %a, double %b) {
+define arm_aapcs_vfpcc float @test_indirect_call_to_varargs(ptr %fptr, float %a, double %b) {
; CHECK-LABEL: name: test_indirect_call_to_varargs
; CHECK-DAG: [[FPTRVREG:%[0-9]+]]:gpr(p0) = COPY $r0
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s32) = COPY $s0
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-pic.ll b/llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-pic.ll
index 85058506824c9..e6828a52f2941 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-pic.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-pic.ll
@@ -22,7 +22,7 @@ define i32 @test_internal_global() {
; DARWIN-MOVT-NOT: .long _internal_global
entry:
- %v = load i32, i32* @internal_global
+ %v = load i32, ptr @internal_global
ret i32 %v
}
@@ -46,7 +46,7 @@ define i32 @test_external_global() {
; DARWIN-NOMOVT: .long L_external_global$non_lazy_ptr-([[ANCHOR]]+4)
; DARWIN-NOMOVT-NOT: .long L_external_global
entry:
- %v = load i32, i32* @external_global
+ %v = load i32, ptr @external_global
ret i32 %v
}
@@ -69,7 +69,7 @@ define i32 @test_internal_constant() {
; DARWIN-MOVT-NOT: .long _internal_constant
entry:
- %v = load i32, i32* @internal_constant
+ %v = load i32, ptr @internal_constant
ret i32 %v
}
@@ -93,7 +93,7 @@ define i32 @test_external_constant() {
; DARWIN-NOMOVT: .long L_external_constant$non_lazy_ptr-([[ANCHOR]]+4)
; DARWIN-NOMOVT-NOT: .long L_external_constant
entry:
- %v = load i32, i32* @external_constant
+ %v = load i32, ptr @external_constant
ret i32 %v
}
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-ropi-rwpi.ll b/llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-ropi-rwpi.ll
index 2fbdc2f9e6147..b846eb8d243c4 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-ropi-rwpi.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-ropi-rwpi.ll
@@ -25,7 +25,7 @@ define i32 @test_internal_global() {
; RWPI-NOMOVT: [[LABEL]]:
; RWPI-NOMOVT-NEXT: .long internal_global(sbrel)
entry:
- %v = load i32, i32* @internal_global
+ %v = load i32, ptr @internal_global
ret i32 %v
}
@@ -49,7 +49,7 @@ define i32 @test_external_global() {
; RWPI-NOMOVT: [[LABEL]]:
; RWPI-NOMOVT-NEXT: .long external_global(sbrel)
entry:
- %v = load i32, i32* @external_global
+ %v = load i32, ptr @external_global
ret i32 %v
}
@@ -75,7 +75,7 @@ define i32 @test_internal_constant() {
; RO-DEFAULT-NOMOVT: [[LABEL]]:
; RO-DEFAULT-NOMOVT-NEXT: .long internal_constant
entry:
- %v = load i32, i32* @internal_constant
+ %v = load i32, ptr @internal_constant
ret i32 %v
}
@@ -101,7 +101,7 @@ define i32 @test_external_constant() {
; RO-DEFAULT-NOMOVT: [[LABEL]]:
; RO-DEFAULT-NOMOVT: .long external_constant
entry:
- %v = load i32, i32* @external_constant
+ %v = load i32, ptr @external_constant
ret i32 %v
}
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-static.ll b/llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-static.ll
index 53819b92acfba..bfbf007dc191a 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-static.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-static.ll
@@ -20,7 +20,7 @@ define i32 @test_internal_global() {
; DARWIN-NOMOVT-NEXT: .long _internal_global
entry:
- %v = load i32, i32* @internal_global
+ %v = load i32, ptr @internal_global
ret i32 %v
}
@@ -40,7 +40,7 @@ define i32 @test_external_global() {
; DARWIN-NOMOVT: [[LABEL]]:
; DARWIN-NOMOVT: .long _external_global
entry:
- %v = load i32, i32* @external_global
+ %v = load i32, ptr @external_global
ret i32 %v
}
diff --git a/llvm/test/CodeGen/ARM/MergeConsecutiveStores.ll b/llvm/test/CodeGen/ARM/MergeConsecutiveStores.ll
index 3f7d625244bda..82eab1aebfcd4 100644
--- a/llvm/test/CodeGen/ARM/MergeConsecutiveStores.ll
+++ b/llvm/test/CodeGen/ARM/MergeConsecutiveStores.ll
@@ -5,24 +5,24 @@
; CHECK: MergeLoadStoreBaseIndexOffset
; CHECK: ldrh [[REG:r[0-9]+]], [{{.*}}]
; CHECK: strh [[REG]], [r1], #2
-define void @MergeLoadStoreBaseIndexOffset(i32* %a, i8* %b, i8* %c, i32 %n) {
+define void @MergeLoadStoreBaseIndexOffset(ptr %a, ptr %b, ptr %c, i32 %n) {
br label %1
; <label>:1
%.09 = phi i32 [ %n, %0 ], [ %11, %1 ]
- %.08 = phi i8* [ %b, %0 ], [ %10, %1 ]
- %.0 = phi i32* [ %a, %0 ], [ %2, %1 ]
- %2 = getelementptr inbounds i32, i32* %.0, i32 1
- %3 = load i32, i32* %.0, align 1
- %4 = getelementptr inbounds i8, i8* %c, i32 %3
- %5 = load i8, i8* %4, align 1
+ %.08 = phi ptr [ %b, %0 ], [ %10, %1 ]
+ %.0 = phi ptr [ %a, %0 ], [ %2, %1 ]
+ %2 = getelementptr inbounds i32, ptr %.0, i32 1
+ %3 = load i32, ptr %.0, align 1
+ %4 = getelementptr inbounds i8, ptr %c, i32 %3
+ %5 = load i8, ptr %4, align 1
%6 = add i32 %3, 1
- %7 = getelementptr inbounds i8, i8* %c, i32 %6
- %8 = load i8, i8* %7, align 1
- store i8 %5, i8* %.08, align 1
- %9 = getelementptr inbounds i8, i8* %.08, i32 1
- store i8 %8, i8* %9, align 1
- %10 = getelementptr inbounds i8, i8* %.08, i32 2
+ %7 = getelementptr inbounds i8, ptr %c, i32 %6
+ %8 = load i8, ptr %7, align 1
+ store i8 %5, ptr %.08, align 1
+ %9 = getelementptr inbounds i8, ptr %.08, i32 1
+ store i8 %8, ptr %9, align 1
+ %10 = getelementptr inbounds i8, ptr %.08, i32 2
%11 = add nsw i32 %.09, -1
%12 = icmp eq i32 %11, 0
br i1 %12, label %13, label %1
@@ -37,25 +37,25 @@ define void @MergeLoadStoreBaseIndexOffset(i32* %a, i8* %b, i8* %c, i32 %n) {
; CHECK: MergeLoadStoreBaseIndexOffsetSext
; CHECK: ldrh [[REG:r[0-9]+]], [{{.*}}]
; CHECK: strh [[REG]], [r1], #2
-define void @MergeLoadStoreBaseIndexOffsetSext(i8* %a, i8* %b, i8* %c, i32 %n) {
+define void @MergeLoadStoreBaseIndexOffsetSext(ptr %a, ptr %b, ptr %c, i32 %n) {
br label %1
; <label>:1
%.09 = phi i32 [ %n, %0 ], [ %12, %1 ]
- %.08 = phi i8* [ %b, %0 ], [ %11, %1 ]
- %.0 = phi i8* [ %a, %0 ], [ %2, %1 ]
- %2 = getelementptr inbounds i8, i8* %.0, i32 1
- %3 = load i8, i8* %.0, align 1
+ %.08 = phi ptr [ %b, %0 ], [ %11, %1 ]
+ %.0 = phi ptr [ %a, %0 ], [ %2, %1 ]
+ %2 = getelementptr inbounds i8, ptr %.0, i32 1
+ %3 = load i8, ptr %.0, align 1
%4 = sext i8 %3 to i32
- %5 = getelementptr inbounds i8, i8* %c, i32 %4
- %6 = load i8, i8* %5, align 1
+ %5 = getelementptr inbounds i8, ptr %c, i32 %4
+ %6 = load i8, ptr %5, align 1
%7 = add i32 %4, 1
- %8 = getelementptr inbounds i8, i8* %c, i32 %7
- %9 = load i8, i8* %8, align 1
- store i8 %6, i8* %.08, align 1
- %10 = getelementptr inbounds i8, i8* %.08, i32 1
- store i8 %9, i8* %10, align 1
- %11 = getelementptr inbounds i8, i8* %.08, i32 2
+ %8 = getelementptr inbounds i8, ptr %c, i32 %7
+ %9 = load i8, ptr %8, align 1
+ store i8 %6, ptr %.08, align 1
+ %10 = getelementptr inbounds i8, ptr %.08, i32 1
+ store i8 %9, ptr %10, align 1
+ %11 = getelementptr inbounds i8, ptr %.08, i32 2
%12 = add nsw i32 %.09, -1
%13 = icmp eq i32 %12, 0
br i1 %13, label %14, label %1
@@ -69,26 +69,26 @@ define void @MergeLoadStoreBaseIndexOffsetSext(i8* %a, i8* %b, i8* %c, i32 %n) {
; CHECK: loadStoreBaseIndexOffsetSextNoSex
; CHECK-NOT: ldrh [[REG:r[0-9]+]], [{{.*}}]
; CHECK-NOT: strh [[REG]], [r1], #2
-define void @loadStoreBaseIndexOffsetSextNoSex(i8* %a, i8* %b, i8* %c, i32 %n) {
+define void @loadStoreBaseIndexOffsetSextNoSex(ptr %a, ptr %b, ptr %c, i32 %n) {
br label %1
; <label>:1
%.09 = phi i32 [ %n, %0 ], [ %12, %1 ]
- %.08 = phi i8* [ %b, %0 ], [ %11, %1 ]
- %.0 = phi i8* [ %a, %0 ], [ %2, %1 ]
- %2 = getelementptr inbounds i8, i8* %.0, i32 1
- %3 = load i8, i8* %.0, align 1
+ %.08 = phi ptr [ %b, %0 ], [ %11, %1 ]
+ %.0 = phi ptr [ %a, %0 ], [ %2, %1 ]
+ %2 = getelementptr inbounds i8, ptr %.0, i32 1
+ %3 = load i8, ptr %.0, align 1
%4 = sext i8 %3 to i32
- %5 = getelementptr inbounds i8, i8* %c, i32 %4
- %6 = load i8, i8* %5, align 1
+ %5 = getelementptr inbounds i8, ptr %c, i32 %4
+ %6 = load i8, ptr %5, align 1
%7 = add i8 %3, 1
%wrap.4 = sext i8 %7 to i32
- %8 = getelementptr inbounds i8, i8* %c, i32 %wrap.4
- %9 = load i8, i8* %8, align 1
- store i8 %6, i8* %.08, align 1
- %10 = getelementptr inbounds i8, i8* %.08, i32 1
- store i8 %9, i8* %10, align 1
- %11 = getelementptr inbounds i8, i8* %.08, i32 2
+ %8 = getelementptr inbounds i8, ptr %c, i32 %wrap.4
+ %9 = load i8, ptr %8, align 1
+ store i8 %6, ptr %.08, align 1
+ %10 = getelementptr inbounds i8, ptr %.08, i32 1
+ store i8 %9, ptr %10, align 1
+ %11 = getelementptr inbounds i8, ptr %.08, i32 2
%12 = add nsw i32 %.09, -1
%13 = icmp eq i32 %12, 0
br i1 %13, label %14, label %1
diff --git a/llvm/test/CodeGen/ARM/PR15053.ll b/llvm/test/CodeGen/ARM/PR15053.ll
index 706a90efe3a82..853cdb11cd6eb 100644
--- a/llvm/test/CodeGen/ARM/PR15053.ll
+++ b/llvm/test/CodeGen/ARM/PR15053.ll
@@ -1,13 +1,13 @@
; RUN: llc -mtriple=armv7 < %s
; PR15053
-declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
-declare { i32, i32 } @llvm.arm.ldrexd(i8*) nounwind readonly
+declare i32 @llvm.arm.strexd(i32, i32, ptr) nounwind
+declare { i32, i32 } @llvm.arm.ldrexd(ptr) nounwind readonly
define void @foo() {
entry:
- %0 = tail call { i32, i32 } @llvm.arm.ldrexd(i8* undef) nounwind
+ %0 = tail call { i32, i32 } @llvm.arm.ldrexd(ptr undef) nounwind
%1 = extractvalue { i32, i32 } %0, 0
- %2 = tail call i32 @llvm.arm.strexd(i32 %1, i32 undef, i8* undef) nounwind
+ %2 = tail call i32 @llvm.arm.strexd(i32 %1, i32 undef, ptr undef) nounwind
ret void
}
diff --git a/llvm/test/CodeGen/ARM/PR35379.ll b/llvm/test/CodeGen/ARM/PR35379.ll
index b99ca40e29efa..1145b90f6ff93 100644
--- a/llvm/test/CodeGen/ARM/PR35379.ll
+++ b/llvm/test/CodeGen/ARM/PR35379.ll
@@ -2,15 +2,14 @@
; RUN: llc -mtriple=armv6m-eabi < %s | FileCheck %s --check-prefix=CHECK-THM
; Function Attrs: minsize optsize
-declare void @g(i32*) local_unnamed_addr #0
+declare void @g(ptr) local_unnamed_addr #0
; Function Attrs: minsize optsize
define void @f() local_unnamed_addr #0 {
entry:
%i = alloca i32, align 4
- %0 = bitcast i32* %i to i8*
- store i32 1, i32* %i, align 4
- call void @g(i32* nonnull %i)
+ store i32 1, ptr %i, align 4
+ call void @g(ptr nonnull %i)
ret void
}
@@ -32,9 +31,8 @@ entry:
define void @f1() local_unnamed_addr #1 {
entry:
%i = alloca i32, align 4
- %0 = bitcast i32* %i to i8*
- store i32 1, i32* %i, align 4
- call void @g(i32* nonnull %i)
+ store i32 1, ptr %i, align 4
+ call void @g(ptr nonnull %i)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/complex_dot_prod.ll b/llvm/test/CodeGen/ARM/ParallelDSP/complex_dot_prod.ll
index 76bd80cf0cd8e..ffa808b459226 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/complex_dot_prod.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/complex_dot_prod.ll
@@ -3,7 +3,7 @@
; RUN: llc -mtriple=thumbv7em -mcpu=cortex-m4 -O3 %s -o - | FileCheck %s --check-prefix=CHECK-LLC
; RUN: opt -S -mtriple=armv7-a -arm-parallel-dsp -dce %s -o - | FileCheck %s --check-prefix=CHECK-OPT
-define dso_local arm_aapcscc void @complex_dot_prod(i16* nocapture readonly %pSrcA, i16* nocapture readonly %pSrcB, i32* nocapture %realResult, i32* nocapture %imagResult) {
+define dso_local arm_aapcscc void @complex_dot_prod(ptr nocapture readonly %pSrcA, ptr nocapture readonly %pSrcB, ptr nocapture %realResult, ptr nocapture %imagResult) {
; CHECK-LLC-LABEL: complex_dot_prod:
; CHECK-LLC: @ %bb.0: @ %entry
; CHECK-LLC-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
@@ -49,83 +49,75 @@ define dso_local arm_aapcscc void @complex_dot_prod(i16* nocapture readonly %pSr
;
; CHECK-OPT-LABEL: @complex_dot_prod(
; CHECK-OPT-NEXT: entry:
-; CHECK-OPT-NEXT: [[TMP0:%.*]] = bitcast i16* [[PSRCA:%.*]] to i32*
-; CHECK-OPT-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 2
+; CHECK-OPT-NEXT: [[TMP1:%.*]] = load i32, ptr [[PSRCA:%.*]], align 2
; CHECK-OPT-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; CHECK-OPT-NEXT: [[TMP3:%.*]] = sext i16 [[TMP2]] to i32
; CHECK-OPT-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 16
; CHECK-OPT-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16
; CHECK-OPT-NEXT: [[TMP6:%.*]] = sext i16 [[TMP5]] to i32
-; CHECK-OPT-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds i16, i16* [[PSRCA]], i32 2
-; CHECK-OPT-NEXT: [[TMP7:%.*]] = bitcast i16* [[PSRCB:%.*]] to i32*
-; CHECK-OPT-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 2
+; CHECK-OPT-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds i16, ptr [[PSRCA]], i32 2
+; CHECK-OPT-NEXT: [[TMP8:%.*]] = load i32, ptr [[PSRCB:%.*]], align 2
; CHECK-OPT-NEXT: [[TMP9:%.*]] = trunc i32 [[TMP8]] to i16
; CHECK-OPT-NEXT: [[TMP10:%.*]] = call i64 @llvm.arm.smlaldx(i32 [[TMP1]], i32 [[TMP8]], i64 0)
; CHECK-OPT-NEXT: [[TMP11:%.*]] = sext i16 [[TMP9]] to i32
; CHECK-OPT-NEXT: [[TMP12:%.*]] = lshr i32 [[TMP8]], 16
; CHECK-OPT-NEXT: [[TMP13:%.*]] = trunc i32 [[TMP12]] to i16
; CHECK-OPT-NEXT: [[TMP14:%.*]] = sext i16 [[TMP13]] to i32
-; CHECK-OPT-NEXT: [[INCDEC_PTR3:%.*]] = getelementptr inbounds i16, i16* [[PSRCB]], i32 2
+; CHECK-OPT-NEXT: [[INCDEC_PTR3:%.*]] = getelementptr inbounds i16, ptr [[PSRCB]], i32 2
; CHECK-OPT-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], [[TMP3]]
; CHECK-OPT-NEXT: [[CONV5:%.*]] = sext i32 [[MUL]] to i64
; CHECK-OPT-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP14]], [[TMP6]]
; CHECK-OPT-NEXT: [[CONV14:%.*]] = sext i32 [[MUL13]] to i64
; CHECK-OPT-NEXT: [[SUB:%.*]] = sub nsw i64 [[CONV5]], [[CONV14]]
-; CHECK-OPT-NEXT: [[TMP15:%.*]] = bitcast i16* [[INCDEC_PTR1]] to i32*
-; CHECK-OPT-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 2
+; CHECK-OPT-NEXT: [[TMP16:%.*]] = load i32, ptr [[INCDEC_PTR1]], align 2
; CHECK-OPT-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i16
; CHECK-OPT-NEXT: [[TMP18:%.*]] = sext i16 [[TMP17]] to i32
; CHECK-OPT-NEXT: [[TMP19:%.*]] = lshr i32 [[TMP16]], 16
; CHECK-OPT-NEXT: [[TMP20:%.*]] = trunc i32 [[TMP19]] to i16
; CHECK-OPT-NEXT: [[TMP21:%.*]] = sext i16 [[TMP20]] to i32
-; CHECK-OPT-NEXT: [[INCDEC_PTR21:%.*]] = getelementptr inbounds i16, i16* [[PSRCA]], i32 4
-; CHECK-OPT-NEXT: [[TMP22:%.*]] = bitcast i16* [[INCDEC_PTR3]] to i32*
-; CHECK-OPT-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 2
+; CHECK-OPT-NEXT: [[INCDEC_PTR21:%.*]] = getelementptr inbounds i16, ptr [[PSRCA]], i32 4
+; CHECK-OPT-NEXT: [[TMP23:%.*]] = load i32, ptr [[INCDEC_PTR3]], align 2
; CHECK-OPT-NEXT: [[TMP24:%.*]] = trunc i32 [[TMP23]] to i16
; CHECK-OPT-NEXT: [[TMP25:%.*]] = call i64 @llvm.arm.smlaldx(i32 [[TMP16]], i32 [[TMP23]], i64 [[TMP10]])
; CHECK-OPT-NEXT: [[TMP26:%.*]] = sext i16 [[TMP24]] to i32
; CHECK-OPT-NEXT: [[TMP27:%.*]] = lshr i32 [[TMP23]], 16
; CHECK-OPT-NEXT: [[TMP28:%.*]] = trunc i32 [[TMP27]] to i16
; CHECK-OPT-NEXT: [[TMP29:%.*]] = sext i16 [[TMP28]] to i32
-; CHECK-OPT-NEXT: [[INCDEC_PTR23:%.*]] = getelementptr inbounds i16, i16* [[PSRCB]], i32 4
+; CHECK-OPT-NEXT: [[INCDEC_PTR23:%.*]] = getelementptr inbounds i16, ptr [[PSRCB]], i32 4
; CHECK-OPT-NEXT: [[MUL26:%.*]] = mul nsw i32 [[TMP26]], [[TMP18]]
; CHECK-OPT-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
; CHECK-OPT-NEXT: [[ADD28:%.*]] = add nsw i64 [[SUB]], [[CONV27]]
; CHECK-OPT-NEXT: [[MUL36:%.*]] = mul nsw i32 [[TMP29]], [[TMP21]]
; CHECK-OPT-NEXT: [[CONV37:%.*]] = sext i32 [[MUL36]] to i64
; CHECK-OPT-NEXT: [[SUB38:%.*]] = sub nsw i64 [[ADD28]], [[CONV37]]
-; CHECK-OPT-NEXT: [[TMP30:%.*]] = bitcast i16* [[INCDEC_PTR21]] to i32*
-; CHECK-OPT-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 2
+; CHECK-OPT-NEXT: [[TMP31:%.*]] = load i32, ptr [[INCDEC_PTR21]], align 2
; CHECK-OPT-NEXT: [[TMP32:%.*]] = trunc i32 [[TMP31]] to i16
; CHECK-OPT-NEXT: [[TMP33:%.*]] = sext i16 [[TMP32]] to i32
; CHECK-OPT-NEXT: [[TMP34:%.*]] = lshr i32 [[TMP31]], 16
; CHECK-OPT-NEXT: [[TMP35:%.*]] = trunc i32 [[TMP34]] to i16
; CHECK-OPT-NEXT: [[TMP36:%.*]] = sext i16 [[TMP35]] to i32
-; CHECK-OPT-NEXT: [[INCDEC_PTR45:%.*]] = getelementptr inbounds i16, i16* [[PSRCA]], i32 6
-; CHECK-OPT-NEXT: [[TMP37:%.*]] = bitcast i16* [[INCDEC_PTR23]] to i32*
-; CHECK-OPT-NEXT: [[TMP38:%.*]] = load i32, i32* [[TMP37]], align 2
+; CHECK-OPT-NEXT: [[INCDEC_PTR45:%.*]] = getelementptr inbounds i16, ptr [[PSRCA]], i32 6
+; CHECK-OPT-NEXT: [[TMP38:%.*]] = load i32, ptr [[INCDEC_PTR23]], align 2
; CHECK-OPT-NEXT: [[TMP39:%.*]] = trunc i32 [[TMP38]] to i16
; CHECK-OPT-NEXT: [[TMP40:%.*]] = call i64 @llvm.arm.smlaldx(i32 [[TMP31]], i32 [[TMP38]], i64 [[TMP25]])
; CHECK-OPT-NEXT: [[TMP41:%.*]] = sext i16 [[TMP39]] to i32
; CHECK-OPT-NEXT: [[TMP42:%.*]] = lshr i32 [[TMP38]], 16
; CHECK-OPT-NEXT: [[TMP43:%.*]] = trunc i32 [[TMP42]] to i16
; CHECK-OPT-NEXT: [[TMP44:%.*]] = sext i16 [[TMP43]] to i32
-; CHECK-OPT-NEXT: [[INCDEC_PTR47:%.*]] = getelementptr inbounds i16, i16* [[PSRCB]], i32 6
+; CHECK-OPT-NEXT: [[INCDEC_PTR47:%.*]] = getelementptr inbounds i16, ptr [[PSRCB]], i32 6
; CHECK-OPT-NEXT: [[MUL50:%.*]] = mul nsw i32 [[TMP41]], [[TMP33]]
; CHECK-OPT-NEXT: [[CONV51:%.*]] = sext i32 [[MUL50]] to i64
; CHECK-OPT-NEXT: [[ADD52:%.*]] = add nsw i64 [[SUB38]], [[CONV51]]
; CHECK-OPT-NEXT: [[MUL60:%.*]] = mul nsw i32 [[TMP44]], [[TMP36]]
; CHECK-OPT-NEXT: [[CONV61:%.*]] = sext i32 [[MUL60]] to i64
; CHECK-OPT-NEXT: [[SUB62:%.*]] = sub nsw i64 [[ADD52]], [[CONV61]]
-; CHECK-OPT-NEXT: [[TMP45:%.*]] = bitcast i16* [[INCDEC_PTR45]] to i32*
-; CHECK-OPT-NEXT: [[TMP46:%.*]] = load i32, i32* [[TMP45]], align 2
+; CHECK-OPT-NEXT: [[TMP46:%.*]] = load i32, ptr [[INCDEC_PTR45]], align 2
; CHECK-OPT-NEXT: [[TMP47:%.*]] = trunc i32 [[TMP46]] to i16
; CHECK-OPT-NEXT: [[TMP48:%.*]] = sext i16 [[TMP47]] to i32
; CHECK-OPT-NEXT: [[TMP49:%.*]] = lshr i32 [[TMP46]], 16
; CHECK-OPT-NEXT: [[TMP50:%.*]] = trunc i32 [[TMP49]] to i16
; CHECK-OPT-NEXT: [[TMP51:%.*]] = sext i16 [[TMP50]] to i32
-; CHECK-OPT-NEXT: [[TMP52:%.*]] = bitcast i16* [[INCDEC_PTR47]] to i32*
-; CHECK-OPT-NEXT: [[TMP53:%.*]] = load i32, i32* [[TMP52]], align 2
+; CHECK-OPT-NEXT: [[TMP53:%.*]] = load i32, ptr [[INCDEC_PTR47]], align 2
; CHECK-OPT-NEXT: [[TMP54:%.*]] = trunc i32 [[TMP53]] to i16
; CHECK-OPT-NEXT: [[TMP55:%.*]] = call i64 @llvm.arm.smlaldx(i32 [[TMP46]], i32 [[TMP53]], i64 [[TMP40]])
; CHECK-OPT-NEXT: [[TMP56:%.*]] = sext i16 [[TMP54]] to i32
@@ -140,20 +132,20 @@ define dso_local arm_aapcscc void @complex_dot_prod(i16* nocapture readonly %pSr
; CHECK-OPT-NEXT: [[SUB86:%.*]] = sub nsw i64 [[ADD76]], [[CONV85]]
; CHECK-OPT-NEXT: [[TMP60:%.*]] = lshr i64 [[SUB86]], 6
; CHECK-OPT-NEXT: [[CONV92:%.*]] = trunc i64 [[TMP60]] to i32
-; CHECK-OPT-NEXT: store i32 [[CONV92]], i32* [[REALRESULT:%.*]], align 4
+; CHECK-OPT-NEXT: store i32 [[CONV92]], ptr [[REALRESULT:%.*]], align 4
; CHECK-OPT-NEXT: [[TMP61:%.*]] = lshr i64 [[TMP55]], 6
; CHECK-OPT-NEXT: [[CONV94:%.*]] = trunc i64 [[TMP61]] to i32
-; CHECK-OPT-NEXT: store i32 [[CONV94]], i32* [[IMAGRESULT:%.*]], align 4
+; CHECK-OPT-NEXT: store i32 [[CONV94]], ptr [[IMAGRESULT:%.*]], align 4
; CHECK-OPT-NEXT: ret void
entry:
- %incdec.ptr = getelementptr inbounds i16, i16* %pSrcA, i32 1
- %0 = load i16, i16* %pSrcA, align 2
- %incdec.ptr1 = getelementptr inbounds i16, i16* %pSrcA, i32 2
- %1 = load i16, i16* %incdec.ptr, align 2
- %incdec.ptr2 = getelementptr inbounds i16, i16* %pSrcB, i32 1
- %2 = load i16, i16* %pSrcB, align 2
- %incdec.ptr3 = getelementptr inbounds i16, i16* %pSrcB, i32 2
- %3 = load i16, i16* %incdec.ptr2, align 2
+ %incdec.ptr = getelementptr inbounds i16, ptr %pSrcA, i32 1
+ %0 = load i16, ptr %pSrcA, align 2
+ %incdec.ptr1 = getelementptr inbounds i16, ptr %pSrcA, i32 2
+ %1 = load i16, ptr %incdec.ptr, align 2
+ %incdec.ptr2 = getelementptr inbounds i16, ptr %pSrcB, i32 1
+ %2 = load i16, ptr %pSrcB, align 2
+ %incdec.ptr3 = getelementptr inbounds i16, ptr %pSrcB, i32 2
+ %3 = load i16, ptr %incdec.ptr2, align 2
%conv = sext i16 %0 to i32
%conv4 = sext i16 %2 to i32
%mul = mul nsw i32 %conv4, %conv
@@ -168,14 +160,14 @@ entry:
%mul17 = mul nsw i32 %conv4, %conv11
%conv18 = sext i32 %mul17 to i64
%add19 = add nsw i64 %conv9, %conv18
- %incdec.ptr20 = getelementptr inbounds i16, i16* %pSrcA, i32 3
- %4 = load i16, i16* %incdec.ptr1, align 2
- %incdec.ptr21 = getelementptr inbounds i16, i16* %pSrcA, i32 4
- %5 = load i16, i16* %incdec.ptr20, align 2
- %incdec.ptr22 = getelementptr inbounds i16, i16* %pSrcB, i32 3
- %6 = load i16, i16* %incdec.ptr3, align 2
- %incdec.ptr23 = getelementptr inbounds i16, i16* %pSrcB, i32 4
- %7 = load i16, i16* %incdec.ptr22, align 2
+ %incdec.ptr20 = getelementptr inbounds i16, ptr %pSrcA, i32 3
+ %4 = load i16, ptr %incdec.ptr1, align 2
+ %incdec.ptr21 = getelementptr inbounds i16, ptr %pSrcA, i32 4
+ %5 = load i16, ptr %incdec.ptr20, align 2
+ %incdec.ptr22 = getelementptr inbounds i16, ptr %pSrcB, i32 3
+ %6 = load i16, ptr %incdec.ptr3, align 2
+ %incdec.ptr23 = getelementptr inbounds i16, ptr %pSrcB, i32 4
+ %7 = load i16, ptr %incdec.ptr22, align 2
%conv24 = sext i16 %4 to i32
%conv25 = sext i16 %6 to i32
%mul26 = mul nsw i32 %conv25, %conv24
@@ -192,14 +184,14 @@ entry:
%conv42 = sext i32 %mul41 to i64
%add33 = add nsw i64 %add19, %conv42
%add43 = add nsw i64 %add33, %conv32
- %incdec.ptr44 = getelementptr inbounds i16, i16* %pSrcA, i32 5
- %8 = load i16, i16* %incdec.ptr21, align 2
- %incdec.ptr45 = getelementptr inbounds i16, i16* %pSrcA, i32 6
- %9 = load i16, i16* %incdec.ptr44, align 2
- %incdec.ptr46 = getelementptr inbounds i16, i16* %pSrcB, i32 5
- %10 = load i16, i16* %incdec.ptr23, align 2
- %incdec.ptr47 = getelementptr inbounds i16, i16* %pSrcB, i32 6
- %11 = load i16, i16* %incdec.ptr46, align 2
+ %incdec.ptr44 = getelementptr inbounds i16, ptr %pSrcA, i32 5
+ %8 = load i16, ptr %incdec.ptr21, align 2
+ %incdec.ptr45 = getelementptr inbounds i16, ptr %pSrcA, i32 6
+ %9 = load i16, ptr %incdec.ptr44, align 2
+ %incdec.ptr46 = getelementptr inbounds i16, ptr %pSrcB, i32 5
+ %10 = load i16, ptr %incdec.ptr23, align 2
+ %incdec.ptr47 = getelementptr inbounds i16, ptr %pSrcB, i32 6
+ %11 = load i16, ptr %incdec.ptr46, align 2
%conv48 = sext i16 %8 to i32
%conv49 = sext i16 %10 to i32
%mul50 = mul nsw i32 %conv49, %conv48
@@ -216,12 +208,12 @@ entry:
%conv66 = sext i32 %mul65 to i64
%add57 = add nsw i64 %add43, %conv66
%add67 = add nsw i64 %add57, %conv56
- %incdec.ptr68 = getelementptr inbounds i16, i16* %pSrcA, i32 7
- %12 = load i16, i16* %incdec.ptr45, align 2
- %13 = load i16, i16* %incdec.ptr68, align 2
- %incdec.ptr70 = getelementptr inbounds i16, i16* %pSrcB, i32 7
- %14 = load i16, i16* %incdec.ptr47, align 2
- %15 = load i16, i16* %incdec.ptr70, align 2
+ %incdec.ptr68 = getelementptr inbounds i16, ptr %pSrcA, i32 7
+ %12 = load i16, ptr %incdec.ptr45, align 2
+ %13 = load i16, ptr %incdec.ptr68, align 2
+ %incdec.ptr70 = getelementptr inbounds i16, ptr %pSrcB, i32 7
+ %14 = load i16, ptr %incdec.ptr47, align 2
+ %15 = load i16, ptr %incdec.ptr70, align 2
%conv72 = sext i16 %12 to i32
%conv73 = sext i16 %14 to i32
%mul74 = mul nsw i32 %conv73, %conv72
@@ -240,9 +232,9 @@ entry:
%add91 = add nsw i64 %add81, %conv80
%16 = lshr i64 %sub86, 6
%conv92 = trunc i64 %16 to i32
- store i32 %conv92, i32* %realResult, align 4
+ store i32 %conv92, ptr %realResult, align 4
%17 = lshr i64 %add91, 6
%conv94 = trunc i64 %17 to i32
- store i32 %conv94, i32* %imagResult, align 4
+ store i32 %conv94, ptr %imagResult, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll b/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
index 4a5e0cba86340..3d60686d5a116 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
@@ -2,7 +2,7 @@
; RUN: llc -O3 -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s | FileCheck %s --check-prefixes=CHECK-LE
; RUN: llc -O3 -mtriple=armeb-none-none-eabi -mcpu=cortex-m33 < %s | FileCheck %s --check-prefixes=CHECK-BE
-define i32 @add_user(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define i32 @add_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
; CHECK-LE-LABEL: add_user:
; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .save {r4, lr}
@@ -70,8 +70,8 @@ entry:
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -84,19 +84,19 @@ for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%count = phi i32 [ %count.next, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%count.next = add i32 %conv4, %count
%mul = mul nsw i32 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = sext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
@@ -106,7 +106,7 @@ for.body:
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}
-define i32 @mul_bottom_user(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define i32 @mul_bottom_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
; CHECK-LE-LABEL: mul_bottom_user:
; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .save {r4, r5, r7, lr}
@@ -175,8 +175,8 @@ entry:
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -189,18 +189,18 @@ for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%count = phi i32 [ %count.next, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = sext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
@@ -211,7 +211,7 @@ for.body:
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}
-define i32 @mul_top_user(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define i32 @mul_top_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
; CHECK-LE-LABEL: mul_top_user:
; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .save {r4, lr}
@@ -280,8 +280,8 @@ entry:
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -294,18 +294,18 @@ for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%count = phi i32 [ %count.next, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = sext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
@@ -316,7 +316,7 @@ for.body:
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}
-define i32 @and_user(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define i32 @and_user(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
; CHECK-LE-LABEL: and_user:
; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .save {r4, lr}
@@ -385,8 +385,8 @@ entry:
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -399,19 +399,19 @@ for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%count = phi i32 [ %count.next, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%bottom = and i32 %conv4, 65535
%mul = mul nsw i32 %conv, %conv4
- %3 = load i16, i16* %arrayidx6, align 2
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = sext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
@@ -422,7 +422,7 @@ for.body:
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}
-define i32 @multi_uses(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define i32 @multi_uses(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
; CHECK-LE-LABEL: multi_uses:
; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .save {r4, lr}
@@ -494,8 +494,8 @@ entry:
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -508,19 +508,19 @@ for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%count = phi i32 [ %count.next, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%bottom = and i32 %conv4, 65535
%mul = mul nsw i32 %conv, %conv4
- %3 = load i16, i16* %arrayidx6, align 2
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = sext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/pr42729.ll b/llvm/test/CodeGen/ARM/ParallelDSP/pr42729.ll
index 11124a504cef0..b2d371a5798c9 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/pr42729.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/pr42729.ll
@@ -1,31 +1,27 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=thumbv7-unknown-linux-android -arm-parallel-dsp -S %s -o - | FileCheck %s
-define void @undef_no_return(i16* %a) {
+define void @undef_no_return(ptr %a) {
; CHECK-LABEL: @undef_no_return(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[INCDEC_PTR21:%.*]] = getelementptr inbounds i16, i16* [[A:%.*]], i32 3
-; CHECK-NEXT: [[INCDEC_PTR29:%.*]] = getelementptr inbounds i16, i16* [[A]], i32 4
+; CHECK-NEXT: [[INCDEC_PTR21:%.*]] = getelementptr inbounds i16, ptr [[A:%.*]], i32 3
+; CHECK-NEXT: [[INCDEC_PTR29:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 4
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[INCDEC_PTR21]], align 2
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast i16* [[INCDEC_PTR21]] to i32*
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 2
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[INCDEC_PTR21]], align 2
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[INCDEC_PTR21]], align 2
; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16
; CHECK-NEXT: [[TMP4:%.*]] = sext i16 [[TMP3]] to i32
; CHECK-NEXT: [[TMP5:%.*]] = lshr i32 [[TMP2]], 16
; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16
; CHECK-NEXT: [[TMP7:%.*]] = sext i16 [[TMP6]] to i32
; CHECK-NEXT: [[CONV25:%.*]] = sext i16 [[TMP0]] to i32
-; CHECK-NEXT: [[UGLYGEP15:%.*]] = getelementptr i8, i8* undef, i32 undef
-; CHECK-NEXT: [[UGLYGEP1516:%.*]] = bitcast i8* [[UGLYGEP15]] to i16*
-; CHECK-NEXT: [[SCEVGEP17:%.*]] = getelementptr i16, i16* [[UGLYGEP1516]], i32 7
-; CHECK-NEXT: [[TMP8:%.*]] = load i16, i16* [[SCEVGEP17]], align 2
-; CHECK-NEXT: [[UGLYGEP12:%.*]] = getelementptr i8, i8* undef, i32 undef
-; CHECK-NEXT: [[UGLYGEP1213:%.*]] = bitcast i8* [[UGLYGEP12]] to i16*
-; CHECK-NEXT: [[SCEVGEP14:%.*]] = getelementptr i16, i16* [[UGLYGEP1213]], i32 6
-; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16* [[SCEVGEP14]] to i32*
-; CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 2
+; CHECK-NEXT: [[UGLYGEP15:%.*]] = getelementptr i8, ptr undef, i32 undef
+; CHECK-NEXT: [[SCEVGEP17:%.*]] = getelementptr i16, ptr [[UGLYGEP15]], i32 7
+; CHECK-NEXT: [[TMP8:%.*]] = load i16, ptr [[SCEVGEP17]], align 2
+; CHECK-NEXT: [[UGLYGEP12:%.*]] = getelementptr i8, ptr undef, i32 undef
+; CHECK-NEXT: [[SCEVGEP14:%.*]] = getelementptr i16, ptr [[UGLYGEP12]], i32 6
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[SCEVGEP14]], align 2
; CHECK-NEXT: [[TMP11:%.*]] = trunc i32 [[TMP10]] to i16
; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.arm.smladx(i32 [[TMP10]], i32 [[TMP2]], i32 undef)
; CHECK-NEXT: [[TMP13:%.*]] = sext i16 [[TMP11]] to i32
@@ -33,9 +29,9 @@ define void @undef_no_return(i16* %a) {
; CHECK-NEXT: [[TMP15:%.*]] = trunc i32 [[TMP14]] to i16
; CHECK-NEXT: [[TMP16:%.*]] = sext i16 [[TMP15]] to i32
; CHECK-NEXT: [[CONV31:%.*]] = sext i16 [[TMP8]] to i32
-; CHECK-NEXT: [[TMP17:%.*]] = load i16, i16* [[INCDEC_PTR29]], align 2
+; CHECK-NEXT: [[TMP17:%.*]] = load i16, ptr [[INCDEC_PTR29]], align 2
; CHECK-NEXT: [[CONV33:%.*]] = sext i16 [[TMP17]] to i32
-; CHECK-NEXT: [[TMP18:%.*]] = load i16, i16* [[SCEVGEP14]], align 2
+; CHECK-NEXT: [[TMP18:%.*]] = load i16, ptr [[SCEVGEP14]], align 2
; CHECK-NEXT: [[CONV39:%.*]] = sext i16 [[TMP18]] to i32
; CHECK-NEXT: [[MUL_I287_NEG_NEG:%.*]] = mul nsw i32 [[TMP16]], [[TMP4]]
; CHECK-NEXT: [[MUL_I283_NEG_NEG:%.*]] = mul nsw i32 [[TMP13]], [[TMP7]]
@@ -44,24 +40,22 @@ define void @undef_no_return(i16* %a) {
; CHECK-NEXT: br label [[FOR_BODY]]
;
entry:
- %incdec.ptr21 = getelementptr inbounds i16, i16* %a, i32 3
- %incdec.ptr29 = getelementptr inbounds i16, i16* %a, i32 4
+ %incdec.ptr21 = getelementptr inbounds i16, ptr %a, i32 3
+ %incdec.ptr29 = getelementptr inbounds i16, ptr %a, i32 4
br label %for.body
for.body:
- %0 = load i16, i16* %incdec.ptr21, align 2
+ %0 = load i16, ptr %incdec.ptr21, align 2
%conv25 = sext i16 %0 to i32
- %uglygep15 = getelementptr i8, i8* undef, i32 undef
- %uglygep1516 = bitcast i8* %uglygep15 to i16*
- %scevgep17 = getelementptr i16, i16* %uglygep1516, i32 7
- %1 = load i16, i16* %scevgep17, align 2
+ %uglygep15 = getelementptr i8, ptr undef, i32 undef
+ %scevgep17 = getelementptr i16, ptr %uglygep15, i32 7
+ %1 = load i16, ptr %scevgep17, align 2
%conv31 = sext i16 %1 to i32
- %2 = load i16, i16* %incdec.ptr29, align 2
+ %2 = load i16, ptr %incdec.ptr29, align 2
%conv33 = sext i16 %2 to i32
- %uglygep12 = getelementptr i8, i8* undef, i32 undef
- %uglygep1213 = bitcast i8* %uglygep12 to i16*
- %scevgep14 = getelementptr i16, i16* %uglygep1213, i32 6
- %3 = load i16, i16* %scevgep14, align 2
+ %uglygep12 = getelementptr i8, ptr undef, i32 undef
+ %scevgep14 = getelementptr i16, ptr %uglygep12, i32 6
+ %3 = load i16, ptr %scevgep14, align 2
%conv39 = sext i16 %3 to i32
%mul.i287.neg.neg = mul nsw i32 %conv31, %conv25
%mul.i283.neg.neg = mul nsw i32 %conv39, %conv33
@@ -70,32 +64,28 @@ for.body:
br label %for.body
}
-define i32 @return(i16* %a, i8* %b, i32 %N) {
+define i32 @return(ptr %a, ptr %b, i32 %N) {
; CHECK-LABEL: @return(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[INCDEC_PTR21:%.*]] = getelementptr inbounds i16, i16* [[A:%.*]], i32 3
-; CHECK-NEXT: [[INCDEC_PTR29:%.*]] = getelementptr inbounds i16, i16* [[A]], i32 4
+; CHECK-NEXT: [[INCDEC_PTR21:%.*]] = getelementptr inbounds i16, ptr [[A:%.*]], i32 3
+; CHECK-NEXT: [[INCDEC_PTR29:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 4
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[N:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[ACC:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP12:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[INCDEC_PTR21]], align 2
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast i16* [[INCDEC_PTR21]] to i32*
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 2
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[INCDEC_PTR21]], align 2
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[INCDEC_PTR21]], align 2
; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16
; CHECK-NEXT: [[TMP4:%.*]] = sext i16 [[TMP3]] to i32
; CHECK-NEXT: [[TMP5:%.*]] = lshr i32 [[TMP2]], 16
; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16
; CHECK-NEXT: [[TMP7:%.*]] = sext i16 [[TMP6]] to i32
; CHECK-NEXT: [[CONV25:%.*]] = sext i16 [[TMP0]] to i32
-; CHECK-NEXT: [[UGLYGEP15:%.*]] = getelementptr i8, i8* [[B:%.*]], i32 0
-; CHECK-NEXT: [[UGLYGEP1516:%.*]] = bitcast i8* [[UGLYGEP15]] to i16*
; CHECK-NEXT: [[B_IDX:%.*]] = add nuw nsw i32 [[IV]], 1
-; CHECK-NEXT: [[SCEVGEP17:%.*]] = getelementptr i16, i16* [[UGLYGEP1516]], i32 [[B_IDX]]
-; CHECK-NEXT: [[SCEVGEP14:%.*]] = getelementptr i16, i16* [[UGLYGEP1516]], i32 [[IV]]
-; CHECK-NEXT: [[TMP8:%.*]] = load i16, i16* [[SCEVGEP17]], align 2
-; CHECK-NEXT: [[TMP9:%.*]] = bitcast i16* [[SCEVGEP14]] to i32*
-; CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 2
+; CHECK-NEXT: [[SCEVGEP17:%.*]] = getelementptr i16, ptr [[B:%.*]], i32 [[B_IDX]]
+; CHECK-NEXT: [[SCEVGEP14:%.*]] = getelementptr i16, ptr [[B]], i32 [[IV]]
+; CHECK-NEXT: [[TMP8:%.*]] = load i16, ptr [[SCEVGEP17]], align 2
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[SCEVGEP14]], align 2
; CHECK-NEXT: [[TMP11:%.*]] = trunc i32 [[TMP10]] to i16
; CHECK-NEXT: [[TMP12]] = call i32 @llvm.arm.smladx(i32 [[TMP10]], i32 [[TMP2]], i32 [[ACC]])
; CHECK-NEXT: [[TMP13:%.*]] = sext i16 [[TMP11]] to i32
@@ -103,9 +93,9 @@ define i32 @return(i16* %a, i8* %b, i32 %N) {
; CHECK-NEXT: [[TMP15:%.*]] = trunc i32 [[TMP14]] to i16
; CHECK-NEXT: [[TMP16:%.*]] = sext i16 [[TMP15]] to i32
; CHECK-NEXT: [[CONV31:%.*]] = sext i16 [[TMP8]] to i32
-; CHECK-NEXT: [[TMP17:%.*]] = load i16, i16* [[INCDEC_PTR29]], align 2
+; CHECK-NEXT: [[TMP17:%.*]] = load i16, ptr [[INCDEC_PTR29]], align 2
; CHECK-NEXT: [[CONV33:%.*]] = sext i16 [[TMP17]] to i32
-; CHECK-NEXT: [[TMP18:%.*]] = load i16, i16* [[SCEVGEP14]], align 2
+; CHECK-NEXT: [[TMP18:%.*]] = load i16, ptr [[SCEVGEP14]], align 2
; CHECK-NEXT: [[CONV39:%.*]] = sext i16 [[TMP18]] to i32
; CHECK-NEXT: [[MUL_I287_NEG_NEG:%.*]] = mul nsw i32 [[TMP16]], [[TMP4]]
; CHECK-NEXT: [[MUL_I283_NEG_NEG:%.*]] = mul nsw i32 [[TMP13]], [[TMP7]]
@@ -118,25 +108,23 @@ define i32 @return(i16* %a, i8* %b, i32 %N) {
; CHECK-NEXT: ret i32 [[TMP12]]
;
entry:
- %incdec.ptr21 = getelementptr inbounds i16, i16* %a, i32 3
- %incdec.ptr29 = getelementptr inbounds i16, i16* %a, i32 4
+ %incdec.ptr21 = getelementptr inbounds i16, ptr %a, i32 3
+ %incdec.ptr29 = getelementptr inbounds i16, ptr %a, i32 4
br label %for.body
for.body:
%iv = phi i32 [ %N, %entry ], [ %iv.next, %for.body ]
%acc = phi i32 [ 0, %entry ], [ %reass.add409, %for.body ]
- %0 = load i16, i16* %incdec.ptr21, align 2
+ %0 = load i16, ptr %incdec.ptr21, align 2
%conv25 = sext i16 %0 to i32
- %uglygep15 = getelementptr i8, i8* %b, i32 0
- %uglygep1516 = bitcast i8* %uglygep15 to i16*
%b.idx = add nuw nsw i32 %iv, 1
- %scevgep17 = getelementptr i16, i16* %uglygep1516, i32 %b.idx
- %scevgep14 = getelementptr i16, i16* %uglygep1516, i32 %iv
- %1 = load i16, i16* %scevgep17, align 2
+ %scevgep17 = getelementptr i16, ptr %b, i32 %b.idx
+ %scevgep14 = getelementptr i16, ptr %b, i32 %iv
+ %1 = load i16, ptr %scevgep17, align 2
%conv31 = sext i16 %1 to i32
- %2 = load i16, i16* %incdec.ptr29, align 2
+ %2 = load i16, ptr %incdec.ptr29, align 2
%conv33 = sext i16 %2 to i32
- %3 = load i16, i16* %scevgep14, align 2
+ %3 = load i16, ptr %scevgep14, align 2
%conv39 = sext i16 %3 to i32
%mul.i287.neg.neg = mul nsw i32 %conv31, %conv25
%mul.i283.neg.neg = mul nsw i32 %conv39, %conv33
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll
index 63398fd46a705..5b2dba4ea30bc 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll
@@ -7,14 +7,12 @@
; Check DSP extension:
; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
-define dso_local i32 @OneReduction(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local i32 @OneReduction(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
;
; CHECK-LABEL: @OneReduction
; CHECK: %mac1{{\.}}026 = phi i32 [ [[V8:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ]
-; CHECK: [[V4:%[0-9]+]] = bitcast i16* %arrayidx to i32*
-; CHECK: [[V5:%[0-9]+]] = load i32, i32* [[V4]], align 2
-; CHECK: [[V6:%[0-9]+]] = bitcast i16* %arrayidx3 to i32*
-; CHECK: [[V7:%[0-9]+]] = load i32, i32* [[V6]], align 2
+; CHECK: [[V5:%[0-9]+]] = load i32, ptr %arrayidx, align 2
+; CHECK: [[V7:%[0-9]+]] = load i32, ptr %arrayidx3, align 2
; CHECK: [[V8]] = call i32 @llvm.arm.smlad(i32 [[V7]], i32 [[V5]], i32 %mac1{{\.}}026)
; CHECK-NOT: call i32 @llvm.arm.smlad
;
@@ -25,8 +23,8 @@ entry:
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -38,18 +36,18 @@ for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = sext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
@@ -62,7 +60,7 @@ for.body:
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}
-define dso_local arm_aapcs_vfpcc i32 @TwoReductions(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local arm_aapcs_vfpcc i32 @TwoReductions(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
;
; CHECK-LABEL: @TwoReductions
;
@@ -91,37 +89,37 @@ for.body:
%mac2.057 = phi i32 [ %add28, %for.body ], [ 0, %for.body.preheader ]
%i.056 = phi i32 [ %add29, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.056
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.056
+ %0 = load i16, ptr %arrayidx, align 2
%add1 = or i32 %i.056, 1
- %arrayidx2 = getelementptr inbounds i16, i16* %arg3, i32 %add1
- %1 = load i16, i16* %arrayidx2, align 2
+ %arrayidx2 = getelementptr inbounds i16, ptr %arg3, i32 %add1
+ %1 = load i16, ptr %arrayidx2, align 2
%add3 = or i32 %i.056, 2
- %arrayidx4 = getelementptr inbounds i16, i16* %arg3, i32 %add3
- %2 = load i16, i16* %arrayidx4, align 2
+ %arrayidx4 = getelementptr inbounds i16, ptr %arg3, i32 %add3
+ %2 = load i16, ptr %arrayidx4, align 2
%add5 = or i32 %i.056, 3
- %arrayidx6 = getelementptr inbounds i16, i16* %arg3, i32 %add5
- %3 = load i16, i16* %arrayidx6, align 2
- %arrayidx8 = getelementptr inbounds i16, i16* %arg2, i32 %i.056
- %4 = load i16, i16* %arrayidx8, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg3, i32 %add5
+ %3 = load i16, ptr %arrayidx6, align 2
+ %arrayidx8 = getelementptr inbounds i16, ptr %arg2, i32 %i.056
+ %4 = load i16, ptr %arrayidx8, align 2
%conv = sext i16 %4 to i32
%conv9 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv9
- %arrayidx11 = getelementptr inbounds i16, i16* %arg2, i32 %add1
- %5 = load i16, i16* %arrayidx11, align 2
+ %arrayidx11 = getelementptr inbounds i16, ptr %arg2, i32 %add1
+ %5 = load i16, ptr %arrayidx11, align 2
%conv12 = sext i16 %5 to i32
%conv13 = sext i16 %1 to i32
%mul14 = mul nsw i32 %conv12, %conv13
%add15 = add i32 %mul, %mac1.058
%add16 = add i32 %add15, %mul14
- %arrayidx18 = getelementptr inbounds i16, i16* %arg2, i32 %add3
- %6 = load i16, i16* %arrayidx18, align 2
+ %arrayidx18 = getelementptr inbounds i16, ptr %arg2, i32 %add3
+ %6 = load i16, ptr %arrayidx18, align 2
%conv19 = sext i16 %6 to i32
%conv20 = sext i16 %2 to i32
%mul21 = mul nsw i32 %conv19, %conv20
- %arrayidx23 = getelementptr inbounds i16, i16* %arg2, i32 %add5
- %7 = load i16, i16* %arrayidx23, align 2
+ %arrayidx23 = getelementptr inbounds i16, ptr %arg2, i32 %add5
+ %7 = load i16, ptr %arrayidx23, align 2
%conv24 = sext i16 %7 to i32
%conv25 = sext i16 %3 to i32
%mul26 = mul nsw i32 %conv24, %conv25
@@ -132,7 +130,7 @@ for.body:
br i1 %cmp, label %for.body, label %for.cond.cleanup
}
-define i32 @one_zext(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define i32 @one_zext(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
; CHECK-LABEL: @one_zext
; CHECK-NOT: call i32 @llvm.arm.smlad
entry:
@@ -140,8 +138,8 @@ entry:
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -151,18 +149,18 @@ for.cond.cleanup:
for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = zext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = zext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
@@ -172,7 +170,7 @@ for.body:
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}
-define i32 @two_zext(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define i32 @two_zext(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
; CHECK-LABEL: @two_zext
; CHECK-NOT: call i32 @llvm.arm.smlad
entry:
@@ -180,8 +178,8 @@ entry:
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -191,18 +189,18 @@ for.cond.cleanup:
for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = zext i16 %2 to i32
%conv4 = zext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = zext i16 %3 to i32
%conv8 = zext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad1.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad1.ll
index cd6ad7dc0f249..1327452e4c623 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad1.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad1.ll
@@ -2,20 +2,18 @@
; CHECK-LABEL: @test1
; CHECK: %mac1{{\.}}026 = phi i32 [ [[V8:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ]
-; CHECK: [[V4:%[0-9]+]] = bitcast i16* %arrayidx to i32*
-; CHECK: [[V5:%[0-9]+]] = load i32, i32* [[V4]], align 2
-; CHECK: [[V6:%[0-9]+]] = bitcast i16* %arrayidx3 to i32*
-; CHECK: [[V7:%[0-9]+]] = load i32, i32* [[V6]], align 2
+; CHECK: [[V5:%[0-9]+]] = load i32, ptr %arrayidx, align 2
+; CHECK: [[V7:%[0-9]+]] = load i32, ptr %arrayidx3, align 2
; CHECK: [[V8]] = call i32 @llvm.arm.smlad(i32 [[V7]], i32 [[V5]], i32 %mac1{{\.}}026)
-define dso_local i32 @test1(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local i32 @test1(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -25,18 +23,18 @@ for.cond.cleanup:
for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = sext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
@@ -54,14 +52,14 @@ for.body:
; CHECK-LABEL: @test2
; CHECK-NOT: call i32 @llvm.arm.smlad
;
-define dso_local i32 @test2(i32 %arg, i32* nocapture readnone %arg1, i8* nocapture readonly %arg2, i8* nocapture readonly %arg3) {
+define dso_local i32 @test2(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i8, i8* %arg3, align 2
- %.pre27 = load i8, i8* %arg2, align 2
+ %.pre = load i8, ptr %arg3, align 2
+ %.pre27 = load i8, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -71,18 +69,18 @@ for.cond.cleanup:
for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i8, i8* %arg3, i32 %i.025
- %0 = load i8, i8* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i8, ptr %arg3, i32 %i.025
+ %0 = load i8, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i8, i8* %arg3, i32 %add
- %1 = load i8, i8* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i8, i8* %arg2, i32 %i.025
- %2 = load i8, i8* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i8, ptr %arg3, i32 %add
+ %1 = load i8, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i8, ptr %arg2, i32 %i.025
+ %2 = load i8, ptr %arrayidx3, align 2
%conv = sext i8 %2 to i32
%conv4 = sext i8 %0 to i32
%mul = mul nsw i32 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i8, i8* %arg2, i32 %add
- %3 = load i8, i8* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i8, ptr %arg2, i32 %add
+ %3 = load i8, ptr %arrayidx6, align 2
%conv7 = sext i8 %3 to i32
%conv8 = sext i8 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad10.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad10.ll
index 8b0f4654742f9..e2b0feb59a4c5 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad10.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad10.ll
@@ -5,14 +5,14 @@
;
; CHECK-NOT: call i32 @llvm.arm.smlad
;
-define dso_local i64 @test(i64 %arg, i64* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local i64 @test(i64 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
entry:
%cmp24 = icmp sgt i64 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -22,18 +22,18 @@ for.cond.cleanup:
for.body:
%mac1.026 = phi i64 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i64 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i64 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i64 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i64 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i64 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i64 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i64 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i64 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i64
%conv4 = sext i16 %0 to i64
%mul = mul nsw i64 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i64 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i64 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i64
%conv8 = sext i16 %1 to i64
%mul9 = mul nsw i64 %conv7, %conv8
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll
index bb0787f11d85d..7c1a9bca1fdb9 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll
@@ -4,15 +4,11 @@
; A more complicated chain: 4 mul operations, so we expect 2 smlad calls.
;
; CHECK: %mac1{{\.}}054 = phi i32 [ [[V17:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ]
-; CHECK: [[V10:%[0-9]+]] = bitcast i16* %arrayidx to i32*
-; CHECK: [[V11:%[0-9]+]] = load i32, i32* [[V10]], align 2
-; CHECK: [[V15:%[0-9]+]] = bitcast i16* %arrayidx4 to i32*
-; CHECK: [[V16:%[0-9]+]] = load i32, i32* [[V15]], align 2
-; CHECK: [[V8:%[0-9]+]] = bitcast i16* %arrayidx8 to i32*
-; CHECK: [[V9:%[0-9]+]] = load i32, i32* [[V8]], align 2
+; CHECK: [[V11:%[0-9]+]] = load i32, ptr %arrayidx, align 2
+; CHECK: [[V16:%[0-9]+]] = load i32, ptr %arrayidx4, align 2
+; CHECK: [[V9:%[0-9]+]] = load i32, ptr %arrayidx8, align 2
; CHECK: [[ACC:%[0-9]+]] = call i32 @llvm.arm.smlad(i32 [[V9]], i32 [[V11]], i32 %mac1{{\.}}054)
-; CHECK: [[V13:%[0-9]+]] = bitcast i16* %arrayidx17 to i32*
-; CHECK: [[V14:%[0-9]+]] = load i32, i32* [[V13]], align 2
+; CHECK: [[V14:%[0-9]+]] = load i32, ptr %arrayidx17, align 2
; CHECK: [[V12:%[0-9]+]] = call i32 @llvm.arm.smlad(i32 [[V14]], i32 [[V16]], i32 [[ACC]])
;
; And we don't want to see a 3rd smlad:
@@ -20,7 +16,7 @@
;
; CHECK: 2 arm-parallel-dsp - Number of smlad instructions generated
;
-define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local i32 @test(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
entry:
%cmp52 = icmp sgt i32 %arg, 0
br i1 %cmp52, label %for.body.preheader, label %for.cond.cleanup
@@ -35,34 +31,34 @@ for.body.preheader:
for.body:
%mac1.054 = phi i32 [ %add28, %for.body ], [ 0, %for.body.preheader ]
%i.053 = phi i32 [ %add29, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.053
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.053
+ %0 = load i16, ptr %arrayidx, align 2
%add1 = or i32 %i.053, 1
- %arrayidx2 = getelementptr inbounds i16, i16* %arg3, i32 %add1
- %1 = load i16, i16* %arrayidx2, align 2
+ %arrayidx2 = getelementptr inbounds i16, ptr %arg3, i32 %add1
+ %1 = load i16, ptr %arrayidx2, align 2
%add3 = or i32 %i.053, 2
- %arrayidx4 = getelementptr inbounds i16, i16* %arg3, i32 %add3
- %2 = load i16, i16* %arrayidx4, align 2
+ %arrayidx4 = getelementptr inbounds i16, ptr %arg3, i32 %add3
+ %2 = load i16, ptr %arrayidx4, align 2
%add5 = or i32 %i.053, 3
- %arrayidx6 = getelementptr inbounds i16, i16* %arg3, i32 %add5
- %3 = load i16, i16* %arrayidx6, align 2
- %arrayidx8 = getelementptr inbounds i16, i16* %arg2, i32 %i.053
- %4 = load i16, i16* %arrayidx8, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg3, i32 %add5
+ %3 = load i16, ptr %arrayidx6, align 2
+ %arrayidx8 = getelementptr inbounds i16, ptr %arg2, i32 %i.053
+ %4 = load i16, ptr %arrayidx8, align 2
%conv = sext i16 %4 to i32
%conv9 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv9
- %arrayidx11 = getelementptr inbounds i16, i16* %arg2, i32 %add1
- %5 = load i16, i16* %arrayidx11, align 2
+ %arrayidx11 = getelementptr inbounds i16, ptr %arg2, i32 %add1
+ %5 = load i16, ptr %arrayidx11, align 2
%conv12 = sext i16 %5 to i32
%conv13 = sext i16 %1 to i32
%mul14 = mul nsw i32 %conv12, %conv13
- %arrayidx17 = getelementptr inbounds i16, i16* %arg2, i32 %add3
- %6 = load i16, i16* %arrayidx17, align 2
+ %arrayidx17 = getelementptr inbounds i16, ptr %arg2, i32 %add3
+ %6 = load i16, ptr %arrayidx17, align 2
%conv18 = sext i16 %6 to i32
%conv19 = sext i16 %2 to i32
%mul20 = mul nsw i32 %conv18, %conv19
- %arrayidx23 = getelementptr inbounds i16, i16* %arg2, i32 %add5
- %7 = load i16, i16* %arrayidx23, align 2
+ %arrayidx23 = getelementptr inbounds i16, ptr %arg2, i32 %add5
+ %7 = load i16, ptr %arrayidx23, align 2
%conv24 = sext i16 %7 to i32
%conv25 = sext i16 %3 to i32
%mul26 = mul nsw i32 %conv24, %conv25
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad12.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad12.ll
index b4d617a376815..a9676260c4947 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad12.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad12.ll
@@ -4,14 +4,14 @@
;
; CHECK: call i32 @llvm.arm.smlad
;
-define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local i32 @test(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -22,18 +22,18 @@ for.cond.cleanup:
for.body:
%mac1.026 = phi i32 [ %add11, %for.body2 ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body2 ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = sext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad2.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad2.ll
index 26c4c23dded8b..ac0f75e62de6d 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad2.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad2.ll
@@ -5,14 +5,14 @@
;
; CHECK-NOT: call i32 @llvm.arm.smlad
;
-define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local i32 @test(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -22,21 +22,21 @@ for.cond.cleanup:
for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i32
; This zero-extends the 2nd operand of %mul:
%conv4 = zext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
; And here we only have sign-extensions. Thus, the operands of
; %mul and %mul9 are not symmetrical:
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad3.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad3.ll
index 787bf687c3fad..73a04a3cf6b02 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad3.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad3.ll
@@ -4,14 +4,14 @@
;
; CHECK-NOT: call i32 @llvm.arm.smlad
;
-define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local i32 @test(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -21,13 +21,13 @@ for.cond.cleanup:
for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
@@ -36,8 +36,8 @@ for.body:
; loads to %3 and %2 are not consecutive:
%add5 = add nuw nsw i32 %i.025, 2
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add5
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add5
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = sext i16 %1 to i32
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad4.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad4.ll
index 6b8a3903d3cd4..a89c7d44a9e0f 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad4.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad4.ll
@@ -6,13 +6,13 @@
;
; Arg2 is now an i32, while Arg3 is still and i16:
;
-define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i32* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local i32 @test(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
entry:
%cmp22 = icmp sgt i32 %arg, 0
br i1 %cmp22, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
+ %.pre = load i16, ptr %arg3, align 2
br label %for.body
for.cond.cleanup:
@@ -24,21 +24,21 @@ for.body:
%mac1.024 = phi i32 [ %add9, %for.body ], [ 0, %for.body.preheader ]
%i.023 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%add = add nuw nsw i32 %i.023, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
%conv = sext i16 %0 to i32
; This is a 'normal' i32 load to %2:
- %arrayidx3 = getelementptr inbounds i32, i32* %arg2, i32 %i.023
- %2 = load i32, i32* %arrayidx3, align 4
+ %arrayidx3 = getelementptr inbounds i32, ptr %arg2, i32 %i.023
+ %2 = load i32, ptr %arrayidx3, align 4
; This mul has now 1 operand which is a narrow load, and the other a normal
; i32 load:
%mul = mul nsw i32 %2, %conv
%add4 = add nuw nsw i32 %i.023, 2
- %arrayidx5 = getelementptr inbounds i32, i32* %arg2, i32 %add4
- %3 = load i32, i32* %arrayidx5, align 4
+ %arrayidx5 = getelementptr inbounds i32, ptr %arg2, i32 %add4
+ %3 = load i32, ptr %arrayidx5, align 4
%conv6 = sext i16 %1 to i32
%mul7 = mul nsw i32 %3, %conv6
%add8 = add i32 %mul, %mac1.024
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad5.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad5.ll
index 2a15fd41b08e9..298afe35a268c 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad5.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad5.ll
@@ -4,14 +4,14 @@
;
; CHECK-NOT: call i32 @llvm.arm.smlad
;
-define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local i32 @test(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -21,18 +21,18 @@ for.cond.cleanup:
for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load volatile i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load volatile i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load volatile i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load volatile i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load volatile i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load volatile i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load volatile i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load volatile i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = sext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad8.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad8.ll
index 1f744dca00eec..bfa154c89ec6e 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad8.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad8.ll
@@ -6,18 +6,17 @@
;
; CHECK-NOT: call i32 @llvm.arm.smlad
;
-define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3, i16* %arg4) {
+define dso_local i32 @test(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3, ptr %arg4) {
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
- %gep0 = getelementptr inbounds i16, i16* %arg4, i32 0
- %gep1 = getelementptr inbounds i16, i16* %arg4, i32 1
- %.add4 = load i16, i16* %gep0, align 2
- %.add5 = load i16, i16* %gep1, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
+ %gep1 = getelementptr inbounds i16, ptr %arg4, i32 1
+ %.add4 = load i16, ptr %arg4, align 2
+ %.add5 = load i16, ptr %gep1, align 2
%.zext4 = zext i16 %.add4 to i32
%.zext5 = zext i16 %.add5 to i32
br label %for.body
@@ -29,13 +28,13 @@ for.cond.cleanup:
for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%add1 = add i32 %conv, %.zext4
@@ -43,8 +42,8 @@ for.body:
; This mul has a more complicated pattern as an operand, %add1
; is another add and load, which we don't support for now.
%mul = mul nsw i32 %add1, %conv4
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = sext i16 %1 to i32
%add2 = add i32 %conv7, %.zext5
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad9.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad9.ll
index 3fb1deb9e1488..0c33d93927ece 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad9.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad9.ll
@@ -5,14 +5,14 @@
;
; CHECK-NOT: call i32 @llvm.arm.smlad
;
-define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local i32 @test(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -23,15 +23,15 @@ for.body:
%mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%add = add nuw nsw i32 %i.025, 1
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %v2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %v2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %v2 to i32
; RHS operand of this mul is a constant
%mul = mul nsw i32 %conv, 43
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %v3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %v3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %v3 to i32
; And this RHS operand is a constant too.
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll
index 737e97a7f36eb..fca5b76138127 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll
@@ -7,14 +7,12 @@
; Check DSP extension:
; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
-define dso_local i64 @OneReduction(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local i64 @OneReduction(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
;
; CHECK-LABEL: @OneReduction
; CHECK: %mac1{{\.}}026 = phi i64 [ [[V8:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ]
-; CHECK: [[V6:%[0-9]+]] = bitcast i16* %arrayidx to i32*
-; CHECK: [[V7:%[0-9]+]] = load i32, i32* [[V6]], align 2
-; CHECK: [[V4:%[0-9]+]] = bitcast i16* %arrayidx3 to i32*
-; CHECK: [[V5:%[0-9]+]] = load i32, i32* [[V4]], align 2
+; CHECK: [[V7:%[0-9]+]] = load i32, ptr %arrayidx, align 2
+; CHECK: [[V5:%[0-9]+]] = load i32, ptr %arrayidx3, align 2
; CHECK: [[V8]] = call i64 @llvm.arm.smlald(i32 [[V5]], i32 [[V7]], i64 %mac1{{\.}}026)
; CHECK-NOT: call i64 @llvm.arm.smlald
;
@@ -25,8 +23,8 @@ entry:
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -38,18 +36,18 @@ for.body:
%mac1.026 = phi i64 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i64
%conv4 = sext i16 %0 to i64
%mul = mul nsw i64 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i64
%conv8 = sext i16 %1 to i64
%mul9 = mul nsw i64 %conv7, %conv8
@@ -62,7 +60,7 @@ for.body:
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}
-define dso_local arm_aapcs_vfpcc i64 @TwoReductions(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local arm_aapcs_vfpcc i64 @TwoReductions(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
;
; CHECK-LABEL: @TwoReductions
;
@@ -91,37 +89,37 @@ for.body:
%mac2.057 = phi i64 [ %add28, %for.body ], [ 0, %for.body.preheader ]
%i.056 = phi i32 [ %add29, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.056
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.056
+ %0 = load i16, ptr %arrayidx, align 2
%add1 = or i32 %i.056, 1
- %arrayidx2 = getelementptr inbounds i16, i16* %arg3, i32 %add1
- %1 = load i16, i16* %arrayidx2, align 2
+ %arrayidx2 = getelementptr inbounds i16, ptr %arg3, i32 %add1
+ %1 = load i16, ptr %arrayidx2, align 2
%add3 = or i32 %i.056, 2
- %arrayidx4 = getelementptr inbounds i16, i16* %arg3, i32 %add3
- %2 = load i16, i16* %arrayidx4, align 2
+ %arrayidx4 = getelementptr inbounds i16, ptr %arg3, i32 %add3
+ %2 = load i16, ptr %arrayidx4, align 2
%add5 = or i32 %i.056, 3
- %arrayidx6 = getelementptr inbounds i16, i16* %arg3, i32 %add5
- %3 = load i16, i16* %arrayidx6, align 2
- %arrayidx8 = getelementptr inbounds i16, i16* %arg2, i32 %i.056
- %4 = load i16, i16* %arrayidx8, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg3, i32 %add5
+ %3 = load i16, ptr %arrayidx6, align 2
+ %arrayidx8 = getelementptr inbounds i16, ptr %arg2, i32 %i.056
+ %4 = load i16, ptr %arrayidx8, align 2
%conv = sext i16 %4 to i64
%conv9 = sext i16 %0 to i64
%mul = mul nsw i64 %conv, %conv9
- %arrayidx11 = getelementptr inbounds i16, i16* %arg2, i32 %add1
- %5 = load i16, i16* %arrayidx11, align 2
+ %arrayidx11 = getelementptr inbounds i16, ptr %arg2, i32 %add1
+ %5 = load i16, ptr %arrayidx11, align 2
%conv12 = sext i16 %5 to i64
%conv13 = sext i16 %1 to i64
%mul14 = mul nsw i64 %conv12, %conv13
%add15 = add i64 %mul, %mac1.058
%add16 = add i64 %add15, %mul14
- %arrayidx18 = getelementptr inbounds i16, i16* %arg2, i32 %add3
- %6 = load i16, i16* %arrayidx18, align 2
+ %arrayidx18 = getelementptr inbounds i16, ptr %arg2, i32 %add3
+ %6 = load i16, ptr %arrayidx18, align 2
%conv19 = sext i16 %6 to i64
%conv20 = sext i16 %2 to i64
%mul21 = mul nsw i64 %conv19, %conv20
- %arrayidx23 = getelementptr inbounds i16, i16* %arg2, i32 %add5
- %7 = load i16, i16* %arrayidx23, align 2
+ %arrayidx23 = getelementptr inbounds i16, ptr %arg2, i32 %add5
+ %7 = load i16, ptr %arrayidx23, align 2
%conv24 = sext i16 %7 to i64
%conv25 = sext i16 %3 to i64
%mul26 = mul nsw i64 %conv24, %conv25
@@ -132,7 +130,7 @@ for.body:
br i1 %cmp, label %for.body, label %for.cond.cleanup
}
-define i64 @reduction_zext(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define i64 @reduction_zext(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
; CHECK-LABEL: @reduction_zext
; CHECK-NOT: call i64 @llvm.arm.smlald
; CHECK-NOT: call i32 @llvm.arm.smlad
@@ -141,8 +139,8 @@ entry:
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -152,18 +150,18 @@ for.cond.cleanup:
for.body:
%mac1.026 = phi i64 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i64
%conv4 = zext i16 %0 to i64
%mul = mul nsw i64 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i64
%conv8 = zext i16 %1 to i64
%mul9 = mul nsw i64 %conv7, %conv8
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlald1.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlald1.ll
index f27292aa18f64..2ab6d713f0f4b 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/smlald1.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlald1.ll
@@ -2,20 +2,18 @@
; CHECK-LABEL: @test1
; CHECK: %mac1{{\.}}026 = phi i64 [ [[V8:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ]
-; CHECK: [[V6:%[0-9]+]] = bitcast i16* %arrayidx to i32*
-; CHECK: [[V7:%[0-9]+]] = load i32, i32* [[V6]], align 2
-; CHECK: [[V4:%[0-9]+]] = bitcast i16* %arrayidx3 to i32*
-; CHECK: [[V5:%[0-9]+]] = load i32, i32* [[V4]], align 2
+; CHECK: [[V7:%[0-9]+]] = load i32, ptr %arrayidx, align 2
+; CHECK: [[V5:%[0-9]+]] = load i32, ptr %arrayidx3, align 2
; CHECK: [[V8]] = call i64 @llvm.arm.smlald(i32 [[V5]], i32 [[V7]], i64 %mac1{{\.}}026)
-define dso_local i64 @test1(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local i64 @test1(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -25,18 +23,18 @@ for.cond.cleanup:
for.body:
%mac1.026 = phi i64 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i64
%conv4 = sext i16 %0 to i64
%mul = mul nsw i64 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i64
%conv8 = sext i16 %1 to i64
%mul9 = mul nsw i64 %conv7, %conv8
@@ -54,14 +52,14 @@ for.body:
; CHECK-LABEL: @test2
; CHECK-NOT: call i64 @llvm.arm.smlad
;
-define dso_local i64 @test2(i32 %arg, i32* nocapture readnone %arg1, i8* nocapture readonly %arg2, i8* nocapture readonly %arg3) {
+define dso_local i64 @test2(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
entry:
%cmp24 = icmp sgt i32 %arg, 0
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i8, i8* %arg3, align 2
- %.pre27 = load i8, i8* %arg2, align 2
+ %.pre = load i8, ptr %arg3, align 2
+ %.pre27 = load i8, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -71,18 +69,18 @@ for.cond.cleanup:
for.body:
%mac1.026 = phi i64 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i8, i8* %arg3, i32 %i.025
- %0 = load i8, i8* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i8, ptr %arg3, i32 %i.025
+ %0 = load i8, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i8, i8* %arg3, i32 %add
- %1 = load i8, i8* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i8, i8* %arg2, i32 %i.025
- %2 = load i8, i8* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i8, ptr %arg3, i32 %add
+ %1 = load i8, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i8, ptr %arg2, i32 %i.025
+ %2 = load i8, ptr %arrayidx3, align 2
%conv = sext i8 %2 to i64
%conv4 = sext i8 %0 to i64
%mul = mul nsw i64 %conv, %conv4
- %arrayidx6 = getelementptr inbounds i8, i8* %arg2, i32 %add
- %3 = load i8, i8* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i8, ptr %arg2, i32 %add
+ %3 = load i8, ptr %arrayidx6, align 2
%conv7 = sext i8 %3 to i64
%conv8 = sext i8 %1 to i64
%mul9 = mul nsw i64 %conv7, %conv8
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll
index 9b04fdffc6252..13c9199cc7924 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll
@@ -6,14 +6,12 @@
; Check DSP extension:
; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
-define dso_local i64 @OneReduction(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local i64 @OneReduction(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
;
; CHECK-LABEL: @OneReduction
; CHECK: %mac1{{\.}}026 = phi i64 [ [[V8:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ]
-; CHECK: [[V6:%[0-9]+]] = bitcast i16* %arrayidx to i32*
-; CHECK: [[V7:%[0-9]+]] = load i32, i32* [[V6]], align 2
-; CHECK: [[V4:%[0-9]+]] = bitcast i16* %arrayidx3 to i32*
-; CHECK: [[V5:%[0-9]+]] = load i32, i32* [[V4]], align 2
+; CHECK: [[V7:%[0-9]+]] = load i32, ptr %arrayidx, align 2
+; CHECK: [[V5:%[0-9]+]] = load i32, ptr %arrayidx3, align 2
; CHECK: [[V8]] = call i64 @llvm.arm.smlald(i32 [[V5]], i32 [[V7]], i64 %mac1{{\.}}026)
; CHECK-NOT: call i64 @llvm.arm.smlald
;
@@ -24,8 +22,8 @@ entry:
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -37,19 +35,19 @@ for.body:
%mac1.026 = phi i64 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
%sext0 = sext i32 %mul to i64
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = sext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
@@ -63,7 +61,7 @@ for.body:
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}
-define dso_local arm_aapcs_vfpcc i64 @TwoReductions(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local arm_aapcs_vfpcc i64 @TwoReductions(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
;
; CHECK-LABEL: @TwoReductions
;
@@ -92,40 +90,40 @@ for.body:
%mac2.057 = phi i64 [ %add28, %for.body ], [ 0, %for.body.preheader ]
%i.056 = phi i32 [ %add29, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.056
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.056
+ %0 = load i16, ptr %arrayidx, align 2
%add1 = or i32 %i.056, 1
- %arrayidx2 = getelementptr inbounds i16, i16* %arg3, i32 %add1
- %1 = load i16, i16* %arrayidx2, align 2
+ %arrayidx2 = getelementptr inbounds i16, ptr %arg3, i32 %add1
+ %1 = load i16, ptr %arrayidx2, align 2
%add3 = or i32 %i.056, 2
- %arrayidx4 = getelementptr inbounds i16, i16* %arg3, i32 %add3
- %2 = load i16, i16* %arrayidx4, align 2
+ %arrayidx4 = getelementptr inbounds i16, ptr %arg3, i32 %add3
+ %2 = load i16, ptr %arrayidx4, align 2
%add5 = or i32 %i.056, 3
- %arrayidx6 = getelementptr inbounds i16, i16* %arg3, i32 %add5
- %3 = load i16, i16* %arrayidx6, align 2
- %arrayidx8 = getelementptr inbounds i16, i16* %arg2, i32 %i.056
- %4 = load i16, i16* %arrayidx8, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg3, i32 %add5
+ %3 = load i16, ptr %arrayidx6, align 2
+ %arrayidx8 = getelementptr inbounds i16, ptr %arg2, i32 %i.056
+ %4 = load i16, ptr %arrayidx8, align 2
%conv = sext i16 %4 to i32
%conv9 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv9
%sext0 = sext i32 %mul to i64
- %arrayidx11 = getelementptr inbounds i16, i16* %arg2, i32 %add1
- %5 = load i16, i16* %arrayidx11, align 2
+ %arrayidx11 = getelementptr inbounds i16, ptr %arg2, i32 %add1
+ %5 = load i16, ptr %arrayidx11, align 2
%conv12 = sext i16 %5 to i32
%conv13 = sext i16 %1 to i32
%mul14 = mul nsw i32 %conv12, %conv13
%sext1 = sext i32 %mul14 to i64
%add15 = add i64 %sext0, %mac1.058
%add16 = add i64 %add15, %sext1
- %arrayidx18 = getelementptr inbounds i16, i16* %arg2, i32 %add3
- %6 = load i16, i16* %arrayidx18, align 2
+ %arrayidx18 = getelementptr inbounds i16, ptr %arg2, i32 %add3
+ %6 = load i16, ptr %arrayidx18, align 2
%conv19 = sext i16 %6 to i32
%conv20 = sext i16 %2 to i32
%mul21 = mul nsw i32 %conv19, %conv20
%sext2 = sext i32 %mul21 to i64
- %arrayidx23 = getelementptr inbounds i16, i16* %arg2, i32 %add5
- %7 = load i16, i16* %arrayidx23, align 2
+ %arrayidx23 = getelementptr inbounds i16, ptr %arg2, i32 %add5
+ %7 = load i16, ptr %arrayidx23, align 2
%conv24 = sext i16 %7 to i32
%conv25 = sext i16 %3 to i32
%mul26 = mul nsw i32 %conv24, %conv25
@@ -137,7 +135,7 @@ for.body:
br i1 %cmp, label %for.body, label %for.cond.cleanup
}
-define i64 @zext_mul_reduction(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define i64 @zext_mul_reduction(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
; CHECK-LABEL: @zext_mul_reduction
; CHECK-NOT: call i64 @llvm.arm.smlald
; CHECK-NOT: call i32 @llvm.arm.smlad
@@ -146,8 +144,8 @@ entry:
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -157,19 +155,19 @@ for.cond.cleanup:
for.body:
%mac1.026 = phi i64 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = zext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
%sext0 = sext i32 %mul to i64
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = zext i16 %3 to i32
%conv8 = sext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
@@ -180,7 +178,7 @@ for.body:
br i1 %exitcond, label %for.body, label %for.cond.cleanup
}
-define i64 @zext_add_reduction(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define i64 @zext_add_reduction(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
; CHECK-LABEL: @zext_add_reduction
; CHECK-NOT: call i64 @llvm.arm.smlald
; CHECK-NOT: call i32 @llvm.arm.smlad
@@ -189,8 +187,8 @@ entry:
br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader:
- %.pre = load i16, i16* %arg3, align 2
- %.pre27 = load i16, i16* %arg2, align 2
+ %.pre = load i16, ptr %arg3, align 2
+ %.pre27 = load i16, ptr %arg2, align 2
br label %for.body
for.cond.cleanup:
@@ -200,19 +198,19 @@ for.cond.cleanup:
for.body:
%mac1.026 = phi i64 [ %add11, %for.body ], [ 0, %for.body.preheader ]
%i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.025
+ %0 = load i16, ptr %arrayidx, align 2
%add = add nuw nsw i32 %i.025, 1
- %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
- %1 = load i16, i16* %arrayidx1, align 2
- %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
- %2 = load i16, i16* %arrayidx3, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add
+ %1 = load i16, ptr %arrayidx1, align 2
+ %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.025
+ %2 = load i16, ptr %arrayidx3, align 2
%conv = sext i16 %2 to i32
%conv4 = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv4
%sext0 = zext i32 %mul to i64
- %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
- %3 = load i16, i16* %arrayidx6, align 2
+ %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add
+ %3 = load i16, ptr %arrayidx6, align 2
%conv7 = sext i16 %3 to i32
%conv8 = sext i16 %1 to i32
%mul9 = mul nsw i32 %conv7, %conv8
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/squaring.ll b/llvm/test/CodeGen/ARM/ParallelDSP/squaring.ll
index 88e23a8957f1f..5a5025d94b4da 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/squaring.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/squaring.ll
@@ -5,76 +5,73 @@ define dso_local void @a() align 2 {
; CHECK-LABEL: @a(
; CHECK-NEXT: for.end:
; CHECK-NEXT: [[B:%.*]] = alloca i32, align 4
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* bitcast (void ()* @a to i16*), align 2
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr @a, align 2
; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[CONV]], [[CONV]]
-; CHECK-NEXT: [[TMP1:%.*]] = load i16, i16* getelementptr (i16, i16* bitcast (void ()* @a to i16*), i32 1), align 2
+; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i16, ptr @a, i32 1), align 2
; CHECK-NEXT: [[CONV3:%.*]] = sext i16 [[TMP1]] to i32
; CHECK-NEXT: [[MUL6:%.*]] = mul nsw i32 [[CONV3]], [[CONV3]]
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[MUL6]], [[MUL]]
-; CHECK-NEXT: [[TMP2:%.*]] = load i16, i16* getelementptr (i16, i16* bitcast (void ()* @a to i16*), i32 2), align 2
+; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr getelementptr (i16, ptr @a, i32 2), align 2
; CHECK-NEXT: [[CONV11:%.*]] = sext i16 [[TMP2]] to i32
; CHECK-NEXT: [[MUL12:%.*]] = mul nsw i32 [[CONV11]], [[CONV3]]
; CHECK-NEXT: [[ADD14:%.*]] = add nsw i32 [[MUL12]], [[ADD]]
-; CHECK-NEXT: [[TMP3:%.*]] = load i16, i16* getelementptr (i16, i16* bitcast (void ()* @a to i16*), i32 3), align 2
+; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr getelementptr (i16, ptr @a, i32 3), align 2
; CHECK-NEXT: [[CONV17:%.*]] = sext i16 [[TMP3]] to i32
; CHECK-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD14]], [[CONV17]]
-; CHECK-NEXT: store i32 [[ADD19]], i32* [[B]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = load i16, i16* getelementptr (i16, i16* bitcast (void ()* @a to i16*), i32 4), align 2
+; CHECK-NEXT: store i32 [[ADD19]], ptr [[B]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr getelementptr (i16, ptr @a, i32 4), align 2
; CHECK-NEXT: [[CONV21:%.*]] = sext i16 [[TMP4]] to i32
-; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[B]], i32 [[CONV21]]
-; CHECK-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds i32, i32* [[ADD_PTR]], i32 9
-; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX22]], align 4
+; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[CONV21]]
+; CHECK-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds i32, ptr [[ADD_PTR]], i32 9
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX22]], align 4
; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[TMP5]], 1
-; CHECK-NEXT: store i32 [[SHL]], i32* [[ARRAYIDX22]], align 4
+; CHECK-NEXT: store i32 [[SHL]], ptr [[ARRAYIDX22]], align 4
; CHECK-NEXT: br label [[FOR_COND23:%.*]]
; CHECK: for.cond23:
; CHECK-NEXT: br label [[FOR_COND23]]
;
for.end:
%b = alloca i32, align 4
- %0 = bitcast i32* %b to i8*
- %1 = load i16, i16* bitcast (void ()* @a to i16*), align 2
- %conv = sext i16 %1 to i32
+ %0 = load i16, ptr @a, align 2
+ %conv = sext i16 %0 to i32
%mul = mul nsw i32 %conv, %conv
- %2 = load i16, i16* getelementptr (i16, i16* bitcast (void ()* @a to i16*), i32 1), align 2
- %conv3 = sext i16 %2 to i32
+ %1 = load i16, ptr getelementptr (i16, ptr @a, i32 1), align 2
+ %conv3 = sext i16 %1 to i32
%mul6 = mul nsw i32 %conv3, %conv3
%add = add nuw nsw i32 %mul6, %mul
- %3 = load i16, i16* getelementptr (i16, i16* bitcast (void ()* @a to i16*), i32 2), align 2
- %conv11 = sext i16 %3 to i32
+ %2 = load i16, ptr getelementptr (i16, ptr @a, i32 2), align 2
+ %conv11 = sext i16 %2 to i32
%mul12 = mul nsw i32 %conv11, %conv3
%add14 = add nsw i32 %mul12, %add
- %4 = load i16, i16* getelementptr (i16, i16* bitcast (void ()* @a to i16*), i32 3), align 2
- %conv17 = sext i16 %4 to i32
+ %3 = load i16, ptr getelementptr (i16, ptr @a, i32 3), align 2
+ %conv17 = sext i16 %3 to i32
%add19 = add nsw i32 %add14, %conv17
- store i32 %add19, i32* %b, align 4
- %5 = load i16, i16* getelementptr (i16, i16* bitcast (void ()* @a to i16*), i32 4), align 2
- %conv21 = sext i16 %5 to i32
- %add.ptr = getelementptr inbounds i32, i32* %b, i32 %conv21
- %arrayidx22 = getelementptr inbounds i32, i32* %add.ptr, i32 9
- %6 = load i32, i32* %arrayidx22, align 4
- %shl = shl i32 %6, 1
- store i32 %shl, i32* %arrayidx22, align 4
+ store i32 %add19, ptr %b, align 4
+ %4 = load i16, ptr getelementptr (i16, ptr @a, i32 4), align 2
+ %conv21 = sext i16 %4 to i32
+ %add.ptr = getelementptr inbounds i32, ptr %b, i32 %conv21
+ %arrayidx22 = getelementptr inbounds i32, ptr %add.ptr, i32 9
+ %5 = load i32, ptr %arrayidx22, align 4
+ %shl = shl i32 %5, 1
+ store i32 %shl, ptr %arrayidx22, align 4
br label %for.cond23
for.cond23: ; preds = %for.cond23, %for.end
br label %for.cond23
}
-define i32 @accumulate_square_a0(i16* %a, i16* %b, i32 %acc) {
+define i32 @accumulate_square_a0(ptr %a, ptr %b, i32 %acc) {
; CHECK-LABEL: @accumulate_square_a0(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[ADDR_A_1:%.*]] = getelementptr i16, i16* [[A:%.*]], i32 1
-; CHECK-NEXT: [[ADDR_B_1:%.*]] = getelementptr i16, i16* [[B:%.*]], i32 1
-; CHECK-NEXT: [[LD_A_0:%.*]] = load i16, i16* [[A]]
+; CHECK-NEXT: [[ADDR_A_1:%.*]] = getelementptr i16, ptr [[A:%.*]], i32 1
+; CHECK-NEXT: [[ADDR_B_1:%.*]] = getelementptr i16, ptr [[B:%.*]], i32 1
+; CHECK-NEXT: [[LD_A_0:%.*]] = load i16, ptr [[A]]
; CHECK-NEXT: [[SEXT_A_0:%.*]] = sext i16 [[LD_A_0]] to i32
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast i16* [[ADDR_A_1]] to i32*
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 2
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ADDR_A_1]], align 2
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[TMP2]] to i32
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast i16* [[ADDR_B_1]] to i32*
-; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 2
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ADDR_B_1]], align 2
; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16
; CHECK-NEXT: [[TMP7:%.*]] = sext i16 [[TMP6]] to i32
; CHECK-NEXT: [[MUL_0:%.*]] = mul i32 [[SEXT_A_0]], [[SEXT_A_0]]
@@ -85,22 +82,22 @@ define i32 @accumulate_square_a0(i16* %a, i16* %b, i32 %acc) {
; CHECK-NEXT: ret i32 [[TMP10]]
;
entry:
- %addr.a.1 = getelementptr i16, i16* %a, i32 1
- %addr.b.1 = getelementptr i16, i16* %b, i32 1
- %ld.a.0 = load i16, i16* %a
+ %addr.a.1 = getelementptr i16, ptr %a, i32 1
+ %addr.b.1 = getelementptr i16, ptr %b, i32 1
+ %ld.a.0 = load i16, ptr %a
%sext.a.0 = sext i16 %ld.a.0 to i32
- %ld.b.0 = load i16, i16* %b
- %ld.a.1 = load i16, i16* %addr.a.1
- %ld.b.1 = load i16, i16* %addr.b.1
+ %ld.b.0 = load i16, ptr %b
+ %ld.a.1 = load i16, ptr %addr.a.1
+ %ld.b.1 = load i16, ptr %addr.b.1
%sext.a.1 = sext i16 %ld.a.1 to i32
%sext.b.1 = sext i16 %ld.b.1 to i32
%sext.b.0 = sext i16 %ld.b.0 to i32
%mul.0 = mul i32 %sext.a.0, %sext.a.0
%mul.1 = mul i32 %sext.a.1, %sext.b.1
- %addr.a.2 = getelementptr i16, i16* %a, i32 2
- %addr.b.2 = getelementptr i16, i16* %b, i32 2
- %ld.a.2 = load i16, i16* %addr.a.2
- %ld.b.2 = load i16, i16* %addr.b.2
+ %addr.a.2 = getelementptr i16, ptr %a, i32 2
+ %addr.b.2 = getelementptr i16, ptr %b, i32 2
+ %ld.a.2 = load i16, ptr %addr.a.2
+ %ld.b.2 = load i16, ptr %addr.b.2
%sext.a.2 = sext i16 %ld.a.2 to i32
%sext.b.2 = sext i16 %ld.b.2 to i32
%mul.2 = mul i32 %sext.a.2, %sext.b.2
@@ -111,24 +108,22 @@ entry:
ret i32 %res
}
-define i32 @accumulate_square_a2(i16* %a, i16* %b, i32 %acc) {
+define i32 @accumulate_square_a2(ptr %a, ptr %b, i32 %acc) {
; CHECK-LABEL: @accumulate_square_a2(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast i16* [[A:%.*]] to i32*
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 2
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A:%.*]], align 2
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 16
; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16
; CHECK-NEXT: [[TMP4:%.*]] = sext i16 [[TMP3]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = bitcast i16* [[B:%.*]] to i32*
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 2
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[B:%.*]], align 2
; CHECK-NEXT: [[TMP7:%.*]] = lshr i32 [[TMP6]], 16
; CHECK-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i16
; CHECK-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
; CHECK-NEXT: [[MUL_1:%.*]] = mul i32 [[TMP4]], [[TMP9]]
-; CHECK-NEXT: [[ADDR_A_2:%.*]] = getelementptr i16, i16* [[A]], i32 2
-; CHECK-NEXT: [[ADDR_B_2:%.*]] = getelementptr i16, i16* [[B]], i32 2
-; CHECK-NEXT: [[LD_A_2:%.*]] = load i16, i16* [[ADDR_A_2]]
-; CHECK-NEXT: [[LD_B_2:%.*]] = load i16, i16* [[ADDR_B_2]]
+; CHECK-NEXT: [[ADDR_A_2:%.*]] = getelementptr i16, ptr [[A]], i32 2
+; CHECK-NEXT: [[ADDR_B_2:%.*]] = getelementptr i16, ptr [[B]], i32 2
+; CHECK-NEXT: [[LD_A_2:%.*]] = load i16, ptr [[ADDR_A_2]]
+; CHECK-NEXT: [[LD_B_2:%.*]] = load i16, ptr [[ADDR_B_2]]
; CHECK-NEXT: [[SEXT_A_2:%.*]] = sext i16 [[LD_A_2]] to i32
; CHECK-NEXT: [[SEXT_B_2:%.*]] = sext i16 [[LD_B_2]] to i32
; CHECK-NEXT: [[MUL_2:%.*]] = mul i32 [[SEXT_A_2]], [[SEXT_A_2]]
@@ -139,22 +134,22 @@ define i32 @accumulate_square_a2(i16* %a, i16* %b, i32 %acc) {
; CHECK-NEXT: ret i32 [[RES]]
;
entry:
- %addr.a.1 = getelementptr i16, i16* %a, i32 1
- %addr.b.1 = getelementptr i16, i16* %b, i32 1
- %ld.a.0 = load i16, i16* %a
+ %addr.a.1 = getelementptr i16, ptr %a, i32 1
+ %addr.b.1 = getelementptr i16, ptr %b, i32 1
+ %ld.a.0 = load i16, ptr %a
%sext.a.0 = sext i16 %ld.a.0 to i32
- %ld.b.0 = load i16, i16* %b
- %ld.a.1 = load i16, i16* %addr.a.1
- %ld.b.1 = load i16, i16* %addr.b.1
+ %ld.b.0 = load i16, ptr %b
+ %ld.a.1 = load i16, ptr %addr.a.1
+ %ld.b.1 = load i16, ptr %addr.b.1
%sext.a.1 = sext i16 %ld.a.1 to i32
%sext.b.1 = sext i16 %ld.b.1 to i32
%sext.b.0 = sext i16 %ld.b.0 to i32
%mul.0 = mul i32 %sext.a.0, %sext.b.0
%mul.1 = mul i32 %sext.a.1, %sext.b.1
- %addr.a.2 = getelementptr i16, i16* %a, i32 2
- %addr.b.2 = getelementptr i16, i16* %b, i32 2
- %ld.a.2 = load i16, i16* %addr.a.2
- %ld.b.2 = load i16, i16* %addr.b.2
+ %addr.a.2 = getelementptr i16, ptr %a, i32 2
+ %addr.b.2 = getelementptr i16, ptr %b, i32 2
+ %ld.a.2 = load i16, ptr %addr.a.2
+ %ld.b.2 = load i16, ptr %addr.b.2
%sext.a.2 = sext i16 %ld.a.2 to i32
%sext.b.2 = sext i16 %ld.b.2 to i32
%mul.2 = mul i32 %sext.a.2, %sext.a.2
@@ -166,21 +161,21 @@ entry:
ret i32 %res
}
-define i32 @accumulate_square_b2(i16* %a, i16* %b, i32 %acc) {
+define i32 @accumulate_square_b2(ptr %a, ptr %b, i32 %acc) {
; CHECK-LABEL: @accumulate_square_b2(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[ADDR_A_1:%.*]] = getelementptr i16, i16* [[A:%.*]], i32 1
-; CHECK-NEXT: [[ADDR_B_1:%.*]] = getelementptr i16, i16* [[B:%.*]], i32 1
-; CHECK-NEXT: [[LD_A_0:%.*]] = load i16, i16* [[A]]
+; CHECK-NEXT: [[ADDR_A_1:%.*]] = getelementptr i16, ptr [[A:%.*]], i32 1
+; CHECK-NEXT: [[ADDR_B_1:%.*]] = getelementptr i16, ptr [[B:%.*]], i32 1
+; CHECK-NEXT: [[LD_A_0:%.*]] = load i16, ptr [[A]]
; CHECK-NEXT: [[SEXT_A_0:%.*]] = sext i16 [[LD_A_0]] to i32
-; CHECK-NEXT: [[LD_A_1:%.*]] = load i16, i16* [[ADDR_A_1]]
-; CHECK-NEXT: [[LD_B_1:%.*]] = load i16, i16* [[ADDR_B_1]]
+; CHECK-NEXT: [[LD_A_1:%.*]] = load i16, ptr [[ADDR_A_1]]
+; CHECK-NEXT: [[LD_B_1:%.*]] = load i16, ptr [[ADDR_B_1]]
; CHECK-NEXT: [[SEXT_A_1:%.*]] = sext i16 [[LD_A_1]] to i32
; CHECK-NEXT: [[SEXT_B_1:%.*]] = sext i16 [[LD_B_1]] to i32
; CHECK-NEXT: [[MUL_0:%.*]] = mul i32 [[SEXT_A_0]], [[SEXT_A_0]]
; CHECK-NEXT: [[MUL_1:%.*]] = mul i32 [[SEXT_A_1]], [[SEXT_B_1]]
-; CHECK-NEXT: [[ADDR_B_2:%.*]] = getelementptr i16, i16* [[B]], i32 2
-; CHECK-NEXT: [[LD_B_2:%.*]] = load i16, i16* [[ADDR_B_2]]
+; CHECK-NEXT: [[ADDR_B_2:%.*]] = getelementptr i16, ptr [[B]], i32 2
+; CHECK-NEXT: [[LD_B_2:%.*]] = load i16, ptr [[ADDR_B_2]]
; CHECK-NEXT: [[SEXT_B_2:%.*]] = sext i16 [[LD_B_2]] to i32
; CHECK-NEXT: [[MUL_2:%.*]] = mul i32 [[SEXT_B_2]], [[SEXT_B_2]]
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[MUL_0]], [[MUL_1]]
@@ -190,22 +185,22 @@ define i32 @accumulate_square_b2(i16* %a, i16* %b, i32 %acc) {
; CHECK-NEXT: ret i32 [[RES]]
;
entry:
- %addr.a.1 = getelementptr i16, i16* %a, i32 1
- %addr.b.1 = getelementptr i16, i16* %b, i32 1
- %ld.a.0 = load i16, i16* %a
+ %addr.a.1 = getelementptr i16, ptr %a, i32 1
+ %addr.b.1 = getelementptr i16, ptr %b, i32 1
+ %ld.a.0 = load i16, ptr %a
%sext.a.0 = sext i16 %ld.a.0 to i32
- %ld.b.0 = load i16, i16* %b
- %ld.a.1 = load i16, i16* %addr.a.1
- %ld.b.1 = load i16, i16* %addr.b.1
+ %ld.b.0 = load i16, ptr %b
+ %ld.a.1 = load i16, ptr %addr.a.1
+ %ld.b.1 = load i16, ptr %addr.b.1
%sext.a.1 = sext i16 %ld.a.1 to i32
%sext.b.1 = sext i16 %ld.b.1 to i32
%sext.b.0 = sext i16 %ld.b.0 to i32
%mul.0 = mul i32 %sext.a.0, %sext.a.0
%mul.1 = mul i32 %sext.a.1, %sext.b.1
- %addr.a.2 = getelementptr i16, i16* %a, i32 2
- %addr.b.2 = getelementptr i16, i16* %b, i32 2
- %ld.a.2 = load i16, i16* %addr.a.2
- %ld.b.2 = load i16, i16* %addr.b.2
+ %addr.a.2 = getelementptr i16, ptr %a, i32 2
+ %addr.b.2 = getelementptr i16, ptr %b, i32 2
+ %ld.a.2 = load i16, ptr %addr.a.2
+ %ld.b.2 = load i16, ptr %addr.b.2
%sext.a.2 = sext i16 %ld.a.2 to i32
%sext.b.2 = sext i16 %ld.b.2 to i32
%mul.2 = mul i32 %sext.b.2, %sext.b.2
@@ -217,23 +212,23 @@ entry:
ret i32 %res
}
-define i32 @accumulate_square_a1(i16* %a, i16* %b, i32 %acc) {
+define i32 @accumulate_square_a1(ptr %a, ptr %b, i32 %acc) {
; CHECK-LABEL: @accumulate_square_a1(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[ADDR_A_1:%.*]] = getelementptr i16, i16* [[A:%.*]], i32 1
-; CHECK-NEXT: [[ADDR_B_1:%.*]] = getelementptr i16, i16* [[B:%.*]], i32 1
-; CHECK-NEXT: [[LD_A_0:%.*]] = load i16, i16* [[A]]
+; CHECK-NEXT: [[ADDR_A_1:%.*]] = getelementptr i16, ptr [[A:%.*]], i32 1
+; CHECK-NEXT: [[ADDR_B_1:%.*]] = getelementptr i16, ptr [[B:%.*]], i32 1
+; CHECK-NEXT: [[LD_A_0:%.*]] = load i16, ptr [[A]]
; CHECK-NEXT: [[SEXT_A_0:%.*]] = sext i16 [[LD_A_0]] to i32
-; CHECK-NEXT: [[LD_A_1:%.*]] = load i16, i16* [[ADDR_A_1]]
-; CHECK-NEXT: [[LD_B_1:%.*]] = load i16, i16* [[ADDR_B_1]]
+; CHECK-NEXT: [[LD_A_1:%.*]] = load i16, ptr [[ADDR_A_1]]
+; CHECK-NEXT: [[LD_B_1:%.*]] = load i16, ptr [[ADDR_B_1]]
; CHECK-NEXT: [[SEXT_A_1:%.*]] = sext i16 [[LD_A_1]] to i32
; CHECK-NEXT: [[SEXT_B_1:%.*]] = sext i16 [[LD_B_1]] to i32
; CHECK-NEXT: [[MUL_0:%.*]] = mul i32 [[SEXT_A_0]], [[SEXT_A_0]]
; CHECK-NEXT: [[MUL_1:%.*]] = mul i32 [[SEXT_A_1]], [[SEXT_A_1]]
-; CHECK-NEXT: [[ADDR_A_2:%.*]] = getelementptr i16, i16* [[A]], i32 2
-; CHECK-NEXT: [[ADDR_B_2:%.*]] = getelementptr i16, i16* [[B]], i32 2
-; CHECK-NEXT: [[LD_A_2:%.*]] = load i16, i16* [[ADDR_A_2]]
-; CHECK-NEXT: [[LD_B_2:%.*]] = load i16, i16* [[ADDR_B_2]]
+; CHECK-NEXT: [[ADDR_A_2:%.*]] = getelementptr i16, ptr [[A]], i32 2
+; CHECK-NEXT: [[ADDR_B_2:%.*]] = getelementptr i16, ptr [[B]], i32 2
+; CHECK-NEXT: [[LD_A_2:%.*]] = load i16, ptr [[ADDR_A_2]]
+; CHECK-NEXT: [[LD_B_2:%.*]] = load i16, ptr [[ADDR_B_2]]
; CHECK-NEXT: [[SEXT_A_2:%.*]] = sext i16 [[LD_A_2]] to i32
; CHECK-NEXT: [[SEXT_B_2:%.*]] = sext i16 [[LD_B_2]] to i32
; CHECK-NEXT: [[MUL_2:%.*]] = mul i32 [[SEXT_A_2]], [[SEXT_B_2]]
@@ -246,22 +241,22 @@ define i32 @accumulate_square_a1(i16* %a, i16* %b, i32 %acc) {
; CHECK-NEXT: ret i32 [[RES]]
;
entry:
- %addr.a.1 = getelementptr i16, i16* %a, i32 1
- %addr.b.1 = getelementptr i16, i16* %b, i32 1
- %ld.a.0 = load i16, i16* %a
+ %addr.a.1 = getelementptr i16, ptr %a, i32 1
+ %addr.b.1 = getelementptr i16, ptr %b, i32 1
+ %ld.a.0 = load i16, ptr %a
%sext.a.0 = sext i16 %ld.a.0 to i32
- %ld.b.0 = load i16, i16* %b
- %ld.a.1 = load i16, i16* %addr.a.1
- %ld.b.1 = load i16, i16* %addr.b.1
+ %ld.b.0 = load i16, ptr %b
+ %ld.a.1 = load i16, ptr %addr.a.1
+ %ld.b.1 = load i16, ptr %addr.b.1
%sext.a.1 = sext i16 %ld.a.1 to i32
%sext.b.1 = sext i16 %ld.b.1 to i32
%sext.b.0 = sext i16 %ld.b.0 to i32
%mul.0 = mul i32 %sext.a.0, %sext.a.0
%mul.1 = mul i32 %sext.a.1, %sext.a.1
- %addr.a.2 = getelementptr i16, i16* %a, i32 2
- %addr.b.2 = getelementptr i16, i16* %b, i32 2
- %ld.a.2 = load i16, i16* %addr.a.2
- %ld.b.2 = load i16, i16* %addr.b.2
+ %addr.a.2 = getelementptr i16, ptr %a, i32 2
+ %addr.b.2 = getelementptr i16, ptr %b, i32 2
+ %ld.a.2 = load i16, ptr %addr.a.2
+ %ld.b.2 = load i16, ptr %addr.b.2
%sext.a.2 = sext i16 %ld.a.2 to i32
%sext.b.2 = sext i16 %ld.b.2 to i32
%mul.2 = mul i32 %sext.a.2, %sext.b.2
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll b/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
index 1e988fe34bf33..3890edeaa353d 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
@@ -9,24 +9,24 @@
; the parallel operations.
; CHECK-LABEL: unroll_n_jam_smlad
-define void @unroll_n_jam_smlad(i32* %res, i16* %A, i16* %B, i32 %N, i32 %idx) {
+define void @unroll_n_jam_smlad(ptr %res, ptr %A, ptr %B, i32 %N, i32 %idx) {
entry:
%xtraiter306.i = and i32 %N, 3
%unroll_iter310.i = sub i32 %N, %xtraiter306.i
- %arrayidx.us.i117.i = getelementptr inbounds i32, i32* %res, i32 %idx
- store i32 0, i32* %arrayidx.us.i117.i, align 4
+ %arrayidx.us.i117.i = getelementptr inbounds i32, ptr %res, i32 %idx
+ store i32 0, ptr %arrayidx.us.i117.i, align 4
%mul.us.i118.i = mul i32 %idx, %N
%inc11.us.i.i = or i32 %idx, 1
- %arrayidx.us.i117.1.i = getelementptr inbounds i32, i32* %res, i32 %inc11.us.i.i
- store i32 0, i32* %arrayidx.us.i117.1.i, align 4
+ %arrayidx.us.i117.1.i = getelementptr inbounds i32, ptr %res, i32 %inc11.us.i.i
+ store i32 0, ptr %arrayidx.us.i117.1.i, align 4
%mul.us.i118.1.i = mul i32 %inc11.us.i.i, %N
%inc11.us.i.1.i = or i32 %idx, 2
- %arrayidx.us.i117.2.i = getelementptr inbounds i32, i32* %res, i32 %inc11.us.i.1.i
- store i32 0, i32* %arrayidx.us.i117.2.i, align 4
+ %arrayidx.us.i117.2.i = getelementptr inbounds i32, ptr %res, i32 %inc11.us.i.1.i
+ store i32 0, ptr %arrayidx.us.i117.2.i, align 4
%mul.us.i118.2.i = mul i32 %inc11.us.i.1.i, %N
%inc11.us.i.2.i = or i32 %idx, 3
- %arrayidx.us.i117.3.i = getelementptr inbounds i32, i32* %res, i32 %inc11.us.i.2.i
- store i32 0, i32* %arrayidx.us.i117.3.i, align 4
+ %arrayidx.us.i117.3.i = getelementptr inbounds i32, ptr %res, i32 %inc11.us.i.2.i
+ store i32 0, ptr %arrayidx.us.i117.3.i, align 4
%mul.us.i118.3.i = mul i32 %inc11.us.i.2.i, %N
%inc11.us.i.3.i = add i32 %idx, 4
br label %for.body
@@ -55,159 +55,159 @@ for.body:
%A6 = phi i32 [ %add9.us.i.3.3.i, %for.body ], [ 0, %entry ]
%niter335.i = phi i32 [ %niter335.nsub.3.i, %for.body ], [ %unroll_iter310.i, %entry ]
%add.us.i.i = add i32 %j.026.us.i.i, %mul.us.i118.i
- %arrayidx4.us.i.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.i
- %A7 = load i16, i16* %arrayidx4.us.i.i, align 2
+ %arrayidx4.us.i.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.i
+ %A7 = load i16, ptr %arrayidx4.us.i.i, align 2
%conv.us.i.i = sext i16 %A7 to i32
- %arrayidx5.us.i.i = getelementptr inbounds i16, i16* %B, i32 %j.026.us.i.i
- %A8 = load i16, i16* %arrayidx5.us.i.i, align 2
+ %arrayidx5.us.i.i = getelementptr inbounds i16, ptr %B, i32 %j.026.us.i.i
+ %A8 = load i16, ptr %arrayidx5.us.i.i, align 2
%conv6.us.i.i = sext i16 %A8 to i32
%mul7.us.i.i = mul nsw i32 %conv6.us.i.i, %conv.us.i.i
%add9.us.i.i = add nsw i32 %mul7.us.i.i, %A3
%inc.us.i.i = or i32 %j.026.us.i.i, 1
%add.us.i.1.i = add i32 %j.026.us.i.i, %mul.us.i118.1.i
- %arrayidx4.us.i.1.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.1.i
- %A9 = load i16, i16* %arrayidx4.us.i.1.i, align 2
+ %arrayidx4.us.i.1.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.1.i
+ %A9 = load i16, ptr %arrayidx4.us.i.1.i, align 2
%conv.us.i.1.i = sext i16 %A9 to i32
- %arrayidx5.us.i.1.i = getelementptr inbounds i16, i16* %B, i32 %j.026.us.i.i
- %B0 = load i16, i16* %arrayidx5.us.i.1.i, align 2
+ %arrayidx5.us.i.1.i = getelementptr inbounds i16, ptr %B, i32 %j.026.us.i.i
+ %B0 = load i16, ptr %arrayidx5.us.i.1.i, align 2
%conv6.us.i.1.i = sext i16 %B0 to i32
%mul7.us.i.1.i = mul nsw i32 %conv6.us.i.1.i, %conv.us.i.1.i
%add9.us.i.1.i = add nsw i32 %mul7.us.i.1.i, %A4
%inc.us.i.1.i = or i32 %j.026.us.i.i, 1
%add.us.i.2.i = add i32 %j.026.us.i.i, %mul.us.i118.2.i
- %arrayidx4.us.i.2.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.2.i
- %B1 = load i16, i16* %arrayidx4.us.i.2.i, align 2
+ %arrayidx4.us.i.2.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.2.i
+ %B1 = load i16, ptr %arrayidx4.us.i.2.i, align 2
%conv.us.i.2.i = sext i16 %B1 to i32
- %arrayidx5.us.i.2.i = getelementptr inbounds i16, i16* %B, i32 %j.026.us.i.i
- %B2 = load i16, i16* %arrayidx5.us.i.2.i, align 2
+ %arrayidx5.us.i.2.i = getelementptr inbounds i16, ptr %B, i32 %j.026.us.i.i
+ %B2 = load i16, ptr %arrayidx5.us.i.2.i, align 2
%conv6.us.i.2.i = sext i16 %B2 to i32
%mul7.us.i.2.i = mul nsw i32 %conv6.us.i.2.i, %conv.us.i.2.i
%add9.us.i.2.i = add nsw i32 %mul7.us.i.2.i, %A5
%inc.us.i.2.i = or i32 %j.026.us.i.i, 1
%add.us.i.3.i = add i32 %j.026.us.i.i, %mul.us.i118.3.i
- %arrayidx4.us.i.3.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.3.i
- %B3 = load i16, i16* %arrayidx4.us.i.3.i, align 2
+ %arrayidx4.us.i.3.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.3.i
+ %B3 = load i16, ptr %arrayidx4.us.i.3.i, align 2
%conv.us.i.3.i = sext i16 %B3 to i32
- %arrayidx5.us.i.3.i = getelementptr inbounds i16, i16* %B, i32 %j.026.us.i.i
- %B4 = load i16, i16* %arrayidx5.us.i.3.i, align 2
+ %arrayidx5.us.i.3.i = getelementptr inbounds i16, ptr %B, i32 %j.026.us.i.i
+ %B4 = load i16, ptr %arrayidx5.us.i.3.i, align 2
%conv6.us.i.3.i = sext i16 %B4 to i32
%mul7.us.i.3.i = mul nsw i32 %conv6.us.i.3.i, %conv.us.i.3.i
%add9.us.i.3.i = add nsw i32 %mul7.us.i.3.i, %A6
%inc.us.i.3.i = or i32 %j.026.us.i.i, 1
%add.us.i.1337.i = add i32 %inc.us.i.i, %mul.us.i118.i
- %arrayidx4.us.i.1338.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.1337.i
- %B5 = load i16, i16* %arrayidx4.us.i.1338.i, align 2
+ %arrayidx4.us.i.1338.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.1337.i
+ %B5 = load i16, ptr %arrayidx4.us.i.1338.i, align 2
%conv.us.i.1339.i = sext i16 %B5 to i32
- %arrayidx5.us.i.1340.i = getelementptr inbounds i16, i16* %B, i32 %inc.us.i.i
- %B6 = load i16, i16* %arrayidx5.us.i.1340.i, align 2
+ %arrayidx5.us.i.1340.i = getelementptr inbounds i16, ptr %B, i32 %inc.us.i.i
+ %B6 = load i16, ptr %arrayidx5.us.i.1340.i, align 2
%conv6.us.i.1341.i = sext i16 %B6 to i32
%mul7.us.i.1342.i = mul nsw i32 %conv6.us.i.1341.i, %conv.us.i.1339.i
%add9.us.i.1343.i = add nsw i32 %mul7.us.i.1342.i, %add9.us.i.i
%inc.us.i.1344.i = or i32 %j.026.us.i.i, 2
%add.us.i.1.1.i = add i32 %inc.us.i.1.i, %mul.us.i118.1.i
- %arrayidx4.us.i.1.1.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.1.1.i
- %B7 = load i16, i16* %arrayidx4.us.i.1.1.i, align 2
+ %arrayidx4.us.i.1.1.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.1.1.i
+ %B7 = load i16, ptr %arrayidx4.us.i.1.1.i, align 2
%conv.us.i.1.1.i = sext i16 %B7 to i32
- %arrayidx5.us.i.1.1.i = getelementptr inbounds i16, i16* %B, i32 %inc.us.i.1.i
- %B6.dup = load i16, i16* %arrayidx5.us.i.1.1.i, align 2
+ %arrayidx5.us.i.1.1.i = getelementptr inbounds i16, ptr %B, i32 %inc.us.i.1.i
+ %B6.dup = load i16, ptr %arrayidx5.us.i.1.1.i, align 2
%conv6.us.i.1.1.i = sext i16 %B6.dup to i32
%mul7.us.i.1.1.i = mul nsw i32 %conv6.us.i.1.1.i, %conv.us.i.1.1.i
%add9.us.i.1.1.i = add nsw i32 %mul7.us.i.1.1.i, %add9.us.i.1.i
%inc.us.i.1.1.i = or i32 %j.026.us.i.i, 2
%add.us.i.2.1.i = add i32 %inc.us.i.2.i, %mul.us.i118.2.i
- %arrayidx4.us.i.2.1.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.2.1.i
- %B9 = load i16, i16* %arrayidx4.us.i.2.1.i, align 2
+ %arrayidx4.us.i.2.1.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.2.1.i
+ %B9 = load i16, ptr %arrayidx4.us.i.2.1.i, align 2
%conv.us.i.2.1.i = sext i16 %B9 to i32
- %arrayidx5.us.i.2.1.i = getelementptr inbounds i16, i16* %B, i32 %inc.us.i.2.i
- %B6.dup.i = load i16, i16* %arrayidx5.us.i.2.1.i, align 2
+ %arrayidx5.us.i.2.1.i = getelementptr inbounds i16, ptr %B, i32 %inc.us.i.2.i
+ %B6.dup.i = load i16, ptr %arrayidx5.us.i.2.1.i, align 2
%conv6.us.i.2.1.i = sext i16 %B6.dup.i to i32
%mul7.us.i.2.1.i = mul nsw i32 %conv6.us.i.2.1.i, %conv.us.i.2.1.i
%add9.us.i.2.1.i = add nsw i32 %mul7.us.i.2.1.i, %add9.us.i.2.i
%inc.us.i.2.1.i = or i32 %j.026.us.i.i, 2
%add.us.i.3.1.i = add i32 %inc.us.i.3.i, %mul.us.i118.3.i
- %arrayidx4.us.i.3.1.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.3.1.i
- %B11 = load i16, i16* %arrayidx4.us.i.3.1.i, align 2
+ %arrayidx4.us.i.3.1.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.3.1.i
+ %B11 = load i16, ptr %arrayidx4.us.i.3.1.i, align 2
%conv.us.i.3.1.i = sext i16 %B11 to i32
- %arrayidx5.us.i.3.1.i = getelementptr inbounds i16, i16* %B, i32 %inc.us.i.3.i
- %B6.dup.i.i = load i16, i16* %arrayidx5.us.i.3.1.i, align 2
+ %arrayidx5.us.i.3.1.i = getelementptr inbounds i16, ptr %B, i32 %inc.us.i.3.i
+ %B6.dup.i.i = load i16, ptr %arrayidx5.us.i.3.1.i, align 2
%conv6.us.i.3.1.i = sext i16 %B6.dup.i.i to i32
%mul7.us.i.3.1.i = mul nsw i32 %conv6.us.i.3.1.i, %conv.us.i.3.1.i
%add9.us.i.3.1.i = add nsw i32 %mul7.us.i.3.1.i, %add9.us.i.3.i
%inc.us.i.3.1.i = or i32 %j.026.us.i.i, 2
%add.us.i.2346.i = add i32 %inc.us.i.1344.i, %mul.us.i118.i
- %arrayidx4.us.i.2347.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.2346.i
- %B13 = load i16, i16* %arrayidx4.us.i.2347.i, align 2
+ %arrayidx4.us.i.2347.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.2346.i
+ %B13 = load i16, ptr %arrayidx4.us.i.2347.i, align 2
%conv.us.i.2348.i = sext i16 %B13 to i32
- %arrayidx5.us.i.2349.i = getelementptr inbounds i16, i16* %B, i32 %inc.us.i.1344.i
- %B14 = load i16, i16* %arrayidx5.us.i.2349.i, align 2
+ %arrayidx5.us.i.2349.i = getelementptr inbounds i16, ptr %B, i32 %inc.us.i.1344.i
+ %B14 = load i16, ptr %arrayidx5.us.i.2349.i, align 2
%conv6.us.i.2350.i = sext i16 %B14 to i32
%mul7.us.i.2351.i = mul nsw i32 %conv6.us.i.2350.i, %conv.us.i.2348.i
%add9.us.i.2352.i = add nsw i32 %mul7.us.i.2351.i, %add9.us.i.1343.i
%inc.us.i.2353.i = or i32 %j.026.us.i.i, 3
%add.us.i.1.2.i = add i32 %inc.us.i.1.1.i, %mul.us.i118.1.i
- %arrayidx4.us.i.1.2.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.1.2.i
- %B15 = load i16, i16* %arrayidx4.us.i.1.2.i, align 2
+ %arrayidx4.us.i.1.2.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.1.2.i
+ %B15 = load i16, ptr %arrayidx4.us.i.1.2.i, align 2
%conv.us.i.1.2.i = sext i16 %B15 to i32
- %arrayidx5.us.i.1.2.i = getelementptr inbounds i16, i16* %B, i32 %inc.us.i.1.1.i
- %B14.dup = load i16, i16* %arrayidx5.us.i.1.2.i, align 2
+ %arrayidx5.us.i.1.2.i = getelementptr inbounds i16, ptr %B, i32 %inc.us.i.1.1.i
+ %B14.dup = load i16, ptr %arrayidx5.us.i.1.2.i, align 2
%conv6.us.i.1.2.i = sext i16 %B14.dup to i32
%mul7.us.i.1.2.i = mul nsw i32 %conv6.us.i.1.2.i, %conv.us.i.1.2.i
%add9.us.i.1.2.i = add nsw i32 %mul7.us.i.1.2.i, %add9.us.i.1.1.i
%inc.us.i.1.2.i = or i32 %j.026.us.i.i, 3
%add.us.i.2.2.i = add i32 %inc.us.i.2.1.i, %mul.us.i118.2.i
- %arrayidx4.us.i.2.2.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.2.2.i
- %B17 = load i16, i16* %arrayidx4.us.i.2.2.i, align 2
+ %arrayidx4.us.i.2.2.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.2.2.i
+ %B17 = load i16, ptr %arrayidx4.us.i.2.2.i, align 2
%conv.us.i.2.2.i = sext i16 %B17 to i32
- %arrayidx5.us.i.2.2.i = getelementptr inbounds i16, i16* %B, i32 %inc.us.i.2.1.i
- %B14.dup.i = load i16, i16* %arrayidx5.us.i.2.2.i, align 2
+ %arrayidx5.us.i.2.2.i = getelementptr inbounds i16, ptr %B, i32 %inc.us.i.2.1.i
+ %B14.dup.i = load i16, ptr %arrayidx5.us.i.2.2.i, align 2
%conv6.us.i.2.2.i = sext i16 %B14.dup.i to i32
%mul7.us.i.2.2.i = mul nsw i32 %conv6.us.i.2.2.i, %conv.us.i.2.2.i
%add9.us.i.2.2.i = add nsw i32 %mul7.us.i.2.2.i, %add9.us.i.2.1.i
%inc.us.i.2.2.i = or i32 %j.026.us.i.i, 3
%add.us.i.3.2.i = add i32 %inc.us.i.3.1.i, %mul.us.i118.3.i
- %arrayidx4.us.i.3.2.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.3.2.i
- %B19 = load i16, i16* %arrayidx4.us.i.3.2.i, align 2
+ %arrayidx4.us.i.3.2.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.3.2.i
+ %B19 = load i16, ptr %arrayidx4.us.i.3.2.i, align 2
%conv.us.i.3.2.i = sext i16 %B19 to i32
- %arrayidx5.us.i.3.2.i = getelementptr inbounds i16, i16* %B, i32 %inc.us.i.3.1.i
- %B14.dup.i.i = load i16, i16* %arrayidx5.us.i.3.2.i, align 2
+ %arrayidx5.us.i.3.2.i = getelementptr inbounds i16, ptr %B, i32 %inc.us.i.3.1.i
+ %B14.dup.i.i = load i16, ptr %arrayidx5.us.i.3.2.i, align 2
%conv6.us.i.3.2.i = sext i16 %B14.dup.i.i to i32
%mul7.us.i.3.2.i = mul nsw i32 %conv6.us.i.3.2.i, %conv.us.i.3.2.i
%add9.us.i.3.2.i = add nsw i32 %mul7.us.i.3.2.i, %add9.us.i.3.1.i
%inc.us.i.3.2.i = or i32 %j.026.us.i.i, 3
%add.us.i.3355.i = add i32 %inc.us.i.2353.i, %mul.us.i118.i
- %arrayidx4.us.i.3356.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.3355.i
- %B21 = load i16, i16* %arrayidx4.us.i.3356.i, align 2
+ %arrayidx4.us.i.3356.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.3355.i
+ %B21 = load i16, ptr %arrayidx4.us.i.3356.i, align 2
%conv.us.i.3357.i = sext i16 %B21 to i32
- %arrayidx5.us.i.3358.i = getelementptr inbounds i16, i16* %B, i32 %inc.us.i.2353.i
- %B22 = load i16, i16* %arrayidx5.us.i.3358.i, align 2
+ %arrayidx5.us.i.3358.i = getelementptr inbounds i16, ptr %B, i32 %inc.us.i.2353.i
+ %B22 = load i16, ptr %arrayidx5.us.i.3358.i, align 2
%conv6.us.i.3359.i = sext i16 %B22 to i32
%mul7.us.i.3360.i = mul nsw i32 %conv6.us.i.3359.i, %conv.us.i.3357.i
%add9.us.i.3361.i = add nsw i32 %mul7.us.i.3360.i, %add9.us.i.2352.i
%inc.us.i.3362.i = add i32 %j.026.us.i.i, 4
%add.us.i.1.3.i = add i32 %inc.us.i.1.2.i, %mul.us.i118.1.i
- %arrayidx4.us.i.1.3.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.1.3.i
- %B23 = load i16, i16* %arrayidx4.us.i.1.3.i, align 2
+ %arrayidx4.us.i.1.3.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.1.3.i
+ %B23 = load i16, ptr %arrayidx4.us.i.1.3.i, align 2
%conv.us.i.1.3.i = sext i16 %B23 to i32
- %arrayidx5.us.i.1.3.i = getelementptr inbounds i16, i16* %B, i32 %inc.us.i.1.2.i
- %B22.dup = load i16, i16* %arrayidx5.us.i.1.3.i, align 2
+ %arrayidx5.us.i.1.3.i = getelementptr inbounds i16, ptr %B, i32 %inc.us.i.1.2.i
+ %B22.dup = load i16, ptr %arrayidx5.us.i.1.3.i, align 2
%conv6.us.i.1.3.i = sext i16 %B22.dup to i32
%mul7.us.i.1.3.i = mul nsw i32 %conv6.us.i.1.3.i, %conv.us.i.1.3.i
%add9.us.i.1.3.i = add nsw i32 %mul7.us.i.1.3.i, %add9.us.i.1.2.i
%add.us.i.2.3.i = add i32 %inc.us.i.2.2.i, %mul.us.i118.2.i
- %arrayidx4.us.i.2.3.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.2.3.i
- %B25 = load i16, i16* %arrayidx4.us.i.2.3.i, align 2
+ %arrayidx4.us.i.2.3.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.2.3.i
+ %B25 = load i16, ptr %arrayidx4.us.i.2.3.i, align 2
%conv.us.i.2.3.i = sext i16 %B25 to i32
- %arrayidx5.us.i.2.3.i = getelementptr inbounds i16, i16* %B, i32 %inc.us.i.2.2.i
- %B22.dup.i = load i16, i16* %arrayidx5.us.i.2.3.i, align 2
+ %arrayidx5.us.i.2.3.i = getelementptr inbounds i16, ptr %B, i32 %inc.us.i.2.2.i
+ %B22.dup.i = load i16, ptr %arrayidx5.us.i.2.3.i, align 2
%conv6.us.i.2.3.i = sext i16 %B22.dup.i to i32
%mul7.us.i.2.3.i = mul nsw i32 %conv6.us.i.2.3.i, %conv.us.i.2.3.i
%add9.us.i.2.3.i = add nsw i32 %mul7.us.i.2.3.i, %add9.us.i.2.2.i
%add.us.i.3.3.i = add i32 %inc.us.i.3.2.i, %mul.us.i118.3.i
- %arrayidx4.us.i.3.3.i = getelementptr inbounds i16, i16* %A, i32 %add.us.i.3.3.i
- %B27 = load i16, i16* %arrayidx4.us.i.3.3.i, align 2
+ %arrayidx4.us.i.3.3.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.3.3.i
+ %B27 = load i16, ptr %arrayidx4.us.i.3.3.i, align 2
%conv.us.i.3.3.i = sext i16 %B27 to i32
- %arrayidx5.us.i.3.3.i = getelementptr inbounds i16, i16* %B, i32 %inc.us.i.3.2.i
- %B22.dup.i.i = load i16, i16* %arrayidx5.us.i.3.3.i, align 2
+ %arrayidx5.us.i.3.3.i = getelementptr inbounds i16, ptr %B, i32 %inc.us.i.3.2.i
+ %B22.dup.i.i = load i16, ptr %arrayidx5.us.i.3.3.i, align 2
%conv6.us.i.3.3.i = sext i16 %B22.dup.i.i to i32
%mul7.us.i.3.3.i = mul nsw i32 %conv6.us.i.3.3.i, %conv.us.i.3.3.i
%add9.us.i.3.3.i = add nsw i32 %mul7.us.i.3.3.i, %add9.us.i.3.2.i
@@ -216,13 +216,12 @@ for.body:
br i1 %niter335.ncmp.3.i, label %exit, label %for.body
exit:
- %arrayidx.out.i = getelementptr inbounds i32, i32* %res, i32 0
- store i32 %add9.us.i.3361.i, i32* %arrayidx.out.i, align 4
- %arrayidx.out.1.i = getelementptr inbounds i32, i32* %res, i32 1
- store i32 %add9.us.i.1.3.i, i32* %arrayidx.out.1.i, align 4
- %arrayidx.out.2.i = getelementptr inbounds i32, i32* %res, i32 2
- store i32 %add9.us.i.2.3.i, i32* %arrayidx.out.2.i, align 4
- %arrayidx.out.3.i = getelementptr inbounds i32, i32* %res, i32 3
- store i32 %add9.us.i.3.3.i, i32* %arrayidx.out.3.i, align 4
+ store i32 %add9.us.i.3361.i, ptr %res, align 4
+ %arrayidx.out.1.i = getelementptr inbounds i32, ptr %res, i32 1
+ store i32 %add9.us.i.1.3.i, ptr %arrayidx.out.1.i, align 4
+ %arrayidx.out.2.i = getelementptr inbounds i32, ptr %res, i32 2
+ store i32 %add9.us.i.2.3.i, ptr %arrayidx.out.2.i, align 4
+ %arrayidx.out.3.i = getelementptr inbounds i32, ptr %res, i32 3
+ store i32 %add9.us.i.3.3.i, ptr %arrayidx.out.3.i, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/SoftFloatVectorExtract.ll b/llvm/test/CodeGen/ARM/SoftFloatVectorExtract.ll
index b27c0ddbb4e91..5681d306d6bdc 100644
--- a/llvm/test/CodeGen/ARM/SoftFloatVectorExtract.ll
+++ b/llvm/test/CodeGen/ARM/SoftFloatVectorExtract.ll
@@ -15,7 +15,7 @@ define double @vector_ex() nounwind #0 {
; CHECK-NEXT: vmov.32 r0, d17[0]
; CHECK-NEXT: vmov.32 r1, d17[1]
; CHECK-NEXT: bx lr
- %v = load <2 x double>, <2 x double>* @m
+ %v = load <2 x double>, ptr @m
%x = extractelement <2 x double> %v, i32 1
ret double %x
}
diff --git a/llvm/test/CodeGen/ARM/Windows/aapcs.ll b/llvm/test/CodeGen/ARM/Windows/aapcs.ll
index 3f9a09f8e7f50..ca3a8b1ef4a2e 100644
--- a/llvm/test/CodeGen/ARM/Windows/aapcs.ll
+++ b/llvm/test/CodeGen/ARM/Windows/aapcs.ll
@@ -3,11 +3,11 @@
; AAPCS mandates an 8-byte stack alignment. The alloca is implicitly aligned,
; and no bic is required.
-declare void @callee(i8 *%i)
+declare void @callee(ptr %i)
define void @caller() {
%i = alloca i8, align 8
- call void @callee(i8* %i)
+ call void @callee(ptr %i)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/Windows/alloca-no-stack-arg-probe.ll b/llvm/test/CodeGen/ARM/Windows/alloca-no-stack-arg-probe.ll
index a1dce7fd4a3cd..11709388053d3 100644
--- a/llvm/test/CodeGen/ARM/Windows/alloca-no-stack-arg-probe.ll
+++ b/llvm/test/CodeGen/ARM/Windows/alloca-no-stack-arg-probe.ll
@@ -4,11 +4,11 @@ declare arm_aapcs_vfpcc i32 @num_entries()
define arm_aapcs_vfpcc void @test___builtin_alloca() "no-stack-arg-probe" {
entry:
- %array = alloca i8*, align 4
+ %array = alloca ptr, align 4
%call = call arm_aapcs_vfpcc i32 @num_entries()
%mul = mul i32 4, %call
%0 = alloca i8, i32 %mul
- store i8* %0, i8** %array, align 4
+ store ptr %0, ptr %array, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/Windows/alloca.ll b/llvm/test/CodeGen/ARM/Windows/alloca.ll
index ec3b130b3d8bf..e014d287db6e9 100644
--- a/llvm/test/CodeGen/ARM/Windows/alloca.ll
+++ b/llvm/test/CodeGen/ARM/Windows/alloca.ll
@@ -6,11 +6,11 @@ declare arm_aapcs_vfpcc i32 @num_entries()
define arm_aapcs_vfpcc void @test___builtin_alloca() {
entry:
- %array = alloca i8*, align 4
+ %array = alloca ptr, align 4
%call = call arm_aapcs_vfpcc i32 @num_entries()
%mul = mul i32 4, %call
%0 = alloca i8, i32 %mul
- store i8* %0, i8** %array, align 4
+ store ptr %0, ptr %array, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/Windows/builtin_longjmp.ll b/llvm/test/CodeGen/ARM/Windows/builtin_longjmp.ll
index 52b6f301bb77f..4d25ee6dfcbf9 100644
--- a/llvm/test/CodeGen/ARM/Windows/builtin_longjmp.ll
+++ b/llvm/test/CodeGen/ARM/Windows/builtin_longjmp.ll
@@ -1,10 +1,10 @@
; RUN: llc -mtriple thumbv7--windows-itanium -filetype asm -o - %s | FileCheck %s
-declare void @llvm.eh.sjlj.longjmp(i8*)
+declare void @llvm.eh.sjlj.longjmp(ptr)
-define arm_aapcs_vfpcc void @test___builtin_longjump(i8* %b) {
+define arm_aapcs_vfpcc void @test___builtin_longjump(ptr %b) {
entry:
- tail call void @llvm.eh.sjlj.longjmp(i8* %b)
+ tail call void @llvm.eh.sjlj.longjmp(ptr %b)
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll b/llvm/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll
index 0934e2805ab7b..5d202c5515e50 100644
--- a/llvm/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll
+++ b/llvm/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll
@@ -9,11 +9,11 @@ define arm_aapcs_vfpcc i8 @isel(i32 %i) {
entry:
%i.addr = alloca i32, align 4
%buffer = alloca [4096 x i8], align 1
- store i32 %i, i32* %i.addr, align 4
- %0 = load i32, i32* %i.addr, align 4
+ store i32 %i, ptr %i.addr, align 4
+ %0 = load i32, ptr %i.addr, align 4
%rem = urem i32 %0, 4096
- %arrayidx = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 %rem
- %1 = load volatile i8, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds [4096 x i8], ptr %buffer, i32 0, i32 %rem
+ %1 = load volatile i8, ptr %arrayidx, align 1
ret i8 %1
}
diff --git a/llvm/test/CodeGen/ARM/Windows/dbzchk.ll b/llvm/test/CodeGen/ARM/Windows/dbzchk.ll
index 74267e826de90..21abc855957e4 100644
--- a/llvm/test/CodeGen/ARM/Windows/dbzchk.ll
+++ b/llvm/test/CodeGen/ARM/Windows/dbzchk.ll
@@ -11,24 +11,24 @@ entry:
%retval = alloca i32, align 4
%n.addr = alloca i32, align 4
%d.addr = alloca i32, align 4
- store i32 %n, i32* %n.addr, align 4
- store i32 %d, i32* %d.addr, align 4
- %0 = load i32, i32* %n.addr, align 4
- %1 = load i32, i32* %d.addr, align 4
+ store i32 %n, ptr %n.addr, align 4
+ store i32 %d, ptr %d.addr, align 4
+ %0 = load i32, ptr %n.addr, align 4
+ %1 = load i32, ptr %d.addr, align 4
%div = sdiv i32 %0, %1
%tobool = icmp ne i32 %div, 0
br i1 %tobool, label %if.then, label %if.end
if.then:
- store i32 1, i32* %retval, align 4
+ store i32 1, ptr %retval, align 4
br label %return
if.end:
- store i32 0, i32* %retval, align 4
+ store i32 0, ptr %retval, align 4
br label %return
return:
- %2 = load i32, i32* %retval, align 4
+ %2 = load i32, ptr %retval, align 4
ret i32 %2
}
@@ -58,7 +58,7 @@ entry:
if.end:
%rem = urem i32 %l, %m
- store i32 %rem, i32* @r, align 4
+ store i32 %rem, ptr @r, align 4
br label %return
return:
@@ -95,13 +95,13 @@ entry:
br i1 %tobool, label %entry.if.end_crit_edge, label %if.then
entry.if.end_crit_edge:
- %.pre = load i32, i32* @c, align 4
+ %.pre = load i32, ptr @c, align 4
br label %if.end
if.then:
%call = tail call arm_aapcs_vfpcc i32 @i()
%rem = urem i32 %call, %u
- store i32 %rem, i32* @c, align 4
+ store i32 %rem, ptr @c, align 4
br label %if.end
if.end:
@@ -153,24 +153,24 @@ define arm_aapcs_vfpcc i32 @j(i32 %i) {
entry:
%retval = alloca i32, align 4
%i.addr = alloca i32, align 4
- store i32 %i, i32* %i.addr, align 4
+ store i32 %i, ptr %i.addr, align 4
%call = call arm_aapcs_vfpcc i32 @l()
%cmp = icmp eq i32 %call, -1
br i1 %cmp, label %if.then, label %if.end
if.then:
- store i32 0, i32* %retval, align 4
+ store i32 0, ptr %retval, align 4
br label %return
if.end:
%call1 = call arm_aapcs_vfpcc i32 @k()
- %0 = load i32, i32* %i.addr, align 4
+ %0 = load i32, ptr %i.addr, align 4
%rem = srem i32 %call1, %0
- store i32 %rem, i32* %retval, align 4
+ store i32 %rem, ptr %retval, align 4
br label %return
return:
- %1 = load i32, i32* %retval, align 4
+ %1 = load i32, ptr %retval, align 4
ret i32 %1
}
diff --git a/llvm/test/CodeGen/ARM/Windows/dllexport.ll b/llvm/test/CodeGen/ARM/Windows/dllexport.ll
index 4f2e21baeb905..0d904119e738d 100644
--- a/llvm/test/CodeGen/ARM/Windows/dllexport.ll
+++ b/llvm/test/CodeGen/ARM/Windows/dllexport.ll
@@ -34,10 +34,10 @@ define weak_odr dllexport void @l() {
@p = weak_odr dllexport global i32 0, align 4
@q = weak_odr dllexport unnamed_addr constant i32 0
- at r = dllexport alias void (), void () * @f
- at s = dllexport alias void (), void () * @g
- at t = dllexport alias void (), void () * @f
- at u = weak_odr dllexport alias void (), void () * @g
+ at r = dllexport alias void (), ptr @f
+ at s = dllexport alias void (), ptr @g
+ at t = dllexport alias void (), ptr @f
+ at u = weak_odr dllexport alias void (), ptr @g
; CHECK: .section .drectve
; CHECK-GNU-NOT: -export:f
diff --git a/llvm/test/CodeGen/ARM/Windows/dllimport.ll b/llvm/test/CodeGen/ARM/Windows/dllimport.ll
index e8ee982162d51..7c2d413f5ff22 100644
--- a/llvm/test/CodeGen/ARM/Windows/dllimport.ll
+++ b/llvm/test/CodeGen/ARM/Windows/dllimport.ll
@@ -8,7 +8,7 @@ declare dllimport arm_aapcs_vfpcc i32 @external()
declare arm_aapcs_vfpcc i32 @internal()
define arm_aapcs_vfpcc i32 @get_var() {
- %1 = load i32, i32* @var, align 4
+ %1 = load i32, ptr @var, align 4
ret i32 %1
}
@@ -20,7 +20,7 @@ define arm_aapcs_vfpcc i32 @get_var() {
; CHECK: bx lr
define arm_aapcs_vfpcc i32 @get_ext() {
- %1 = load i32, i32* @ext, align 4
+ %1 = load i32, ptr @ext, align 4
ret i32 %1
}
@@ -30,8 +30,8 @@ define arm_aapcs_vfpcc i32 @get_ext() {
; CHECK: ldr r0, [r0]
; CHECK: bx lr
-define arm_aapcs_vfpcc i32* @get_var_pointer() {
- ret i32* @var
+define arm_aapcs_vfpcc ptr @get_var_pointer() {
+ ret ptr @var
}
; CHECK-LABEL: get_var_pointer
diff --git a/llvm/test/CodeGen/ARM/Windows/frame-register.ll b/llvm/test/CodeGen/ARM/Windows/frame-register.ll
index 6605ffc60f4aa..7ad51f2f84512 100644
--- a/llvm/test/CodeGen/ARM/Windows/frame-register.ll
+++ b/llvm/test/CodeGen/ARM/Windows/frame-register.ll
@@ -7,13 +7,13 @@ define i32 @calleer(i32 %i) {
entry:
%i.addr = alloca i32, align 4
%j = alloca i32, align 4
- store i32 %i, i32* %i.addr, align 4
- %0 = load i32, i32* %i.addr, align 4
+ store i32 %i, ptr %i.addr, align 4
+ %0 = load i32, ptr %i.addr, align 4
%add = add nsw i32 %0, 1
- store i32 %add, i32* %j, align 4
- %1 = load i32, i32* %j, align 4
+ store i32 %add, ptr %j, align 4
+ %1 = load i32, ptr %j, align 4
call void @callee(i32 %1)
- %2 = load i32, i32* %j, align 4
+ %2 = load i32, ptr %j, align 4
%add1 = add nsw i32 %2, 1
ret i32 %add1
}
diff --git a/llvm/test/CodeGen/ARM/Windows/global-minsize.ll b/llvm/test/CodeGen/ARM/Windows/global-minsize.ll
index c0be36caa6c49..aee5f08000b94 100644
--- a/llvm/test/CodeGen/ARM/Windows/global-minsize.ll
+++ b/llvm/test/CodeGen/ARM/Windows/global-minsize.ll
@@ -3,9 +3,9 @@
@i = internal global i32 0, align 4
; Function Attrs: minsize
-define arm_aapcs_vfpcc i32* @function() #0 {
+define arm_aapcs_vfpcc ptr @function() #0 {
entry:
- ret i32* @i
+ ret ptr @i
}
attributes #0 = { minsize }
diff --git a/llvm/test/CodeGen/ARM/Windows/if-cvt-bundle.ll b/llvm/test/CodeGen/ARM/Windows/if-cvt-bundle.ll
index 5521ed72ee283..66598cc732336 100644
--- a/llvm/test/CodeGen/ARM/Windows/if-cvt-bundle.ll
+++ b/llvm/test/CodeGen/ARM/Windows/if-cvt-bundle.ll
@@ -3,13 +3,13 @@
declare void @llvm.trap()
declare arm_aapcs_vfpcc zeroext i1 @g()
-define arm_aapcs_vfpcc i8* @f() {
+define arm_aapcs_vfpcc ptr @f() {
entry:
%call = tail call arm_aapcs_vfpcc zeroext i1 @g()
br i1 %call, label %if.then, label %if.end
if.then:
- ret i8* bitcast (i1 ()* @g to i8*)
+ ret ptr @g
if.end:
tail call void @llvm.trap()
diff --git a/llvm/test/CodeGen/ARM/Windows/memset.ll b/llvm/test/CodeGen/ARM/Windows/memset.ll
index d4d918a29c14b..921166333ae84 100644
--- a/llvm/test/CodeGen/ARM/Windows/memset.ll
+++ b/llvm/test/CodeGen/ARM/Windows/memset.ll
@@ -2,11 +2,11 @@
@source = common global [512 x i8] zeroinitializer, align 4
-declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) nounwind
+declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) nounwind
define void @function() {
entry:
- call void @llvm.memset.p0i8.i32(i8* bitcast ([512 x i8]* @source to i8*), i8 0, i32 512, i1 false)
+ call void @llvm.memset.p0.i32(ptr @source, i8 0, i32 512, i1 false)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/Windows/mingw-refptr.ll b/llvm/test/CodeGen/ARM/Windows/mingw-refptr.ll
index adc2ed6275b63..63f405f756231 100644
--- a/llvm/test/CodeGen/ARM/Windows/mingw-refptr.ll
+++ b/llvm/test/CodeGen/ARM/Windows/mingw-refptr.ll
@@ -14,7 +14,7 @@ define dso_local i32 @getVar() {
; CHECK: ldr r0, [r0]
; CHECK: bx lr
entry:
- %0 = load i32, i32* @var, align 4
+ %0 = load i32, ptr @var, align 4
ret i32 %0
}
@@ -25,7 +25,7 @@ define dso_local i32 @getDsoLocalVar() {
; CHECK: ldr r0, [r0]
; CHECK: bx lr
entry:
- %0 = load i32, i32* @dsolocalvar, align 4
+ %0 = load i32, ptr @dsolocalvar, align 4
ret i32 %0
}
@@ -36,7 +36,7 @@ define dso_local i32 @getLocalVar() {
; CHECK: ldr r0, [r0]
; CHECK: bx lr
entry:
- %0 = load i32, i32* @localvar, align 4
+ %0 = load i32, ptr @localvar, align 4
ret i32 %0
}
@@ -47,7 +47,7 @@ define dso_local i32 @getLocalCommon() {
; CHECK: ldr r0, [r0]
; CHECK: bx lr
entry:
- %0 = load i32, i32* @localcommon, align 4
+ %0 = load i32, ptr @localcommon, align 4
ret i32 %0
}
@@ -59,7 +59,7 @@ define dso_local i32 @getExtVar() {
; CHECK: ldr r0, [r0]
; CHECK: bx lr
entry:
- %0 = load i32, i32* @extvar, align 4
+ %0 = load i32, ptr @extvar, align 4
ret i32 %0
}
diff --git a/llvm/test/CodeGen/ARM/Windows/mov32t-bundling.ll b/llvm/test/CodeGen/ARM/Windows/mov32t-bundling.ll
index 5f838378fa87e..a9a3f65b0a6ef 100644
--- a/llvm/test/CodeGen/ARM/Windows/mov32t-bundling.ll
+++ b/llvm/test/CodeGen/ARM/Windows/mov32t-bundling.ll
@@ -7,7 +7,7 @@ declare arm_aapcs_vfpcc void @force_emission()
define arm_aapcs_vfpcc void @bundle() {
entry:
- br i1 icmp uge (i32 sub (i32 ptrtoint (i8* @_end to i32), i32 ptrtoint (i8* @_begin to i32)), i32 4), label %if.then, label %if.end
+ br i1 icmp uge (i32 sub (i32 ptrtoint (ptr @_end to i32), i32 ptrtoint (ptr @_begin to i32)), i32 4), label %if.then, label %if.end
if.then:
tail call arm_aapcs_vfpcc void @force_emission()
diff --git a/llvm/test/CodeGen/ARM/Windows/movw-movt-relocations.ll b/llvm/test/CodeGen/ARM/Windows/movw-movt-relocations.ll
index c21aee087cf4a..d75e7df3ee1e1 100644
--- a/llvm/test/CodeGen/ARM/Windows/movw-movt-relocations.ll
+++ b/llvm/test/CodeGen/ARM/Windows/movw-movt-relocations.ll
@@ -10,8 +10,8 @@
; Function Attrs: nounwind optsize readonly
define i32 @relocation(i32 %j, i32 %k) {
entry:
- %0 = load i32, i32* @i, align 4
- %1 = load i32, i32* @j, align 4
+ %0 = load i32, ptr @i, align 4
+ %1 = load i32, ptr @j, align 4
%add = add nsw i32 %1, %0
ret i32 %add
}
diff --git a/llvm/test/CodeGen/ARM/Windows/no-aeabi.ll b/llvm/test/CodeGen/ARM/Windows/no-aeabi.ll
index a5f7fc8daf6e3..22b57876ab684 100644
--- a/llvm/test/CodeGen/ARM/Windows/no-aeabi.ll
+++ b/llvm/test/CodeGen/ARM/Windows/no-aeabi.ll
@@ -1,14 +1,14 @@
; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -verify-machineinstrs -o - %s | FileCheck %s
-declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
+declare void @llvm.memmove.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
@source = common global [512 x i8] zeroinitializer, align 4
@target = common global [512 x i8] zeroinitializer, align 4
define void @move() nounwind {
entry:
- call void @llvm.memmove.p0i8.p0i8.i32(i8* bitcast ([512 x i8]* @target to i8*), i8* bitcast ([512 x i8]* @source to i8*), i32 512, i1 false)
+ call void @llvm.memmove.p0.p0.i32(ptr @target, ptr @source, i32 512, i1 false)
unreachable
}
@@ -16,7 +16,7 @@ entry:
define void @copy() nounwind {
entry:
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* bitcast ([512 x i8]* @target to i8*), i8* bitcast ([512 x i8]* @source to i8*), i32 512, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr @target, ptr @source, i32 512, i1 false)
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/Windows/no-frame-register.ll b/llvm/test/CodeGen/ARM/Windows/no-frame-register.ll
index 80187af7ef228..bbe3d97195758 100644
--- a/llvm/test/CodeGen/ARM/Windows/no-frame-register.ll
+++ b/llvm/test/CodeGen/ARM/Windows/no-frame-register.ll
@@ -6,13 +6,13 @@ define i32 @calleer(i32 %i) {
entry:
%i.addr = alloca i32, align 4
%j = alloca i32, align 4
- store i32 %i, i32* %i.addr, align 4
- %0 = load i32, i32* %i.addr, align 4
+ store i32 %i, ptr %i.addr, align 4
+ %0 = load i32, ptr %i.addr, align 4
%add = add nsw i32 %0, 1
- store i32 %add, i32* %j, align 4
- %1 = load i32, i32* %j, align 4
+ store i32 %add, ptr %j, align 4
+ %1 = load i32, ptr %j, align 4
call void @callee(i32 %1)
- %2 = load i32, i32* %j, align 4
+ %2 = load i32, ptr %j, align 4
%add1 = add nsw i32 %2, 1
ret i32 %add1
}
diff --git a/llvm/test/CodeGen/ARM/Windows/pic.ll b/llvm/test/CodeGen/ARM/Windows/pic.ll
index 958fc26e4f57b..10d1c3e1314f5 100644
--- a/llvm/test/CodeGen/ARM/Windows/pic.ll
+++ b/llvm/test/CodeGen/ARM/Windows/pic.ll
@@ -8,7 +8,7 @@
define arm_aapcs_vfpcc i8 @return_external() {
entry:
- %0 = load i8, i8* @external, align 1
+ %0 = load i8, ptr @external, align 1
ret i8 %0
}
diff --git a/llvm/test/CodeGen/ARM/Windows/read-only-data.ll b/llvm/test/CodeGen/ARM/Windows/read-only-data.ll
index c387d1d5137c4..b2efe9390dea7 100644
--- a/llvm/test/CodeGen/ARM/Windows/read-only-data.ll
+++ b/llvm/test/CodeGen/ARM/Windows/read-only-data.ll
@@ -2,11 +2,11 @@
@.str = private unnamed_addr constant [7 x i8] c"string\00", align 1
-declare arm_aapcs_vfpcc void @callee(i8*)
+declare arm_aapcs_vfpcc void @callee(ptr)
define arm_aapcs_vfpcc void @function() {
entry:
- call arm_aapcs_vfpcc void @callee(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0))
+ call arm_aapcs_vfpcc void @callee(ptr @.str)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/Windows/stack-probe-non-default.ll b/llvm/test/CodeGen/ARM/Windows/stack-probe-non-default.ll
index d66e93ad34ee9..51fcee0eba693 100644
--- a/llvm/test/CodeGen/ARM/Windows/stack-probe-non-default.ll
+++ b/llvm/test/CodeGen/ARM/Windows/stack-probe-non-default.ll
@@ -4,16 +4,15 @@
; RUN: llc -mtriple thumbv7-windows -mcpu cortex-a9 -code-model large -o - %s \
; RUN: | FileCheck %s -check-prefix CHECK-LARGE-CODE-MODEL
-declare dllimport arm_aapcs_vfpcc void @initialise(i8*)
+declare dllimport arm_aapcs_vfpcc void @initialise(ptr)
define dllexport arm_aapcs_vfpcc signext i8 @function(i32 %offset) #0 {
entry:
%buffer = alloca [4096 x i8], align 1
- %0 = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 0
- call arm_aapcs_vfpcc void @initialise(i8* %0)
- %arrayidx = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 %offset
- %1 = load i8, i8* %arrayidx, align 1
- ret i8 %1
+ call arm_aapcs_vfpcc void @initialise(ptr %buffer)
+ %arrayidx = getelementptr inbounds [4096 x i8], ptr %buffer, i32 0, i32 %offset
+ %0 = load i8, ptr %arrayidx, align 1
+ ret i8 %0
}
attributes #0 = { "stack-probe-size"="8096" }
diff --git a/llvm/test/CodeGen/ARM/Windows/stack-protector-msvc.ll b/llvm/test/CodeGen/ARM/Windows/stack-protector-msvc.ll
index 3a38aa01b2a5a..882fd9d3a1329 100644
--- a/llvm/test/CodeGen/ARM/Windows/stack-protector-msvc.ll
+++ b/llvm/test/CodeGen/ARM/Windows/stack-protector-msvc.ll
@@ -4,12 +4,11 @@
define void @_Z1fv() sspreq {
entry:
%x = alloca i32, align 4
- %0 = bitcast i32* %x to i8*
- call void @_Z7CapturePi(i32* nonnull %x)
+ call void @_Z7CapturePi(ptr nonnull %x)
ret void
}
-declare void @_Z7CapturePi(i32*)
+declare void @_Z7CapturePi(ptr)
; MSVC: movw r0, :lower16:__security_cookie
; MSVC: movt r0, :upper16:__security_cookie
diff --git a/llvm/test/CodeGen/ARM/Windows/stack-protector-musttail.ll b/llvm/test/CodeGen/ARM/Windows/stack-protector-musttail.ll
index 74829f9d78048..c35738c87c6c8 100644
--- a/llvm/test/CodeGen/ARM/Windows/stack-protector-musttail.ll
+++ b/llvm/test/CodeGen/ARM/Windows/stack-protector-musttail.ll
@@ -1,6 +1,6 @@
; RUN: llc -mtriple=thumbv7-windows-msvc -fast-isel %s -o - -start-before=stack-protector -stop-after=stack-protector | FileCheck %s
- at var = global [2 x i64]* null
+ at var = global ptr null
declare void @callee()
@@ -13,7 +13,7 @@ define void @caller1() sspreq {
; CHECK: musttail call void @callee()
; CHECK-NEXT: ret void
%var = alloca [2 x i64]
- store [2 x i64]* %var, [2 x i64]** @var
+ store ptr %var, ptr @var
musttail call void @callee()
ret void
}
@@ -27,31 +27,29 @@ define void @justret() sspreq {
; CHECK: ret void
%var = alloca [2 x i64]
- store [2 x i64]* %var, [2 x i64]** @var
+ store ptr %var, ptr @var
br label %retblock
retblock:
ret void
}
-declare i64* @callee2()
+declare ptr @callee2()
-define i8* @caller2() sspreq {
-; CHECK-LABEL: define i8* @caller2()
+define ptr @caller2() sspreq {
+; CHECK-LABEL: define ptr @caller2()
; Prologue:
; CHECK: @llvm.stackguard
; CHECK: call void @__security_check_cookie
-; CHECK: [[TMP:%.*]] = musttail call i64* @callee2()
-; CHECK-NEXT: [[RES:%.*]] = bitcast i64* [[TMP]] to i8*
-; CHECK-NEXT: ret i8* [[RES]]
+; CHECK: [[TMP:%.*]] = musttail call ptr @callee2()
+; CHECK-NEXT: ret ptr [[TMP]]
%var = alloca [2 x i64]
- store [2 x i64]* %var, [2 x i64]** @var
- %tmp = musttail call i64* @callee2()
- %res = bitcast i64* %tmp to i8*
- ret i8* %res
+ store ptr %var, ptr @var
+ %tmp = musttail call ptr @callee2()
+ ret ptr %tmp
}
define void @caller3() sspreq {
@@ -63,25 +61,23 @@ define void @caller3() sspreq {
; CHECK: tail call void @callee()
; CHECK-NEXT: ret void
%var = alloca [2 x i64]
- store [2 x i64]* %var, [2 x i64]** @var
+ store ptr %var, ptr @var
tail call void @callee()
ret void
}
-define i8* @caller4() sspreq {
-; CHECK-LABEL: define i8* @caller4()
+define ptr @caller4() sspreq {
+; CHECK-LABEL: define ptr @caller4()
; Prologue:
; CHECK: @llvm.stackguard
; CHECK: call void @__security_check_cookie
-; CHECK: [[TMP:%.*]] = tail call i64* @callee2()
-; CHECK-NEXT: [[RES:%.*]] = bitcast i64* [[TMP]] to i8*
-; CHECK-NEXT: ret i8* [[RES]]
+; CHECK: [[TMP:%.*]] = tail call ptr @callee2()
+; CHECK-NEXT: ret ptr [[TMP]]
%var = alloca [2 x i64]
- store [2 x i64]* %var, [2 x i64]** @var
- %tmp = tail call i64* @callee2()
- %res = bitcast i64* %tmp to i8*
- ret i8* %res
+ store ptr %var, ptr @var
+ %tmp = tail call ptr @callee2()
+ ret ptr %tmp
}
diff --git a/llvm/test/CodeGen/ARM/Windows/structors.ll b/llvm/test/CodeGen/ARM/Windows/structors.ll
index eff1c7f4b3845..cd138819b96a1 100644
--- a/llvm/test/CodeGen/ARM/Windows/structors.ll
+++ b/llvm/test/CodeGen/ARM/Windows/structors.ll
@@ -4,7 +4,7 @@
; RUN: llc -mtriple thumbv7-windows-gnu -o - %s \
; RUN: | FileCheck %s -check-prefix CHECK-GNU
- at llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @function, i8* null }]
+ at llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @function, ptr null }]
define arm_aapcs_vfpcc void @function() {
entry:
diff --git a/llvm/test/CodeGen/ARM/Windows/tls.ll b/llvm/test/CodeGen/ARM/Windows/tls.ll
index 4cd7f54deff34..6e2337286bd70 100644
--- a/llvm/test/CodeGen/ARM/Windows/tls.ll
+++ b/llvm/test/CodeGen/ARM/Windows/tls.ll
@@ -9,7 +9,7 @@
@o = thread_local global i8 0
define i32 @f() {
- %1 = load i32, i32* @i
+ %1 = load i32, ptr @i
ret i32 %1
}
@@ -29,7 +29,7 @@ define i32 @f() {
; CHECK-NEXT: .long i(SECREL32)
define i32 @e() {
- %1 = load i32, i32* @j
+ %1 = load i32, ptr @j
ret i32 %1
}
@@ -49,7 +49,7 @@ define i32 @e() {
; CHECK-NEXT: .long j(SECREL32)
define i32 @d() {
- %1 = load i32, i32* @k
+ %1 = load i32, ptr @k
ret i32 %1
}
@@ -69,7 +69,7 @@ define i32 @d() {
; CHECK-NEXT: .long k(SECREL32)
define i32 @c() {
- %1 = load i32, i32* @l
+ %1 = load i32, ptr @l
ret i32 %1
}
@@ -89,7 +89,7 @@ define i32 @c() {
; CHECK-NEXT: .long l(SECREL32)
define i32 @b() {
- %1 = load i32, i32* @m
+ %1 = load i32, ptr @m
ret i32 %1
}
@@ -109,7 +109,7 @@ define i32 @b() {
; CHECK: .long m(SECREL32)
define i16 @a() {
- %1 = load i16, i16* @n
+ %1 = load i16, ptr @n
ret i16 %1
}
@@ -129,7 +129,7 @@ define i16 @a() {
; CHECK: .long n(SECREL32)
define i8 @Z() {
- %1 = load i8, i8* @o
+ %1 = load i8, ptr @o
ret i8 %1
}
diff --git a/llvm/test/CodeGen/ARM/Windows/vla-cpsr.ll b/llvm/test/CodeGen/ARM/Windows/vla-cpsr.ll
index 88af4475bfb47..5d51775851ecd 100644
--- a/llvm/test/CodeGen/ARM/Windows/vla-cpsr.ll
+++ b/llvm/test/CodeGen/ARM/Windows/vla-cpsr.ll
@@ -1,11 +1,11 @@
; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o /dev/null %s -print-after=finalize-isel 2>&1 | FileCheck %s
-declare arm_aapcs_vfpcc void @g(i8*) local_unnamed_addr
+declare arm_aapcs_vfpcc void @g(ptr) local_unnamed_addr
define arm_aapcs_vfpcc void @f(i32 %i) local_unnamed_addr {
entry:
%vla = alloca i8, i32 %i, align 1
- call arm_aapcs_vfpcc void @g(i8* nonnull %vla)
+ call arm_aapcs_vfpcc void @g(ptr nonnull %vla)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/Windows/vla.ll b/llvm/test/CodeGen/ARM/Windows/vla.ll
index f095197f3d644..459db0c290b5a 100644
--- a/llvm/test/CodeGen/ARM/Windows/vla.ll
+++ b/llvm/test/CodeGen/ARM/Windows/vla.ll
@@ -8,8 +8,8 @@
define arm_aapcs_vfpcc i8 @function(i32 %sz, i32 %idx) {
entry:
%vla = alloca i8, i32 %sz, align 1
- %arrayidx = getelementptr inbounds i8, i8* %vla, i32 %idx
- %0 = load volatile i8, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds i8, ptr %vla, i32 %idx
+ %0 = load volatile i8, ptr %arrayidx, align 1
ret i8 %0
}
diff --git a/llvm/test/CodeGen/ARM/a15-SD-dep.ll b/llvm/test/CodeGen/ARM/a15-SD-dep.ll
index d0edccbf433e8..f9c8a5b0457e5 100644
--- a/llvm/test/CodeGen/ARM/a15-SD-dep.ll
+++ b/llvm/test/CodeGen/ARM/a15-SD-dep.ll
@@ -55,7 +55,7 @@ define arm_aapcs_vfpcc <4 x float> @t5(<4 x float> %q, float %f) {
; Test that DPair can be successfully passed as QPR.
; CHECK-LABEL: test_DPair1:
-define void @test_DPair1(i32 %vsout, i8* nocapture %out, float %x, float %y) {
+define void @test_DPair1(i32 %vsout, ptr nocapture %out, float %x, float %y) {
entry:
%0 = insertelement <4 x float> undef, float %x, i32 1
%1 = insertelement <4 x float> %0, float %y, i32 0
@@ -77,7 +77,7 @@ sw.bb6: ; preds = %sw.bb, %entry
%sum.0 = phi <4 x float> [ %1, %entry ], [ %2, %sw.bb ]
%3 = extractelement <4 x float> %sum.0, i32 0
%conv = fptoui float %3 to i8
- store i8 %conv, i8* %out, align 1
+ store i8 %conv, ptr %out, align 1
ret void
sw.epilog: ; preds = %entry
@@ -85,7 +85,7 @@ sw.epilog: ; preds = %entry
}
; CHECK-LABEL: test_DPair2:
-define void @test_DPair2(i32 %vsout, i8* nocapture %out, float %x) {
+define void @test_DPair2(i32 %vsout, ptr nocapture %out, float %x) {
entry:
%0 = insertelement <4 x float> undef, float %x, i32 0
; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d{{[0-9]*}}[0]
@@ -103,7 +103,7 @@ sw.bb1: ; preds = %entry, %sw.bb
%sum.0 = phi <4 x float> [ %0, %entry ], [ %1, %sw.bb ]
%2 = extractelement <4 x float> %sum.0, i32 0
%conv = fptoui float %2 to i8
- store i8 %conv, i8* %out, align 1
+ store i8 %conv, ptr %out, align 1
br label %sw.epilog
sw.epilog: ; preds = %entry, %sw.bb1
diff --git a/llvm/test/CodeGen/ARM/a15-partial-update.ll b/llvm/test/CodeGen/ARM/a15-partial-update.ll
index a3971d6a034bf..7a531913ebcfe 100644
--- a/llvm/test/CodeGen/ARM/a15-partial-update.ll
+++ b/llvm/test/CodeGen/ARM/a15-partial-update.ll
@@ -8,14 +8,14 @@
; vld1.32 instruction. The test checks that a vmov.f64 was not
; generated.
-define <2 x float> @t1(float* %A, <2 x float> %B) {
+define <2 x float> @t1(ptr %A, <2 x float> %B) {
; CHECK-LABEL: t1:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov d16, r2, r3
; CHECK-NEXT: vld1.32 {d16[1]}, [r0:32]
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp2 = load float, float* %A, align 4
+ %tmp2 = load float, ptr %A, align 4
%tmp3 = insertelement <2 x float> %B, float %tmp2, i32 1
ret <2 x float> %tmp3
}
@@ -24,7 +24,7 @@ define <2 x float> @t1(float* %A, <2 x float> %B) {
; We check that a dependency breaking vmov* instruction was
; generated.
-define void @t2(<4 x i8> *%in, <4 x i8> *%out, i32 %n) {
+define void @t2(ptr %in, ptr %out, i32 %n) {
; CHECK-LABEL: t2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: add r0, r0, #4
@@ -46,10 +46,10 @@ entry:
loop:
%oldcount = phi i32 [0, %entry], [%newcount, %loop]
%newcount = add i32 %oldcount, 1
- %p1 = getelementptr <4 x i8>, <4 x i8> *%in, i32 %newcount
- %p2 = getelementptr <4 x i8>, <4 x i8> *%out, i32 %newcount
- %tmp1 = load <4 x i8> , <4 x i8> *%p1, align 4
- store <4 x i8> %tmp1, <4 x i8> *%p2
+ %p1 = getelementptr <4 x i8>, ptr %in, i32 %newcount
+ %p2 = getelementptr <4 x i8>, ptr %out, i32 %newcount
+ %tmp1 = load <4 x i8> , ptr %p1, align 4
+ store <4 x i8> %tmp1, ptr %p2
%cmp = icmp eq i32 %newcount, %n
br i1 %cmp, label %loop, label %ret
ret:
@@ -61,7 +61,7 @@ ret:
; TODO: This (and above) could use a splat load to remove the false
; dependence with no extra instruction.
-define void @t2_minsize(<4 x i8> *%in, <4 x i8> *%out, i32 %n) minsize {
+define void @t2_minsize(ptr %in, ptr %out, i32 %n) minsize {
; CHECK-LABEL: t2_minsize:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: add r0, r0, #4
@@ -82,10 +82,10 @@ entry:
loop:
%oldcount = phi i32 [0, %entry], [%newcount, %loop]
%newcount = add i32 %oldcount, 1
- %p1 = getelementptr <4 x i8>, <4 x i8> *%in, i32 %newcount
- %p2 = getelementptr <4 x i8>, <4 x i8> *%out, i32 %newcount
- %tmp1 = load <4 x i8> , <4 x i8> *%p1, align 4
- store <4 x i8> %tmp1, <4 x i8> *%p2
+ %p1 = getelementptr <4 x i8>, ptr %in, i32 %newcount
+ %p2 = getelementptr <4 x i8>, ptr %out, i32 %newcount
+ %tmp1 = load <4 x i8> , ptr %p1, align 4
+ store <4 x i8> %tmp1, ptr %p2
%cmp = icmp eq i32 %newcount, %n
br i1 %cmp, label %loop, label %ret
ret:
diff --git a/llvm/test/CodeGen/ARM/add-like-or.ll b/llvm/test/CodeGen/ARM/add-like-or.ll
index 20d3ba398e16f..5de03a92afeb4 100644
--- a/llvm/test/CodeGen/ARM/add-like-or.ll
+++ b/llvm/test/CodeGen/ARM/add-like-or.ll
@@ -184,7 +184,7 @@ entry:
ret i32 %add
}
-define i32 @orgep(i32 %i, i32* %x, i32* %y) {
+define i32 @orgep(i32 %i, ptr %x, ptr %y) {
; CHECK-T1-LABEL: orgep:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: lsls r0, r0, #3
@@ -206,12 +206,12 @@ define i32 @orgep(i32 %i, i32* %x, i32* %y) {
entry:
%mul = shl i32 %i, 1
%add = or i32 %mul, 1
- %arrayidx = getelementptr inbounds i32, i32* %x, i32 %add
- %0 = load i32, i32* %arrayidx, align 8
+ %arrayidx = getelementptr inbounds i32, ptr %x, i32 %add
+ %0 = load i32, ptr %arrayidx, align 8
ret i32 %0
}
-define i32 @orgeps(i32 %i, i32* %x, i32* %y) {
+define i32 @orgeps(i32 %i, ptr %x, ptr %y) {
; CHECK-T1-LABEL: orgeps:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: lsls r0, r0, #3
@@ -237,16 +237,16 @@ define i32 @orgeps(i32 %i, i32* %x, i32* %y) {
entry:
%mul = shl i32 %i, 1
%add = or i32 %mul, 1
- %arrayidx = getelementptr inbounds i32, i32* %x, i32 %add
- %0 = load i32, i32* %arrayidx, align 8
+ %arrayidx = getelementptr inbounds i32, ptr %x, i32 %add
+ %0 = load i32, ptr %arrayidx, align 8
%add2 = add i32 %mul, 2
- %arrayidx3 = getelementptr inbounds i32, i32* %x, i32 %add2
- %1 = load i32, i32* %arrayidx3, align 8
+ %arrayidx3 = getelementptr inbounds i32, ptr %x, i32 %add2
+ %1 = load i32, ptr %arrayidx3, align 8
%add4 = add i32 %1, %0
ret i32 %add4
}
-define i32 @multiuse(i32 %i, i32* %x, i32* %y) {
+define i32 @multiuse(i32 %i, ptr %x, ptr %y) {
; CHECK-T1-LABEL: multiuse:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: lsls r0, r0, #1
@@ -274,8 +274,8 @@ define i32 @multiuse(i32 %i, i32* %x, i32* %y) {
entry:
%mul = shl i32 %i, 1
%add = or i32 %mul, 1
- %arrayidx = getelementptr inbounds i32, i32* %x, i32 %add
- %0 = load i32, i32* %arrayidx, align 8
+ %arrayidx = getelementptr inbounds i32, ptr %x, i32 %add
+ %0 = load i32, ptr %arrayidx, align 8
%r = add i32 %add, %0
ret i32 %r
}
diff --git a/llvm/test/CodeGen/ARM/addrmode.ll b/llvm/test/CodeGen/ARM/addrmode.ll
index 52bb9a20662ec..72f7d2645a0f0 100644
--- a/llvm/test/CodeGen/ARM/addrmode.ll
+++ b/llvm/test/CodeGen/ARM/addrmode.ll
@@ -3,15 +3,15 @@
define i32 @t1(i32 %a) {
%b = mul i32 %a, 9
- %c = inttoptr i32 %b to i32*
- %d = load i32, i32* %c
+ %c = inttoptr i32 %b to ptr
+ %d = load i32, ptr %c
ret i32 %d
}
define i32 @t2(i32 %a) {
%b = mul i32 %a, -7
- %c = inttoptr i32 %b to i32*
- %d = load i32, i32* %c
+ %c = inttoptr i32 %b to ptr
+ %d = load i32, ptr %c
ret i32 %d
}
diff --git a/llvm/test/CodeGen/ARM/addrspacecast.ll b/llvm/test/CodeGen/ARM/addrspacecast.ll
index 7b6237d719d17..950c3c4452a49 100644
--- a/llvm/test/CodeGen/ARM/addrspacecast.ll
+++ b/llvm/test/CodeGen/ARM/addrspacecast.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=arm-eabi %s -o /dev/null
; Check that codegen for an addrspace cast succeeds without error.
-define <4 x i32 addrspace(1)*> @f (<4 x i32*> %x) {
- %1 = addrspacecast <4 x i32*> %x to <4 x i32 addrspace(1)*>
- ret <4 x i32 addrspace(1)*> %1
+define <4 x ptr addrspace(1)> @f (<4 x ptr> %x) {
+ %1 = addrspacecast <4 x ptr> %x to <4 x ptr addrspace(1)>
+ ret <4 x ptr addrspace(1)> %1
}
diff --git a/llvm/test/CodeGen/ARM/addsubo-legalization.ll b/llvm/test/CodeGen/ARM/addsubo-legalization.ll
index 64a6faf85345f..5ebb115791c66 100644
--- a/llvm/test/CodeGen/ARM/addsubo-legalization.ll
+++ b/llvm/test/CodeGen/ARM/addsubo-legalization.ll
@@ -6,7 +6,7 @@ declare {<2 x i64>, <2 x i1>} @llvm.usub.with.overflow.v2i64(<2 x i64>, <2 x i64
declare {<2 x i64>, <2 x i1>} @llvm.sadd.with.overflow.v2i64(<2 x i64>, <2 x i64>)
declare {<2 x i64>, <2 x i1>} @llvm.ssub.with.overflow.v2i64(<2 x i64>, <2 x i64>)
-define <2 x i1> @uaddo(<2 x i64> *%ptr, <2 x i64> *%ptr2) {
+define <2 x i1> @uaddo(ptr %ptr, ptr %ptr2) {
; CHECK-LABEL: uaddo:
; CHECK: @ %bb.0:
; CHECK-NEXT: push {r4, r5, r6, r7, lr}
@@ -36,16 +36,16 @@ define <2 x i1> @uaddo(<2 x i64> *%ptr, <2 x i64> *%ptr2) {
; CHECK-NEXT: vst1.64 {d16, d17}, [r0]
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
- %x = load <2 x i64>, <2 x i64>* %ptr, align 8
- %y = load <2 x i64>, <2 x i64>* %ptr2, align 8
+ %x = load <2 x i64>, ptr %ptr, align 8
+ %y = load <2 x i64>, ptr %ptr2, align 8
%s = call {<2 x i64>, <2 x i1>} @llvm.uadd.with.overflow.v2i64(<2 x i64> %x, <2 x i64> %y)
%m = extractvalue {<2 x i64>, <2 x i1>} %s, 0
%o = extractvalue {<2 x i64>, <2 x i1>} %s, 1
- store <2 x i64> %m, <2 x i64>* %ptr
+ store <2 x i64> %m, ptr %ptr
ret <2 x i1> %o
}
-define <2 x i1> @usubo(<2 x i64> *%ptr, <2 x i64> *%ptr2) {
+define <2 x i1> @usubo(ptr %ptr, ptr %ptr2) {
; CHECK-LABEL: usubo:
; CHECK: @ %bb.0:
; CHECK-NEXT: push {r4, r5, r6, r7, lr}
@@ -75,16 +75,16 @@ define <2 x i1> @usubo(<2 x i64> *%ptr, <2 x i64> *%ptr2) {
; CHECK-NEXT: vst1.64 {d16, d17}, [r0]
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
- %x = load <2 x i64>, <2 x i64>* %ptr, align 8
- %y = load <2 x i64>, <2 x i64>* %ptr2, align 8
+ %x = load <2 x i64>, ptr %ptr, align 8
+ %y = load <2 x i64>, ptr %ptr2, align 8
%s = call {<2 x i64>, <2 x i1>} @llvm.usub.with.overflow.v2i64(<2 x i64> %x, <2 x i64> %y)
%m = extractvalue {<2 x i64>, <2 x i1>} %s, 0
%o = extractvalue {<2 x i64>, <2 x i1>} %s, 1
- store <2 x i64> %m, <2 x i64>* %ptr
+ store <2 x i64> %m, ptr %ptr
ret <2 x i1> %o
}
-define <2 x i1> @saddo(<2 x i64> *%ptr, <2 x i64> *%ptr2) {
+define <2 x i1> @saddo(ptr %ptr, ptr %ptr2) {
; CHECK-LABEL: saddo:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -100,16 +100,16 @@ define <2 x i1> @saddo(<2 x i64> *%ptr, <2 x i64> *%ptr2) {
; CHECK-NEXT: vmov r2, r1, d18
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: bx lr
- %x = load <2 x i64>, <2 x i64>* %ptr, align 8
- %y = load <2 x i64>, <2 x i64>* %ptr2, align 8
+ %x = load <2 x i64>, ptr %ptr, align 8
+ %y = load <2 x i64>, ptr %ptr2, align 8
%s = call {<2 x i64>, <2 x i1>} @llvm.sadd.with.overflow.v2i64(<2 x i64> %x, <2 x i64> %y)
%m = extractvalue {<2 x i64>, <2 x i1>} %s, 0
%o = extractvalue {<2 x i64>, <2 x i1>} %s, 1
- store <2 x i64> %m, <2 x i64>* %ptr
+ store <2 x i64> %m, ptr %ptr
ret <2 x i1> %o
}
-define <2 x i1> @ssubo(<2 x i64> *%ptr, <2 x i64> *%ptr2) {
+define <2 x i1> @ssubo(ptr %ptr, ptr %ptr2) {
; CHECK-LABEL: ssubo:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -125,11 +125,11 @@ define <2 x i1> @ssubo(<2 x i64> *%ptr, <2 x i64> *%ptr2) {
; CHECK-NEXT: vmov r2, r1, d18
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: bx lr
- %x = load <2 x i64>, <2 x i64>* %ptr, align 8
- %y = load <2 x i64>, <2 x i64>* %ptr2, align 8
+ %x = load <2 x i64>, ptr %ptr, align 8
+ %y = load <2 x i64>, ptr %ptr2, align 8
%s = call {<2 x i64>, <2 x i1>} @llvm.ssub.with.overflow.v2i64(<2 x i64> %x, <2 x i64> %y)
%m = extractvalue {<2 x i64>, <2 x i1>} %s, 0
%o = extractvalue {<2 x i64>, <2 x i1>} %s, 1
- store <2 x i64> %m, <2 x i64>* %ptr
+ store <2 x i64> %m, ptr %ptr
ret <2 x i1> %o
}
diff --git a/llvm/test/CodeGen/ARM/aeabi-read-tp.ll b/llvm/test/CodeGen/ARM/aeabi-read-tp.ll
index d15755a837fcb..6e081c0444d7c 100644
--- a/llvm/test/CodeGen/ARM/aeabi-read-tp.ll
+++ b/llvm/test/CodeGen/ARM/aeabi-read-tp.ll
@@ -7,7 +7,7 @@
define dso_local i32 @f() local_unnamed_addr {
entry:
- %0 = load i32, i32* @i, align 4
+ %0 = load i32, ptr @i, align 4
ret i32 %0
}
diff --git a/llvm/test/CodeGen/ARM/alias_align.ll b/llvm/test/CodeGen/ARM/alias_align.ll
index 452dfefbfcc65..e59d12d893818 100644
--- a/llvm/test/CodeGen/ARM/alias_align.ll
+++ b/llvm/test/CodeGen/ARM/alias_align.ll
@@ -11,15 +11,11 @@ target triple = "armv8-arm-none-eabi"
define i64 @somesortofhash() {
entry:
%helper = alloca i8, i32 64, align 8
- %helper.0.4x32 = bitcast i8* %helper to <4 x i32>*
- %helper.20 = getelementptr inbounds i8, i8* %helper, i32 20
- %helper.24 = getelementptr inbounds i8, i8* %helper, i32 24
- store <4 x i32> zeroinitializer, <4 x i32>* %helper.0.4x32, align 8
- %helper.20.32 = bitcast i8* %helper.20 to i32*
- %helper.24.32 = bitcast i8* %helper.24 to i32*
- store i32 0, i32* %helper.20.32
- store i32 0, i32* %helper.24.32, align 8
- %helper.20.64 = bitcast i8* %helper.20 to i64*
- %load.helper.20.64 = load i64, i64* %helper.20.64, align 4
+ %helper.20 = getelementptr inbounds i8, ptr %helper, i32 20
+ %helper.24 = getelementptr inbounds i8, ptr %helper, i32 24
+ store <4 x i32> zeroinitializer, ptr %helper, align 8
+ store i32 0, ptr %helper.20
+ store i32 0, ptr %helper.24, align 8
+ %load.helper.20.64 = load i64, ptr %helper.20, align 4
ret i64 %load.helper.20.64
}
diff --git a/llvm/test/CodeGen/ARM/alias_store.ll b/llvm/test/CodeGen/ARM/alias_store.ll
index 1509cb78f8c58..c6612334eaf1b 100644
--- a/llvm/test/CodeGen/ARM/alias_store.ll
+++ b/llvm/test/CodeGen/ARM/alias_store.ll
@@ -1,11 +1,11 @@
; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
@X = constant {i8, i8 } { i8 0, i8 0 }
- at XA = alias i8, getelementptr inbounds ({ i8, i8 }, {i8, i8}* @X, i32 0, i32 1)
+ at XA = alias i8, getelementptr inbounds ({ i8, i8 }, ptr @X, i32 0, i32 1)
-define void @f(i8** %p) align 2 {
+define void @f(ptr %p) align 2 {
entry:
- store i8* @XA, i8 **%p, align 4
+ store ptr @XA, ptr %p, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/aliases.ll b/llvm/test/CodeGen/ARM/aliases.ll
index 74694f3922107..cc423afa240c4 100644
--- a/llvm/test/CodeGen/ARM/aliases.ll
+++ b/llvm/test/CodeGen/ARM/aliases.ll
@@ -33,29 +33,29 @@
; CHECK: .size elem1, 4
@bar = global i32 42
- at foo1 = alias i32, i32* @bar
- at foo2 = alias i32, i32* @bar
+ at foo1 = alias i32, ptr @bar
+ at foo2 = alias i32, ptr @bar
%FunTy = type i32()
define i32 @foo_f() {
ret i32 0
}
- at bar_f = weak alias %FunTy, %FunTy* @foo_f
+ at bar_f = weak alias %FunTy, ptr @foo_f
- at bar_i = internal alias i32, i32* @bar
+ at bar_i = internal alias i32, ptr @bar
- at A = alias i64, bitcast (i32* @bar to i64*)
+ at A = alias i64, ptr @bar
@structvar = private global {i32, i32} {i32 1, i32 2}
- at elem0 = alias i32, getelementptr({i32, i32}, {i32, i32}* @structvar, i32 0, i32 0)
- at elem1 = alias i32, getelementptr({i32, i32}, {i32, i32}* @structvar, i32 0, i32 1)
+ at elem0 = alias i32, getelementptr({i32, i32}, ptr @structvar, i32 0, i32 0)
+ at elem1 = alias i32, getelementptr({i32, i32}, ptr @structvar, i32 0, i32 1)
define i32 @test() {
entry:
- %tmp = load i32, i32* @foo1
- %tmp1 = load i32, i32* @foo2
- %tmp0 = load i32, i32* @bar_i
+ %tmp = load i32, ptr @foo1
+ %tmp1 = load i32, ptr @foo2
+ %tmp0 = load i32, ptr @bar_i
%tmp2 = call i32 @foo_f()
%tmp3 = add i32 %tmp, %tmp2
%tmp4 = call i32 @bar_f()
diff --git a/llvm/test/CodeGen/ARM/align-sp-adjustment.ll b/llvm/test/CodeGen/ARM/align-sp-adjustment.ll
index 7840d95c151be..c09940a388eac 100644
--- a/llvm/test/CodeGen/ARM/align-sp-adjustment.ll
+++ b/llvm/test/CodeGen/ARM/align-sp-adjustment.ll
@@ -10,35 +10,34 @@
@.str.2 = private unnamed_addr constant [2 x i8] c"c\00", align 1
@.str.3 = private unnamed_addr constant [2 x i8] c"d\00", align 1
-declare i32* @_Z4bar3iiPKcS0_i(i32, i32, i8*, i8*, i32)
-declare void @_Z4bar1i8struct_2(i32, %struct.struct_2* byval(%struct.struct_2) align 4)
-declare i32 @_Z4bar2PiPKc(i32*, i8*)
+declare ptr @_Z4bar3iiPKcS0_i(i32, i32, ptr, ptr, i32)
+declare void @_Z4bar1i8struct_2(i32, ptr byval(%struct.struct_2) align 4)
+declare i32 @_Z4bar2PiPKc(ptr, ptr)
define void @_Z3fooiiiii(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) #0 {
entry:
%params = alloca %struct.struct_2, align 4
- %0 = bitcast %struct.struct_2* %params to i8*
br label %for.body
for.body:
%i.015 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
- %call = tail call i32* @_Z4bar3iiPKcS0_i(i32 %p1, i32 %p5, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.1, i32 0, i32 0), i32 %i.015) #4
- %cmp1 = icmp eq i32* %call, null
+ %call = tail call ptr @_Z4bar3iiPKcS0_i(i32 %p1, i32 %p5, ptr @.str, ptr @.str.1, i32 %i.015) #4
+ %cmp1 = icmp eq ptr %call, null
br i1 %cmp1, label %cleanup.8, label %for.inc
for.inc:
- %call2 = tail call i32 @_Z4bar2PiPKc(i32* %call, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.2, i32 0, i32 0)) #4
- %f1 = getelementptr inbounds %struct.struct_2, %struct.struct_2* %params, i32 0, i32 0, i32 %i.015, i32 0
- store i32 %call2, i32* %f1, align 4
- %call3 = tail call i32 @_Z4bar2PiPKc(i32* %call, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.3, i32 0, i32 0)) #4
- %f2 = getelementptr inbounds %struct.struct_2, %struct.struct_2* %params, i32 0, i32 0, i32 %i.015, i32 1
- store i32 %call3, i32* %f2, align 4
+ %call2 = tail call i32 @_Z4bar2PiPKc(ptr %call, ptr @.str.2) #4
+ %f1 = getelementptr inbounds %struct.struct_2, ptr %params, i32 0, i32 0, i32 %i.015, i32 0
+ store i32 %call2, ptr %f1, align 4
+ %call3 = tail call i32 @_Z4bar2PiPKc(ptr %call, ptr @.str.3) #4
+ %f2 = getelementptr inbounds %struct.struct_2, ptr %params, i32 0, i32 0, i32 %i.015, i32 1
+ store i32 %call3, ptr %f2, align 4
%inc = add nuw nsw i32 %i.015, 1
%cmp = icmp slt i32 %inc, 4
br i1 %cmp, label %for.body, label %for.end
for.end:
- call void @_Z4bar1i8struct_2(i32 %p4, %struct.struct_2* byval(%struct.struct_2) nonnull align 4 %params) #4
+ call void @_Z4bar1i8struct_2(i32 %p4, ptr byval(%struct.struct_2) nonnull align 4 %params) #4
br label %cleanup.8
cleanup.8:
diff --git a/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll b/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll
index f0c066911f12d..9b20f9a641570 100644
--- a/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll
+++ b/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll
@@ -4,7 +4,7 @@
; When realign-stack is set to false, make sure we are not creating stack
; objects that are assumed to be 64-byte aligned.
-define void @test1(<16 x float>* noalias sret(<16 x float>) %agg.result) nounwind ssp "no-realign-stack" {
+define void @test1(ptr noalias sret(<16 x float>) %agg.result) nounwind ssp "no-realign-stack" {
; CHECK-LABEL: test1:
; CHECK: mov r[[PTR:[0-9]+]], r{{[0-9]+}}
; CHECK: mov r[[NOTALIGNED:[0-9]+]], sp
@@ -16,22 +16,18 @@ define void @test1(<16 x float>* noalias sret(<16 x float>) %agg.result) nounwin
; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[NOTALIGNED]]:128]
entry:
%retval = alloca <16 x float>, align 64
- %a1 = bitcast <16 x float>* %retval to float*
- %a2 = getelementptr inbounds float, float* %a1, i64 8
- %a3 = bitcast float* %a2 to <4 x float>*
+ %a2 = getelementptr inbounds float, ptr %retval, i64 8
- %b1 = bitcast <16 x float>* %agg.result to float*
- %b2 = getelementptr inbounds float, float* %b1, i64 8
- %b3 = bitcast float* %b2 to <4 x float>*
+ %b2 = getelementptr inbounds float, ptr %agg.result, i64 8
- %0 = load <4 x float>, <4 x float>* %a3, align 16
- %1 = load <4 x float>, <4 x float>* %b3, align 16
- store <4 x float> %0, <4 x float>* %b3, align 16
- store <4 x float> %1, <4 x float>* %a3, align 16
+ %0 = load <4 x float>, ptr %a2, align 16
+ %1 = load <4 x float>, ptr %b2, align 16
+ store <4 x float> %0, ptr %b2, align 16
+ store <4 x float> %1, ptr %a2, align 16
ret void
}
-define void @test2(<16 x float>* noalias sret(<16 x float>) %agg.result) nounwind ssp {
+define void @test2(ptr noalias sret(<16 x float>) %agg.result) nounwind ssp {
; CHECK-LABEL: test2:
; CHECK: mov r[[PTR:[0-9]+]], r{{[0-9]+}}
; CHECK: mov r[[ALIGNED:[0-9]+]], sp
@@ -43,17 +39,13 @@ define void @test2(<16 x float>* noalias sret(<16 x float>) %agg.result) nounwin
; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[ALIGNED]]:128]
entry:
%retval = alloca <16 x float>, align 64
- %a1 = bitcast <16 x float>* %retval to float*
- %a2 = getelementptr inbounds float, float* %a1, i64 8
- %a3 = bitcast float* %a2 to <4 x float>*
+ %a2 = getelementptr inbounds float, ptr %retval, i64 8
- %b1 = bitcast <16 x float>* %agg.result to float*
- %b2 = getelementptr inbounds float, float* %b1, i64 8
- %b3 = bitcast float* %b2 to <4 x float>*
+ %b2 = getelementptr inbounds float, ptr %agg.result, i64 8
- %0 = load <4 x float>, <4 x float>* %a3, align 16
- %1 = load <4 x float>, <4 x float>* %b3, align 16
- store <4 x float> %0, <4 x float>* %b3, align 16
- store <4 x float> %1, <4 x float>* %a3, align 16
+ %0 = load <4 x float>, ptr %a2, align 16
+ %1 = load <4 x float>, ptr %b2, align 16
+ store <4 x float> %0, ptr %b2, align 16
+ store <4 x float> %1, ptr %a2, align 16
ret void
}
diff --git a/llvm/test/CodeGen/ARM/alloca-align.ll b/llvm/test/CodeGen/ARM/alloca-align.ll
index 76c265abbd1a3..6f5eb9d012da3 100644
--- a/llvm/test/CodeGen/ARM/alloca-align.ll
+++ b/llvm/test/CodeGen/ARM/alloca-align.ll
@@ -1,9 +1,9 @@
; RUN: llc -o - %s | FileCheck %s
target triple="arm--"
- at glob = external global i32*
+ at glob = external global ptr
-declare void @bar(i32*, [20000 x i8]* byval([20000 x i8]))
+declare void @bar(ptr, ptr byval([20000 x i8]))
; CHECK-LABEL: foo:
; We should see the stack getting additional alignment
@@ -14,10 +14,9 @@ declare void @bar(i32*, [20000 x i8]* byval([20000 x i8]))
; Which is passed to the call
; CHECK: mov r0, r6
; CHECK: bl bar
-define void @foo([20000 x i8]* %addr) {
+define void @foo(ptr %addr) {
%tmp = alloca [4 x i32], align 32
- %tmp0 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 0
- call void @bar(i32* %tmp0, [20000 x i8]* byval([20000 x i8]) %addr)
+ call void @bar(ptr %tmp, ptr byval([20000 x i8]) %addr)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/alloca.ll b/llvm/test/CodeGen/ARM/alloca.ll
index efa0ae347ddcc..8c5405db97b1b 100644
--- a/llvm/test/CodeGen/ARM/alloca.ll
+++ b/llvm/test/CodeGen/ARM/alloca.ll
@@ -3,10 +3,10 @@
define void @f(i32 %a) {
entry:
; CHECK: add r11, sp, #8
- %tmp = alloca i8, i32 %a ; <i8*> [#uses=1]
- call void @g( i8* %tmp, i32 %a, i32 1, i32 2, i32 3 )
+ %tmp = alloca i8, i32 %a ; <ptr> [#uses=1]
+ call void @g( ptr %tmp, i32 %a, i32 1, i32 2, i32 3 )
ret void
; CHECK: sub sp, r11, #8
}
-declare void @g(i8*, i32, i32, i32, i32)
+declare void @g(ptr, i32, i32, i32, i32)
diff --git a/llvm/test/CodeGen/ARM/and-cmpz.ll b/llvm/test/CodeGen/ARM/and-cmpz.ll
index b327f04ba06f3..1f72307f12a68 100644
--- a/llvm/test/CodeGen/ARM/and-cmpz.ll
+++ b/llvm/test/CodeGen/ARM/and-cmpz.ll
@@ -23,8 +23,8 @@ false:
; T2-NEXT: mov
; T2-NEXT: it
; T1-NEXT: bmi
-define i32 @single_bit_multi_use(i32 %p, i32* %z) {
- store i32 %p, i32* %z
+define i32 @single_bit_multi_use(i32 %p, ptr %z) {
+ store i32 %p, ptr %z
%a = and i32 %p, 256
%b = icmp eq i32 %a, 0
br i1 %b, label %true, label %false
@@ -95,7 +95,7 @@ false:
; T2: uxth r0, r0
; T2-NEXT: movs r2, #0
; T2-NEXT: cmp.w r2, r0, lsr #9
-define void @i16_cmpz(i16 %x, void (i32)* %foo) {
+define void @i16_cmpz(i16 %x, ptr %foo) {
entry:
%cmp = icmp ult i16 %x, 512
br i1 %cmp, label %if.then, label %if.end
diff --git a/llvm/test/CodeGen/ARM/and-load-combine.ll b/llvm/test/CodeGen/ARM/and-load-combine.ll
index 41361947d5b01..dfb71483851da 100644
--- a/llvm/test/CodeGen/ARM/and-load-combine.ll
+++ b/llvm/test/CodeGen/ARM/and-load-combine.ll
@@ -4,7 +4,7 @@
; RUN: llc -mtriple=armv6m %s -o - | FileCheck %s --check-prefix=THUMB1
; RUN: llc -mtriple=thumbv8m.main %s -o - | FileCheck %s --check-prefix=THUMB2
-define arm_aapcscc zeroext i1 @cmp_xor8_short_short(i16* nocapture readonly %a, i16* nocapture readonly %b) {
+define arm_aapcscc zeroext i1 @cmp_xor8_short_short(ptr nocapture readonly %a, ptr nocapture readonly %b) {
; ARM-LABEL: cmp_xor8_short_short:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r0, [r0]
@@ -41,15 +41,15 @@ define arm_aapcscc zeroext i1 @cmp_xor8_short_short(i16* nocapture readonly %a,
; THUMB2-NEXT: lsrs r0, r0, #5
; THUMB2-NEXT: bx lr
entry:
- %0 = load i16, i16* %a, align 2
- %1 = load i16, i16* %b, align 2
+ %0 = load i16, ptr %a, align 2
+ %1 = load i16, ptr %b, align 2
%xor2 = xor i16 %1, %0
%2 = and i16 %xor2, 255
%cmp = icmp eq i16 %2, 0
ret i1 %cmp
}
-define arm_aapcscc zeroext i1 @cmp_xor8_short_int(i16* nocapture readonly %a, i32* nocapture readonly %b) {
+define arm_aapcscc zeroext i1 @cmp_xor8_short_int(ptr nocapture readonly %a, ptr nocapture readonly %b) {
; ARM-LABEL: cmp_xor8_short_int:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r0, [r0]
@@ -86,16 +86,16 @@ define arm_aapcscc zeroext i1 @cmp_xor8_short_int(i16* nocapture readonly %a, i3
; THUMB2-NEXT: lsrs r0, r0, #5
; THUMB2-NEXT: bx lr
entry:
- %0 = load i16, i16* %a, align 2
+ %0 = load i16, ptr %a, align 2
%conv = zext i16 %0 to i32
- %1 = load i32, i32* %b, align 4
+ %1 = load i32, ptr %b, align 4
%xor = xor i32 %1, %conv
%and = and i32 %xor, 255
%cmp = icmp eq i32 %and, 0
ret i1 %cmp
}
-define arm_aapcscc zeroext i1 @cmp_xor8_int_int(i32* nocapture readonly %a, i32* nocapture readonly %b) {
+define arm_aapcscc zeroext i1 @cmp_xor8_int_int(ptr nocapture readonly %a, ptr nocapture readonly %b) {
; ARM-LABEL: cmp_xor8_int_int:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r0, [r0]
@@ -132,15 +132,15 @@ define arm_aapcscc zeroext i1 @cmp_xor8_int_int(i32* nocapture readonly %a, i32*
; THUMB2-NEXT: lsrs r0, r0, #5
; THUMB2-NEXT: bx lr
entry:
- %0 = load i32, i32* %a, align 4
- %1 = load i32, i32* %b, align 4
+ %0 = load i32, ptr %a, align 4
+ %1 = load i32, ptr %b, align 4
%xor = xor i32 %1, %0
%and = and i32 %xor, 255
%cmp = icmp eq i32 %and, 0
ret i1 %cmp
}
-define arm_aapcscc zeroext i1 @cmp_xor16(i32* nocapture readonly %a, i32* nocapture readonly %b) {
+define arm_aapcscc zeroext i1 @cmp_xor16(ptr nocapture readonly %a, ptr nocapture readonly %b) {
; ARM-LABEL: cmp_xor16:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrh r0, [r0]
@@ -177,15 +177,15 @@ define arm_aapcscc zeroext i1 @cmp_xor16(i32* nocapture readonly %a, i32* nocapt
; THUMB2-NEXT: lsrs r0, r0, #5
; THUMB2-NEXT: bx lr
entry:
- %0 = load i32, i32* %a, align 4
- %1 = load i32, i32* %b, align 4
+ %0 = load i32, ptr %a, align 4
+ %1 = load i32, ptr %b, align 4
%xor = xor i32 %1, %0
%and = and i32 %xor, 65535
%cmp = icmp eq i32 %and, 0
ret i1 %cmp
}
-define arm_aapcscc zeroext i1 @cmp_or8_short_short(i16* nocapture readonly %a, i16* nocapture readonly %b) {
+define arm_aapcscc zeroext i1 @cmp_or8_short_short(ptr nocapture readonly %a, ptr nocapture readonly %b) {
; ARM-LABEL: cmp_or8_short_short:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r0, [r0]
@@ -222,15 +222,15 @@ define arm_aapcscc zeroext i1 @cmp_or8_short_short(i16* nocapture readonly %a, i
; THUMB2-NEXT: lsrs r0, r0, #5
; THUMB2-NEXT: bx lr
entry:
- %0 = load i16, i16* %a, align 2
- %1 = load i16, i16* %b, align 2
+ %0 = load i16, ptr %a, align 2
+ %1 = load i16, ptr %b, align 2
%or2 = or i16 %1, %0
%2 = and i16 %or2, 255
%cmp = icmp eq i16 %2, 0
ret i1 %cmp
}
-define arm_aapcscc zeroext i1 @cmp_or8_short_int(i16* nocapture readonly %a, i32* nocapture readonly %b) {
+define arm_aapcscc zeroext i1 @cmp_or8_short_int(ptr nocapture readonly %a, ptr nocapture readonly %b) {
; ARM-LABEL: cmp_or8_short_int:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r0, [r0]
@@ -267,16 +267,16 @@ define arm_aapcscc zeroext i1 @cmp_or8_short_int(i16* nocapture readonly %a, i32
; THUMB2-NEXT: lsrs r0, r0, #5
; THUMB2-NEXT: bx lr
entry:
- %0 = load i16, i16* %a, align 2
+ %0 = load i16, ptr %a, align 2
%conv = zext i16 %0 to i32
- %1 = load i32, i32* %b, align 4
+ %1 = load i32, ptr %b, align 4
%or = or i32 %1, %conv
%and = and i32 %or, 255
%cmp = icmp eq i32 %and, 0
ret i1 %cmp
}
-define arm_aapcscc zeroext i1 @cmp_or8_int_int(i32* nocapture readonly %a, i32* nocapture readonly %b) {
+define arm_aapcscc zeroext i1 @cmp_or8_int_int(ptr nocapture readonly %a, ptr nocapture readonly %b) {
; ARM-LABEL: cmp_or8_int_int:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r0, [r0]
@@ -313,15 +313,15 @@ define arm_aapcscc zeroext i1 @cmp_or8_int_int(i32* nocapture readonly %a, i32*
; THUMB2-NEXT: lsrs r0, r0, #5
; THUMB2-NEXT: bx lr
entry:
- %0 = load i32, i32* %a, align 4
- %1 = load i32, i32* %b, align 4
+ %0 = load i32, ptr %a, align 4
+ %1 = load i32, ptr %b, align 4
%or = or i32 %1, %0
%and = and i32 %or, 255
%cmp = icmp eq i32 %and, 0
ret i1 %cmp
}
-define arm_aapcscc zeroext i1 @cmp_or16(i32* nocapture readonly %a, i32* nocapture readonly %b) {
+define arm_aapcscc zeroext i1 @cmp_or16(ptr nocapture readonly %a, ptr nocapture readonly %b) {
; ARM-LABEL: cmp_or16:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrh r0, [r0]
@@ -358,15 +358,15 @@ define arm_aapcscc zeroext i1 @cmp_or16(i32* nocapture readonly %a, i32* nocaptu
; THUMB2-NEXT: lsrs r0, r0, #5
; THUMB2-NEXT: bx lr
entry:
- %0 = load i32, i32* %a, align 4
- %1 = load i32, i32* %b, align 4
+ %0 = load i32, ptr %a, align 4
+ %1 = load i32, ptr %b, align 4
%or = or i32 %1, %0
%and = and i32 %or, 65535
%cmp = icmp eq i32 %and, 0
ret i1 %cmp
}
-define arm_aapcscc zeroext i1 @cmp_and8_short_short(i16* nocapture readonly %a, i16* nocapture readonly %b) {
+define arm_aapcscc zeroext i1 @cmp_and8_short_short(ptr nocapture readonly %a, ptr nocapture readonly %b) {
; ARM-LABEL: cmp_and8_short_short:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r1, [r1]
@@ -403,15 +403,15 @@ define arm_aapcscc zeroext i1 @cmp_and8_short_short(i16* nocapture readonly %a,
; THUMB2-NEXT: lsrs r0, r0, #5
; THUMB2-NEXT: bx lr
entry:
- %0 = load i16, i16* %a, align 2
- %1 = load i16, i16* %b, align 2
+ %0 = load i16, ptr %a, align 2
+ %1 = load i16, ptr %b, align 2
%and3 = and i16 %0, 255
%2 = and i16 %and3, %1
%cmp = icmp eq i16 %2, 0
ret i1 %cmp
}
-define arm_aapcscc zeroext i1 @cmp_and8_short_int(i16* nocapture readonly %a, i32* nocapture readonly %b) {
+define arm_aapcscc zeroext i1 @cmp_and8_short_int(ptr nocapture readonly %a, ptr nocapture readonly %b) {
; ARM-LABEL: cmp_and8_short_int:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r0, [r0]
@@ -448,8 +448,8 @@ define arm_aapcscc zeroext i1 @cmp_and8_short_int(i16* nocapture readonly %a, i3
; THUMB2-NEXT: lsrs r0, r0, #5
; THUMB2-NEXT: bx lr
entry:
- %0 = load i16, i16* %a, align 2
- %1 = load i32, i32* %b, align 4
+ %0 = load i16, ptr %a, align 2
+ %1 = load i32, ptr %b, align 4
%2 = and i16 %0, 255
%and = zext i16 %2 to i32
%and1 = and i32 %1, %and
@@ -457,7 +457,7 @@ entry:
ret i1 %cmp
}
-define arm_aapcscc zeroext i1 @cmp_and8_int_int(i32* nocapture readonly %a, i32* nocapture readonly %b) {
+define arm_aapcscc zeroext i1 @cmp_and8_int_int(ptr nocapture readonly %a, ptr nocapture readonly %b) {
; ARM-LABEL: cmp_and8_int_int:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r1, [r1]
@@ -494,15 +494,15 @@ define arm_aapcscc zeroext i1 @cmp_and8_int_int(i32* nocapture readonly %a, i32*
; THUMB2-NEXT: lsrs r0, r0, #5
; THUMB2-NEXT: bx lr
entry:
- %0 = load i32, i32* %a, align 4
- %1 = load i32, i32* %b, align 4
+ %0 = load i32, ptr %a, align 4
+ %1 = load i32, ptr %b, align 4
%and = and i32 %0, 255
%and1 = and i32 %and, %1
%cmp = icmp eq i32 %and1, 0
ret i1 %cmp
}
-define arm_aapcscc zeroext i1 @cmp_and16(i32* nocapture readonly %a, i32* nocapture readonly %b) {
+define arm_aapcscc zeroext i1 @cmp_and16(ptr nocapture readonly %a, ptr nocapture readonly %b) {
; ARM-LABEL: cmp_and16:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrh r1, [r1]
@@ -539,15 +539,15 @@ define arm_aapcscc zeroext i1 @cmp_and16(i32* nocapture readonly %a, i32* nocapt
; THUMB2-NEXT: lsrs r0, r0, #5
; THUMB2-NEXT: bx lr
entry:
- %0 = load i32, i32* %a, align 4
- %1 = load i32, i32* %b, align 4
+ %0 = load i32, ptr %a, align 4
+ %1 = load i32, ptr %b, align 4
%and = and i32 %0, 65535
%and1 = and i32 %and, %1
%cmp = icmp eq i32 %and1, 0
ret i1 %cmp
}
-define arm_aapcscc i32 @add_and16(i32* nocapture readonly %a, i32 %y, i32 %z) {
+define arm_aapcscc i32 @add_and16(ptr nocapture readonly %a, i32 %y, i32 %z) {
; ARM-LABEL: add_and16:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: add r1, r1, r2
@@ -580,14 +580,14 @@ define arm_aapcscc i32 @add_and16(i32* nocapture readonly %a, i32 %y, i32 %z) {
; THUMB2-NEXT: orrs r0, r1
; THUMB2-NEXT: bx lr
entry:
- %x = load i32, i32* %a, align 4
+ %x = load i32, ptr %a, align 4
%add = add i32 %y, %z
%or = or i32 %x, %add
%and = and i32 %or, 65535
ret i32 %and
}
-define arm_aapcscc i32 @test1(i32* %a, i32* %b, i32 %x, i32 %y) {
+define arm_aapcscc i32 @test1(ptr %a, ptr %b, i32 %x, i32 %y) {
; ARM-LABEL: test1:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: mul r2, r2, r3
@@ -629,8 +629,8 @@ define arm_aapcscc i32 @test1(i32* %a, i32* %b, i32 %x, i32 %y) {
; THUMB2-NEXT: orrs r0, r1
; THUMB2-NEXT: bx lr
entry:
- %0 = load i32, i32* %a, align 4
- %1 = load i32, i32* %b, align 4
+ %0 = load i32, ptr %a, align 4
+ %1 = load i32, ptr %b, align 4
%mul = mul i32 %x, %y
%xor = xor i32 %0, %1
%or = or i32 %xor, %mul
@@ -638,7 +638,7 @@ entry:
ret i32 %and
}
-define arm_aapcscc i32 @test2(i32* %a, i32* %b, i32 %x, i32 %y) {
+define arm_aapcscc i32 @test2(ptr %a, ptr %b, i32 %x, i32 %y) {
; ARM-LABEL: test2:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldr r1, [r1]
@@ -679,8 +679,8 @@ define arm_aapcscc i32 @test2(i32* %a, i32* %b, i32 %x, i32 %y) {
; THUMB2-NEXT: uxth r0, r0
; THUMB2-NEXT: bx lr
entry:
- %0 = load i32, i32* %a, align 4
- %1 = load i32, i32* %b, align 4
+ %0 = load i32, ptr %a, align 4
+ %1 = load i32, ptr %b, align 4
%mul = mul i32 %x, %1
%xor = xor i32 %0, %y
%or = or i32 %xor, %mul
@@ -688,7 +688,7 @@ entry:
ret i32 %and
}
-define arm_aapcscc i32 @test3(i32* %a, i32* %b, i32 %x, i16* %y) {
+define arm_aapcscc i32 @test3(ptr %a, ptr %b, i32 %x, ptr %y) {
; ARM-LABEL: test3:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldr r0, [r0]
@@ -729,8 +729,8 @@ define arm_aapcscc i32 @test3(i32* %a, i32* %b, i32 %x, i16* %y) {
; THUMB2-NEXT: uxth r0, r0
; THUMB2-NEXT: bx lr
entry:
- %0 = load i32, i32* %a, align 4
- %1 = load i16, i16* %y, align 4
+ %0 = load i32, ptr %a, align 4
+ %1 = load i16, ptr %y, align 4
%2 = zext i16 %1 to i32
%mul = mul i32 %x, %0
%xor = xor i32 %0, %2
@@ -739,7 +739,7 @@ entry:
ret i32 %and
}
-define arm_aapcscc i32 @test4(i32* %a, i32* %b, i32 %x, i32 %y) {
+define arm_aapcscc i32 @test4(ptr %a, ptr %b, i32 %x, i32 %y) {
; ARM-LABEL: test4:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: mul r2, r2, r3
@@ -781,8 +781,8 @@ define arm_aapcscc i32 @test4(i32* %a, i32* %b, i32 %x, i32 %y) {
; THUMB2-NEXT: orrs r0, r1
; THUMB2-NEXT: bx lr
entry:
- %0 = load i32, i32* %a, align 4
- %1 = load i32, i32* %b, align 4
+ %0 = load i32, ptr %a, align 4
+ %1 = load i32, ptr %b, align 4
%mul = mul i32 %x, %y
%xor = xor i32 %0, %1
%or = or i32 %xor, %mul
@@ -790,7 +790,7 @@ entry:
ret i32 %and
}
-define arm_aapcscc i32 @test5(i32* %a, i32* %b, i32 %x, i16 zeroext %y) {
+define arm_aapcscc i32 @test5(ptr %a, ptr %b, i32 %x, i16 zeroext %y) {
; ARM-LABEL: test5:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldr r1, [r1]
@@ -832,8 +832,8 @@ define arm_aapcscc i32 @test5(i32* %a, i32* %b, i32 %x, i16 zeroext %y) {
; THUMB2-NEXT: orrs r0, r1
; THUMB2-NEXT: bx lr
entry:
- %0 = load i32, i32* %a, align 4
- %1 = load i32, i32* %b, align 4
+ %0 = load i32, ptr %a, align 4
+ %1 = load i32, ptr %b, align 4
%mul = mul i32 %x, %1
%ext = zext i16 %y to i32
%xor = xor i32 %0, %ext
@@ -842,7 +842,7 @@ entry:
ret i32 %and
}
-define arm_aapcscc i1 @test6(i8* %x, i8 %y, i8 %z) {
+define arm_aapcscc i1 @test6(ptr %x, i8 %y, i8 %z) {
; ARM-LABEL: test6:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r0, [r0]
@@ -883,13 +883,13 @@ define arm_aapcscc i1 @test6(i8* %x, i8 %y, i8 %z) {
; THUMB2-NEXT: lsrs r0, r0, #5
; THUMB2-NEXT: bx lr
entry:
- %0 = load i8, i8* %x, align 4
+ %0 = load i8, ptr %x, align 4
%1 = and i8 %0, %y
%2 = icmp eq i8 %1, %z
ret i1 %2
}
-define arm_aapcscc i1 @test7(i16* %x, i16 %y, i8 %z) {
+define arm_aapcscc i1 @test7(ptr %x, i16 %y, i8 %z) {
; ARM-LABEL: test7:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r0, [r0]
@@ -930,14 +930,14 @@ define arm_aapcscc i1 @test7(i16* %x, i16 %y, i8 %z) {
; THUMB2-NEXT: lsrs r0, r0, #5
; THUMB2-NEXT: bx lr
entry:
- %0 = load i16, i16* %x, align 4
+ %0 = load i16, ptr %x, align 4
%1 = and i16 %0, %y
%2 = trunc i16 %1 to i8
%3 = icmp eq i8 %2, %z
ret i1 %3
}
-define arm_aapcscc void @test8(i32* nocapture %p) {
+define arm_aapcscc void @test8(ptr nocapture %p) {
; ARM-LABEL: test8:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r1, [r0]
@@ -967,14 +967,14 @@ define arm_aapcscc void @test8(i32* nocapture %p) {
; THUMB2-NEXT: str r1, [r0]
; THUMB2-NEXT: bx lr
entry:
- %0 = load i32, i32* %p, align 4
+ %0 = load i32, ptr %p, align 4
%neg = and i32 %0, 255
%and = xor i32 %neg, 255
- store i32 %and, i32* %p, align 4
+ store i32 %and, ptr %p, align 4
ret void
}
-define arm_aapcscc void @test9(i32* nocapture %p) {
+define arm_aapcscc void @test9(ptr nocapture %p) {
; ARM-LABEL: test9:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r1, [r0]
@@ -1004,14 +1004,14 @@ define arm_aapcscc void @test9(i32* nocapture %p) {
; THUMB2-NEXT: str r1, [r0]
; THUMB2-NEXT: bx lr
entry:
- %0 = load i32, i32* %p, align 4
+ %0 = load i32, ptr %p, align 4
%neg = xor i32 %0, -1
%and = and i32 %neg, 255
- store i32 %and, i32* %p, align 4
+ store i32 %and, ptr %p, align 4
ret void
}
-define arm_aapcscc void @test10(i32* nocapture %p) {
+define arm_aapcscc void @test10(ptr nocapture %p) {
; ARM-LABEL: test10:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r1, [r0]
@@ -1041,14 +1041,14 @@ define arm_aapcscc void @test10(i32* nocapture %p) {
; THUMB2-NEXT: str r1, [r0]
; THUMB2-NEXT: bx lr
entry:
- %0 = load i32, i32* %p, align 4
+ %0 = load i32, ptr %p, align 4
%neg = and i32 %0, 255
%and = xor i32 %neg, 255
- store i32 %and, i32* %p, align 4
+ store i32 %and, ptr %p, align 4
ret void
}
-define arm_aapcscc i32 @test11(i32* nocapture %p) {
+define arm_aapcscc i32 @test11(ptr nocapture %p) {
; ARM-LABEL: test11:
; ARM: @ %bb.0:
; ARM-NEXT: ldrb r0, [r0, #1]
@@ -1072,12 +1072,12 @@ define arm_aapcscc i32 @test11(i32* nocapture %p) {
; THUMB2-NEXT: ldrb r0, [r0, #1]
; THUMB2-NEXT: lsls r0, r0, #8
; THUMB2-NEXT: bx lr
- %1 = load i32, i32* %p, align 4
+ %1 = load i32, ptr %p, align 4
%and = and i32 %1, 65280
ret i32 %and
}
-define arm_aapcscc i32 @test12(i32* nocapture %p) {
+define arm_aapcscc i32 @test12(ptr nocapture %p) {
; ARM-LABEL: test12:
; ARM: @ %bb.0:
; ARM-NEXT: ldrb r0, [r0, #2]
@@ -1101,12 +1101,12 @@ define arm_aapcscc i32 @test12(i32* nocapture %p) {
; THUMB2-NEXT: ldrb r0, [r0, #2]
; THUMB2-NEXT: lsls r0, r0, #16
; THUMB2-NEXT: bx lr
- %1 = load i32, i32* %p, align 4
+ %1 = load i32, ptr %p, align 4
%and = and i32 %1, 16711680
ret i32 %and
}
-define arm_aapcscc i32 @test13(i32* nocapture %p) {
+define arm_aapcscc i32 @test13(ptr nocapture %p) {
; ARM-LABEL: test13:
; ARM: @ %bb.0:
; ARM-NEXT: ldrb r0, [r0, #3]
@@ -1130,12 +1130,12 @@ define arm_aapcscc i32 @test13(i32* nocapture %p) {
; THUMB2-NEXT: ldrb r0, [r0, #3]
; THUMB2-NEXT: lsls r0, r0, #24
; THUMB2-NEXT: bx lr
- %1 = load i32, i32* %p, align 4
+ %1 = load i32, ptr %p, align 4
%and = and i32 %1, 4278190080
ret i32 %and
}
-define arm_aapcscc i32 @test14(i32* nocapture %p) {
+define arm_aapcscc i32 @test14(ptr nocapture %p) {
; ARM-LABEL: test14:
; ARM: @ %bb.0:
; ARM-NEXT: ldrh r0, [r0, #1]
@@ -1164,12 +1164,12 @@ define arm_aapcscc i32 @test14(i32* nocapture %p) {
; THUMB2-NEXT: ldrh.w r0, [r0, #1]
; THUMB2-NEXT: lsls r0, r0, #8
; THUMB2-NEXT: bx lr
- %1 = load i32, i32* %p, align 4
+ %1 = load i32, ptr %p, align 4
%and = and i32 %1, 16776960
ret i32 %and
}
-define arm_aapcscc i32 @test15(i32* nocapture %p) {
+define arm_aapcscc i32 @test15(ptr nocapture %p) {
; ARM-LABEL: test15:
; ARM: @ %bb.0:
; ARM-NEXT: ldrh r0, [r0, #2]
@@ -1193,12 +1193,12 @@ define arm_aapcscc i32 @test15(i32* nocapture %p) {
; THUMB2-NEXT: ldrh r0, [r0, #2]
; THUMB2-NEXT: lsls r0, r0, #16
; THUMB2-NEXT: bx lr
- %1 = load i32, i32* %p, align 4
+ %1 = load i32, ptr %p, align 4
%and = and i32 %1, 4294901760
ret i32 %and
}
-define arm_aapcscc i32 @test16(i64* nocapture %p) {
+define arm_aapcscc i32 @test16(ptr nocapture %p) {
; ARM-LABEL: test16:
; ARM: @ %bb.0:
; ARM-NEXT: ldrb r0, [r0, #1]
@@ -1222,13 +1222,13 @@ define arm_aapcscc i32 @test16(i64* nocapture %p) {
; THUMB2-NEXT: ldrb r0, [r0, #1]
; THUMB2-NEXT: lsls r0, r0, #8
; THUMB2-NEXT: bx lr
- %1 = load i64, i64* %p, align 8
+ %1 = load i64, ptr %p, align 8
%and = and i64 %1, 65280
%trunc = trunc i64 %and to i32
ret i32 %trunc
}
-define arm_aapcscc i32 @test17(i64* nocapture %p) {
+define arm_aapcscc i32 @test17(ptr nocapture %p) {
; ARM-LABEL: test17:
; ARM: @ %bb.0:
; ARM-NEXT: ldrb r0, [r0, #2]
@@ -1252,13 +1252,13 @@ define arm_aapcscc i32 @test17(i64* nocapture %p) {
; THUMB2-NEXT: ldrb r0, [r0, #2]
; THUMB2-NEXT: lsls r0, r0, #16
; THUMB2-NEXT: bx lr
- %1 = load i64, i64* %p, align 8
+ %1 = load i64, ptr %p, align 8
%and = and i64 %1, 16711680
%trunc = trunc i64 %and to i32
ret i32 %trunc
}
-define arm_aapcscc i32 @test18(i64* nocapture %p) {
+define arm_aapcscc i32 @test18(ptr nocapture %p) {
; ARM-LABEL: test18:
; ARM: @ %bb.0:
; ARM-NEXT: ldrb r0, [r0, #3]
@@ -1282,13 +1282,13 @@ define arm_aapcscc i32 @test18(i64* nocapture %p) {
; THUMB2-NEXT: ldrb r0, [r0, #3]
; THUMB2-NEXT: lsls r0, r0, #24
; THUMB2-NEXT: bx lr
- %1 = load i64, i64* %p, align 8
+ %1 = load i64, ptr %p, align 8
%and = and i64 %1, 4278190080
%trunc = trunc i64 %and to i32
ret i32 %trunc
}
-define arm_aapcscc i64 @test19(i64* nocapture %p) {
+define arm_aapcscc i64 @test19(ptr nocapture %p) {
; ARM-LABEL: test19:
; ARM: @ %bb.0:
; ARM-NEXT: ldrb r1, [r0, #4]
@@ -1312,12 +1312,12 @@ define arm_aapcscc i64 @test19(i64* nocapture %p) {
; THUMB2-NEXT: ldrb r1, [r0, #4]
; THUMB2-NEXT: movs r0, #0
; THUMB2-NEXT: bx lr
- %1 = load i64, i64* %p, align 8
+ %1 = load i64, ptr %p, align 8
%and = and i64 %1, 1095216660480
ret i64 %and
}
-define arm_aapcscc i64 @test20(i64* nocapture %p) {
+define arm_aapcscc i64 @test20(ptr nocapture %p) {
; ARM-LABEL: test20:
; ARM: @ %bb.0:
; ARM-NEXT: ldrb r0, [r0, #5]
@@ -1345,12 +1345,12 @@ define arm_aapcscc i64 @test20(i64* nocapture %p) {
; THUMB2-NEXT: lsls r1, r0, #8
; THUMB2-NEXT: movs r0, #0
; THUMB2-NEXT: bx lr
- %1 = load i64, i64* %p, align 8
+ %1 = load i64, ptr %p, align 8
%and = and i64 %1, 280375465082880
ret i64 %and
}
-define arm_aapcscc i64 @test21(i64* nocapture %p) {
+define arm_aapcscc i64 @test21(ptr nocapture %p) {
; ARM-LABEL: test21:
; ARM: @ %bb.0:
; ARM-NEXT: ldrb r0, [r0, #6]
@@ -1378,12 +1378,12 @@ define arm_aapcscc i64 @test21(i64* nocapture %p) {
; THUMB2-NEXT: lsls r1, r0, #16
; THUMB2-NEXT: movs r0, #0
; THUMB2-NEXT: bx lr
- %1 = load i64, i64* %p, align 8
+ %1 = load i64, ptr %p, align 8
%and = and i64 %1, 71776119061217280
ret i64 %and
}
-define arm_aapcscc i64 @test22(i64* nocapture %p) {
+define arm_aapcscc i64 @test22(ptr nocapture %p) {
; ARM-LABEL: test22:
; ARM: @ %bb.0:
; ARM-NEXT: ldrb r0, [r0, #7]
@@ -1411,12 +1411,12 @@ define arm_aapcscc i64 @test22(i64* nocapture %p) {
; THUMB2-NEXT: lsls r1, r0, #24
; THUMB2-NEXT: movs r0, #0
; THUMB2-NEXT: bx lr
- %1 = load i64, i64* %p, align 8
+ %1 = load i64, ptr %p, align 8
%and = and i64 %1, -72057594037927936
ret i64 %and
}
-define arm_aapcscc i64 @test23(i64* nocapture %p) {
+define arm_aapcscc i64 @test23(ptr nocapture %p) {
; ARM-LABEL: test23:
; ARM: @ %bb.0:
; ARM-NEXT: ldrh r1, [r0, #3]
@@ -1444,12 +1444,12 @@ define arm_aapcscc i64 @test23(i64* nocapture %p) {
; THUMB2-NEXT: lsls r0, r1, #24
; THUMB2-NEXT: lsrs r1, r1, #8
; THUMB2-NEXT: bx lr
- %1 = load i64, i64* %p, align 8
+ %1 = load i64, ptr %p, align 8
%and = and i64 %1, 1099494850560
ret i64 %and
}
-define arm_aapcscc i64 @test24(i64* nocapture %p) {
+define arm_aapcscc i64 @test24(ptr nocapture %p) {
; ARM-LABEL: test24:
; ARM: @ %bb.0:
; ARM-NEXT: ldrh r1, [r0, #4]
@@ -1473,12 +1473,12 @@ define arm_aapcscc i64 @test24(i64* nocapture %p) {
; THUMB2-NEXT: ldrh r1, [r0, #4]
; THUMB2-NEXT: movs r0, #0
; THUMB2-NEXT: bx lr
- %1 = load i64, i64* %p, align 8
+ %1 = load i64, ptr %p, align 8
%and = and i64 %1, 281470681743360
ret i64 %and
}
-define arm_aapcscc i64 @test25(i64* nocapture %p) {
+define arm_aapcscc i64 @test25(ptr nocapture %p) {
; ARM-LABEL: test25:
; ARM: @ %bb.0:
; ARM-NEXT: ldrh r0, [r0, #5]
@@ -1511,12 +1511,12 @@ define arm_aapcscc i64 @test25(i64* nocapture %p) {
; THUMB2-NEXT: lsls r1, r0, #8
; THUMB2-NEXT: movs r0, #0
; THUMB2-NEXT: bx lr
- %1 = load i64, i64* %p, align 8
+ %1 = load i64, ptr %p, align 8
%and = and i64 %1, 72056494526300160
ret i64 %and
}
-define arm_aapcscc i64 @test26(i64* nocapture %p) {
+define arm_aapcscc i64 @test26(ptr nocapture %p) {
; ARM-LABEL: test26:
; ARM: @ %bb.0:
; ARM-NEXT: ldrh r0, [r0, #6]
@@ -1544,12 +1544,12 @@ define arm_aapcscc i64 @test26(i64* nocapture %p) {
; THUMB2-NEXT: lsls r1, r0, #16
; THUMB2-NEXT: movs r0, #0
; THUMB2-NEXT: bx lr
- %1 = load i64, i64* %p, align 8
+ %1 = load i64, ptr %p, align 8
%and = and i64 %1, -281474976710656
ret i64 %and
}
-define void @test27(i32* nocapture %ptr) {
+define void @test27(ptr nocapture %ptr) {
; ARM-LABEL: test27:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r1, [r0, #1]
@@ -1578,9 +1578,9 @@ define void @test27(i32* nocapture %ptr) {
; THUMB2-NEXT: str r1, [r0]
; THUMB2-NEXT: bx lr
entry:
- %0 = load i32, i32* %ptr, align 4
+ %0 = load i32, ptr %ptr, align 4
%and = and i32 %0, 65280
%shl = shl i32 %and, 8
- store i32 %shl, i32* %ptr, align 4
+ store i32 %shl, ptr %ptr, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/and-sext-combine.ll b/llvm/test/CodeGen/ARM/and-sext-combine.ll
index 4a20c87043869..3ca72b6b37a20 100644
--- a/llvm/test/CodeGen/ARM/and-sext-combine.ll
+++ b/llvm/test/CodeGen/ARM/and-sext-combine.ll
@@ -17,10 +17,10 @@
; CHECK-NEXT: smulbb r0, r0, r1
; CHECK-NEXT: mul r0, r0, r1
; CHECK-NEXT: bx lr
-define i32 @f_i16_i32(i16* %a, i16* %b) {
- %1 = load i16, i16* %a, align 2
+define i32 @f_i16_i32(ptr %a, ptr %b) {
+ %1 = load i16, ptr %a, align 2
%sext.1 = sext i16 %1 to i32
- %2 = load i16, i16* %b, align 2
+ %2 = load i16, ptr %b, align 2
%sext.2 = sext i16 %2 to i32
%masked = and i32 %sext.2, 65535
%mul = mul nsw i32 %sext.2, %sext.1
diff --git a/llvm/test/CodeGen/ARM/apcs-vfp.ll b/llvm/test/CodeGen/ARM/apcs-vfp.ll
index 9157521bfbc44..3c84d348dddef 100644
--- a/llvm/test/CodeGen/ARM/apcs-vfp.ll
+++ b/llvm/test/CodeGen/ARM/apcs-vfp.ll
@@ -7,10 +7,10 @@ entry:
; CHECK: vadd.f32
%a.addr = alloca float, align 4
%b.addr = alloca float, align 4
- store float %a, float* %a.addr, align 4
- store float %b, float* %b.addr, align 4
- %0 = load float, float* %a.addr, align 4
- %1 = load float, float* %b.addr, align 4
+ store float %a, ptr %a.addr, align 4
+ store float %b, ptr %b.addr, align 4
+ %0 = load float, ptr %a.addr, align 4
+ %1 = load float, ptr %b.addr, align 4
%add = fadd float %0, %1
ret float %add
}
@@ -22,10 +22,10 @@ entry:
; CHECK: vadd.f64
%a.addr = alloca double, align 8
%b.addr = alloca double, align 8
- store double %a, double* %a.addr, align 8
- store double %b, double* %b.addr, align 8
- %0 = load double, double* %a.addr, align 8
- %1 = load double, double* %b.addr, align 8
+ store double %a, ptr %a.addr, align 8
+ store double %b, ptr %b.addr, align 8
+ %0 = load double, ptr %a.addr, align 8
+ %1 = load double, ptr %b.addr, align 8
%add = fadd double %0, %1
ret double %add
}
diff --git a/llvm/test/CodeGen/ARM/arg-copy-elide.ll b/llvm/test/CodeGen/ARM/arg-copy-elide.ll
index 625b570734068..da1d16e9f9d78 100644
--- a/llvm/test/CodeGen/ARM/arg-copy-elide.ll
+++ b/llvm/test/CodeGen/ARM/arg-copy-elide.ll
@@ -1,13 +1,13 @@
; RUN: llc -mtriple=armv7-linux < %s | FileCheck %s
-declare arm_aapcscc void @addrof_i32(i32*)
-declare arm_aapcscc void @addrof_i64(i64*)
+declare arm_aapcscc void @addrof_i32(ptr)
+declare arm_aapcscc void @addrof_i64(ptr)
define arm_aapcscc void @simple(i32, i32, i32, i32, i32 %x) {
entry:
%x.addr = alloca i32
- store i32 %x, i32* %x.addr
- call void @addrof_i32(i32* %x.addr)
+ store i32 %x, ptr %x.addr
+ call void @addrof_i32(ptr %x.addr)
ret void
}
@@ -24,8 +24,8 @@ entry:
define arm_aapcscc i32 @use_arg(i32, i32, i32, i32, i32 %x) {
entry:
%x.addr = alloca i32
- store i32 %x, i32* %x.addr
- call void @addrof_i32(i32* %x.addr)
+ store i32 %x, ptr %x.addr
+ call void @addrof_i32(ptr %x.addr)
ret i32 %x
}
@@ -41,8 +41,8 @@ entry:
define arm_aapcscc i64 @split_i64(i32, i32, i32, i32, i64 %x) {
entry:
%x.addr = alloca i64, align 4
- store i64 %x, i64* %x.addr, align 4
- call void @addrof_i64(i64* %x.addr)
+ store i64 %x, ptr %x.addr, align 4
+ call void @addrof_i64(ptr %x.addr)
ret i64 %x
}
diff --git a/llvm/test/CodeGen/ARM/argaddr.ll b/llvm/test/CodeGen/ARM/argaddr.ll
index 40bc5e0b82a7d..dbd45e1b45025 100644
--- a/llvm/test/CodeGen/ARM/argaddr.ll
+++ b/llvm/test/CodeGen/ARM/argaddr.ll
@@ -2,18 +2,18 @@
define void @f(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
entry:
- %a_addr = alloca i32 ; <i32*> [#uses=2]
- %b_addr = alloca i32 ; <i32*> [#uses=2]
- %c_addr = alloca i32 ; <i32*> [#uses=2]
- %d_addr = alloca i32 ; <i32*> [#uses=2]
- %e_addr = alloca i32 ; <i32*> [#uses=2]
- store i32 %a, i32* %a_addr
- store i32 %b, i32* %b_addr
- store i32 %c, i32* %c_addr
- store i32 %d, i32* %d_addr
- store i32 %e, i32* %e_addr
- call void @g( i32* %a_addr, i32* %b_addr, i32* %c_addr, i32* %d_addr, i32* %e_addr )
+ %a_addr = alloca i32 ; <ptr> [#uses=2]
+ %b_addr = alloca i32 ; <ptr> [#uses=2]
+ %c_addr = alloca i32 ; <ptr> [#uses=2]
+ %d_addr = alloca i32 ; <ptr> [#uses=2]
+ %e_addr = alloca i32 ; <ptr> [#uses=2]
+ store i32 %a, ptr %a_addr
+ store i32 %b, ptr %b_addr
+ store i32 %c, ptr %c_addr
+ store i32 %d, ptr %d_addr
+ store i32 %e, ptr %e_addr
+ call void @g( ptr %a_addr, ptr %b_addr, ptr %c_addr, ptr %d_addr, ptr %e_addr )
ret void
}
-declare void @g(i32*, i32*, i32*, i32*, i32*)
+declare void @g(ptr, ptr, ptr, ptr, ptr)
diff --git a/llvm/test/CodeGen/ARM/arm-abi-attr.ll b/llvm/test/CodeGen/ARM/arm-abi-attr.ll
index f05e6e788d6fc..2025ac4cd9cc7 100644
--- a/llvm/test/CodeGen/ARM/arm-abi-attr.ll
+++ b/llvm/test/CodeGen/ARM/arm-abi-attr.ll
@@ -21,8 +21,8 @@ define void @g() {
; AAPCS-NOT: bic
%c = alloca i8, align 8
- call void @f(i8* %c)
+ call void @f(ptr %c)
ret void
}
-declare void @f(i8*)
+declare void @f(ptr)
diff --git a/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll b/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
index 31458b71e88d7..365727c9dd27d 100644
--- a/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
+++ b/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
@@ -6,12 +6,12 @@
; FIXME: The -mtriple=thumb test doesn't change if -disable-peephole is specified.
-%struct.Foo = type { i8* }
+%struct.Foo = type { ptr }
; ARM-LABEL: foo:
; THUMB-LABEL: foo:
; T2-LABEL: foo:
-define %struct.Foo* @foo(%struct.Foo* %this, i32 %acc) nounwind readonly align 2 {
+define ptr @foo(ptr %this, i32 %acc) nounwind readonly align 2 {
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: add r2, r0, #4
; ARM-NEXT: mov r12, #1
@@ -159,17 +159,16 @@ define %struct.Foo* @foo(%struct.Foo* %this, i32 %acc) nounwind readonly align 2
; V8-NEXT: add.w r0, r0, r1, lsl #2
; V8-NEXT: bx lr
entry:
- %scevgep = getelementptr %struct.Foo, %struct.Foo* %this, i32 1
+ %scevgep = getelementptr %struct.Foo, ptr %this, i32 1
br label %tailrecurse
tailrecurse: ; preds = %sw.bb, %entry
- %lsr.iv2 = phi %struct.Foo* [ %scevgep3, %sw.bb ], [ %scevgep, %entry ]
+ %lsr.iv2 = phi ptr [ %scevgep3, %sw.bb ], [ %scevgep, %entry ]
%lsr.iv = phi i32 [ %lsr.iv.next, %sw.bb ], [ 1, %entry ]
%acc.tr = phi i32 [ %or, %sw.bb ], [ %acc, %entry ]
- %lsr.iv24 = bitcast %struct.Foo* %lsr.iv2 to i8**
- %scevgep5 = getelementptr i8*, i8** %lsr.iv24, i32 -1
- %tmp2 = load i8*, i8** %scevgep5
- %0 = ptrtoint i8* %tmp2 to i32
+ %scevgep5 = getelementptr ptr, ptr %lsr.iv2, i32 -1
+ %tmp2 = load ptr, ptr %scevgep5
+ %0 = ptrtoint ptr %tmp2 to i32
@@ -190,32 +189,32 @@ sw.bb: ; preds = %tailrecurse.switch,
%shl = shl i32 %acc.tr, 1
%or = or i32 %and, %shl
%lsr.iv.next = add i32 %lsr.iv, 1
- %scevgep3 = getelementptr %struct.Foo, %struct.Foo* %lsr.iv2, i32 1
+ %scevgep3 = getelementptr %struct.Foo, ptr %lsr.iv2, i32 1
br label %tailrecurse
sw.bb6: ; preds = %tailrecurse.switch
- ret %struct.Foo* %lsr.iv2
+ ret ptr %lsr.iv2
sw.bb8: ; preds = %tailrecurse.switch
%tmp1 = add i32 %acc.tr, %lsr.iv
- %add.ptr11 = getelementptr inbounds %struct.Foo, %struct.Foo* %this, i32 %tmp1
- ret %struct.Foo* %add.ptr11
+ %add.ptr11 = getelementptr inbounds %struct.Foo, ptr %this, i32 %tmp1
+ ret ptr %add.ptr11
sw.epilog: ; preds = %tailrecurse.switch
- ret %struct.Foo* undef
+ ret ptr undef
}
; Another test that exercises the AND/TST peephole optimization and also
; generates a predicated ANDS instruction. Check that the predicate is printed
; after the "S" modifier on the instruction.
-%struct.S = type { i8* (i8*)*, [1 x i8] }
+%struct.S = type { ptr, [1 x i8] }
; ARM-LABEL: bar:
; THUMB-LABEL: bar:
; T2-LABEL: bar:
; V8-LABEL: bar:
-define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly {
+define internal zeroext i8 @bar(ptr %x, ptr nocapture %y) nounwind readonly {
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r2, [r0, #4]
; ARM-NEXT: ands r2, r2, #112
@@ -288,16 +287,16 @@ define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind
; V8-NEXT: movs r0, #1
; V8-NEXT: bx lr
entry:
- %0 = getelementptr inbounds %struct.S, %struct.S* %x, i32 0, i32 1, i32 0
- %1 = load i8, i8* %0, align 1
+ %0 = getelementptr inbounds %struct.S, ptr %x, i32 0, i32 1, i32 0
+ %1 = load i8, ptr %0, align 1
%2 = zext i8 %1 to i32
%3 = and i32 %2, 112
%4 = icmp eq i32 %3, 0
br i1 %4, label %return, label %bb
bb: ; preds = %entry
- %5 = getelementptr inbounds %struct.S, %struct.S* %y, i32 0, i32 1, i32 0
- %6 = load i8, i8* %5, align 1
+ %5 = getelementptr inbounds %struct.S, ptr %y, i32 0, i32 1, i32 0
+ %6 = load i8, ptr %5, align 1
%7 = zext i8 %6 to i32
%8 = and i32 %7, 112
%9 = icmp eq i32 %8, 0
@@ -310,7 +309,7 @@ bb2: ; preds = %bb
br i1 %or.cond, label %bb4, label %return
bb4: ; preds = %bb2
- %12 = ptrtoint %struct.S* %x to i32
+ %12 = ptrtoint ptr %x to i32
%phitmp = trunc i32 %12 to i8
ret i8 %phitmp
diff --git a/llvm/test/CodeGen/ARM/arm-asm.ll b/llvm/test/CodeGen/ARM/arm-asm.ll
index f9199ff82b38c..5007621dd2d93 100644
--- a/llvm/test/CodeGen/ARM/arm-asm.ll
+++ b/llvm/test/CodeGen/ARM/arm-asm.ll
@@ -2,6 +2,6 @@
define void @frame_dummy() {
entry:
- %tmp1 = tail call void (i8*)* (void (i8*)*) asm "", "=r,0,~{dirflag},~{fpsr},~{flags}"( void (i8*)* null ) ; <void (i8*)*> [#uses=0]
+ %tmp1 = tail call ptr (ptr) asm "", "=r,0,~{dirflag},~{fpsr},~{flags}"( ptr null ) ; <ptr> [#uses=0]
ret void
}
diff --git a/llvm/test/CodeGen/ARM/arm-bf16-pcs.ll b/llvm/test/CodeGen/ARM/arm-bf16-pcs.ll
index 8b665bab9da08..07ae23c6d0591 100644
--- a/llvm/test/CodeGen/ARM/arm-bf16-pcs.ll
+++ b/llvm/test/CodeGen/ARM/arm-bf16-pcs.ll
@@ -4,7 +4,7 @@
; RUN: llc -mtriple armv8.6a-arm-none-eabi -mattr=+fullfp16 -o - %s | FileCheck %s --check-prefix=FULLFP16 --check-prefix=FULLFP16-ARM
; RUN: llc -mtriple thumbv8.6a-arm-none-eabi -mattr=+fullfp16 -o - %s | FileCheck %s --check-prefix=FULLFP16 --check-prefix=FULLFP16-THUMB
-define bfloat @bf_load_soft(bfloat* %p) {
+define bfloat @bf_load_soft(ptr %p) {
; BASE-LABEL: bf_load_soft:
; BASE: @ %bb.0:
; BASE-NEXT: ldrh r0, [r0]
@@ -15,11 +15,11 @@ define bfloat @bf_load_soft(bfloat* %p) {
; FULLFP16-NEXT: vldr.16 s0, [r0]
; FULLFP16-NEXT: vmov r0, s0
; FULLFP16-NEXT: bx lr
- %f = load bfloat, bfloat* %p, align 2
+ %f = load bfloat, ptr %p, align 2
ret bfloat %f
}
-define arm_aapcs_vfpcc bfloat @bf_load_hard(bfloat* %p) {
+define arm_aapcs_vfpcc bfloat @bf_load_hard(ptr %p) {
; BASE-LABEL: bf_load_hard:
; BASE: @ %bb.0:
; BASE-NEXT: ldrh r0, [r0]
@@ -30,11 +30,11 @@ define arm_aapcs_vfpcc bfloat @bf_load_hard(bfloat* %p) {
; FULLFP16: @ %bb.0:
; FULLFP16-NEXT: vldr.16 s0, [r0]
; FULLFP16-NEXT: bx lr
- %f = load bfloat, bfloat* %p, align 2
+ %f = load bfloat, ptr %p, align 2
ret bfloat %f
}
-define void @bf_store_soft(bfloat* %p, bfloat %f) {
+define void @bf_store_soft(ptr %p, bfloat %f) {
; BASE-LABEL: bf_store_soft:
; BASE: @ %bb.0:
; BASE-NEXT: strh r1, [r0]
@@ -45,11 +45,11 @@ define void @bf_store_soft(bfloat* %p, bfloat %f) {
; FULLFP16-NEXT: vmov.f16 s0, r1
; FULLFP16-NEXT: vstr.16 s0, [r0]
; FULLFP16-NEXT: bx lr
- store bfloat %f, bfloat* %p, align 2
+ store bfloat %f, ptr %p, align 2
ret void
}
-define arm_aapcs_vfpcc void @bf_store_hard(bfloat* %p, bfloat %f) {
+define arm_aapcs_vfpcc void @bf_store_hard(ptr %p, bfloat %f) {
; BASE-LABEL: bf_store_hard:
; BASE: @ %bb.0:
; BASE-NEXT: vmov r1, s0
@@ -60,7 +60,7 @@ define arm_aapcs_vfpcc void @bf_store_hard(bfloat* %p, bfloat %f) {
; FULLFP16: @ %bb.0:
; FULLFP16-NEXT: vstr.16 s0, [r0]
; FULLFP16-NEXT: bx lr
- store bfloat %f, bfloat* %p, align 2
+ store bfloat %f, ptr %p, align 2
ret void
}
@@ -155,7 +155,7 @@ define arm_aapcs_vfpcc bfloat @bf_from_int_hard(i32 %w) {
ret bfloat %f
}
-define bfloat @test_fncall_soft(bfloat %bf, bfloat (bfloat, bfloat)* %f) {
+define bfloat @test_fncall_soft(bfloat %bf, ptr %f) {
; BASE-ARM-LABEL: test_fncall_soft:
; BASE-ARM: @ %bb.0:
; BASE-ARM-NEXT: .save {r4, r5, r11, lr}
@@ -238,7 +238,7 @@ define bfloat @test_fncall_soft(bfloat %bf, bfloat (bfloat, bfloat)* %f) {
ret bfloat %call
}
-define arm_aapcs_vfpcc bfloat @test_fncall_hard(bfloat %bf, bfloat (bfloat, bfloat)* %f) {
+define arm_aapcs_vfpcc bfloat @test_fncall_hard(bfloat %bf, ptr %f) {
; BASE-ARM-LABEL: test_fncall_hard:
; BASE-ARM: @ %bb.0:
; BASE-ARM-NEXT: .save {r4, lr}
diff --git a/llvm/test/CodeGen/ARM/arm-eabi.ll b/llvm/test/CodeGen/ARM/arm-eabi.ll
index c2f364ab92b25..9abdb81805bda 100644
--- a/llvm/test/CodeGen/ARM/arm-eabi.ll
+++ b/llvm/test/CodeGen/ARM/arm-eabi.ll
@@ -29,43 +29,41 @@
%struct.my_s = type { [18 x i32] }
-define void @foo(i32* %t) {
+define void @foo(ptr %t) {
; CHECK-LABEL: foo
- %1 = alloca i32*, align 4
- store i32* %t, i32** %1, align 4
- %2 = load i32*, i32** %1, align 4
- %3 = bitcast i32* %2 to %struct.my_s*
- %4 = bitcast %struct.my_s* %3 to i8*
+ %1 = alloca ptr, align 4
+ store ptr %t, ptr %1, align 4
+ %2 = load ptr, ptr %1, align 4
; CHECK-EABI: bl __aeabi_memcpy
; CHECK-GNUEABI: bl memcpy
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %4, i8* align 4 inttoptr (i32 1 to i8*), i32 72, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 4 %2, ptr align 4 inttoptr (i32 1 to ptr), i32 72, i1 false)
ret void
}
-define void @f1(i8* %dest, i8* %src) {
+define void @f1(ptr %dest, ptr %src) {
entry:
; CHECK-LABEL: f1
; memmove
; CHECK-EABI: bl __aeabi_memmove
; CHECK-GNUEABI: bl memmove
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i1 false)
+ call void @llvm.memmove.p0.p0.i32(ptr %dest, ptr %src, i32 500, i1 false)
; memcpy
; CHECK-EABI: bl __aeabi_memcpy
; CHECK-GNUEABI: bl memcpy
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr %src, i32 500, i1 false)
; memset
; CHECK-EABI: mov r2, #1
; CHECK-EABI: bl __aeabi_memset
; CHECK-GNUEABI: mov r1, #1
; CHECK-GNUEABI: bl memset
- call void @llvm.memset.p0i8.i32(i8* %dest, i8 1, i32 500, i1 false)
+ call void @llvm.memset.p0.i32(ptr %dest, i8 1, i32 500, i1 false)
ret void
}
-declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
-declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) nounwind
+declare void @llvm.memmove.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
+declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) nounwind
diff --git a/llvm/test/CodeGen/ARM/arm-frame-lowering-no-terminator.ll b/llvm/test/CodeGen/ARM/arm-frame-lowering-no-terminator.ll
index 5a48fa3c394d6..1ea5b4b9c2583 100644
--- a/llvm/test/CodeGen/ARM/arm-frame-lowering-no-terminator.ll
+++ b/llvm/test/CodeGen/ARM/arm-frame-lowering-no-terminator.ll
@@ -6,39 +6,38 @@ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv7-unknown-linux-gnueabihf"
%t1 = type { [4 x float] }
-%t3 = type { i32 (...)** }
+%t3 = type { ptr }
%t2 = type { %t3, i8, %t1, %t1, float }
-define internal void @foo(%t2* nocapture %this, %t1* nocapture readonly %triangle, i32 %partId, i32 %triangleIndex) {
+define internal void @foo(ptr nocapture %this, ptr nocapture readonly %triangle, i32 %partId, i32 %triangleIndex) {
entry:
br i1 undef, label %if.else, label %if.end
if.else: ; preds = %entry
- %arrayidx.i = getelementptr inbounds %t1, %t1* %triangle, i32 0, i32 0, i32 0
- %0 = load float, float* %arrayidx.i, align 4
- %arrayidx5.i = getelementptr inbounds %t1, %t1* %triangle, i32 0, i32 0, i32 1
- %1 = load float, float* %arrayidx5.i, align 4
- %2 = load float, float* null, align 4
- %arrayidx11.i = getelementptr inbounds %t1, %t1* %triangle, i32 0, i32 0, i32 2
- %3 = load float, float* %arrayidx11.i, align 4
- %arrayidx13.i = getelementptr inbounds %t2, %t2* %this, i32 0, i32 2, i32 0, i32 2
- %4 = load float, float* %arrayidx13.i, align 4
- %arrayidx.i129 = getelementptr inbounds %t1, %t1* %triangle, i32 1, i32 0, i32 0
- %5 = load float, float* %arrayidx.i129, align 4
+ %0 = load float, ptr %triangle, align 4
+ %arrayidx5.i = getelementptr inbounds %t1, ptr %triangle, i32 0, i32 0, i32 1
+ %1 = load float, ptr %arrayidx5.i, align 4
+ %2 = load float, ptr null, align 4
+ %arrayidx11.i = getelementptr inbounds %t1, ptr %triangle, i32 0, i32 0, i32 2
+ %3 = load float, ptr %arrayidx11.i, align 4
+ %arrayidx13.i = getelementptr inbounds %t2, ptr %this, i32 0, i32 2, i32 0, i32 2
+ %4 = load float, ptr %arrayidx13.i, align 4
+ %arrayidx.i129 = getelementptr inbounds %t1, ptr %triangle, i32 1, i32 0, i32 0
+ %5 = load float, ptr %arrayidx.i129, align 4
%sub.i131 = fsub float %5, 0.000000e+00
- %arrayidx5.i132 = getelementptr inbounds %t1, %t1* %triangle, i32 1, i32 0, i32 1
- %6 = load float, float* %arrayidx5.i132, align 4
+ %arrayidx5.i132 = getelementptr inbounds %t1, ptr %triangle, i32 1, i32 0, i32 1
+ %6 = load float, ptr %arrayidx5.i132, align 4
%sub8.i134 = fsub float %6, %2
- %arrayidx11.i135 = getelementptr inbounds %t1, %t1* %triangle, i32 1, i32 0, i32 2
- %7 = load float, float* %arrayidx11.i135, align 4
+ %arrayidx11.i135 = getelementptr inbounds %t1, ptr %triangle, i32 1, i32 0, i32 2
+ %7 = load float, ptr %arrayidx11.i135, align 4
%sub14.i137 = fsub float %7, %4
- %arrayidx.i149 = getelementptr inbounds %t1, %t1* %triangle, i32 2, i32 0, i32 0
- %8 = load float, float* %arrayidx.i149, align 4
+ %arrayidx.i149 = getelementptr inbounds %t1, ptr %triangle, i32 2, i32 0, i32 0
+ %8 = load float, ptr %arrayidx.i149, align 4
%sub.i151 = fsub float %8, 0.000000e+00
- %arrayidx5.i152 = getelementptr inbounds %t1, %t1* %triangle, i32 2, i32 0, i32 1
- %9 = load float, float* %arrayidx5.i152, align 4
+ %arrayidx5.i152 = getelementptr inbounds %t1, ptr %triangle, i32 2, i32 0, i32 1
+ %9 = load float, ptr %arrayidx5.i152, align 4
%sub8.i154 = fsub float %9, %2
- %10 = load float, float* undef, align 4
+ %10 = load float, ptr undef, align 4
%sub14.i157 = fsub float %10, %4
%mul.i = fmul float %sub8.i134, %sub14.i157
%mul10.i = fmul float %sub14.i137, %sub8.i154
@@ -64,15 +63,15 @@ if.else: ; preds = %entry
%mul.i.i = fmul float %add.i93, %mul
%mul4.i.i = fmul float %add8.i96, %mul
%mul8.i.i = fmul float %mul, %add14.i
- %arrayidx3.i = getelementptr inbounds %t2, %t2* %this, i32 0, i32 3, i32 0, i32 0
+ %arrayidx3.i = getelementptr inbounds %t2, ptr %this, i32 0, i32 3, i32 0, i32 0
%add.i = fadd float undef, %mul.i.i
- store float %add.i, float* %arrayidx3.i, align 4
- %arrayidx7.i86 = getelementptr inbounds %t2, %t2* %this, i32 0, i32 3, i32 0, i32 1
+ store float %add.i, ptr %arrayidx3.i, align 4
+ %arrayidx7.i86 = getelementptr inbounds %t2, ptr %this, i32 0, i32 3, i32 0, i32 1
%add8.i = fadd float %mul4.i.i, undef
- store float %add8.i, float* %arrayidx7.i86, align 4
- %arrayidx12.i = getelementptr inbounds %t2, %t2* %this, i32 0, i32 3, i32 0, i32 2
+ store float %add8.i, ptr %arrayidx7.i86, align 4
+ %arrayidx12.i = getelementptr inbounds %t2, ptr %this, i32 0, i32 3, i32 0, i32 2
%add13.i = fadd float %mul8.i.i, undef
- store float %add13.i, float* %arrayidx12.i, align 4
+ store float %add13.i, ptr %arrayidx12.i, align 4
br label %if.end
if.end: ; preds = %if.else, %entry
diff --git a/llvm/test/CodeGen/ARM/arm-frameaddr.ll b/llvm/test/CodeGen/ARM/arm-frameaddr.ll
index 9c4173ef0ce23..79800423b561a 100644
--- a/llvm/test/CodeGen/ARM/arm-frameaddr.ll
+++ b/llvm/test/CodeGen/ARM/arm-frameaddr.ll
@@ -3,15 +3,15 @@
; PR4344
; PR4416
-define i8* @t() nounwind {
+define ptr @t() nounwind {
entry:
; DARWIN-LABEL: t:
; DARWIN: mov r0, r7
; LINUX-LABEL: t:
; LINUX: mov r0, r11
- %0 = call i8* @llvm.frameaddress(i32 0)
- ret i8* %0
+ %0 = call ptr @llvm.frameaddress(i32 0)
+ ret ptr %0
}
-declare i8* @llvm.frameaddress(i32) nounwind readnone
+declare ptr @llvm.frameaddress(i32) nounwind readnone
diff --git a/llvm/test/CodeGen/ARM/arm-insert-subvector.ll b/llvm/test/CodeGen/ARM/arm-insert-subvector.ll
index e4739281a0386..7a524ecb7cfa6 100644
--- a/llvm/test/CodeGen/ARM/arm-insert-subvector.ll
+++ b/llvm/test/CodeGen/ARM/arm-insert-subvector.ll
@@ -1,23 +1,23 @@
; RUN: llc -mtriple armv8-unknown-linux -o - < %s | FileCheck %s
-define <2 x float> @test_float(<6 x float>* %src) {
- %v= load <6 x float>, <6 x float>* %src, align 1
+define <2 x float> @test_float(ptr %src) {
+ %v= load <6 x float>, ptr %src, align 1
%r = shufflevector <6 x float> %v, <6 x float> undef, <2 x i32> <i32 2, i32 5>
ret <2 x float> %r
}
; CHECK-LABEL: test_float
; CHECK: vld3.32 {d16, d17, d18}, [r0]
-define <2 x i32> @test_i32(<6 x i32>* %src) {
- %v= load <6 x i32>, <6 x i32>* %src, align 1
+define <2 x i32> @test_i32(ptr %src) {
+ %v= load <6 x i32>, ptr %src, align 1
%r = shufflevector <6 x i32> %v, <6 x i32> undef, <2 x i32> <i32 2, i32 5>
ret <2 x i32> %r
}
; CHECK-LABEL: test_i32
; CHECK: vld3.32 {d16, d17, d18}, [r0]
-define <4 x i16> @test_i16(<12 x i16>* %src) {
- %v= load <12 x i16>, <12 x i16>* %src, align 1
+define <4 x i16> @test_i16(ptr %src) {
+ %v= load <12 x i16>, ptr %src, align 1
%r = shufflevector <12 x i16> %v, <12 x i16> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 7>
ret <4 x i16> %r
}
@@ -25,8 +25,8 @@ define <4 x i16> @test_i16(<12 x i16>* %src) {
; CHECK: vld1.8 {d16, d17}, [r0]!
; CHECK: vmov.u16 r1, d16[2]
-define <8 x i8> @test_i8(<24 x i8>* %src) {
- %v= load <24 x i8>, <24 x i8>* %src, align 1
+define <8 x i8> @test_i8(ptr %src) {
+ %v= load <24 x i8>, ptr %src, align 1
%r = shufflevector <24 x i8> %v, <24 x i8> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
ret <8 x i8> %r
}
diff --git a/llvm/test/CodeGen/ARM/arm-modifier.ll b/llvm/test/CodeGen/ARM/arm-modifier.ll
index 93a16fa26249a..1c7ce098aeefa 100644
--- a/llvm/test/CodeGen/ARM/arm-modifier.ll
+++ b/llvm/test/CodeGen/ARM/arm-modifier.ll
@@ -4,10 +4,10 @@ define i32 @foo(float %scale, float %scale2) nounwind {
entry:
%scale.addr = alloca float, align 4
%scale2.addr = alloca float, align 4
- store float %scale, float* %scale.addr, align 4
- store float %scale2, float* %scale2.addr, align 4
- %tmp = load float, float* %scale.addr, align 4
- %tmp1 = load float, float* %scale2.addr, align 4
+ store float %scale, ptr %scale.addr, align 4
+ store float %scale2, ptr %scale2.addr, align 4
+ %tmp = load float, ptr %scale.addr, align 4
+ %tmp1 = load float, ptr %scale2.addr, align 4
call void asm sideeffect "vmul.f32 q0, q0, ${0:y} \0A\09vmul.f32 q1, q1, ${0:y} \0A\09vmul.f32 q1, q0, ${1:y} \0A\09", "w,w,~{q0},~{q1}"(float %tmp, float %tmp1) nounwind
ret i32 0
}
@@ -28,18 +28,18 @@ call void asm sideeffect ".word ${0:L} \0A\09", "i"(i32 -1) nounwind
ret void
}
- at f2_ptr = internal global i32* @f2_var, align 4
+ at f2_ptr = internal global ptr @f2_var, align 4
@f2_var = external global i32
define void @f2() nounwind {
entry:
; CHECK: f2
; CHECK: ldr r0, [r{{[0-9]+}}]
-call void asm sideeffect "ldr r0, [${0:m}]\0A\09", "*m,~{r0}"(i32** elementtype(i32*) @f2_ptr) nounwind
+call void asm sideeffect "ldr r0, [${0:m}]\0A\09", "*m,~{r0}"(ptr elementtype(ptr) @f2_ptr) nounwind
ret void
}
- at f3_ptr = internal global i64* @f3_var, align 4
+ at f3_ptr = internal global ptr @f3_var, align 4
@f3_var = external global i64
@f3_var2 = external global i64
@@ -49,20 +49,20 @@ entry:
; CHECK: stm {{lr|r[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}}
; CHECK: adds {{lr|r[0-9]+}}, [[REG1]]
; CHECK: ldm {{lr|r[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}}
-%tmp = load i64, i64* @f3_var, align 4
-%tmp1 = load i64, i64* @f3_var2, align 4
-%0 = call i64 asm sideeffect "stm ${0:m}, ${1:M}\0A\09adds $3, $1\0A\09", "=*m,=r,1,r"(i64** elementtype(i64*) @f3_ptr, i64 %tmp, i64 %tmp1) nounwind
-store i64 %0, i64* @f3_var, align 4
-%1 = call i64 asm sideeffect "ldm ${1:m}, ${0:M}\0A\09", "=r,*m"(i64** elementtype(i64*) @f3_ptr) nounwind
-store i64 %1, i64* @f3_var, align 4
+%tmp = load i64, ptr @f3_var, align 4
+%tmp1 = load i64, ptr @f3_var2, align 4
+%0 = call i64 asm sideeffect "stm ${0:m}, ${1:M}\0A\09adds $3, $1\0A\09", "=*m,=r,1,r"(ptr elementtype(ptr) @f3_ptr, i64 %tmp, i64 %tmp1) nounwind
+store i64 %0, ptr @f3_var, align 4
+%1 = call i64 asm sideeffect "ldm ${1:m}, ${0:M}\0A\09", "=r,*m"(ptr elementtype(ptr) @f3_ptr) nounwind
+store i64 %1, ptr @f3_var, align 4
ret void
}
-define i64 @f4(i64* %val) nounwind {
+define i64 @f4(ptr %val) nounwind {
entry:
;CHECK-LABEL: f4:
;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
- %0 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [$1]", "=&r,r,*Qo"(i64* %val, i64* elementtype(i64) %val) nounwind
+ %0 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [$1]", "=&r,r,*Qo"(ptr %val, ptr elementtype(i64) %val) nounwind
ret i64 %0
}
diff --git a/llvm/test/CodeGen/ARM/arm-negative-stride.ll b/llvm/test/CodeGen/ARM/arm-negative-stride.ll
index 2ea15cf429e1d..e3134776137b0 100644
--- a/llvm/test/CodeGen/ARM/arm-negative-stride.ll
+++ b/llvm/test/CodeGen/ARM/arm-negative-stride.ll
@@ -3,7 +3,7 @@
; This loop is rewritten with an indvar which counts down, which
; frees up a register from holding the trip count.
-define void @test(i32* %P, i32 %A, i32 %i) nounwind {
+define void @test(ptr %P, i32 %A, i32 %i) nounwind {
entry:
; CHECK: str r1, [{{r.*}}, {{r.*}}, lsl #2]
icmp eq i32 %i, 0 ; <i1>:0 [#uses=1]
@@ -12,8 +12,8 @@ entry:
bb: ; preds = %bb, %entry
%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
%i_addr.09.0 = sub i32 %i, %indvar ; <i32> [#uses=1]
- %tmp2 = getelementptr i32, i32* %P, i32 %i_addr.09.0 ; <i32*> [#uses=1]
- store i32 %A, i32* %tmp2
+ %tmp2 = getelementptr i32, ptr %P, i32 %i_addr.09.0 ; <ptr> [#uses=1]
+ store i32 %A, ptr %tmp2
%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
icmp eq i32 %indvar.next, %i ; <i1>:1 [#uses=1]
br i1 %1, label %return, label %bb
@@ -25,7 +25,7 @@ return: ; preds = %bb, %entry
; This loop has a non-address use of the count-up indvar, so
; it'll remain. Now the original store uses a negative-stride address.
-define void @test_with_forced_iv(i32* %P, i32 %A, i32 %i) nounwind {
+define void @test_with_forced_iv(ptr %P, i32 %A, i32 %i) nounwind {
entry:
; CHECK: str r1, [{{r.*}}, -{{r.*}}, lsl #2]
icmp eq i32 %i, 0 ; <i1>:0 [#uses=1]
@@ -34,9 +34,9 @@ entry:
bb: ; preds = %bb, %entry
%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
%i_addr.09.0 = sub i32 %i, %indvar ; <i32> [#uses=1]
- %tmp2 = getelementptr i32, i32* %P, i32 %i_addr.09.0 ; <i32*> [#uses=1]
- store i32 %A, i32* %tmp2
- store i32 %indvar, i32* null
+ %tmp2 = getelementptr i32, ptr %P, i32 %i_addr.09.0 ; <ptr> [#uses=1]
+ store i32 %A, ptr %tmp2
+ store i32 %indvar, ptr null
%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
icmp eq i32 %indvar.next, %i ; <i1>:1 [#uses=1]
br i1 %1, label %return, label %bb
diff --git a/llvm/test/CodeGen/ARM/arm-position-independence.ll b/llvm/test/CodeGen/ARM/arm-position-independence.ll
index 4aa817f7a4814..54b525b879d92 100644
--- a/llvm/test/CodeGen/ARM/arm-position-independence.ll
+++ b/llvm/test/CodeGen/ARM/arm-position-independence.ll
@@ -26,7 +26,7 @@ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
define i32 @read() {
entry:
- %0 = load i32, i32* @a, align 4
+ %0 = load i32, ptr @a, align 4
ret i32 %0
; CHECK-LABEL: read:
@@ -76,7 +76,7 @@ entry:
define void @write(i32 %v) {
entry:
- store i32 %v, i32* @a, align 4
+ store i32 %v, ptr @a, align 4
ret void
; CHECK-LABEL: write:
@@ -126,7 +126,7 @@ entry:
define i32 @read_const() {
entry:
- %0 = load i32, i32* @b, align 4
+ %0 = load i32, ptr @b, align 4
ret i32 %0
; CHECK-LABEL: read_const:
@@ -194,9 +194,9 @@ entry:
; THUMB1_RO_PC-NEXT: .long b-([[LPC]]+4)
}
-define i32* @take_addr() {
+define ptr @take_addr() {
entry:
- ret i32* @a
+ ret ptr @a
; CHECK-LABEL: take_addr:
; ARM_RW_ABS: movw r[[REG:[0-9]]], :lower16:a
@@ -240,9 +240,9 @@ entry:
; THUMB1_RW_SB: .long a(sbrel)
}
-define i32* @take_addr_const() {
+define ptr @take_addr_const() {
entry:
- ret i32* @b
+ ret ptr @b
; CHECK-LABEL: take_addr_const:
; ARM_RO_ABS: movw r[[REG:[0-9]]], :lower16:b
@@ -300,9 +300,9 @@ entry:
; THUMB1_RO_PC-NEXT: .long b-([[LPC]]+4)
}
-define i8* @take_addr_func() {
+define ptr @take_addr_func() {
entry:
- ret i8* bitcast (i8* ()* @take_addr_func to i8*)
+ ret ptr @take_addr_func
; CHECK-LABEL: take_addr_func:
; ARM_RO_ABS: movw r[[REG:[0-9]]], :lower16:take_addr_func
@@ -360,12 +360,12 @@ entry:
; THUMB1_RO_PC-NEXT: .long take_addr_func-([[LPC]]+4)
}
-define i8* @block_addr() {
+define ptr @block_addr() {
entry:
br label %lab1
lab1:
- ret i8* blockaddress(@block_addr, %lab1)
+ ret ptr blockaddress(@block_addr, %lab1)
; CHECK-LABEL: block_addr:
diff --git a/llvm/test/CodeGen/ARM/arm-post-indexing-opt.ll b/llvm/test/CodeGen/ARM/arm-post-indexing-opt.ll
index 322c55a14909a..e16f31e9e28bf 100644
--- a/llvm/test/CodeGen/ARM/arm-post-indexing-opt.ll
+++ b/llvm/test/CodeGen/ARM/arm-post-indexing-opt.ll
@@ -4,7 +4,7 @@
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv8-unknown-linux-gnueabihf"
-define <4 x float> @test(float* %A) {
+define <4 x float> @test(ptr %A) {
; CHECK-LABEL: test:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.32 {d16, d17}, [r0]!
@@ -13,20 +13,17 @@ define <4 x float> @test(float* %A) {
; CHECK-NEXT: vld1.32 {d18, d19}, [r0]
; CHECK-NEXT: vadd.f32 q0, q8, q9
; CHECK-NEXT: bx lr
- %X.ptr = bitcast float* %A to <4 x float>*
- %X = load <4 x float>, <4 x float>* %X.ptr, align 4
- %Y.ptr.elt = getelementptr inbounds float, float* %A, i32 4
- %Y.ptr = bitcast float* %Y.ptr.elt to <4 x float>*
- %Y = load <4 x float>, <4 x float>* %Y.ptr, align 4
- %Z.ptr.elt = getelementptr inbounds float, float* %A, i32 8
- %Z.ptr = bitcast float* %Z.ptr.elt to <4 x float>*
- %Z = load <4 x float>, <4 x float>* %Z.ptr, align 4
+ %X = load <4 x float>, ptr %A, align 4
+ %Y.ptr.elt = getelementptr inbounds float, ptr %A, i32 4
+ %Y = load <4 x float>, ptr %Y.ptr.elt, align 4
+ %Z.ptr.elt = getelementptr inbounds float, ptr %A, i32 8
+ %Z = load <4 x float>, ptr %Z.ptr.elt, align 4
%tmp.sum = fadd <4 x float> %X, %Y
%sum = fadd <4 x float> %tmp.sum, %Z
ret <4 x float> %sum
}
-define <4 x float> @test_stride(float* %A) {
+define <4 x float> @test_stride(ptr %A) {
; CHECK-LABEL: test_stride:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r1, #24
@@ -36,20 +33,17 @@ define <4 x float> @test_stride(float* %A) {
; CHECK-NEXT: vld1.32 {d18, d19}, [r0]
; CHECK-NEXT: vadd.f32 q0, q8, q9
; CHECK-NEXT: bx lr
- %X.ptr = bitcast float* %A to <4 x float>*
- %X = load <4 x float>, <4 x float>* %X.ptr, align 4
- %Y.ptr.elt = getelementptr inbounds float, float* %A, i32 6
- %Y.ptr = bitcast float* %Y.ptr.elt to <4 x float>*
- %Y = load <4 x float>, <4 x float>* %Y.ptr, align 4
- %Z.ptr.elt = getelementptr inbounds float, float* %A, i32 12
- %Z.ptr = bitcast float* %Z.ptr.elt to <4 x float>*
- %Z = load <4 x float>, <4 x float>* %Z.ptr, align 4
+ %X = load <4 x float>, ptr %A, align 4
+ %Y.ptr.elt = getelementptr inbounds float, ptr %A, i32 6
+ %Y = load <4 x float>, ptr %Y.ptr.elt, align 4
+ %Z.ptr.elt = getelementptr inbounds float, ptr %A, i32 12
+ %Z = load <4 x float>, ptr %Z.ptr.elt, align 4
%tmp.sum = fadd <4 x float> %X, %Y
%sum = fadd <4 x float> %tmp.sum, %Z
ret <4 x float> %sum
}
-define <4 x float> @test_stride_mixed(float* %A) {
+define <4 x float> @test_stride_mixed(ptr %A) {
; CHECK-LABEL: test_stride_mixed:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r1, #24
@@ -59,21 +53,18 @@ define <4 x float> @test_stride_mixed(float* %A) {
; CHECK-NEXT: vld1.32 {d18, d19}, [r0]
; CHECK-NEXT: vadd.f32 q0, q8, q9
; CHECK-NEXT: bx lr
- %X.ptr = bitcast float* %A to <4 x float>*
- %X = load <4 x float>, <4 x float>* %X.ptr, align 4
- %Y.ptr.elt = getelementptr inbounds float, float* %A, i32 6
- %Y.ptr = bitcast float* %Y.ptr.elt to <4 x float>*
- %Y = load <4 x float>, <4 x float>* %Y.ptr, align 4
- %Z.ptr.elt = getelementptr inbounds float, float* %A, i32 10
- %Z.ptr = bitcast float* %Z.ptr.elt to <4 x float>*
- %Z = load <4 x float>, <4 x float>* %Z.ptr, align 4
+ %X = load <4 x float>, ptr %A, align 4
+ %Y.ptr.elt = getelementptr inbounds float, ptr %A, i32 6
+ %Y = load <4 x float>, ptr %Y.ptr.elt, align 4
+ %Z.ptr.elt = getelementptr inbounds float, ptr %A, i32 10
+ %Z = load <4 x float>, ptr %Z.ptr.elt, align 4
%tmp.sum = fadd <4 x float> %X, %Y
%sum = fadd <4 x float> %tmp.sum, %Z
ret <4 x float> %sum
}
; Refrain from using multiple stride registers
-define <4 x float> @test_stride_noop(float* %A) {
+define <4 x float> @test_stride_noop(ptr %A) {
; CHECK-LABEL: test_stride_noop:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r1, #24
@@ -84,20 +75,17 @@ define <4 x float> @test_stride_noop(float* %A) {
; CHECK-NEXT: vld1.32 {d18, d19}, [r0]
; CHECK-NEXT: vadd.f32 q0, q8, q9
; CHECK-NEXT: bx lr
- %X.ptr = bitcast float* %A to <4 x float>*
- %X = load <4 x float>, <4 x float>* %X.ptr, align 4
- %Y.ptr.elt = getelementptr inbounds float, float* %A, i32 6
- %Y.ptr = bitcast float* %Y.ptr.elt to <4 x float>*
- %Y = load <4 x float>, <4 x float>* %Y.ptr, align 4
- %Z.ptr.elt = getelementptr inbounds float, float* %A, i32 14
- %Z.ptr = bitcast float* %Z.ptr.elt to <4 x float>*
- %Z = load <4 x float>, <4 x float>* %Z.ptr, align 4
+ %X = load <4 x float>, ptr %A, align 4
+ %Y.ptr.elt = getelementptr inbounds float, ptr %A, i32 6
+ %Y = load <4 x float>, ptr %Y.ptr.elt, align 4
+ %Z.ptr.elt = getelementptr inbounds float, ptr %A, i32 14
+ %Z = load <4 x float>, ptr %Z.ptr.elt, align 4
%tmp.sum = fadd <4 x float> %X, %Y
%sum = fadd <4 x float> %tmp.sum, %Z
ret <4 x float> %sum
}
-define <4 x float> @test_positive_initial_offset(float* %A) {
+define <4 x float> @test_positive_initial_offset(ptr %A) {
; CHECK-LABEL: test_positive_initial_offset:
; CHECK: @ %bb.0:
; CHECK-NEXT: add r0, r0, #32
@@ -107,21 +95,18 @@ define <4 x float> @test_positive_initial_offset(float* %A) {
; CHECK-NEXT: vld1.32 {d18, d19}, [r0]
; CHECK-NEXT: vadd.f32 q0, q8, q9
; CHECK-NEXT: bx lr
- %X.ptr.elt = getelementptr inbounds float, float* %A, i32 8
- %X.ptr = bitcast float* %X.ptr.elt to <4 x float>*
- %X = load <4 x float>, <4 x float>* %X.ptr, align 4
- %Y.ptr.elt = getelementptr inbounds float, float* %A, i32 12
- %Y.ptr = bitcast float* %Y.ptr.elt to <4 x float>*
- %Y = load <4 x float>, <4 x float>* %Y.ptr, align 4
- %Z.ptr.elt = getelementptr inbounds float, float* %A, i32 16
- %Z.ptr = bitcast float* %Z.ptr.elt to <4 x float>*
- %Z = load <4 x float>, <4 x float>* %Z.ptr, align 4
+ %X.ptr.elt = getelementptr inbounds float, ptr %A, i32 8
+ %X = load <4 x float>, ptr %X.ptr.elt, align 4
+ %Y.ptr.elt = getelementptr inbounds float, ptr %A, i32 12
+ %Y = load <4 x float>, ptr %Y.ptr.elt, align 4
+ %Z.ptr.elt = getelementptr inbounds float, ptr %A, i32 16
+ %Z = load <4 x float>, ptr %Z.ptr.elt, align 4
%tmp.sum = fadd <4 x float> %X, %Y
%sum = fadd <4 x float> %tmp.sum, %Z
ret <4 x float> %sum
}
-define <4 x float> @test_negative_initial_offset(float* %A) {
+define <4 x float> @test_negative_initial_offset(ptr %A) {
; CHECK-LABEL: test_negative_initial_offset:
; CHECK: @ %bb.0:
; CHECK-NEXT: sub r0, r0, #64
@@ -131,15 +116,12 @@ define <4 x float> @test_negative_initial_offset(float* %A) {
; CHECK-NEXT: vld1.32 {d18, d19}, [r0]
; CHECK-NEXT: vadd.f32 q0, q8, q9
; CHECK-NEXT: bx lr
- %X.ptr.elt = getelementptr inbounds float, float* %A, i32 -16
- %X.ptr = bitcast float* %X.ptr.elt to <4 x float>*
- %X = load <4 x float>, <4 x float>* %X.ptr, align 4
- %Y.ptr.elt = getelementptr inbounds float, float* %A, i32 -12
- %Y.ptr = bitcast float* %Y.ptr.elt to <4 x float>*
- %Y = load <4 x float>, <4 x float>* %Y.ptr, align 4
- %Z.ptr.elt = getelementptr inbounds float, float* %A, i32 -8
- %Z.ptr = bitcast float* %Z.ptr.elt to <4 x float>*
- %Z = load <4 x float>, <4 x float>* %Z.ptr, align 4
+ %X.ptr.elt = getelementptr inbounds float, ptr %A, i32 -16
+ %X = load <4 x float>, ptr %X.ptr.elt, align 4
+ %Y.ptr.elt = getelementptr inbounds float, ptr %A, i32 -12
+ %Y = load <4 x float>, ptr %Y.ptr.elt, align 4
+ %Z.ptr.elt = getelementptr inbounds float, ptr %A, i32 -8
+ %Z = load <4 x float>, ptr %Z.ptr.elt, align 4
%tmp.sum = fadd <4 x float> %X, %Y
%sum = fadd <4 x float> %tmp.sum, %Z
ret <4 x float> %sum
@@ -158,9 +140,9 @@ define <4 x float> @test_global() {
; CHECK-NEXT: vld1.32 {d18, d19}, [r0]
; CHECK-NEXT: vadd.f32 q0, q8, q9
; CHECK-NEXT: bx lr
- %X = load <4 x float>, <4 x float>* bitcast (float* getelementptr inbounds ([128 x float], [128 x float]* @global_float_array, i32 0, i32 8) to <4 x float>*), align 4
- %Y = load <4 x float>, <4 x float>* bitcast (float* getelementptr inbounds ([128 x float], [128 x float]* @global_float_array, i32 0, i32 12) to <4 x float>*), align 4
- %Z = load <4 x float>, <4 x float>* bitcast (float* getelementptr inbounds ([128 x float], [128 x float]* @global_float_array, i32 0, i32 16) to <4 x float>*), align 4
+ %X = load <4 x float>, ptr getelementptr inbounds ([128 x float], ptr @global_float_array, i32 0, i32 8), align 4
+ %Y = load <4 x float>, ptr getelementptr inbounds ([128 x float], ptr @global_float_array, i32 0, i32 12), align 4
+ %Z = load <4 x float>, ptr getelementptr inbounds ([128 x float], ptr @global_float_array, i32 0, i32 16), align 4
%tmp.sum = fadd <4 x float> %X, %Y
%sum = fadd <4 x float> %tmp.sum, %Z
ret <4 x float> %sum
@@ -188,22 +170,18 @@ define <4 x float> @test_stack() {
; CHECK-NEXT: sub sp, r11, #8
; CHECK-NEXT: pop {r4, r10, r11, pc}
%array = alloca [32 x float], align 128
- %arraydecay = getelementptr inbounds [32 x float], [32 x float]* %array, i32 0, i32 0
- call void @external_function(float* %arraydecay)
- %X.ptr = bitcast [32 x float]* %array to <4 x float>*
- %X = load <4 x float>, <4 x float>* %X.ptr, align 4
- %Y.ptr.elt = getelementptr inbounds [32 x float], [32 x float]* %array, i32 0, i32 4
- %Y.ptr = bitcast float* %Y.ptr.elt to <4 x float>*
- %Y = load <4 x float>, <4 x float>* %Y.ptr, align 4
- %Z.ptr.elt = getelementptr inbounds [32 x float], [32 x float]* %array, i32 0, i32 8
- %Z.ptr = bitcast float* %Z.ptr.elt to <4 x float>*
- %Z = load <4 x float>, <4 x float>* %Z.ptr, align 4
+ call void @external_function(ptr %array)
+ %X = load <4 x float>, ptr %array, align 4
+ %Y.ptr.elt = getelementptr inbounds [32 x float], ptr %array, i32 0, i32 4
+ %Y = load <4 x float>, ptr %Y.ptr.elt, align 4
+ %Z.ptr.elt = getelementptr inbounds [32 x float], ptr %array, i32 0, i32 8
+ %Z = load <4 x float>, ptr %Z.ptr.elt, align 4
%tmp.sum = fadd <4 x float> %X, %Y
%sum = fadd <4 x float> %tmp.sum, %Z
ret <4 x float> %sum
}
-define <2 x double> @test_double(double* %A) {
+define <2 x double> @test_double(ptr %A) {
; CHECK-LABEL: test_double:
; CHECK: @ %bb.0:
; CHECK-NEXT: add r0, r0, #64
@@ -215,21 +193,18 @@ define <2 x double> @test_double(double* %A) {
; CHECK-NEXT: vadd.f64 d1, d20, d23
; CHECK-NEXT: vadd.f64 d0, d16, d22
; CHECK-NEXT: bx lr
- %X.ptr.elt = getelementptr inbounds double, double* %A, i32 8
- %X.ptr = bitcast double* %X.ptr.elt to <2 x double>*
- %X = load <2 x double>, <2 x double>* %X.ptr, align 8
- %Y.ptr.elt = getelementptr inbounds double, double* %A, i32 10
- %Y.ptr = bitcast double* %Y.ptr.elt to <2 x double>*
- %Y = load <2 x double>, <2 x double>* %Y.ptr, align 8
- %Z.ptr.elt = getelementptr inbounds double, double* %A, i32 12
- %Z.ptr = bitcast double* %Z.ptr.elt to <2 x double>*
- %Z = load <2 x double>, <2 x double>* %Z.ptr, align 8
+ %X.ptr.elt = getelementptr inbounds double, ptr %A, i32 8
+ %X = load <2 x double>, ptr %X.ptr.elt, align 8
+ %Y.ptr.elt = getelementptr inbounds double, ptr %A, i32 10
+ %Y = load <2 x double>, ptr %Y.ptr.elt, align 8
+ %Z.ptr.elt = getelementptr inbounds double, ptr %A, i32 12
+ %Z = load <2 x double>, ptr %Z.ptr.elt, align 8
%tmp.sum = fadd <2 x double> %X, %Y
%sum = fadd <2 x double> %tmp.sum, %Z
ret <2 x double> %sum
}
-define void @test_various_instructions(float* %A) {
+define void @test_various_instructions(ptr %A) {
; CHECK-LABEL: test_various_instructions:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.32 {d16, d17}, [r0]!
@@ -237,19 +212,16 @@ define void @test_various_instructions(float* %A) {
; CHECK-NEXT: vadd.f32 q8, q8, q9
; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
- %X.ptr = bitcast float* %A to i8*
- %X = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* %X.ptr, i32 1)
- %Y.ptr.elt = getelementptr inbounds float, float* %A, i32 4
- %Y.ptr = bitcast float* %Y.ptr.elt to <4 x float>*
- %Y = load <4 x float>, <4 x float>* %Y.ptr, align 4
- %Z.ptr.elt = getelementptr inbounds float, float* %A, i32 8
- %Z.ptr = bitcast float* %Z.ptr.elt to i8*
+ %X = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr %A, i32 1)
+ %Y.ptr.elt = getelementptr inbounds float, ptr %A, i32 4
+ %Y = load <4 x float>, ptr %Y.ptr.elt, align 4
+ %Z.ptr.elt = getelementptr inbounds float, ptr %A, i32 8
%Z = fadd <4 x float> %X, %Y
- tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* nonnull %Z.ptr, <4 x float> %Z, i32 4)
+ tail call void @llvm.arm.neon.vst1.p0.v4f32(ptr nonnull %Z.ptr.elt, <4 x float> %Z, i32 4)
ret void
}
-define void @test_lsr_geps(float* %a, float* %b, i32 %n) {
+define void @test_lsr_geps(ptr %a, ptr %b, i32 %n) {
; CHECK-LABEL: test_lsr_geps:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r2, #1
@@ -286,40 +258,34 @@ for.cond.cleanup:
for.body:
%lsr.iv1 = phi i32 [ 0, %for.body.preheader ], [ %lsr.iv.next2, %for.body ]
%lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
- %0 = bitcast float* %a to i8*
- %1 = bitcast float* %b to i8*
- %uglygep19 = getelementptr i8, i8* %0, i32 %lsr.iv1
- %uglygep1920 = bitcast i8* %uglygep19 to <4 x float>*
- %2 = load <4 x float>, <4 x float>* %uglygep1920, align 4
- %uglygep16 = getelementptr i8, i8* %0, i32 %lsr.iv1
- %uglygep1617 = bitcast i8* %uglygep16 to <4 x float>*
- %scevgep18 = getelementptr <4 x float>, <4 x float>* %uglygep1617, i32 1
- %3 = load <4 x float>, <4 x float>* %scevgep18, align 4
- %uglygep13 = getelementptr i8, i8* %0, i32 %lsr.iv1
- %uglygep1314 = bitcast i8* %uglygep13 to <4 x float>*
- %scevgep15 = getelementptr <4 x float>, <4 x float>* %uglygep1314, i32 2
- %4 = load <4 x float>, <4 x float>* %scevgep15, align 4
- %uglygep10 = getelementptr i8, i8* %0, i32 %lsr.iv1
- %uglygep1011 = bitcast i8* %uglygep10 to <4 x float>*
- %scevgep12 = getelementptr <4 x float>, <4 x float>* %uglygep1011, i32 3
- %5 = load <4 x float>, <4 x float>* %scevgep12, align 4
- %uglygep8 = getelementptr i8, i8* %1, i32 %lsr.iv1
- tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %uglygep8, <4 x float> %2, i32 4)
- %uglygep6 = getelementptr i8, i8* %1, i32 %lsr.iv1
- %scevgep7 = getelementptr i8, i8* %uglygep6, i32 16
- tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* nonnull %scevgep7, <4 x float> %3, i32 4)
- %uglygep4 = getelementptr i8, i8* %1, i32 %lsr.iv1
- %scevgep5 = getelementptr i8, i8* %uglygep4, i32 32
- tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* nonnull %scevgep5, <4 x float> %4, i32 4)
- %uglygep = getelementptr i8, i8* %1, i32 %lsr.iv1
- %scevgep = getelementptr i8, i8* %uglygep, i32 48
- tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* nonnull %scevgep, <4 x float> %5, i32 4)
+ %uglygep19 = getelementptr i8, ptr %a, i32 %lsr.iv1
+ %0 = load <4 x float>, ptr %uglygep19, align 4
+ %uglygep16 = getelementptr i8, ptr %a, i32 %lsr.iv1
+ %scevgep18 = getelementptr <4 x float>, ptr %uglygep16, i32 1
+ %1 = load <4 x float>, ptr %scevgep18, align 4
+ %uglygep13 = getelementptr i8, ptr %a, i32 %lsr.iv1
+ %scevgep15 = getelementptr <4 x float>, ptr %uglygep13, i32 2
+ %2 = load <4 x float>, ptr %scevgep15, align 4
+ %uglygep10 = getelementptr i8, ptr %a, i32 %lsr.iv1
+ %scevgep12 = getelementptr <4 x float>, ptr %uglygep10, i32 3
+ %3 = load <4 x float>, ptr %scevgep12, align 4
+ %uglygep8 = getelementptr i8, ptr %b, i32 %lsr.iv1
+ tail call void @llvm.arm.neon.vst1.p0.v4f32(ptr %uglygep8, <4 x float> %0, i32 4)
+ %uglygep6 = getelementptr i8, ptr %b, i32 %lsr.iv1
+ %scevgep7 = getelementptr i8, ptr %uglygep6, i32 16
+ tail call void @llvm.arm.neon.vst1.p0.v4f32(ptr nonnull %scevgep7, <4 x float> %1, i32 4)
+ %uglygep4 = getelementptr i8, ptr %b, i32 %lsr.iv1
+ %scevgep5 = getelementptr i8, ptr %uglygep4, i32 32
+ tail call void @llvm.arm.neon.vst1.p0.v4f32(ptr nonnull %scevgep5, <4 x float> %2, i32 4)
+ %uglygep = getelementptr i8, ptr %b, i32 %lsr.iv1
+ %scevgep = getelementptr i8, ptr %uglygep, i32 48
+ tail call void @llvm.arm.neon.vst1.p0.v4f32(ptr nonnull %scevgep, <4 x float> %3, i32 4)
%lsr.iv.next = add i32 %lsr.iv, -1
%lsr.iv.next2 = add nuw i32 %lsr.iv1, 64
%exitcond.not = icmp eq i32 %lsr.iv.next, 0
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
}
-declare void @external_function(float*)
-declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8*, i32) nounwind readonly
-declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind argmemonly
+declare void @external_function(ptr)
+declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr, i32) nounwind readonly
+declare void @llvm.arm.neon.vst1.p0.v4f32(ptr, <4 x float>, i32) nounwind argmemonly
diff --git a/llvm/test/CodeGen/ARM/arm-returnaddr.ll b/llvm/test/CodeGen/ARM/arm-returnaddr.ll
index 26f8c67bb15a2..0045145e319c0 100644
--- a/llvm/test/CodeGen/ARM/arm-returnaddr.ll
+++ b/llvm/test/CodeGen/ARM/arm-returnaddr.ll
@@ -5,22 +5,22 @@
; rdar://8015977
; rdar://8020118
-define i8* @rt0(i32 %x) nounwind readnone {
+define ptr @rt0(i32 %x) nounwind readnone {
entry:
; CHECK-LABEL: rt0:
; CHECK: mov r0, lr
- %0 = tail call i8* @llvm.returnaddress(i32 0)
- ret i8* %0
+ %0 = tail call ptr @llvm.returnaddress(i32 0)
+ ret ptr %0
}
-define i8* @rt2() nounwind readnone {
+define ptr @rt2() nounwind readnone {
entry:
; CHECK-LABEL: rt2:
; CHECK: ldr r[[R0:[0-9]+]], [r7]
; CHECK: ldr r0, [r[[R0]]]
; CHECK: ldr r0, [r[[R0]], #4]
- %0 = tail call i8* @llvm.returnaddress(i32 2)
- ret i8* %0
+ %0 = tail call ptr @llvm.returnaddress(i32 2)
+ ret ptr %0
}
-declare i8* @llvm.returnaddress(i32) nounwind readnone
+declare ptr @llvm.returnaddress(i32) nounwind readnone
diff --git a/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll b/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
index a4243276c70a4..f367a5626c8d3 100644
--- a/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
+++ b/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
@@ -14,7 +14,7 @@ target triple = "armv7--linux-gnueabi"
; It also post-dominates the loop body and we use to generate invalid
; restore sequence. I.e., we restored too early.
-define fastcc i8* @wrongUseOfPostDominate(i8* readonly %s, i32 %off, i8* readnone %lim) {
+define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnone %lim) {
; ENABLE-LABEL: wrongUseOfPostDominate:
; ENABLE: @ %bb.0: @ %entry
; ENABLE-NEXT: .save {r11, lr}
@@ -200,28 +200,28 @@ entry:
while.cond.preheader: ; preds = %entry
%tobool4 = icmp ne i32 %off, 0
- %cmp15 = icmp ult i8* %s, %lim
+ %cmp15 = icmp ult ptr %s, %lim
%sel66 = and i1 %tobool4, %cmp15
br i1 %sel66, label %while.body, label %if.end29
while.body: ; preds = %while.body, %while.cond.preheader
- %s.addr.08 = phi i8* [ %add.ptr, %while.body ], [ %s, %while.cond.preheader ]
+ %s.addr.08 = phi ptr [ %add.ptr, %while.body ], [ %s, %while.cond.preheader ]
%off.addr.07 = phi i32 [ %dec, %while.body ], [ %off, %while.cond.preheader ]
%dec = add nsw i32 %off.addr.07, -1
- %tmp = load i8, i8* %s.addr.08, align 1, !tbaa !2
+ %tmp = load i8, ptr %s.addr.08, align 1, !tbaa !2
%idxprom = zext i8 %tmp to i32
- %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* @skip, i32 0, i32 %idxprom
- %tmp1 = load i8, i8* %arrayidx, align 1, !tbaa !2
+ %arrayidx = getelementptr inbounds [2 x i8], ptr @skip, i32 0, i32 %idxprom
+ %tmp1 = load i8, ptr %arrayidx, align 1, !tbaa !2
%conv = zext i8 %tmp1 to i32
- %add.ptr = getelementptr inbounds i8, i8* %s.addr.08, i32 %conv
+ %add.ptr = getelementptr inbounds i8, ptr %s.addr.08, i32 %conv
%tobool = icmp ne i32 %off.addr.07, 1
- %cmp1 = icmp ult i8* %add.ptr, %lim
+ %cmp1 = icmp ult ptr %add.ptr, %lim
%sel6 = and i1 %tobool, %cmp1
br i1 %sel6, label %while.body, label %if.end29
while.cond2.outer: ; preds = %while.body24.land.rhs14_crit_edge, %while.body24, %land.rhs14.preheader, %if.then7, %entry
%off.addr.1.ph = phi i32 [ %off, %entry ], [ %inc, %land.rhs14.preheader ], [ %inc, %if.then7 ], [ %inc, %while.body24.land.rhs14_crit_edge ], [ %inc, %while.body24 ]
- %s.addr.1.ph = phi i8* [ %s, %entry ], [ %incdec.ptr, %land.rhs14.preheader ], [ %incdec.ptr, %if.then7 ], [ %lsr.iv, %while.body24.land.rhs14_crit_edge ], [ %lsr.iv, %while.body24 ]
+ %s.addr.1.ph = phi ptr [ %s, %entry ], [ %incdec.ptr, %land.rhs14.preheader ], [ %incdec.ptr, %if.then7 ], [ %lsr.iv, %while.body24.land.rhs14_crit_edge ], [ %lsr.iv, %while.body24 ]
br label %while.cond2
while.cond2: ; preds = %while.body4, %while.cond2.outer
@@ -231,15 +231,15 @@ while.cond2: ; preds = %while.body4, %while
br i1 %tobool3, label %if.end29, label %while.body4
while.body4: ; preds = %while.cond2
- %tmp2 = icmp ugt i8* %s.addr.1.ph, %lim
+ %tmp2 = icmp ugt ptr %s.addr.1.ph, %lim
br i1 %tmp2, label %if.then7, label %while.cond2
if.then7: ; preds = %while.body4
- %incdec.ptr = getelementptr inbounds i8, i8* %s.addr.1.ph, i32 -1
- %tmp3 = load i8, i8* %incdec.ptr, align 1, !tbaa !2
+ %incdec.ptr = getelementptr inbounds i8, ptr %s.addr.1.ph, i32 -1
+ %tmp3 = load i8, ptr %incdec.ptr, align 1, !tbaa !2
%conv1525 = zext i8 %tmp3 to i32
%tobool9 = icmp slt i8 %tmp3, 0
- %cmp129 = icmp ugt i8* %incdec.ptr, %lim
+ %cmp129 = icmp ugt ptr %incdec.ptr, %lim
%or.cond13 = and i1 %tobool9, %cmp129
br i1 %or.cond13, label %land.rhs14.preheader, label %while.cond2.outer
@@ -250,26 +250,26 @@ land.rhs14.preheader: ; preds = %if.then7
br i1 %or.cond27, label %while.body24.preheader, label %while.cond2.outer
while.body24.preheader: ; preds = %land.rhs14.preheader
- %scevgep = getelementptr i8, i8* %s.addr.1.ph, i32 -2
+ %scevgep = getelementptr i8, ptr %s.addr.1.ph, i32 -2
br label %while.body24
while.body24: ; preds = %while.body24.land.rhs14_crit_edge, %while.body24.preheader
- %lsr.iv = phi i8* [ %scevgep, %while.body24.preheader ], [ %scevgep34, %while.body24.land.rhs14_crit_edge ]
- %cmp12 = icmp ugt i8* %lsr.iv, %lim
+ %lsr.iv = phi ptr [ %scevgep, %while.body24.preheader ], [ %scevgep34, %while.body24.land.rhs14_crit_edge ]
+ %cmp12 = icmp ugt ptr %lsr.iv, %lim
br i1 %cmp12, label %while.body24.land.rhs14_crit_edge, label %while.cond2.outer
while.body24.land.rhs14_crit_edge: ; preds = %while.body24
- %.pre = load i8, i8* %lsr.iv, align 1, !tbaa !2
+ %.pre = load i8, ptr %lsr.iv, align 1, !tbaa !2
%cmp16 = icmp slt i8 %.pre, 0
%conv15 = zext i8 %.pre to i32
%cmp20 = icmp ult i32 %conv15, 192
%or.cond = and i1 %cmp16, %cmp20
- %scevgep34 = getelementptr i8, i8* %lsr.iv, i32 -1
+ %scevgep34 = getelementptr i8, ptr %lsr.iv, i32 -1
br i1 %or.cond, label %while.body24, label %while.cond2.outer
if.end29: ; preds = %while.cond2, %while.body, %while.cond.preheader
- %s.addr.3 = phi i8* [ %s, %while.cond.preheader ], [ %add.ptr, %while.body ], [ %s.addr.1.ph, %while.cond2 ]
- ret i8* %s.addr.3
+ %s.addr.3 = phi ptr [ %s, %while.cond.preheader ], [ %add.ptr, %while.body ], [ %s.addr.1.ph, %while.cond2 ]
+ ret ptr %s.addr.3
}
!llvm.module.flags = !{!0, !1}
diff --git a/llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll b/llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
index fa94812509534..7b221557f71f1 100644
--- a/llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
+++ b/llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
@@ -129,8 +129,8 @@ define i32 @foo(i32 %a, i32 %b) "frame-pointer"="all" {
br i1 %tmp2, label %true, label %false
true:
- store i32 %a, i32* %tmp, align 4
- %tmp4 = call i32 @doSomething(i32 0, i32* %tmp)
+ store i32 %a, ptr %tmp, align 4
+ %tmp4 = call i32 @doSomething(i32 0, ptr %tmp)
br label %false
false:
@@ -139,7 +139,7 @@ false:
}
; Function Attrs: optsize
-declare i32 @doSomething(i32, i32*)
+declare i32 @doSomething(i32, ptr)
; Check that we do not perform the restore inside the loop whereas the save
@@ -1499,7 +1499,7 @@ for.body: ; preds = %for.body, %entry
%sum.03 = phi i32 [ 0, %if.then ], [ %add, %for.body ]
%call = tail call i32 asm sideeffect "mov $0, #1", "=r,~{r4}"()
%add = add nsw i32 %call, %sum.03
- store i32 %add, i32* %ptr
+ store i32 %add, ptr %ptr
br label %for.body
if.end:
@@ -1521,7 +1521,7 @@ for.body: ; preds = %for.body, %entry
%sum.03 = phi i32 [ 0, %if.then ], [ %add, %body1 ], [ 1, %body2]
%call = tail call i32 asm "mov $0, #0", "=r,~{r4}"()
%add = add nsw i32 %call, %sum.03
- store i32 %add, i32* %ptr
+ store i32 %add, ptr %ptr
br i1 undef, label %body1, label %body2
body1:
@@ -1705,21 +1705,19 @@ body: ; preds = %entry
br i1 undef, label %loop2a, label %end
loop1: ; preds = %loop2a, %loop2b
- %var.phi = phi i32* [ %next.phi, %loop2b ], [ %var, %loop2a ]
- %next.phi = phi i32* [ %next.load, %loop2b ], [ %next.var, %loop2a ]
- %0 = icmp eq i32* %var, null
- %next.load = load i32*, i32** undef
+ %var.phi = phi ptr [ %next.phi, %loop2b ], [ %var, %loop2a ]
+ %next.phi = phi ptr [ %next.load, %loop2b ], [ %next.var, %loop2a ]
+ %0 = icmp eq ptr %var, null
+ %next.load = load ptr, ptr undef
br i1 %0, label %loop2a, label %loop2b
loop2a: ; preds = %loop1, %body, %entry
- %var = phi i32* [ null, %body ], [ null, %entry ], [ %next.phi, %loop1 ]
- %next.var = phi i32* [ undef, %body ], [ null, %entry ], [ %next.load, %loop1 ]
+ %var = phi ptr [ null, %body ], [ null, %entry ], [ %next.phi, %loop1 ]
+ %next.var = phi ptr [ undef, %body ], [ null, %entry ], [ %next.load, %loop1 ]
br label %loop1
loop2b: ; preds = %loop1
- %gep1 = bitcast i32* %var.phi to i32*
- %next.ptr = bitcast i32* %gep1 to i32**
- store i32* %next.phi, i32** %next.ptr
+ store ptr %next.phi, ptr %var.phi
br label %loop1
end:
diff --git a/llvm/test/CodeGen/ARM/arm-storebytesmerge.ll b/llvm/test/CodeGen/ARM/arm-storebytesmerge.ll
index c7bd79e7ca1d2..20448570502c0 100644
--- a/llvm/test/CodeGen/ARM/arm-storebytesmerge.ll
+++ b/llvm/test/CodeGen/ARM/arm-storebytesmerge.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv7em-arm-none-eabi %s -o - | FileCheck %s
-define arm_aapcs_vfpcc void @test(i8* %v50) {
+define arm_aapcs_vfpcc void @test(ptr %v50) {
; CHECK-LABEL: test:
; CHECK: @ %bb.0:
; CHECK-NEXT: movw r1, #65534
@@ -94,242 +94,242 @@ define arm_aapcs_vfpcc void @test(i8* %v50) {
; CHECK-NEXT: movt r1, #36236
; CHECK-NEXT: str.w r1, [r0, #394]
; CHECK-NEXT: bx lr
- %v190 = getelementptr inbounds i8, i8* %v50, i32 394
- store i8 -118, i8* %v190, align 1
- %v191 = getelementptr inbounds i8, i8* %v50, i32 395
- store i8 -117, i8* %v191, align 1
- %v192 = getelementptr inbounds i8, i8* %v50, i32 396
- store i8 -116, i8* %v192, align 1
- %v193 = getelementptr inbounds i8, i8* %v50, i32 397
- store i8 -115, i8* %v193, align 1
- %v194 = getelementptr inbounds i8, i8* %v50, i32 398
- store i8 -114, i8* %v194, align 1
- %v195 = getelementptr inbounds i8, i8* %v50, i32 399
- store i8 -113, i8* %v195, align 1
- %v196 = getelementptr inbounds i8, i8* %v50, i32 400
- store i8 -112, i8* %v196, align 1
- %v197 = getelementptr inbounds i8, i8* %v50, i32 401
- store i8 -111, i8* %v197, align 1
- %v198 = getelementptr inbounds i8, i8* %v50, i32 402
- store i8 -110, i8* %v198, align 1
- %v199 = getelementptr inbounds i8, i8* %v50, i32 403
- store i8 -109, i8* %v199, align 1
- %v200 = getelementptr inbounds i8, i8* %v50, i32 404
- store i8 -108, i8* %v200, align 1
- %v201 = getelementptr inbounds i8, i8* %v50, i32 405
- store i8 -107, i8* %v201, align 1
- %v202 = getelementptr inbounds i8, i8* %v50, i32 406
- store i8 -106, i8* %v202, align 1
- %v203 = getelementptr inbounds i8, i8* %v50, i32 407
- store i8 -105, i8* %v203, align 1
- %v204 = getelementptr inbounds i8, i8* %v50, i32 408
- store i8 -104, i8* %v204, align 1
- %v205 = getelementptr inbounds i8, i8* %v50, i32 409
- store i8 -103, i8* %v205, align 1
- %v206 = getelementptr inbounds i8, i8* %v50, i32 410
- store i8 -102, i8* %v206, align 1
- %v207 = getelementptr inbounds i8, i8* %v50, i32 411
- store i8 -101, i8* %v207, align 1
- %v208 = getelementptr inbounds i8, i8* %v50, i32 412
- store i8 -100, i8* %v208, align 1
- %v209 = getelementptr inbounds i8, i8* %v50, i32 413
- store i8 -99, i8* %v209, align 1
- %v210 = getelementptr inbounds i8, i8* %v50, i32 414
- store i8 -98, i8* %v210, align 1
- %v211 = getelementptr inbounds i8, i8* %v50, i32 415
- store i8 -97, i8* %v211, align 1
- %v212 = getelementptr inbounds i8, i8* %v50, i32 416
- store i8 -96, i8* %v212, align 1
- %v213 = getelementptr inbounds i8, i8* %v50, i32 417
- store i8 -95, i8* %v213, align 1
- %v214 = getelementptr inbounds i8, i8* %v50, i32 418
- store i8 -94, i8* %v214, align 1
- %v215 = getelementptr inbounds i8, i8* %v50, i32 419
- store i8 -93, i8* %v215, align 1
- %v216 = getelementptr inbounds i8, i8* %v50, i32 420
- store i8 -92, i8* %v216, align 1
- %v217 = getelementptr inbounds i8, i8* %v50, i32 421
- store i8 -91, i8* %v217, align 1
- %v218 = getelementptr inbounds i8, i8* %v50, i32 422
- store i8 -90, i8* %v218, align 1
- %v219 = getelementptr inbounds i8, i8* %v50, i32 423
- store i8 -89, i8* %v219, align 1
- %v220 = getelementptr inbounds i8, i8* %v50, i32 424
- store i8 -88, i8* %v220, align 1
- %v221 = getelementptr inbounds i8, i8* %v50, i32 425
- store i8 -87, i8* %v221, align 1
- %v222 = getelementptr inbounds i8, i8* %v50, i32 426
- store i8 -86, i8* %v222, align 1
- %v223 = getelementptr inbounds i8, i8* %v50, i32 427
- store i8 -85, i8* %v223, align 1
- %v224 = getelementptr inbounds i8, i8* %v50, i32 428
- store i8 -84, i8* %v224, align 1
- %v225 = getelementptr inbounds i8, i8* %v50, i32 429
- store i8 -83, i8* %v225, align 1
- %v226 = getelementptr inbounds i8, i8* %v50, i32 430
- store i8 -82, i8* %v226, align 1
- %v227 = getelementptr inbounds i8, i8* %v50, i32 431
- store i8 -81, i8* %v227, align 1
- %v228 = getelementptr inbounds i8, i8* %v50, i32 432
- store i8 -80, i8* %v228, align 1
- %v229 = getelementptr inbounds i8, i8* %v50, i32 433
- store i8 -79, i8* %v229, align 1
- %v230 = getelementptr inbounds i8, i8* %v50, i32 434
- store i8 -78, i8* %v230, align 1
- %v231 = getelementptr inbounds i8, i8* %v50, i32 435
- store i8 -77, i8* %v231, align 1
- %v232 = getelementptr inbounds i8, i8* %v50, i32 436
- store i8 -76, i8* %v232, align 1
- %v233 = getelementptr inbounds i8, i8* %v50, i32 437
- store i8 -75, i8* %v233, align 1
- %v234 = getelementptr inbounds i8, i8* %v50, i32 438
- store i8 -74, i8* %v234, align 1
- %v235 = getelementptr inbounds i8, i8* %v50, i32 439
- store i8 -73, i8* %v235, align 1
- %v236 = getelementptr inbounds i8, i8* %v50, i32 440
- store i8 -72, i8* %v236, align 1
- %v237 = getelementptr inbounds i8, i8* %v50, i32 441
- store i8 -71, i8* %v237, align 1
- %v238 = getelementptr inbounds i8, i8* %v50, i32 442
- store i8 -70, i8* %v238, align 1
- %v239 = getelementptr inbounds i8, i8* %v50, i32 443
- store i8 -69, i8* %v239, align 1
- %v240 = getelementptr inbounds i8, i8* %v50, i32 444
- store i8 -68, i8* %v240, align 1
- %v241 = getelementptr inbounds i8, i8* %v50, i32 445
- store i8 -67, i8* %v241, align 1
- %v242 = getelementptr inbounds i8, i8* %v50, i32 446
- store i8 -66, i8* %v242, align 1
- %v243 = getelementptr inbounds i8, i8* %v50, i32 447
- store i8 -65, i8* %v243, align 1
- %v244 = getelementptr inbounds i8, i8* %v50, i32 448
- store i8 -64, i8* %v244, align 1
- %v245 = getelementptr inbounds i8, i8* %v50, i32 449
- store i8 -63, i8* %v245, align 1
- %v246 = getelementptr inbounds i8, i8* %v50, i32 450
- store i8 -62, i8* %v246, align 1
- %v247 = getelementptr inbounds i8, i8* %v50, i32 451
- store i8 -61, i8* %v247, align 1
- %v248 = getelementptr inbounds i8, i8* %v50, i32 452
- store i8 -60, i8* %v248, align 1
- %v249 = getelementptr inbounds i8, i8* %v50, i32 453
- store i8 -59, i8* %v249, align 1
- %v250 = getelementptr inbounds i8, i8* %v50, i32 454
- store i8 -58, i8* %v250, align 1
- %v251 = getelementptr inbounds i8, i8* %v50, i32 455
- store i8 -57, i8* %v251, align 1
- %v252 = getelementptr inbounds i8, i8* %v50, i32 456
- store i8 -56, i8* %v252, align 1
- %v253 = getelementptr inbounds i8, i8* %v50, i32 457
- store i8 -55, i8* %v253, align 1
- %v254 = getelementptr inbounds i8, i8* %v50, i32 458
- store i8 -54, i8* %v254, align 1
- %v255 = getelementptr inbounds i8, i8* %v50, i32 459
- store i8 -53, i8* %v255, align 1
- %v256 = getelementptr inbounds i8, i8* %v50, i32 460
- store i8 -52, i8* %v256, align 1
- %v257 = getelementptr inbounds i8, i8* %v50, i32 461
- store i8 -51, i8* %v257, align 1
- %v258 = getelementptr inbounds i8, i8* %v50, i32 462
- store i8 -50, i8* %v258, align 1
- %v259 = getelementptr inbounds i8, i8* %v50, i32 463
- store i8 -49, i8* %v259, align 1
- %v260 = getelementptr inbounds i8, i8* %v50, i32 464
- store i8 -48, i8* %v260, align 1
- %v261 = getelementptr inbounds i8, i8* %v50, i32 465
- store i8 -47, i8* %v261, align 1
- %v262 = getelementptr inbounds i8, i8* %v50, i32 466
- store i8 -46, i8* %v262, align 1
- %v263 = getelementptr inbounds i8, i8* %v50, i32 467
- store i8 -45, i8* %v263, align 1
- %v264 = getelementptr inbounds i8, i8* %v50, i32 468
- store i8 -44, i8* %v264, align 1
- %v265 = getelementptr inbounds i8, i8* %v50, i32 469
- store i8 -43, i8* %v265, align 1
- %v266 = getelementptr inbounds i8, i8* %v50, i32 470
- store i8 -42, i8* %v266, align 1
- %v267 = getelementptr inbounds i8, i8* %v50, i32 471
- store i8 -41, i8* %v267, align 1
- %v268 = getelementptr inbounds i8, i8* %v50, i32 472
- store i8 -40, i8* %v268, align 1
- %v269 = getelementptr inbounds i8, i8* %v50, i32 473
- store i8 -39, i8* %v269, align 1
- %v270 = getelementptr inbounds i8, i8* %v50, i32 474
- store i8 -38, i8* %v270, align 1
- %v271 = getelementptr inbounds i8, i8* %v50, i32 475
- store i8 -37, i8* %v271, align 1
- %v272 = getelementptr inbounds i8, i8* %v50, i32 476
- store i8 -36, i8* %v272, align 1
- %v273 = getelementptr inbounds i8, i8* %v50, i32 477
- store i8 -35, i8* %v273, align 1
- %v274 = getelementptr inbounds i8, i8* %v50, i32 478
- store i8 -34, i8* %v274, align 1
- %v275 = getelementptr inbounds i8, i8* %v50, i32 479
- store i8 -33, i8* %v275, align 1
- %v276 = getelementptr inbounds i8, i8* %v50, i32 480
- store i8 -32, i8* %v276, align 1
- %v277 = getelementptr inbounds i8, i8* %v50, i32 481
- store i8 -31, i8* %v277, align 1
- %v278 = getelementptr inbounds i8, i8* %v50, i32 482
- store i8 -30, i8* %v278, align 1
- %v279 = getelementptr inbounds i8, i8* %v50, i32 483
- store i8 -29, i8* %v279, align 1
- %v280 = getelementptr inbounds i8, i8* %v50, i32 484
- store i8 -28, i8* %v280, align 1
- %v281 = getelementptr inbounds i8, i8* %v50, i32 485
- store i8 -27, i8* %v281, align 1
- %v282 = getelementptr inbounds i8, i8* %v50, i32 486
- store i8 -26, i8* %v282, align 1
- %v283 = getelementptr inbounds i8, i8* %v50, i32 487
- store i8 -25, i8* %v283, align 1
- %v284 = getelementptr inbounds i8, i8* %v50, i32 488
- store i8 -24, i8* %v284, align 1
- %v285 = getelementptr inbounds i8, i8* %v50, i32 489
- store i8 -23, i8* %v285, align 1
- %v286 = getelementptr inbounds i8, i8* %v50, i32 490
- store i8 -22, i8* %v286, align 1
- %v287 = getelementptr inbounds i8, i8* %v50, i32 491
- store i8 -21, i8* %v287, align 1
- %v288 = getelementptr inbounds i8, i8* %v50, i32 492
- store i8 -20, i8* %v288, align 1
- %v289 = getelementptr inbounds i8, i8* %v50, i32 493
- store i8 -19, i8* %v289, align 1
- %v290 = getelementptr inbounds i8, i8* %v50, i32 494
- store i8 -18, i8* %v290, align 1
- %v291 = getelementptr inbounds i8, i8* %v50, i32 495
- store i8 -17, i8* %v291, align 1
- %v292 = getelementptr inbounds i8, i8* %v50, i32 496
- store i8 -16, i8* %v292, align 1
- %v293 = getelementptr inbounds i8, i8* %v50, i32 497
- store i8 -15, i8* %v293, align 1
- %v294 = getelementptr inbounds i8, i8* %v50, i32 498
- store i8 -14, i8* %v294, align 1
- %v295 = getelementptr inbounds i8, i8* %v50, i32 499
- store i8 -13, i8* %v295, align 1
- %v296 = getelementptr inbounds i8, i8* %v50, i32 500
- store i8 -12, i8* %v296, align 1
- %v297 = getelementptr inbounds i8, i8* %v50, i32 501
- store i8 -11, i8* %v297, align 1
- %v298 = getelementptr inbounds i8, i8* %v50, i32 502
- store i8 -10, i8* %v298, align 1
- %v299 = getelementptr inbounds i8, i8* %v50, i32 503
- store i8 -9, i8* %v299, align 1
- %v300 = getelementptr inbounds i8, i8* %v50, i32 504
- store i8 -8, i8* %v300, align 1
- %v301 = getelementptr inbounds i8, i8* %v50, i32 505
- store i8 -7, i8* %v301, align 1
- %v302 = getelementptr inbounds i8, i8* %v50, i32 506
- store i8 -6, i8* %v302, align 1
- %v303 = getelementptr inbounds i8, i8* %v50, i32 507
- store i8 -5, i8* %v303, align 1
- %v304 = getelementptr inbounds i8, i8* %v50, i32 508
- store i8 -4, i8* %v304, align 1
- %v305 = getelementptr inbounds i8, i8* %v50, i32 509
- store i8 -3, i8* %v305, align 1
- %v306 = getelementptr inbounds i8, i8* %v50, i32 510
- store i8 -2, i8* %v306, align 1
- %v307 = getelementptr inbounds i8, i8* %v50, i32 511
- store i8 -1, i8* %v307, align 1
+ %v190 = getelementptr inbounds i8, ptr %v50, i32 394
+ store i8 -118, ptr %v190, align 1
+ %v191 = getelementptr inbounds i8, ptr %v50, i32 395
+ store i8 -117, ptr %v191, align 1
+ %v192 = getelementptr inbounds i8, ptr %v50, i32 396
+ store i8 -116, ptr %v192, align 1
+ %v193 = getelementptr inbounds i8, ptr %v50, i32 397
+ store i8 -115, ptr %v193, align 1
+ %v194 = getelementptr inbounds i8, ptr %v50, i32 398
+ store i8 -114, ptr %v194, align 1
+ %v195 = getelementptr inbounds i8, ptr %v50, i32 399
+ store i8 -113, ptr %v195, align 1
+ %v196 = getelementptr inbounds i8, ptr %v50, i32 400
+ store i8 -112, ptr %v196, align 1
+ %v197 = getelementptr inbounds i8, ptr %v50, i32 401
+ store i8 -111, ptr %v197, align 1
+ %v198 = getelementptr inbounds i8, ptr %v50, i32 402
+ store i8 -110, ptr %v198, align 1
+ %v199 = getelementptr inbounds i8, ptr %v50, i32 403
+ store i8 -109, ptr %v199, align 1
+ %v200 = getelementptr inbounds i8, ptr %v50, i32 404
+ store i8 -108, ptr %v200, align 1
+ %v201 = getelementptr inbounds i8, ptr %v50, i32 405
+ store i8 -107, ptr %v201, align 1
+ %v202 = getelementptr inbounds i8, ptr %v50, i32 406
+ store i8 -106, ptr %v202, align 1
+ %v203 = getelementptr inbounds i8, ptr %v50, i32 407
+ store i8 -105, ptr %v203, align 1
+ %v204 = getelementptr inbounds i8, ptr %v50, i32 408
+ store i8 -104, ptr %v204, align 1
+ %v205 = getelementptr inbounds i8, ptr %v50, i32 409
+ store i8 -103, ptr %v205, align 1
+ %v206 = getelementptr inbounds i8, ptr %v50, i32 410
+ store i8 -102, ptr %v206, align 1
+ %v207 = getelementptr inbounds i8, ptr %v50, i32 411
+ store i8 -101, ptr %v207, align 1
+ %v208 = getelementptr inbounds i8, ptr %v50, i32 412
+ store i8 -100, ptr %v208, align 1
+ %v209 = getelementptr inbounds i8, ptr %v50, i32 413
+ store i8 -99, ptr %v209, align 1
+ %v210 = getelementptr inbounds i8, ptr %v50, i32 414
+ store i8 -98, ptr %v210, align 1
+ %v211 = getelementptr inbounds i8, ptr %v50, i32 415
+ store i8 -97, ptr %v211, align 1
+ %v212 = getelementptr inbounds i8, ptr %v50, i32 416
+ store i8 -96, ptr %v212, align 1
+ %v213 = getelementptr inbounds i8, ptr %v50, i32 417
+ store i8 -95, ptr %v213, align 1
+ %v214 = getelementptr inbounds i8, ptr %v50, i32 418
+ store i8 -94, ptr %v214, align 1
+ %v215 = getelementptr inbounds i8, ptr %v50, i32 419
+ store i8 -93, ptr %v215, align 1
+ %v216 = getelementptr inbounds i8, ptr %v50, i32 420
+ store i8 -92, ptr %v216, align 1
+ %v217 = getelementptr inbounds i8, ptr %v50, i32 421
+ store i8 -91, ptr %v217, align 1
+ %v218 = getelementptr inbounds i8, ptr %v50, i32 422
+ store i8 -90, ptr %v218, align 1
+ %v219 = getelementptr inbounds i8, ptr %v50, i32 423
+ store i8 -89, ptr %v219, align 1
+ %v220 = getelementptr inbounds i8, ptr %v50, i32 424
+ store i8 -88, ptr %v220, align 1
+ %v221 = getelementptr inbounds i8, ptr %v50, i32 425
+ store i8 -87, ptr %v221, align 1
+ %v222 = getelementptr inbounds i8, ptr %v50, i32 426
+ store i8 -86, ptr %v222, align 1
+ %v223 = getelementptr inbounds i8, ptr %v50, i32 427
+ store i8 -85, ptr %v223, align 1
+ %v224 = getelementptr inbounds i8, ptr %v50, i32 428
+ store i8 -84, ptr %v224, align 1
+ %v225 = getelementptr inbounds i8, ptr %v50, i32 429
+ store i8 -83, ptr %v225, align 1
+ %v226 = getelementptr inbounds i8, ptr %v50, i32 430
+ store i8 -82, ptr %v226, align 1
+ %v227 = getelementptr inbounds i8, ptr %v50, i32 431
+ store i8 -81, ptr %v227, align 1
+ %v228 = getelementptr inbounds i8, ptr %v50, i32 432
+ store i8 -80, ptr %v228, align 1
+ %v229 = getelementptr inbounds i8, ptr %v50, i32 433
+ store i8 -79, ptr %v229, align 1
+ %v230 = getelementptr inbounds i8, ptr %v50, i32 434
+ store i8 -78, ptr %v230, align 1
+ %v231 = getelementptr inbounds i8, ptr %v50, i32 435
+ store i8 -77, ptr %v231, align 1
+ %v232 = getelementptr inbounds i8, ptr %v50, i32 436
+ store i8 -76, ptr %v232, align 1
+ %v233 = getelementptr inbounds i8, ptr %v50, i32 437
+ store i8 -75, ptr %v233, align 1
+ %v234 = getelementptr inbounds i8, ptr %v50, i32 438
+ store i8 -74, ptr %v234, align 1
+ %v235 = getelementptr inbounds i8, ptr %v50, i32 439
+ store i8 -73, ptr %v235, align 1
+ %v236 = getelementptr inbounds i8, ptr %v50, i32 440
+ store i8 -72, ptr %v236, align 1
+ %v237 = getelementptr inbounds i8, ptr %v50, i32 441
+ store i8 -71, ptr %v237, align 1
+ %v238 = getelementptr inbounds i8, ptr %v50, i32 442
+ store i8 -70, ptr %v238, align 1
+ %v239 = getelementptr inbounds i8, ptr %v50, i32 443
+ store i8 -69, ptr %v239, align 1
+ %v240 = getelementptr inbounds i8, ptr %v50, i32 444
+ store i8 -68, ptr %v240, align 1
+ %v241 = getelementptr inbounds i8, ptr %v50, i32 445
+ store i8 -67, ptr %v241, align 1
+ %v242 = getelementptr inbounds i8, ptr %v50, i32 446
+ store i8 -66, ptr %v242, align 1
+ %v243 = getelementptr inbounds i8, ptr %v50, i32 447
+ store i8 -65, ptr %v243, align 1
+ %v244 = getelementptr inbounds i8, ptr %v50, i32 448
+ store i8 -64, ptr %v244, align 1
+ %v245 = getelementptr inbounds i8, ptr %v50, i32 449
+ store i8 -63, ptr %v245, align 1
+ %v246 = getelementptr inbounds i8, ptr %v50, i32 450
+ store i8 -62, ptr %v246, align 1
+ %v247 = getelementptr inbounds i8, ptr %v50, i32 451
+ store i8 -61, ptr %v247, align 1
+ %v248 = getelementptr inbounds i8, ptr %v50, i32 452
+ store i8 -60, ptr %v248, align 1
+ %v249 = getelementptr inbounds i8, ptr %v50, i32 453
+ store i8 -59, ptr %v249, align 1
+ %v250 = getelementptr inbounds i8, ptr %v50, i32 454
+ store i8 -58, ptr %v250, align 1
+ %v251 = getelementptr inbounds i8, ptr %v50, i32 455
+ store i8 -57, ptr %v251, align 1
+ %v252 = getelementptr inbounds i8, ptr %v50, i32 456
+ store i8 -56, ptr %v252, align 1
+ %v253 = getelementptr inbounds i8, ptr %v50, i32 457
+ store i8 -55, ptr %v253, align 1
+ %v254 = getelementptr inbounds i8, ptr %v50, i32 458
+ store i8 -54, ptr %v254, align 1
+ %v255 = getelementptr inbounds i8, ptr %v50, i32 459
+ store i8 -53, ptr %v255, align 1
+ %v256 = getelementptr inbounds i8, ptr %v50, i32 460
+ store i8 -52, ptr %v256, align 1
+ %v257 = getelementptr inbounds i8, ptr %v50, i32 461
+ store i8 -51, ptr %v257, align 1
+ %v258 = getelementptr inbounds i8, ptr %v50, i32 462
+ store i8 -50, ptr %v258, align 1
+ %v259 = getelementptr inbounds i8, ptr %v50, i32 463
+ store i8 -49, ptr %v259, align 1
+ %v260 = getelementptr inbounds i8, ptr %v50, i32 464
+ store i8 -48, ptr %v260, align 1
+ %v261 = getelementptr inbounds i8, ptr %v50, i32 465
+ store i8 -47, ptr %v261, align 1
+ %v262 = getelementptr inbounds i8, ptr %v50, i32 466
+ store i8 -46, ptr %v262, align 1
+ %v263 = getelementptr inbounds i8, ptr %v50, i32 467
+ store i8 -45, ptr %v263, align 1
+ %v264 = getelementptr inbounds i8, ptr %v50, i32 468
+ store i8 -44, ptr %v264, align 1
+ %v265 = getelementptr inbounds i8, ptr %v50, i32 469
+ store i8 -43, ptr %v265, align 1
+ %v266 = getelementptr inbounds i8, ptr %v50, i32 470
+ store i8 -42, ptr %v266, align 1
+ %v267 = getelementptr inbounds i8, ptr %v50, i32 471
+ store i8 -41, ptr %v267, align 1
+ %v268 = getelementptr inbounds i8, ptr %v50, i32 472
+ store i8 -40, ptr %v268, align 1
+ %v269 = getelementptr inbounds i8, ptr %v50, i32 473
+ store i8 -39, ptr %v269, align 1
+ %v270 = getelementptr inbounds i8, ptr %v50, i32 474
+ store i8 -38, ptr %v270, align 1
+ %v271 = getelementptr inbounds i8, ptr %v50, i32 475
+ store i8 -37, ptr %v271, align 1
+ %v272 = getelementptr inbounds i8, ptr %v50, i32 476
+ store i8 -36, ptr %v272, align 1
+ %v273 = getelementptr inbounds i8, ptr %v50, i32 477
+ store i8 -35, ptr %v273, align 1
+ %v274 = getelementptr inbounds i8, ptr %v50, i32 478
+ store i8 -34, ptr %v274, align 1
+ %v275 = getelementptr inbounds i8, ptr %v50, i32 479
+ store i8 -33, ptr %v275, align 1
+ %v276 = getelementptr inbounds i8, ptr %v50, i32 480
+ store i8 -32, ptr %v276, align 1
+ %v277 = getelementptr inbounds i8, ptr %v50, i32 481
+ store i8 -31, ptr %v277, align 1
+ %v278 = getelementptr inbounds i8, ptr %v50, i32 482
+ store i8 -30, ptr %v278, align 1
+ %v279 = getelementptr inbounds i8, ptr %v50, i32 483
+ store i8 -29, ptr %v279, align 1
+ %v280 = getelementptr inbounds i8, ptr %v50, i32 484
+ store i8 -28, ptr %v280, align 1
+ %v281 = getelementptr inbounds i8, ptr %v50, i32 485
+ store i8 -27, ptr %v281, align 1
+ %v282 = getelementptr inbounds i8, ptr %v50, i32 486
+ store i8 -26, ptr %v282, align 1
+ %v283 = getelementptr inbounds i8, ptr %v50, i32 487
+ store i8 -25, ptr %v283, align 1
+ %v284 = getelementptr inbounds i8, ptr %v50, i32 488
+ store i8 -24, ptr %v284, align 1
+ %v285 = getelementptr inbounds i8, ptr %v50, i32 489
+ store i8 -23, ptr %v285, align 1
+ %v286 = getelementptr inbounds i8, ptr %v50, i32 490
+ store i8 -22, ptr %v286, align 1
+ %v287 = getelementptr inbounds i8, ptr %v50, i32 491
+ store i8 -21, ptr %v287, align 1
+ %v288 = getelementptr inbounds i8, ptr %v50, i32 492
+ store i8 -20, ptr %v288, align 1
+ %v289 = getelementptr inbounds i8, ptr %v50, i32 493
+ store i8 -19, ptr %v289, align 1
+ %v290 = getelementptr inbounds i8, ptr %v50, i32 494
+ store i8 -18, ptr %v290, align 1
+ %v291 = getelementptr inbounds i8, ptr %v50, i32 495
+ store i8 -17, ptr %v291, align 1
+ %v292 = getelementptr inbounds i8, ptr %v50, i32 496
+ store i8 -16, ptr %v292, align 1
+ %v293 = getelementptr inbounds i8, ptr %v50, i32 497
+ store i8 -15, ptr %v293, align 1
+ %v294 = getelementptr inbounds i8, ptr %v50, i32 498
+ store i8 -14, ptr %v294, align 1
+ %v295 = getelementptr inbounds i8, ptr %v50, i32 499
+ store i8 -13, ptr %v295, align 1
+ %v296 = getelementptr inbounds i8, ptr %v50, i32 500
+ store i8 -12, ptr %v296, align 1
+ %v297 = getelementptr inbounds i8, ptr %v50, i32 501
+ store i8 -11, ptr %v297, align 1
+ %v298 = getelementptr inbounds i8, ptr %v50, i32 502
+ store i8 -10, ptr %v298, align 1
+ %v299 = getelementptr inbounds i8, ptr %v50, i32 503
+ store i8 -9, ptr %v299, align 1
+ %v300 = getelementptr inbounds i8, ptr %v50, i32 504
+ store i8 -8, ptr %v300, align 1
+ %v301 = getelementptr inbounds i8, ptr %v50, i32 505
+ store i8 -7, ptr %v301, align 1
+ %v302 = getelementptr inbounds i8, ptr %v50, i32 506
+ store i8 -6, ptr %v302, align 1
+ %v303 = getelementptr inbounds i8, ptr %v50, i32 507
+ store i8 -5, ptr %v303, align 1
+ %v304 = getelementptr inbounds i8, ptr %v50, i32 508
+ store i8 -4, ptr %v304, align 1
+ %v305 = getelementptr inbounds i8, ptr %v50, i32 509
+ store i8 -3, ptr %v305, align 1
+ %v306 = getelementptr inbounds i8, ptr %v50, i32 510
+ store i8 -2, ptr %v306, align 1
+ %v307 = getelementptr inbounds i8, ptr %v50, i32 511
+ store i8 -1, ptr %v307, align 1
ret void
}
diff --git a/llvm/test/CodeGen/ARM/arm-ttype-target2.ll b/llvm/test/CodeGen/ARM/arm-ttype-target2.ll
index 8db6a1d696f19..9f50b5727dfed 100644
--- a/llvm/test/CodeGen/ARM/arm-ttype-target2.ll
+++ b/llvm/test/CodeGen/ARM/arm-ttype-target2.ll
@@ -1,27 +1,27 @@
; RUN: llc -mtriple=armv7-none-linux-gnueabi -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
- at _ZTVN10__cxxabiv117__class_type_infoE = external global i8*
+ at _ZTVN10__cxxabiv117__class_type_infoE = external global ptr
@_ZTS3Foo = linkonce_odr constant [5 x i8] c"3Foo\00"
- at _ZTI3Foo = linkonce_odr unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i32 2) to i8*), i8* getelementptr inbounds ([5 x i8], [5 x i8]* @_ZTS3Foo, i32 0, i32 0) }
+ at _ZTI3Foo = linkonce_odr unnamed_addr constant { ptr, ptr } { ptr getelementptr inbounds (ptr, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i32 2), ptr @_ZTS3Foo }
-define i32 @main() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+define i32 @main() personality ptr @__gxx_personality_v0 {
entry:
invoke void @_Z3foov()
to label %return unwind label %lpad
lpad: ; preds = %entry
- %0 = landingpad { i8*, i32 }
- catch i8* bitcast ({ i8*, i8* }* @_ZTI3Foo to i8*)
- %1 = extractvalue { i8*, i32 } %0, 1
- %2 = tail call i32 @llvm.eh.typeid.for(i8* bitcast ({ i8*, i8* }* @_ZTI3Foo to i8*)) nounwind
+ %0 = landingpad { ptr, i32 }
+ catch ptr @_ZTI3Foo
+ %1 = extractvalue { ptr, i32 } %0, 1
+ %2 = tail call i32 @llvm.eh.typeid.for(ptr @_ZTI3Foo) nounwind
; CHECK: _ZTI3Foo(target2)
%matches = icmp eq i32 %1, %2
br i1 %matches, label %catch, label %eh.resume
catch: ; preds = %lpad
- %3 = extractvalue { i8*, i32 } %0, 0
- %4 = tail call i8* @__cxa_begin_catch(i8* %3) nounwind
+ %3 = extractvalue { ptr, i32 } %0, 0
+ %4 = tail call ptr @__cxa_begin_catch(ptr %3) nounwind
tail call void @__cxa_end_catch()
br label %return
@@ -30,15 +30,15 @@ return: ; preds = %entry, %catch
ret i32 %retval.0
eh.resume: ; preds = %lpad
- resume { i8*, i32 } %0
+ resume { ptr, i32 } %0
}
declare void @_Z3foov()
declare i32 @__gxx_personality_v0(...)
-declare i32 @llvm.eh.typeid.for(i8*) nounwind readnone
+declare i32 @llvm.eh.typeid.for(ptr) nounwind readnone
-declare i8* @__cxa_begin_catch(i8*)
+declare ptr @__cxa_begin_catch(ptr)
declare void @__cxa_end_catch()
diff --git a/llvm/test/CodeGen/ARM/arm-vld1.ll b/llvm/test/CodeGen/ARM/arm-vld1.ll
index 8cd27ccef4ff8..1ea48e908abbd 100644
--- a/llvm/test/CodeGen/ARM/arm-vld1.ll
+++ b/llvm/test/CodeGen/ARM/arm-vld1.ll
@@ -33,553 +33,553 @@
%struct.uint8x16x3_t = type { <16 x i8>, <16 x i8>, <16 x i8> }
%struct.uint8x16x4_t = type { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }
-declare %struct.uint16x4x2_t @llvm.arm.neon.vld1x2.v4i16.p0i16(i16*) nounwind readonly
-declare %struct.uint16x4x3_t @llvm.arm.neon.vld1x3.v4i16.p0i16(i16*) nounwind readonly
-declare %struct.uint16x4x4_t @llvm.arm.neon.vld1x4.v4i16.p0i16(i16*) nounwind readonly
+declare %struct.uint16x4x2_t @llvm.arm.neon.vld1x2.v4i16.p0(ptr) nounwind readonly
+declare %struct.uint16x4x3_t @llvm.arm.neon.vld1x3.v4i16.p0(ptr) nounwind readonly
+declare %struct.uint16x4x4_t @llvm.arm.neon.vld1x4.v4i16.p0(ptr) nounwind readonly
-declare %struct.uint32x2x2_t @llvm.arm.neon.vld1x2.v2i32.p0i32(i32*) nounwind readonly
-declare %struct.uint32x2x3_t @llvm.arm.neon.vld1x3.v2i32.p0i32(i32*) nounwind readonly
-declare %struct.uint32x2x4_t @llvm.arm.neon.vld1x4.v2i32.p0i32(i32*) nounwind readonly
+declare %struct.uint32x2x2_t @llvm.arm.neon.vld1x2.v2i32.p0(ptr) nounwind readonly
+declare %struct.uint32x2x3_t @llvm.arm.neon.vld1x3.v2i32.p0(ptr) nounwind readonly
+declare %struct.uint32x2x4_t @llvm.arm.neon.vld1x4.v2i32.p0(ptr) nounwind readonly
-declare %struct.uint64x1x2_t @llvm.arm.neon.vld1x2.v1i64.p0i64(i64*) nounwind readonly
-declare %struct.uint64x1x3_t @llvm.arm.neon.vld1x3.v1i64.p0i64(i64*) nounwind readonly
-declare %struct.uint64x1x4_t @llvm.arm.neon.vld1x4.v1i64.p0i64(i64*) nounwind readonly
+declare %struct.uint64x1x2_t @llvm.arm.neon.vld1x2.v1i64.p0(ptr) nounwind readonly
+declare %struct.uint64x1x3_t @llvm.arm.neon.vld1x3.v1i64.p0(ptr) nounwind readonly
+declare %struct.uint64x1x4_t @llvm.arm.neon.vld1x4.v1i64.p0(ptr) nounwind readonly
-declare %struct.uint8x8x2_t @llvm.arm.neon.vld1x2.v8i8.p0i8(i8*) nounwind readonly
-declare %struct.uint8x8x3_t @llvm.arm.neon.vld1x3.v8i8.p0i8(i8*) nounwind readonly
-declare %struct.uint8x8x4_t @llvm.arm.neon.vld1x4.v8i8.p0i8(i8*) nounwind readonly
+declare %struct.uint8x8x2_t @llvm.arm.neon.vld1x2.v8i8.p0(ptr) nounwind readonly
+declare %struct.uint8x8x3_t @llvm.arm.neon.vld1x3.v8i8.p0(ptr) nounwind readonly
+declare %struct.uint8x8x4_t @llvm.arm.neon.vld1x4.v8i8.p0(ptr) nounwind readonly
-declare %struct.uint16x8x2_t @llvm.arm.neon.vld1x2.v8i16.p0i16(i16*) nounwind readonly
-declare %struct.uint16x8x3_t @llvm.arm.neon.vld1x3.v8i16.p0i16(i16*) nounwind readonly
-declare %struct.uint16x8x4_t @llvm.arm.neon.vld1x4.v8i16.p0i16(i16*) nounwind readonly
+declare %struct.uint16x8x2_t @llvm.arm.neon.vld1x2.v8i16.p0(ptr) nounwind readonly
+declare %struct.uint16x8x3_t @llvm.arm.neon.vld1x3.v8i16.p0(ptr) nounwind readonly
+declare %struct.uint16x8x4_t @llvm.arm.neon.vld1x4.v8i16.p0(ptr) nounwind readonly
-declare %struct.uint32x4x2_t @llvm.arm.neon.vld1x2.v4i32.p0i32(i32*) nounwind readonly
-declare %struct.uint32x4x3_t @llvm.arm.neon.vld1x3.v4i32.p0i32(i32*) nounwind readonly
-declare %struct.uint32x4x4_t @llvm.arm.neon.vld1x4.v4i32.p0i32(i32*) nounwind readonly
+declare %struct.uint32x4x2_t @llvm.arm.neon.vld1x2.v4i32.p0(ptr) nounwind readonly
+declare %struct.uint32x4x3_t @llvm.arm.neon.vld1x3.v4i32.p0(ptr) nounwind readonly
+declare %struct.uint32x4x4_t @llvm.arm.neon.vld1x4.v4i32.p0(ptr) nounwind readonly
-declare %struct.uint64x2x2_t @llvm.arm.neon.vld1x2.v2i64.p0i64(i64*) nounwind readonly
-declare %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64*) nounwind readonly
-declare %struct.uint64x2x4_t @llvm.arm.neon.vld1x4.v2i64.p0i64(i64*) nounwind readonly
+declare %struct.uint64x2x2_t @llvm.arm.neon.vld1x2.v2i64.p0(ptr) nounwind readonly
+declare %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0(ptr) nounwind readonly
+declare %struct.uint64x2x4_t @llvm.arm.neon.vld1x4.v2i64.p0(ptr) nounwind readonly
-declare %struct.uint8x16x2_t @llvm.arm.neon.vld1x2.v16i8.p0i8(i8*) nounwind readonly
-declare %struct.uint8x16x3_t @llvm.arm.neon.vld1x3.v16i8.p0i8(i8*) nounwind readonly
-declare %struct.uint8x16x4_t @llvm.arm.neon.vld1x4.v16i8.p0i8(i8*) nounwind readonly
+declare %struct.uint8x16x2_t @llvm.arm.neon.vld1x2.v16i8.p0(ptr) nounwind readonly
+declare %struct.uint8x16x3_t @llvm.arm.neon.vld1x3.v16i8.p0(ptr) nounwind readonly
+declare %struct.uint8x16x4_t @llvm.arm.neon.vld1x4.v16i8.p0(ptr) nounwind readonly
; CHECK-LABEL: test_vld1_u16_x2
; CHECK: vld1.16 {d16, d17}, [r0:64]
-define %struct.uint16x4x2_t @test_vld1_u16_x2(i16* %a) nounwind {
- %tmp = tail call %struct.uint16x4x2_t @llvm.arm.neon.vld1x2.v4i16.p0i16(i16* %a)
+define %struct.uint16x4x2_t @test_vld1_u16_x2(ptr %a) nounwind {
+ %tmp = tail call %struct.uint16x4x2_t @llvm.arm.neon.vld1x2.v4i16.p0(ptr %a)
ret %struct.uint16x4x2_t %tmp
}
; CHECK-LABEL: test_vld1_u16_x3
; CHECK: vld1.16 {d16, d17, d18}, [r1:64]
-define %struct.uint16x4x3_t @test_vld1_u16_x3(i16* %a) nounwind {
- %tmp = tail call %struct.uint16x4x3_t @llvm.arm.neon.vld1x3.v4i16.p0i16(i16* %a)
+define %struct.uint16x4x3_t @test_vld1_u16_x3(ptr %a) nounwind {
+ %tmp = tail call %struct.uint16x4x3_t @llvm.arm.neon.vld1x3.v4i16.p0(ptr %a)
ret %struct.uint16x4x3_t %tmp
}
; CHECK-LABEL: test_vld1_u16_x4
; CHECK: vld1.16 {d16, d17, d18, d19}, [r1:256]
-define %struct.uint16x4x4_t @test_vld1_u16_x4(i16* %a) nounwind {
- %tmp = tail call %struct.uint16x4x4_t @llvm.arm.neon.vld1x4.v4i16.p0i16(i16* %a)
+define %struct.uint16x4x4_t @test_vld1_u16_x4(ptr %a) nounwind {
+ %tmp = tail call %struct.uint16x4x4_t @llvm.arm.neon.vld1x4.v4i16.p0(ptr %a)
ret %struct.uint16x4x4_t %tmp
}
; CHECK-LABEL: test_vld1_u32_x2
; CHECK: vld1.32 {d16, d17}, [r0:64]
-define %struct.uint32x2x2_t @test_vld1_u32_x2(i32* %a) nounwind {
- %tmp = tail call %struct.uint32x2x2_t @llvm.arm.neon.vld1x2.v2i32.p0i32(i32* %a)
+define %struct.uint32x2x2_t @test_vld1_u32_x2(ptr %a) nounwind {
+ %tmp = tail call %struct.uint32x2x2_t @llvm.arm.neon.vld1x2.v2i32.p0(ptr %a)
ret %struct.uint32x2x2_t %tmp
}
; CHECK-LABEL: test_vld1_u32_x3
; CHECK: vld1.32 {d16, d17, d18}, [r1:64]
-define %struct.uint32x2x3_t @test_vld1_u32_x3(i32* %a) nounwind {
- %tmp = tail call %struct.uint32x2x3_t @llvm.arm.neon.vld1x3.v2i32.p0i32(i32* %a)
+define %struct.uint32x2x3_t @test_vld1_u32_x3(ptr %a) nounwind {
+ %tmp = tail call %struct.uint32x2x3_t @llvm.arm.neon.vld1x3.v2i32.p0(ptr %a)
ret %struct.uint32x2x3_t %tmp
}
; CHECK-LABEL: test_vld1_u32_x4
; CHECK: vld1.32 {d16, d17, d18, d19}, [r1:256]
-define %struct.uint32x2x4_t @test_vld1_u32_x4(i32* %a) nounwind {
- %tmp = tail call %struct.uint32x2x4_t @llvm.arm.neon.vld1x4.v2i32.p0i32(i32* %a)
+define %struct.uint32x2x4_t @test_vld1_u32_x4(ptr %a) nounwind {
+ %tmp = tail call %struct.uint32x2x4_t @llvm.arm.neon.vld1x4.v2i32.p0(ptr %a)
ret %struct.uint32x2x4_t %tmp
}
; CHECK-LABEL: test_vld1_u64_x2
; CHECK: vld1.64 {d16, d17}, [r0:64]
-define %struct.uint64x1x2_t @test_vld1_u64_x2(i64* %a) nounwind {
- %tmp = tail call %struct.uint64x1x2_t @llvm.arm.neon.vld1x2.v1i64.p0i64(i64* %a)
+define %struct.uint64x1x2_t @test_vld1_u64_x2(ptr %a) nounwind {
+ %tmp = tail call %struct.uint64x1x2_t @llvm.arm.neon.vld1x2.v1i64.p0(ptr %a)
ret %struct.uint64x1x2_t %tmp
}
; CHECK-LABEL: test_vld1_u64_x3
; CHECK: vld1.64 {d16, d17, d18}, [r1:64]
-define %struct.uint64x1x3_t @test_vld1_u64_x3(i64* %a) nounwind {
- %tmp = tail call %struct.uint64x1x3_t @llvm.arm.neon.vld1x3.v1i64.p0i64(i64* %a)
+define %struct.uint64x1x3_t @test_vld1_u64_x3(ptr %a) nounwind {
+ %tmp = tail call %struct.uint64x1x3_t @llvm.arm.neon.vld1x3.v1i64.p0(ptr %a)
ret %struct.uint64x1x3_t %tmp
}
; CHECK-LABEL: test_vld1_u64_x4
; CHECK: vld1.64 {d16, d17, d18, d19}, [r1:256]
-define %struct.uint64x1x4_t @test_vld1_u64_x4(i64* %a) nounwind {
- %tmp = tail call %struct.uint64x1x4_t @llvm.arm.neon.vld1x4.v1i64.p0i64(i64* %a)
+define %struct.uint64x1x4_t @test_vld1_u64_x4(ptr %a) nounwind {
+ %tmp = tail call %struct.uint64x1x4_t @llvm.arm.neon.vld1x4.v1i64.p0(ptr %a)
ret %struct.uint64x1x4_t %tmp
}
; CHECK-LABEL: test_vld1_u8_x2
; CHECK: vld1.8 {d16, d17}, [r0:64]
-define %struct.uint8x8x2_t @test_vld1_u8_x2(i8* %a) nounwind {
- %tmp = tail call %struct.uint8x8x2_t @llvm.arm.neon.vld1x2.v8i8.p0i8(i8* %a)
+define %struct.uint8x8x2_t @test_vld1_u8_x2(ptr %a) nounwind {
+ %tmp = tail call %struct.uint8x8x2_t @llvm.arm.neon.vld1x2.v8i8.p0(ptr %a)
ret %struct.uint8x8x2_t %tmp
}
; CHECK-LABEL: test_vld1_u8_x3
; CHECK: vld1.8 {d16, d17, d18}, [r1:64]
-define %struct.uint8x8x3_t @test_vld1_u8_x3(i8* %a) nounwind {
- %tmp = tail call %struct.uint8x8x3_t @llvm.arm.neon.vld1x3.v8i8.p0i8(i8* %a)
+define %struct.uint8x8x3_t @test_vld1_u8_x3(ptr %a) nounwind {
+ %tmp = tail call %struct.uint8x8x3_t @llvm.arm.neon.vld1x3.v8i8.p0(ptr %a)
ret %struct.uint8x8x3_t %tmp
}
; CHECK-LABEL: test_vld1_u8_x4
; CHECK: vld1.8 {d16, d17, d18, d19}, [r1:256]
-define %struct.uint8x8x4_t @test_vld1_u8_x4(i8* %a) nounwind {
- %tmp = tail call %struct.uint8x8x4_t @llvm.arm.neon.vld1x4.v8i8.p0i8(i8* %a)
+define %struct.uint8x8x4_t @test_vld1_u8_x4(ptr %a) nounwind {
+ %tmp = tail call %struct.uint8x8x4_t @llvm.arm.neon.vld1x4.v8i8.p0(ptr %a)
ret %struct.uint8x8x4_t %tmp
}
; CHECK-LABEL: test_vld1q_u16_x2
; CHECK: vld1.16 {d16, d17, d18, d19}, [r1:256]
-define %struct.uint16x8x2_t @test_vld1q_u16_x2(i16* %a) nounwind {
- %tmp = tail call %struct.uint16x8x2_t @llvm.arm.neon.vld1x2.v8i16.p0i16(i16* %a)
+define %struct.uint16x8x2_t @test_vld1q_u16_x2(ptr %a) nounwind {
+ %tmp = tail call %struct.uint16x8x2_t @llvm.arm.neon.vld1x2.v8i16.p0(ptr %a)
ret %struct.uint16x8x2_t %tmp
}
; CHECK-LABEL: test_vld1q_u16_x3
; CHECK: vld1.16 {d16, d17, d18}, [r1:64]!
; CHECK: vld1.16 {d19, d20, d21}, [r1:64]
-define %struct.uint16x8x3_t @test_vld1q_u16_x3(i16* %a) nounwind {
- %tmp = tail call %struct.uint16x8x3_t @llvm.arm.neon.vld1x3.v8i16.p0i16(i16* %a)
+define %struct.uint16x8x3_t @test_vld1q_u16_x3(ptr %a) nounwind {
+ %tmp = tail call %struct.uint16x8x3_t @llvm.arm.neon.vld1x3.v8i16.p0(ptr %a)
ret %struct.uint16x8x3_t %tmp
}
; CHECK-LABEL: test_vld1q_u16_x4
; CHECK: vld1.16 {d16, d17, d18, d19}, [r1:256]!
; CHECK: vld1.16 {d20, d21, d22, d23}, [r1:256]
-define %struct.uint16x8x4_t @test_vld1q_u16_x4(i16* %a) nounwind {
- %tmp = tail call %struct.uint16x8x4_t @llvm.arm.neon.vld1x4.v8i16.p0i16(i16* %a)
+define %struct.uint16x8x4_t @test_vld1q_u16_x4(ptr %a) nounwind {
+ %tmp = tail call %struct.uint16x8x4_t @llvm.arm.neon.vld1x4.v8i16.p0(ptr %a)
ret %struct.uint16x8x4_t %tmp
}
; CHECK-LABEL: test_vld1q_u32_x2
; CHECK: vld1.32 {d16, d17, d18, d19}, [r1:256]
-define %struct.uint32x4x2_t @test_vld1q_u32_x2(i32* %a) nounwind {
- %tmp = tail call %struct.uint32x4x2_t @llvm.arm.neon.vld1x2.v4i32.p0i32(i32* %a)
+define %struct.uint32x4x2_t @test_vld1q_u32_x2(ptr %a) nounwind {
+ %tmp = tail call %struct.uint32x4x2_t @llvm.arm.neon.vld1x2.v4i32.p0(ptr %a)
ret %struct.uint32x4x2_t %tmp
}
; CHECK-LABEL: test_vld1q_u32_x3
; CHECK: vld1.32 {d16, d17, d18}, [r1:64]!
; CHECK: vld1.32 {d19, d20, d21}, [r1:64]
-define %struct.uint32x4x3_t @test_vld1q_u32_x3(i32* %a) nounwind {
- %tmp = tail call %struct.uint32x4x3_t @llvm.arm.neon.vld1x3.v4i32.p0i32(i32* %a)
+define %struct.uint32x4x3_t @test_vld1q_u32_x3(ptr %a) nounwind {
+ %tmp = tail call %struct.uint32x4x3_t @llvm.arm.neon.vld1x3.v4i32.p0(ptr %a)
ret %struct.uint32x4x3_t %tmp
}
; CHECK-LABEL: test_vld1q_u32_x4
; CHECK: vld1.32 {d16, d17, d18, d19}, [r1:256]!
; CHECK: vld1.32 {d20, d21, d22, d23}, [r1:256]
-define %struct.uint32x4x4_t @test_vld1q_u32_x4(i32* %a) nounwind {
- %tmp = tail call %struct.uint32x4x4_t @llvm.arm.neon.vld1x4.v4i32.p0i32(i32* %a)
+define %struct.uint32x4x4_t @test_vld1q_u32_x4(ptr %a) nounwind {
+ %tmp = tail call %struct.uint32x4x4_t @llvm.arm.neon.vld1x4.v4i32.p0(ptr %a)
ret %struct.uint32x4x4_t %tmp
}
; CHECK-LABEL: test_vld1q_u64_x2
; CHECK: vld1.64 {d16, d17, d18, d19}, [r1:256]
-define %struct.uint64x2x2_t @test_vld1q_u64_x2(i64* %a) nounwind {
- %tmp = tail call %struct.uint64x2x2_t @llvm.arm.neon.vld1x2.v2i64.p0i64(i64* %a)
+define %struct.uint64x2x2_t @test_vld1q_u64_x2(ptr %a) nounwind {
+ %tmp = tail call %struct.uint64x2x2_t @llvm.arm.neon.vld1x2.v2i64.p0(ptr %a)
ret %struct.uint64x2x2_t %tmp
}
; CHECK-LABEL: test_vld1q_u64_x3
; CHECK: vld1.64 {d16, d17, d18}, [r1:64]!
; CHECK: vld1.64 {d19, d20, d21}, [r1:64]
-define %struct.uint64x2x3_t @test_vld1q_u64_x3(i64* %a) nounwind {
- %tmp = tail call %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64* %a)
+define %struct.uint64x2x3_t @test_vld1q_u64_x3(ptr %a) nounwind {
+ %tmp = tail call %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0(ptr %a)
ret %struct.uint64x2x3_t %tmp
}
; CHECK-LABEL: test_vld1q_u64_x4
; CHECK: vld1.64 {d16, d17, d18, d19}, [r1:256]!
; CHECK: vld1.64 {d20, d21, d22, d23}, [r1:256]
-define %struct.uint64x2x4_t @test_vld1q_u64_x4(i64* %a) nounwind {
- %tmp = tail call %struct.uint64x2x4_t @llvm.arm.neon.vld1x4.v2i64.p0i64(i64* %a)
+define %struct.uint64x2x4_t @test_vld1q_u64_x4(ptr %a) nounwind {
+ %tmp = tail call %struct.uint64x2x4_t @llvm.arm.neon.vld1x4.v2i64.p0(ptr %a)
ret %struct.uint64x2x4_t %tmp
}
; CHECK-LABEL: test_vld1q_u8_x2
; CHECK: vld1.8 {d16, d17, d18, d19}, [r1:256]
-define %struct.uint8x16x2_t @test_vld1q_u8_x2(i8* %a) nounwind {
- %tmp = tail call %struct.uint8x16x2_t @llvm.arm.neon.vld1x2.v16i8.p0i8(i8* %a)
+define %struct.uint8x16x2_t @test_vld1q_u8_x2(ptr %a) nounwind {
+ %tmp = tail call %struct.uint8x16x2_t @llvm.arm.neon.vld1x2.v16i8.p0(ptr %a)
ret %struct.uint8x16x2_t %tmp
}
; CHECK-LABEL: test_vld1q_u8_x3
; CHECK: vld1.8 {d16, d17, d18}, [r1:64]!
; CHECK: vld1.8 {d19, d20, d21}, [r1:64]
-define %struct.uint8x16x3_t @test_vld1q_u8_x3(i8* %a) nounwind {
- %tmp = tail call %struct.uint8x16x3_t @llvm.arm.neon.vld1x3.v16i8.p0i8(i8* %a)
+define %struct.uint8x16x3_t @test_vld1q_u8_x3(ptr %a) nounwind {
+ %tmp = tail call %struct.uint8x16x3_t @llvm.arm.neon.vld1x3.v16i8.p0(ptr %a)
ret %struct.uint8x16x3_t %tmp
}
; CHECK-LABEL: test_vld1q_u8_x4
; CHECK: vld1.8 {d16, d17, d18, d19}, [r1:256]!
; CHECK: vld1.8 {d20, d21, d22, d23}, [r1:256]
-define %struct.uint8x16x4_t @test_vld1q_u8_x4(i8* %a) nounwind {
- %tmp = tail call %struct.uint8x16x4_t @llvm.arm.neon.vld1x4.v16i8.p0i8(i8* %a)
+define %struct.uint8x16x4_t @test_vld1q_u8_x4(ptr %a) nounwind {
+ %tmp = tail call %struct.uint8x16x4_t @llvm.arm.neon.vld1x4.v16i8.p0(ptr %a)
ret %struct.uint8x16x4_t %tmp
}
; Post-increment.
-define %struct.uint16x4x2_t @test_vld1_u16_x2_post_imm(i16* %a, i16** %ptr) nounwind {
+define %struct.uint16x4x2_t @test_vld1_u16_x2_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1_u16_x2_post_imm:
; CHECK: vld1.16 {d16, d17}, [r0:64]!
- %ld = tail call %struct.uint16x4x2_t @llvm.arm.neon.vld1x2.v4i16.p0i16(i16* %a)
- %tmp = getelementptr i16, i16* %a, i32 8
- store i16* %tmp, i16** %ptr
+ %ld = tail call %struct.uint16x4x2_t @llvm.arm.neon.vld1x2.v4i16.p0(ptr %a)
+ %tmp = getelementptr i16, ptr %a, i32 8
+ store ptr %tmp, ptr %ptr
ret %struct.uint16x4x2_t %ld
}
-define %struct.uint16x4x2_t @test_vld1_u16_x2_post_reg(i16* %a, i16** %ptr, i32 %inc) nounwind {
+define %struct.uint16x4x2_t @test_vld1_u16_x2_post_reg(ptr %a, ptr %ptr, i32 %inc) nounwind {
; CHECK-LABEL: test_vld1_u16_x2_post_reg:
; CHECK: lsl r2, r2, #1
; CHECK-NEXT: vld1.16 {d16, d17}, [r0:64], r2
- %ld = tail call %struct.uint16x4x2_t @llvm.arm.neon.vld1x2.v4i16.p0i16(i16* %a)
- %tmp = getelementptr i16, i16* %a, i32 %inc
- store i16* %tmp, i16** %ptr
+ %ld = tail call %struct.uint16x4x2_t @llvm.arm.neon.vld1x2.v4i16.p0(ptr %a)
+ %tmp = getelementptr i16, ptr %a, i32 %inc
+ store ptr %tmp, ptr %ptr
ret %struct.uint16x4x2_t %ld
}
-define %struct.uint16x4x3_t @test_vld1_u16_x3_post_imm(i16* %a, i16** %ptr) nounwind {
+define %struct.uint16x4x3_t @test_vld1_u16_x3_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1_u16_x3_post_imm:
; CHECK: vld1.16 {d16, d17, d18}, [r1:64]!
- %ld = tail call %struct.uint16x4x3_t @llvm.arm.neon.vld1x3.v4i16.p0i16(i16* %a)
- %tmp = getelementptr i16, i16* %a, i32 12
- store i16* %tmp, i16** %ptr
+ %ld = tail call %struct.uint16x4x3_t @llvm.arm.neon.vld1x3.v4i16.p0(ptr %a)
+ %tmp = getelementptr i16, ptr %a, i32 12
+ store ptr %tmp, ptr %ptr
ret %struct.uint16x4x3_t %ld
}
-define %struct.uint16x4x3_t @test_vld1_u16_x3_post_reg(i16* %a, i16** %ptr, i32 %inc) nounwind {
+define %struct.uint16x4x3_t @test_vld1_u16_x3_post_reg(ptr %a, ptr %ptr, i32 %inc) nounwind {
; CHECK-LABEL: test_vld1_u16_x3_post_reg:
; CHECK: lsl r3, r3, #1
; CHECK-NEXT: vld1.16 {d16, d17, d18}, [r1:64], r3
- %ld = tail call %struct.uint16x4x3_t @llvm.arm.neon.vld1x3.v4i16.p0i16(i16* %a)
- %tmp = getelementptr i16, i16* %a, i32 %inc
- store i16* %tmp, i16** %ptr
+ %ld = tail call %struct.uint16x4x3_t @llvm.arm.neon.vld1x3.v4i16.p0(ptr %a)
+ %tmp = getelementptr i16, ptr %a, i32 %inc
+ store ptr %tmp, ptr %ptr
ret %struct.uint16x4x3_t %ld
}
-define %struct.uint16x4x4_t @test_vld1_u16_x4_post_imm(i16* %a, i16** %ptr) nounwind {
+define %struct.uint16x4x4_t @test_vld1_u16_x4_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1_u16_x4_post_imm:
; CHECK: vld1.16 {d16, d17, d18, d19}, [r1:256]!
- %ld = tail call %struct.uint16x4x4_t @llvm.arm.neon.vld1x4.v4i16.p0i16(i16* %a)
- %tmp = getelementptr i16, i16* %a, i32 16
- store i16* %tmp, i16** %ptr
+ %ld = tail call %struct.uint16x4x4_t @llvm.arm.neon.vld1x4.v4i16.p0(ptr %a)
+ %tmp = getelementptr i16, ptr %a, i32 16
+ store ptr %tmp, ptr %ptr
ret %struct.uint16x4x4_t %ld
}
-define %struct.uint16x4x4_t @test_vld1_u16_x4_post_reg(i16* %a, i16** %ptr, i32 %inc) nounwind {
+define %struct.uint16x4x4_t @test_vld1_u16_x4_post_reg(ptr %a, ptr %ptr, i32 %inc) nounwind {
; CHECK-LABEL: test_vld1_u16_x4_post_reg:
; CHECK: lsl r3, r3, #1
; CHECK-NEXT: vld1.16 {d16, d17, d18, d19}, [r1:256], r3
- %ld = tail call %struct.uint16x4x4_t @llvm.arm.neon.vld1x4.v4i16.p0i16(i16* %a)
- %tmp = getelementptr i16, i16* %a, i32 %inc
- store i16* %tmp, i16** %ptr
+ %ld = tail call %struct.uint16x4x4_t @llvm.arm.neon.vld1x4.v4i16.p0(ptr %a)
+ %tmp = getelementptr i16, ptr %a, i32 %inc
+ store ptr %tmp, ptr %ptr
ret %struct.uint16x4x4_t %ld
}
-define %struct.uint32x2x2_t @test_vld1_u32_x2_post_imm(i32* %a, i32** %ptr) nounwind {
+define %struct.uint32x2x2_t @test_vld1_u32_x2_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1_u32_x2_post_imm:
; CHECK: vld1.32 {d16, d17}, [r0:64]!
- %ld = tail call %struct.uint32x2x2_t @llvm.arm.neon.vld1x2.v2i32.p0i32(i32* %a)
- %tmp = getelementptr i32, i32* %a, i32 4
- store i32* %tmp, i32** %ptr
+ %ld = tail call %struct.uint32x2x2_t @llvm.arm.neon.vld1x2.v2i32.p0(ptr %a)
+ %tmp = getelementptr i32, ptr %a, i32 4
+ store ptr %tmp, ptr %ptr
ret %struct.uint32x2x2_t %ld
}
-define %struct.uint32x2x2_t @test_vld1_u32_x2_post_reg(i32* %a, i32** %ptr, i32 %inc) nounwind {
+define %struct.uint32x2x2_t @test_vld1_u32_x2_post_reg(ptr %a, ptr %ptr, i32 %inc) nounwind {
; CHECK-LABEL: test_vld1_u32_x2_post_reg:
; CHECK: lsl r2, r2, #2
; CHECK-NEXT: vld1.32 {d16, d17}, [r0:64], r2
- %ld = tail call %struct.uint32x2x2_t @llvm.arm.neon.vld1x2.v2i32.p0i32(i32* %a)
- %tmp = getelementptr i32, i32* %a, i32 %inc
- store i32* %tmp, i32** %ptr
+ %ld = tail call %struct.uint32x2x2_t @llvm.arm.neon.vld1x2.v2i32.p0(ptr %a)
+ %tmp = getelementptr i32, ptr %a, i32 %inc
+ store ptr %tmp, ptr %ptr
ret %struct.uint32x2x2_t %ld
}
-define %struct.uint32x2x3_t @test_vld1_u32_x3_post_imm(i32* %a, i32** %ptr) nounwind {
+define %struct.uint32x2x3_t @test_vld1_u32_x3_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1_u32_x3_post_imm:
; CHECK: vld1.32 {d16, d17, d18}, [r1:64]!
- %ld = tail call %struct.uint32x2x3_t @llvm.arm.neon.vld1x3.v2i32.p0i32(i32* %a)
- %tmp = getelementptr i32, i32* %a, i32 6
- store i32* %tmp, i32** %ptr
+ %ld = tail call %struct.uint32x2x3_t @llvm.arm.neon.vld1x3.v2i32.p0(ptr %a)
+ %tmp = getelementptr i32, ptr %a, i32 6
+ store ptr %tmp, ptr %ptr
ret %struct.uint32x2x3_t %ld
}
-define %struct.uint32x2x3_t @test_vld1_u32_x3_post_reg(i32* %a, i32** %ptr, i32 %inc) nounwind {
+define %struct.uint32x2x3_t @test_vld1_u32_x3_post_reg(ptr %a, ptr %ptr, i32 %inc) nounwind {
; CHECK-LABEL: test_vld1_u32_x3_post_reg:
; CHECK: lsl r3, r3, #2
; CHECK-NEXT: vld1.32 {d16, d17, d18}, [r1:64], r3
- %ld = tail call %struct.uint32x2x3_t @llvm.arm.neon.vld1x3.v2i32.p0i32(i32* %a)
- %tmp = getelementptr i32, i32* %a, i32 %inc
- store i32* %tmp, i32** %ptr
+ %ld = tail call %struct.uint32x2x3_t @llvm.arm.neon.vld1x3.v2i32.p0(ptr %a)
+ %tmp = getelementptr i32, ptr %a, i32 %inc
+ store ptr %tmp, ptr %ptr
ret %struct.uint32x2x3_t %ld
}
-define %struct.uint32x2x4_t @test_vld1_u32_x4_post_imm(i32* %a, i32** %ptr) nounwind {
+define %struct.uint32x2x4_t @test_vld1_u32_x4_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1_u32_x4_post_imm:
; CHECK: vld1.32 {d16, d17, d18, d19}, [r1:256]!
- %ld = tail call %struct.uint32x2x4_t @llvm.arm.neon.vld1x4.v2i32.p0i32(i32* %a)
- %tmp = getelementptr i32, i32* %a, i32 8
- store i32* %tmp, i32** %ptr
+ %ld = tail call %struct.uint32x2x4_t @llvm.arm.neon.vld1x4.v2i32.p0(ptr %a)
+ %tmp = getelementptr i32, ptr %a, i32 8
+ store ptr %tmp, ptr %ptr
ret %struct.uint32x2x4_t %ld
}
-define %struct.uint32x2x4_t @test_vld1_u32_x4_post_reg(i32* %a, i32** %ptr, i32 %inc) nounwind {
+define %struct.uint32x2x4_t @test_vld1_u32_x4_post_reg(ptr %a, ptr %ptr, i32 %inc) nounwind {
; CHECK-LABEL: test_vld1_u32_x4_post_reg:
; CHECK: lsl r3, r3, #2
; CHECK-NEXT: vld1.32 {d16, d17, d18, d19}, [r1:256], r3
- %ld = tail call %struct.uint32x2x4_t @llvm.arm.neon.vld1x4.v2i32.p0i32(i32* %a)
- %tmp = getelementptr i32, i32* %a, i32 %inc
- store i32* %tmp, i32** %ptr
+ %ld = tail call %struct.uint32x2x4_t @llvm.arm.neon.vld1x4.v2i32.p0(ptr %a)
+ %tmp = getelementptr i32, ptr %a, i32 %inc
+ store ptr %tmp, ptr %ptr
ret %struct.uint32x2x4_t %ld
}
-define %struct.uint64x1x2_t @test_vld1_u64_x2_post_imm(i64* %a, i64** %ptr) nounwind {
+define %struct.uint64x1x2_t @test_vld1_u64_x2_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1_u64_x2_post_imm:
; CHECK: vld1.64 {d16, d17}, [r0:64]!
- %ld = tail call %struct.uint64x1x2_t @llvm.arm.neon.vld1x2.v1i64.p0i64(i64* %a)
- %tmp = getelementptr i64, i64* %a, i32 2
- store i64* %tmp, i64** %ptr
+ %ld = tail call %struct.uint64x1x2_t @llvm.arm.neon.vld1x2.v1i64.p0(ptr %a)
+ %tmp = getelementptr i64, ptr %a, i32 2
+ store ptr %tmp, ptr %ptr
ret %struct.uint64x1x2_t %ld
}
-define %struct.uint64x1x2_t @test_vld1_u64_x2_post_reg(i64* %a, i64** %ptr, i32 %inc) nounwind {
+define %struct.uint64x1x2_t @test_vld1_u64_x2_post_reg(ptr %a, ptr %ptr, i32 %inc) nounwind {
; CHECK-LABEL: test_vld1_u64_x2_post_reg:
; CHECK: lsl r2, r2, #3
; CHECK-NEXT: vld1.64 {d16, d17}, [r0:64], r2
- %ld = tail call %struct.uint64x1x2_t @llvm.arm.neon.vld1x2.v1i64.p0i64(i64* %a)
- %tmp = getelementptr i64, i64* %a, i32 %inc
- store i64* %tmp, i64** %ptr
+ %ld = tail call %struct.uint64x1x2_t @llvm.arm.neon.vld1x2.v1i64.p0(ptr %a)
+ %tmp = getelementptr i64, ptr %a, i32 %inc
+ store ptr %tmp, ptr %ptr
ret %struct.uint64x1x2_t %ld
}
-define %struct.uint64x1x3_t @test_vld1_u64_x3_post_imm(i64* %a, i64** %ptr) nounwind {
+define %struct.uint64x1x3_t @test_vld1_u64_x3_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1_u64_x3_post_imm:
; CHECK: vld1.64 {d16, d17, d18}, [r1:64]!
- %ld = tail call %struct.uint64x1x3_t @llvm.arm.neon.vld1x3.v1i64.p0i64(i64* %a)
- %tmp = getelementptr i64, i64* %a, i32 3
- store i64* %tmp, i64** %ptr
+ %ld = tail call %struct.uint64x1x3_t @llvm.arm.neon.vld1x3.v1i64.p0(ptr %a)
+ %tmp = getelementptr i64, ptr %a, i32 3
+ store ptr %tmp, ptr %ptr
ret %struct.uint64x1x3_t %ld
}
-define %struct.uint64x1x3_t @test_vld1_u64_x3_post_reg(i64* %a, i64** %ptr, i32 %inc) nounwind {
+define %struct.uint64x1x3_t @test_vld1_u64_x3_post_reg(ptr %a, ptr %ptr, i32 %inc) nounwind {
; CHECK-LABEL: test_vld1_u64_x3_post_reg:
; CHECK: lsl r3, r3, #3
; CHECK-NEXT: vld1.64 {d16, d17, d18}, [r1:64], r3
- %ld = tail call %struct.uint64x1x3_t @llvm.arm.neon.vld1x3.v1i64.p0i64(i64* %a)
- %tmp = getelementptr i64, i64* %a, i32 %inc
- store i64* %tmp, i64** %ptr
+ %ld = tail call %struct.uint64x1x3_t @llvm.arm.neon.vld1x3.v1i64.p0(ptr %a)
+ %tmp = getelementptr i64, ptr %a, i32 %inc
+ store ptr %tmp, ptr %ptr
ret %struct.uint64x1x3_t %ld
}
-define %struct.uint64x1x4_t @test_vld1_u64_x4_post_imm(i64* %a, i64** %ptr) nounwind {
+define %struct.uint64x1x4_t @test_vld1_u64_x4_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1_u64_x4_post_imm:
; CHECK: vld1.64 {d16, d17, d18, d19}, [r1:256]!
- %ld = tail call %struct.uint64x1x4_t @llvm.arm.neon.vld1x4.v1i64.p0i64(i64* %a)
- %tmp = getelementptr i64, i64* %a, i32 4
- store i64* %tmp, i64** %ptr
+ %ld = tail call %struct.uint64x1x4_t @llvm.arm.neon.vld1x4.v1i64.p0(ptr %a)
+ %tmp = getelementptr i64, ptr %a, i32 4
+ store ptr %tmp, ptr %ptr
ret %struct.uint64x1x4_t %ld
}
-define %struct.uint64x1x4_t @test_vld1_u64_x4_post_reg(i64* %a, i64** %ptr, i32 %inc) nounwind {
+define %struct.uint64x1x4_t @test_vld1_u64_x4_post_reg(ptr %a, ptr %ptr, i32 %inc) nounwind {
; CHECK-LABEL: test_vld1_u64_x4_post_reg:
; CHECK: lsl r3, r3, #3
; CHECK-NEXT: vld1.64 {d16, d17, d18, d19}, [r1:256], r3
- %ld = tail call %struct.uint64x1x4_t @llvm.arm.neon.vld1x4.v1i64.p0i64(i64* %a)
- %tmp = getelementptr i64, i64* %a, i32 %inc
- store i64* %tmp, i64** %ptr
+ %ld = tail call %struct.uint64x1x4_t @llvm.arm.neon.vld1x4.v1i64.p0(ptr %a)
+ %tmp = getelementptr i64, ptr %a, i32 %inc
+ store ptr %tmp, ptr %ptr
ret %struct.uint64x1x4_t %ld
}
-define %struct.uint8x8x2_t @test_vld1_u8_x2_post_imm(i8* %a, i8** %ptr) nounwind {
+define %struct.uint8x8x2_t @test_vld1_u8_x2_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1_u8_x2_post_imm:
; CHECK: vld1.8 {d16, d17}, [r0:64]!
- %ld = tail call %struct.uint8x8x2_t @llvm.arm.neon.vld1x2.v8i8.p0i8(i8* %a)
- %tmp = getelementptr i8, i8* %a, i32 16
- store i8* %tmp, i8** %ptr
+ %ld = tail call %struct.uint8x8x2_t @llvm.arm.neon.vld1x2.v8i8.p0(ptr %a)
+ %tmp = getelementptr i8, ptr %a, i32 16
+ store ptr %tmp, ptr %ptr
ret %struct.uint8x8x2_t %ld
}
-define %struct.uint8x8x2_t @test_vld1_u8_x2_post_reg(i8* %a, i8** %ptr, i32 %inc) nounwind {
+define %struct.uint8x8x2_t @test_vld1_u8_x2_post_reg(ptr %a, ptr %ptr, i32 %inc) nounwind {
; CHECK-LABEL: test_vld1_u8_x2_post_reg:
; CHECK: vld1.8 {d16, d17}, [r0:64], r2
- %ld = tail call %struct.uint8x8x2_t @llvm.arm.neon.vld1x2.v8i8.p0i8(i8* %a)
- %tmp = getelementptr i8, i8* %a, i32 %inc
- store i8* %tmp, i8** %ptr
+ %ld = tail call %struct.uint8x8x2_t @llvm.arm.neon.vld1x2.v8i8.p0(ptr %a)
+ %tmp = getelementptr i8, ptr %a, i32 %inc
+ store ptr %tmp, ptr %ptr
ret %struct.uint8x8x2_t %ld
}
-define %struct.uint8x8x3_t @test_vld1_u8_x3_post_imm(i8* %a, i8** %ptr) nounwind {
+define %struct.uint8x8x3_t @test_vld1_u8_x3_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1_u8_x3_post_imm:
; CHECK: vld1.8 {d16, d17, d18}, [r1:64]!
- %ld = tail call %struct.uint8x8x3_t @llvm.arm.neon.vld1x3.v8i8.p0i8(i8* %a)
- %tmp = getelementptr i8, i8* %a, i32 24
- store i8* %tmp, i8** %ptr
+ %ld = tail call %struct.uint8x8x3_t @llvm.arm.neon.vld1x3.v8i8.p0(ptr %a)
+ %tmp = getelementptr i8, ptr %a, i32 24
+ store ptr %tmp, ptr %ptr
ret %struct.uint8x8x3_t %ld
}
-define %struct.uint8x8x3_t @test_vld1_u8_x3_post_reg(i8* %a, i8** %ptr, i32 %inc) nounwind {
+define %struct.uint8x8x3_t @test_vld1_u8_x3_post_reg(ptr %a, ptr %ptr, i32 %inc) nounwind {
; CHECK-LABEL: test_vld1_u8_x3_post_reg:
; CHECK: vld1.8 {d16, d17, d18}, [r1:64], r3
- %ld = tail call %struct.uint8x8x3_t @llvm.arm.neon.vld1x3.v8i8.p0i8(i8* %a)
- %tmp = getelementptr i8, i8* %a, i32 %inc
- store i8* %tmp, i8** %ptr
+ %ld = tail call %struct.uint8x8x3_t @llvm.arm.neon.vld1x3.v8i8.p0(ptr %a)
+ %tmp = getelementptr i8, ptr %a, i32 %inc
+ store ptr %tmp, ptr %ptr
ret %struct.uint8x8x3_t %ld
}
-define %struct.uint8x8x4_t @test_vld1_u8_x4_post_imm(i8* %a, i8** %ptr) nounwind {
+define %struct.uint8x8x4_t @test_vld1_u8_x4_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1_u8_x4_post_imm:
; CHECK: vld1.8 {d16, d17, d18, d19}, [r1:256]!
- %ld = tail call %struct.uint8x8x4_t @llvm.arm.neon.vld1x4.v8i8.p0i8(i8* %a)
- %tmp = getelementptr i8, i8* %a, i32 32
- store i8* %tmp, i8** %ptr
+ %ld = tail call %struct.uint8x8x4_t @llvm.arm.neon.vld1x4.v8i8.p0(ptr %a)
+ %tmp = getelementptr i8, ptr %a, i32 32
+ store ptr %tmp, ptr %ptr
ret %struct.uint8x8x4_t %ld
}
-define %struct.uint8x8x4_t @test_vld1_u8_x4_post_reg(i8* %a, i8** %ptr, i32 %inc) nounwind {
+define %struct.uint8x8x4_t @test_vld1_u8_x4_post_reg(ptr %a, ptr %ptr, i32 %inc) nounwind {
; CHECK-LABEL: test_vld1_u8_x4_post_reg:
; CHECK: vld1.8 {d16, d17, d18, d19}, [r1:256], r3
- %ld = tail call %struct.uint8x8x4_t @llvm.arm.neon.vld1x4.v8i8.p0i8(i8* %a)
- %tmp = getelementptr i8, i8* %a, i32 %inc
- store i8* %tmp, i8** %ptr
+ %ld = tail call %struct.uint8x8x4_t @llvm.arm.neon.vld1x4.v8i8.p0(ptr %a)
+ %tmp = getelementptr i8, ptr %a, i32 %inc
+ store ptr %tmp, ptr %ptr
ret %struct.uint8x8x4_t %ld
}
-define %struct.uint16x8x2_t @test_vld1q_u16_x2_post_imm(i16* %a, i16** %ptr) nounwind {
+define %struct.uint16x8x2_t @test_vld1q_u16_x2_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1q_u16_x2_post_imm:
; CHECK: vld1.16 {d16, d17, d18, d19}, [r1:256]!
- %ld = tail call %struct.uint16x8x2_t @llvm.arm.neon.vld1x2.v8i16.p0i16(i16* %a)
- %tmp = getelementptr i16, i16* %a, i32 16
- store i16* %tmp, i16** %ptr
+ %ld = tail call %struct.uint16x8x2_t @llvm.arm.neon.vld1x2.v8i16.p0(ptr %a)
+ %tmp = getelementptr i16, ptr %a, i32 16
+ store ptr %tmp, ptr %ptr
ret %struct.uint16x8x2_t %ld
}
-define %struct.uint16x8x3_t @test_vld1q_u16_x3_post_imm(i16* %a, i16** %ptr) nounwind {
+define %struct.uint16x8x3_t @test_vld1q_u16_x3_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1q_u16_x3_post_imm:
; CHECK: vld1.16 {d16, d17, d18}, [r1:64]!
; CHECK-NEXT: vld1.16 {d19, d20, d21}, [r1:64]!
- %ld = tail call %struct.uint16x8x3_t @llvm.arm.neon.vld1x3.v8i16.p0i16(i16* %a)
- %tmp = getelementptr i16, i16* %a, i32 24
- store i16* %tmp, i16** %ptr
+ %ld = tail call %struct.uint16x8x3_t @llvm.arm.neon.vld1x3.v8i16.p0(ptr %a)
+ %tmp = getelementptr i16, ptr %a, i32 24
+ store ptr %tmp, ptr %ptr
ret %struct.uint16x8x3_t %ld
}
-define %struct.uint16x8x4_t @test_vld1q_u16_x4_post_imm(i16* %a, i16** %ptr) nounwind {
+define %struct.uint16x8x4_t @test_vld1q_u16_x4_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1q_u16_x4_post_imm:
; CHECK: vld1.16 {d16, d17, d18, d19}, [r1:256]!
; CHECK-NEXT: vld1.16 {d20, d21, d22, d23}, [r1:256]!
- %ld = tail call %struct.uint16x8x4_t @llvm.arm.neon.vld1x4.v8i16.p0i16(i16* %a)
- %tmp = getelementptr i16, i16* %a, i32 32
- store i16* %tmp, i16** %ptr
+ %ld = tail call %struct.uint16x8x4_t @llvm.arm.neon.vld1x4.v8i16.p0(ptr %a)
+ %tmp = getelementptr i16, ptr %a, i32 32
+ store ptr %tmp, ptr %ptr
ret %struct.uint16x8x4_t %ld
}
-define %struct.uint32x4x2_t @test_vld1q_u32_x2_post_imm(i32* %a, i32** %ptr) nounwind {
+define %struct.uint32x4x2_t @test_vld1q_u32_x2_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1q_u32_x2_post_imm:
; CHECK: vld1.32 {d16, d17, d18, d19}, [r1:256]!
- %ld = tail call %struct.uint32x4x2_t @llvm.arm.neon.vld1x2.v4i32.p0i32(i32* %a)
- %tmp = getelementptr i32, i32* %a, i32 8
- store i32* %tmp, i32** %ptr
+ %ld = tail call %struct.uint32x4x2_t @llvm.arm.neon.vld1x2.v4i32.p0(ptr %a)
+ %tmp = getelementptr i32, ptr %a, i32 8
+ store ptr %tmp, ptr %ptr
ret %struct.uint32x4x2_t %ld
}
-define %struct.uint32x4x3_t @test_vld1q_u32_x3_post_imm(i32* %a, i32** %ptr) nounwind {
+define %struct.uint32x4x3_t @test_vld1q_u32_x3_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1q_u32_x3_post_imm:
; CHECK: vld1.32 {d16, d17, d18}, [r1:64]!
; CHECK-NEXT: vld1.32 {d19, d20, d21}, [r1:64]!
- %ld = tail call %struct.uint32x4x3_t @llvm.arm.neon.vld1x3.v4i32.p0i32(i32* %a)
- %tmp = getelementptr i32, i32* %a, i32 12
- store i32* %tmp, i32** %ptr
+ %ld = tail call %struct.uint32x4x3_t @llvm.arm.neon.vld1x3.v4i32.p0(ptr %a)
+ %tmp = getelementptr i32, ptr %a, i32 12
+ store ptr %tmp, ptr %ptr
ret %struct.uint32x4x3_t %ld
}
-define %struct.uint32x4x4_t @test_vld1q_u32_x4_post_imm(i32* %a, i32** %ptr) nounwind {
+define %struct.uint32x4x4_t @test_vld1q_u32_x4_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1q_u32_x4_post_imm:
; CHECK: vld1.32 {d16, d17, d18, d19}, [r1:256]!
; CHECK-NEXT: vld1.32 {d20, d21, d22, d23}, [r1:256]!
- %ld = tail call %struct.uint32x4x4_t @llvm.arm.neon.vld1x4.v4i32.p0i32(i32* %a)
- %tmp = getelementptr i32, i32* %a, i32 16
- store i32* %tmp, i32** %ptr
+ %ld = tail call %struct.uint32x4x4_t @llvm.arm.neon.vld1x4.v4i32.p0(ptr %a)
+ %tmp = getelementptr i32, ptr %a, i32 16
+ store ptr %tmp, ptr %ptr
ret %struct.uint32x4x4_t %ld
}
-define %struct.uint64x2x2_t @test_vld1q_u64_x2_post_imm(i64* %a, i64** %ptr) nounwind {
+define %struct.uint64x2x2_t @test_vld1q_u64_x2_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1q_u64_x2_post_imm:
; CHECK: vld1.64 {d16, d17, d18, d19}, [r1:256]!
- %ld = tail call %struct.uint64x2x2_t @llvm.arm.neon.vld1x2.v2i64.p0i64(i64* %a)
- %tmp = getelementptr i64, i64* %a, i32 4
- store i64* %tmp, i64** %ptr
+ %ld = tail call %struct.uint64x2x2_t @llvm.arm.neon.vld1x2.v2i64.p0(ptr %a)
+ %tmp = getelementptr i64, ptr %a, i32 4
+ store ptr %tmp, ptr %ptr
ret %struct.uint64x2x2_t %ld
}
-define %struct.uint64x2x3_t @test_vld1q_u64_x3_post_imm(i64* %a, i64** %ptr) nounwind {
+define %struct.uint64x2x3_t @test_vld1q_u64_x3_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1q_u64_x3_post_imm:
; CHECK: vld1.64 {d16, d17, d18}, [r1:64]!
; CHECK-NEXT: vld1.64 {d19, d20, d21}, [r1:64]!
- %ld = tail call %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64* %a)
- %tmp = getelementptr i64, i64* %a, i32 6
- store i64* %tmp, i64** %ptr
+ %ld = tail call %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0(ptr %a)
+ %tmp = getelementptr i64, ptr %a, i32 6
+ store ptr %tmp, ptr %ptr
ret %struct.uint64x2x3_t %ld
}
-define %struct.uint64x2x4_t @test_vld1q_u64_x4_post_imm(i64* %a, i64** %ptr) nounwind {
+define %struct.uint64x2x4_t @test_vld1q_u64_x4_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1q_u64_x4_post_imm:
; CHECK: vld1.64 {d16, d17, d18, d19}, [r1:256]!
; CHECK-NEXT: vld1.64 {d20, d21, d22, d23}, [r1:256]!
- %ld = tail call %struct.uint64x2x4_t @llvm.arm.neon.vld1x4.v2i64.p0i64(i64* %a)
- %tmp = getelementptr i64, i64* %a, i32 8
- store i64* %tmp, i64** %ptr
+ %ld = tail call %struct.uint64x2x4_t @llvm.arm.neon.vld1x4.v2i64.p0(ptr %a)
+ %tmp = getelementptr i64, ptr %a, i32 8
+ store ptr %tmp, ptr %ptr
ret %struct.uint64x2x4_t %ld
}
-define %struct.uint8x16x2_t @test_vld1q_u8_x2_post_imm(i8* %a, i8** %ptr) nounwind {
+define %struct.uint8x16x2_t @test_vld1q_u8_x2_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1q_u8_x2_post_imm:
; CHECK: vld1.8 {d16, d17, d18, d19}, [r1:256]!
- %ld = tail call %struct.uint8x16x2_t @llvm.arm.neon.vld1x2.v16i8.p0i8(i8* %a)
- %tmp = getelementptr i8, i8* %a, i32 32
- store i8* %tmp, i8** %ptr
+ %ld = tail call %struct.uint8x16x2_t @llvm.arm.neon.vld1x2.v16i8.p0(ptr %a)
+ %tmp = getelementptr i8, ptr %a, i32 32
+ store ptr %tmp, ptr %ptr
ret %struct.uint8x16x2_t %ld
}
-define %struct.uint8x16x3_t @test_vld1q_u8_x3_post_imm(i8* %a, i8** %ptr) nounwind {
+define %struct.uint8x16x3_t @test_vld1q_u8_x3_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1q_u8_x3_post_imm:
; CHECK: vld1.8 {d16, d17, d18}, [r1:64]!
; CHECK-NEXT: vld1.8 {d19, d20, d21}, [r1:64]!
- %ld = tail call %struct.uint8x16x3_t @llvm.arm.neon.vld1x3.v16i8.p0i8(i8* %a)
- %tmp = getelementptr i8, i8* %a, i32 48
- store i8* %tmp, i8** %ptr
+ %ld = tail call %struct.uint8x16x3_t @llvm.arm.neon.vld1x3.v16i8.p0(ptr %a)
+ %tmp = getelementptr i8, ptr %a, i32 48
+ store ptr %tmp, ptr %ptr
ret %struct.uint8x16x3_t %ld
}
-define %struct.uint8x16x4_t @test_vld1q_u8_x4_post_imm(i8* %a, i8** %ptr) nounwind {
+define %struct.uint8x16x4_t @test_vld1q_u8_x4_post_imm(ptr %a, ptr %ptr) nounwind {
; CHECK-LABEL: test_vld1q_u8_x4_post_imm:
; CHECK: vld1.8 {d16, d17, d18, d19}, [r1:256]!
; CHECK-NEXT: vld1.8 {d20, d21, d22, d23}, [r1:256]!
- %ld = tail call %struct.uint8x16x4_t @llvm.arm.neon.vld1x4.v16i8.p0i8(i8* %a)
- %tmp = getelementptr i8, i8* %a, i32 64
- store i8* %tmp, i8** %ptr
+ %ld = tail call %struct.uint8x16x4_t @llvm.arm.neon.vld1x4.v16i8.p0(ptr %a)
+ %tmp = getelementptr i8, ptr %a, i32 64
+ store ptr %tmp, ptr %ptr
ret %struct.uint8x16x4_t %ld
}
diff --git a/llvm/test/CodeGen/ARM/arm-vlddup-update.ll b/llvm/test/CodeGen/ARM/arm-vlddup-update.ll
index 28740fa1953a8..d4b2f0203bde7 100644
--- a/llvm/test/CodeGen/ARM/arm-vlddup-update.ll
+++ b/llvm/test/CodeGen/ARM/arm-vlddup-update.ll
@@ -29,467 +29,467 @@
%struct.uint8x16x3_t = type { <16 x i8>, <16 x i8>, <16 x i8> }
%struct.uint8x16x4_t = type { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }
-declare %struct.uint8x8x2_t @llvm.arm.neon.vld2dup.v8i8.p0i8(i8*, i32)
-declare %struct.uint16x4x2_t @llvm.arm.neon.vld2dup.v4i16.p0i8(i8*, i32)
-declare %struct.uint32x2x2_t @llvm.arm.neon.vld2dup.v2i32.p0i8(i8*, i32)
-declare %struct.uint64x1x2_t @llvm.arm.neon.vld2dup.v1i64.p0i8(i8*, i32)
-
-declare %struct.uint8x8x3_t @llvm.arm.neon.vld3dup.v8i8.p0i8(i8*, i32)
-declare %struct.uint16x4x3_t @llvm.arm.neon.vld3dup.v4i16.p0i8(i8*, i32)
-declare %struct.uint32x2x3_t @llvm.arm.neon.vld3dup.v2i32.p0i8(i8*, i32)
-declare %struct.uint64x1x3_t @llvm.arm.neon.vld3dup.v1i64.p0i8(i8*, i32)
-
-declare %struct.uint8x8x4_t @llvm.arm.neon.vld4dup.v8i8.p0i8(i8*, i32)
-declare %struct.uint16x4x4_t @llvm.arm.neon.vld4dup.v4i16.p0i8(i8*, i32)
-declare %struct.uint32x2x4_t @llvm.arm.neon.vld4dup.v2i32.p0i8(i8*, i32)
-declare %struct.uint64x1x4_t @llvm.arm.neon.vld4dup.v1i64.p0i8(i8*, i32)
-
-declare %struct.uint8x16x2_t @llvm.arm.neon.vld2dup.v16i8.p0i8(i8*, i32)
-declare %struct.uint16x8x2_t @llvm.arm.neon.vld2dup.v8i16.p0i8(i8*, i32)
-declare %struct.uint32x4x2_t @llvm.arm.neon.vld2dup.v4i32.p0i8(i8*, i32)
-
-declare %struct.uint8x16x3_t @llvm.arm.neon.vld3dup.v16i8.p0i8(i8*, i32)
-declare %struct.uint16x8x3_t @llvm.arm.neon.vld3dup.v8i16.p0i8(i8*, i32)
-declare %struct.uint32x4x3_t @llvm.arm.neon.vld3dup.v4i32.p0i8(i8*, i32)
-
-declare %struct.uint8x16x4_t @llvm.arm.neon.vld4dup.v16i8.p0i8(i8*, i32)
-declare %struct.uint16x8x4_t @llvm.arm.neon.vld4dup.v8i16.p0i8(i8*, i32)
-declare %struct.uint32x4x4_t @llvm.arm.neon.vld4dup.v4i32.p0i8(i8*, i32)
-
-define i8* @test_vld2_dup_u16_update(%struct.uint16x4x2_t* %dest, i8* %src) {
+declare %struct.uint8x8x2_t @llvm.arm.neon.vld2dup.v8i8.p0(ptr, i32)
+declare %struct.uint16x4x2_t @llvm.arm.neon.vld2dup.v4i16.p0(ptr, i32)
+declare %struct.uint32x2x2_t @llvm.arm.neon.vld2dup.v2i32.p0(ptr, i32)
+declare %struct.uint64x1x2_t @llvm.arm.neon.vld2dup.v1i64.p0(ptr, i32)
+
+declare %struct.uint8x8x3_t @llvm.arm.neon.vld3dup.v8i8.p0(ptr, i32)
+declare %struct.uint16x4x3_t @llvm.arm.neon.vld3dup.v4i16.p0(ptr, i32)
+declare %struct.uint32x2x3_t @llvm.arm.neon.vld3dup.v2i32.p0(ptr, i32)
+declare %struct.uint64x1x3_t @llvm.arm.neon.vld3dup.v1i64.p0(ptr, i32)
+
+declare %struct.uint8x8x4_t @llvm.arm.neon.vld4dup.v8i8.p0(ptr, i32)
+declare %struct.uint16x4x4_t @llvm.arm.neon.vld4dup.v4i16.p0(ptr, i32)
+declare %struct.uint32x2x4_t @llvm.arm.neon.vld4dup.v2i32.p0(ptr, i32)
+declare %struct.uint64x1x4_t @llvm.arm.neon.vld4dup.v1i64.p0(ptr, i32)
+
+declare %struct.uint8x16x2_t @llvm.arm.neon.vld2dup.v16i8.p0(ptr, i32)
+declare %struct.uint16x8x2_t @llvm.arm.neon.vld2dup.v8i16.p0(ptr, i32)
+declare %struct.uint32x4x2_t @llvm.arm.neon.vld2dup.v4i32.p0(ptr, i32)
+
+declare %struct.uint8x16x3_t @llvm.arm.neon.vld3dup.v16i8.p0(ptr, i32)
+declare %struct.uint16x8x3_t @llvm.arm.neon.vld3dup.v8i16.p0(ptr, i32)
+declare %struct.uint32x4x3_t @llvm.arm.neon.vld3dup.v4i32.p0(ptr, i32)
+
+declare %struct.uint8x16x4_t @llvm.arm.neon.vld4dup.v16i8.p0(ptr, i32)
+declare %struct.uint16x8x4_t @llvm.arm.neon.vld4dup.v8i16.p0(ptr, i32)
+declare %struct.uint32x4x4_t @llvm.arm.neon.vld4dup.v4i32.p0(ptr, i32)
+
+define ptr @test_vld2_dup_u16_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld2_dup_u16_update:
; CHECK: vld2.16 {d16[], d17[]}, [r1]!
entry:
- %tmp = tail call %struct.uint16x4x2_t @llvm.arm.neon.vld2dup.v4i16.p0i8(i8* %src, i32 2)
- store %struct.uint16x4x2_t %tmp, %struct.uint16x4x2_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 4
- ret i8* %updated_src
+ %tmp = tail call %struct.uint16x4x2_t @llvm.arm.neon.vld2dup.v4i16.p0(ptr %src, i32 2)
+ store %struct.uint16x4x2_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 4
+ ret ptr %updated_src
}
-define i8* @test_vld2_dup_u16_update_reg(%struct.uint16x4x2_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld2_dup_u16_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld2_dup_u16_update_reg:
; CHECK: vld2.16 {d16[], d17[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint16x4x2_t @llvm.arm.neon.vld2dup.v4i16.p0i8(i8* %src, i32 2)
- store %struct.uint16x4x2_t %tmp, %struct.uint16x4x2_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint16x4x2_t @llvm.arm.neon.vld2dup.v4i16.p0(ptr %src, i32 2)
+ store %struct.uint16x4x2_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld2_dup_update(%struct.uint32x2x2_t* %dest, i8* %src) {
+define ptr @test_vld2_dup_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld2_dup_update:
; CHECK: vld2.32 {d16[], d17[]}, [r1]!
entry:
- %tmp = tail call %struct.uint32x2x2_t @llvm.arm.neon.vld2dup.v2i32.p0i8(i8* %src, i32 4)
- store %struct.uint32x2x2_t %tmp, %struct.uint32x2x2_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 8
- ret i8* %updated_src
+ %tmp = tail call %struct.uint32x2x2_t @llvm.arm.neon.vld2dup.v2i32.p0(ptr %src, i32 4)
+ store %struct.uint32x2x2_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 8
+ ret ptr %updated_src
}
-define i8* @test_vld2_dup_update_reg(%struct.uint32x2x2_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld2_dup_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld2_dup_update_reg:
; CHECK: vld2.32 {d16[], d17[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint32x2x2_t @llvm.arm.neon.vld2dup.v2i32.p0i8(i8* %src, i32 4)
- store %struct.uint32x2x2_t %tmp, %struct.uint32x2x2_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint32x2x2_t @llvm.arm.neon.vld2dup.v2i32.p0(ptr %src, i32 4)
+ store %struct.uint32x2x2_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld2_dup_u64_update(%struct.uint64x1x2_t* %dest, i8* %src) {
+define ptr @test_vld2_dup_u64_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld2_dup_u64_update:
; CHECK: vld1.64 {d16, d17}, [r1:64]!
entry:
- %tmp = tail call %struct.uint64x1x2_t @llvm.arm.neon.vld2dup.v1i64.p0i8(i8* %src, i32 8)
- store %struct.uint64x1x2_t %tmp, %struct.uint64x1x2_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 16
- ret i8* %updated_src
+ %tmp = tail call %struct.uint64x1x2_t @llvm.arm.neon.vld2dup.v1i64.p0(ptr %src, i32 8)
+ store %struct.uint64x1x2_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 16
+ ret ptr %updated_src
}
-define i8* @test_vld2_dup_u64_update_reg(%struct.uint64x1x2_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld2_dup_u64_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld2_dup_u64_update_reg:
; CHECK: vld1.64 {d16, d17}, [r1:64], r2
entry:
- %tmp = tail call %struct.uint64x1x2_t @llvm.arm.neon.vld2dup.v1i64.p0i8(i8* %src, i32 8)
- store %struct.uint64x1x2_t %tmp, %struct.uint64x1x2_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint64x1x2_t @llvm.arm.neon.vld2dup.v1i64.p0(ptr %src, i32 8)
+ store %struct.uint64x1x2_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld2_dup_u8_update(%struct.uint8x8x2_t* %dest, i8* %src) {
+define ptr @test_vld2_dup_u8_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld2_dup_u8_update:
; CHECK: vld2.8 {d16[], d17[]}, [r1]!
entry:
- %tmp = tail call %struct.uint8x8x2_t @llvm.arm.neon.vld2dup.v8i8.p0i8(i8* %src, i32 1)
- store %struct.uint8x8x2_t %tmp, %struct.uint8x8x2_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 2
- ret i8* %updated_src
+ %tmp = tail call %struct.uint8x8x2_t @llvm.arm.neon.vld2dup.v8i8.p0(ptr %src, i32 1)
+ store %struct.uint8x8x2_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 2
+ ret ptr %updated_src
}
-define i8* @test_vld2_dup_u8_update_reg(%struct.uint8x8x2_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld2_dup_u8_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld2_dup_u8_update_reg:
; CHECK: vld2.8 {d16[], d17[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint8x8x2_t @llvm.arm.neon.vld2dup.v8i8.p0i8(i8* %src, i32 1)
- store %struct.uint8x8x2_t %tmp, %struct.uint8x8x2_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint8x8x2_t @llvm.arm.neon.vld2dup.v8i8.p0(ptr %src, i32 1)
+ store %struct.uint8x8x2_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld3_dup_u16_update(%struct.uint16x4x3_t* %dest, i8* %src) {
+define ptr @test_vld3_dup_u16_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld3_dup_u16_update:
; CHECK: vld3.16 {d16[], d17[], d18[]}, [r1]!
entry:
- %tmp = tail call %struct.uint16x4x3_t @llvm.arm.neon.vld3dup.v4i16.p0i8(i8* %src, i32 2)
- store %struct.uint16x4x3_t %tmp, %struct.uint16x4x3_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 6
- ret i8* %updated_src
+ %tmp = tail call %struct.uint16x4x3_t @llvm.arm.neon.vld3dup.v4i16.p0(ptr %src, i32 2)
+ store %struct.uint16x4x3_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 6
+ ret ptr %updated_src
}
-define i8* @test_vld3_dup_u16_update_reg(%struct.uint16x4x3_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld3_dup_u16_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld3_dup_u16_update_reg:
; CHECK: vld3.16 {d16[], d17[], d18[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint16x4x3_t @llvm.arm.neon.vld3dup.v4i16.p0i8(i8* %src, i32 2)
- store %struct.uint16x4x3_t %tmp, %struct.uint16x4x3_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint16x4x3_t @llvm.arm.neon.vld3dup.v4i16.p0(ptr %src, i32 2)
+ store %struct.uint16x4x3_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld3_dup_u32_update(%struct.uint32x2x3_t* %dest, i8* %src) {
+define ptr @test_vld3_dup_u32_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld3_dup_u32_update:
; CHECK: vld3.32 {d16[], d17[], d18[]}, [r1]!
entry:
- %tmp = tail call %struct.uint32x2x3_t @llvm.arm.neon.vld3dup.v2i32.p0i8(i8* %src, i32 4)
- store %struct.uint32x2x3_t %tmp, %struct.uint32x2x3_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 12
- ret i8* %updated_src
+ %tmp = tail call %struct.uint32x2x3_t @llvm.arm.neon.vld3dup.v2i32.p0(ptr %src, i32 4)
+ store %struct.uint32x2x3_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 12
+ ret ptr %updated_src
}
-define i8* @test_vld3_dup_u32_update_reg(%struct.uint32x2x3_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld3_dup_u32_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld3_dup_u32_update_reg:
; CHECK: vld3.32 {d16[], d17[], d18[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint32x2x3_t @llvm.arm.neon.vld3dup.v2i32.p0i8(i8* %src, i32 4)
- store %struct.uint32x2x3_t %tmp, %struct.uint32x2x3_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint32x2x3_t @llvm.arm.neon.vld3dup.v2i32.p0(ptr %src, i32 4)
+ store %struct.uint32x2x3_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld3_dup_u64_update(%struct.uint64x1x3_t* %dest, i8* %src) {
+define ptr @test_vld3_dup_u64_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld3_dup_u64_update:
; CHECK: vld1.64 {d16, d17, d18}, [r1]!
entry:
- %tmp = tail call %struct.uint64x1x3_t @llvm.arm.neon.vld3dup.v1i64.p0i8(i8* %src, i32 8)
- store %struct.uint64x1x3_t %tmp, %struct.uint64x1x3_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 24
- ret i8* %updated_src
+ %tmp = tail call %struct.uint64x1x3_t @llvm.arm.neon.vld3dup.v1i64.p0(ptr %src, i32 8)
+ store %struct.uint64x1x3_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 24
+ ret ptr %updated_src
}
-define i8* @test_vld3_dup_u64_update_reg(%struct.uint64x1x3_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld3_dup_u64_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld3_dup_u64_update_reg:
; CHECK: vld1.64 {d16, d17, d18}, [r1], r2
entry:
- %tmp = tail call %struct.uint64x1x3_t @llvm.arm.neon.vld3dup.v1i64.p0i8(i8* %src, i32 8)
- store %struct.uint64x1x3_t %tmp, %struct.uint64x1x3_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint64x1x3_t @llvm.arm.neon.vld3dup.v1i64.p0(ptr %src, i32 8)
+ store %struct.uint64x1x3_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld3_dup_u8_update(%struct.uint8x8x3_t* %dest, i8* %src) {
+define ptr @test_vld3_dup_u8_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld3_dup_u8_update:
; CHECK: vld3.8 {d16[], d17[], d18[]}, [r1]!
entry:
- %tmp = tail call %struct.uint8x8x3_t @llvm.arm.neon.vld3dup.v8i8.p0i8(i8* %src, i32 1)
- store %struct.uint8x8x3_t %tmp, %struct.uint8x8x3_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 3
- ret i8* %updated_src
+ %tmp = tail call %struct.uint8x8x3_t @llvm.arm.neon.vld3dup.v8i8.p0(ptr %src, i32 1)
+ store %struct.uint8x8x3_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 3
+ ret ptr %updated_src
}
-define i8* @test_vld3_dup_u8_update_reg(%struct.uint8x8x3_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld3_dup_u8_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld3_dup_u8_update_reg:
; CHECK: vld3.8 {d16[], d17[], d18[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint8x8x3_t @llvm.arm.neon.vld3dup.v8i8.p0i8(i8* %src, i32 1)
- store %struct.uint8x8x3_t %tmp, %struct.uint8x8x3_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint8x8x3_t @llvm.arm.neon.vld3dup.v8i8.p0(ptr %src, i32 1)
+ store %struct.uint8x8x3_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld4_dup_u16_update(%struct.uint16x4x4_t* %dest, i8* %src) {
+define ptr @test_vld4_dup_u16_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld4_dup_u16_update:
; CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r1]!
entry:
- %tmp = tail call %struct.uint16x4x4_t @llvm.arm.neon.vld4dup.v4i16.p0i8(i8* %src, i32 2)
- store %struct.uint16x4x4_t %tmp, %struct.uint16x4x4_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 8
- ret i8* %updated_src
+ %tmp = tail call %struct.uint16x4x4_t @llvm.arm.neon.vld4dup.v4i16.p0(ptr %src, i32 2)
+ store %struct.uint16x4x4_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 8
+ ret ptr %updated_src
}
-define i8* @test_vld4_dup_u16_update_reg(%struct.uint16x4x4_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld4_dup_u16_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld4_dup_u16_update_reg:
; CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint16x4x4_t @llvm.arm.neon.vld4dup.v4i16.p0i8(i8* %src, i32 2)
- store %struct.uint16x4x4_t %tmp, %struct.uint16x4x4_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint16x4x4_t @llvm.arm.neon.vld4dup.v4i16.p0(ptr %src, i32 2)
+ store %struct.uint16x4x4_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld4_dup_u32_update(%struct.uint32x2x4_t* %dest, i8* %src) {
+define ptr @test_vld4_dup_u32_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld4_dup_u32_update:
; CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r1]!
entry:
- %tmp = tail call %struct.uint32x2x4_t @llvm.arm.neon.vld4dup.v2i32.p0i8(i8* %src, i32 4)
- store %struct.uint32x2x4_t %tmp, %struct.uint32x2x4_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 16
- ret i8* %updated_src
+ %tmp = tail call %struct.uint32x2x4_t @llvm.arm.neon.vld4dup.v2i32.p0(ptr %src, i32 4)
+ store %struct.uint32x2x4_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 16
+ ret ptr %updated_src
}
-define i8* @test_vld4_dup_u32_update_reg(%struct.uint32x2x4_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld4_dup_u32_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld4_dup_u32_update_reg:
; CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint32x2x4_t @llvm.arm.neon.vld4dup.v2i32.p0i8(i8* %src, i32 4)
- store %struct.uint32x2x4_t %tmp, %struct.uint32x2x4_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint32x2x4_t @llvm.arm.neon.vld4dup.v2i32.p0(ptr %src, i32 4)
+ store %struct.uint32x2x4_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld4_dup_u64_update(%struct.uint64x1x4_t* %dest, i8* %src) {
+define ptr @test_vld4_dup_u64_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld4_dup_u64_update:
; CHECK: vld1.64 {d16, d17, d18, d19}, [r1:64]!
entry:
- %tmp = tail call %struct.uint64x1x4_t @llvm.arm.neon.vld4dup.v1i64.p0i8(i8* %src, i32 8)
- store %struct.uint64x1x4_t %tmp, %struct.uint64x1x4_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 32
- ret i8* %updated_src
+ %tmp = tail call %struct.uint64x1x4_t @llvm.arm.neon.vld4dup.v1i64.p0(ptr %src, i32 8)
+ store %struct.uint64x1x4_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 32
+ ret ptr %updated_src
}
-define i8* @test_vld4_dup_u64_update_reg(%struct.uint64x1x4_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld4_dup_u64_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld4_dup_u64_update_reg:
; CHECK: vld1.64 {d16, d17, d18, d19}, [r1:64], r2
entry:
- %tmp = tail call %struct.uint64x1x4_t @llvm.arm.neon.vld4dup.v1i64.p0i8(i8* %src, i32 8)
- store %struct.uint64x1x4_t %tmp, %struct.uint64x1x4_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint64x1x4_t @llvm.arm.neon.vld4dup.v1i64.p0(ptr %src, i32 8)
+ store %struct.uint64x1x4_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld4_dup_u8_update(%struct.uint8x8x4_t* %dest, i8* %src) {
+define ptr @test_vld4_dup_u8_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld4_dup_u8_update:
; CHECK: vld4.8 {d16[], d17[], d18[], d19[]}, [r1]!
entry:
- %tmp = tail call %struct.uint8x8x4_t @llvm.arm.neon.vld4dup.v8i8.p0i8(i8* %src, i32 1)
- store %struct.uint8x8x4_t %tmp, %struct.uint8x8x4_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 4
- ret i8* %updated_src
+ %tmp = tail call %struct.uint8x8x4_t @llvm.arm.neon.vld4dup.v8i8.p0(ptr %src, i32 1)
+ store %struct.uint8x8x4_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 4
+ ret ptr %updated_src
}
-define i8* @test_vld4_dup_u8_update_reg(%struct.uint8x8x4_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld4_dup_u8_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld4_dup_u8_update_reg:
; CHECK: vld4.8 {d16[], d17[], d18[], d19[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint8x8x4_t @llvm.arm.neon.vld4dup.v8i8.p0i8(i8* %src, i32 1)
- store %struct.uint8x8x4_t %tmp, %struct.uint8x8x4_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint8x8x4_t @llvm.arm.neon.vld4dup.v8i8.p0(ptr %src, i32 1)
+ store %struct.uint8x8x4_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld2q_dup_u16_update(%struct.uint16x8x2_t* %dest, i8* %src, <8 x i16>* %dest0) {
+define ptr @test_vld2q_dup_u16_update(ptr %dest, ptr %src, ptr %dest0) {
; CHECK-LABEL: test_vld2q_dup_u16_update:
; CHECK: vld2.16 {d16[], d18[]}, [r1]
; CHECK-NEXT: vld2.16 {d17[], d19[]}, [r1]!
entry:
- %tmp = tail call %struct.uint16x8x2_t @llvm.arm.neon.vld2dup.v8i16.p0i8(i8* %src, i32 2)
- store %struct.uint16x8x2_t %tmp, %struct.uint16x8x2_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 4
- ret i8* %updated_src
+ %tmp = tail call %struct.uint16x8x2_t @llvm.arm.neon.vld2dup.v8i16.p0(ptr %src, i32 2)
+ store %struct.uint16x8x2_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 4
+ ret ptr %updated_src
}
-define i8* @test_vld2q_dup_u16_update_reg(%struct.uint16x8x2_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld2q_dup_u16_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld2q_dup_u16_update_reg:
; CHECK: vld2.16 {d16[], d18[]}, [r1]
; CHECK-NEXT: vld2.16 {d17[], d19[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint16x8x2_t @llvm.arm.neon.vld2dup.v8i16.p0i8(i8* %src, i32 2)
- store %struct.uint16x8x2_t %tmp, %struct.uint16x8x2_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint16x8x2_t @llvm.arm.neon.vld2dup.v8i16.p0(ptr %src, i32 2)
+ store %struct.uint16x8x2_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld2q_dup_u32_update(%struct.uint32x4x2_t* %dest, i8* %src) {
+define ptr @test_vld2q_dup_u32_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld2q_dup_u32_update:
; CHECK: vld2.32 {d16[], d18[]}, [r1]
; CHECK-NEXT: vld2.32 {d17[], d19[]}, [r1]!
entry:
- %tmp = tail call %struct.uint32x4x2_t @llvm.arm.neon.vld2dup.v4i32.p0i8(i8* %src, i32 4)
- store %struct.uint32x4x2_t %tmp, %struct.uint32x4x2_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 8
- ret i8* %updated_src
+ %tmp = tail call %struct.uint32x4x2_t @llvm.arm.neon.vld2dup.v4i32.p0(ptr %src, i32 4)
+ store %struct.uint32x4x2_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 8
+ ret ptr %updated_src
}
-define i8* @test_vld2q_dup_u32_update_reg(%struct.uint32x4x2_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld2q_dup_u32_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld2q_dup_u32_update_reg:
; CHECK: vld2.32 {d16[], d18[]}, [r1]
; CHECK-NEXT: vld2.32 {d17[], d19[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint32x4x2_t @llvm.arm.neon.vld2dup.v4i32.p0i8(i8* %src, i32 4)
- store %struct.uint32x4x2_t %tmp, %struct.uint32x4x2_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint32x4x2_t @llvm.arm.neon.vld2dup.v4i32.p0(ptr %src, i32 4)
+ store %struct.uint32x4x2_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld2q_dup_u8_update(%struct.uint8x16x2_t* %dest, i8* %src) {
+define ptr @test_vld2q_dup_u8_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld2q_dup_u8_update:
; CHECK: vld2.8 {d16[], d18[]}, [r1]
; CHECK-NEXT: vld2.8 {d17[], d19[]}, [r1]!
entry:
- %tmp = tail call %struct.uint8x16x2_t @llvm.arm.neon.vld2dup.v16i8.p0i8(i8* %src, i32 1)
- store %struct.uint8x16x2_t %tmp, %struct.uint8x16x2_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 2
- ret i8* %updated_src
+ %tmp = tail call %struct.uint8x16x2_t @llvm.arm.neon.vld2dup.v16i8.p0(ptr %src, i32 1)
+ store %struct.uint8x16x2_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 2
+ ret ptr %updated_src
}
-define i8* @test_vld2q_dup_u8_update_reg(%struct.uint8x16x2_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld2q_dup_u8_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld2q_dup_u8_update_reg:
; CHECK: vld2.8 {d16[], d18[]}, [r1]
; CHECK-NEXT: vld2.8 {d17[], d19[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint8x16x2_t @llvm.arm.neon.vld2dup.v16i8.p0i8(i8* %src, i32 1)
- store %struct.uint8x16x2_t %tmp, %struct.uint8x16x2_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint8x16x2_t @llvm.arm.neon.vld2dup.v16i8.p0(ptr %src, i32 1)
+ store %struct.uint8x16x2_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld3q_dup_u16_update(%struct.uint16x8x3_t* %dest, i8* %src) {
+define ptr @test_vld3q_dup_u16_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld3q_dup_u16_update:
; CHECK: vld3.16 {d16[], d18[], d20[]}, [r1]
; CHECK: vld3.16 {d17[], d19[], d21[]}, [r1]!
entry:
- %tmp = tail call %struct.uint16x8x3_t @llvm.arm.neon.vld3dup.v8i16.p0i8(i8* %src, i32 2)
- store %struct.uint16x8x3_t %tmp, %struct.uint16x8x3_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 6
- ret i8* %updated_src
+ %tmp = tail call %struct.uint16x8x3_t @llvm.arm.neon.vld3dup.v8i16.p0(ptr %src, i32 2)
+ store %struct.uint16x8x3_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 6
+ ret ptr %updated_src
}
-define i8* @test_vld3q_dup_u16_update_reg(%struct.uint16x8x3_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld3q_dup_u16_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld3q_dup_u16_update_reg:
; CHECK: vld3.16 {d16[], d18[], d20[]}, [r1]
; CHECK-NEXT: vld3.16 {d17[], d19[], d21[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint16x8x3_t @llvm.arm.neon.vld3dup.v8i16.p0i8(i8* %src, i32 2)
- store %struct.uint16x8x3_t %tmp, %struct.uint16x8x3_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint16x8x3_t @llvm.arm.neon.vld3dup.v8i16.p0(ptr %src, i32 2)
+ store %struct.uint16x8x3_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld3q_dup_u32_update(%struct.uint32x4x3_t* %dest, i8* %src) {
+define ptr @test_vld3q_dup_u32_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld3q_dup_u32_update:
; CHECK: vld3.32 {d16[], d18[], d20[]}, [r1]
; CHECK: vld3.32 {d17[], d19[], d21[]}, [r1]!
entry:
- %tmp = tail call %struct.uint32x4x3_t @llvm.arm.neon.vld3dup.v4i32.p0i8(i8* %src, i32 4)
- store %struct.uint32x4x3_t %tmp, %struct.uint32x4x3_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 12
- ret i8* %updated_src
+ %tmp = tail call %struct.uint32x4x3_t @llvm.arm.neon.vld3dup.v4i32.p0(ptr %src, i32 4)
+ store %struct.uint32x4x3_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 12
+ ret ptr %updated_src
}
-define i8* @test_vld3q_dup_u32_update_reg(%struct.uint32x4x3_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld3q_dup_u32_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld3q_dup_u32_update_reg:
; CHECK: vld3.32 {d16[], d18[], d20[]}, [r1]
; CHECK-NEXT: vld3.32 {d17[], d19[], d21[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint32x4x3_t @llvm.arm.neon.vld3dup.v4i32.p0i8(i8* %src, i32 4)
- store %struct.uint32x4x3_t %tmp, %struct.uint32x4x3_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint32x4x3_t @llvm.arm.neon.vld3dup.v4i32.p0(ptr %src, i32 4)
+ store %struct.uint32x4x3_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld3q_dup_u8_update(%struct.uint8x16x3_t* %dest, i8* %src) {
+define ptr @test_vld3q_dup_u8_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld3q_dup_u8_update:
; CHECK: vld3.8 {d16[], d18[], d20[]}, [r1]
; CHECK: vld3.8 {d17[], d19[], d21[]}, [r1]!
entry:
- %tmp = tail call %struct.uint8x16x3_t @llvm.arm.neon.vld3dup.v16i8.p0i8(i8* %src, i32 1)
- store %struct.uint8x16x3_t %tmp, %struct.uint8x16x3_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 3
- ret i8* %updated_src
+ %tmp = tail call %struct.uint8x16x3_t @llvm.arm.neon.vld3dup.v16i8.p0(ptr %src, i32 1)
+ store %struct.uint8x16x3_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 3
+ ret ptr %updated_src
}
-define i8* @test_vld3q_dup_u8_update_reg(%struct.uint8x16x3_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld3q_dup_u8_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld3q_dup_u8_update_reg:
; CHECK: vld3.8 {d16[], d18[], d20[]}, [r1]
; CHECK-NEXT: vld3.8 {d17[], d19[], d21[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint8x16x3_t @llvm.arm.neon.vld3dup.v16i8.p0i8(i8* %src, i32 1)
- store %struct.uint8x16x3_t %tmp, %struct.uint8x16x3_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint8x16x3_t @llvm.arm.neon.vld3dup.v16i8.p0(ptr %src, i32 1)
+ store %struct.uint8x16x3_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld4q_dup_u16_update(%struct.uint16x8x4_t* %dest, i8* %src) {
+define ptr @test_vld4q_dup_u16_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld4q_dup_u16_update:
; CHECK: vld4.16 {d16[], d18[], d20[], d22[]}, [r1]
; CHECK: vld4.16 {d17[], d19[], d21[], d23[]}, [r1]!
entry:
- %tmp = tail call %struct.uint16x8x4_t @llvm.arm.neon.vld4dup.v8i16.p0i8(i8* %src, i32 2)
- store %struct.uint16x8x4_t %tmp, %struct.uint16x8x4_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 8
- ret i8* %updated_src
+ %tmp = tail call %struct.uint16x8x4_t @llvm.arm.neon.vld4dup.v8i16.p0(ptr %src, i32 2)
+ store %struct.uint16x8x4_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 8
+ ret ptr %updated_src
}
-define i8* @test_vld4q_dup_u16_update_reg(%struct.uint16x8x4_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld4q_dup_u16_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld4q_dup_u16_update_reg:
; CHECK: vld4.16 {d16[], d18[], d20[], d22[]}, [r1]
; CHECK-NEXT: vld4.16 {d17[], d19[], d21[], d23[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint16x8x4_t @llvm.arm.neon.vld4dup.v8i16.p0i8(i8* %src, i32 2)
- store %struct.uint16x8x4_t %tmp, %struct.uint16x8x4_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint16x8x4_t @llvm.arm.neon.vld4dup.v8i16.p0(ptr %src, i32 2)
+ store %struct.uint16x8x4_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld4q_dup_u32_update(%struct.uint32x4x4_t* %dest, i8* %src) {
+define ptr @test_vld4q_dup_u32_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld4q_dup_u32_update:
; CHECK: vld4.32 {d16[], d18[], d20[], d22[]}, [r1]
; CHECK: vld4.32 {d17[], d19[], d21[], d23[]}, [r1]!
entry:
- %tmp = tail call %struct.uint32x4x4_t @llvm.arm.neon.vld4dup.v4i32.p0i8(i8* %src, i32 4)
- store %struct.uint32x4x4_t %tmp, %struct.uint32x4x4_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 16
- ret i8* %updated_src
+ %tmp = tail call %struct.uint32x4x4_t @llvm.arm.neon.vld4dup.v4i32.p0(ptr %src, i32 4)
+ store %struct.uint32x4x4_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 16
+ ret ptr %updated_src
}
-define i8* @test_vld4q_dup_u32_update_reg(%struct.uint32x4x4_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld4q_dup_u32_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld4q_dup_u32_update_reg:
; CHECK: vld4.32 {d16[], d18[], d20[], d22[]}, [r1]
; CHECK-NEXT: vld4.32 {d17[], d19[], d21[], d23[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint32x4x4_t @llvm.arm.neon.vld4dup.v4i32.p0i8(i8* %src, i32 4)
- store %struct.uint32x4x4_t %tmp, %struct.uint32x4x4_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint32x4x4_t @llvm.arm.neon.vld4dup.v4i32.p0(ptr %src, i32 4)
+ store %struct.uint32x4x4_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
-define i8* @test_vld4q_dup_u8_update(%struct.uint8x16x4_t* %dest, i8* %src) {
+define ptr @test_vld4q_dup_u8_update(ptr %dest, ptr %src) {
; CHECK-LABEL: test_vld4q_dup_u8_update:
; CHECK: vld4.8 {d16[], d18[], d20[], d22[]}, [r1]
; CHECK: vld4.8 {d17[], d19[], d21[], d23[]}, [r1]!
entry:
- %tmp = tail call %struct.uint8x16x4_t @llvm.arm.neon.vld4dup.v16i8.p0i8(i8* %src, i32 1)
- store %struct.uint8x16x4_t %tmp, %struct.uint8x16x4_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 4
- ret i8* %updated_src
+ %tmp = tail call %struct.uint8x16x4_t @llvm.arm.neon.vld4dup.v16i8.p0(ptr %src, i32 1)
+ store %struct.uint8x16x4_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 4
+ ret ptr %updated_src
}
-define i8* @test_vld4q_dup_u8_update_reg(%struct.uint8x16x4_t* %dest, i8* %src, i32 %inc) {
+define ptr @test_vld4q_dup_u8_update_reg(ptr %dest, ptr %src, i32 %inc) {
; CHECK-LABEL: test_vld4q_dup_u8_update_reg:
; CHECK: vld4.8 {d16[], d18[], d20[], d22[]}, [r1]
; CHECK-NEXT: vld4.8 {d17[], d19[], d21[], d23[]}, [r1], r2
entry:
- %tmp = tail call %struct.uint8x16x4_t @llvm.arm.neon.vld4dup.v16i8.p0i8(i8* %src, i32 1)
- store %struct.uint8x16x4_t %tmp, %struct.uint8x16x4_t* %dest, align 8
- %updated_src = getelementptr inbounds i8, i8* %src, i32 %inc
- ret i8* %updated_src
+ %tmp = tail call %struct.uint8x16x4_t @llvm.arm.neon.vld4dup.v16i8.p0(ptr %src, i32 1)
+ store %struct.uint8x16x4_t %tmp, ptr %dest, align 8
+ %updated_src = getelementptr inbounds i8, ptr %src, i32 %inc
+ ret ptr %updated_src
}
diff --git a/llvm/test/CodeGen/ARM/arm-vlddup.ll b/llvm/test/CodeGen/ARM/arm-vlddup.ll
index e43b80f2addac..c22d1374761f3 100644
--- a/llvm/test/CodeGen/ARM/arm-vlddup.ll
+++ b/llvm/test/CodeGen/ARM/arm-vlddup.ll
@@ -29,206 +29,206 @@
%struct.uint8x16x3_t = type { <16 x i8>, <16 x i8>, <16 x i8> }
%struct.uint8x16x4_t = type { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }
-declare %struct.uint8x8x2_t @llvm.arm.neon.vld2dup.v8i8.p0i8(i8*, i32)
-declare %struct.uint16x4x2_t @llvm.arm.neon.vld2dup.v4i16.p0i8(i8*, i32)
-declare %struct.uint32x2x2_t @llvm.arm.neon.vld2dup.v2i32.p0i8(i8*, i32)
-declare %struct.uint64x1x2_t @llvm.arm.neon.vld2dup.v1i64.p0i8(i8*, i32)
+declare %struct.uint8x8x2_t @llvm.arm.neon.vld2dup.v8i8.p0(ptr, i32)
+declare %struct.uint16x4x2_t @llvm.arm.neon.vld2dup.v4i16.p0(ptr, i32)
+declare %struct.uint32x2x2_t @llvm.arm.neon.vld2dup.v2i32.p0(ptr, i32)
+declare %struct.uint64x1x2_t @llvm.arm.neon.vld2dup.v1i64.p0(ptr, i32)
-declare %struct.uint8x8x3_t @llvm.arm.neon.vld3dup.v8i8.p0i8(i8*, i32)
-declare %struct.uint16x4x3_t @llvm.arm.neon.vld3dup.v4i16.p0i8(i8*, i32)
-declare %struct.uint32x2x3_t @llvm.arm.neon.vld3dup.v2i32.p0i8(i8*, i32)
-declare %struct.uint64x1x3_t @llvm.arm.neon.vld3dup.v1i64.p0i8(i8*, i32)
+declare %struct.uint8x8x3_t @llvm.arm.neon.vld3dup.v8i8.p0(ptr, i32)
+declare %struct.uint16x4x3_t @llvm.arm.neon.vld3dup.v4i16.p0(ptr, i32)
+declare %struct.uint32x2x3_t @llvm.arm.neon.vld3dup.v2i32.p0(ptr, i32)
+declare %struct.uint64x1x3_t @llvm.arm.neon.vld3dup.v1i64.p0(ptr, i32)
-declare %struct.uint8x8x4_t @llvm.arm.neon.vld4dup.v8i8.p0i8(i8*, i32)
-declare %struct.uint16x4x4_t @llvm.arm.neon.vld4dup.v4i16.p0i8(i8*, i32)
-declare %struct.uint32x2x4_t @llvm.arm.neon.vld4dup.v2i32.p0i8(i8*, i32)
-declare %struct.uint64x1x4_t @llvm.arm.neon.vld4dup.v1i64.p0i8(i8*, i32)
+declare %struct.uint8x8x4_t @llvm.arm.neon.vld4dup.v8i8.p0(ptr, i32)
+declare %struct.uint16x4x4_t @llvm.arm.neon.vld4dup.v4i16.p0(ptr, i32)
+declare %struct.uint32x2x4_t @llvm.arm.neon.vld4dup.v2i32.p0(ptr, i32)
+declare %struct.uint64x1x4_t @llvm.arm.neon.vld4dup.v1i64.p0(ptr, i32)
-declare %struct.uint8x16x2_t @llvm.arm.neon.vld2dup.v16i8.p0i8(i8*, i32)
-declare %struct.uint16x8x2_t @llvm.arm.neon.vld2dup.v8i16.p0i8(i8*, i32)
-declare %struct.uint32x4x2_t @llvm.arm.neon.vld2dup.v4i32.p0i8(i8*, i32)
+declare %struct.uint8x16x2_t @llvm.arm.neon.vld2dup.v16i8.p0(ptr, i32)
+declare %struct.uint16x8x2_t @llvm.arm.neon.vld2dup.v8i16.p0(ptr, i32)
+declare %struct.uint32x4x2_t @llvm.arm.neon.vld2dup.v4i32.p0(ptr, i32)
-declare %struct.uint8x16x3_t @llvm.arm.neon.vld3dup.v16i8.p0i8(i8*, i32)
-declare %struct.uint16x8x3_t @llvm.arm.neon.vld3dup.v8i16.p0i8(i8*, i32)
-declare %struct.uint32x4x3_t @llvm.arm.neon.vld3dup.v4i32.p0i8(i8*, i32)
+declare %struct.uint8x16x3_t @llvm.arm.neon.vld3dup.v16i8.p0(ptr, i32)
+declare %struct.uint16x8x3_t @llvm.arm.neon.vld3dup.v8i16.p0(ptr, i32)
+declare %struct.uint32x4x3_t @llvm.arm.neon.vld3dup.v4i32.p0(ptr, i32)
-declare %struct.uint8x16x4_t @llvm.arm.neon.vld4dup.v16i8.p0i8(i8*, i32)
-declare %struct.uint16x8x4_t @llvm.arm.neon.vld4dup.v8i16.p0i8(i8*, i32)
-declare %struct.uint32x4x4_t @llvm.arm.neon.vld4dup.v4i32.p0i8(i8*, i32)
+declare %struct.uint8x16x4_t @llvm.arm.neon.vld4dup.v16i8.p0(ptr, i32)
+declare %struct.uint16x8x4_t @llvm.arm.neon.vld4dup.v8i16.p0(ptr, i32)
+declare %struct.uint32x4x4_t @llvm.arm.neon.vld4dup.v4i32.p0(ptr, i32)
; CHECK-LABEL: test_vld2_dup_u16
; CHECK: vld2.16 {d16[], d17[]}, [r0]
-define %struct.uint16x4x2_t @test_vld2_dup_u16(i8* %src) {
+define %struct.uint16x4x2_t @test_vld2_dup_u16(ptr %src) {
entry:
- %tmp = tail call %struct.uint16x4x2_t @llvm.arm.neon.vld2dup.v4i16.p0i8(i8* %src, i32 2)
+ %tmp = tail call %struct.uint16x4x2_t @llvm.arm.neon.vld2dup.v4i16.p0(ptr %src, i32 2)
ret %struct.uint16x4x2_t %tmp
}
; CHECK-LABEL: test_vld2_dup_u32
; CHECK: vld2.32 {d16[], d17[]}, [r0]
-define %struct.uint32x2x2_t @test_vld2_dup_u32(i8* %src) {
+define %struct.uint32x2x2_t @test_vld2_dup_u32(ptr %src) {
entry:
- %tmp = tail call %struct.uint32x2x2_t @llvm.arm.neon.vld2dup.v2i32.p0i8(i8* %src, i32 4)
+ %tmp = tail call %struct.uint32x2x2_t @llvm.arm.neon.vld2dup.v2i32.p0(ptr %src, i32 4)
ret %struct.uint32x2x2_t %tmp
}
; CHECK-LABEL: test_vld2_dup_u64
; CHECK: vld1.64 {d16, d17}, [r0:64]
-define %struct.uint64x1x2_t @test_vld2_dup_u64(i8* %src) {
+define %struct.uint64x1x2_t @test_vld2_dup_u64(ptr %src) {
entry:
- %tmp = tail call %struct.uint64x1x2_t @llvm.arm.neon.vld2dup.v1i64.p0i8(i8* %src, i32 8)
+ %tmp = tail call %struct.uint64x1x2_t @llvm.arm.neon.vld2dup.v1i64.p0(ptr %src, i32 8)
ret %struct.uint64x1x2_t %tmp
}
; CHECK-LABEL: test_vld2_dup_u8
; CHECK: vld2.8 {d16[], d17[]}, [r0]
-define %struct.uint8x8x2_t @test_vld2_dup_u8(i8* %src) {
+define %struct.uint8x8x2_t @test_vld2_dup_u8(ptr %src) {
entry:
- %tmp = tail call %struct.uint8x8x2_t @llvm.arm.neon.vld2dup.v8i8.p0i8(i8* %src, i32 1)
+ %tmp = tail call %struct.uint8x8x2_t @llvm.arm.neon.vld2dup.v8i8.p0(ptr %src, i32 1)
ret %struct.uint8x8x2_t %tmp
}
; CHECK-LABEL: test_vld3_dup_u16
; CHECK: vld3.16 {d16[], d17[], d18[]}, [r1]
-define %struct.uint16x4x3_t @test_vld3_dup_u16(i8* %src) {
+define %struct.uint16x4x3_t @test_vld3_dup_u16(ptr %src) {
entry:
- %tmp = tail call %struct.uint16x4x3_t @llvm.arm.neon.vld3dup.v4i16.p0i8(i8* %src, i32 2)
+ %tmp = tail call %struct.uint16x4x3_t @llvm.arm.neon.vld3dup.v4i16.p0(ptr %src, i32 2)
ret %struct.uint16x4x3_t %tmp
}
; CHECK-LABEL: test_vld3_dup_u32
; CHECK: vld3.32 {d16[], d17[], d18[]}, [r1]
-define %struct.uint32x2x3_t @test_vld3_dup_u32(i8* %src) {
+define %struct.uint32x2x3_t @test_vld3_dup_u32(ptr %src) {
entry:
- %tmp = tail call %struct.uint32x2x3_t @llvm.arm.neon.vld3dup.v2i32.p0i8(i8* %src, i32 4)
+ %tmp = tail call %struct.uint32x2x3_t @llvm.arm.neon.vld3dup.v2i32.p0(ptr %src, i32 4)
ret %struct.uint32x2x3_t %tmp
}
; CHECK-LABEL: test_vld3_dup_u64
; CHECK: vld1.64 {d16, d17, d18}, [r1]
-define %struct.uint64x1x3_t @test_vld3_dup_u64(i8* %src) {
+define %struct.uint64x1x3_t @test_vld3_dup_u64(ptr %src) {
entry:
- %tmp = tail call %struct.uint64x1x3_t @llvm.arm.neon.vld3dup.v1i64.p0i8(i8* %src, i32 8)
+ %tmp = tail call %struct.uint64x1x3_t @llvm.arm.neon.vld3dup.v1i64.p0(ptr %src, i32 8)
ret %struct.uint64x1x3_t %tmp
}
; CHECK-LABEL: test_vld3_dup_u8
; CHECK: vld3.8 {d16[], d17[], d18[]}, [r1]
-define %struct.uint8x8x3_t @test_vld3_dup_u8(i8* %src) {
+define %struct.uint8x8x3_t @test_vld3_dup_u8(ptr %src) {
entry:
- %tmp = tail call %struct.uint8x8x3_t @llvm.arm.neon.vld3dup.v8i8.p0i8(i8* %src, i32 1)
+ %tmp = tail call %struct.uint8x8x3_t @llvm.arm.neon.vld3dup.v8i8.p0(ptr %src, i32 1)
ret %struct.uint8x8x3_t %tmp
}
; CHECK-LABEL: test_vld4_dup_u16
; CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r1]
-define %struct.uint16x4x4_t @test_vld4_dup_u16(i8* %src) {
+define %struct.uint16x4x4_t @test_vld4_dup_u16(ptr %src) {
entry:
- %tmp = tail call %struct.uint16x4x4_t @llvm.arm.neon.vld4dup.v4i16.p0i8(i8* %src, i32 2)
+ %tmp = tail call %struct.uint16x4x4_t @llvm.arm.neon.vld4dup.v4i16.p0(ptr %src, i32 2)
ret %struct.uint16x4x4_t %tmp
}
; CHECK-LABEL: test_vld4_dup_u32
; CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r1]
-define %struct.uint32x2x4_t @test_vld4_dup_u32(i8* %src) {
+define %struct.uint32x2x4_t @test_vld4_dup_u32(ptr %src) {
entry:
- %tmp = tail call %struct.uint32x2x4_t @llvm.arm.neon.vld4dup.v2i32.p0i8(i8* %src, i32 4)
+ %tmp = tail call %struct.uint32x2x4_t @llvm.arm.neon.vld4dup.v2i32.p0(ptr %src, i32 4)
ret %struct.uint32x2x4_t %tmp
}
; CHECK-LABEL: test_vld4_dup_u64
; CHECK: vld1.64 {d16, d17, d18, d19}, [r1:64]
-define %struct.uint64x1x4_t @test_vld4_dup_u64(i8* %src) {
+define %struct.uint64x1x4_t @test_vld4_dup_u64(ptr %src) {
entry:
- %tmp = tail call %struct.uint64x1x4_t @llvm.arm.neon.vld4dup.v1i64.p0i8(i8* %src, i32 8)
+ %tmp = tail call %struct.uint64x1x4_t @llvm.arm.neon.vld4dup.v1i64.p0(ptr %src, i32 8)
ret %struct.uint64x1x4_t %tmp
}
; CHECK-LABEL: test_vld4_dup_u8
; CHECK: vld4.8 {d16[], d17[], d18[], d19[]}, [r1]
-define %struct.uint8x8x4_t @test_vld4_dup_u8(i8* %src) {
+define %struct.uint8x8x4_t @test_vld4_dup_u8(ptr %src) {
entry:
- %tmp = tail call %struct.uint8x8x4_t @llvm.arm.neon.vld4dup.v8i8.p0i8(i8* %src, i32 1)
+ %tmp = tail call %struct.uint8x8x4_t @llvm.arm.neon.vld4dup.v8i8.p0(ptr %src, i32 1)
ret %struct.uint8x8x4_t %tmp
}
; CHECK-LABEL: test_vld2q_dup_u16
; CHECK: vld2.16 {d16[], d18[]}, [r1]
; CHECK: vld2.16 {d17[], d19[]}, [r1]
-define %struct.uint16x8x2_t @test_vld2q_dup_u16(i8* %src) {
+define %struct.uint16x8x2_t @test_vld2q_dup_u16(ptr %src) {
entry:
- %tmp = tail call %struct.uint16x8x2_t @llvm.arm.neon.vld2dup.v8i16.p0i8(i8* %src, i32 2)
+ %tmp = tail call %struct.uint16x8x2_t @llvm.arm.neon.vld2dup.v8i16.p0(ptr %src, i32 2)
ret %struct.uint16x8x2_t %tmp
}
; CHECK-LABEL: test_vld2q_dup_u32
; CHECK: vld2.32 {d16[], d18[]}, [r1]
; CHECK: vld2.32 {d17[], d19[]}, [r1]
-define %struct.uint32x4x2_t @test_vld2q_dup_u32(i8* %src) {
+define %struct.uint32x4x2_t @test_vld2q_dup_u32(ptr %src) {
entry:
- %tmp = tail call %struct.uint32x4x2_t @llvm.arm.neon.vld2dup.v4i32.p0i8(i8* %src, i32 4)
+ %tmp = tail call %struct.uint32x4x2_t @llvm.arm.neon.vld2dup.v4i32.p0(ptr %src, i32 4)
ret %struct.uint32x4x2_t %tmp
}
; CHECK-LABEL: test_vld2q_dup_u8
; CHECK: vld2.8 {d16[], d18[]}, [r1]
; CHECK: vld2.8 {d17[], d19[]}, [r1]
-define %struct.uint8x16x2_t @test_vld2q_dup_u8(i8* %src) {
+define %struct.uint8x16x2_t @test_vld2q_dup_u8(ptr %src) {
entry:
- %tmp = tail call %struct.uint8x16x2_t @llvm.arm.neon.vld2dup.v16i8.p0i8(i8* %src, i32 1)
+ %tmp = tail call %struct.uint8x16x2_t @llvm.arm.neon.vld2dup.v16i8.p0(ptr %src, i32 1)
ret %struct.uint8x16x2_t %tmp
}
; CHECK-LABEL: test_vld3q_dup_u16
; CHECK: vld3.16 {d16[], d18[], d20[]}, [r1]
; CHECK: vld3.16 {d17[], d19[], d21[]}, [r1]
-define %struct.uint16x8x3_t @test_vld3q_dup_u16(i8* %src) {
+define %struct.uint16x8x3_t @test_vld3q_dup_u16(ptr %src) {
entry:
- %tmp = tail call %struct.uint16x8x3_t @llvm.arm.neon.vld3dup.v8i16.p0i8(i8* %src, i32 2)
+ %tmp = tail call %struct.uint16x8x3_t @llvm.arm.neon.vld3dup.v8i16.p0(ptr %src, i32 2)
ret %struct.uint16x8x3_t %tmp
}
; CHECK-LABEL: test_vld3q_dup_u32
; CHECK: vld3.32 {d16[], d18[], d20[]}, [r1]
; CHECK: vld3.32 {d17[], d19[], d21[]}, [r1]
-define %struct.uint32x4x3_t @test_vld3q_dup_u32(i8* %src) {
+define %struct.uint32x4x3_t @test_vld3q_dup_u32(ptr %src) {
entry:
- %tmp = tail call %struct.uint32x4x3_t @llvm.arm.neon.vld3dup.v4i32.p0i8(i8* %src, i32 4)
+ %tmp = tail call %struct.uint32x4x3_t @llvm.arm.neon.vld3dup.v4i32.p0(ptr %src, i32 4)
ret %struct.uint32x4x3_t %tmp
}
; CHECK-LABEL: test_vld3q_dup_u8
; CHECK: vld3.8 {d16[], d18[], d20[]}, [r1]
; CHECK: vld3.8 {d17[], d19[], d21[]}, [r1]
-define %struct.uint8x16x3_t @test_vld3q_dup_u8(i8* %src) {
+define %struct.uint8x16x3_t @test_vld3q_dup_u8(ptr %src) {
entry:
- %tmp = tail call %struct.uint8x16x3_t @llvm.arm.neon.vld3dup.v16i8.p0i8(i8* %src, i32 1)
+ %tmp = tail call %struct.uint8x16x3_t @llvm.arm.neon.vld3dup.v16i8.p0(ptr %src, i32 1)
ret %struct.uint8x16x3_t %tmp
}
; CHECK-LABEL: test_vld4q_dup_u16
; CHECK: vld4.16 {d16[], d18[], d20[], d22[]}, [r1]
; CHECK: vld4.16 {d17[], d19[], d21[], d23[]}, [r1]
-define %struct.uint16x8x4_t @test_vld4q_dup_u16(i8* %src) {
+define %struct.uint16x8x4_t @test_vld4q_dup_u16(ptr %src) {
entry:
- %tmp = tail call %struct.uint16x8x4_t @llvm.arm.neon.vld4dup.v8i16.p0i8(i8* %src, i32 2)
+ %tmp = tail call %struct.uint16x8x4_t @llvm.arm.neon.vld4dup.v8i16.p0(ptr %src, i32 2)
ret %struct.uint16x8x4_t %tmp
}
; CHECK-LABEL: test_vld4q_dup_u32
; CHECK: vld4.32 {d16[], d18[], d20[], d22[]}, [r1]
; CHECK: vld4.32 {d17[], d19[], d21[], d23[]}, [r1]
-define %struct.uint32x4x4_t @test_vld4q_dup_u32(i8* %src) {
+define %struct.uint32x4x4_t @test_vld4q_dup_u32(ptr %src) {
entry:
- %tmp = tail call %struct.uint32x4x4_t @llvm.arm.neon.vld4dup.v4i32.p0i8(i8* %src, i32 4)
+ %tmp = tail call %struct.uint32x4x4_t @llvm.arm.neon.vld4dup.v4i32.p0(ptr %src, i32 4)
ret %struct.uint32x4x4_t %tmp
}
; CHECK-LABEL: test_vld4q_dup_u8
; CHECK: vld4.8 {d16[], d18[], d20[], d22[]}, [r1]
; CHECK: vld4.8 {d17[], d19[], d21[], d23[]}, [r1]
-define %struct.uint8x16x4_t @test_vld4q_dup_u8(i8* %src) {
+define %struct.uint8x16x4_t @test_vld4q_dup_u8(ptr %src) {
entry:
- %tmp = tail call %struct.uint8x16x4_t @llvm.arm.neon.vld4dup.v16i8.p0i8(i8* %src, i32 1)
+ %tmp = tail call %struct.uint8x16x4_t @llvm.arm.neon.vld4dup.v16i8.p0(ptr %src, i32 1)
ret %struct.uint8x16x4_t %tmp
}
diff --git a/llvm/test/CodeGen/ARM/arm-vst1.ll b/llvm/test/CodeGen/ARM/arm-vst1.ll
index 2fcf9b75638bb..7dacd8b0b99f9 100644
--- a/llvm/test/CodeGen/ARM/arm-vst1.ll
+++ b/llvm/test/CodeGen/ARM/arm-vst1.ll
@@ -58,50 +58,50 @@
%struct.uint8x16x3_t = type { [3 x <16 x i8>] }
%struct.uint8x16x4_t = type { [4 x <16 x i8>] }
-declare void @llvm.arm.neon.vst1x2.p0i16.v4i16(i16* nocapture, <4 x i16>, <4 x i16>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x3.p0i16.v4i16(i16* nocapture, <4 x i16>, <4 x i16>, <4 x i16>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x4.p0i16.v4i16(i16* nocapture, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x2.p0.v4i16(ptr nocapture, <4 x i16>, <4 x i16>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x3.p0.v4i16(ptr nocapture, <4 x i16>, <4 x i16>, <4 x i16>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x4.p0.v4i16(ptr nocapture, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x2.p0i32.v2i32(i32* nocapture, <2 x i32>, <2 x i32>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x3.p0i32.v2i32(i32* nocapture, <2 x i32>, <2 x i32>, <2 x i32>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x4.p0i32.v2i32(i32* nocapture, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x2.p0.v2i32(ptr nocapture, <2 x i32>, <2 x i32>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x3.p0.v2i32(ptr nocapture, <2 x i32>, <2 x i32>, <2 x i32>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x4.p0.v2i32(ptr nocapture, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x2.p0i64.v1i64(i64* nocapture, <1 x i64>, <1 x i64>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x3.p0i64.v1i64(i64* nocapture, <1 x i64>, <1 x i64>, <1 x i64>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x4.p0i64.v1i64(i64* nocapture, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x2.p0.v1i64(ptr nocapture, <1 x i64>, <1 x i64>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x3.p0.v1i64(ptr nocapture, <1 x i64>, <1 x i64>, <1 x i64>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x4.p0.v1i64(ptr nocapture, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x2.p0i8.v8i8(i8* nocapture, <8 x i8>, <8 x i8>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x3.p0i8.v8i8(i8* nocapture, <8 x i8>, <8 x i8>, <8 x i8>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x4.p0i8.v8i8(i8* nocapture, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x2.p0.v8i8(ptr nocapture, <8 x i8>, <8 x i8>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x3.p0.v8i8(ptr nocapture, <8 x i8>, <8 x i8>, <8 x i8>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x4.p0.v8i8(ptr nocapture, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x2.p0i16.v8i16(i16* nocapture, <8 x i16>, <8 x i16>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x3.p0i16.v8i16(i16* nocapture, <8 x i16>, <8 x i16>, <8 x i16>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x4.p0i16.v8i16(i16* nocapture, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x2.p0.v8i16(ptr nocapture, <8 x i16>, <8 x i16>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x3.p0.v8i16(ptr nocapture, <8 x i16>, <8 x i16>, <8 x i16>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x4.p0.v8i16(ptr nocapture, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x2.p0i32.v4i32(i32* nocapture, <4 x i32>, <4 x i32>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x3.p0i32.v4i32(i32* nocapture, <4 x i32>, <4 x i32>, <4 x i32>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x4.p0i32.v4i32(i32* nocapture, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x2.p0.v4i32(ptr nocapture, <4 x i32>, <4 x i32>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x3.p0.v4i32(ptr nocapture, <4 x i32>, <4 x i32>, <4 x i32>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x4.p0.v4i32(ptr nocapture, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x2.p0i64.v2i64(i64* nocapture, <2 x i64>, <2 x i64>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x3.p0i64.v2i64(i64* nocapture, <2 x i64>, <2 x i64>, <2 x i64>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x4.p0i64.v2i64(i64* nocapture, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x2.p0.v2i64(ptr nocapture, <2 x i64>, <2 x i64>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x3.p0.v2i64(ptr nocapture, <2 x i64>, <2 x i64>, <2 x i64>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x4.p0.v2i64(ptr nocapture, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x2.p0i8.v16i8(i8* nocapture, <16 x i8>, <16 x i8>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x3.p0i8.v16i8(i8* nocapture, <16 x i8>, <16 x i8>, <16 x i8>) argmemonly nounwind
-declare void @llvm.arm.neon.vst1x4.p0i8.v16i8(i8* nocapture, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x2.p0.v16i8(ptr nocapture, <16 x i8>, <16 x i8>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x3.p0.v16i8(ptr nocapture, <16 x i8>, <16 x i8>, <16 x i8>) argmemonly nounwind
+declare void @llvm.arm.neon.vst1x4.p0.v16i8(ptr nocapture, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) argmemonly nounwind
-define arm_aapcs_vfpcc void @test_vst1_u16_x2(i16* %a, %struct.uint16x4x2_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1_u16_x2(ptr %a, %struct.uint16x4x2_t %b) nounwind {
; CHECK-LABEL: test_vst1_u16_x2:
; CHECK: vst1.16 {d0, d1}, [r0:64]
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint16x4x2_t %b, 0, 0
%b1 = extractvalue %struct.uint16x4x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i16.v4i16(i16* %a, <4 x i16> %b0, <4 x i16> %b1)
+ tail call void @llvm.arm.neon.vst1x2.p0.v4i16(ptr %a, <4 x i16> %b0, <4 x i16> %b1)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1_u16_x3(i16* %a, %struct.uint16x4x3_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1_u16_x3(ptr %a, %struct.uint16x4x3_t %b) nounwind {
; CHECK-LABEL: test_vst1_u16_x3:
; CHECK: vst1.16 {d0, d1, d2}, [r0:64]
; CHECK-NEXT: bx lr
@@ -109,11 +109,11 @@ entry:
%b0 = extractvalue %struct.uint16x4x3_t %b, 0, 0
%b1 = extractvalue %struct.uint16x4x3_t %b, 0, 1
%b2 = extractvalue %struct.uint16x4x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i16.v4i16(i16* %a, <4 x i16> %b0, <4 x i16> %b1, <4 x i16> %b2)
+ tail call void @llvm.arm.neon.vst1x3.p0.v4i16(ptr %a, <4 x i16> %b0, <4 x i16> %b1, <4 x i16> %b2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1_u16_x4(i16* %a, %struct.uint16x4x4_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1_u16_x4(ptr %a, %struct.uint16x4x4_t %b) nounwind {
; CHECK-LABEL: test_vst1_u16_x4:
; CHECK: vst1.16 {d0, d1, d2, d3}, [r0:256]
; CHECK-NEXT: bx lr
@@ -122,22 +122,22 @@ entry:
%b1 = extractvalue %struct.uint16x4x4_t %b, 0, 1
%b2 = extractvalue %struct.uint16x4x4_t %b, 0, 2
%b3 = extractvalue %struct.uint16x4x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i16.v4i16(i16* %a, <4 x i16> %b0, <4 x i16> %b1, <4 x i16> %b2, <4 x i16> %b3)
+ tail call void @llvm.arm.neon.vst1x4.p0.v4i16(ptr %a, <4 x i16> %b0, <4 x i16> %b1, <4 x i16> %b2, <4 x i16> %b3)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1_u32_x2(i32* %a, %struct.uint32x2x2_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1_u32_x2(ptr %a, %struct.uint32x2x2_t %b) nounwind {
; CHECK-LABEL: test_vst1_u32_x2:
; CHECK: vst1.32 {d0, d1}, [r0:64]
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint32x2x2_t %b, 0, 0
%b1 = extractvalue %struct.uint32x2x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i32.v2i32(i32* %a, <2 x i32> %b0, <2 x i32> %b1)
+ tail call void @llvm.arm.neon.vst1x2.p0.v2i32(ptr %a, <2 x i32> %b0, <2 x i32> %b1)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1_u32_x3(i32* %a, %struct.uint32x2x3_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1_u32_x3(ptr %a, %struct.uint32x2x3_t %b) nounwind {
; CHECK-LABEL: test_vst1_u32_x3:
; CHECK: vst1.32 {d0, d1, d2}, [r0:64]
; CHECK-NEXT: bx lr
@@ -145,11 +145,11 @@ entry:
%b0 = extractvalue %struct.uint32x2x3_t %b, 0, 0
%b1 = extractvalue %struct.uint32x2x3_t %b, 0, 1
%b2 = extractvalue %struct.uint32x2x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i32.v2i32(i32* %a, <2 x i32> %b0, <2 x i32> %b1, <2 x i32> %b2)
+ tail call void @llvm.arm.neon.vst1x3.p0.v2i32(ptr %a, <2 x i32> %b0, <2 x i32> %b1, <2 x i32> %b2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1_u32_x4(i32* %a, %struct.uint32x2x4_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1_u32_x4(ptr %a, %struct.uint32x2x4_t %b) nounwind {
; CHECK-LABEL: test_vst1_u32_x4:
; CHECK: vst1.32 {d0, d1, d2, d3}, [r0:256]
; CHECK-NEXT: bx lr
@@ -158,22 +158,22 @@ entry:
%b1 = extractvalue %struct.uint32x2x4_t %b, 0, 1
%b2 = extractvalue %struct.uint32x2x4_t %b, 0, 2
%b3 = extractvalue %struct.uint32x2x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i32.v2i32(i32* %a, <2 x i32> %b0, <2 x i32> %b1, <2 x i32> %b2, <2 x i32> %b3)
+ tail call void @llvm.arm.neon.vst1x4.p0.v2i32(ptr %a, <2 x i32> %b0, <2 x i32> %b1, <2 x i32> %b2, <2 x i32> %b3)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1_u64_x2(i64* %a, %struct.uint64x1x2_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1_u64_x2(ptr %a, %struct.uint64x1x2_t %b) nounwind {
; CHECK-LABEL: test_vst1_u64_x2:
; CHECK: vst1.64 {d0, d1}, [r0:64]
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint64x1x2_t %b, 0, 0
%b1 = extractvalue %struct.uint64x1x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i64.v1i64(i64* %a, <1 x i64> %b0, <1 x i64> %b1)
+ tail call void @llvm.arm.neon.vst1x2.p0.v1i64(ptr %a, <1 x i64> %b0, <1 x i64> %b1)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1_u64_x3(i64* %a, %struct.uint64x1x3_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1_u64_x3(ptr %a, %struct.uint64x1x3_t %b) nounwind {
; CHECK-LABEL: test_vst1_u64_x3:
; CHECK: vst1.64 {d0, d1, d2}, [r0:64]
; CHECK-NEXT: bx lr
@@ -181,11 +181,11 @@ entry:
%b0 = extractvalue %struct.uint64x1x3_t %b, 0, 0
%b1 = extractvalue %struct.uint64x1x3_t %b, 0, 1
%b2 = extractvalue %struct.uint64x1x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i64.v1i64(i64* %a, <1 x i64> %b0, <1 x i64> %b1, <1 x i64> %b2)
+ tail call void @llvm.arm.neon.vst1x3.p0.v1i64(ptr %a, <1 x i64> %b0, <1 x i64> %b1, <1 x i64> %b2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1_u64_x4(i64* %a, %struct.uint64x1x4_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1_u64_x4(ptr %a, %struct.uint64x1x4_t %b) nounwind {
; CHECK-LABEL: test_vst1_u64_x4:
; CHECK: vst1.64 {d0, d1, d2, d3}, [r0:256]
; CHECK-NEXT: bx lr
@@ -194,22 +194,22 @@ entry:
%b1 = extractvalue %struct.uint64x1x4_t %b, 0, 1
%b2 = extractvalue %struct.uint64x1x4_t %b, 0, 2
%b3 = extractvalue %struct.uint64x1x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i64.v1i64(i64* %a, <1 x i64> %b0, <1 x i64> %b1, <1 x i64> %b2, <1 x i64> %b3)
+ tail call void @llvm.arm.neon.vst1x4.p0.v1i64(ptr %a, <1 x i64> %b0, <1 x i64> %b1, <1 x i64> %b2, <1 x i64> %b3)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1_u8_x2(i8* %a, %struct.uint8x8x2_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1_u8_x2(ptr %a, %struct.uint8x8x2_t %b) nounwind {
; CHECK-LABEL: test_vst1_u8_x2:
; CHECK: vst1.8 {d0, d1}, [r0:64]
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint8x8x2_t %b, 0, 0
%b1 = extractvalue %struct.uint8x8x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i8.v8i8(i8* %a, <8 x i8> %b0, <8 x i8> %b1)
+ tail call void @llvm.arm.neon.vst1x2.p0.v8i8(ptr %a, <8 x i8> %b0, <8 x i8> %b1)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1_u8_x3(i8* %a, %struct.uint8x8x3_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1_u8_x3(ptr %a, %struct.uint8x8x3_t %b) nounwind {
; CHECK-LABEL: test_vst1_u8_x3:
; CHECK: vst1.8 {d0, d1, d2}, [r0:64]
; CHECK-NEXT: bx lr
@@ -217,11 +217,11 @@ entry:
%b0 = extractvalue %struct.uint8x8x3_t %b, 0, 0
%b1 = extractvalue %struct.uint8x8x3_t %b, 0, 1
%b2 = extractvalue %struct.uint8x8x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i8.v8i8(i8* %a, <8 x i8> %b0, <8 x i8> %b1, <8 x i8> %b2)
+ tail call void @llvm.arm.neon.vst1x3.p0.v8i8(ptr %a, <8 x i8> %b0, <8 x i8> %b1, <8 x i8> %b2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1_u8_x4(i8* %a, %struct.uint8x8x4_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1_u8_x4(ptr %a, %struct.uint8x8x4_t %b) nounwind {
; CHECK-LABEL: test_vst1_u8_x4:
; CHECK: vst1.8 {d0, d1, d2, d3}, [r0:256]
; CHECK-NEXT: bx lr
@@ -230,22 +230,22 @@ entry:
%b1 = extractvalue %struct.uint8x8x4_t %b, 0, 1
%b2 = extractvalue %struct.uint8x8x4_t %b, 0, 2
%b3 = extractvalue %struct.uint8x8x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i8.v8i8(i8* %a, <8 x i8> %b0, <8 x i8> %b1, <8 x i8> %b2, <8 x i8> %b3)
+ tail call void @llvm.arm.neon.vst1x4.p0.v8i8(ptr %a, <8 x i8> %b0, <8 x i8> %b1, <8 x i8> %b2, <8 x i8> %b3)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_u16_x2(i16* %a, %struct.uint16x8x2_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1q_u16_x2(ptr %a, %struct.uint16x8x2_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u16_x2:
; CHECK: vst1.16 {d0, d1, d2, d3}, [r0:256]
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint16x8x2_t %b, 0, 0
%b1 = extractvalue %struct.uint16x8x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i16.v8i16(i16* %a, <8 x i16> %b0, <8 x i16> %b1)
+ tail call void @llvm.arm.neon.vst1x2.p0.v8i16(ptr %a, <8 x i16> %b0, <8 x i16> %b1)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_u16_x3(i16* %a, %struct.uint16x8x3_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1q_u16_x3(ptr %a, %struct.uint16x8x3_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u16_x3:
; CHECK: vst1.16 {d0, d1, d2}, [r0:64]!
; CHECK-NEXT: vst1.16 {d3, d4, d5}, [r0:64]
@@ -254,11 +254,11 @@ entry:
%b0 = extractvalue %struct.uint16x8x3_t %b, 0, 0
%b1 = extractvalue %struct.uint16x8x3_t %b, 0, 1
%b2 = extractvalue %struct.uint16x8x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i16.v8i16(i16* %a, <8 x i16> %b0, <8 x i16> %b1, <8 x i16> %b2)
+ tail call void @llvm.arm.neon.vst1x3.p0.v8i16(ptr %a, <8 x i16> %b0, <8 x i16> %b1, <8 x i16> %b2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_u16_x4(i16* %a, %struct.uint16x8x4_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1q_u16_x4(ptr %a, %struct.uint16x8x4_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u16_x4:
; CHECK: vst1.16 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: vst1.16 {d4, d5, d6, d7}, [r0:256]
@@ -268,22 +268,22 @@ entry:
%b1 = extractvalue %struct.uint16x8x4_t %b, 0, 1
%b2 = extractvalue %struct.uint16x8x4_t %b, 0, 2
%b3 = extractvalue %struct.uint16x8x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i16.v8i16(i16* %a, <8 x i16> %b0, <8 x i16> %b1, <8 x i16> %b2, <8 x i16> %b3)
+ tail call void @llvm.arm.neon.vst1x4.p0.v8i16(ptr %a, <8 x i16> %b0, <8 x i16> %b1, <8 x i16> %b2, <8 x i16> %b3)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_u32_x2(i32* %a, %struct.uint32x4x2_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1q_u32_x2(ptr %a, %struct.uint32x4x2_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u32_x2:
; CHECK: vst1.32 {d0, d1, d2, d3}, [r0:256]
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint32x4x2_t %b, 0, 0
%b1 = extractvalue %struct.uint32x4x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i32.v4i32(i32* %a, <4 x i32> %b0, <4 x i32> %b1)
+ tail call void @llvm.arm.neon.vst1x2.p0.v4i32(ptr %a, <4 x i32> %b0, <4 x i32> %b1)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_u32_x3(i32* %a, %struct.uint32x4x3_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1q_u32_x3(ptr %a, %struct.uint32x4x3_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u32_x3:
; CHECK: vst1.32 {d0, d1, d2}, [r0:64]!
; CHECK-NEXT: vst1.32 {d3, d4, d5}, [r0:64]
@@ -292,11 +292,11 @@ entry:
%b0 = extractvalue %struct.uint32x4x3_t %b, 0, 0
%b1 = extractvalue %struct.uint32x4x3_t %b, 0, 1
%b2 = extractvalue %struct.uint32x4x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i32.v4i32(i32* %a, <4 x i32> %b0, <4 x i32> %b1, <4 x i32> %b2)
+ tail call void @llvm.arm.neon.vst1x3.p0.v4i32(ptr %a, <4 x i32> %b0, <4 x i32> %b1, <4 x i32> %b2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_u32_x4(i32* %a, %struct.uint32x4x4_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1q_u32_x4(ptr %a, %struct.uint32x4x4_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u32_x4:
; CHECK: vst1.32 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: vst1.32 {d4, d5, d6, d7}, [r0:256]
@@ -306,22 +306,22 @@ entry:
%b1 = extractvalue %struct.uint32x4x4_t %b, 0, 1
%b2 = extractvalue %struct.uint32x4x4_t %b, 0, 2
%b3 = extractvalue %struct.uint32x4x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i32.v4i32(i32* %a, <4 x i32> %b0, <4 x i32> %b1, <4 x i32> %b2, <4 x i32> %b3)
+ tail call void @llvm.arm.neon.vst1x4.p0.v4i32(ptr %a, <4 x i32> %b0, <4 x i32> %b1, <4 x i32> %b2, <4 x i32> %b3)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_u64_x2(i64* %a, %struct.uint64x2x2_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1q_u64_x2(ptr %a, %struct.uint64x2x2_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u64_x2:
; CHECK: vst1.64 {d0, d1, d2, d3}, [r0:256]
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint64x2x2_t %b, 0, 0
%b1 = extractvalue %struct.uint64x2x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i64.v2i64(i64* %a, <2 x i64> %b0, <2 x i64> %b1)
+ tail call void @llvm.arm.neon.vst1x2.p0.v2i64(ptr %a, <2 x i64> %b0, <2 x i64> %b1)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_u64_x3(i64* %a, %struct.uint64x2x3_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1q_u64_x3(ptr %a, %struct.uint64x2x3_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u64_x3:
; CHECK: vst1.64 {d0, d1, d2}, [r0:64]!
; CHECK-NEXT: vst1.64 {d3, d4, d5}, [r0:64]
@@ -330,11 +330,11 @@ entry:
%b0 = extractvalue %struct.uint64x2x3_t %b, 0, 0
%b1 = extractvalue %struct.uint64x2x3_t %b, 0, 1
%b2 = extractvalue %struct.uint64x2x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i64.v2i64(i64* %a, <2 x i64> %b0, <2 x i64> %b1, <2 x i64> %b2)
+ tail call void @llvm.arm.neon.vst1x3.p0.v2i64(ptr %a, <2 x i64> %b0, <2 x i64> %b1, <2 x i64> %b2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_u64_x4(i64* %a, %struct.uint64x2x4_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1q_u64_x4(ptr %a, %struct.uint64x2x4_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u64_x4:
; CHECK: vst1.64 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: vst1.64 {d4, d5, d6, d7}, [r0:256]
@@ -344,22 +344,22 @@ entry:
%b1 = extractvalue %struct.uint64x2x4_t %b, 0, 1
%b2 = extractvalue %struct.uint64x2x4_t %b, 0, 2
%b3 = extractvalue %struct.uint64x2x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i64.v2i64(i64* %a, <2 x i64> %b0, <2 x i64> %b1, <2 x i64> %b2, <2 x i64> %b3)
+ tail call void @llvm.arm.neon.vst1x4.p0.v2i64(ptr %a, <2 x i64> %b0, <2 x i64> %b1, <2 x i64> %b2, <2 x i64> %b3)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_u8_x2(i8* %a, %struct.uint8x16x2_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1q_u8_x2(ptr %a, %struct.uint8x16x2_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u8_x2:
; CHECK: vst1.8 {d0, d1, d2, d3}, [r0:256]
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint8x16x2_t %b, 0, 0
%b1 = extractvalue %struct.uint8x16x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i8.v16i8(i8* %a, <16 x i8> %b0, <16 x i8> %b1)
+ tail call void @llvm.arm.neon.vst1x2.p0.v16i8(ptr %a, <16 x i8> %b0, <16 x i8> %b1)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_u8_x3(i8* %a, %struct.uint8x16x3_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1q_u8_x3(ptr %a, %struct.uint8x16x3_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u8_x3:
; CHECK: vst1.8 {d0, d1, d2}, [r0:64]!
; CHECK-NEXT: vst1.8 {d3, d4, d5}, [r0:64]
@@ -368,11 +368,11 @@ entry:
%b0 = extractvalue %struct.uint8x16x3_t %b, 0, 0
%b1 = extractvalue %struct.uint8x16x3_t %b, 0, 1
%b2 = extractvalue %struct.uint8x16x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i8.v16i8(i8* %a, <16 x i8> %b0, <16 x i8> %b1, <16 x i8> %b2)
+ tail call void @llvm.arm.neon.vst1x3.p0.v16i8(ptr %a, <16 x i8> %b0, <16 x i8> %b1, <16 x i8> %b2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_u8_x4(i8* %a, %struct.uint8x16x4_t %b) nounwind {
+define arm_aapcs_vfpcc void @test_vst1q_u8_x4(ptr %a, %struct.uint8x16x4_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u8_x4:
; CHECK: vst1.8 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: vst1.8 {d4, d5, d6, d7}, [r0:256]
@@ -382,72 +382,72 @@ entry:
%b1 = extractvalue %struct.uint8x16x4_t %b, 0, 1
%b2 = extractvalue %struct.uint8x16x4_t %b, 0, 2
%b3 = extractvalue %struct.uint8x16x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i8.v16i8(i8* %a, <16 x i8> %b0, <16 x i8> %b1, <16 x i8> %b2, <16 x i8> %b3)
+ tail call void @llvm.arm.neon.vst1x4.p0.v16i8(ptr %a, <16 x i8> %b0, <16 x i8> %b1, <16 x i8> %b2, <16 x i8> %b3)
ret void
}
; Post increment
-define arm_aapcs_vfpcc i8* @test_vst1_u8_x2_post_imm(i8* %a, %struct.uint8x8x2_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u8_x2_post_imm(ptr %a, %struct.uint8x8x2_t %b) nounwind {
; CHECK-LABEL: test_vst1_u8_x2_post_imm:
; CHECK: vst1.8 {d0, d1}, [r0:64]!
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint8x8x2_t %b, 0, 0
%b1 = extractvalue %struct.uint8x8x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i8.v8i8(i8* %a, <8 x i8> %b0, <8 x i8> %b1)
- %tmp = getelementptr i8, i8* %a, i32 16
- ret i8* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v8i8(ptr %a, <8 x i8> %b0, <8 x i8> %b1)
+ %tmp = getelementptr i8, ptr %a, i32 16
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i8* @test_vst1_u8_x2_post_reg(i8* %a, %struct.uint8x8x2_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u8_x2_post_reg(ptr %a, %struct.uint8x8x2_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1_u8_x2_post_reg:
; CHECK: vst1.8 {d0, d1}, [r0:64], r1
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint8x8x2_t %b, 0, 0
%b1 = extractvalue %struct.uint8x8x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i8.v8i8(i8* %a, <8 x i8> %b0, <8 x i8> %b1)
- %tmp = getelementptr i8, i8* %a, i32 %inc
- ret i8* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v8i8(ptr %a, <8 x i8> %b0, <8 x i8> %b1)
+ %tmp = getelementptr i8, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i16* @test_vst1_u16_x2_post_imm(i16* %a, %struct.uint16x4x2_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u16_x2_post_imm(ptr %a, %struct.uint16x4x2_t %b) nounwind {
; CHECK-LABEL: test_vst1_u16_x2_post_imm:
; CHECK: vst1.16 {d0, d1}, [r0:64]!
; CHECK-NEXT: bx lr
%b0 = extractvalue %struct.uint16x4x2_t %b, 0, 0
%b1 = extractvalue %struct.uint16x4x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i16.v4i16(i16* %a, <4 x i16> %b0, <4 x i16> %b1)
- %tmp = getelementptr i16, i16* %a, i32 8
- ret i16* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v4i16(ptr %a, <4 x i16> %b0, <4 x i16> %b1)
+ %tmp = getelementptr i16, ptr %a, i32 8
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i16* @test_vst1_u16_x2_post_reg(i16* %a, %struct.uint16x4x2_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u16_x2_post_reg(ptr %a, %struct.uint16x4x2_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1_u16_x2_post_reg:
; CHECK: lsl r1, r1, #1
; CHECK-NEXT: vst1.16 {d0, d1}, [r0:64], r1
; CHECK-NEXT: bx lr
%b0 = extractvalue %struct.uint16x4x2_t %b, 0, 0
%b1 = extractvalue %struct.uint16x4x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i16.v4i16(i16* %a, <4 x i16> %b0, <4 x i16> %b1)
- %tmp = getelementptr i16, i16* %a, i32 %inc
- ret i16* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v4i16(ptr %a, <4 x i16> %b0, <4 x i16> %b1)
+ %tmp = getelementptr i16, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i32* @test_vst1_u32_x2_post_imm(i32* %a, %struct.uint32x2x2_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u32_x2_post_imm(ptr %a, %struct.uint32x2x2_t %b) nounwind {
; CHECK-LABEL: test_vst1_u32_x2_post_imm:
; CHECK: vst1.32 {d0, d1}, [r0:64]!
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint32x2x2_t %b, 0, 0
%b1 = extractvalue %struct.uint32x2x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i32.v2i32(i32* %a, <2 x i32> %b0, <2 x i32> %b1)
- %tmp = getelementptr i32, i32* %a, i32 4
- ret i32* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v2i32(ptr %a, <2 x i32> %b0, <2 x i32> %b1)
+ %tmp = getelementptr i32, ptr %a, i32 4
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i32* @test_vst1_u32_x2_post_reg(i32* %a, %struct.uint32x2x2_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u32_x2_post_reg(ptr %a, %struct.uint32x2x2_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1_u32_x2_post_reg:
; CHECK: lsl r1, r1, #2
; CHECK-NEXT: vst1.32 {d0, d1}, [r0:64], r1
@@ -455,24 +455,24 @@ define arm_aapcs_vfpcc i32* @test_vst1_u32_x2_post_reg(i32* %a, %struct.uint32x2
entry:
%b0 = extractvalue %struct.uint32x2x2_t %b, 0, 0
%b1 = extractvalue %struct.uint32x2x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i32.v2i32(i32* %a, <2 x i32> %b0, <2 x i32> %b1)
- %tmp = getelementptr i32, i32* %a, i32 %inc
- ret i32* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v2i32(ptr %a, <2 x i32> %b0, <2 x i32> %b1)
+ %tmp = getelementptr i32, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i64* @test_vst1_u64_x2_post_imm(i64* %a, %struct.uint64x1x2_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u64_x2_post_imm(ptr %a, %struct.uint64x1x2_t %b) nounwind {
; CHECK-LABEL: test_vst1_u64_x2_post_imm:
; CHECK: vst1.64 {d0, d1}, [r0:64]!
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint64x1x2_t %b, 0, 0
%b1 = extractvalue %struct.uint64x1x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i64.v1i64(i64* %a, <1 x i64> %b0, <1 x i64> %b1)
- %tmp = getelementptr i64, i64* %a, i32 2
- ret i64* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v1i64(ptr %a, <1 x i64> %b0, <1 x i64> %b1)
+ %tmp = getelementptr i64, ptr %a, i32 2
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i64* @test_vst1_u64_x2_post_reg(i64* %a, %struct.uint64x1x2_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u64_x2_post_reg(ptr %a, %struct.uint64x1x2_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1_u64_x2_post_reg:
; CHECK: lsl r1, r1, #3
; CHECK-NEXT: vst1.64 {d0, d1}, [r0:64], r1
@@ -480,48 +480,48 @@ define arm_aapcs_vfpcc i64* @test_vst1_u64_x2_post_reg(i64* %a, %struct.uint64x1
entry:
%b0 = extractvalue %struct.uint64x1x2_t %b, 0, 0
%b1 = extractvalue %struct.uint64x1x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i64.v1i64(i64* %a, <1 x i64> %b0, <1 x i64> %b1)
- %tmp = getelementptr i64, i64* %a, i32 %inc
- ret i64* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v1i64(ptr %a, <1 x i64> %b0, <1 x i64> %b1)
+ %tmp = getelementptr i64, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i8* @test_vst1q_u8_x2_post_imm(i8* %a, %struct.uint8x16x2_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u8_x2_post_imm(ptr %a, %struct.uint8x16x2_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u8_x2_post_imm:
; CHECK: vst1.8 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint8x16x2_t %b, 0, 0
%b1 = extractvalue %struct.uint8x16x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i8.v16i8(i8* %a, <16 x i8> %b0, <16 x i8> %b1)
- %tmp = getelementptr i8, i8* %a, i32 32
- ret i8* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v16i8(ptr %a, <16 x i8> %b0, <16 x i8> %b1)
+ %tmp = getelementptr i8, ptr %a, i32 32
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i8* @test_vst1q_u8_x2_post_reg(i8* %a, %struct.uint8x16x2_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u8_x2_post_reg(ptr %a, %struct.uint8x16x2_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1q_u8_x2_post_reg:
; CHECK: vst1.8 {d0, d1, d2, d3}, [r0:256], r1
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint8x16x2_t %b, 0, 0
%b1 = extractvalue %struct.uint8x16x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i8.v16i8(i8* %a, <16 x i8> %b0, <16 x i8> %b1)
- %tmp = getelementptr i8, i8* %a, i32 %inc
- ret i8* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v16i8(ptr %a, <16 x i8> %b0, <16 x i8> %b1)
+ %tmp = getelementptr i8, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i16* @test_vst1q_u16_x2_post_imm(i16* %a, %struct.uint16x8x2_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u16_x2_post_imm(ptr %a, %struct.uint16x8x2_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u16_x2_post_imm:
; CHECK: vst1.16 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint16x8x2_t %b, 0, 0
%b1 = extractvalue %struct.uint16x8x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i16.v8i16(i16* %a, <8 x i16> %b0, <8 x i16> %b1)
- %tmp = getelementptr i16, i16* %a, i32 16
- ret i16* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v8i16(ptr %a, <8 x i16> %b0, <8 x i16> %b1)
+ %tmp = getelementptr i16, ptr %a, i32 16
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i16* @test_vst1q_u16_x2_post_reg(i16* %a, %struct.uint16x8x2_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u16_x2_post_reg(ptr %a, %struct.uint16x8x2_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1q_u16_x2_post_reg:
; CHECK: lsl r1, r1, #1
; CHECK-NEXT: vst1.16 {d0, d1, d2, d3}, [r0:256], r1
@@ -529,24 +529,24 @@ define arm_aapcs_vfpcc i16* @test_vst1q_u16_x2_post_reg(i16* %a, %struct.uint16x
entry:
%b0 = extractvalue %struct.uint16x8x2_t %b, 0, 0
%b1 = extractvalue %struct.uint16x8x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i16.v8i16(i16* %a, <8 x i16> %b0, <8 x i16> %b1)
- %tmp = getelementptr i16, i16* %a, i32 %inc
- ret i16* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v8i16(ptr %a, <8 x i16> %b0, <8 x i16> %b1)
+ %tmp = getelementptr i16, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i32* @test_vst1q_u32_x2_post_imm(i32* %a, %struct.uint32x4x2_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u32_x2_post_imm(ptr %a, %struct.uint32x4x2_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u32_x2_post_imm:
; CHECK: vst1.32 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint32x4x2_t %b, 0, 0
%b1 = extractvalue %struct.uint32x4x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i32.v4i32(i32* %a, <4 x i32> %b0, <4 x i32> %b1)
- %tmp = getelementptr i32, i32* %a, i32 8
- ret i32* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v4i32(ptr %a, <4 x i32> %b0, <4 x i32> %b1)
+ %tmp = getelementptr i32, ptr %a, i32 8
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i32* @test_vst1q_u32_x2_post_reg(i32* %a, %struct.uint32x4x2_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u32_x2_post_reg(ptr %a, %struct.uint32x4x2_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1q_u32_x2_post_reg:
; CHECK: lsl r1, r1, #2
; CHECK-NEXT: vst1.32 {d0, d1, d2, d3}, [r0:256], r1
@@ -554,24 +554,24 @@ define arm_aapcs_vfpcc i32* @test_vst1q_u32_x2_post_reg(i32* %a, %struct.uint32x
entry:
%b0 = extractvalue %struct.uint32x4x2_t %b, 0, 0
%b1 = extractvalue %struct.uint32x4x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i32.v4i32(i32* %a, <4 x i32> %b0, <4 x i32> %b1)
- %tmp = getelementptr i32, i32* %a, i32 %inc
- ret i32* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v4i32(ptr %a, <4 x i32> %b0, <4 x i32> %b1)
+ %tmp = getelementptr i32, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i64* @test_vst1q_u64_x2_post_imm(i64* %a, %struct.uint64x2x2_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u64_x2_post_imm(ptr %a, %struct.uint64x2x2_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u64_x2_post_imm:
; CHECK: vst1.64 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: bx lr
entry:
%b0 = extractvalue %struct.uint64x2x2_t %b, 0, 0
%b1 = extractvalue %struct.uint64x2x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i64.v2i64(i64* %a, <2 x i64> %b0, <2 x i64> %b1)
- %tmp = getelementptr i64, i64* %a, i32 4
- ret i64* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v2i64(ptr %a, <2 x i64> %b0, <2 x i64> %b1)
+ %tmp = getelementptr i64, ptr %a, i32 4
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i64* @test_vst1q_u64_x2_post_reg(i64* %a, %struct.uint64x2x2_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u64_x2_post_reg(ptr %a, %struct.uint64x2x2_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1q_u64_x2_post_reg:
; CHECK: lsl r1, r1, #3
; CHECK-NEXT: vst1.64 {d0, d1, d2, d3}, [r0:256], r1
@@ -579,13 +579,13 @@ define arm_aapcs_vfpcc i64* @test_vst1q_u64_x2_post_reg(i64* %a, %struct.uint64x
entry:
%b0 = extractvalue %struct.uint64x2x2_t %b, 0, 0
%b1 = extractvalue %struct.uint64x2x2_t %b, 0, 1
- tail call void @llvm.arm.neon.vst1x2.p0i64.v2i64(i64* %a, <2 x i64> %b0, <2 x i64> %b1)
- %tmp = getelementptr i64, i64* %a, i32 %inc
- ret i64* %tmp
+ tail call void @llvm.arm.neon.vst1x2.p0.v2i64(ptr %a, <2 x i64> %b0, <2 x i64> %b1)
+ %tmp = getelementptr i64, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i8* @test_vst1_u8_x3_post_imm(i8* %a, %struct.uint8x8x3_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u8_x3_post_imm(ptr %a, %struct.uint8x8x3_t %b) nounwind {
; CHECK-LABEL: test_vst1_u8_x3_post_imm:
; CHECK: vst1.8 {d0, d1, d2}, [r0:64]!
; CHECK-NEXT: bx lr
@@ -593,12 +593,12 @@ entry:
%b0 = extractvalue %struct.uint8x8x3_t %b, 0, 0
%b1 = extractvalue %struct.uint8x8x3_t %b, 0, 1
%b2 = extractvalue %struct.uint8x8x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i8.v8i8(i8* %a, <8 x i8> %b0, <8 x i8> %b1, <8 x i8> %b2)
- %tmp = getelementptr i8, i8* %a, i32 24
- ret i8* %tmp
+ tail call void @llvm.arm.neon.vst1x3.p0.v8i8(ptr %a, <8 x i8> %b0, <8 x i8> %b1, <8 x i8> %b2)
+ %tmp = getelementptr i8, ptr %a, i32 24
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i8* @test_vst1_u8_x3_post_reg(i8* %a, %struct.uint8x8x3_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u8_x3_post_reg(ptr %a, %struct.uint8x8x3_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1_u8_x3_post_reg:
; CHECK: vst1.8 {d0, d1, d2}, [r0:64], r1
; CHECK-NEXT: bx lr
@@ -606,24 +606,24 @@ entry:
%b0 = extractvalue %struct.uint8x8x3_t %b, 0, 0
%b1 = extractvalue %struct.uint8x8x3_t %b, 0, 1
%b2 = extractvalue %struct.uint8x8x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i8.v8i8(i8* %a, <8 x i8> %b0, <8 x i8> %b1, <8 x i8> %b2)
- %tmp = getelementptr i8, i8* %a, i32 %inc
- ret i8* %tmp
+ tail call void @llvm.arm.neon.vst1x3.p0.v8i8(ptr %a, <8 x i8> %b0, <8 x i8> %b1, <8 x i8> %b2)
+ %tmp = getelementptr i8, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i16* @test_vst1_u16_x3_post_imm(i16* %a, %struct.uint16x4x3_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u16_x3_post_imm(ptr %a, %struct.uint16x4x3_t %b) nounwind {
; CHECK-LABEL: test_vst1_u16_x3_post_imm:
; CHECK: vst1.16 {d0, d1, d2}, [r0:64]!
; CHECK-NEXT: bx lr
%b0 = extractvalue %struct.uint16x4x3_t %b, 0, 0
%b1 = extractvalue %struct.uint16x4x3_t %b, 0, 1
%b2 = extractvalue %struct.uint16x4x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i16.v4i16(i16* %a, <4 x i16> %b0, <4 x i16> %b1, <4 x i16> %b2)
- %tmp = getelementptr i16, i16* %a, i32 12
- ret i16* %tmp
+ tail call void @llvm.arm.neon.vst1x3.p0.v4i16(ptr %a, <4 x i16> %b0, <4 x i16> %b1, <4 x i16> %b2)
+ %tmp = getelementptr i16, ptr %a, i32 12
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i16* @test_vst1_u16_x3_post_reg(i16* %a, %struct.uint16x4x3_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u16_x3_post_reg(ptr %a, %struct.uint16x4x3_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1_u16_x3_post_reg:
; CHECK: lsl r1, r1, #1
; CHECK-NEXT: vst1.16 {d0, d1, d2}, [r0:64], r1
@@ -631,12 +631,12 @@ define arm_aapcs_vfpcc i16* @test_vst1_u16_x3_post_reg(i16* %a, %struct.uint16x4
%b0 = extractvalue %struct.uint16x4x3_t %b, 0, 0
%b1 = extractvalue %struct.uint16x4x3_t %b, 0, 1
%b2 = extractvalue %struct.uint16x4x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i16.v4i16(i16* %a, <4 x i16> %b0, <4 x i16> %b1, <4 x i16> %b2)
- %tmp = getelementptr i16, i16* %a, i32 %inc
- ret i16* %tmp
+ tail call void @llvm.arm.neon.vst1x3.p0.v4i16(ptr %a, <4 x i16> %b0, <4 x i16> %b1, <4 x i16> %b2)
+ %tmp = getelementptr i16, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i32* @test_vst1_u32_x3_post_imm(i32* %a, %struct.uint32x2x3_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u32_x3_post_imm(ptr %a, %struct.uint32x2x3_t %b) nounwind {
; CHECK-LABEL: test_vst1_u32_x3_post_imm:
; CHECK: vst1.32 {d0, d1, d2}, [r0:64]!
; CHECK-NEXT: bx lr
@@ -644,12 +644,12 @@ entry:
%b0 = extractvalue %struct.uint32x2x3_t %b, 0, 0
%b1 = extractvalue %struct.uint32x2x3_t %b, 0, 1
%b2 = extractvalue %struct.uint32x2x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i32.v2i32(i32* %a, <2 x i32> %b0, <2 x i32> %b1, <2 x i32> %b2)
- %tmp = getelementptr i32, i32* %a, i32 6
- ret i32* %tmp
+ tail call void @llvm.arm.neon.vst1x3.p0.v2i32(ptr %a, <2 x i32> %b0, <2 x i32> %b1, <2 x i32> %b2)
+ %tmp = getelementptr i32, ptr %a, i32 6
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i32* @test_vst1_u32_x3_post_reg(i32* %a, %struct.uint32x2x3_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u32_x3_post_reg(ptr %a, %struct.uint32x2x3_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1_u32_x3_post_reg:
; CHECK: lsl r1, r1, #2
; CHECK-NEXT: vst1.32 {d0, d1, d2}, [r0:64], r1
@@ -658,12 +658,12 @@ entry:
%b0 = extractvalue %struct.uint32x2x3_t %b, 0, 0
%b1 = extractvalue %struct.uint32x2x3_t %b, 0, 1
%b2 = extractvalue %struct.uint32x2x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i32.v2i32(i32* %a, <2 x i32> %b0, <2 x i32> %b1, <2 x i32> %b2)
- %tmp = getelementptr i32, i32* %a, i32 %inc
- ret i32* %tmp
+ tail call void @llvm.arm.neon.vst1x3.p0.v2i32(ptr %a, <2 x i32> %b0, <2 x i32> %b1, <2 x i32> %b2)
+ %tmp = getelementptr i32, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i64* @test_vst1_u64_x3_post_imm(i64* %a, %struct.uint64x1x3_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u64_x3_post_imm(ptr %a, %struct.uint64x1x3_t %b) nounwind {
; CHECK-LABEL: test_vst1_u64_x3_post_imm:
; CHECK: vst1.64 {d0, d1, d2}, [r0:64]!
; CHECK-NEXT: bx lr
@@ -671,12 +671,12 @@ entry:
%b0 = extractvalue %struct.uint64x1x3_t %b, 0, 0
%b1 = extractvalue %struct.uint64x1x3_t %b, 0, 1
%b2 = extractvalue %struct.uint64x1x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i64.v1i64(i64* %a, <1 x i64> %b0, <1 x i64> %b1, <1 x i64> %b2)
- %tmp = getelementptr i64, i64* %a, i32 3
- ret i64* %tmp
+ tail call void @llvm.arm.neon.vst1x3.p0.v1i64(ptr %a, <1 x i64> %b0, <1 x i64> %b1, <1 x i64> %b2)
+ %tmp = getelementptr i64, ptr %a, i32 3
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i64* @test_vst1_u64_x3_post_reg(i64* %a, %struct.uint64x1x3_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u64_x3_post_reg(ptr %a, %struct.uint64x1x3_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1_u64_x3_post_reg:
; CHECK: lsl r1, r1, #3
; CHECK-NEXT: vst1.64 {d0, d1, d2}, [r0:64], r1
@@ -685,12 +685,12 @@ entry:
%b0 = extractvalue %struct.uint64x1x3_t %b, 0, 0
%b1 = extractvalue %struct.uint64x1x3_t %b, 0, 1
%b2 = extractvalue %struct.uint64x1x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i64.v1i64(i64* %a, <1 x i64> %b0, <1 x i64> %b1, <1 x i64> %b2)
- %tmp = getelementptr i64, i64* %a, i32 %inc
- ret i64* %tmp
+ tail call void @llvm.arm.neon.vst1x3.p0.v1i64(ptr %a, <1 x i64> %b0, <1 x i64> %b1, <1 x i64> %b2)
+ %tmp = getelementptr i64, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i8* @test_vst1q_u8_x3_post_imm(i8* %a, %struct.uint8x16x3_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u8_x3_post_imm(ptr %a, %struct.uint8x16x3_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u8_x3_post_imm:
; CHECK: vst1.8 {d0, d1, d2}, [r0:64]!
; CHECK-NEXT: vst1.8 {d3, d4, d5}, [r0:64]!
@@ -699,12 +699,12 @@ entry:
%b0 = extractvalue %struct.uint8x16x3_t %b, 0, 0
%b1 = extractvalue %struct.uint8x16x3_t %b, 0, 1
%b2 = extractvalue %struct.uint8x16x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i8.v16i8(i8* %a, <16 x i8> %b0, <16 x i8> %b1, <16 x i8> %b2)
- %tmp = getelementptr i8, i8* %a, i32 48
- ret i8* %tmp
+ tail call void @llvm.arm.neon.vst1x3.p0.v16i8(ptr %a, <16 x i8> %b0, <16 x i8> %b1, <16 x i8> %b2)
+ %tmp = getelementptr i8, ptr %a, i32 48
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i16* @test_vst1q_u16_x3_post_imm(i16* %a, %struct.uint16x8x3_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u16_x3_post_imm(ptr %a, %struct.uint16x8x3_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u16_x3_post_imm:
; CHECK: vst1.16 {d0, d1, d2}, [r0:64]!
; CHECK-NEXT: vst1.16 {d3, d4, d5}, [r0:64]!
@@ -713,12 +713,12 @@ entry:
%b0 = extractvalue %struct.uint16x8x3_t %b, 0, 0
%b1 = extractvalue %struct.uint16x8x3_t %b, 0, 1
%b2 = extractvalue %struct.uint16x8x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i16.v8i16(i16* %a, <8 x i16> %b0, <8 x i16> %b1, <8 x i16> %b2)
- %tmp = getelementptr i16, i16* %a, i32 24
- ret i16* %tmp
+ tail call void @llvm.arm.neon.vst1x3.p0.v8i16(ptr %a, <8 x i16> %b0, <8 x i16> %b1, <8 x i16> %b2)
+ %tmp = getelementptr i16, ptr %a, i32 24
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i32* @test_vst1q_u32_x3_post_imm(i32* %a, %struct.uint32x4x3_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u32_x3_post_imm(ptr %a, %struct.uint32x4x3_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u32_x3_post_imm:
; CHECK: vst1.32 {d0, d1, d2}, [r0:64]!
; CHECK-NEXT: vst1.32 {d3, d4, d5}, [r0:64]!
@@ -727,12 +727,12 @@ entry:
%b0 = extractvalue %struct.uint32x4x3_t %b, 0, 0
%b1 = extractvalue %struct.uint32x4x3_t %b, 0, 1
%b2 = extractvalue %struct.uint32x4x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i32.v4i32(i32* %a, <4 x i32> %b0, <4 x i32> %b1, <4 x i32> %b2)
- %tmp = getelementptr i32, i32* %a, i32 12
- ret i32* %tmp
+ tail call void @llvm.arm.neon.vst1x3.p0.v4i32(ptr %a, <4 x i32> %b0, <4 x i32> %b1, <4 x i32> %b2)
+ %tmp = getelementptr i32, ptr %a, i32 12
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i64* @test_vst1q_u64_x3_post_imm(i64* %a, %struct.uint64x2x3_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u64_x3_post_imm(ptr %a, %struct.uint64x2x3_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u64_x3_post_imm:
; CHECK: vst1.64 {d0, d1, d2}, [r0:64]!
; CHECK-NEXT: vst1.64 {d3, d4, d5}, [r0:64]!
@@ -741,12 +741,12 @@ entry:
%b0 = extractvalue %struct.uint64x2x3_t %b, 0, 0
%b1 = extractvalue %struct.uint64x2x3_t %b, 0, 1
%b2 = extractvalue %struct.uint64x2x3_t %b, 0, 2
- tail call void @llvm.arm.neon.vst1x3.p0i64.v2i64(i64* %a, <2 x i64> %b0, <2 x i64> %b1, <2 x i64> %b2)
- %tmp = getelementptr i64, i64* %a, i32 6
- ret i64* %tmp
+ tail call void @llvm.arm.neon.vst1x3.p0.v2i64(ptr %a, <2 x i64> %b0, <2 x i64> %b1, <2 x i64> %b2)
+ %tmp = getelementptr i64, ptr %a, i32 6
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i8* @test_vst1_u8_x4_post_imm(i8* %a, %struct.uint8x8x4_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u8_x4_post_imm(ptr %a, %struct.uint8x8x4_t %b) nounwind {
; CHECK-LABEL: test_vst1_u8_x4_post_imm:
; CHECK: vst1.8 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: bx lr
@@ -755,12 +755,12 @@ entry:
%b1 = extractvalue %struct.uint8x8x4_t %b, 0, 1
%b2 = extractvalue %struct.uint8x8x4_t %b, 0, 2
%b3 = extractvalue %struct.uint8x8x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i8.v8i8(i8* %a, <8 x i8> %b0, <8 x i8> %b1, <8 x i8> %b2, <8 x i8> %b3)
- %tmp = getelementptr i8, i8* %a, i32 32
- ret i8* %tmp
+ tail call void @llvm.arm.neon.vst1x4.p0.v8i8(ptr %a, <8 x i8> %b0, <8 x i8> %b1, <8 x i8> %b2, <8 x i8> %b3)
+ %tmp = getelementptr i8, ptr %a, i32 32
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i8* @test_vst1_u8_x4_post_reg(i8* %a, %struct.uint8x8x4_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u8_x4_post_reg(ptr %a, %struct.uint8x8x4_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1_u8_x4_post_reg:
; CHECK: vst1.8 {d0, d1, d2, d3}, [r0:256], r1
; CHECK-NEXT: bx lr
@@ -769,12 +769,12 @@ entry:
%b1 = extractvalue %struct.uint8x8x4_t %b, 0, 1
%b2 = extractvalue %struct.uint8x8x4_t %b, 0, 2
%b3 = extractvalue %struct.uint8x8x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i8.v8i8(i8* %a, <8 x i8> %b0, <8 x i8> %b1, <8 x i8> %b2, <8 x i8> %b3)
- %tmp = getelementptr i8, i8* %a, i32 %inc
- ret i8* %tmp
+ tail call void @llvm.arm.neon.vst1x4.p0.v8i8(ptr %a, <8 x i8> %b0, <8 x i8> %b1, <8 x i8> %b2, <8 x i8> %b3)
+ %tmp = getelementptr i8, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i16* @test_vst1_u16_x4_post_imm(i16* %a, %struct.uint16x4x4_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u16_x4_post_imm(ptr %a, %struct.uint16x4x4_t %b) nounwind {
; CHECK-LABEL: test_vst1_u16_x4_post_imm:
; CHECK: vst1.16 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: bx lr
@@ -782,12 +782,12 @@ define arm_aapcs_vfpcc i16* @test_vst1_u16_x4_post_imm(i16* %a, %struct.uint16x4
%b1 = extractvalue %struct.uint16x4x4_t %b, 0, 1
%b2 = extractvalue %struct.uint16x4x4_t %b, 0, 2
%b3 = extractvalue %struct.uint16x4x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i16.v4i16(i16* %a, <4 x i16> %b0, <4 x i16> %b1, <4 x i16> %b2, <4 x i16> %b3)
- %tmp = getelementptr i16, i16* %a, i32 16
- ret i16* %tmp
+ tail call void @llvm.arm.neon.vst1x4.p0.v4i16(ptr %a, <4 x i16> %b0, <4 x i16> %b1, <4 x i16> %b2, <4 x i16> %b3)
+ %tmp = getelementptr i16, ptr %a, i32 16
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i16* @test_vst1_u16_x4_post_reg(i16* %a, %struct.uint16x4x4_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u16_x4_post_reg(ptr %a, %struct.uint16x4x4_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1_u16_x4_post_reg:
; CHECK: lsl r1, r1, #1
; CHECK-NEXT: vst1.16 {d0, d1, d2, d3}, [r0:256], r1
@@ -796,12 +796,12 @@ define arm_aapcs_vfpcc i16* @test_vst1_u16_x4_post_reg(i16* %a, %struct.uint16x4
%b1 = extractvalue %struct.uint16x4x4_t %b, 0, 1
%b2 = extractvalue %struct.uint16x4x4_t %b, 0, 2
%b3 = extractvalue %struct.uint16x4x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i16.v4i16(i16* %a, <4 x i16> %b0, <4 x i16> %b1, <4 x i16> %b2, <4 x i16> %b3)
- %tmp = getelementptr i16, i16* %a, i32 %inc
- ret i16* %tmp
+ tail call void @llvm.arm.neon.vst1x4.p0.v4i16(ptr %a, <4 x i16> %b0, <4 x i16> %b1, <4 x i16> %b2, <4 x i16> %b3)
+ %tmp = getelementptr i16, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i32* @test_vst1_u32_x4_post_imm(i32* %a, %struct.uint32x2x4_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u32_x4_post_imm(ptr %a, %struct.uint32x2x4_t %b) nounwind {
; CHECK-LABEL: test_vst1_u32_x4_post_imm:
; CHECK: vst1.32 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: bx lr
@@ -810,12 +810,12 @@ entry:
%b1 = extractvalue %struct.uint32x2x4_t %b, 0, 1
%b2 = extractvalue %struct.uint32x2x4_t %b, 0, 2
%b3 = extractvalue %struct.uint32x2x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i32.v2i32(i32* %a, <2 x i32> %b0, <2 x i32> %b1, <2 x i32> %b2, <2 x i32> %b3)
- %tmp = getelementptr i32, i32* %a, i32 8
- ret i32* %tmp
+ tail call void @llvm.arm.neon.vst1x4.p0.v2i32(ptr %a, <2 x i32> %b0, <2 x i32> %b1, <2 x i32> %b2, <2 x i32> %b3)
+ %tmp = getelementptr i32, ptr %a, i32 8
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i32* @test_vst1_u32_x4_post_reg(i32* %a, %struct.uint32x2x4_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u32_x4_post_reg(ptr %a, %struct.uint32x2x4_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1_u32_x4_post_reg:
; CHECK: lsl r1, r1, #2
; CHECK-NEXT: vst1.32 {d0, d1, d2, d3}, [r0:256], r1
@@ -825,12 +825,12 @@ entry:
%b1 = extractvalue %struct.uint32x2x4_t %b, 0, 1
%b2 = extractvalue %struct.uint32x2x4_t %b, 0, 2
%b3 = extractvalue %struct.uint32x2x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i32.v2i32(i32* %a, <2 x i32> %b0, <2 x i32> %b1, <2 x i32> %b2, <2 x i32> %b3)
- %tmp = getelementptr i32, i32* %a, i32 %inc
- ret i32* %tmp
+ tail call void @llvm.arm.neon.vst1x4.p0.v2i32(ptr %a, <2 x i32> %b0, <2 x i32> %b1, <2 x i32> %b2, <2 x i32> %b3)
+ %tmp = getelementptr i32, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i64* @test_vst1_u64_x4_post_imm(i64* %a, %struct.uint64x1x4_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u64_x4_post_imm(ptr %a, %struct.uint64x1x4_t %b) nounwind {
; CHECK-LABEL: test_vst1_u64_x4_post_imm:
; CHECK: vst1.64 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: bx lr
@@ -839,12 +839,12 @@ entry:
%b1 = extractvalue %struct.uint64x1x4_t %b, 0, 1
%b2 = extractvalue %struct.uint64x1x4_t %b, 0, 2
%b3 = extractvalue %struct.uint64x1x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i64.v1i64(i64* %a, <1 x i64> %b0, <1 x i64> %b1, <1 x i64> %b2, <1 x i64> %b3)
- %tmp = getelementptr i64, i64* %a, i32 4
- ret i64* %tmp
+ tail call void @llvm.arm.neon.vst1x4.p0.v1i64(ptr %a, <1 x i64> %b0, <1 x i64> %b1, <1 x i64> %b2, <1 x i64> %b3)
+ %tmp = getelementptr i64, ptr %a, i32 4
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i64* @test_vst1_u64_x4_post_reg(i64* %a, %struct.uint64x1x4_t %b, i32 %inc) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1_u64_x4_post_reg(ptr %a, %struct.uint64x1x4_t %b, i32 %inc) nounwind {
; CHECK-LABEL: test_vst1_u64_x4_post_reg:
; CHECK: lsl r1, r1, #3
; CHECK-NEXT: vst1.64 {d0, d1, d2, d3}, [r0:256], r1
@@ -854,12 +854,12 @@ entry:
%b1 = extractvalue %struct.uint64x1x4_t %b, 0, 1
%b2 = extractvalue %struct.uint64x1x4_t %b, 0, 2
%b3 = extractvalue %struct.uint64x1x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i64.v1i64(i64* %a, <1 x i64> %b0, <1 x i64> %b1, <1 x i64> %b2, <1 x i64> %b3)
- %tmp = getelementptr i64, i64* %a, i32 %inc
- ret i64* %tmp
+ tail call void @llvm.arm.neon.vst1x4.p0.v1i64(ptr %a, <1 x i64> %b0, <1 x i64> %b1, <1 x i64> %b2, <1 x i64> %b3)
+ %tmp = getelementptr i64, ptr %a, i32 %inc
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i8* @test_vst1q_u8_x4_post_imm(i8* %a, %struct.uint8x16x4_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u8_x4_post_imm(ptr %a, %struct.uint8x16x4_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u8_x4_post_imm:
; CHECK: vst1.8 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: vst1.8 {d4, d5, d6, d7}, [r0:256]!
@@ -869,12 +869,12 @@ entry:
%b1 = extractvalue %struct.uint8x16x4_t %b, 0, 1
%b2 = extractvalue %struct.uint8x16x4_t %b, 0, 2
%b3 = extractvalue %struct.uint8x16x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i8.v16i8(i8* %a, <16 x i8> %b0, <16 x i8> %b1, <16 x i8> %b2, <16 x i8> %b3)
- %tmp = getelementptr i8, i8* %a, i32 64
- ret i8* %tmp
+ tail call void @llvm.arm.neon.vst1x4.p0.v16i8(ptr %a, <16 x i8> %b0, <16 x i8> %b1, <16 x i8> %b2, <16 x i8> %b3)
+ %tmp = getelementptr i8, ptr %a, i32 64
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i16* @test_vst1q_u16_x4_post_imm(i16* %a, %struct.uint16x8x4_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u16_x4_post_imm(ptr %a, %struct.uint16x8x4_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u16_x4_post_imm:
; CHECK: vst1.16 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: vst1.16 {d4, d5, d6, d7}, [r0:256]!
@@ -884,12 +884,12 @@ entry:
%b1 = extractvalue %struct.uint16x8x4_t %b, 0, 1
%b2 = extractvalue %struct.uint16x8x4_t %b, 0, 2
%b3 = extractvalue %struct.uint16x8x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i16.v8i16(i16* %a, <8 x i16> %b0, <8 x i16> %b1, <8 x i16> %b2, <8 x i16> %b3)
- %tmp = getelementptr i16, i16* %a, i32 32
- ret i16* %tmp
+ tail call void @llvm.arm.neon.vst1x4.p0.v8i16(ptr %a, <8 x i16> %b0, <8 x i16> %b1, <8 x i16> %b2, <8 x i16> %b3)
+ %tmp = getelementptr i16, ptr %a, i32 32
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i32* @test_vst1q_u32_x4_post_imm(i32* %a, %struct.uint32x4x4_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u32_x4_post_imm(ptr %a, %struct.uint32x4x4_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u32_x4_post_imm:
; CHECK: vst1.32 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: vst1.32 {d4, d5, d6, d7}, [r0:256]!
@@ -899,12 +899,12 @@ entry:
%b1 = extractvalue %struct.uint32x4x4_t %b, 0, 1
%b2 = extractvalue %struct.uint32x4x4_t %b, 0, 2
%b3 = extractvalue %struct.uint32x4x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i32.v4i32(i32* %a, <4 x i32> %b0, <4 x i32> %b1, <4 x i32> %b2, <4 x i32> %b3)
- %tmp = getelementptr i32, i32* %a, i32 16
- ret i32* %tmp
+ tail call void @llvm.arm.neon.vst1x4.p0.v4i32(ptr %a, <4 x i32> %b0, <4 x i32> %b1, <4 x i32> %b2, <4 x i32> %b3)
+ %tmp = getelementptr i32, ptr %a, i32 16
+ ret ptr %tmp
}
-define arm_aapcs_vfpcc i64* @test_vst1q_u64_x4_post_imm(i64* %a, %struct.uint64x2x4_t %b) nounwind {
+define arm_aapcs_vfpcc ptr @test_vst1q_u64_x4_post_imm(ptr %a, %struct.uint64x2x4_t %b) nounwind {
; CHECK-LABEL: test_vst1q_u64_x4_post_imm:
; CHECK: vst1.64 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: vst1.64 {d4, d5, d6, d7}, [r0:256]!
@@ -914,7 +914,7 @@ entry:
%b1 = extractvalue %struct.uint64x2x4_t %b, 0, 1
%b2 = extractvalue %struct.uint64x2x4_t %b, 0, 2
%b3 = extractvalue %struct.uint64x2x4_t %b, 0, 3
- tail call void @llvm.arm.neon.vst1x4.p0i64.v2i64(i64* %a, <2 x i64> %b0, <2 x i64> %b1, <2 x i64> %b2, <2 x i64> %b3)
- %tmp = getelementptr i64, i64* %a, i32 8
- ret i64* %tmp
+ tail call void @llvm.arm.neon.vst1x4.p0.v2i64(ptr %a, <2 x i64> %b0, <2 x i64> %b1, <2 x i64> %b2, <2 x i64> %b3)
+ %tmp = getelementptr i64, ptr %a, i32 8
+ ret ptr %tmp
}
diff --git a/llvm/test/CodeGen/ARM/armv4.ll b/llvm/test/CodeGen/ARM/armv4.ll
index a0379caaa4fbf..030ff115ee4c4 100644
--- a/llvm/test/CodeGen/ARM/armv4.ll
+++ b/llvm/test/CodeGen/ARM/armv4.ll
@@ -14,7 +14,7 @@ entry:
ret i32 %a
}
- at helper = global i32 ()* null, align 4
+ at helper = global ptr null, align 4
define i32 @test_indirect() #0 {
entry:
@@ -22,7 +22,7 @@ entry:
; ARM: mov pc
; THUMB-LABEL: test_indirect
; THUMB: bx
- %0 = load i32 ()*, i32 ()** @helper, align 4
+ %0 = load ptr, ptr @helper, align 4
%call = tail call i32 %0()
ret i32 %call
}
diff --git a/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll b/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
index 24d9c8870c307..9570c70676dbb 100644
--- a/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
+++ b/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
@@ -1437,14 +1437,14 @@ entry:
ret <8 x half> %shuffle.i
}
-define <4 x half> @test_vld_dup1_4xhalf(half* %b) {
+define <4 x half> @test_vld_dup1_4xhalf(ptr %b) {
; CHECK-LABEL: test_vld_dup1_4xhalf:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d0[]}, [r0:16]
; CHECK-NEXT: bx lr
entry:
- %b1 = load half, half* %b, align 2
+ %b1 = load half, ptr %b, align 2
%vecinit = insertelement <4 x half> undef, half %b1, i32 0
%vecinit2 = insertelement <4 x half> %vecinit, half %b1, i32 1
%vecinit3 = insertelement <4 x half> %vecinit2, half %b1, i32 2
@@ -1452,14 +1452,14 @@ entry:
ret <4 x half> %vecinit4
}
-define <8 x half> @test_vld_dup1_8xhalf(half* %b) local_unnamed_addr {
+define <8 x half> @test_vld_dup1_8xhalf(ptr %b) local_unnamed_addr {
; CHECK-LABEL: test_vld_dup1_8xhalf:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d0[], d1[]}, [r0:16]
; CHECK-NEXT: bx lr
entry:
- %b1 = load half, half* %b, align 2
+ %b1 = load half, ptr %b, align 2
%vecinit = insertelement <8 x half> undef, half %b1, i32 0
%vecinit8 = shufflevector <8 x half> %vecinit, <8 x half> undef, <8 x i32> zeroinitializer
ret <8 x half> %vecinit8
@@ -1535,20 +1535,20 @@ declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>)
declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)
declare <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8>, <8 x i8>, <8 x i8>)
declare <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
-declare { <8 x half>, <8 x half> } @llvm.arm.neon.vld2lane.v8f16.p0i8(i8*, <8 x half>, <8 x half>, i32, i32)
-declare { <4 x half>, <4 x half> } @llvm.arm.neon.vld2lane.v4f16.p0i8(i8*, <4 x half>, <4 x half>, i32, i32)
-declare { <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld3lane.v8f16.p0i8(i8*, <8 x half>, <8 x half>, <8 x half>, i32, i32)
-declare { <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld3lane.v4f16.p0i8(i8*, <4 x half>, <4 x half>, <4 x half>, i32, i32)
-declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld4lane.v8f16.p0i8(i8*, <8 x half>, <8 x half>, <8 x half>, <8 x half>, i32, i32)
-declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld4lane.v4f16.p0i8(i8*, <4 x half>, <4 x half>, <4 x half>, <4 x half>, i32, i32)
-declare void @llvm.arm.neon.vst2lane.p0i8.v8f16(i8*, <8 x half>, <8 x half>, i32, i32)
-declare void @llvm.arm.neon.vst2lane.p0i8.v4f16(i8*, <4 x half>, <4 x half>, i32, i32)
-declare void @llvm.arm.neon.vst3lane.p0i8.v8f16(i8*, <8 x half>, <8 x half>, <8 x half>, i32, i32)
-declare void @llvm.arm.neon.vst3lane.p0i8.v4f16(i8*, <4 x half>, <4 x half>, <4 x half>, i32, i32)
-declare void @llvm.arm.neon.vst4lane.p0i8.v8f16(i8*, <8 x half>, <8 x half>, <8 x half>, <8 x half>, i32, i32)
-declare void @llvm.arm.neon.vst4lane.p0i8.v4f16(i8*, <4 x half>, <4 x half>, <4 x half>, <4 x half>, i32, i32)
-
-define { <8 x half>, <8 x half> } @test_vld2q_lane_f16(i8*, <8 x half>, <8 x half>) {
+declare { <8 x half>, <8 x half> } @llvm.arm.neon.vld2lane.v8f16.p0(ptr, <8 x half>, <8 x half>, i32, i32)
+declare { <4 x half>, <4 x half> } @llvm.arm.neon.vld2lane.v4f16.p0(ptr, <4 x half>, <4 x half>, i32, i32)
+declare { <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld3lane.v8f16.p0(ptr, <8 x half>, <8 x half>, <8 x half>, i32, i32)
+declare { <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld3lane.v4f16.p0(ptr, <4 x half>, <4 x half>, <4 x half>, i32, i32)
+declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld4lane.v8f16.p0(ptr, <8 x half>, <8 x half>, <8 x half>, <8 x half>, i32, i32)
+declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld4lane.v4f16.p0(ptr, <4 x half>, <4 x half>, <4 x half>, <4 x half>, i32, i32)
+declare void @llvm.arm.neon.vst2lane.p0.v8f16(ptr, <8 x half>, <8 x half>, i32, i32)
+declare void @llvm.arm.neon.vst2lane.p0.v4f16(ptr, <4 x half>, <4 x half>, i32, i32)
+declare void @llvm.arm.neon.vst3lane.p0.v8f16(ptr, <8 x half>, <8 x half>, <8 x half>, i32, i32)
+declare void @llvm.arm.neon.vst3lane.p0.v4f16(ptr, <4 x half>, <4 x half>, <4 x half>, i32, i32)
+declare void @llvm.arm.neon.vst4lane.p0.v8f16(ptr, <8 x half>, <8 x half>, <8 x half>, <8 x half>, i32, i32)
+declare void @llvm.arm.neon.vst4lane.p0.v4f16(ptr, <4 x half>, <4 x half>, <4 x half>, <4 x half>, i32, i32)
+
+define { <8 x half>, <8 x half> } @test_vld2q_lane_f16(ptr, <8 x half>, <8 x half>) {
; CHECK-LABEL: test_vld2q_lane_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
@@ -1556,11 +1556,11 @@ define { <8 x half>, <8 x half> } @test_vld2q_lane_f16(i8*, <8 x half>, <8 x hal
; CHECK-NEXT: vld2.16 {d1[3], d3[3]}, [r0]
; CHECK-NEXT: bx lr
entry:
- %3 = tail call { <8 x half>, <8 x half> } @llvm.arm.neon.vld2lane.v8f16.p0i8(i8* %0, <8 x half> %1, <8 x half> %2, i32 7, i32 2)
+ %3 = tail call { <8 x half>, <8 x half> } @llvm.arm.neon.vld2lane.v8f16.p0(ptr %0, <8 x half> %1, <8 x half> %2, i32 7, i32 2)
ret { <8 x half>, <8 x half> } %3
}
-define { <4 x half>, <4 x half> } @test_vld2_lane_f16(i8*, <4 x half>, <4 x half>) {
+define { <4 x half>, <4 x half> } @test_vld2_lane_f16(ptr, <4 x half>, <4 x half>) {
; CHECK-LABEL: test_vld2_lane_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
@@ -1568,11 +1568,11 @@ define { <4 x half>, <4 x half> } @test_vld2_lane_f16(i8*, <4 x half>, <4 x half
; CHECK-NEXT: vld2.16 {d0[3], d1[3]}, [r0]
; CHECK-NEXT: bx lr
entry:
- %3 = tail call { <4 x half>, <4 x half> } @llvm.arm.neon.vld2lane.v4f16.p0i8(i8* %0, <4 x half> %1, <4 x half> %2, i32 3, i32 2)
+ %3 = tail call { <4 x half>, <4 x half> } @llvm.arm.neon.vld2lane.v4f16.p0(ptr %0, <4 x half> %1, <4 x half> %2, i32 3, i32 2)
ret { <4 x half>, <4 x half> } %3
}
-define { <8 x half>, <8 x half>, <8 x half> } @test_vld3q_lane_f16(i8*, <8 x half>, <8 x half>, <8 x half>) {
+define { <8 x half>, <8 x half>, <8 x half> } @test_vld3q_lane_f16(ptr, <8 x half>, <8 x half>, <8 x half>) {
; CHECK-LABEL: test_vld3q_lane_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
@@ -1581,11 +1581,11 @@ define { <8 x half>, <8 x half>, <8 x half> } @test_vld3q_lane_f16(i8*, <8 x hal
; CHECK-NEXT: vld3.16 {d1[3], d3[3], d5[3]}, [r0]
; CHECK-NEXT: bx lr
entry:
- %4 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld3lane.v8f16.p0i8(i8* %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, i32 7, i32 2)
+ %4 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld3lane.v8f16.p0(ptr %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, i32 7, i32 2)
ret { <8 x half>, <8 x half>, <8 x half> } %4
}
-define { <4 x half>, <4 x half>, <4 x half> } @test_vld3_lane_f16(i8*, <4 x half>, <4 x half>, <4 x half>) {
+define { <4 x half>, <4 x half>, <4 x half> } @test_vld3_lane_f16(ptr, <4 x half>, <4 x half>, <4 x half>) {
; CHECK-LABEL: test_vld3_lane_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
@@ -1594,10 +1594,10 @@ define { <4 x half>, <4 x half>, <4 x half> } @test_vld3_lane_f16(i8*, <4 x half
; CHECK-NEXT: vld3.16 {d0[3], d1[3], d2[3]}, [r0]
; CHECK-NEXT: bx lr
entry:
- %4 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld3lane.v4f16.p0i8(i8* %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, i32 3, i32 2)
+ %4 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld3lane.v4f16.p0(ptr %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, i32 3, i32 2)
ret { <4 x half>, <4 x half>, <4 x half> } %4
}
-define { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @test_vld4lane_v8f16_p0i8(i8*, <8 x half>, <8 x half>, <8 x half>, <8 x half>) {
+define { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @test_vld4lane_v8f16_p0i8(ptr, <8 x half>, <8 x half>, <8 x half>, <8 x half>) {
; CHECK-LABEL: test_vld4lane_v8f16_p0i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
@@ -1607,10 +1607,10 @@ define { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @test_vld4lane_v8f16_p
; CHECK-NEXT: vld4.16 {d1[3], d3[3], d5[3], d7[3]}, [r0]
; CHECK-NEXT: bx lr
entry:
- %5 = tail call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld4lane.v8f16.p0i8(i8* %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, <8 x half> %4, i32 7, i32 2)
+ %5 = tail call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld4lane.v8f16.p0(ptr %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, <8 x half> %4, i32 7, i32 2)
ret { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %5
}
-define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @test_vld4lane_v4f16_p0i8(i8*, <4 x half>, <4 x half>, <4 x half>, <4 x half>) {
+define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @test_vld4lane_v4f16_p0i8(ptr, <4 x half>, <4 x half>, <4 x half>, <4 x half>) {
; CHECK-LABEL: test_vld4lane_v4f16_p0i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q0_q1 def $q0_q1
@@ -1620,10 +1620,10 @@ define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @test_vld4lane_v4f16_p
; CHECK-NEXT: vld4.16 {d0[3], d1[3], d2[3], d3[3]}, [r0]
; CHECK-NEXT: bx lr
entry:
- %5 = tail call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld4lane.v4f16.p0i8(i8* %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, <4 x half> %4, i32 3, i32 2)
+ %5 = tail call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld4lane.v4f16.p0(ptr %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, <4 x half> %4, i32 3, i32 2)
ret { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %5
}
-define void @test_vst2lane_p0i8_v8f16(i8*, <8 x half>, <8 x half>) {
+define void @test_vst2lane_p0i8_v8f16(ptr, <8 x half>, <8 x half>) {
; CHECK-LABEL: test_vst2lane_p0i8_v8f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
@@ -1631,10 +1631,10 @@ define void @test_vst2lane_p0i8_v8f16(i8*, <8 x half>, <8 x half>) {
; CHECK-NEXT: vst2.16 {d0[0], d2[0]}, [r0]
; CHECK-NEXT: bx lr
entry:
- tail call void @llvm.arm.neon.vst2lane.p0i8.v8f16(i8* %0, <8 x half> %1, <8 x half> %2, i32 0, i32 1)
+ tail call void @llvm.arm.neon.vst2lane.p0.v8f16(ptr %0, <8 x half> %1, <8 x half> %2, i32 0, i32 1)
ret void
}
-define void @test_vst2lane_p0i8_v4f16(i8*, <4 x half>, <4 x half>) {
+define void @test_vst2lane_p0i8_v4f16(ptr, <4 x half>, <4 x half>) {
; CHECK-LABEL: test_vst2lane_p0i8_v4f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
@@ -1642,10 +1642,10 @@ define void @test_vst2lane_p0i8_v4f16(i8*, <4 x half>, <4 x half>) {
; CHECK-NEXT: vst2.16 {d0[0], d1[0]}, [r0:32]
; CHECK-NEXT: bx lr
entry:
- tail call void @llvm.arm.neon.vst2lane.p0i8.v4f16(i8* %0, <4 x half> %1, <4 x half> %2, i32 0, i32 0)
+ tail call void @llvm.arm.neon.vst2lane.p0.v4f16(ptr %0, <4 x half> %1, <4 x half> %2, i32 0, i32 0)
ret void
}
-define void @test_vst3lane_p0i8_v8f16(i8*, <8 x half>, <8 x half>, <8 x half>) {
+define void @test_vst3lane_p0i8_v8f16(ptr, <8 x half>, <8 x half>, <8 x half>) {
; CHECK-LABEL: test_vst3lane_p0i8_v8f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
@@ -1654,10 +1654,10 @@ define void @test_vst3lane_p0i8_v8f16(i8*, <8 x half>, <8 x half>, <8 x half>) {
; CHECK-NEXT: vst3.16 {d0[0], d2[0], d4[0]}, [r0]
; CHECK-NEXT: bx lr
entry:
- tail call void @llvm.arm.neon.vst3lane.p0i8.v8f16(i8* %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, i32 0, i32 0)
+ tail call void @llvm.arm.neon.vst3lane.p0.v8f16(ptr %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, i32 0, i32 0)
ret void
}
-define void @test_vst3lane_p0i8_v4f16(i8*, <4 x half>, <4 x half>, <4 x half>) {
+define void @test_vst3lane_p0i8_v4f16(ptr, <4 x half>, <4 x half>, <4 x half>) {
; CHECK-LABEL: test_vst3lane_p0i8_v4f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
@@ -1666,10 +1666,10 @@ define void @test_vst3lane_p0i8_v4f16(i8*, <4 x half>, <4 x half>, <4 x half>) {
; CHECK-NEXT: vst3.16 {d0[0], d1[0], d2[0]}, [r0]
; CHECK-NEXT: bx lr
entry:
- tail call void @llvm.arm.neon.vst3lane.p0i8.v4f16(i8* %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, i32 0, i32 0)
+ tail call void @llvm.arm.neon.vst3lane.p0.v4f16(ptr %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, i32 0, i32 0)
ret void
}
-define void @test_vst4lane_p0i8_v8f16(i8*, <8 x half>, <8 x half>, <8 x half>, <8 x half>) {
+define void @test_vst4lane_p0i8_v8f16(ptr, <8 x half>, <8 x half>, <8 x half>, <8 x half>) {
; CHECK-LABEL: test_vst4lane_p0i8_v8f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
@@ -1679,10 +1679,10 @@ define void @test_vst4lane_p0i8_v8f16(i8*, <8 x half>, <8 x half>, <8 x half>, <
; CHECK-NEXT: vst4.16 {d0[0], d2[0], d4[0], d6[0]}, [r0:64]
; CHECK-NEXT: bx lr
entry:
- tail call void @llvm.arm.neon.vst4lane.p0i8.v8f16(i8* %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, <8 x half> %4, i32 0, i32 0)
+ tail call void @llvm.arm.neon.vst4lane.p0.v8f16(ptr %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, <8 x half> %4, i32 0, i32 0)
ret void
}
-define void @test_vst4lane_p0i8_v4f16(i8*, <4 x half>, <4 x half>, <4 x half>, <4 x half>) {
+define void @test_vst4lane_p0i8_v4f16(ptr, <4 x half>, <4 x half>, <4 x half>, <4 x half>) {
; CHECK-LABEL: test_vst4lane_p0i8_v4f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q0_q1 def $q0_q1
@@ -1692,6 +1692,6 @@ define void @test_vst4lane_p0i8_v4f16(i8*, <4 x half>, <4 x half>, <4 x half>, <
; CHECK-NEXT: vst4.16 {d0[0], d1[0], d2[0], d3[0]}, [r0:64]
; CHECK-NEXT: bx lr
entry:
- tail call void @llvm.arm.neon.vst4lane.p0i8.v4f16(i8* %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, <4 x half> %4, i32 0, i32 0)
+ tail call void @llvm.arm.neon.vst4lane.p0.v4f16(ptr %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, <4 x half> %4, i32 0, i32 0)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/atomic-64bit.ll b/llvm/test/CodeGen/ARM/atomic-64bit.ll
index f000b8a821887..312f9551573e1 100644
--- a/llvm/test/CodeGen/ARM/atomic-64bit.ll
+++ b/llvm/test/CodeGen/ARM/atomic-64bit.ll
@@ -5,7 +5,7 @@
; RUN: llc < %s -mtriple=armv7m--none-eabi | FileCheck %s --check-prefix=CHECK-M
; RUN: llc < %s -mtriple=armv8m--none-eabi | FileCheck %s --check-prefix=CHECK-M
-define i64 @test1(i64* %ptr, i64 %val) {
+define i64 @test1(ptr %ptr, i64 %val) {
; CHECK-LABEL: test1:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
@@ -32,11 +32,11 @@ define i64 @test1(i64* %ptr, i64 %val) {
; CHECK-M: __atomic_fetch_add_8
- %r = atomicrmw add i64* %ptr, i64 %val seq_cst
+ %r = atomicrmw add ptr %ptr, i64 %val seq_cst
ret i64 %r
}
-define i64 @test2(i64* %ptr, i64 %val) {
+define i64 @test2(ptr %ptr, i64 %val) {
; CHECK-LABEL: test2:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
@@ -63,11 +63,11 @@ define i64 @test2(i64* %ptr, i64 %val) {
; CHECK-M: __atomic_fetch_sub_8
- %r = atomicrmw sub i64* %ptr, i64 %val seq_cst
+ %r = atomicrmw sub ptr %ptr, i64 %val seq_cst
ret i64 %r
}
-define i64 @test3(i64* %ptr, i64 %val) {
+define i64 @test3(ptr %ptr, i64 %val) {
; CHECK-LABEL: test3:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
@@ -94,11 +94,11 @@ define i64 @test3(i64* %ptr, i64 %val) {
; CHECK-M: _atomic_fetch_and_8
- %r = atomicrmw and i64* %ptr, i64 %val seq_cst
+ %r = atomicrmw and ptr %ptr, i64 %val seq_cst
ret i64 %r
}
-define i64 @test4(i64* %ptr, i64 %val) {
+define i64 @test4(ptr %ptr, i64 %val) {
; CHECK-LABEL: test4:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
@@ -125,11 +125,11 @@ define i64 @test4(i64* %ptr, i64 %val) {
; CHECK-M: __atomic_fetch_or_8
- %r = atomicrmw or i64* %ptr, i64 %val seq_cst
+ %r = atomicrmw or ptr %ptr, i64 %val seq_cst
ret i64 %r
}
-define i64 @test5(i64* %ptr, i64 %val) {
+define i64 @test5(ptr %ptr, i64 %val) {
; CHECK-LABEL: test5:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
@@ -156,11 +156,11 @@ define i64 @test5(i64* %ptr, i64 %val) {
; CHECK-M: __atomic_fetch_xor_8
- %r = atomicrmw xor i64* %ptr, i64 %val seq_cst
+ %r = atomicrmw xor ptr %ptr, i64 %val seq_cst
ret i64 %r
}
-define i64 @test6(i64* %ptr, i64 %val) {
+define i64 @test6(ptr %ptr, i64 %val) {
; CHECK-LABEL: test6:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
@@ -179,11 +179,11 @@ define i64 @test6(i64* %ptr, i64 %val) {
; CHECK-M: __atomic_exchange_8
- %r = atomicrmw xchg i64* %ptr, i64 %val seq_cst
+ %r = atomicrmw xchg ptr %ptr, i64 %val seq_cst
ret i64 %r
}
-define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
+define i64 @test7(ptr %ptr, i64 %val1, i64 %val2) {
; CHECK-LABEL: test7:
; CHECK-DAG: mov [[VAL1LO:r[0-9]+]], r1
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
@@ -215,14 +215,14 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
; CHECK-M: __atomic_compare_exchange_8
- %pair = cmpxchg i64* %ptr, i64 %val1, i64 %val2 seq_cst seq_cst
+ %pair = cmpxchg ptr %ptr, i64 %val1, i64 %val2 seq_cst seq_cst
%r = extractvalue { i64, i1 } %pair, 0
ret i64 %r
}
; Compiles down to a single ldrexd, except on M class devices where ldrexd
; isn't supported.
-define i64 @test8(i64* %ptr) {
+define i64 @test8(ptr %ptr) {
; CHECK-LABEL: test8:
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK-NOT: strexd
@@ -239,14 +239,14 @@ define i64 @test8(i64* %ptr) {
; CHECK-M: __atomic_load_8
- %r = load atomic i64, i64* %ptr seq_cst, align 8
+ %r = load atomic i64, ptr %ptr seq_cst, align 8
ret i64 %r
}
; Compiles down to atomicrmw xchg; there really isn't any more efficient
; way to write it. Except on M class devices, where ldrexd/strexd aren't
; supported.
-define void @test9(i64* %ptr, i64 %val) {
+define void @test9(ptr %ptr, i64 %val) {
; CHECK-LABEL: test9:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
@@ -265,11 +265,11 @@ define void @test9(i64* %ptr, i64 %val) {
; CHECK-M: __atomic_store_8
- store atomic i64 %val, i64* %ptr seq_cst, align 8
+ store atomic i64 %val, ptr %ptr seq_cst, align 8
ret void
}
-define i64 @test10(i64* %ptr, i64 %val) {
+define i64 @test10(ptr %ptr, i64 %val) {
; CHECK-LABEL: test10:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
@@ -310,11 +310,11 @@ define i64 @test10(i64* %ptr, i64 %val) {
; CHECK-M: __atomic_compare_exchange_8
- %r = atomicrmw min i64* %ptr, i64 %val seq_cst
+ %r = atomicrmw min ptr %ptr, i64 %val seq_cst
ret i64 %r
}
-define i64 @test11(i64* %ptr, i64 %val) {
+define i64 @test11(ptr %ptr, i64 %val) {
; CHECK-LABEL: test11:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
@@ -355,11 +355,11 @@ define i64 @test11(i64* %ptr, i64 %val) {
; CHECK-M: __atomic_compare_exchange_8
- %r = atomicrmw umin i64* %ptr, i64 %val seq_cst
+ %r = atomicrmw umin ptr %ptr, i64 %val seq_cst
ret i64 %r
}
-define i64 @test12(i64* %ptr, i64 %val) {
+define i64 @test12(ptr %ptr, i64 %val) {
; CHECK-LABEL: test12:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
@@ -400,11 +400,11 @@ define i64 @test12(i64* %ptr, i64 %val) {
; CHECK-M: __atomic_compare_exchange_8
- %r = atomicrmw max i64* %ptr, i64 %val seq_cst
+ %r = atomicrmw max ptr %ptr, i64 %val seq_cst
ret i64 %r
}
-define i64 @test13(i64* %ptr, i64 %val) {
+define i64 @test13(ptr %ptr, i64 %val) {
; CHECK-LABEL: test13:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
@@ -445,7 +445,7 @@ define i64 @test13(i64* %ptr, i64 %val) {
; CHECK-M: __atomic_compare_exchange_8
- %r = atomicrmw umax i64* %ptr, i64 %val seq_cst
+ %r = atomicrmw umax ptr %ptr, i64 %val seq_cst
ret i64 %r
}
diff --git a/llvm/test/CodeGen/ARM/atomic-cmp.ll b/llvm/test/CodeGen/ARM/atomic-cmp.ll
index 2f2f9d88bc0e1..115e489df9648 100644
--- a/llvm/test/CodeGen/ARM/atomic-cmp.ll
+++ b/llvm/test/CodeGen/ARM/atomic-cmp.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -verify-machineinstrs | FileCheck %s -check-prefix=T2
; rdar://8964854
-define i8 @t(i8* %a, i8 %b, i8 %c) nounwind {
+define i8 @t(ptr %a, i8 %b, i8 %c) nounwind {
; ARM-LABEL: t:
; ARM: ldrexb
; ARM: strexb
@@ -12,7 +12,7 @@ define i8 @t(i8* %a, i8 %b, i8 %c) nounwind {
; T2: ldrexb
; T2: strexb
; T2: clrex
- %tmp0 = cmpxchg i8* %a, i8 %b, i8 %c monotonic monotonic
+ %tmp0 = cmpxchg ptr %a, i8 %b, i8 %c monotonic monotonic
%tmp1 = extractvalue { i8, i1 } %tmp0, 0
ret i8 %tmp1
}
diff --git a/llvm/test/CodeGen/ARM/atomic-cmpxchg.ll b/llvm/test/CodeGen/ARM/atomic-cmpxchg.ll
index 0f2c6600e93d5..4bf42d4ac9629 100644
--- a/llvm/test/CodeGen/ARM/atomic-cmpxchg.ll
+++ b/llvm/test/CodeGen/ARM/atomic-cmpxchg.ll
@@ -8,7 +8,7 @@
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -asm-verbose=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-ARMV7
; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -asm-verbose=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-THUMBV7
-define zeroext i1 @test_cmpxchg_res_i8(i8* %addr, i8 %desired, i8 zeroext %new) {
+define zeroext i1 @test_cmpxchg_res_i8(ptr %addr, i8 %desired, i8 zeroext %new) {
; CHECK-ARM-LABEL: test_cmpxchg_res_i8:
; CHECK-ARM: .save {r4, lr}
; CHECK-ARM-NEXT: push {r4, lr}
@@ -93,7 +93,7 @@ define zeroext i1 @test_cmpxchg_res_i8(i8* %addr, i8 %desired, i8 zeroext %new)
; CHECK-THUMBV7-NEXT: clrex
; CHECK-THUMBV7-NEXT: bx lr
entry:
- %0 = cmpxchg i8* %addr, i8 %desired, i8 %new monotonic monotonic
+ %0 = cmpxchg ptr %addr, i8 %desired, i8 %new monotonic monotonic
%1 = extractvalue { i8, i1 } %0, 1
ret i1 %1
}
diff --git a/llvm/test/CodeGen/ARM/atomic-load-store.ll b/llvm/test/CodeGen/ARM/atomic-load-store.ll
index ac33e4c65ca83..4f2e63b5f2467 100644
--- a/llvm/test/CodeGen/ARM/atomic-load-store.ll
+++ b/llvm/test/CodeGen/ARM/atomic-load-store.ll
@@ -7,7 +7,7 @@
; RUN: llc < %s -mtriple=armv6 | FileCheck %s -check-prefix=ARMV6
; RUN: llc < %s -mtriple=thumbv7m | FileCheck %s -check-prefix=THUMBM
-define void @test1(i32* %ptr, i32 %val1) {
+define void @test1(ptr %ptr, i32 %val1) {
; ARM-LABEL: test1:
; ARM: @ %bb.0:
; ARM-NEXT: dmb ish
@@ -57,11 +57,11 @@ define void @test1(i32* %ptr, i32 %val1) {
; THUMBM-NEXT: str r1, [r0]
; THUMBM-NEXT: dmb sy
; THUMBM-NEXT: bx lr
- store atomic i32 %val1, i32* %ptr seq_cst, align 4
+ store atomic i32 %val1, ptr %ptr seq_cst, align 4
ret void
}
-define i32 @test2(i32* %ptr) {
+define i32 @test2(ptr %ptr) {
; ARM-LABEL: test2:
; ARM: @ %bb.0:
; ARM-NEXT: ldr r0, [r0]
@@ -108,11 +108,11 @@ define i32 @test2(i32* %ptr) {
; THUMBM-NEXT: ldr r0, [r0]
; THUMBM-NEXT: dmb sy
; THUMBM-NEXT: bx lr
- %val = load atomic i32, i32* %ptr seq_cst, align 4
+ %val = load atomic i32, ptr %ptr seq_cst, align 4
ret i32 %val
}
-define void @test3(i8* %ptr1, i8* %ptr2) {
+define void @test3(ptr %ptr1, ptr %ptr2) {
; ARM-LABEL: test3:
; ARM: @ %bb.0:
; ARM-NEXT: ldrb r0, [r0]
@@ -164,12 +164,12 @@ define void @test3(i8* %ptr1, i8* %ptr2) {
- %val = load atomic i8, i8* %ptr1 unordered, align 1
- store atomic i8 %val, i8* %ptr2 unordered, align 1
+ %val = load atomic i8, ptr %ptr1 unordered, align 1
+ store atomic i8 %val, ptr %ptr2 unordered, align 1
ret void
}
-define void @test4(i8* %ptr1, i8* %ptr2) {
+define void @test4(ptr %ptr1, ptr %ptr2) {
; ARM-LABEL: test4:
; ARM: @ %bb.0:
; ARM-NEXT: ldrb r0, [r0]
@@ -239,12 +239,12 @@ define void @test4(i8* %ptr1, i8* %ptr2) {
; THUMBM-NEXT: strb r0, [r1]
; THUMBM-NEXT: dmb sy
; THUMBM-NEXT: bx lr
- %val = load atomic i8, i8* %ptr1 seq_cst, align 1
- store atomic i8 %val, i8* %ptr2 seq_cst, align 1
+ %val = load atomic i8, ptr %ptr1 seq_cst, align 1
+ store atomic i8 %val, ptr %ptr2 seq_cst, align 1
ret void
}
-define i64 @test_old_load_64bit(i64* %p) {
+define i64 @test_old_load_64bit(ptr %p) {
; ARM-LABEL: test_old_load_64bit:
; ARM: @ %bb.0:
; ARM-NEXT: ldrexd r0, r1, [r0]
@@ -301,11 +301,11 @@ define i64 @test_old_load_64bit(i64* %p) {
; THUMBM-NEXT: movs r1, #5
; THUMBM-NEXT: bl __atomic_load_8
; THUMBM-NEXT: pop {r7, pc}
- %1 = load atomic i64, i64* %p seq_cst, align 8
+ %1 = load atomic i64, ptr %p seq_cst, align 8
ret i64 %1
}
-define void @test_old_store_64bit(i64* %p, i64 %v) {
+define void @test_old_store_64bit(ptr %p, i64 %v) {
; ARM-LABEL: test_old_store_64bit:
; ARM: @ %bb.0:
; ARM-NEXT: push {r4, r5, lr}
@@ -436,6 +436,6 @@ define void @test_old_store_64bit(i64* %p, i64 %v) {
; THUMBM-NEXT: bl __atomic_store_8
; THUMBM-NEXT: add sp, #8
; THUMBM-NEXT: pop {r7, pc}
- store atomic i64 %v, i64* %p seq_cst, align 8
+ store atomic i64 %v, ptr %p seq_cst, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/atomic-op.ll b/llvm/test/CodeGen/ARM/atomic-op.ll
index d831c94108e40..9cbed5e98b004 100644
--- a/llvm/test/CodeGen/ARM/atomic-op.ll
+++ b/llvm/test/CodeGen/ARM/atomic-op.ll
@@ -7,26 +7,26 @@
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
; CHECK-LABEL: _func:
-define void @func(i32 %argc, i8** %argv) nounwind {
+define void @func(i32 %argc, ptr %argv) nounwind {
entry:
- %argc.addr = alloca i32 ; <i32*> [#uses=1]
- %argv.addr = alloca i8** ; <i8***> [#uses=1]
- %val1 = alloca i32 ; <i32*> [#uses=2]
- %val2 = alloca i32 ; <i32*> [#uses=15]
- %andt = alloca i32 ; <i32*> [#uses=2]
- %ort = alloca i32 ; <i32*> [#uses=2]
- %xort = alloca i32 ; <i32*> [#uses=2]
- %old = alloca i32 ; <i32*> [#uses=18]
- %temp = alloca i32 ; <i32*> [#uses=2]
- store i32 %argc, i32* %argc.addr
- store i8** %argv, i8*** %argv.addr
- store i32 0, i32* %val1
- store i32 31, i32* %val2
- store i32 3855, i32* %andt
- store i32 3855, i32* %ort
- store i32 3855, i32* %xort
- store i32 4, i32* %temp
- %tmp = load i32, i32* %temp
+ %argc.addr = alloca i32 ; <ptr> [#uses=1]
+ %argv.addr = alloca ptr ; <ptr> [#uses=1]
+ %val1 = alloca i32 ; <ptr> [#uses=2]
+ %val2 = alloca i32 ; <ptr> [#uses=15]
+ %andt = alloca i32 ; <ptr> [#uses=2]
+ %ort = alloca i32 ; <ptr> [#uses=2]
+ %xort = alloca i32 ; <ptr> [#uses=2]
+ %old = alloca i32 ; <ptr> [#uses=18]
+ %temp = alloca i32 ; <ptr> [#uses=2]
+ store i32 %argc, ptr %argc.addr
+ store ptr %argv, ptr %argv.addr
+ store i32 0, ptr %val1
+ store i32 31, ptr %val2
+ store i32 3855, ptr %andt
+ store i32 3855, ptr %ort
+ store i32 3855, ptr %xort
+ store i32 4, ptr %temp
+ %tmp = load i32, ptr %temp
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
; CHECK: ldrex
; CHECK: add
@@ -35,8 +35,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_fetch_add_4
; CHECK-BAREMETAL: add
; CHECK-BAREMETAL-NOT: __sync
- %0 = atomicrmw add i32* %val1, i32 %tmp monotonic
- store i32 %0, i32* %old
+ %0 = atomicrmw add ptr %val1, i32 %tmp monotonic
+ store i32 %0, ptr %old
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
; CHECK: ldrex
; CHECK: sub
@@ -45,8 +45,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_fetch_sub_4
; CHECK-BAREMETAL: sub
; CHECK-BAREMETAL-NOT: __sync
- %1 = atomicrmw sub i32* %val2, i32 30 monotonic
- store i32 %1, i32* %old
+ %1 = atomicrmw sub ptr %val2, i32 30 monotonic
+ store i32 %1, ptr %old
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
; CHECK: ldrex
; CHECK: add
@@ -55,8 +55,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_fetch_add_4
; CHECK-BAREMETAL: add
; CHECK-BAREMETAL-NOT: __sync
- %2 = atomicrmw add i32* %val2, i32 1 monotonic
- store i32 %2, i32* %old
+ %2 = atomicrmw add ptr %val2, i32 1 monotonic
+ store i32 %2, ptr %old
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
; CHECK: ldrex
; CHECK: sub
@@ -65,8 +65,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_fetch_sub_4
; CHECK-BAREMETAL: sub
; CHECK-BAREMETAL-NOT: __sync
- %3 = atomicrmw sub i32* %val2, i32 1 monotonic
- store i32 %3, i32* %old
+ %3 = atomicrmw sub ptr %val2, i32 1 monotonic
+ store i32 %3, ptr %old
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
; CHECK: ldrex
; CHECK: and
@@ -75,8 +75,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_fetch_and_4
; CHECK-BAREMETAL: and
; CHECK-BAREMETAL-NOT: __sync
- %4 = atomicrmw and i32* %andt, i32 4080 monotonic
- store i32 %4, i32* %old
+ %4 = atomicrmw and ptr %andt, i32 4080 monotonic
+ store i32 %4, ptr %old
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
; CHECK: ldrex
; CHECK: or
@@ -85,8 +85,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_fetch_or_4
; CHECK-BAREMETAL: or
; CHECK-BAREMETAL-NOT: __sync
- %5 = atomicrmw or i32* %ort, i32 4080 monotonic
- store i32 %5, i32* %old
+ %5 = atomicrmw or ptr %ort, i32 4080 monotonic
+ store i32 %5, ptr %old
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
; CHECK: ldrex
; CHECK: eor
@@ -95,8 +95,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_fetch_xor_4
; CHECK-BAREMETAL: eor
; CHECK-BAREMETAL-NOT: __sync
- %6 = atomicrmw xor i32* %xort, i32 4080 monotonic
- store i32 %6, i32* %old
+ %6 = atomicrmw xor ptr %xort, i32 4080 monotonic
+ store i32 %6, ptr %old
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
; CHECK: ldrex
; CHECK: cmp
@@ -105,8 +105,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_compare_exchange_4
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
- %7 = atomicrmw min i32* %val2, i32 16 monotonic
- store i32 %7, i32* %old
+ %7 = atomicrmw min ptr %val2, i32 16 monotonic
+ store i32 %7, ptr %old
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
%neg = sub i32 0, 1
; CHECK: ldrex
@@ -116,8 +116,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_compare_exchange_4
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
- %8 = atomicrmw min i32* %val2, i32 %neg monotonic
- store i32 %8, i32* %old
+ %8 = atomicrmw min ptr %val2, i32 %neg monotonic
+ store i32 %8, ptr %old
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
; CHECK: ldrex
; CHECK: cmp
@@ -126,8 +126,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_compare_exchange_4
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
- %9 = atomicrmw max i32* %val2, i32 1 monotonic
- store i32 %9, i32* %old
+ %9 = atomicrmw max ptr %val2, i32 1 monotonic
+ store i32 %9, ptr %old
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
; CHECK: ldrex
; CHECK: bic
@@ -137,8 +137,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_compare_exchange_4
; CHECK-BAREMETAL: bic
; CHECK-BAREMETAL-NOT: __sync
- %10 = atomicrmw max i32* %val2, i32 0 monotonic
- store i32 %10, i32* %old
+ %10 = atomicrmw max ptr %val2, i32 0 monotonic
+ store i32 %10, ptr %old
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
; CHECK: ldrex
; CHECK: cmp
@@ -147,8 +147,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_compare_exchange_4
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
- %11 = atomicrmw umin i32* %val2, i32 16 monotonic
- store i32 %11, i32* %old
+ %11 = atomicrmw umin ptr %val2, i32 16 monotonic
+ store i32 %11, ptr %old
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
%uneg = sub i32 0, 1
; CHECK: ldrex
@@ -158,8 +158,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_compare_exchange_4
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
- %12 = atomicrmw umin i32* %val2, i32 %uneg monotonic
- store i32 %12, i32* %old
+ %12 = atomicrmw umin ptr %val2, i32 %uneg monotonic
+ store i32 %12, ptr %old
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
; CHECK: ldrex
; CHECK: strex
@@ -168,8 +168,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_compare_exchange_4
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
- %13 = atomicrmw umax i32* %val2, i32 1 monotonic
- store i32 %13, i32* %old
+ %13 = atomicrmw umax ptr %val2, i32 1 monotonic
+ store i32 %13, ptr %old
call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
; CHECK: ldrex
; CHECK: strex
@@ -178,8 +178,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_compare_exchange_4
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
- %14 = atomicrmw umax i32* %val2, i32 0 monotonic
- store i32 %14, i32* %old
+ %14 = atomicrmw umax ptr %val2, i32 0 monotonic
+ store i32 %14, ptr %old
ret void
}
@@ -189,7 +189,7 @@ define void @func2() nounwind {
entry:
%val = alloca i16
%old = alloca i16
- store i16 31, i16* %val
+ store i16 31, ptr %val
; CHECK: ldrex
; CHECK: strex
; CHECK: cmp
@@ -197,8 +197,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_compare_exchange_2
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
- %0 = atomicrmw umin i16* %val, i16 16 monotonic
- store i16 %0, i16* %old
+ %0 = atomicrmw umin ptr %val, i16 16 monotonic
+ store i16 %0, ptr %old
%uneg = sub i16 0, 1
; CHECK: ldrex
; CHECK: strex
@@ -207,8 +207,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_compare_exchange_2
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
- %1 = atomicrmw umin i16* %val, i16 %uneg monotonic
- store i16 %1, i16* %old
+ %1 = atomicrmw umin ptr %val, i16 %uneg monotonic
+ store i16 %1, ptr %old
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
@@ -216,8 +216,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_compare_exchange_2
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
- %2 = atomicrmw umax i16* %val, i16 1 monotonic
- store i16 %2, i16* %old
+ %2 = atomicrmw umax ptr %val, i16 1 monotonic
+ store i16 %2, ptr %old
; CHECK: ldrex
; CHECK: strex
; CHECK: cmp
@@ -225,8 +225,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_compare_exchange_2
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
- %3 = atomicrmw umax i16* %val, i16 0 monotonic
- store i16 %3, i16* %old
+ %3 = atomicrmw umax ptr %val, i16 0 monotonic
+ store i16 %3, ptr %old
ret void
}
@@ -235,7 +235,7 @@ define void @func3() nounwind {
entry:
%val = alloca i8
%old = alloca i8
- store i8 31, i8* %val
+ store i8 31, ptr %val
; CHECK: ldrex
; CHECK: strex
; CHECK: cmp
@@ -243,8 +243,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_compare_exchange_1
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
- %0 = atomicrmw umin i8* %val, i8 16 monotonic
- store i8 %0, i8* %old
+ %0 = atomicrmw umin ptr %val, i8 16 monotonic
+ store i8 %0, ptr %old
; CHECK: ldrex
; CHECK: strex
; CHECK: cmp
@@ -253,8 +253,8 @@ entry:
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%uneg = sub i8 0, 1
- %1 = atomicrmw umin i8* %val, i8 %uneg monotonic
- store i8 %1, i8* %old
+ %1 = atomicrmw umin ptr %val, i8 %uneg monotonic
+ store i8 %1, ptr %old
; CHECK: ldrex
; CHECK: strex
; CHECK: cmp
@@ -262,8 +262,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_compare_exchange_1
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
- %2 = atomicrmw umax i8* %val, i8 1 monotonic
- store i8 %2, i8* %old
+ %2 = atomicrmw umax ptr %val, i8 1 monotonic
+ store i8 %2, ptr %old
; CHECK: ldrex
; CHECK: strex
; CHECK: cmp
@@ -271,8 +271,8 @@ entry:
; CHECK-T1-M0: bl ___atomic_compare_exchange_1
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
- %3 = atomicrmw umax i8* %val, i8 0 monotonic
- store i8 %3, i8* %old
+ %3 = atomicrmw umax ptr %val, i8 0 monotonic
+ store i8 %3, ptr %old
ret void
}
@@ -280,16 +280,16 @@ entry:
; This function should not need to use callee-saved registers.
; rdar://problem/12203728
; CHECK-NOT: r4
-define i32 @func4(i32* %p) nounwind optsize ssp {
+define i32 @func4(ptr %p) nounwind optsize ssp {
entry:
- %0 = atomicrmw add i32* %p, i32 1 monotonic
+ %0 = atomicrmw add ptr %p, i32 1 monotonic
ret i32 %0
}
-define i32 @test_cmpxchg_fail_order(i32 *%addr, i32 %desired, i32 %new) {
+define i32 @test_cmpxchg_fail_order(ptr %addr, i32 %desired, i32 %new) {
; CHECK-LABEL: test_cmpxchg_fail_order:
- %pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
+ %pair = cmpxchg ptr %addr, i32 %desired, i32 %new seq_cst monotonic
%oldval = extractvalue { i32, i1 } %pair, 0
; CHECK-ARMV7: mov r[[ADDR:[0-9]+]], r0
; CHECK-ARMV7: ldrex [[OLDVAL:r[0-9]+]], [r0]
@@ -328,10 +328,10 @@ define i32 @test_cmpxchg_fail_order(i32 *%addr, i32 %desired, i32 %new) {
ret i32 %oldval
}
-define i32 @test_cmpxchg_fail_order1(i32 *%addr, i32 %desired, i32 %new) {
+define i32 @test_cmpxchg_fail_order1(ptr %addr, i32 %desired, i32 %new) {
; CHECK-LABEL: test_cmpxchg_fail_order1:
- %pair = cmpxchg i32* %addr, i32 %desired, i32 %new acquire acquire
+ %pair = cmpxchg ptr %addr, i32 %desired, i32 %new acquire acquire
%oldval = extractvalue { i32, i1 } %pair, 0
; CHECK-NOT: dmb ish
; CHECK: [[LOOP_BB:\.?LBB[0-9]+_1]]:
@@ -351,10 +351,10 @@ define i32 @test_cmpxchg_fail_order1(i32 *%addr, i32 %desired, i32 %new) {
ret i32 %oldval
}
-define i32 @load_load_add_acquire(i32* %mem1, i32* %mem2) nounwind {
+define i32 @load_load_add_acquire(ptr %mem1, ptr %mem2) nounwind {
; CHECK-LABEL: load_load_add_acquire
- %val1 = load atomic i32, i32* %mem1 acquire, align 4
- %val2 = load atomic i32, i32* %mem2 acquire, align 4
+ %val1 = load atomic i32, ptr %mem1 acquire, align 4
+ %val2 = load atomic i32, ptr %mem2 acquire, align 4
%tmp = add i32 %val1, %val2
; CHECK: ldr {{r[0-9]}}, [r0]
@@ -378,10 +378,10 @@ define i32 @load_load_add_acquire(i32* %mem1, i32* %mem2) nounwind {
ret i32 %tmp
}
-define void @store_store_release(i32* %mem1, i32 %val1, i32* %mem2, i32 %val2) {
+define void @store_store_release(ptr %mem1, i32 %val1, ptr %mem2, i32 %val2) {
; CHECK-LABEL: store_store_release
- store atomic i32 %val1, i32* %mem1 release, align 4
- store atomic i32 %val2, i32* %mem2 release, align 4
+ store atomic i32 %val1, ptr %mem1 release, align 4
+ store atomic i32 %val2, ptr %mem2 release, align 4
; CHECK: dmb
; CHECK: str r1, [r0]
@@ -402,11 +402,11 @@ define void @store_store_release(i32* %mem1, i32 %val1, i32* %mem2, i32 %val2) {
ret void
}
-define void @load_fence_store_monotonic(i32* %mem1, i32* %mem2) {
+define void @load_fence_store_monotonic(ptr %mem1, ptr %mem2) {
; CHECK-LABEL: load_fence_store_monotonic
- %val = load atomic i32, i32* %mem1 monotonic, align 4
+ %val = load atomic i32, ptr %mem1 monotonic, align 4
fence seq_cst
- store atomic i32 %val, i32* %mem2 monotonic, align 4
+ store atomic i32 %val, ptr %mem2 monotonic, align 4
; CHECK: ldr [[R0:r[0-9]]], [r0]
; CHECK: dmb
diff --git a/llvm/test/CodeGen/ARM/atomic-ops-m33.ll b/llvm/test/CodeGen/ARM/atomic-ops-m33.ll
index 4eadded66226b..97969082cb991 100644
--- a/llvm/test/CodeGen/ARM/atomic-ops-m33.ll
+++ b/llvm/test/CodeGen/ARM/atomic-ops-m33.ll
@@ -2,7 +2,7 @@
define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_add_i8:
- %old = atomicrmw add i8* @var8, i8 %offset seq_cst
+ %old = atomicrmw add ptr @var8, i8 %offset seq_cst
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
@@ -25,7 +25,7 @@ define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_add_i16:
- %old = atomicrmw add i16* @var16, i16 %offset acquire
+ %old = atomicrmw add ptr @var16, i16 %offset acquire
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
@@ -48,7 +48,7 @@ define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_add_i32:
- %old = atomicrmw add i32* @var32, i32 %offset release
+ %old = atomicrmw add ptr @var32, i32 %offset release
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
@@ -72,64 +72,64 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
define void @test_atomic_load_add_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_add_i64:
; CHECK: bl __atomic_fetch_add_8
- %old = atomicrmw add i64* @var64, i64 %offset monotonic
- store i64 %old, i64* @var64
+ %old = atomicrmw add ptr @var64, i64 %offset monotonic
+ store i64 %old, ptr @var64
ret void
}
-define i8 @test_load_acquire_i8(i8* %ptr) {
+define i8 @test_load_acquire_i8(ptr %ptr) {
; CHECK-LABEL: test_load_acquire_i8:
; CHECK: ldab r0, [r0]
- %val = load atomic i8, i8* %ptr seq_cst, align 1
+ %val = load atomic i8, ptr %ptr seq_cst, align 1
ret i8 %val
}
-define i16 @test_load_acquire_i16(i16* %ptr) {
+define i16 @test_load_acquire_i16(ptr %ptr) {
; CHECK-LABEL: test_load_acquire_i16:
; CHECK: ldah r0, [r0]
- %val = load atomic i16, i16* %ptr acquire, align 2
+ %val = load atomic i16, ptr %ptr acquire, align 2
ret i16 %val
}
-define i32 @test_load_acquire_i32(i32* %ptr) {
+define i32 @test_load_acquire_i32(ptr %ptr) {
; CHECK-LABEL: test_load_acquire_i32:
; CHECK: lda r0, [r0]
- %val = load atomic i32, i32* %ptr acquire, align 4
+ %val = load atomic i32, ptr %ptr acquire, align 4
ret i32 %val
}
-define i64 @test_load_acquire_i64(i64* %ptr) {
+define i64 @test_load_acquire_i64(ptr %ptr) {
; CHECK-LABEL: test_load_acquire_i64:
; CHECK: bl __atomic_load
- %val = load atomic i64, i64* %ptr acquire, align 4
+ %val = load atomic i64, ptr %ptr acquire, align 4
ret i64 %val
}
-define void @test_store_release_i8(i8 %val, i8* %ptr) {
+define void @test_store_release_i8(i8 %val, ptr %ptr) {
; CHECK-LABEL: test_store_release_i8:
; CHECK: stlb r0, [r1]
- store atomic i8 %val, i8* %ptr seq_cst, align 1
+ store atomic i8 %val, ptr %ptr seq_cst, align 1
ret void
}
-define void @test_store_release_i16(i16 %val, i16* %ptr) {
+define void @test_store_release_i16(i16 %val, ptr %ptr) {
; CHECK-LABEL: test_store_release_i16:
; CHECK: stlh r0, [r1]
- store atomic i16 %val, i16* %ptr release, align 2
+ store atomic i16 %val, ptr %ptr release, align 2
ret void
}
-define void @test_store_release_i32(i32 %val, i32* %ptr) {
+define void @test_store_release_i32(i32 %val, ptr %ptr) {
; CHECK-LABEL: test_store_release_i32:
; CHECK: stl r0, [r1]
- store atomic i32 %val, i32* %ptr seq_cst, align 4
+ store atomic i32 %val, ptr %ptr seq_cst, align 4
ret void
}
-define void @test_store_release_i64(i64 %val, i64* %ptr) {
+define void @test_store_release_i64(i64 %val, ptr %ptr) {
; CHECK-LABEL: test_store_release_i64:
; CHECK: bl __atomic_store
- store atomic i64 %val, i64* %ptr seq_cst, align 4
+ store atomic i64 %val, ptr %ptr seq_cst, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/atomic-ops-v8.ll b/llvm/test/CodeGen/ARM/atomic-ops-v8.ll
index faf0f4d7ed6f8..0a467c2b70acf 100644
--- a/llvm/test/CodeGen/ARM/atomic-ops-v8.ll
+++ b/llvm/test/CodeGen/ARM/atomic-ops-v8.ll
@@ -10,7 +10,7 @@
define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_add_i8:
- %old = atomicrmw add i8* @var8, i8 %offset seq_cst
+ %old = atomicrmw add ptr @var8, i8 %offset seq_cst
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
@@ -33,7 +33,7 @@ define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_add_i16:
- %old = atomicrmw add i16* @var16, i16 %offset acquire
+ %old = atomicrmw add ptr @var16, i16 %offset acquire
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
@@ -56,7 +56,7 @@ define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_add_i32:
- %old = atomicrmw add i32* @var32, i32 %offset release
+ %old = atomicrmw add ptr @var32, i32 %offset release
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
@@ -79,7 +79,7 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
define void @test_atomic_load_add_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_add_i64:
- %old = atomicrmw add i64* @var64, i64 %offset monotonic
+ %old = atomicrmw add ptr @var64, i64 %offset monotonic
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
@@ -100,13 +100,13 @@ define void @test_atomic_load_add_i64(i64 %offset) nounwind {
; CHECK-NOT: mcr
; CHECK: strd r[[OLD1]], r[[OLD2]], [r[[ADDR]]]
- store i64 %old, i64* @var64
+ store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_sub_i8:
- %old = atomicrmw sub i8* @var8, i8 %offset monotonic
+ %old = atomicrmw sub ptr @var8, i8 %offset monotonic
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
@@ -129,7 +129,7 @@ define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_sub_i16:
- %old = atomicrmw sub i16* @var16, i16 %offset release
+ %old = atomicrmw sub ptr @var16, i16 %offset release
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
@@ -152,7 +152,7 @@ define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_sub_i32:
- %old = atomicrmw sub i32* @var32, i32 %offset acquire
+ %old = atomicrmw sub ptr @var32, i32 %offset acquire
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
@@ -175,7 +175,7 @@ define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
define void @test_atomic_load_sub_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_sub_i64:
- %old = atomicrmw sub i64* @var64, i64 %offset seq_cst
+ %old = atomicrmw sub ptr @var64, i64 %offset seq_cst
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
@@ -196,13 +196,13 @@ define void @test_atomic_load_sub_i64(i64 %offset) nounwind {
; CHECK-NOT: mcr
; CHECK: strd r[[OLD1]], r[[OLD2]], [r[[ADDR]]]
- store i64 %old, i64* @var64
+ store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_and_i8:
- %old = atomicrmw and i8* @var8, i8 %offset release
+ %old = atomicrmw and ptr @var8, i8 %offset release
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
@@ -225,7 +225,7 @@ define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_and_i16:
- %old = atomicrmw and i16* @var16, i16 %offset monotonic
+ %old = atomicrmw and ptr @var16, i16 %offset monotonic
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
@@ -248,7 +248,7 @@ define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_and_i32:
- %old = atomicrmw and i32* @var32, i32 %offset seq_cst
+ %old = atomicrmw and ptr @var32, i32 %offset seq_cst
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
@@ -271,7 +271,7 @@ define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
define void @test_atomic_load_and_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_and_i64:
- %old = atomicrmw and i64* @var64, i64 %offset acquire
+ %old = atomicrmw and ptr @var64, i64 %offset acquire
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
@@ -292,13 +292,13 @@ define void @test_atomic_load_and_i64(i64 %offset) nounwind {
; CHECK-NOT: mcr
; CHECK: strd r[[OLD1]], r[[OLD2]], [r[[ADDR]]]
- store i64 %old, i64* @var64
+ store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_or_i8:
- %old = atomicrmw or i8* @var8, i8 %offset seq_cst
+ %old = atomicrmw or ptr @var8, i8 %offset seq_cst
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
@@ -321,7 +321,7 @@ define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_or_i16:
- %old = atomicrmw or i16* @var16, i16 %offset monotonic
+ %old = atomicrmw or ptr @var16, i16 %offset monotonic
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
@@ -344,7 +344,7 @@ define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_or_i32:
- %old = atomicrmw or i32* @var32, i32 %offset acquire
+ %old = atomicrmw or ptr @var32, i32 %offset acquire
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
@@ -367,7 +367,7 @@ define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
define void @test_atomic_load_or_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_or_i64:
- %old = atomicrmw or i64* @var64, i64 %offset release
+ %old = atomicrmw or ptr @var64, i64 %offset release
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
@@ -388,13 +388,13 @@ define void @test_atomic_load_or_i64(i64 %offset) nounwind {
; CHECK-NOT: mcr
; CHECK: strd r[[OLD1]], r[[OLD2]], [r[[ADDR]]]
- store i64 %old, i64* @var64
+ store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xor_i8:
- %old = atomicrmw xor i8* @var8, i8 %offset acquire
+ %old = atomicrmw xor ptr @var8, i8 %offset acquire
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
@@ -417,7 +417,7 @@ define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xor_i16:
- %old = atomicrmw xor i16* @var16, i16 %offset release
+ %old = atomicrmw xor ptr @var16, i16 %offset release
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
@@ -440,7 +440,7 @@ define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xor_i32:
- %old = atomicrmw xor i32* @var32, i32 %offset seq_cst
+ %old = atomicrmw xor ptr @var32, i32 %offset seq_cst
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
@@ -463,7 +463,7 @@ define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
define void @test_atomic_load_xor_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xor_i64:
- %old = atomicrmw xor i64* @var64, i64 %offset monotonic
+ %old = atomicrmw xor ptr @var64, i64 %offset monotonic
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
@@ -484,13 +484,13 @@ define void @test_atomic_load_xor_i64(i64 %offset) nounwind {
; CHECK-NOT: mcr
; CHECK: strd r[[OLD1]], r[[OLD2]], [r[[ADDR]]]
- store i64 %old, i64* @var64
+ store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xchg_i8:
- %old = atomicrmw xchg i8* @var8, i8 %offset monotonic
+ %old = atomicrmw xchg ptr @var8, i8 %offset monotonic
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
@@ -512,7 +512,7 @@ define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xchg_i16:
- %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst
+ %old = atomicrmw xchg ptr @var16, i16 %offset seq_cst
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
@@ -534,7 +534,7 @@ define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xchg_i32:
- %old = atomicrmw xchg i32* @var32, i32 %offset release
+ %old = atomicrmw xchg ptr @var32, i32 %offset release
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
@@ -556,7 +556,7 @@ define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
define void @test_atomic_load_xchg_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xchg_i64:
- %old = atomicrmw xchg i64* @var64, i64 %offset acquire
+ %old = atomicrmw xchg ptr @var64, i64 %offset acquire
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
@@ -573,13 +573,13 @@ define void @test_atomic_load_xchg_i64(i64 %offset) nounwind {
; CHECK-NOT: mcr
; CHECK: strd [[OLD1]], [[OLD2]], [r[[ADDR]]]
- store i64 %old, i64* @var64
+ store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_min_i8(i8 signext %offset) nounwind {
; CHECK-LABEL: test_atomic_load_min_i8:
- %old = atomicrmw min i8* @var8, i8 %offset acquire
+ %old = atomicrmw min ptr @var8, i8 %offset acquire
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK-DAG: movw [[ADDR:r[0-9]+|lr]], :lower16:var8
@@ -605,7 +605,7 @@ define i8 @test_atomic_load_min_i8(i8 signext %offset) nounwind {
define i16 @test_atomic_load_min_i16(i16 signext %offset) nounwind {
; CHECK-LABEL: test_atomic_load_min_i16:
- %old = atomicrmw min i16* @var16, i16 %offset release
+ %old = atomicrmw min ptr @var16, i16 %offset release
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var16
@@ -631,7 +631,7 @@ define i16 @test_atomic_load_min_i16(i16 signext %offset) nounwind {
define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_min_i32:
- %old = atomicrmw min i32* @var32, i32 %offset monotonic
+ %old = atomicrmw min ptr @var32, i32 %offset monotonic
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
@@ -657,7 +657,7 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
define void @test_atomic_load_min_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_min_i64:
- %old = atomicrmw min i64* @var64, i64 %offset seq_cst
+ %old = atomicrmw min ptr @var64, i64 %offset seq_cst
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
@@ -686,13 +686,13 @@ define void @test_atomic_load_min_i64(i64 %offset) nounwind {
; CHECK-NOT: mcr
; CHECK-ARM: strd [[OLD1]], [[OLD2]], [r[[ADDR]]]
- store i64 %old, i64* @var64
+ store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_max_i8(i8 signext %offset) nounwind {
; CHECK-LABEL: test_atomic_load_max_i8:
- %old = atomicrmw max i8* @var8, i8 %offset seq_cst
+ %old = atomicrmw max ptr @var8, i8 %offset seq_cst
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var8
@@ -718,7 +718,7 @@ define i8 @test_atomic_load_max_i8(i8 signext %offset) nounwind {
define i16 @test_atomic_load_max_i16(i16 signext %offset) nounwind {
; CHECK-LABEL: test_atomic_load_max_i16:
- %old = atomicrmw max i16* @var16, i16 %offset acquire
+ %old = atomicrmw max ptr @var16, i16 %offset acquire
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
@@ -744,7 +744,7 @@ define i16 @test_atomic_load_max_i16(i16 signext %offset) nounwind {
define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_max_i32:
- %old = atomicrmw max i32* @var32, i32 %offset release
+ %old = atomicrmw max ptr @var32, i32 %offset release
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
@@ -770,7 +770,7 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
define void @test_atomic_load_max_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_max_i64:
- %old = atomicrmw max i64* @var64, i64 %offset monotonic
+ %old = atomicrmw max ptr @var64, i64 %offset monotonic
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
@@ -799,13 +799,13 @@ define void @test_atomic_load_max_i64(i64 %offset) nounwind {
; CHECK-NOT: mcr
; CHECK-ARM: strd [[OLD1]], [[OLD2]], [r[[ADDR]]]
- store i64 %old, i64* @var64
+ store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_umin_i8(i8 zeroext %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umin_i8:
- %old = atomicrmw umin i8* @var8, i8 %offset monotonic
+ %old = atomicrmw umin ptr @var8, i8 %offset monotonic
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var8
@@ -831,7 +831,7 @@ define i8 @test_atomic_load_umin_i8(i8 zeroext %offset) nounwind {
define i16 @test_atomic_load_umin_i16(i16 zeroext %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umin_i16:
- %old = atomicrmw umin i16* @var16, i16 %offset acquire
+ %old = atomicrmw umin ptr @var16, i16 %offset acquire
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var16
@@ -857,7 +857,7 @@ define i16 @test_atomic_load_umin_i16(i16 zeroext %offset) nounwind {
define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umin_i32:
- %old = atomicrmw umin i32* @var32, i32 %offset seq_cst
+ %old = atomicrmw umin ptr @var32, i32 %offset seq_cst
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
@@ -883,7 +883,7 @@ define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
define void @test_atomic_load_umin_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umin_i64:
- %old = atomicrmw umin i64* @var64, i64 %offset seq_cst
+ %old = atomicrmw umin ptr @var64, i64 %offset seq_cst
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
@@ -912,13 +912,13 @@ define void @test_atomic_load_umin_i64(i64 %offset) nounwind {
; CHECK-NOT: mcr
; CHECK-ARM: strd [[OLD1]], [[OLD2]], [r[[ADDR]]]
- store i64 %old, i64* @var64
+ store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_umax_i8(i8 zeroext %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umax_i8:
- %old = atomicrmw umax i8* @var8, i8 %offset acq_rel
+ %old = atomicrmw umax ptr @var8, i8 %offset acq_rel
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var8
@@ -944,7 +944,7 @@ define i8 @test_atomic_load_umax_i8(i8 zeroext %offset) nounwind {
define i16 @test_atomic_load_umax_i16(i16 zeroext %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umax_i16:
- %old = atomicrmw umax i16* @var16, i16 %offset monotonic
+ %old = atomicrmw umax ptr @var16, i16 %offset monotonic
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var16
@@ -970,7 +970,7 @@ define i16 @test_atomic_load_umax_i16(i16 zeroext %offset) nounwind {
define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umax_i32:
- %old = atomicrmw umax i32* @var32, i32 %offset seq_cst
+ %old = atomicrmw umax ptr @var32, i32 %offset seq_cst
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
@@ -996,7 +996,7 @@ define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
define void @test_atomic_load_umax_i64(i64 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_umax_i64:
- %old = atomicrmw umax i64* @var64, i64 %offset seq_cst
+ %old = atomicrmw umax ptr @var64, i64 %offset seq_cst
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
@@ -1025,13 +1025,13 @@ define void @test_atomic_load_umax_i64(i64 %offset) nounwind {
; CHECK-NOT: mcr
; CHECK-ARM: strd [[OLD1]], [[OLD2]], [r[[ADDR]]]
- store i64 %old, i64* @var64
+ store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_cmpxchg_i8(i8 zeroext %wanted, i8 zeroext %new) nounwind {
; CHECK-LABEL: test_atomic_cmpxchg_i8:
- %pair = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire acquire
+ %pair = cmpxchg ptr @var8, i8 %wanted, i8 %new acquire acquire
%old = extractvalue { i8, i1 } %pair, 0
; CHECK-NOT: dmb
; CHECK-NOT: mcr
@@ -1063,7 +1063,7 @@ define i8 @test_atomic_cmpxchg_i8(i8 zeroext %wanted, i8 zeroext %new) nounwind
define i16 @test_atomic_cmpxchg_i16(i16 zeroext %wanted, i16 zeroext %new) nounwind {
; CHECK-LABEL: test_atomic_cmpxchg_i16:
- %pair = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst seq_cst
+ %pair = cmpxchg ptr @var16, i16 %wanted, i16 %new seq_cst seq_cst
%old = extractvalue { i16, i1 } %pair, 0
; CHECK-NOT: dmb
; CHECK-NOT: mcr
@@ -1099,9 +1099,9 @@ define i16 @test_atomic_cmpxchg_i16(i16 zeroext %wanted, i16 zeroext %new) nounw
define void @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
; CHECK-LABEL: test_atomic_cmpxchg_i32:
- %pair = cmpxchg i32* @var32, i32 %wanted, i32 %new release monotonic
+ %pair = cmpxchg ptr @var32, i32 %wanted, i32 %new release monotonic
%old = extractvalue { i32, i1 } %pair, 0
- store i32 %old, i32* @var32
+ store i32 %old, ptr @var32
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
@@ -1132,7 +1132,7 @@ define void @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
; CHECK-LABEL: test_atomic_cmpxchg_i64:
- %pair = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic monotonic
+ %pair = cmpxchg ptr @var64, i64 %wanted, i64 %new monotonic monotonic
%old = extractvalue { i64, i1 } %pair, 0
; CHECK-NOT: dmb
; CHECK-NOT: mcr
@@ -1165,13 +1165,13 @@ define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
; CHECK-NOT: mcr
; CHECK-ARM: strd [[OLD1]], [[OLD2]], [r[[ADDR]]]
- store i64 %old, i64* @var64
+ store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_monotonic_i8() nounwind {
; CHECK-LABEL: test_atomic_load_monotonic_i8:
- %val = load atomic i8, i8* @var8 monotonic, align 1
+ %val = load atomic i8, ptr @var8 monotonic, align 1
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
@@ -1186,9 +1186,9 @@ define i8 @test_atomic_load_monotonic_i8() nounwind {
define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
; CHECK-LABEL: test_atomic_load_monotonic_regoff_i8:
%addr_int = add i64 %base, %off
- %addr = inttoptr i64 %addr_int to i8*
+ %addr = inttoptr i64 %addr_int to ptr
- %val = load atomic i8, i8* %addr monotonic, align 1
+ %val = load atomic i8, ptr %addr monotonic, align 1
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK-LE: ldrb r0, [r0, r2]
@@ -1201,7 +1201,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
define i8 @test_atomic_load_acquire_i8() nounwind {
; CHECK-LABEL: test_atomic_load_acquire_i8:
- %val = load atomic i8, i8* @var8 acquire, align 1
+ %val = load atomic i8, ptr @var8 acquire, align 1
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
@@ -1218,7 +1218,7 @@ define i8 @test_atomic_load_acquire_i8() nounwind {
define i8 @test_atomic_load_seq_cst_i8() nounwind {
; CHECK-LABEL: test_atomic_load_seq_cst_i8:
- %val = load atomic i8, i8* @var8 seq_cst, align 1
+ %val = load atomic i8, ptr @var8 seq_cst, align 1
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
@@ -1235,7 +1235,7 @@ define i8 @test_atomic_load_seq_cst_i8() nounwind {
define i16 @test_atomic_load_monotonic_i16() nounwind {
; CHECK-LABEL: test_atomic_load_monotonic_i16:
- %val = load atomic i16, i16* @var16 monotonic, align 2
+ %val = load atomic i16, ptr @var16 monotonic, align 2
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
@@ -1254,9 +1254,9 @@ define i16 @test_atomic_load_monotonic_i16() nounwind {
define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind {
; CHECK-LABEL: test_atomic_load_monotonic_regoff_i32:
%addr_int = add i64 %base, %off
- %addr = inttoptr i64 %addr_int to i32*
+ %addr = inttoptr i64 %addr_int to ptr
- %val = load atomic i32, i32* %addr monotonic, align 4
+ %val = load atomic i32, ptr %addr monotonic, align 4
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK-LE: ldr r0, [r0, r2]
@@ -1269,7 +1269,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind
define i64 @test_atomic_load_seq_cst_i64() nounwind {
; CHECK-LABEL: test_atomic_load_seq_cst_i64:
- %val = load atomic i64, i64* @var64 seq_cst, align 8
+ %val = load atomic i64, ptr @var64 seq_cst, align 8
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
@@ -1286,7 +1286,7 @@ define i64 @test_atomic_load_seq_cst_i64() nounwind {
define void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
; CHECK-LABEL: test_atomic_store_monotonic_i8:
- store atomic i8 %val, i8* @var8 monotonic, align 1
+ store atomic i8 %val, ptr @var8 monotonic, align 1
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
; CHECK: movt r[[ADDR]], :upper16:var8
; CHECK: strb r0, [r[[ADDR]]]
@@ -1298,9 +1298,9 @@ define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val)
; CHECK-LABEL: test_atomic_store_monotonic_regoff_i8:
%addr_int = add i64 %base, %off
- %addr = inttoptr i64 %addr_int to i8*
+ %addr = inttoptr i64 %addr_int to ptr
- store atomic i8 %val, i8* %addr monotonic, align 1
+ store atomic i8 %val, ptr %addr monotonic, align 1
; CHECK-LE: ldr{{b?(\.w)?}} [[VAL:r[0-9]+]], [sp]
; CHECK-LE: strb [[VAL]], [r0, r2]
; CHECK-BE: ldrb{{(\.w)?}} [[VAL:r[0-9]+]], [sp, #3]
@@ -1311,7 +1311,7 @@ define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val)
define void @test_atomic_store_release_i8(i8 %val) nounwind {
; CHECK-LABEL: test_atomic_store_release_i8:
- store atomic i8 %val, i8* @var8 release, align 1
+ store atomic i8 %val, ptr @var8 release, align 1
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
@@ -1328,7 +1328,7 @@ define void @test_atomic_store_release_i8(i8 %val) nounwind {
define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
; CHECK-LABEL: test_atomic_store_seq_cst_i8:
- store atomic i8 %val, i8* @var8 seq_cst, align 1
+ store atomic i8 %val, ptr @var8 seq_cst, align 1
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
@@ -1345,7 +1345,7 @@ define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
define void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
; CHECK-LABEL: test_atomic_store_monotonic_i16:
- store atomic i16 %val, i16* @var16 monotonic, align 2
+ store atomic i16 %val, ptr @var16 monotonic, align 2
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
@@ -1364,9 +1364,9 @@ define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %va
; CHECK-LABEL: test_atomic_store_monotonic_regoff_i32:
%addr_int = add i64 %base, %off
- %addr = inttoptr i64 %addr_int to i32*
+ %addr = inttoptr i64 %addr_int to ptr
- store atomic i32 %val, i32* %addr monotonic, align 4
+ store atomic i32 %val, ptr %addr monotonic, align 4
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: ldr [[VAL:r[0-9]+]], [sp]
@@ -1382,7 +1382,7 @@ define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %va
define void @test_atomic_store_release_i64(i64 %val) nounwind {
; CHECK-LABEL: test_atomic_store_release_i64:
- store atomic i64 %val, i64* @var64 release, align 8
+ store atomic i64 %val, ptr @var64 release, align 8
; CHECK-NOT: dmb
; CHECK-NOT: mcr
; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var64
@@ -1400,17 +1400,17 @@ define void @test_atomic_store_release_i64(i64 %val) nounwind {
ret void
}
-define i32 @not.barriers(i32* %var, i1 %cond) {
+define i32 @not.barriers(ptr %var, i1 %cond) {
; CHECK-LABEL: not.barriers:
br i1 %cond, label %atomic_ver, label %simple_ver
simple_ver:
- %oldval = load i32, i32* %var
+ %oldval = load i32, ptr %var
%newval = add nsw i32 %oldval, -1
- store i32 %newval, i32* %var
+ store i32 %newval, ptr %var
br label %somewhere
atomic_ver:
fence seq_cst
- %val = atomicrmw add i32* %var, i32 -1 monotonic
+ %val = atomicrmw add ptr %var, i32 -1 monotonic
fence seq_cst
br label %somewhere
; CHECK: dmb
diff --git a/llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll b/llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
index 13a90adb96c04..161692137fc30 100644
--- a/llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
+++ b/llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
@@ -208,7 +208,7 @@ define i8 @test_xchg_i8() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw xchg i8* @atomic_i8, i8 1 monotonic
+ %0 = atomicrmw xchg ptr @atomic_i8, i8 1 monotonic
ret i8 %0
}
define i8 @test_add_i8() {
@@ -405,7 +405,7 @@ define i8 @test_add_i8() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw add i8* @atomic_i8, i8 1 monotonic
+ %0 = atomicrmw add ptr @atomic_i8, i8 1 monotonic
ret i8 %0
}
define i8 @test_sub_i8() {
@@ -602,7 +602,7 @@ define i8 @test_sub_i8() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw sub i8* @atomic_i8, i8 1 monotonic
+ %0 = atomicrmw sub ptr @atomic_i8, i8 1 monotonic
ret i8 %0
}
define i8 @test_and_i8() {
@@ -801,7 +801,7 @@ define i8 @test_and_i8() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw and i8* @atomic_i8, i8 1 monotonic
+ %0 = atomicrmw and ptr @atomic_i8, i8 1 monotonic
ret i8 %0
}
define i8 @test_nand_i8() {
@@ -1006,7 +1006,7 @@ define i8 @test_nand_i8() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw nand i8* @atomic_i8, i8 1 monotonic
+ %0 = atomicrmw nand ptr @atomic_i8, i8 1 monotonic
ret i8 %0
}
define i8 @test_or_i8() {
@@ -1205,7 +1205,7 @@ define i8 @test_or_i8() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw or i8* @atomic_i8, i8 1 monotonic
+ %0 = atomicrmw or ptr @atomic_i8, i8 1 monotonic
ret i8 %0
}
define i8 @test_xor_i8() {
@@ -1404,7 +1404,7 @@ define i8 @test_xor_i8() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw xor i8* @atomic_i8, i8 1 monotonic
+ %0 = atomicrmw xor ptr @atomic_i8, i8 1 monotonic
ret i8 %0
}
define i8 @test_max_i8() {
@@ -1625,7 +1625,7 @@ define i8 @test_max_i8() {
; CHECK-THUMB8BASE-NEXT: add sp, #20
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw max i8* @atomic_i8, i8 1 monotonic
+ %0 = atomicrmw max ptr @atomic_i8, i8 1 monotonic
ret i8 %0
}
define i8 @test_min_i8() {
@@ -1846,7 +1846,7 @@ define i8 @test_min_i8() {
; CHECK-THUMB8BASE-NEXT: add sp, #20
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw min i8* @atomic_i8, i8 1 monotonic
+ %0 = atomicrmw min ptr @atomic_i8, i8 1 monotonic
ret i8 %0
}
define i8 @test_umax_i8() {
@@ -2071,7 +2071,7 @@ define i8 @test_umax_i8() {
; CHECK-THUMB8BASE-NEXT: add sp, #24
; CHECK-THUMB8BASE-NEXT: pop {r4, r5, r7, pc}
entry:
- %0 = atomicrmw umax i8* @atomic_i8, i8 1 monotonic
+ %0 = atomicrmw umax ptr @atomic_i8, i8 1 monotonic
ret i8 %0
}
define i8 @test_umin_i8() {
@@ -2296,7 +2296,7 @@ define i8 @test_umin_i8() {
; CHECK-THUMB8BASE-NEXT: add sp, #24
; CHECK-THUMB8BASE-NEXT: pop {r4, r5, r7, pc}
entry:
- %0 = atomicrmw umin i8* @atomic_i8, i8 1 monotonic
+ %0 = atomicrmw umin ptr @atomic_i8, i8 1 monotonic
ret i8 %0
}
@@ -2495,7 +2495,7 @@ define i16 @test_xchg_i16() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw xchg i16* @atomic_i16, i16 1 monotonic
+ %0 = atomicrmw xchg ptr @atomic_i16, i16 1 monotonic
ret i16 %0
}
define i16 @test_add_i16() {
@@ -2692,7 +2692,7 @@ define i16 @test_add_i16() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw add i16* @atomic_i16, i16 1 monotonic
+ %0 = atomicrmw add ptr @atomic_i16, i16 1 monotonic
ret i16 %0
}
define i16 @test_sub_i16() {
@@ -2889,7 +2889,7 @@ define i16 @test_sub_i16() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw sub i16* @atomic_i16, i16 1 monotonic
+ %0 = atomicrmw sub ptr @atomic_i16, i16 1 monotonic
ret i16 %0
}
define i16 @test_and_i16() {
@@ -3088,7 +3088,7 @@ define i16 @test_and_i16() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw and i16* @atomic_i16, i16 1 monotonic
+ %0 = atomicrmw and ptr @atomic_i16, i16 1 monotonic
ret i16 %0
}
define i16 @test_nand_i16() {
@@ -3293,7 +3293,7 @@ define i16 @test_nand_i16() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw nand i16* @atomic_i16, i16 1 monotonic
+ %0 = atomicrmw nand ptr @atomic_i16, i16 1 monotonic
ret i16 %0
}
define i16 @test_or_i16() {
@@ -3492,7 +3492,7 @@ define i16 @test_or_i16() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw or i16* @atomic_i16, i16 1 monotonic
+ %0 = atomicrmw or ptr @atomic_i16, i16 1 monotonic
ret i16 %0
}
define i16 @test_xor_i16() {
@@ -3691,7 +3691,7 @@ define i16 @test_xor_i16() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw xor i16* @atomic_i16, i16 1 monotonic
+ %0 = atomicrmw xor ptr @atomic_i16, i16 1 monotonic
ret i16 %0
}
define i16 @test_max_i16() {
@@ -3912,7 +3912,7 @@ define i16 @test_max_i16() {
; CHECK-THUMB8BASE-NEXT: add sp, #20
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw max i16* @atomic_i16, i16 1 monotonic
+ %0 = atomicrmw max ptr @atomic_i16, i16 1 monotonic
ret i16 %0
}
define i16 @test_min_i16() {
@@ -4133,7 +4133,7 @@ define i16 @test_min_i16() {
; CHECK-THUMB8BASE-NEXT: add sp, #20
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw min i16* @atomic_i16, i16 1 monotonic
+ %0 = atomicrmw min ptr @atomic_i16, i16 1 monotonic
ret i16 %0
}
define i16 @test_umax_i16() {
@@ -4358,7 +4358,7 @@ define i16 @test_umax_i16() {
; CHECK-THUMB8BASE-NEXT: add sp, #24
; CHECK-THUMB8BASE-NEXT: pop {r4, r5, r7, pc}
entry:
- %0 = atomicrmw umax i16* @atomic_i16, i16 1 monotonic
+ %0 = atomicrmw umax ptr @atomic_i16, i16 1 monotonic
ret i16 %0
}
define i16 @test_umin_i16() {
@@ -4583,7 +4583,7 @@ define i16 @test_umin_i16() {
; CHECK-THUMB8BASE-NEXT: add sp, #24
; CHECK-THUMB8BASE-NEXT: pop {r4, r5, r7, pc}
entry:
- %0 = atomicrmw umin i16* @atomic_i16, i16 1 monotonic
+ %0 = atomicrmw umin ptr @atomic_i16, i16 1 monotonic
ret i16 %0
}
@@ -4774,7 +4774,7 @@ define i32 @test_xchg_i32() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw xchg i32* @atomic_i32, i32 1 monotonic
+ %0 = atomicrmw xchg ptr @atomic_i32, i32 1 monotonic
ret i32 %0
}
define i32 @test_add_i32() {
@@ -4963,7 +4963,7 @@ define i32 @test_add_i32() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw add i32* @atomic_i32, i32 1 monotonic
+ %0 = atomicrmw add ptr @atomic_i32, i32 1 monotonic
ret i32 %0
}
define i32 @test_sub_i32() {
@@ -5152,7 +5152,7 @@ define i32 @test_sub_i32() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw sub i32* @atomic_i32, i32 1 monotonic
+ %0 = atomicrmw sub ptr @atomic_i32, i32 1 monotonic
ret i32 %0
}
define i32 @test_and_i32() {
@@ -5343,7 +5343,7 @@ define i32 @test_and_i32() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw and i32* @atomic_i32, i32 1 monotonic
+ %0 = atomicrmw and ptr @atomic_i32, i32 1 monotonic
ret i32 %0
}
define i32 @test_nand_i32() {
@@ -5540,7 +5540,7 @@ define i32 @test_nand_i32() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw nand i32* @atomic_i32, i32 1 monotonic
+ %0 = atomicrmw nand ptr @atomic_i32, i32 1 monotonic
ret i32 %0
}
define i32 @test_or_i32() {
@@ -5731,7 +5731,7 @@ define i32 @test_or_i32() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw or i32* @atomic_i32, i32 1 monotonic
+ %0 = atomicrmw or ptr @atomic_i32, i32 1 monotonic
ret i32 %0
}
define i32 @test_xor_i32() {
@@ -5922,7 +5922,7 @@ define i32 @test_xor_i32() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw xor i32* @atomic_i32, i32 1 monotonic
+ %0 = atomicrmw xor ptr @atomic_i32, i32 1 monotonic
ret i32 %0
}
define i32 @test_max_i32() {
@@ -6131,7 +6131,7 @@ define i32 @test_max_i32() {
; CHECK-THUMB8BASE-NEXT: add sp, #20
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw max i32* @atomic_i32, i32 1 monotonic
+ %0 = atomicrmw max ptr @atomic_i32, i32 1 monotonic
ret i32 %0
}
define i32 @test_min_i32() {
@@ -6340,7 +6340,7 @@ define i32 @test_min_i32() {
; CHECK-THUMB8BASE-NEXT: add sp, #20
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw min i32* @atomic_i32, i32 1 monotonic
+ %0 = atomicrmw min ptr @atomic_i32, i32 1 monotonic
ret i32 %0
}
define i32 @test_umax_i32() {
@@ -6549,7 +6549,7 @@ define i32 @test_umax_i32() {
; CHECK-THUMB8BASE-NEXT: add sp, #20
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw umax i32* @atomic_i32, i32 1 monotonic
+ %0 = atomicrmw umax ptr @atomic_i32, i32 1 monotonic
ret i32 %0
}
define i32 @test_umin_i32() {
@@ -6758,7 +6758,7 @@ define i32 @test_umin_i32() {
; CHECK-THUMB8BASE-NEXT: add sp, #20
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw umin i32* @atomic_i32, i32 1 monotonic
+ %0 = atomicrmw umin ptr @atomic_i32, i32 1 monotonic
ret i32 %0
}
@@ -6969,7 +6969,7 @@ define i64 @test_xchg_i64() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r7, pc}
entry:
- %0 = atomicrmw xchg i64* @atomic_i64, i64 1 monotonic
+ %0 = atomicrmw xchg ptr @atomic_i64, i64 1 monotonic
ret i64 %0
}
define i64 @test_add_i64() {
@@ -7179,7 +7179,7 @@ define i64 @test_add_i64() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r7, pc}
entry:
- %0 = atomicrmw add i64* @atomic_i64, i64 1 monotonic
+ %0 = atomicrmw add ptr @atomic_i64, i64 1 monotonic
ret i64 %0
}
define i64 @test_sub_i64() {
@@ -7389,7 +7389,7 @@ define i64 @test_sub_i64() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r7, pc}
entry:
- %0 = atomicrmw sub i64* @atomic_i64, i64 1 monotonic
+ %0 = atomicrmw sub ptr @atomic_i64, i64 1 monotonic
ret i64 %0
}
define i64 @test_and_i64() {
@@ -7599,7 +7599,7 @@ define i64 @test_and_i64() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r7, pc}
entry:
- %0 = atomicrmw and i64* @atomic_i64, i64 1 monotonic
+ %0 = atomicrmw and ptr @atomic_i64, i64 1 monotonic
ret i64 %0
}
define i64 @test_nand_i64() {
@@ -7814,7 +7814,7 @@ define i64 @test_nand_i64() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r7, pc}
entry:
- %0 = atomicrmw nand i64* @atomic_i64, i64 1 monotonic
+ %0 = atomicrmw nand ptr @atomic_i64, i64 1 monotonic
ret i64 %0
}
define i64 @test_or_i64() {
@@ -8021,7 +8021,7 @@ define i64 @test_or_i64() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r7, pc}
entry:
- %0 = atomicrmw or i64* @atomic_i64, i64 1 monotonic
+ %0 = atomicrmw or ptr @atomic_i64, i64 1 monotonic
ret i64 %0
}
define i64 @test_xor_i64() {
@@ -8228,7 +8228,7 @@ define i64 @test_xor_i64() {
; CHECK-THUMB8BASE-NEXT: add sp, #8
; CHECK-THUMB8BASE-NEXT: pop {r7, pc}
entry:
- %0 = atomicrmw xor i64* @atomic_i64, i64 1 monotonic
+ %0 = atomicrmw xor ptr @atomic_i64, i64 1 monotonic
ret i64 %0
}
@@ -8533,7 +8533,7 @@ define i64 @test_max_i64() {
; CHECK-THUMB8BASE-NEXT: add sp, #72
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw max i64* @atomic_i64, i64 1 monotonic
+ %0 = atomicrmw max ptr @atomic_i64, i64 1 monotonic
ret i64 %0
}
define i64 @test_min_i64() {
@@ -8837,7 +8837,7 @@ define i64 @test_min_i64() {
; CHECK-THUMB8BASE-NEXT: add sp, #72
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw min i64* @atomic_i64, i64 1 monotonic
+ %0 = atomicrmw min ptr @atomic_i64, i64 1 monotonic
ret i64 %0
}
define i64 @test_umax_i64() {
@@ -9141,7 +9141,7 @@ define i64 @test_umax_i64() {
; CHECK-THUMB8BASE-NEXT: add sp, #72
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw umax i64* @atomic_i64, i64 1 monotonic
+ %0 = atomicrmw umax ptr @atomic_i64, i64 1 monotonic
ret i64 %0
}
define i64 @test_umin_i64() {
@@ -9445,6 +9445,6 @@ define i64 @test_umin_i64() {
; CHECK-THUMB8BASE-NEXT: add sp, #72
; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
entry:
- %0 = atomicrmw umin i64* @atomic_i64, i64 1 monotonic
+ %0 = atomicrmw umin ptr @atomic_i64, i64 1 monotonic
ret i64 %0
}
diff --git a/llvm/test/CodeGen/ARM/atomicrmw_minmax.ll b/llvm/test/CodeGen/ARM/atomicrmw_minmax.ll
index 68bf71486a239..2866b1a356782 100644
--- a/llvm/test/CodeGen/ARM/atomicrmw_minmax.ll
+++ b/llvm/test/CodeGen/ARM/atomicrmw_minmax.ll
@@ -1,21 +1,21 @@
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s
; CHECK-LABEL: max:
-define i32 @max(i8 %ctx, i32* %ptr, i32 %val)
+define i32 @max(i8 %ctx, ptr %ptr, i32 %val)
{
; CHECK: ldrex
; CHECK: cmp [[old:r[0-9]*]], [[val:r[0-9]*]]
; CHECK: movhi {{r[0-9]*}}, [[old]]
- %old = atomicrmw umax i32* %ptr, i32 %val monotonic
+ %old = atomicrmw umax ptr %ptr, i32 %val monotonic
ret i32 %old
}
; CHECK-LABEL: min:
-define i32 @min(i8 %ctx, i32* %ptr, i32 %val)
+define i32 @min(i8 %ctx, ptr %ptr, i32 %val)
{
; CHECK: ldrex
; CHECK: cmp [[old:r[0-9]*]], [[val:r[0-9]*]]
; CHECK: movls {{r[0-9]*}}, [[old]]
- %old = atomicrmw umin i32* %ptr, i32 %val monotonic
+ %old = atomicrmw umin ptr %ptr, i32 %val monotonic
ret i32 %old
}
diff --git a/llvm/test/CodeGen/ARM/available_externally.ll b/llvm/test/CodeGen/ARM/available_externally.ll
index 055074738e5c2..230653b7b17d5 100644
--- a/llvm/test/CodeGen/ARM/available_externally.ll
+++ b/llvm/test/CodeGen/ARM/available_externally.ll
@@ -5,8 +5,8 @@
@B = external hidden constant i32
define i32 @t1() {
- %tmp = load i32, i32* @A
- store i32 %tmp, i32* @B
+ %tmp = load i32, ptr @A
+ store i32 %tmp, ptr @B
ret i32 %tmp
}
diff --git a/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll
index 5c8350af98f5a..c13702a38e404 100644
--- a/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll
+++ b/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll
@@ -20,7 +20,7 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
; Avoid partial CPSR dependency via loop backedge.
; rdar://10357570
-define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind {
+define void @t2(ptr nocapture %ptr1, ptr %ptr2, i32 %c) nounwind {
entry:
; CHECK-LABEL: t2:
br label %while.body
@@ -29,22 +29,22 @@ while.body:
; CHECK: while.body
; CHECK: mul r{{[0-9]+}}
; CHECK-NOT: muls
- %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
- %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
- %0 = load i32, i32* %ptr1.addr.09, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 1
- %1 = load i32, i32* %arrayidx1, align 4
- %arrayidx3 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 2
- %2 = load i32, i32* %arrayidx3, align 4
- %arrayidx4 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 3
- %3 = load i32, i32* %arrayidx4, align 4
- %add.ptr = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 4
+ %ptr1.addr.09 = phi ptr [ %add.ptr, %while.body ], [ %ptr1, %entry ]
+ %ptr2.addr.08 = phi ptr [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
+ %0 = load i32, ptr %ptr1.addr.09, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 1
+ %1 = load i32, ptr %arrayidx1, align 4
+ %arrayidx3 = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 2
+ %2 = load i32, ptr %arrayidx3, align 4
+ %arrayidx4 = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 3
+ %3 = load i32, ptr %arrayidx4, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 4
%mul = mul i32 %1, %0
%mul5 = mul i32 %mul, %2
%mul6 = mul i32 %mul5, %3
- store i32 %mul6, i32* %ptr2.addr.08, align 4
- %incdec.ptr = getelementptr inbounds i32, i32* %ptr2.addr.08, i32 -1
- %tobool = icmp eq i32* %incdec.ptr, null
+ store i32 %mul6, ptr %ptr2.addr.08, align 4
+ %incdec.ptr = getelementptr inbounds i32, ptr %ptr2.addr.08, i32 -1
+ %tobool = icmp eq ptr %incdec.ptr, null
br i1 %tobool, label %while.end, label %while.body
while.end:
@@ -53,7 +53,7 @@ while.end:
; Allow partial CPSR dependency when code size is the priority.
; rdar://12878928
-define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize {
+define void @t3(ptr nocapture %ptr1, ptr %ptr2, i32 %c) nounwind minsize {
entry:
; CHECK-LABEL: t3:
br label %while.body
@@ -62,22 +62,22 @@ while.body:
; CHECK: while.body
; CHECK: muls r{{[0-9]+}}
; CHECK: muls
- %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
- %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
- %0 = load i32, i32* %ptr1.addr.09, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 1
- %1 = load i32, i32* %arrayidx1, align 4
- %arrayidx3 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 2
- %2 = load i32, i32* %arrayidx3, align 4
- %arrayidx4 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 3
- %3 = load i32, i32* %arrayidx4, align 4
- %add.ptr = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 4
+ %ptr1.addr.09 = phi ptr [ %add.ptr, %while.body ], [ %ptr1, %entry ]
+ %ptr2.addr.08 = phi ptr [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
+ %0 = load i32, ptr %ptr1.addr.09, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 1
+ %1 = load i32, ptr %arrayidx1, align 4
+ %arrayidx3 = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 2
+ %2 = load i32, ptr %arrayidx3, align 4
+ %arrayidx4 = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 3
+ %3 = load i32, ptr %arrayidx4, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 4
%mul = mul i32 %1, %0
%mul5 = mul i32 %mul, %2
%mul6 = mul i32 %mul5, %3
- store i32 %mul6, i32* %ptr2.addr.08, align 4
- %incdec.ptr = getelementptr inbounds i32, i32* %ptr2.addr.08, i32 -1
- %tobool = icmp eq i32* %incdec.ptr, null
+ store i32 %mul6, ptr %ptr2.addr.08, align 4
+ %incdec.ptr = getelementptr inbounds i32, ptr %ptr2.addr.08, i32 -1
+ %tobool = icmp eq ptr %incdec.ptr, null
br i1 %tobool, label %while.end, label %while.body
while.end:
@@ -86,29 +86,29 @@ while.end:
; Avoid producing tMOVi8 after a high-latency flag-setting operation.
; <rdar://problem/13468102>
-define void @t4(i32* nocapture %p, double* nocapture %q) {
+define void @t4(ptr nocapture %p, ptr nocapture %q) {
entry:
; CHECK: t4
; CHECK: vmrs APSR_nzcv, fpscr
; CHECK: if.then
; CHECK-NOT: movs
- %0 = load double, double* %q, align 4
+ %0 = load double, ptr %q, align 4
%cmp = fcmp olt double %0, 1.000000e+01
- %incdec.ptr1 = getelementptr inbounds i32, i32* %p, i32 1
+ %incdec.ptr1 = getelementptr inbounds i32, ptr %p, i32 1
br i1 %cmp, label %if.then, label %if.else
if.then:
- store i32 7, i32* %p, align 4
- %incdec.ptr2 = getelementptr inbounds i32, i32* %p, i32 2
- store i32 8, i32* %incdec.ptr1, align 4
- store i32 9, i32* %incdec.ptr2, align 4
+ store i32 7, ptr %p, align 4
+ %incdec.ptr2 = getelementptr inbounds i32, ptr %p, i32 2
+ store i32 8, ptr %incdec.ptr1, align 4
+ store i32 9, ptr %incdec.ptr2, align 4
br label %if.end
if.else:
- store i32 3, i32* %p, align 4
- %incdec.ptr5 = getelementptr inbounds i32, i32* %p, i32 3
- store i32 5, i32* %incdec.ptr1, align 4
- store i32 6, i32* %incdec.ptr5, align 4
+ store i32 3, ptr %p, align 4
+ %incdec.ptr5 = getelementptr inbounds i32, ptr %p, i32 3
+ store i32 5, ptr %incdec.ptr1, align 4
+ store i32 6, ptr %incdec.ptr5, align 4
br label %if.end
if.end:
diff --git a/llvm/test/CodeGen/ARM/bf16-intrinsics-ld-st.ll b/llvm/test/CodeGen/ARM/bf16-intrinsics-ld-st.ll
index 0f6a520c33027..cccbdd0435765 100644
--- a/llvm/test/CodeGen/ARM/bf16-intrinsics-ld-st.ll
+++ b/llvm/test/CodeGen/ARM/bf16-intrinsics-ld-st.ll
@@ -3,69 +3,67 @@
; FIXME: Remove fullfp16 once bfloat arguments and returns lowering stops
; depending on it.
-define arm_aapcs_vfpcc <4 x bfloat> @test_vld1_bf16(bfloat* nocapture readonly %ptr) {
+define arm_aapcs_vfpcc <4 x bfloat> @test_vld1_bf16(ptr nocapture readonly %ptr) {
; CHECK-LABEL: test_vld1_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d0}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to <4 x bfloat>*
- %1 = load <4 x bfloat>, <4 x bfloat>* %0, align 2
- ret <4 x bfloat> %1
+ %0 = load <4 x bfloat>, ptr %ptr, align 2
+ ret <4 x bfloat> %0
}
-define arm_aapcs_vfpcc <8 x bfloat> @test_vld1q_bf16(bfloat* nocapture readonly %ptr) {
+define arm_aapcs_vfpcc <8 x bfloat> @test_vld1q_bf16(ptr nocapture readonly %ptr) {
; CHECK-LABEL: test_vld1q_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d0, d1}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to <8 x bfloat>*
- %1 = load <8 x bfloat>, <8 x bfloat>* %0, align 2
- ret <8 x bfloat> %1
+ %0 = load <8 x bfloat>, ptr %ptr, align 2
+ ret <8 x bfloat> %0
}
-define arm_aapcs_vfpcc <4 x bfloat> @test_vld1_lane_bf16(bfloat* nocapture readonly %ptr, <4 x bfloat> %src) {
+define arm_aapcs_vfpcc <4 x bfloat> @test_vld1_lane_bf16(ptr nocapture readonly %ptr, <4 x bfloat> %src) {
; CHECK-LABEL: test_vld1_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d0[0]}, [r0:16]
; CHECK-NEXT: bx lr
entry:
- %0 = load bfloat, bfloat* %ptr, align 2
+ %0 = load bfloat, ptr %ptr, align 2
%vld1_lane = insertelement <4 x bfloat> %src, bfloat %0, i32 0
ret <4 x bfloat> %vld1_lane
}
-define arm_aapcs_vfpcc <8 x bfloat> @test_vld1q_lane_bf16(bfloat* nocapture readonly %ptr, <8 x bfloat> %src) {
+define arm_aapcs_vfpcc <8 x bfloat> @test_vld1q_lane_bf16(ptr nocapture readonly %ptr, <8 x bfloat> %src) {
; CHECK-LABEL: test_vld1q_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d1[3]}, [r0:16]
; CHECK-NEXT: bx lr
entry:
- %0 = load bfloat, bfloat* %ptr, align 2
+ %0 = load bfloat, ptr %ptr, align 2
%vld1_lane = insertelement <8 x bfloat> %src, bfloat %0, i32 7
ret <8 x bfloat> %vld1_lane
}
-define arm_aapcs_vfpcc <4 x bfloat> @test_vld1_dup_bf16(bfloat* nocapture readonly %ptr) {
+define arm_aapcs_vfpcc <4 x bfloat> @test_vld1_dup_bf16(ptr nocapture readonly %ptr) {
; CHECK-LABEL: test_vld1_dup_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d0[]}, [r0:16]
; CHECK-NEXT: bx lr
entry:
- %0 = load bfloat, bfloat* %ptr, align 2
+ %0 = load bfloat, ptr %ptr, align 2
%1 = insertelement <4 x bfloat> undef, bfloat %0, i32 0
%lane = shufflevector <4 x bfloat> %1, <4 x bfloat> undef, <4 x i32> zeroinitializer
ret <4 x bfloat> %lane
}
-define arm_aapcs_vfpcc [2 x <2 x i32>] @test_vld1_bf16_x2(bfloat* %ptr) {
+define arm_aapcs_vfpcc [2 x <2 x i32>] @test_vld1_bf16_x2(ptr %ptr) {
; CHECK-LABEL: test_vld1_bf16_x2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d0, d1}, [r0:64]
; CHECK-NEXT: bx lr
entry:
- %vld1xN = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x2.v4bf16.p0bf16(bfloat* %ptr)
+ %vld1xN = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x2.v4bf16.p0(ptr %ptr)
%vld1xN.fca.0.extract = extractvalue { <4 x bfloat>, <4 x bfloat> } %vld1xN, 0
%vld1xN.fca.1.extract = extractvalue { <4 x bfloat>, <4 x bfloat> } %vld1xN, 1
%0 = bitcast <4 x bfloat> %vld1xN.fca.0.extract to <2 x i32>
@@ -75,13 +73,13 @@ entry:
ret [2 x <2 x i32>] %.fca.1.insert
}
-define arm_aapcs_vfpcc [2 x <4 x i32>] @test_vld1q_bf16_x2(bfloat* %ptr) {
+define arm_aapcs_vfpcc [2 x <4 x i32>] @test_vld1q_bf16_x2(ptr %ptr) {
; CHECK-LABEL: test_vld1q_bf16_x2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d0, d1, d2, d3}, [r0:256]
; CHECK-NEXT: bx lr
entry:
- %vld1xN = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x2.v8bf16.p0bf16(bfloat* %ptr)
+ %vld1xN = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x2.v8bf16.p0(ptr %ptr)
%vld1xN.fca.0.extract = extractvalue { <8 x bfloat>, <8 x bfloat> } %vld1xN, 0
%vld1xN.fca.1.extract = extractvalue { <8 x bfloat>, <8 x bfloat> } %vld1xN, 1
%0 = bitcast <8 x bfloat> %vld1xN.fca.0.extract to <4 x i32>
@@ -91,13 +89,13 @@ entry:
ret [2 x <4 x i32>] %.fca.1.insert
}
-define arm_aapcs_vfpcc [3 x <2 x i32>] @test_vld1_bf16_x3(bfloat* %ptr) {
+define arm_aapcs_vfpcc [3 x <2 x i32>] @test_vld1_bf16_x3(ptr %ptr) {
; CHECK-LABEL: test_vld1_bf16_x3:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d0, d1, d2}, [r0:64]
; CHECK-NEXT: bx lr
entry:
- %vld1xN = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x3.v4bf16.p0bf16(bfloat* %ptr)
+ %vld1xN = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x3.v4bf16.p0(ptr %ptr)
%vld1xN.fca.0.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld1xN, 0
%vld1xN.fca.1.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld1xN, 1
%vld1xN.fca.2.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld1xN, 2
@@ -110,14 +108,14 @@ entry:
ret [3 x <2 x i32>] %.fca.2.insert
}
-define arm_aapcs_vfpcc [3 x <4 x i32>] @test_vld1q_bf16_x3(bfloat* %ptr) {
+define arm_aapcs_vfpcc [3 x <4 x i32>] @test_vld1q_bf16_x3(ptr %ptr) {
; CHECK-LABEL: test_vld1q_bf16_x3:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d0, d1, d2}, [r0:64]!
; CHECK-NEXT: vld1.16 {d3, d4, d5}, [r0:64]
; CHECK-NEXT: bx lr
entry:
- %vld1xN = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x3.v8bf16.p0bf16(bfloat* %ptr)
+ %vld1xN = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x3.v8bf16.p0(ptr %ptr)
%vld1xN.fca.0.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld1xN, 0
%vld1xN.fca.1.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld1xN, 1
%vld1xN.fca.2.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld1xN, 2
@@ -130,13 +128,13 @@ entry:
ret [3 x <4 x i32>] %.fca.2.insert
}
-define arm_aapcs_vfpcc [4 x <2 x i32>] @test_vld1_bf16_x4(bfloat* %ptr) {
+define arm_aapcs_vfpcc [4 x <2 x i32>] @test_vld1_bf16_x4(ptr %ptr) {
; CHECK-LABEL: test_vld1_bf16_x4:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d0, d1, d2, d3}, [r0:256]
; CHECK-NEXT: bx lr
entry:
- %vld1xN = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x4.v4bf16.p0bf16(bfloat* %ptr)
+ %vld1xN = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x4.v4bf16.p0(ptr %ptr)
%vld1xN.fca.0.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld1xN, 0
%vld1xN.fca.1.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld1xN, 1
%vld1xN.fca.2.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld1xN, 2
@@ -152,14 +150,14 @@ entry:
ret [4 x <2 x i32>] %.fca.3.insert
}
-define arm_aapcs_vfpcc [4 x <4 x i32>] @test_vld1q_bf16_x4(bfloat* %ptr) {
+define arm_aapcs_vfpcc [4 x <4 x i32>] @test_vld1q_bf16_x4(ptr %ptr) {
; CHECK-LABEL: test_vld1q_bf16_x4:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d0, d1, d2, d3}, [r0:256]!
; CHECK-NEXT: vld1.16 {d4, d5, d6, d7}, [r0:256]
; CHECK-NEXT: bx lr
entry:
- %vld1xN = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x4.v8bf16.p0bf16(bfloat* %ptr)
+ %vld1xN = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x4.v8bf16.p0(ptr %ptr)
%vld1xN.fca.0.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld1xN, 0
%vld1xN.fca.1.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld1xN, 1
%vld1xN.fca.2.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld1xN, 2
@@ -175,53 +173,51 @@ entry:
ret [4 x <4 x i32>] %.fca.3.insert
}
-define arm_aapcs_vfpcc <8 x bfloat> @test_vld1q_dup_bf16(bfloat* nocapture readonly %ptr) {
+define arm_aapcs_vfpcc <8 x bfloat> @test_vld1q_dup_bf16(ptr nocapture readonly %ptr) {
; CHECK-LABEL: test_vld1q_dup_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d0[], d1[]}, [r0:16]
; CHECK-NEXT: bx lr
entry:
- %0 = load bfloat, bfloat* %ptr, align 2
+ %0 = load bfloat, ptr %ptr, align 2
%1 = insertelement <8 x bfloat> undef, bfloat %0, i32 0
%lane = shufflevector <8 x bfloat> %1, <8 x bfloat> undef, <8 x i32> zeroinitializer
ret <8 x bfloat> %lane
}
-define arm_aapcs_vfpcc [2 x <2 x i32>] @test_vld2_bf16(bfloat* %ptr) {
+define arm_aapcs_vfpcc [2 x <2 x i32>] @test_vld2_bf16(ptr %ptr) {
; CHECK-LABEL: test_vld2_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld2.16 {d0, d1}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to i8*
- %vld2_v = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2.v4bf16.p0i8(i8* %0, i32 2)
+ %vld2_v = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2.v4bf16.p0(ptr %ptr, i32 2)
%vld2_v.fca.0.extract = extractvalue { <4 x bfloat>, <4 x bfloat> } %vld2_v, 0
%vld2_v.fca.1.extract = extractvalue { <4 x bfloat>, <4 x bfloat> } %vld2_v, 1
- %1 = bitcast <4 x bfloat> %vld2_v.fca.0.extract to <2 x i32>
- %2 = bitcast <4 x bfloat> %vld2_v.fca.1.extract to <2 x i32>
- %.fca.0.insert = insertvalue [2 x <2 x i32>] undef, <2 x i32> %1, 0
- %.fca.1.insert = insertvalue [2 x <2 x i32>] %.fca.0.insert, <2 x i32> %2, 1
+ %0 = bitcast <4 x bfloat> %vld2_v.fca.0.extract to <2 x i32>
+ %1 = bitcast <4 x bfloat> %vld2_v.fca.1.extract to <2 x i32>
+ %.fca.0.insert = insertvalue [2 x <2 x i32>] undef, <2 x i32> %0, 0
+ %.fca.1.insert = insertvalue [2 x <2 x i32>] %.fca.0.insert, <2 x i32> %1, 1
ret [2 x <2 x i32>] %.fca.1.insert
}
-define arm_aapcs_vfpcc [2 x <4 x i32>] @test_vld2q_bf16(bfloat* %ptr) {
+define arm_aapcs_vfpcc [2 x <4 x i32>] @test_vld2q_bf16(ptr %ptr) {
; CHECK-LABEL: test_vld2q_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld2.16 {d0, d1, d2, d3}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to i8*
- %vld2q_v = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2.v8bf16.p0i8(i8* %0, i32 2)
+ %vld2q_v = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2.v8bf16.p0(ptr %ptr, i32 2)
%vld2q_v.fca.0.extract = extractvalue { <8 x bfloat>, <8 x bfloat> } %vld2q_v, 0
%vld2q_v.fca.1.extract = extractvalue { <8 x bfloat>, <8 x bfloat> } %vld2q_v, 1
- %1 = bitcast <8 x bfloat> %vld2q_v.fca.0.extract to <4 x i32>
- %2 = bitcast <8 x bfloat> %vld2q_v.fca.1.extract to <4 x i32>
- %.fca.0.insert = insertvalue [2 x <4 x i32>] undef, <4 x i32> %1, 0
- %.fca.1.insert = insertvalue [2 x <4 x i32>] %.fca.0.insert, <4 x i32> %2, 1
+ %0 = bitcast <8 x bfloat> %vld2q_v.fca.0.extract to <4 x i32>
+ %1 = bitcast <8 x bfloat> %vld2q_v.fca.1.extract to <4 x i32>
+ %.fca.0.insert = insertvalue [2 x <4 x i32>] undef, <4 x i32> %0, 0
+ %.fca.1.insert = insertvalue [2 x <4 x i32>] %.fca.0.insert, <4 x i32> %1, 1
ret [2 x <4 x i32>] %.fca.1.insert
}
-define arm_aapcs_vfpcc [2 x <2 x i32>] @test_vld2_lane_bf16(bfloat* %ptr, [2 x <2 x i32>] %src.coerce) {
+define arm_aapcs_vfpcc [2 x <2 x i32>] @test_vld2_lane_bf16(ptr %ptr, [2 x <2 x i32>] %src.coerce) {
; CHECK-LABEL: test_vld2_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
@@ -233,18 +229,17 @@ entry:
%src.coerce.fca.1.extract = extractvalue [2 x <2 x i32>] %src.coerce, 1
%0 = bitcast <2 x i32> %src.coerce.fca.0.extract to <4 x bfloat>
%1 = bitcast <2 x i32> %src.coerce.fca.1.extract to <4 x bfloat>
- %2 = bitcast bfloat* %ptr to i8*
- %vld2_lane_v = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2lane.v4bf16.p0i8(i8* %2, <4 x bfloat> %0, <4 x bfloat> %1, i32 1, i32 2)
+ %vld2_lane_v = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2lane.v4bf16.p0(ptr %ptr, <4 x bfloat> %0, <4 x bfloat> %1, i32 1, i32 2)
%vld2_lane_v.fca.0.extract = extractvalue { <4 x bfloat>, <4 x bfloat> } %vld2_lane_v, 0
%vld2_lane_v.fca.1.extract = extractvalue { <4 x bfloat>, <4 x bfloat> } %vld2_lane_v, 1
- %3 = bitcast <4 x bfloat> %vld2_lane_v.fca.0.extract to <2 x i32>
- %4 = bitcast <4 x bfloat> %vld2_lane_v.fca.1.extract to <2 x i32>
- %.fca.0.insert = insertvalue [2 x <2 x i32>] undef, <2 x i32> %3, 0
- %.fca.1.insert = insertvalue [2 x <2 x i32>] %.fca.0.insert, <2 x i32> %4, 1
+ %2 = bitcast <4 x bfloat> %vld2_lane_v.fca.0.extract to <2 x i32>
+ %3 = bitcast <4 x bfloat> %vld2_lane_v.fca.1.extract to <2 x i32>
+ %.fca.0.insert = insertvalue [2 x <2 x i32>] undef, <2 x i32> %2, 0
+ %.fca.1.insert = insertvalue [2 x <2 x i32>] %.fca.0.insert, <2 x i32> %3, 1
ret [2 x <2 x i32>] %.fca.1.insert
}
-define arm_aapcs_vfpcc [2 x <4 x i32>] @test_vld2q_lane_bf16(bfloat* %ptr, [2 x <4 x i32>] %src.coerce) {
+define arm_aapcs_vfpcc [2 x <4 x i32>] @test_vld2q_lane_bf16(ptr %ptr, [2 x <4 x i32>] %src.coerce) {
; CHECK-LABEL: test_vld2q_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
@@ -256,59 +251,56 @@ entry:
%src.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %src.coerce, 1
%0 = bitcast <4 x i32> %src.coerce.fca.0.extract to <8 x bfloat>
%1 = bitcast <4 x i32> %src.coerce.fca.1.extract to <8 x bfloat>
- %2 = bitcast bfloat* %ptr to i8*
- %vld2q_lane_v = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2lane.v8bf16.p0i8(i8* %2, <8 x bfloat> %0, <8 x bfloat> %1, i32 7, i32 2)
+ %vld2q_lane_v = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2lane.v8bf16.p0(ptr %ptr, <8 x bfloat> %0, <8 x bfloat> %1, i32 7, i32 2)
%vld2q_lane_v.fca.0.extract = extractvalue { <8 x bfloat>, <8 x bfloat> } %vld2q_lane_v, 0
%vld2q_lane_v.fca.1.extract = extractvalue { <8 x bfloat>, <8 x bfloat> } %vld2q_lane_v, 1
- %3 = bitcast <8 x bfloat> %vld2q_lane_v.fca.0.extract to <4 x i32>
- %4 = bitcast <8 x bfloat> %vld2q_lane_v.fca.1.extract to <4 x i32>
- %.fca.0.insert = insertvalue [2 x <4 x i32>] undef, <4 x i32> %3, 0
- %.fca.1.insert = insertvalue [2 x <4 x i32>] %.fca.0.insert, <4 x i32> %4, 1
+ %2 = bitcast <8 x bfloat> %vld2q_lane_v.fca.0.extract to <4 x i32>
+ %3 = bitcast <8 x bfloat> %vld2q_lane_v.fca.1.extract to <4 x i32>
+ %.fca.0.insert = insertvalue [2 x <4 x i32>] undef, <4 x i32> %2, 0
+ %.fca.1.insert = insertvalue [2 x <4 x i32>] %.fca.0.insert, <4 x i32> %3, 1
ret [2 x <4 x i32>] %.fca.1.insert
}
-define arm_aapcs_vfpcc [3 x <2 x i32>] @test_vld3_bf16(bfloat* %ptr) {
+define arm_aapcs_vfpcc [3 x <2 x i32>] @test_vld3_bf16(ptr %ptr) {
; CHECK-LABEL: test_vld3_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld3.16 {d0, d1, d2}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to i8*
- %vld3_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3.v4bf16.p0i8(i8* %0, i32 2)
+ %vld3_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3.v4bf16.p0(ptr %ptr, i32 2)
%vld3_v.fca.0.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld3_v, 0
%vld3_v.fca.1.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld3_v, 1
%vld3_v.fca.2.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld3_v, 2
- %1 = bitcast <4 x bfloat> %vld3_v.fca.0.extract to <2 x i32>
- %2 = bitcast <4 x bfloat> %vld3_v.fca.1.extract to <2 x i32>
- %3 = bitcast <4 x bfloat> %vld3_v.fca.2.extract to <2 x i32>
- %.fca.0.insert = insertvalue [3 x <2 x i32>] undef, <2 x i32> %1, 0
- %.fca.1.insert = insertvalue [3 x <2 x i32>] %.fca.0.insert, <2 x i32> %2, 1
- %.fca.2.insert = insertvalue [3 x <2 x i32>] %.fca.1.insert, <2 x i32> %3, 2
+ %0 = bitcast <4 x bfloat> %vld3_v.fca.0.extract to <2 x i32>
+ %1 = bitcast <4 x bfloat> %vld3_v.fca.1.extract to <2 x i32>
+ %2 = bitcast <4 x bfloat> %vld3_v.fca.2.extract to <2 x i32>
+ %.fca.0.insert = insertvalue [3 x <2 x i32>] undef, <2 x i32> %0, 0
+ %.fca.1.insert = insertvalue [3 x <2 x i32>] %.fca.0.insert, <2 x i32> %1, 1
+ %.fca.2.insert = insertvalue [3 x <2 x i32>] %.fca.1.insert, <2 x i32> %2, 2
ret [3 x <2 x i32>] %.fca.2.insert
}
-define arm_aapcs_vfpcc [3 x <4 x i32>] @test_vld3q_bf16(bfloat* %ptr) {
+define arm_aapcs_vfpcc [3 x <4 x i32>] @test_vld3q_bf16(ptr %ptr) {
; CHECK-LABEL: test_vld3q_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld3.16 {d0, d2, d4}, [r0]!
; CHECK-NEXT: vld3.16 {d1, d3, d5}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to i8*
- %vld3q_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3.v8bf16.p0i8(i8* %0, i32 2)
+ %vld3q_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3.v8bf16.p0(ptr %ptr, i32 2)
%vld3q_v.fca.0.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld3q_v, 0
%vld3q_v.fca.1.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld3q_v, 1
%vld3q_v.fca.2.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld3q_v, 2
- %1 = bitcast <8 x bfloat> %vld3q_v.fca.0.extract to <4 x i32>
- %2 = bitcast <8 x bfloat> %vld3q_v.fca.1.extract to <4 x i32>
- %3 = bitcast <8 x bfloat> %vld3q_v.fca.2.extract to <4 x i32>
- %.fca.0.insert = insertvalue [3 x <4 x i32>] undef, <4 x i32> %1, 0
- %.fca.1.insert = insertvalue [3 x <4 x i32>] %.fca.0.insert, <4 x i32> %2, 1
- %.fca.2.insert = insertvalue [3 x <4 x i32>] %.fca.1.insert, <4 x i32> %3, 2
+ %0 = bitcast <8 x bfloat> %vld3q_v.fca.0.extract to <4 x i32>
+ %1 = bitcast <8 x bfloat> %vld3q_v.fca.1.extract to <4 x i32>
+ %2 = bitcast <8 x bfloat> %vld3q_v.fca.2.extract to <4 x i32>
+ %.fca.0.insert = insertvalue [3 x <4 x i32>] undef, <4 x i32> %0, 0
+ %.fca.1.insert = insertvalue [3 x <4 x i32>] %.fca.0.insert, <4 x i32> %1, 1
+ %.fca.2.insert = insertvalue [3 x <4 x i32>] %.fca.1.insert, <4 x i32> %2, 2
ret [3 x <4 x i32>] %.fca.2.insert
}
-define arm_aapcs_vfpcc [3 x <2 x i32>] @test_vld3_lane_bf16(bfloat* %ptr, [3 x <2 x i32>] %src.coerce) {
+define arm_aapcs_vfpcc [3 x <2 x i32>] @test_vld3_lane_bf16(ptr %ptr, [3 x <2 x i32>] %src.coerce) {
; CHECK-LABEL: test_vld3_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
@@ -323,21 +315,20 @@ entry:
%0 = bitcast <2 x i32> %src.coerce.fca.0.extract to <4 x bfloat>
%1 = bitcast <2 x i32> %src.coerce.fca.1.extract to <4 x bfloat>
%2 = bitcast <2 x i32> %src.coerce.fca.2.extract to <4 x bfloat>
- %3 = bitcast bfloat* %ptr to i8*
- %vld3_lane_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3lane.v4bf16.p0i8(i8* %3, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, i32 1, i32 2)
+ %vld3_lane_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3lane.v4bf16.p0(ptr %ptr, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, i32 1, i32 2)
%vld3_lane_v.fca.0.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld3_lane_v, 0
%vld3_lane_v.fca.1.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld3_lane_v, 1
%vld3_lane_v.fca.2.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld3_lane_v, 2
- %4 = bitcast <4 x bfloat> %vld3_lane_v.fca.0.extract to <2 x i32>
- %5 = bitcast <4 x bfloat> %vld3_lane_v.fca.1.extract to <2 x i32>
- %6 = bitcast <4 x bfloat> %vld3_lane_v.fca.2.extract to <2 x i32>
- %.fca.0.insert = insertvalue [3 x <2 x i32>] undef, <2 x i32> %4, 0
- %.fca.1.insert = insertvalue [3 x <2 x i32>] %.fca.0.insert, <2 x i32> %5, 1
- %.fca.2.insert = insertvalue [3 x <2 x i32>] %.fca.1.insert, <2 x i32> %6, 2
+ %3 = bitcast <4 x bfloat> %vld3_lane_v.fca.0.extract to <2 x i32>
+ %4 = bitcast <4 x bfloat> %vld3_lane_v.fca.1.extract to <2 x i32>
+ %5 = bitcast <4 x bfloat> %vld3_lane_v.fca.2.extract to <2 x i32>
+ %.fca.0.insert = insertvalue [3 x <2 x i32>] undef, <2 x i32> %3, 0
+ %.fca.1.insert = insertvalue [3 x <2 x i32>] %.fca.0.insert, <2 x i32> %4, 1
+ %.fca.2.insert = insertvalue [3 x <2 x i32>] %.fca.1.insert, <2 x i32> %5, 2
ret [3 x <2 x i32>] %.fca.2.insert
}
-define arm_aapcs_vfpcc [3 x <4 x i32>] @test_vld3q_lane_bf16(bfloat* %ptr, [3 x <4 x i32>] %src.coerce) {
+define arm_aapcs_vfpcc [3 x <4 x i32>] @test_vld3q_lane_bf16(ptr %ptr, [3 x <4 x i32>] %src.coerce) {
; CHECK-LABEL: test_vld3q_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
@@ -352,68 +343,65 @@ entry:
%0 = bitcast <4 x i32> %src.coerce.fca.0.extract to <8 x bfloat>
%1 = bitcast <4 x i32> %src.coerce.fca.1.extract to <8 x bfloat>
%2 = bitcast <4 x i32> %src.coerce.fca.2.extract to <8 x bfloat>
- %3 = bitcast bfloat* %ptr to i8*
- %vld3q_lane_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3lane.v8bf16.p0i8(i8* %3, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, i32 7, i32 2)
+ %vld3q_lane_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3lane.v8bf16.p0(ptr %ptr, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, i32 7, i32 2)
%vld3q_lane_v.fca.0.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld3q_lane_v, 0
%vld3q_lane_v.fca.1.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld3q_lane_v, 1
%vld3q_lane_v.fca.2.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld3q_lane_v, 2
- %4 = bitcast <8 x bfloat> %vld3q_lane_v.fca.0.extract to <4 x i32>
- %5 = bitcast <8 x bfloat> %vld3q_lane_v.fca.1.extract to <4 x i32>
- %6 = bitcast <8 x bfloat> %vld3q_lane_v.fca.2.extract to <4 x i32>
- %.fca.0.insert = insertvalue [3 x <4 x i32>] undef, <4 x i32> %4, 0
- %.fca.1.insert = insertvalue [3 x <4 x i32>] %.fca.0.insert, <4 x i32> %5, 1
- %.fca.2.insert = insertvalue [3 x <4 x i32>] %.fca.1.insert, <4 x i32> %6, 2
+ %3 = bitcast <8 x bfloat> %vld3q_lane_v.fca.0.extract to <4 x i32>
+ %4 = bitcast <8 x bfloat> %vld3q_lane_v.fca.1.extract to <4 x i32>
+ %5 = bitcast <8 x bfloat> %vld3q_lane_v.fca.2.extract to <4 x i32>
+ %.fca.0.insert = insertvalue [3 x <4 x i32>] undef, <4 x i32> %3, 0
+ %.fca.1.insert = insertvalue [3 x <4 x i32>] %.fca.0.insert, <4 x i32> %4, 1
+ %.fca.2.insert = insertvalue [3 x <4 x i32>] %.fca.1.insert, <4 x i32> %5, 2
ret [3 x <4 x i32>] %.fca.2.insert
}
-define arm_aapcs_vfpcc [4 x <2 x i32>] @test_vld4_bf16(bfloat* %ptr) {
+define arm_aapcs_vfpcc [4 x <2 x i32>] @test_vld4_bf16(ptr %ptr) {
; CHECK-LABEL: test_vld4_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld4.16 {d0, d1, d2, d3}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to i8*
- %vld4_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4.v4bf16.p0i8(i8* %0, i32 2)
+ %vld4_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4.v4bf16.p0(ptr %ptr, i32 2)
%vld4_v.fca.0.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld4_v, 0
%vld4_v.fca.1.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld4_v, 1
%vld4_v.fca.2.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld4_v, 2
%vld4_v.fca.3.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld4_v, 3
- %1 = bitcast <4 x bfloat> %vld4_v.fca.0.extract to <2 x i32>
- %2 = bitcast <4 x bfloat> %vld4_v.fca.1.extract to <2 x i32>
- %3 = bitcast <4 x bfloat> %vld4_v.fca.2.extract to <2 x i32>
- %4 = bitcast <4 x bfloat> %vld4_v.fca.3.extract to <2 x i32>
- %.fca.0.insert = insertvalue [4 x <2 x i32>] undef, <2 x i32> %1, 0
- %.fca.1.insert = insertvalue [4 x <2 x i32>] %.fca.0.insert, <2 x i32> %2, 1
- %.fca.2.insert = insertvalue [4 x <2 x i32>] %.fca.1.insert, <2 x i32> %3, 2
- %.fca.3.insert = insertvalue [4 x <2 x i32>] %.fca.2.insert, <2 x i32> %4, 3
+ %0 = bitcast <4 x bfloat> %vld4_v.fca.0.extract to <2 x i32>
+ %1 = bitcast <4 x bfloat> %vld4_v.fca.1.extract to <2 x i32>
+ %2 = bitcast <4 x bfloat> %vld4_v.fca.2.extract to <2 x i32>
+ %3 = bitcast <4 x bfloat> %vld4_v.fca.3.extract to <2 x i32>
+ %.fca.0.insert = insertvalue [4 x <2 x i32>] undef, <2 x i32> %0, 0
+ %.fca.1.insert = insertvalue [4 x <2 x i32>] %.fca.0.insert, <2 x i32> %1, 1
+ %.fca.2.insert = insertvalue [4 x <2 x i32>] %.fca.1.insert, <2 x i32> %2, 2
+ %.fca.3.insert = insertvalue [4 x <2 x i32>] %.fca.2.insert, <2 x i32> %3, 3
ret [4 x <2 x i32>] %.fca.3.insert
}
-define arm_aapcs_vfpcc [4 x <4 x i32>] @test_vld4q_bf16(bfloat* %ptr) {
+define arm_aapcs_vfpcc [4 x <4 x i32>] @test_vld4q_bf16(ptr %ptr) {
; CHECK-LABEL: test_vld4q_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld4.16 {d0, d2, d4, d6}, [r0]!
; CHECK-NEXT: vld4.16 {d1, d3, d5, d7}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to i8*
- %vld4q_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4.v8bf16.p0i8(i8* %0, i32 2)
+ %vld4q_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4.v8bf16.p0(ptr %ptr, i32 2)
%vld4q_v.fca.0.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld4q_v, 0
%vld4q_v.fca.1.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld4q_v, 1
%vld4q_v.fca.2.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld4q_v, 2
%vld4q_v.fca.3.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld4q_v, 3
- %1 = bitcast <8 x bfloat> %vld4q_v.fca.0.extract to <4 x i32>
- %2 = bitcast <8 x bfloat> %vld4q_v.fca.1.extract to <4 x i32>
- %3 = bitcast <8 x bfloat> %vld4q_v.fca.2.extract to <4 x i32>
- %4 = bitcast <8 x bfloat> %vld4q_v.fca.3.extract to <4 x i32>
- %.fca.0.insert = insertvalue [4 x <4 x i32>] undef, <4 x i32> %1, 0
- %.fca.1.insert = insertvalue [4 x <4 x i32>] %.fca.0.insert, <4 x i32> %2, 1
- %.fca.2.insert = insertvalue [4 x <4 x i32>] %.fca.1.insert, <4 x i32> %3, 2
- %.fca.3.insert = insertvalue [4 x <4 x i32>] %.fca.2.insert, <4 x i32> %4, 3
+ %0 = bitcast <8 x bfloat> %vld4q_v.fca.0.extract to <4 x i32>
+ %1 = bitcast <8 x bfloat> %vld4q_v.fca.1.extract to <4 x i32>
+ %2 = bitcast <8 x bfloat> %vld4q_v.fca.2.extract to <4 x i32>
+ %3 = bitcast <8 x bfloat> %vld4q_v.fca.3.extract to <4 x i32>
+ %.fca.0.insert = insertvalue [4 x <4 x i32>] undef, <4 x i32> %0, 0
+ %.fca.1.insert = insertvalue [4 x <4 x i32>] %.fca.0.insert, <4 x i32> %1, 1
+ %.fca.2.insert = insertvalue [4 x <4 x i32>] %.fca.1.insert, <4 x i32> %2, 2
+ %.fca.3.insert = insertvalue [4 x <4 x i32>] %.fca.2.insert, <4 x i32> %3, 3
ret [4 x <4 x i32>] %.fca.3.insert
}
-define arm_aapcs_vfpcc [4 x <2 x i32>] @test_vld4_lane_bf16(bfloat* %ptr, [4 x <2 x i32>] %src.coerce) {
+define arm_aapcs_vfpcc [4 x <2 x i32>] @test_vld4_lane_bf16(ptr %ptr, [4 x <2 x i32>] %src.coerce) {
; CHECK-LABEL: test_vld4_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q0_q1 def $q0_q1
@@ -431,24 +419,23 @@ entry:
%1 = bitcast <2 x i32> %src.coerce.fca.1.extract to <4 x bfloat>
%2 = bitcast <2 x i32> %src.coerce.fca.2.extract to <4 x bfloat>
%3 = bitcast <2 x i32> %src.coerce.fca.3.extract to <4 x bfloat>
- %4 = bitcast bfloat* %ptr to i8*
- %vld4_lane_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4lane.v4bf16.p0i8(i8* %4, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, <4 x bfloat> %3, i32 1, i32 2)
+ %vld4_lane_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4lane.v4bf16.p0(ptr %ptr, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, <4 x bfloat> %3, i32 1, i32 2)
%vld4_lane_v.fca.0.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld4_lane_v, 0
%vld4_lane_v.fca.1.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld4_lane_v, 1
%vld4_lane_v.fca.2.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld4_lane_v, 2
%vld4_lane_v.fca.3.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld4_lane_v, 3
- %5 = bitcast <4 x bfloat> %vld4_lane_v.fca.0.extract to <2 x i32>
- %6 = bitcast <4 x bfloat> %vld4_lane_v.fca.1.extract to <2 x i32>
- %7 = bitcast <4 x bfloat> %vld4_lane_v.fca.2.extract to <2 x i32>
- %8 = bitcast <4 x bfloat> %vld4_lane_v.fca.3.extract to <2 x i32>
- %.fca.0.insert = insertvalue [4 x <2 x i32>] undef, <2 x i32> %5, 0
- %.fca.1.insert = insertvalue [4 x <2 x i32>] %.fca.0.insert, <2 x i32> %6, 1
- %.fca.2.insert = insertvalue [4 x <2 x i32>] %.fca.1.insert, <2 x i32> %7, 2
- %.fca.3.insert = insertvalue [4 x <2 x i32>] %.fca.2.insert, <2 x i32> %8, 3
+ %4 = bitcast <4 x bfloat> %vld4_lane_v.fca.0.extract to <2 x i32>
+ %5 = bitcast <4 x bfloat> %vld4_lane_v.fca.1.extract to <2 x i32>
+ %6 = bitcast <4 x bfloat> %vld4_lane_v.fca.2.extract to <2 x i32>
+ %7 = bitcast <4 x bfloat> %vld4_lane_v.fca.3.extract to <2 x i32>
+ %.fca.0.insert = insertvalue [4 x <2 x i32>] undef, <2 x i32> %4, 0
+ %.fca.1.insert = insertvalue [4 x <2 x i32>] %.fca.0.insert, <2 x i32> %5, 1
+ %.fca.2.insert = insertvalue [4 x <2 x i32>] %.fca.1.insert, <2 x i32> %6, 2
+ %.fca.3.insert = insertvalue [4 x <2 x i32>] %.fca.2.insert, <2 x i32> %7, 3
ret [4 x <2 x i32>] %.fca.3.insert
}
-define arm_aapcs_vfpcc [4 x <4 x i32>] @test_vld4q_lane_bf16(bfloat* %ptr, [4 x <4 x i32>] %src.coerce) {
+define arm_aapcs_vfpcc [4 x <4 x i32>] @test_vld4q_lane_bf16(ptr %ptr, [4 x <4 x i32>] %src.coerce) {
; CHECK-LABEL: test_vld4q_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
@@ -466,169 +453,160 @@ entry:
%1 = bitcast <4 x i32> %src.coerce.fca.1.extract to <8 x bfloat>
%2 = bitcast <4 x i32> %src.coerce.fca.2.extract to <8 x bfloat>
%3 = bitcast <4 x i32> %src.coerce.fca.3.extract to <8 x bfloat>
- %4 = bitcast bfloat* %ptr to i8*
- %vld4q_lane_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4lane.v8bf16.p0i8(i8* %4, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, <8 x bfloat> %3, i32 7, i32 2)
+ %vld4q_lane_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4lane.v8bf16.p0(ptr %ptr, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, <8 x bfloat> %3, i32 7, i32 2)
%vld4q_lane_v.fca.0.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld4q_lane_v, 0
%vld4q_lane_v.fca.1.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld4q_lane_v, 1
%vld4q_lane_v.fca.2.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld4q_lane_v, 2
%vld4q_lane_v.fca.3.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld4q_lane_v, 3
- %5 = bitcast <8 x bfloat> %vld4q_lane_v.fca.0.extract to <4 x i32>
- %6 = bitcast <8 x bfloat> %vld4q_lane_v.fca.1.extract to <4 x i32>
- %7 = bitcast <8 x bfloat> %vld4q_lane_v.fca.2.extract to <4 x i32>
- %8 = bitcast <8 x bfloat> %vld4q_lane_v.fca.3.extract to <4 x i32>
- %.fca.0.insert = insertvalue [4 x <4 x i32>] undef, <4 x i32> %5, 0
- %.fca.1.insert = insertvalue [4 x <4 x i32>] %.fca.0.insert, <4 x i32> %6, 1
- %.fca.2.insert = insertvalue [4 x <4 x i32>] %.fca.1.insert, <4 x i32> %7, 2
- %.fca.3.insert = insertvalue [4 x <4 x i32>] %.fca.2.insert, <4 x i32> %8, 3
+ %4 = bitcast <8 x bfloat> %vld4q_lane_v.fca.0.extract to <4 x i32>
+ %5 = bitcast <8 x bfloat> %vld4q_lane_v.fca.1.extract to <4 x i32>
+ %6 = bitcast <8 x bfloat> %vld4q_lane_v.fca.2.extract to <4 x i32>
+ %7 = bitcast <8 x bfloat> %vld4q_lane_v.fca.3.extract to <4 x i32>
+ %.fca.0.insert = insertvalue [4 x <4 x i32>] undef, <4 x i32> %4, 0
+ %.fca.1.insert = insertvalue [4 x <4 x i32>] %.fca.0.insert, <4 x i32> %5, 1
+ %.fca.2.insert = insertvalue [4 x <4 x i32>] %.fca.1.insert, <4 x i32> %6, 2
+ %.fca.3.insert = insertvalue [4 x <4 x i32>] %.fca.2.insert, <4 x i32> %7, 3
ret [4 x <4 x i32>] %.fca.3.insert
}
-define arm_aapcs_vfpcc [2 x <2 x i32>] @test_vld2_dup_bf16(bfloat* %ptr) {
+define arm_aapcs_vfpcc [2 x <2 x i32>] @test_vld2_dup_bf16(ptr %ptr) {
; CHECK-LABEL: test_vld2_dup_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld2.16 {d0[], d1[]}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to i8*
- %vld2_dup_v = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2dup.v4bf16.p0i8(i8* %0, i32 2)
+ %vld2_dup_v = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2dup.v4bf16.p0(ptr %ptr, i32 2)
%vld2_dup_v.fca.0.extract = extractvalue { <4 x bfloat>, <4 x bfloat> } %vld2_dup_v, 0
%vld2_dup_v.fca.1.extract = extractvalue { <4 x bfloat>, <4 x bfloat> } %vld2_dup_v, 1
- %1 = bitcast <4 x bfloat> %vld2_dup_v.fca.0.extract to <2 x i32>
- %2 = bitcast <4 x bfloat> %vld2_dup_v.fca.1.extract to <2 x i32>
- %.fca.0.insert = insertvalue [2 x <2 x i32>] undef, <2 x i32> %1, 0
- %.fca.1.insert = insertvalue [2 x <2 x i32>] %.fca.0.insert, <2 x i32> %2, 1
+ %0 = bitcast <4 x bfloat> %vld2_dup_v.fca.0.extract to <2 x i32>
+ %1 = bitcast <4 x bfloat> %vld2_dup_v.fca.1.extract to <2 x i32>
+ %.fca.0.insert = insertvalue [2 x <2 x i32>] undef, <2 x i32> %0, 0
+ %.fca.1.insert = insertvalue [2 x <2 x i32>] %.fca.0.insert, <2 x i32> %1, 1
ret [2 x <2 x i32>] %.fca.1.insert
}
-define arm_aapcs_vfpcc [2 x <4 x i32>] @test_vld2q_dup_bf16(bfloat* %ptr) {
+define arm_aapcs_vfpcc [2 x <4 x i32>] @test_vld2q_dup_bf16(ptr %ptr) {
; CHECK-LABEL: test_vld2q_dup_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld2.16 {d16[], d18[]}, [r0]
; CHECK-NEXT: vld2.16 {d1[], d3[]}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to i8*
- %vld2q_dup_v = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2dup.v8bf16.p0i8(i8* %0, i32 2)
+ %vld2q_dup_v = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2dup.v8bf16.p0(ptr %ptr, i32 2)
%vld2q_dup_v.fca.0.extract = extractvalue { <8 x bfloat>, <8 x bfloat> } %vld2q_dup_v, 0
%vld2q_dup_v.fca.1.extract = extractvalue { <8 x bfloat>, <8 x bfloat> } %vld2q_dup_v, 1
- %1 = bitcast <8 x bfloat> %vld2q_dup_v.fca.0.extract to <4 x i32>
- %2 = bitcast <8 x bfloat> %vld2q_dup_v.fca.1.extract to <4 x i32>
- %.fca.0.insert = insertvalue [2 x <4 x i32>] undef, <4 x i32> %1, 0
- %.fca.1.insert = insertvalue [2 x <4 x i32>] %.fca.0.insert, <4 x i32> %2, 1
+ %0 = bitcast <8 x bfloat> %vld2q_dup_v.fca.0.extract to <4 x i32>
+ %1 = bitcast <8 x bfloat> %vld2q_dup_v.fca.1.extract to <4 x i32>
+ %.fca.0.insert = insertvalue [2 x <4 x i32>] undef, <4 x i32> %0, 0
+ %.fca.1.insert = insertvalue [2 x <4 x i32>] %.fca.0.insert, <4 x i32> %1, 1
ret [2 x <4 x i32>] %.fca.1.insert
}
-define arm_aapcs_vfpcc [3 x <2 x i32>] @test_vld3_dup_bf16(bfloat* %ptr) {
+define arm_aapcs_vfpcc [3 x <2 x i32>] @test_vld3_dup_bf16(ptr %ptr) {
; CHECK-LABEL: test_vld3_dup_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld3.16 {d0[], d1[], d2[]}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to i8*
- %vld3_dup_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3dup.v4bf16.p0i8(i8* %0, i32 2)
+ %vld3_dup_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3dup.v4bf16.p0(ptr %ptr, i32 2)
%vld3_dup_v.fca.0.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld3_dup_v, 0
%vld3_dup_v.fca.1.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld3_dup_v, 1
%vld3_dup_v.fca.2.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld3_dup_v, 2
- %1 = bitcast <4 x bfloat> %vld3_dup_v.fca.0.extract to <2 x i32>
- %2 = bitcast <4 x bfloat> %vld3_dup_v.fca.1.extract to <2 x i32>
- %3 = bitcast <4 x bfloat> %vld3_dup_v.fca.2.extract to <2 x i32>
- %.fca.0.insert = insertvalue [3 x <2 x i32>] undef, <2 x i32> %1, 0
- %.fca.1.insert = insertvalue [3 x <2 x i32>] %.fca.0.insert, <2 x i32> %2, 1
- %.fca.2.insert = insertvalue [3 x <2 x i32>] %.fca.1.insert, <2 x i32> %3, 2
+ %0 = bitcast <4 x bfloat> %vld3_dup_v.fca.0.extract to <2 x i32>
+ %1 = bitcast <4 x bfloat> %vld3_dup_v.fca.1.extract to <2 x i32>
+ %2 = bitcast <4 x bfloat> %vld3_dup_v.fca.2.extract to <2 x i32>
+ %.fca.0.insert = insertvalue [3 x <2 x i32>] undef, <2 x i32> %0, 0
+ %.fca.1.insert = insertvalue [3 x <2 x i32>] %.fca.0.insert, <2 x i32> %1, 1
+ %.fca.2.insert = insertvalue [3 x <2 x i32>] %.fca.1.insert, <2 x i32> %2, 2
ret [3 x <2 x i32>] %.fca.2.insert
}
-define arm_aapcs_vfpcc [3 x <4 x i32>] @test_vld3q_dup_bf16(bfloat* %ptr) {
+define arm_aapcs_vfpcc [3 x <4 x i32>] @test_vld3q_dup_bf16(ptr %ptr) {
; CHECK-LABEL: test_vld3q_dup_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld3.16 {d0[], d2[], d4[]}, [r0]
; CHECK-NEXT: vld3.16 {d1[], d3[], d5[]}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to i8*
- %vld3q_dup_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3dup.v8bf16.p0i8(i8* %0, i32 2)
+ %vld3q_dup_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3dup.v8bf16.p0(ptr %ptr, i32 2)
%vld3q_dup_v.fca.0.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld3q_dup_v, 0
%vld3q_dup_v.fca.1.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld3q_dup_v, 1
%vld3q_dup_v.fca.2.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld3q_dup_v, 2
- %1 = bitcast <8 x bfloat> %vld3q_dup_v.fca.0.extract to <4 x i32>
- %2 = bitcast <8 x bfloat> %vld3q_dup_v.fca.1.extract to <4 x i32>
- %3 = bitcast <8 x bfloat> %vld3q_dup_v.fca.2.extract to <4 x i32>
- %.fca.0.insert = insertvalue [3 x <4 x i32>] undef, <4 x i32> %1, 0
- %.fca.1.insert = insertvalue [3 x <4 x i32>] %.fca.0.insert, <4 x i32> %2, 1
- %.fca.2.insert = insertvalue [3 x <4 x i32>] %.fca.1.insert, <4 x i32> %3, 2
+ %0 = bitcast <8 x bfloat> %vld3q_dup_v.fca.0.extract to <4 x i32>
+ %1 = bitcast <8 x bfloat> %vld3q_dup_v.fca.1.extract to <4 x i32>
+ %2 = bitcast <8 x bfloat> %vld3q_dup_v.fca.2.extract to <4 x i32>
+ %.fca.0.insert = insertvalue [3 x <4 x i32>] undef, <4 x i32> %0, 0
+ %.fca.1.insert = insertvalue [3 x <4 x i32>] %.fca.0.insert, <4 x i32> %1, 1
+ %.fca.2.insert = insertvalue [3 x <4 x i32>] %.fca.1.insert, <4 x i32> %2, 2
ret [3 x <4 x i32>] %.fca.2.insert
}
-define arm_aapcs_vfpcc [4 x <2 x i32>] @test_vld4_dup_bf16(bfloat* %ptr) {
+define arm_aapcs_vfpcc [4 x <2 x i32>] @test_vld4_dup_bf16(ptr %ptr) {
; CHECK-LABEL: test_vld4_dup_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld4.16 {d0[], d1[], d2[], d3[]}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to i8*
- %vld4_dup_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4dup.v4bf16.p0i8(i8* %0, i32 2)
+ %vld4_dup_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4dup.v4bf16.p0(ptr %ptr, i32 2)
%vld4_dup_v.fca.0.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld4_dup_v, 0
%vld4_dup_v.fca.1.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld4_dup_v, 1
%vld4_dup_v.fca.2.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld4_dup_v, 2
%vld4_dup_v.fca.3.extract = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %vld4_dup_v, 3
- %1 = bitcast <4 x bfloat> %vld4_dup_v.fca.0.extract to <2 x i32>
- %2 = bitcast <4 x bfloat> %vld4_dup_v.fca.1.extract to <2 x i32>
- %3 = bitcast <4 x bfloat> %vld4_dup_v.fca.2.extract to <2 x i32>
- %4 = bitcast <4 x bfloat> %vld4_dup_v.fca.3.extract to <2 x i32>
- %.fca.0.insert = insertvalue [4 x <2 x i32>] undef, <2 x i32> %1, 0
- %.fca.1.insert = insertvalue [4 x <2 x i32>] %.fca.0.insert, <2 x i32> %2, 1
- %.fca.2.insert = insertvalue [4 x <2 x i32>] %.fca.1.insert, <2 x i32> %3, 2
- %.fca.3.insert = insertvalue [4 x <2 x i32>] %.fca.2.insert, <2 x i32> %4, 3
+ %0 = bitcast <4 x bfloat> %vld4_dup_v.fca.0.extract to <2 x i32>
+ %1 = bitcast <4 x bfloat> %vld4_dup_v.fca.1.extract to <2 x i32>
+ %2 = bitcast <4 x bfloat> %vld4_dup_v.fca.2.extract to <2 x i32>
+ %3 = bitcast <4 x bfloat> %vld4_dup_v.fca.3.extract to <2 x i32>
+ %.fca.0.insert = insertvalue [4 x <2 x i32>] undef, <2 x i32> %0, 0
+ %.fca.1.insert = insertvalue [4 x <2 x i32>] %.fca.0.insert, <2 x i32> %1, 1
+ %.fca.2.insert = insertvalue [4 x <2 x i32>] %.fca.1.insert, <2 x i32> %2, 2
+ %.fca.3.insert = insertvalue [4 x <2 x i32>] %.fca.2.insert, <2 x i32> %3, 3
ret [4 x <2 x i32>] %.fca.3.insert
}
-define arm_aapcs_vfpcc [4 x <4 x i32>] @test_vld4q_dup_bf16(bfloat* %ptr) {
+define arm_aapcs_vfpcc [4 x <4 x i32>] @test_vld4q_dup_bf16(ptr %ptr) {
; CHECK-LABEL: test_vld4q_dup_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld4.16 {d0[], d2[], d4[], d6[]}, [r0]
; CHECK-NEXT: vld4.16 {d1[], d3[], d5[], d7[]}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to i8*
- %vld4q_dup_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4dup.v8bf16.p0i8(i8* %0, i32 2)
+ %vld4q_dup_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4dup.v8bf16.p0(ptr %ptr, i32 2)
%vld4q_dup_v.fca.0.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld4q_dup_v, 0
%vld4q_dup_v.fca.1.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld4q_dup_v, 1
%vld4q_dup_v.fca.2.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld4q_dup_v, 2
%vld4q_dup_v.fca.3.extract = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %vld4q_dup_v, 3
- %1 = bitcast <8 x bfloat> %vld4q_dup_v.fca.0.extract to <4 x i32>
- %2 = bitcast <8 x bfloat> %vld4q_dup_v.fca.1.extract to <4 x i32>
- %3 = bitcast <8 x bfloat> %vld4q_dup_v.fca.2.extract to <4 x i32>
- %4 = bitcast <8 x bfloat> %vld4q_dup_v.fca.3.extract to <4 x i32>
- %.fca.0.insert = insertvalue [4 x <4 x i32>] undef, <4 x i32> %1, 0
- %.fca.1.insert = insertvalue [4 x <4 x i32>] %.fca.0.insert, <4 x i32> %2, 1
- %.fca.2.insert = insertvalue [4 x <4 x i32>] %.fca.1.insert, <4 x i32> %3, 2
- %.fca.3.insert = insertvalue [4 x <4 x i32>] %.fca.2.insert, <4 x i32> %4, 3
+ %0 = bitcast <8 x bfloat> %vld4q_dup_v.fca.0.extract to <4 x i32>
+ %1 = bitcast <8 x bfloat> %vld4q_dup_v.fca.1.extract to <4 x i32>
+ %2 = bitcast <8 x bfloat> %vld4q_dup_v.fca.2.extract to <4 x i32>
+ %3 = bitcast <8 x bfloat> %vld4q_dup_v.fca.3.extract to <4 x i32>
+ %.fca.0.insert = insertvalue [4 x <4 x i32>] undef, <4 x i32> %0, 0
+ %.fca.1.insert = insertvalue [4 x <4 x i32>] %.fca.0.insert, <4 x i32> %1, 1
+ %.fca.2.insert = insertvalue [4 x <4 x i32>] %.fca.1.insert, <4 x i32> %2, 2
+ %.fca.3.insert = insertvalue [4 x <4 x i32>] %.fca.2.insert, <4 x i32> %3, 3
ret [4 x <4 x i32>] %.fca.3.insert
}
-define arm_aapcs_vfpcc void @test_vst1_bf16(bfloat* %ptr, <4 x bfloat> %val) {
+define arm_aapcs_vfpcc void @test_vst1_bf16(ptr %ptr, <4 x bfloat> %val) {
; CHECK-LABEL: test_vst1_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vst1.16 {d0}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to i8*
- tail call void @llvm.arm.neon.vst1.p0i8.v4bf16(i8* %0, <4 x bfloat> %val, i32 2)
+ tail call void @llvm.arm.neon.vst1.p0.v4bf16(ptr %ptr, <4 x bfloat> %val, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_bf16(bfloat* %ptr, <8 x bfloat> %val) {
+define arm_aapcs_vfpcc void @test_vst1q_bf16(ptr %ptr, <8 x bfloat> %val) {
; CHECK-LABEL: test_vst1q_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vst1.16 {d0, d1}, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = bitcast bfloat* %ptr to i8*
- tail call void @llvm.arm.neon.vst1.p0i8.v8bf16(i8* %0, <8 x bfloat> %val, i32 2)
+ tail call void @llvm.arm.neon.vst1.p0.v8bf16(ptr %ptr, <8 x bfloat> %val, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1_lane_bf16(bfloat* nocapture %ptr, <4 x bfloat> %val) {
+define arm_aapcs_vfpcc void @test_vst1_lane_bf16(ptr nocapture %ptr, <4 x bfloat> %val) {
; CHECK-LABEL: test_vst1_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s0, s0
@@ -636,11 +614,11 @@ define arm_aapcs_vfpcc void @test_vst1_lane_bf16(bfloat* nocapture %ptr, <4 x bf
; CHECK-NEXT: bx lr
entry:
%0 = extractelement <4 x bfloat> %val, i32 1
- store bfloat %0, bfloat* %ptr, align 2
+ store bfloat %0, ptr %ptr, align 2
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_lane_bf16(bfloat* nocapture %ptr, <8 x bfloat> %val) {
+define arm_aapcs_vfpcc void @test_vst1q_lane_bf16(ptr nocapture %ptr, <8 x bfloat> %val) {
; CHECK-LABEL: test_vst1q_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s0, s3
@@ -648,11 +626,11 @@ define arm_aapcs_vfpcc void @test_vst1q_lane_bf16(bfloat* nocapture %ptr, <8 x b
; CHECK-NEXT: bx lr
entry:
%0 = extractelement <8 x bfloat> %val, i32 7
- store bfloat %0, bfloat* %ptr, align 2
+ store bfloat %0, ptr %ptr, align 2
ret void
}
-define arm_aapcs_vfpcc void @test_vst1_bf16_x2(bfloat* nocapture %ptr, [2 x <2 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst1_bf16_x2(ptr nocapture %ptr, [2 x <2 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst1_bf16_x2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
@@ -664,11 +642,11 @@ entry:
%val.coerce.fca.1.extract = extractvalue [2 x <2 x i32>] %val.coerce, 1
%0 = bitcast <2 x i32> %val.coerce.fca.0.extract to <4 x bfloat>
%1 = bitcast <2 x i32> %val.coerce.fca.1.extract to <4 x bfloat>
- tail call void @llvm.arm.neon.vst1x2.p0bf16.v4bf16(bfloat* %ptr, <4 x bfloat> %0, <4 x bfloat> %1)
+ tail call void @llvm.arm.neon.vst1x2.p0.v4bf16(ptr %ptr, <4 x bfloat> %0, <4 x bfloat> %1)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_bf16_x2(bfloat* nocapture %ptr, [2 x <4 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst1q_bf16_x2(ptr nocapture %ptr, [2 x <4 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst1q_bf16_x2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
@@ -680,11 +658,11 @@ entry:
%val.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %val.coerce, 1
%0 = bitcast <4 x i32> %val.coerce.fca.0.extract to <8 x bfloat>
%1 = bitcast <4 x i32> %val.coerce.fca.1.extract to <8 x bfloat>
- tail call void @llvm.arm.neon.vst1x2.p0bf16.v8bf16(bfloat* %ptr, <8 x bfloat> %0, <8 x bfloat> %1)
+ tail call void @llvm.arm.neon.vst1x2.p0.v8bf16(ptr %ptr, <8 x bfloat> %0, <8 x bfloat> %1)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1_bf16_x3(bfloat* nocapture %ptr, [3 x <2 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst1_bf16_x3(ptr nocapture %ptr, [3 x <2 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst1_bf16_x3:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
@@ -699,11 +677,11 @@ entry:
%0 = bitcast <2 x i32> %val.coerce.fca.0.extract to <4 x bfloat>
%1 = bitcast <2 x i32> %val.coerce.fca.1.extract to <4 x bfloat>
%2 = bitcast <2 x i32> %val.coerce.fca.2.extract to <4 x bfloat>
- tail call void @llvm.arm.neon.vst1x3.p0bf16.v4bf16(bfloat* %ptr, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2)
+ tail call void @llvm.arm.neon.vst1x3.p0.v4bf16(ptr %ptr, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_bf16_x3(bfloat* nocapture %ptr, [3 x <4 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst1q_bf16_x3(ptr nocapture %ptr, [3 x <4 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst1q_bf16_x3:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
@@ -719,11 +697,11 @@ entry:
%0 = bitcast <4 x i32> %val.coerce.fca.0.extract to <8 x bfloat>
%1 = bitcast <4 x i32> %val.coerce.fca.1.extract to <8 x bfloat>
%2 = bitcast <4 x i32> %val.coerce.fca.2.extract to <8 x bfloat>
- tail call void @llvm.arm.neon.vst1x3.p0bf16.v8bf16(bfloat* %ptr, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2)
+ tail call void @llvm.arm.neon.vst1x3.p0.v8bf16(ptr %ptr, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1_bf16_x4(bfloat* nocapture %ptr, [4 x <2 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst1_bf16_x4(ptr nocapture %ptr, [4 x <2 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst1_bf16_x4:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q0_q1 def $q0_q1
@@ -741,11 +719,11 @@ entry:
%1 = bitcast <2 x i32> %val.coerce.fca.1.extract to <4 x bfloat>
%2 = bitcast <2 x i32> %val.coerce.fca.2.extract to <4 x bfloat>
%3 = bitcast <2 x i32> %val.coerce.fca.3.extract to <4 x bfloat>
- tail call void @llvm.arm.neon.vst1x4.p0bf16.v4bf16(bfloat* %ptr, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, <4 x bfloat> %3)
+ tail call void @llvm.arm.neon.vst1x4.p0.v4bf16(ptr %ptr, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, <4 x bfloat> %3)
ret void
}
-define arm_aapcs_vfpcc void @test_vst1q_bf16_x4(bfloat* nocapture %ptr, [4 x <4 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst1q_bf16_x4(ptr nocapture %ptr, [4 x <4 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst1q_bf16_x4:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
@@ -764,11 +742,11 @@ entry:
%1 = bitcast <4 x i32> %val.coerce.fca.1.extract to <8 x bfloat>
%2 = bitcast <4 x i32> %val.coerce.fca.2.extract to <8 x bfloat>
%3 = bitcast <4 x i32> %val.coerce.fca.3.extract to <8 x bfloat>
- tail call void @llvm.arm.neon.vst1x4.p0bf16.v8bf16(bfloat* %ptr, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, <8 x bfloat> %3)
+ tail call void @llvm.arm.neon.vst1x4.p0.v8bf16(ptr %ptr, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, <8 x bfloat> %3)
ret void
}
-define arm_aapcs_vfpcc void @test_vst2_bf16(bfloat* %ptr, [2 x <2 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst2_bf16(ptr %ptr, [2 x <2 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst2_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
@@ -780,12 +758,11 @@ entry:
%val.coerce.fca.1.extract = extractvalue [2 x <2 x i32>] %val.coerce, 1
%0 = bitcast <2 x i32> %val.coerce.fca.0.extract to <4 x bfloat>
%1 = bitcast <2 x i32> %val.coerce.fca.1.extract to <4 x bfloat>
- %2 = bitcast bfloat* %ptr to i8*
- tail call void @llvm.arm.neon.vst2.p0i8.v4bf16(i8* %2, <4 x bfloat> %0, <4 x bfloat> %1, i32 2)
+ tail call void @llvm.arm.neon.vst2.p0.v4bf16(ptr %ptr, <4 x bfloat> %0, <4 x bfloat> %1, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst2q_bf16(bfloat* %ptr, [2 x <4 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst2q_bf16(ptr %ptr, [2 x <4 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst2q_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
@@ -797,12 +774,11 @@ entry:
%val.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %val.coerce, 1
%0 = bitcast <4 x i32> %val.coerce.fca.0.extract to <8 x bfloat>
%1 = bitcast <4 x i32> %val.coerce.fca.1.extract to <8 x bfloat>
- %2 = bitcast bfloat* %ptr to i8*
- tail call void @llvm.arm.neon.vst2.p0i8.v8bf16(i8* %2, <8 x bfloat> %0, <8 x bfloat> %1, i32 2)
+ tail call void @llvm.arm.neon.vst2.p0.v8bf16(ptr %ptr, <8 x bfloat> %0, <8 x bfloat> %1, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst2_lane_bf16(bfloat* %ptr, [2 x <2 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst2_lane_bf16(ptr %ptr, [2 x <2 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst2_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
@@ -814,12 +790,11 @@ entry:
%val.coerce.fca.1.extract = extractvalue [2 x <2 x i32>] %val.coerce, 1
%0 = bitcast <2 x i32> %val.coerce.fca.0.extract to <4 x bfloat>
%1 = bitcast <2 x i32> %val.coerce.fca.1.extract to <4 x bfloat>
- %2 = bitcast bfloat* %ptr to i8*
- tail call void @llvm.arm.neon.vst2lane.p0i8.v4bf16(i8* %2, <4 x bfloat> %0, <4 x bfloat> %1, i32 1, i32 2)
+ tail call void @llvm.arm.neon.vst2lane.p0.v4bf16(ptr %ptr, <4 x bfloat> %0, <4 x bfloat> %1, i32 1, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst2q_lane_bf16(bfloat* %ptr, [2 x <4 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst2q_lane_bf16(ptr %ptr, [2 x <4 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst2q_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
@@ -831,12 +806,11 @@ entry:
%val.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %val.coerce, 1
%0 = bitcast <4 x i32> %val.coerce.fca.0.extract to <8 x bfloat>
%1 = bitcast <4 x i32> %val.coerce.fca.1.extract to <8 x bfloat>
- %2 = bitcast bfloat* %ptr to i8*
- tail call void @llvm.arm.neon.vst2lane.p0i8.v8bf16(i8* %2, <8 x bfloat> %0, <8 x bfloat> %1, i32 7, i32 2)
+ tail call void @llvm.arm.neon.vst2lane.p0.v8bf16(ptr %ptr, <8 x bfloat> %0, <8 x bfloat> %1, i32 7, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst3_bf16(bfloat* %ptr, [3 x <2 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst3_bf16(ptr %ptr, [3 x <2 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst3_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
@@ -851,12 +825,11 @@ entry:
%0 = bitcast <2 x i32> %val.coerce.fca.0.extract to <4 x bfloat>
%1 = bitcast <2 x i32> %val.coerce.fca.1.extract to <4 x bfloat>
%2 = bitcast <2 x i32> %val.coerce.fca.2.extract to <4 x bfloat>
- %3 = bitcast bfloat* %ptr to i8*
- tail call void @llvm.arm.neon.vst3.p0i8.v4bf16(i8* %3, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, i32 2)
+ tail call void @llvm.arm.neon.vst3.p0.v4bf16(ptr %ptr, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst3q_bf16(bfloat* %ptr, [3 x <4 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst3q_bf16(ptr %ptr, [3 x <4 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst3q_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
@@ -872,12 +845,11 @@ entry:
%0 = bitcast <4 x i32> %val.coerce.fca.0.extract to <8 x bfloat>
%1 = bitcast <4 x i32> %val.coerce.fca.1.extract to <8 x bfloat>
%2 = bitcast <4 x i32> %val.coerce.fca.2.extract to <8 x bfloat>
- %3 = bitcast bfloat* %ptr to i8*
- tail call void @llvm.arm.neon.vst3.p0i8.v8bf16(i8* %3, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, i32 2)
+ tail call void @llvm.arm.neon.vst3.p0.v8bf16(ptr %ptr, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst3_lane_bf16(bfloat* %ptr, [3 x <2 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst3_lane_bf16(ptr %ptr, [3 x <2 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst3_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
@@ -892,12 +864,11 @@ entry:
%0 = bitcast <2 x i32> %val.coerce.fca.0.extract to <4 x bfloat>
%1 = bitcast <2 x i32> %val.coerce.fca.1.extract to <4 x bfloat>
%2 = bitcast <2 x i32> %val.coerce.fca.2.extract to <4 x bfloat>
- %3 = bitcast bfloat* %ptr to i8*
- tail call void @llvm.arm.neon.vst3lane.p0i8.v4bf16(i8* %3, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, i32 1, i32 2)
+ tail call void @llvm.arm.neon.vst3lane.p0.v4bf16(ptr %ptr, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, i32 1, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst3q_lane_bf16(bfloat* %ptr, [3 x <4 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst3q_lane_bf16(ptr %ptr, [3 x <4 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst3q_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
@@ -912,12 +883,11 @@ entry:
%0 = bitcast <4 x i32> %val.coerce.fca.0.extract to <8 x bfloat>
%1 = bitcast <4 x i32> %val.coerce.fca.1.extract to <8 x bfloat>
%2 = bitcast <4 x i32> %val.coerce.fca.2.extract to <8 x bfloat>
- %3 = bitcast bfloat* %ptr to i8*
- tail call void @llvm.arm.neon.vst3lane.p0i8.v8bf16(i8* %3, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, i32 7, i32 2)
+ tail call void @llvm.arm.neon.vst3lane.p0.v8bf16(ptr %ptr, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, i32 7, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst4_bf16(bfloat* %ptr, [4 x <2 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst4_bf16(ptr %ptr, [4 x <2 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst4_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q0_q1 def $q0_q1
@@ -935,12 +905,11 @@ entry:
%1 = bitcast <2 x i32> %val.coerce.fca.1.extract to <4 x bfloat>
%2 = bitcast <2 x i32> %val.coerce.fca.2.extract to <4 x bfloat>
%3 = bitcast <2 x i32> %val.coerce.fca.3.extract to <4 x bfloat>
- %4 = bitcast bfloat* %ptr to i8*
- tail call void @llvm.arm.neon.vst4.p0i8.v4bf16(i8* %4, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, <4 x bfloat> %3, i32 2)
+ tail call void @llvm.arm.neon.vst4.p0.v4bf16(ptr %ptr, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, <4 x bfloat> %3, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst4q_bf16(bfloat* %ptr, [4 x <4 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst4q_bf16(ptr %ptr, [4 x <4 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst4q_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
@@ -959,12 +928,11 @@ entry:
%1 = bitcast <4 x i32> %val.coerce.fca.1.extract to <8 x bfloat>
%2 = bitcast <4 x i32> %val.coerce.fca.2.extract to <8 x bfloat>
%3 = bitcast <4 x i32> %val.coerce.fca.3.extract to <8 x bfloat>
- %4 = bitcast bfloat* %ptr to i8*
- tail call void @llvm.arm.neon.vst4.p0i8.v8bf16(i8* %4, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, <8 x bfloat> %3, i32 2)
+ tail call void @llvm.arm.neon.vst4.p0.v8bf16(ptr %ptr, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, <8 x bfloat> %3, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst4_lane_bf16(bfloat* %ptr, [4 x <2 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst4_lane_bf16(ptr %ptr, [4 x <2 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst4_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q0_q1 def $q0_q1
@@ -982,12 +950,11 @@ entry:
%1 = bitcast <2 x i32> %val.coerce.fca.1.extract to <4 x bfloat>
%2 = bitcast <2 x i32> %val.coerce.fca.2.extract to <4 x bfloat>
%3 = bitcast <2 x i32> %val.coerce.fca.3.extract to <4 x bfloat>
- %4 = bitcast bfloat* %ptr to i8*
- tail call void @llvm.arm.neon.vst4lane.p0i8.v4bf16(i8* %4, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, <4 x bfloat> %3, i32 1, i32 2)
+ tail call void @llvm.arm.neon.vst4lane.p0.v4bf16(ptr %ptr, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, <4 x bfloat> %3, i32 1, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @test_vst4q_lane_bf16(bfloat* %ptr, [4 x <4 x i32>] %val.coerce) {
+define arm_aapcs_vfpcc void @test_vst4q_lane_bf16(ptr %ptr, [4 x <4 x i32>] %val.coerce) {
; CHECK-LABEL: test_vst4q_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
@@ -1005,58 +972,57 @@ entry:
%1 = bitcast <4 x i32> %val.coerce.fca.1.extract to <8 x bfloat>
%2 = bitcast <4 x i32> %val.coerce.fca.2.extract to <8 x bfloat>
%3 = bitcast <4 x i32> %val.coerce.fca.3.extract to <8 x bfloat>
- %4 = bitcast bfloat* %ptr to i8*
- tail call void @llvm.arm.neon.vst4lane.p0i8.v8bf16(i8* %4, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, <8 x bfloat> %3, i32 7, i32 2)
+ tail call void @llvm.arm.neon.vst4lane.p0.v8bf16(ptr %ptr, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, <8 x bfloat> %3, i32 7, i32 2)
ret void
}
-declare { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2.v4bf16.p0i8(i8*, i32)
-declare { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2.v8bf16.p0i8(i8*, i32)
-declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3.v4bf16.p0i8(i8*, i32)
-declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3.v8bf16.p0i8(i8*, i32)
-declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4.v4bf16.p0i8(i8*, i32)
-declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4.v8bf16.p0i8(i8*, i32)
+declare { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2.v4bf16.p0(ptr, i32)
+declare { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2.v8bf16.p0(ptr, i32)
+declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3.v4bf16.p0(ptr, i32)
+declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3.v8bf16.p0(ptr, i32)
+declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4.v4bf16.p0(ptr, i32)
+declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4.v8bf16.p0(ptr, i32)
-declare { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2dup.v4bf16.p0i8(i8*, i32)
-declare { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2dup.v8bf16.p0i8(i8*, i32)
-declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3dup.v4bf16.p0i8(i8*, i32)
-declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3dup.v8bf16.p0i8(i8*, i32)
-declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4dup.v4bf16.p0i8(i8*, i32)
-declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4dup.v8bf16.p0i8(i8*, i32)
+declare { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2dup.v4bf16.p0(ptr, i32)
+declare { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2dup.v8bf16.p0(ptr, i32)
+declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3dup.v4bf16.p0(ptr, i32)
+declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3dup.v8bf16.p0(ptr, i32)
+declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4dup.v4bf16.p0(ptr, i32)
+declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4dup.v8bf16.p0(ptr, i32)
-declare { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x2.v4bf16.p0bf16(bfloat*)
-declare { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x2.v8bf16.p0bf16(bfloat*)
-declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x3.v4bf16.p0bf16(bfloat*)
-declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x3.v8bf16.p0bf16(bfloat*)
-declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x4.v4bf16.p0bf16(bfloat*)
-declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x4.v8bf16.p0bf16(bfloat*)
+declare { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x2.v4bf16.p0(ptr)
+declare { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x2.v8bf16.p0(ptr)
+declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x3.v4bf16.p0(ptr)
+declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x3.v8bf16.p0(ptr)
+declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x4.v4bf16.p0(ptr)
+declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x4.v8bf16.p0(ptr)
-declare { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2lane.v4bf16.p0i8(i8*, <4 x bfloat>, <4 x bfloat>, i32, i32)
-declare { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2lane.v8bf16.p0i8(i8*, <8 x bfloat>, <8 x bfloat>, i32, i32)
-declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3lane.v4bf16.p0i8(i8*, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, i32, i32)
-declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3lane.v8bf16.p0i8(i8*, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, i32, i32)
-declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4lane.v4bf16.p0i8(i8*, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, i32, i32)
-declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4lane.v8bf16.p0i8(i8*, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, i32, i32)
+declare { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2lane.v4bf16.p0(ptr, <4 x bfloat>, <4 x bfloat>, i32, i32)
+declare { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2lane.v8bf16.p0(ptr, <8 x bfloat>, <8 x bfloat>, i32, i32)
+declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3lane.v4bf16.p0(ptr, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, i32, i32)
+declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3lane.v8bf16.p0(ptr, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, i32, i32)
+declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4lane.v4bf16.p0(ptr, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, i32, i32)
+declare { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4lane.v8bf16.p0(ptr, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, i32, i32)
-declare void @llvm.arm.neon.vst1.p0i8.v4bf16(i8*, <4 x bfloat>, i32)
-declare void @llvm.arm.neon.vst1.p0i8.v8bf16(i8*, <8 x bfloat>, i32)
-declare void @llvm.arm.neon.vst2.p0i8.v4bf16(i8*, <4 x bfloat>, <4 x bfloat>, i32)
-declare void @llvm.arm.neon.vst2.p0i8.v8bf16(i8*, <8 x bfloat>, <8 x bfloat>, i32)
-declare void @llvm.arm.neon.vst3.p0i8.v4bf16(i8*, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, i32)
-declare void @llvm.arm.neon.vst3.p0i8.v8bf16(i8*, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, i32)
-declare void @llvm.arm.neon.vst4.p0i8.v4bf16(i8*, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, i32)
-declare void @llvm.arm.neon.vst4.p0i8.v8bf16(i8*, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, i32)
+declare void @llvm.arm.neon.vst1.p0.v4bf16(ptr, <4 x bfloat>, i32)
+declare void @llvm.arm.neon.vst1.p0.v8bf16(ptr, <8 x bfloat>, i32)
+declare void @llvm.arm.neon.vst2.p0.v4bf16(ptr, <4 x bfloat>, <4 x bfloat>, i32)
+declare void @llvm.arm.neon.vst2.p0.v8bf16(ptr, <8 x bfloat>, <8 x bfloat>, i32)
+declare void @llvm.arm.neon.vst3.p0.v4bf16(ptr, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, i32)
+declare void @llvm.arm.neon.vst3.p0.v8bf16(ptr, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, i32)
+declare void @llvm.arm.neon.vst4.p0.v4bf16(ptr, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, i32)
+declare void @llvm.arm.neon.vst4.p0.v8bf16(ptr, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, i32)
-declare void @llvm.arm.neon.vst1x2.p0bf16.v4bf16(bfloat* nocapture, <4 x bfloat>, <4 x bfloat>)
-declare void @llvm.arm.neon.vst1x2.p0bf16.v8bf16(bfloat* nocapture, <8 x bfloat>, <8 x bfloat>)
-declare void @llvm.arm.neon.vst1x3.p0bf16.v4bf16(bfloat* nocapture, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>)
-declare void @llvm.arm.neon.vst1x3.p0bf16.v8bf16(bfloat* nocapture, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>)
-declare void @llvm.arm.neon.vst1x4.p0bf16.v4bf16(bfloat* nocapture, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>)
-declare void @llvm.arm.neon.vst1x4.p0bf16.v8bf16(bfloat* nocapture, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>)
+declare void @llvm.arm.neon.vst1x2.p0.v4bf16(ptr nocapture, <4 x bfloat>, <4 x bfloat>)
+declare void @llvm.arm.neon.vst1x2.p0.v8bf16(ptr nocapture, <8 x bfloat>, <8 x bfloat>)
+declare void @llvm.arm.neon.vst1x3.p0.v4bf16(ptr nocapture, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>)
+declare void @llvm.arm.neon.vst1x3.p0.v8bf16(ptr nocapture, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>)
+declare void @llvm.arm.neon.vst1x4.p0.v4bf16(ptr nocapture, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>)
+declare void @llvm.arm.neon.vst1x4.p0.v8bf16(ptr nocapture, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>)
-declare void @llvm.arm.neon.vst2lane.p0i8.v4bf16(i8*, <4 x bfloat>, <4 x bfloat>, i32, i32)
-declare void @llvm.arm.neon.vst2lane.p0i8.v8bf16(i8*, <8 x bfloat>, <8 x bfloat>, i32, i32)
-declare void @llvm.arm.neon.vst3lane.p0i8.v4bf16(i8*, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, i32, i32)
-declare void @llvm.arm.neon.vst3lane.p0i8.v8bf16(i8*, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, i32, i32)
-declare void @llvm.arm.neon.vst4lane.p0i8.v4bf16(i8*, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, i32, i32)
-declare void @llvm.arm.neon.vst4lane.p0i8.v8bf16(i8*, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, i32, i32)
+declare void @llvm.arm.neon.vst2lane.p0.v4bf16(ptr, <4 x bfloat>, <4 x bfloat>, i32, i32)
+declare void @llvm.arm.neon.vst2lane.p0.v8bf16(ptr, <8 x bfloat>, <8 x bfloat>, i32, i32)
+declare void @llvm.arm.neon.vst3lane.p0.v4bf16(ptr, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, i32, i32)
+declare void @llvm.arm.neon.vst3lane.p0.v8bf16(ptr, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, i32, i32)
+declare void @llvm.arm.neon.vst4lane.p0.v4bf16(ptr, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, i32, i32)
+declare void @llvm.arm.neon.vst4lane.p0.v8bf16(ptr, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, i32, i32)
diff --git a/llvm/test/CodeGen/ARM/bf16-shuffle.ll b/llvm/test/CodeGen/ARM/bf16-shuffle.ll
index 47ac45caea369..9968e7887f4b3 100644
--- a/llvm/test/CodeGen/ARM/bf16-shuffle.ll
+++ b/llvm/test/CodeGen/ARM/bf16-shuffle.ll
@@ -458,13 +458,13 @@ entry:
ret <8 x bfloat> %shuffle.i
}
-define <4 x bfloat> @test_vld_dup1_4xbfloat(bfloat* %b) {
+define <4 x bfloat> @test_vld_dup1_4xbfloat(ptr %b) {
; CHECK-LABEL: test_vld_dup1_4xbfloat:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d0[]}, [r0:16]
; CHECK-NEXT: bx lr
entry:
- %b1 = load bfloat, bfloat* %b, align 2
+ %b1 = load bfloat, ptr %b, align 2
%vecinit = insertelement <4 x bfloat> undef, bfloat %b1, i32 0
%vecinit2 = insertelement <4 x bfloat> %vecinit, bfloat %b1, i32 1
%vecinit3 = insertelement <4 x bfloat> %vecinit2, bfloat %b1, i32 2
@@ -472,13 +472,13 @@ entry:
ret <4 x bfloat> %vecinit4
}
-define <8 x bfloat> @test_vld_dup1_8xbfloat(bfloat* %b) local_unnamed_addr {
+define <8 x bfloat> @test_vld_dup1_8xbfloat(ptr %b) local_unnamed_addr {
; CHECK-LABEL: test_vld_dup1_8xbfloat:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.16 {d0[], d1[]}, [r0:16]
; CHECK-NEXT: bx lr
entry:
- %b1 = load bfloat, bfloat* %b, align 2
+ %b1 = load bfloat, ptr %b, align 2
%vecinit = insertelement <8 x bfloat> undef, bfloat %b1, i32 0
%vecinit8 = shufflevector <8 x bfloat> %vecinit, <8 x bfloat> undef, <8 x i32> zeroinitializer
ret <8 x bfloat> %vecinit8
diff --git a/llvm/test/CodeGen/ARM/bfi-chain-cse-crash.ll b/llvm/test/CodeGen/ARM/bfi-chain-cse-crash.ll
index e58be8fdd7eea..6424f7b665ed9 100644
--- a/llvm/test/CodeGen/ARM/bfi-chain-cse-crash.ll
+++ b/llvm/test/CodeGen/ARM/bfi-chain-cse-crash.ll
@@ -3,7 +3,7 @@
target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
target triple = "thumbv7s-apple-ios3.1.3"
-define void @bfi_chain_cse_crash(i8* %0, i8 *%ptr) {
+define void @bfi_chain_cse_crash(ptr %0, ptr %ptr) {
; CHECK-LABEL: bfi_chain_cse_crash:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrb r2, [r0]
@@ -16,7 +16,7 @@ define void @bfi_chain_cse_crash(i8* %0, i8 *%ptr) {
; CHECK-NEXT: strb r0, [r1]
; CHECK-NEXT: bx lr
entry:
- %1 = load i8, i8* %0, align 1
+ %1 = load i8, ptr %0, align 1
%2 = and i8 %1, 1
%3 = select i1 false, i8 %2, i8 0
%4 = and i8 %1, 4
@@ -35,7 +35,7 @@ entry:
%17 = trunc i32 %16 to i8
%18 = select i1 %11, i8 %2, i8 %14
%19 = select i1 %11, i8 %9, i8 %17
- store i8 %18, i8* %0, align 1
- store i8 %19, i8* %ptr, align 1
+ store i8 %18, ptr %0, align 1
+ store i8 %19, ptr %ptr, align 1
ret void
}
diff --git a/llvm/test/CodeGen/ARM/bfi.ll b/llvm/test/CodeGen/ARM/bfi.ll
index 786bf1c2522ce..91a74e535a221 100644
--- a/llvm/test/CodeGen/ARM/bfi.ll
+++ b/llvm/test/CodeGen/ARM/bfi.ll
@@ -3,7 +3,7 @@
%struct.F = type { [3 x i8], i8 }
- at X = common global %struct.F zeroinitializer, align 4 ; <%struct.F*> [#uses=1]
+ at X = common global %struct.F zeroinitializer, align 4 ; <ptr> [#uses=1]
define void @f1([1 x i32] %f.coerce0) nounwind {
; CHECK-LABEL: f1:
@@ -16,10 +16,10 @@ define void @f1([1 x i32] %f.coerce0) nounwind {
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = load i32, i32* bitcast (%struct.F* @X to i32*), align 4 ; <i32> [#uses=1]
+ %0 = load i32, ptr @X, align 4 ; <i32> [#uses=1]
%1 = and i32 %0, -62914561 ; <i32> [#uses=1]
%2 = or i32 %1, 41943040 ; <i32> [#uses=1]
- store i32 %2, i32* bitcast (%struct.F* @X to i32*), align 4
+ store i32 %2, ptr @X, align 4
ret void
}
@@ -394,7 +394,7 @@ define void @bfi3_uses(i32 %a, i32 %b) {
ret void
}
-define i32 @bfi4(i32 %A, i2 zeroext %BB, i32* %d) {
+define i32 @bfi4(i32 %A, i2 zeroext %BB, ptr %d) {
; CHECK-LABEL: bfi4:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push {r11, lr}
@@ -422,7 +422,7 @@ entry:
%tobool21.not = icmp eq i32 %and20, 0
%or26 = or i32 %spec.select112, 1032
%spec.select114 = select i1 %tobool21.not, i32 %spec.select112, i32 %or26
- store i32 %spec.select114, i32* %d, align 4
+ store i32 %spec.select114, ptr %d, align 4
%and29 = shl i32 %A, 8
%l2 = and i32 %and29, 2048
%l3 = or i32 %l2, %spec.select114
@@ -433,7 +433,7 @@ entry:
%and45 = shl i32 %A, 1
%l4 = and i32 %and45, 128
%l5 = or i32 %l4, %spec.select
- store i32 %l5, i32* %d, align 4
+ store i32 %l5, ptr %d, align 4
%and52 = and i32 %A, 128
ret i32 %and52
}
diff --git a/llvm/test/CodeGen/ARM/bfloat.ll b/llvm/test/CodeGen/ARM/bfloat.ll
index 53b7cd6018f6f..be62e076c5739 100644
--- a/llvm/test/CodeGen/ARM/bfloat.ll
+++ b/llvm/test/CodeGen/ARM/bfloat.ll
@@ -5,7 +5,7 @@
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv8.6a-arm-none-eabi"
-define bfloat @load_scalar_bf(bfloat* %addr) {
+define bfloat @load_scalar_bf(ptr %addr) {
; HARD-LABEL: load_scalar_bf:
; HARD: @ %bb.0: @ %entry
; HARD-NEXT: vldr.16 s0, [r0]
@@ -17,11 +17,11 @@ define bfloat @load_scalar_bf(bfloat* %addr) {
; SOFT-NEXT: vmov r0, s0
; SOFT-NEXT: bx lr
entry:
- %0 = load bfloat, bfloat* %addr, align 2
+ %0 = load bfloat, ptr %addr, align 2
ret bfloat %0
}
-define void @store_scalar_bf(bfloat %v, bfloat* %addr) {
+define void @store_scalar_bf(bfloat %v, ptr %addr) {
; HARD-LABEL: store_scalar_bf:
; HARD: @ %bb.0: @ %entry
; HARD-NEXT: vstr.16 s0, [r0]
@@ -33,11 +33,11 @@ define void @store_scalar_bf(bfloat %v, bfloat* %addr) {
; SOFT-NEXT: vstr.16 s0, [r1]
; SOFT-NEXT: bx lr
entry:
- store bfloat %v, bfloat* %addr, align 2
+ store bfloat %v, ptr %addr, align 2
ret void
}
-define <4 x bfloat> @load_vector4_bf(<4 x bfloat>* %addr) {
+define <4 x bfloat> @load_vector4_bf(ptr %addr) {
; HARD-LABEL: load_vector4_bf:
; HARD: @ %bb.0: @ %entry
; HARD-NEXT: vldr d0, [r0]
@@ -49,11 +49,11 @@ define <4 x bfloat> @load_vector4_bf(<4 x bfloat>* %addr) {
; SOFT-NEXT: vmov r0, r1, d16
; SOFT-NEXT: bx lr
entry:
- %0 = load <4 x bfloat>, <4 x bfloat>* %addr, align 8
+ %0 = load <4 x bfloat>, ptr %addr, align 8
ret <4 x bfloat> %0
}
-define void @store_vector4_bf(<4 x bfloat> %v, <4 x bfloat>* %addr) {
+define void @store_vector4_bf(<4 x bfloat> %v, ptr %addr) {
; HARD-LABEL: store_vector4_bf:
; HARD: @ %bb.0: @ %entry
; HARD-NEXT: vstr d0, [r0]
@@ -64,11 +64,11 @@ define void @store_vector4_bf(<4 x bfloat> %v, <4 x bfloat>* %addr) {
; SOFT-NEXT: strd r0, r1, [r2]
; SOFT-NEXT: bx lr
entry:
- store <4 x bfloat> %v, <4 x bfloat>* %addr, align 8
+ store <4 x bfloat> %v, ptr %addr, align 8
ret void
}
-define <8 x bfloat> @load_vector8_bf(<8 x bfloat>* %addr) {
+define <8 x bfloat> @load_vector8_bf(ptr %addr) {
; HARD-LABEL: load_vector8_bf:
; HARD: @ %bb.0: @ %entry
; HARD-NEXT: vld1.64 {d0, d1}, [r0]
@@ -81,11 +81,11 @@ define <8 x bfloat> @load_vector8_bf(<8 x bfloat>* %addr) {
; SOFT-NEXT: vmov r2, r3, d17
; SOFT-NEXT: bx lr
entry:
- %0 = load <8 x bfloat>, <8 x bfloat>* %addr, align 8
+ %0 = load <8 x bfloat>, ptr %addr, align 8
ret <8 x bfloat> %0
}
-define void @store_vector8_bf(<8 x bfloat> %v, <8 x bfloat>* %addr) {
+define void @store_vector8_bf(<8 x bfloat> %v, ptr %addr) {
; HARD-LABEL: store_vector8_bf:
; HARD: @ %bb.0: @ %entry
; HARD-NEXT: vst1.64 {d0, d1}, [r0]
@@ -99,7 +99,7 @@ define void @store_vector8_bf(<8 x bfloat> %v, <8 x bfloat>* %addr) {
; SOFT-NEXT: vst1.64 {d16, d17}, [r12]
; SOFT-NEXT: bx lr
entry:
- store <8 x bfloat> %v, <8 x bfloat>* %addr, align 8
+ store <8 x bfloat> %v, ptr %addr, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/bfx.ll b/llvm/test/CodeGen/ARM/bfx.ll
index 629060218e435..a585fc8be9ede 100644
--- a/llvm/test/CodeGen/ARM/bfx.ll
+++ b/llvm/test/CodeGen/ARM/bfx.ll
@@ -27,7 +27,7 @@ define i32 @ubfx2(i32 %a) {
}
; rdar://12870177
-define i32 @ubfx_opt(i32* nocapture %ctx, i32 %x) nounwind readonly ssp {
+define i32 @ubfx_opt(ptr nocapture %ctx, i32 %x) nounwind readonly ssp {
entry:
; CHECK: ubfx_opt
; CHECK: lsr [[REG1:(lr|r[0-9]+)]], r1, #24
@@ -41,13 +41,13 @@ entry:
%and1 = lshr i32 %x, 16
%shr2 = and i32 %and1, 255
%shr4 = lshr i32 %x, 24
- %arrayidx = getelementptr inbounds i32, i32* %ctx, i32 %shr4
- %0 = load i32, i32* %arrayidx, align 4
- %arrayidx5 = getelementptr inbounds i32, i32* %ctx, i32 %shr2
- %1 = load i32, i32* %arrayidx5, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %ctx, i32 %shr4
+ %0 = load i32, ptr %arrayidx, align 4
+ %arrayidx5 = getelementptr inbounds i32, ptr %ctx, i32 %shr2
+ %1 = load i32, ptr %arrayidx5, align 4
%add = add i32 %1, %0
- %arrayidx6 = getelementptr inbounds i32, i32* %ctx, i32 %shr
- %2 = load i32, i32* %arrayidx6, align 4
+ %arrayidx6 = getelementptr inbounds i32, ptr %ctx, i32 %shr
+ %2 = load i32, ptr %arrayidx6, align 4
%add7 = add i32 %add, %2
ret i32 %add7
}
diff --git a/llvm/test/CodeGen/ARM/big-endian-eh-unwind.ll b/llvm/test/CodeGen/ARM/big-endian-eh-unwind.ll
index 7df5f30570ef6..1d0e5d49e264e 100644
--- a/llvm/test/CodeGen/ARM/big-endian-eh-unwind.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-eh-unwind.ll
@@ -14,16 +14,16 @@
; }
;}
-define void @_Z4testii(i32 %a, i32 %b) #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+define void @_Z4testii(i32 %a, i32 %b) #0 personality ptr @__gxx_personality_v0 {
entry:
invoke void @_Z3fooi(i32 %a)
to label %try.cont unwind label %lpad
lpad: ; preds = %entry
- %0 = landingpad { i8*, i32 }
- catch i8* null
- %1 = extractvalue { i8*, i32 } %0, 0
- %2 = tail call i8* @__cxa_begin_catch(i8* %1) #2
+ %0 = landingpad { ptr, i32 }
+ catch ptr null
+ %1 = extractvalue { ptr, i32 } %0, 0
+ %2 = tail call ptr @__cxa_begin_catch(ptr %1) #2
invoke void @_Z3fooi(i32 %b)
to label %invoke.cont2 unwind label %lpad1
@@ -35,19 +35,19 @@ try.cont: ; preds = %entry, %invoke.cont
ret void
lpad1: ; preds = %lpad
- %3 = landingpad { i8*, i32 }
+ %3 = landingpad { ptr, i32 }
cleanup
invoke void @__cxa_end_catch()
to label %eh.resume unwind label %terminate.lpad
eh.resume: ; preds = %lpad1
- resume { i8*, i32 } %3
+ resume { ptr, i32 } %3
terminate.lpad: ; preds = %lpad1
- %4 = landingpad { i8*, i32 }
- catch i8* null
- %5 = extractvalue { i8*, i32 } %4, 0
- tail call void @__clang_call_terminate(i8* %5) #3
+ %4 = landingpad { ptr, i32 }
+ catch ptr null
+ %5 = extractvalue { ptr, i32 } %4, 0
+ tail call void @__clang_call_terminate(ptr %5) #3
unreachable
}
@@ -55,13 +55,13 @@ declare void @_Z3fooi(i32) #0
declare i32 @__gxx_personality_v0(...)
-declare i8* @__cxa_begin_catch(i8*)
+declare ptr @__cxa_begin_catch(ptr)
declare void @__cxa_end_catch()
; Function Attrs: noinline noreturn nounwind
-define linkonce_odr hidden void @__clang_call_terminate(i8*) #1 {
- %2 = tail call i8* @__cxa_begin_catch(i8* %0) #2
+define linkonce_odr hidden void @__clang_call_terminate(ptr) #1 {
+ %2 = tail call ptr @__cxa_begin_catch(ptr %0) #2
tail call void @_ZSt9terminatev() #3
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/big-endian-neon-bitconv.ll b/llvm/test/CodeGen/ARM/big-endian-neon-bitconv.ll
index 462d67518a4e4..6ad17839efef4 100644
--- a/llvm/test/CodeGen/ARM/big-endian-neon-bitconv.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-neon-bitconv.ll
@@ -15,346 +15,346 @@
; 64 bit conversions
-define void @conv_i64_to_v8i8( i64 %val, <8 x i8>* %store ) {
+define void @conv_i64_to_v8i8( i64 %val, ptr %store ) {
; CHECK-LABEL: conv_i64_to_v8i8:
; CHECK: vrev64.8
%v = bitcast i64 %val to <8 x i8>
- %w = load <8 x i8>, <8 x i8>* @v8i8
+ %w = load <8 x i8>, ptr @v8i8
%a = add <8 x i8> %v, %w
- store <8 x i8> %a, <8 x i8>* %store
+ store <8 x i8> %a, ptr %store
ret void
}
-define void @conv_v8i8_to_i64( <8 x i8>* %load, <8 x i8>* %store ) {
+define void @conv_v8i8_to_i64( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v8i8_to_i64:
; CHECK: vrev64.8
- %v = load <8 x i8>, <8 x i8>* %load
- %w = load <8 x i8>, <8 x i8>* @v8i8
+ %v = load <8 x i8>, ptr %load
+ %w = load <8 x i8>, ptr @v8i8
%a = add <8 x i8> %v, %w
%f = bitcast <8 x i8> %a to i64
- call void @conv_i64_to_v8i8( i64 %f, <8 x i8>* %store )
+ call void @conv_i64_to_v8i8( i64 %f, ptr %store )
ret void
}
-define void @conv_i64_to_v4i16( i64 %val, <4 x i16>* %store ) {
+define void @conv_i64_to_v4i16( i64 %val, ptr %store ) {
; CHECK-LABEL: conv_i64_to_v4i16:
; CHECK: vrev64.16
%v = bitcast i64 %val to <4 x i16>
- %w = load <4 x i16>, <4 x i16>* @v4i16
+ %w = load <4 x i16>, ptr @v4i16
%a = add <4 x i16> %v, %w
- store <4 x i16> %a, <4 x i16>* %store
+ store <4 x i16> %a, ptr %store
ret void
}
-define void @conv_v4i16_to_i64( <4 x i16>* %load, <4 x i16>* %store ) {
+define void @conv_v4i16_to_i64( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v4i16_to_i64:
; CHECK: vrev64.16
- %v = load <4 x i16>, <4 x i16>* %load
- %w = load <4 x i16>, <4 x i16>* @v4i16
+ %v = load <4 x i16>, ptr %load
+ %w = load <4 x i16>, ptr @v4i16
%a = add <4 x i16> %v, %w
%f = bitcast <4 x i16> %a to i64
- call void @conv_i64_to_v4i16( i64 %f, <4 x i16>* %store )
+ call void @conv_i64_to_v4i16( i64 %f, ptr %store )
ret void
}
-define void @conv_i64_to_v2i32( i64 %val, <2 x i32>* %store ) {
+define void @conv_i64_to_v2i32( i64 %val, ptr %store ) {
; CHECK-LABEL: conv_i64_to_v2i32:
; CHECK: vrev64.32
%v = bitcast i64 %val to <2 x i32>
- %w = load <2 x i32>, <2 x i32>* @v2i32
+ %w = load <2 x i32>, ptr @v2i32
%a = add <2 x i32> %v, %w
- store <2 x i32> %a, <2 x i32>* %store
+ store <2 x i32> %a, ptr %store
ret void
}
-define void @conv_v2i32_to_i64( <2 x i32>* %load, <2 x i32>* %store ) {
+define void @conv_v2i32_to_i64( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v2i32_to_i64:
; CHECK: vrev64.32
- %v = load <2 x i32>, <2 x i32>* %load
- %w = load <2 x i32>, <2 x i32>* @v2i32
+ %v = load <2 x i32>, ptr %load
+ %w = load <2 x i32>, ptr @v2i32
%a = add <2 x i32> %v, %w
%f = bitcast <2 x i32> %a to i64
- call void @conv_i64_to_v2i32( i64 %f, <2 x i32>* %store )
+ call void @conv_i64_to_v2i32( i64 %f, ptr %store )
ret void
}
-define void @conv_i64_to_v2f32( i64 %val, <2 x float>* %store ) {
+define void @conv_i64_to_v2f32( i64 %val, ptr %store ) {
; CHECK-LABEL: conv_i64_to_v2f32:
; CHECK: vrev64.32
%v = bitcast i64 %val to <2 x float>
- %w = load <2 x float>, <2 x float>* @v2f32
+ %w = load <2 x float>, ptr @v2f32
%a = fadd <2 x float> %v, %w
- store <2 x float> %a, <2 x float>* %store
+ store <2 x float> %a, ptr %store
ret void
}
-define void @conv_v2f32_to_i64( <2 x float>* %load, <2 x float>* %store ) {
+define void @conv_v2f32_to_i64( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v2f32_to_i64:
; CHECK: vrev64.32
- %v = load <2 x float>, <2 x float>* %load
- %w = load <2 x float>, <2 x float>* @v2f32
+ %v = load <2 x float>, ptr %load
+ %w = load <2 x float>, ptr @v2f32
%a = fadd <2 x float> %v, %w
%f = bitcast <2 x float> %a to i64
- call void @conv_i64_to_v2f32( i64 %f, <2 x float>* %store )
+ call void @conv_i64_to_v2f32( i64 %f, ptr %store )
ret void
}
-define void @conv_f64_to_v8i8( double %val, <8 x i8>* %store ) {
+define void @conv_f64_to_v8i8( double %val, ptr %store ) {
; CHECK-LABEL: conv_f64_to_v8i8:
; CHECK: vrev64.8
%v = bitcast double %val to <8 x i8>
- %w = load <8 x i8>, <8 x i8>* @v8i8
+ %w = load <8 x i8>, ptr @v8i8
%a = add <8 x i8> %v, %w
- store <8 x i8> %a, <8 x i8>* %store
+ store <8 x i8> %a, ptr %store
ret void
}
-define void @conv_v8i8_to_f64( <8 x i8>* %load, <8 x i8>* %store ) {
+define void @conv_v8i8_to_f64( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v8i8_to_f64:
; CHECK: vrev64.8
- %v = load <8 x i8>, <8 x i8>* %load
- %w = load <8 x i8>, <8 x i8>* @v8i8
+ %v = load <8 x i8>, ptr %load
+ %w = load <8 x i8>, ptr @v8i8
%a = add <8 x i8> %v, %w
%f = bitcast <8 x i8> %a to double
- call void @conv_f64_to_v8i8( double %f, <8 x i8>* %store )
+ call void @conv_f64_to_v8i8( double %f, ptr %store )
ret void
}
-define void @conv_f64_to_v4i16( double %val, <4 x i16>* %store ) {
+define void @conv_f64_to_v4i16( double %val, ptr %store ) {
; CHECK-LABEL: conv_f64_to_v4i16:
; CHECK: vrev64.16
%v = bitcast double %val to <4 x i16>
- %w = load <4 x i16>, <4 x i16>* @v4i16
+ %w = load <4 x i16>, ptr @v4i16
%a = add <4 x i16> %v, %w
- store <4 x i16> %a, <4 x i16>* %store
+ store <4 x i16> %a, ptr %store
ret void
}
-define void @conv_v4i16_to_f64( <4 x i16>* %load, <4 x i16>* %store ) {
+define void @conv_v4i16_to_f64( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v4i16_to_f64:
; CHECK: vrev64.16
- %v = load <4 x i16>, <4 x i16>* %load
- %w = load <4 x i16>, <4 x i16>* @v4i16
+ %v = load <4 x i16>, ptr %load
+ %w = load <4 x i16>, ptr @v4i16
%a = add <4 x i16> %v, %w
%f = bitcast <4 x i16> %a to double
- call void @conv_f64_to_v4i16( double %f, <4 x i16>* %store )
+ call void @conv_f64_to_v4i16( double %f, ptr %store )
ret void
}
-define void @conv_f64_to_v2i32( double %val, <2 x i32>* %store ) {
+define void @conv_f64_to_v2i32( double %val, ptr %store ) {
; CHECK-LABEL: conv_f64_to_v2i32:
; CHECK: vrev64.32
%v = bitcast double %val to <2 x i32>
- %w = load <2 x i32>, <2 x i32>* @v2i32
+ %w = load <2 x i32>, ptr @v2i32
%a = add <2 x i32> %v, %w
- store <2 x i32> %a, <2 x i32>* %store
+ store <2 x i32> %a, ptr %store
ret void
}
-define void @conv_v2i32_to_f64( <2 x i32>* %load, <2 x i32>* %store ) {
+define void @conv_v2i32_to_f64( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v2i32_to_f64:
; CHECK: vrev64.32
- %v = load <2 x i32>, <2 x i32>* %load
- %w = load <2 x i32>, <2 x i32>* @v2i32
+ %v = load <2 x i32>, ptr %load
+ %w = load <2 x i32>, ptr @v2i32
%a = add <2 x i32> %v, %w
%f = bitcast <2 x i32> %a to double
- call void @conv_f64_to_v2i32( double %f, <2 x i32>* %store )
+ call void @conv_f64_to_v2i32( double %f, ptr %store )
ret void
}
-define void @conv_f64_to_v2f32( double %val, <2 x float>* %store ) {
+define void @conv_f64_to_v2f32( double %val, ptr %store ) {
; CHECK-LABEL: conv_f64_to_v2f32:
; CHECK: vrev64.32
%v = bitcast double %val to <2 x float>
- %w = load <2 x float>, <2 x float>* @v2f32
+ %w = load <2 x float>, ptr @v2f32
%a = fadd <2 x float> %v, %w
- store <2 x float> %a, <2 x float>* %store
+ store <2 x float> %a, ptr %store
ret void
}
-define void @conv_v2f32_to_f64( <2 x float>* %load, <2 x float>* %store ) {
+define void @conv_v2f32_to_f64( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v2f32_to_f64:
; CHECK: vrev64.32
- %v = load <2 x float>, <2 x float>* %load
- %w = load <2 x float>, <2 x float>* @v2f32
+ %v = load <2 x float>, ptr %load
+ %w = load <2 x float>, ptr @v2f32
%a = fadd <2 x float> %v, %w
%f = bitcast <2 x float> %a to double
- call void @conv_f64_to_v2f32( double %f, <2 x float>* %store )
+ call void @conv_f64_to_v2f32( double %f, ptr %store )
ret void
}
; 128 bit conversions
-define void @conv_i128_to_v16i8( i128 %val, <16 x i8>* %store ) {
+define void @conv_i128_to_v16i8( i128 %val, ptr %store ) {
; CHECK-LABEL: conv_i128_to_v16i8:
; CHECK: vrev32.8
%v = bitcast i128 %val to <16 x i8>
- %w = load <16 x i8>, <16 x i8>* @v16i8
+ %w = load <16 x i8>, ptr @v16i8
%a = add <16 x i8> %v, %w
- store <16 x i8> %a, <16 x i8>* %store
+ store <16 x i8> %a, ptr %store
ret void
}
-define void @conv_v16i8_to_i128( <16 x i8>* %load, <16 x i8>* %store ) {
+define void @conv_v16i8_to_i128( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v16i8_to_i128:
; CHECK: vrev32.8
- %v = load <16 x i8>, <16 x i8>* %load
- %w = load <16 x i8>, <16 x i8>* @v16i8
+ %v = load <16 x i8>, ptr %load
+ %w = load <16 x i8>, ptr @v16i8
%a = add <16 x i8> %v, %w
%f = bitcast <16 x i8> %a to i128
- call void @conv_i128_to_v16i8( i128 %f, <16 x i8>* %store )
+ call void @conv_i128_to_v16i8( i128 %f, ptr %store )
ret void
}
-define void @conv_i128_to_v8i16( i128 %val, <8 x i16>* %store ) {
+define void @conv_i128_to_v8i16( i128 %val, ptr %store ) {
; CHECK-LABEL: conv_i128_to_v8i16:
; CHECK: vrev32.16
%v = bitcast i128 %val to <8 x i16>
- %w = load <8 x i16>, <8 x i16>* @v8i16
+ %w = load <8 x i16>, ptr @v8i16
%a = add <8 x i16> %v, %w
- store <8 x i16> %a, <8 x i16>* %store
+ store <8 x i16> %a, ptr %store
ret void
}
-define void @conv_v8i16_to_i128( <8 x i16>* %load, <8 x i16>* %store ) {
+define void @conv_v8i16_to_i128( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v8i16_to_i128:
; CHECK: vrev32.16
- %v = load <8 x i16>, <8 x i16>* %load
- %w = load <8 x i16>, <8 x i16>* @v8i16
+ %v = load <8 x i16>, ptr %load
+ %w = load <8 x i16>, ptr @v8i16
%a = add <8 x i16> %v, %w
%f = bitcast <8 x i16> %a to i128
- call void @conv_i128_to_v8i16( i128 %f, <8 x i16>* %store )
+ call void @conv_i128_to_v8i16( i128 %f, ptr %store )
ret void
}
-define void @conv_i128_to_v4i32( i128 %val, <4 x i32>* %store ) {
+define void @conv_i128_to_v4i32( i128 %val, ptr %store ) {
; CHECK-LABEL: conv_i128_to_v4i32:
; CHECK: vrev64.32
%v = bitcast i128 %val to <4 x i32>
- %w = load <4 x i32>, <4 x i32>* @v4i32
+ %w = load <4 x i32>, ptr @v4i32
%a = add <4 x i32> %v, %w
- store <4 x i32> %a, <4 x i32>* %store
+ store <4 x i32> %a, ptr %store
ret void
}
-define void @conv_v4i32_to_i128( <4 x i32>* %load, <4 x i32>* %store ) {
+define void @conv_v4i32_to_i128( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v4i32_to_i128:
; CHECK: vrev64.32
- %v = load <4 x i32>, <4 x i32>* %load
- %w = load <4 x i32>, <4 x i32>* @v4i32
+ %v = load <4 x i32>, ptr %load
+ %w = load <4 x i32>, ptr @v4i32
%a = add <4 x i32> %v, %w
%f = bitcast <4 x i32> %a to i128
- call void @conv_i128_to_v4i32( i128 %f, <4 x i32>* %store )
+ call void @conv_i128_to_v4i32( i128 %f, ptr %store )
ret void
}
-define void @conv_i128_to_v4f32( i128 %val, <4 x float>* %store ) {
+define void @conv_i128_to_v4f32( i128 %val, ptr %store ) {
; CHECK-LABEL: conv_i128_to_v4f32:
; CHECK: vrev64.32
%v = bitcast i128 %val to <4 x float>
- %w = load <4 x float>, <4 x float>* @v4f32
+ %w = load <4 x float>, ptr @v4f32
%a = fadd <4 x float> %v, %w
- store <4 x float> %a, <4 x float>* %store
+ store <4 x float> %a, ptr %store
ret void
}
-define void @conv_v4f32_to_i128( <4 x float>* %load, <4 x float>* %store ) {
+define void @conv_v4f32_to_i128( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v4f32_to_i128:
; CHECK: vrev64.32
- %v = load <4 x float>, <4 x float>* %load
- %w = load <4 x float>, <4 x float>* @v4f32
+ %v = load <4 x float>, ptr %load
+ %w = load <4 x float>, ptr @v4f32
%a = fadd <4 x float> %v, %w
%f = bitcast <4 x float> %a to i128
- call void @conv_i128_to_v4f32( i128 %f, <4 x float>* %store )
+ call void @conv_i128_to_v4f32( i128 %f, ptr %store )
ret void
}
-define void @conv_f128_to_v2f64( fp128 %val, <2 x double>* %store ) {
+define void @conv_f128_to_v2f64( fp128 %val, ptr %store ) {
; CHECK-LABEL: conv_f128_to_v2f64:
; CHECK: vrev64.32
%v = bitcast fp128 %val to <2 x double>
- %w = load <2 x double>, <2 x double>* @v2f64
+ %w = load <2 x double>, ptr @v2f64
%a = fadd <2 x double> %v, %w
- store <2 x double> %a, <2 x double>* %store
+ store <2 x double> %a, ptr %store
ret void
}
-define void @conv_v2f64_to_f128( <2 x double>* %load, <2 x double>* %store ) {
+define void @conv_v2f64_to_f128( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v2f64_to_f128:
; CHECK: vrev64.32
- %v = load <2 x double>, <2 x double>* %load
- %w = load <2 x double>, <2 x double>* @v2f64
+ %v = load <2 x double>, ptr %load
+ %w = load <2 x double>, ptr @v2f64
%a = fadd <2 x double> %v, %w
%f = bitcast <2 x double> %a to fp128
- call void @conv_f128_to_v2f64( fp128 %f, <2 x double>* %store )
+ call void @conv_f128_to_v2f64( fp128 %f, ptr %store )
ret void
}
-define void @conv_f128_to_v16i8( fp128 %val, <16 x i8>* %store ) {
+define void @conv_f128_to_v16i8( fp128 %val, ptr %store ) {
; CHECK-LABEL: conv_f128_to_v16i8:
; CHECK: vrev32.8
%v = bitcast fp128 %val to <16 x i8>
- %w = load <16 x i8>, <16 x i8>* @v16i8
+ %w = load <16 x i8>, ptr @v16i8
%a = add <16 x i8> %v, %w
- store <16 x i8> %a, <16 x i8>* %store
+ store <16 x i8> %a, ptr %store
ret void
}
-define void @conv_v16i8_to_f128( <16 x i8>* %load, <16 x i8>* %store ) {
+define void @conv_v16i8_to_f128( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v16i8_to_f128:
; CHECK: vrev32.8
- %v = load <16 x i8>, <16 x i8>* %load
- %w = load <16 x i8>, <16 x i8>* @v16i8
+ %v = load <16 x i8>, ptr %load
+ %w = load <16 x i8>, ptr @v16i8
%a = add <16 x i8> %v, %w
%f = bitcast <16 x i8> %a to fp128
- call void @conv_f128_to_v16i8( fp128 %f, <16 x i8>* %store )
+ call void @conv_f128_to_v16i8( fp128 %f, ptr %store )
ret void
}
-define void @conv_f128_to_v8i16( fp128 %val, <8 x i16>* %store ) {
+define void @conv_f128_to_v8i16( fp128 %val, ptr %store ) {
; CHECK-LABEL: conv_f128_to_v8i16:
; CHECK: vrev32.16
%v = bitcast fp128 %val to <8 x i16>
- %w = load <8 x i16>, <8 x i16>* @v8i16
+ %w = load <8 x i16>, ptr @v8i16
%a = add <8 x i16> %v, %w
- store <8 x i16> %a, <8 x i16>* %store
+ store <8 x i16> %a, ptr %store
ret void
}
-define void @conv_v8i16_to_f128( <8 x i16>* %load, <8 x i16>* %store ) {
+define void @conv_v8i16_to_f128( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v8i16_to_f128:
; CHECK: vrev32.16
- %v = load <8 x i16>, <8 x i16>* %load
- %w = load <8 x i16>, <8 x i16>* @v8i16
+ %v = load <8 x i16>, ptr %load
+ %w = load <8 x i16>, ptr @v8i16
%a = add <8 x i16> %v, %w
%f = bitcast <8 x i16> %a to fp128
- call void @conv_f128_to_v8i16( fp128 %f, <8 x i16>* %store )
+ call void @conv_f128_to_v8i16( fp128 %f, ptr %store )
ret void
}
-define void @conv_f128_to_v4f32( fp128 %val, <4 x float>* %store ) {
+define void @conv_f128_to_v4f32( fp128 %val, ptr %store ) {
; CHECK-LABEL: conv_f128_to_v4f32:
; CHECK: vrev64.32
%v = bitcast fp128 %val to <4 x float>
- %w = load <4 x float>, <4 x float>* @v4f32
+ %w = load <4 x float>, ptr @v4f32
%a = fadd <4 x float> %v, %w
- store <4 x float> %a, <4 x float>* %store
+ store <4 x float> %a, ptr %store
ret void
}
-define void @conv_v4f32_to_f128( <4 x float>* %load, <4 x float>* %store ) {
+define void @conv_v4f32_to_f128( ptr %load, ptr %store ) {
; CHECK-LABEL: conv_v4f32_to_f128:
; CHECK: vrev64.32
- %v = load <4 x float>, <4 x float>* %load
- %w = load <4 x float>, <4 x float>* @v4f32
+ %v = load <4 x float>, ptr %load
+ %w = load <4 x float>, ptr @v4f32
%a = fadd <4 x float> %v, %w
%f = bitcast <4 x float> %a to fp128
- call void @conv_f128_to_v4f32( fp128 %f, <4 x float>* %store )
+ call void @conv_f128_to_v4f32( fp128 %f, ptr %store )
ret void
}
-define void @arg_v4i32( <4 x i32> %var, <4 x i32>* %store ) {
+define void @arg_v4i32( <4 x i32> %var, ptr %store ) {
; CHECK-LABEL: arg_v4i32:
; CHECK: vmov [[REG2:d[0-9]+]], r3, r2
; CHECK: vmov [[REG1:d[0-9]+]], r1, r0
@@ -362,11 +362,11 @@ define void @arg_v4i32( <4 x i32> %var, <4 x i32>* %store ) {
; CHECK-HARD-LABEL: arg_v4i32:
; CHECK-HARD-NOT: vmov
; CHECK-HARD: vst1.64 {d0, d1}
- store <4 x i32> %var, <4 x i32>* %store
+ store <4 x i32> %var, ptr %store
ret void
}
-define void @arg_v8i16( <8 x i16> %var, <8 x i16>* %store ) {
+define void @arg_v8i16( <8 x i16> %var, ptr %store ) {
; CHECK-LABEL: arg_v8i16:
; CHECK: vmov [[REG2:d[0-9]+]], r3, r2
; CHECK: vmov [[REG1:d[0-9]+]], r1, r0
@@ -374,11 +374,11 @@ define void @arg_v8i16( <8 x i16> %var, <8 x i16>* %store ) {
; CHECK-HARD-LABEL: arg_v8i16:
; CHECK-HARD-NOT: vmov
; CHECK-HARD: vst1.64 {d0, d1}
- store <8 x i16> %var, <8 x i16>* %store
+ store <8 x i16> %var, ptr %store
ret void
}
-define void @arg_v16i8( <16 x i8> %var, <16 x i8>* %store ) {
+define void @arg_v16i8( <16 x i8> %var, ptr %store ) {
; CHECK-LABEL: arg_v16i8:
; CHECK: vmov [[REG2:d[0-9]+]], r3, r2
; CHECK: vmov [[REG1:d[0-9]+]], r1, r0
@@ -386,7 +386,7 @@ define void @arg_v16i8( <16 x i8> %var, <16 x i8>* %store ) {
; CHECK-HARD-LABEL: arg_v16i8:
; CHECK-HARD-NOT: vmov
; CHECK-HARD: vst1.64 {d0, d1}
- store <16 x i8> %var, <16 x i8>* %store
+ store <16 x i8> %var, ptr %store
ret void
}
diff --git a/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll b/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll
index f8542b708b8ad..6645cbe2e1bc0 100644
--- a/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple armeb-eabi -mattr v7,neon -o - | FileCheck %s
-define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ) {
+define void @vector_ext_2i8_to_2i64( ptr %loadaddr, ptr %storeaddr ) {
; CHECK-LABEL: vector_ext_2i8_to_2i64:
; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
@@ -9,13 +9,13 @@ define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr
; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
; CHECK-NEXT: bx lr
- %1 = load <2 x i8>, <2 x i8>* %loadaddr
+ %1 = load <2 x i8>, ptr %loadaddr
%2 = zext <2 x i8> %1 to <2 x i64>
- store <2 x i64> %2, <2 x i64>* %storeaddr
+ store <2 x i64> %2, ptr %storeaddr
ret void
}
-define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeaddr ) {
+define void @vector_ext_2i16_to_2i64( ptr %loadaddr, ptr %storeaddr ) {
; CHECK-LABEL: vector_ext_2i16_to_2i64:
; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
@@ -23,14 +23,14 @@ define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeadd
; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
; CHECK-NEXT: bx lr
- %1 = load <2 x i16>, <2 x i16>* %loadaddr
+ %1 = load <2 x i16>, ptr %loadaddr
%2 = zext <2 x i16> %1 to <2 x i64>
- store <2 x i64> %2, <2 x i64>* %storeaddr
+ store <2 x i64> %2, ptr %storeaddr
ret void
}
-define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr ) {
+define void @vector_ext_2i8_to_2i32( ptr %loadaddr, ptr %storeaddr ) {
; CHECK-LABEL: vector_ext_2i8_to_2i32:
; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
@@ -39,13 +39,13 @@ define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr
; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
; CHECK-NEXT: vstr [[REG]], [r1]
; CHECK-NEXT: bx lr
- %1 = load <2 x i8>, <2 x i8>* %loadaddr
+ %1 = load <2 x i8>, ptr %loadaddr
%2 = zext <2 x i8> %1 to <2 x i32>
- store <2 x i32> %2, <2 x i32>* %storeaddr
+ store <2 x i32> %2, ptr %storeaddr
ret void
}
-define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeaddr ) {
+define void @vector_ext_2i16_to_2i32( ptr %loadaddr, ptr %storeaddr ) {
; CHECK-LABEL: vector_ext_2i16_to_2i32:
; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
@@ -53,13 +53,13 @@ define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeadd
; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
; CHECK-NEXT: vstr [[REG]], [r1]
; CHECK-NEXT: bx lr
- %1 = load <2 x i16>, <2 x i16>* %loadaddr
+ %1 = load <2 x i16>, ptr %loadaddr
%2 = zext <2 x i16> %1 to <2 x i32>
- store <2 x i32> %2, <2 x i32>* %storeaddr
+ store <2 x i32> %2, ptr %storeaddr
ret void
}
-define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr ) {
+define void @vector_ext_2i8_to_2i16( ptr %loadaddr, ptr %storeaddr ) {
; CHECK-LABEL: vector_ext_2i8_to_2i16:
; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
@@ -70,13 +70,13 @@ define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr
; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}}
; CHECK-NEXT: vst1.32 {[[REG]][0]}, [r1:32]
; CHECK-NEXT: bx lr
- %1 = load <2 x i8>, <2 x i8>* %loadaddr
+ %1 = load <2 x i8>, ptr %loadaddr
%2 = zext <2 x i8> %1 to <2 x i16>
- store <2 x i16> %2, <2 x i16>* %storeaddr
+ store <2 x i16> %2, ptr %storeaddr
ret void
}
-define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr ) {
+define void @vector_ext_4i8_to_4i32( ptr %loadaddr, ptr %storeaddr ) {
; CHECK-LABEL: vector_ext_4i8_to_4i32:
; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]
@@ -85,13 +85,13 @@ define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
; CHECK-NEXT: bx lr
- %1 = load <4 x i8>, <4 x i8>* %loadaddr
+ %1 = load <4 x i8>, ptr %loadaddr
%2 = zext <4 x i8> %1 to <4 x i32>
- store <4 x i32> %2, <4 x i32>* %storeaddr
+ store <4 x i32> %2, ptr %storeaddr
ret void
}
-define void @vector_ext_4i8_to_4i16( <4 x i8>* %loadaddr, <4 x i16>* %storeaddr ) {
+define void @vector_ext_4i8_to_4i16( ptr %loadaddr, ptr %storeaddr ) {
; CHECK-LABEL: vector_ext_4i8_to_4i16:
; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]
@@ -99,8 +99,8 @@ define void @vector_ext_4i8_to_4i16( <4 x i8>* %loadaddr, <4 x i16>* %storeaddr
; CHECK-NEXT: vrev64.16 [[REG]], [[REG]]
; CHECK-NEXT: vstr [[REG]], [r1]
; CHECK-NEXT: bx lr
- %1 = load <4 x i8>, <4 x i8>* %loadaddr
+ %1 = load <4 x i8>, ptr %loadaddr
%2 = zext <4 x i8> %1 to <4 x i16>
- store <4 x i16> %2, <4 x i16>* %storeaddr
+ store <4 x i16> %2, ptr %storeaddr
ret void
}
diff --git a/llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll b/llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll
index 96b6f3237df10..4026495a0f2b4 100644
--- a/llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple armeb-eabi -mattr=armv8.2-a,neon,fullfp16 -target-abi=aapcs-gnu -float-abi hard -o - %s | FileCheck %s
;64 bit conversions to v4f16
-define void @conv_i64_to_v4f16( i64 %val, <4 x half>* %store ) {
+define void @conv_i64_to_v4f16( i64 %val, ptr %store ) {
; CHECK-LABEL: conv_i64_to_v4f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov d16, r1, r0
@@ -15,13 +15,13 @@ define void @conv_i64_to_v4f16( i64 %val, <4 x half>* %store ) {
; CHECK-NEXT: bx lr
entry:
%v = bitcast i64 %val to <4 x half>
- %w = load <4 x half>, <4 x half>* %store
+ %w = load <4 x half>, ptr %store
%a = fadd <4 x half> %v, %w
- store <4 x half> %a, <4 x half>* %store
+ store <4 x half> %a, ptr %store
ret void
}
-define void @conv_f64_to_v4f16( double %val, <4 x half>* %store ) {
+define void @conv_f64_to_v4f16( double %val, ptr %store ) {
; CHECK-LABEL: conv_f64_to_v4f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, [r0]
@@ -33,13 +33,13 @@ define void @conv_f64_to_v4f16( double %val, <4 x half>* %store ) {
; CHECK-NEXT: bx lr
entry:
%v = bitcast double %val to <4 x half>
- %w = load <4 x half>, <4 x half>* %store
+ %w = load <4 x half>, ptr %store
%a = fadd <4 x half> %v, %w
- store <4 x half> %a, <4 x half>* %store
+ store <4 x half> %a, ptr %store
ret void
}
-define void @conv_v2f32_to_v4f16( <2 x float> %a, <4 x half>* %store ) {
+define void @conv_v2f32_to_v4f16( <2 x float> %a, ptr %store ) {
; CHECK-LABEL: conv_v2f32_to_v4f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, .LCPI2_0
@@ -61,13 +61,13 @@ define void @conv_v2f32_to_v4f16( <2 x float> %a, <4 x half>* %store ) {
entry:
%c = fadd <2 x float> %a, <float -1.0, float 1.0>
%v = bitcast <2 x float> %c to <4 x half>
- %w = load <4 x half>, <4 x half>* %store
+ %w = load <4 x half>, ptr %store
%z = fadd <4 x half> %v, %w
- store <4 x half> %z, <4 x half>* %store
+ store <4 x half> %z, ptr %store
ret void
}
-define void @conv_v2i32_to_v4f16( <2 x i32> %a, <4 x half>* %store ) {
+define void @conv_v2i32_to_v4f16( <2 x i32> %a, ptr %store ) {
; CHECK-LABEL: conv_v2i32_to_v4f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, .LCPI3_0
@@ -89,13 +89,13 @@ define void @conv_v2i32_to_v4f16( <2 x i32> %a, <4 x half>* %store ) {
entry:
%c = add <2 x i32> %a, <i32 1, i32 -1>
%v = bitcast <2 x i32> %c to <4 x half>
- %w = load <4 x half>, <4 x half>* %store
+ %w = load <4 x half>, ptr %store
%z = fadd <4 x half> %v, %w
- store <4 x half> %z, <4 x half>* %store
+ store <4 x half> %z, ptr %store
ret void
}
-define void @conv_v4i16_to_v4f16( <4 x i16> %a, <4 x half>* %store ) {
+define void @conv_v4i16_to_v4f16( <4 x i16> %a, ptr %store ) {
; CHECK-LABEL: conv_v4i16_to_v4f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i64 d16, #0xffff00000000ffff
@@ -111,13 +111,13 @@ define void @conv_v4i16_to_v4f16( <4 x i16> %a, <4 x half>* %store ) {
entry:
%c = add <4 x i16> %a, <i16 -1, i16 0, i16 0, i16 -1>
%v = bitcast <4 x i16> %c to <4 x half>
- %w = load <4 x half>, <4 x half>* %store
+ %w = load <4 x half>, ptr %store
%z = fadd <4 x half> %v, %w
- store <4 x half> %z, <4 x half>* %store
+ store <4 x half> %z, ptr %store
ret void
}
-define void @conv_v8i8_to_v4f16( <8 x i8> %a, <4 x half>* %store ) {
+define void @conv_v8i8_to_v4f16( <8 x i8> %a, ptr %store ) {
; CHECK-LABEL: conv_v8i8_to_v4f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i8 d16, #0x1
@@ -133,13 +133,13 @@ define void @conv_v8i8_to_v4f16( <8 x i8> %a, <4 x half>* %store ) {
entry:
%c = add <8 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
%v = bitcast <8 x i8> %c to <4 x half>
- %w = load <4 x half>, <4 x half>* %store
+ %w = load <4 x half>, ptr %store
%z = fadd <4 x half> %v, %w
- store <4 x half> %z, <4 x half>* %store
+ store <4 x half> %z, ptr %store
ret void
}
-define void @conv_v2i64_to_v8f16( <2 x i64> %val, <8 x half>* %store ) {
+define void @conv_v2i64_to_v8f16( <2 x i64> %val, ptr %store ) {
; CHECK-LABEL: conv_v2i64_to_v8f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -162,12 +162,12 @@ define void @conv_v2i64_to_v8f16( <2 x i64> %val, <8 x half>* %store ) {
entry:
%v = add <2 x i64> %val, <i64 1, i64 -1>
%v1 = bitcast <2 x i64> %v to <8 x half>
- %w = load <8 x half>, <8 x half>* %store
+ %w = load <8 x half>, ptr %store
%a = fadd <8 x half> %v1, %w
- store <8 x half> %a, <8 x half>* %store
+ store <8 x half> %a, ptr %store
ret void
}
-define void @conv_v2f64_to_v8f16( <2 x double> %val, <8 x half>* %store ) {
+define void @conv_v2f64_to_v8f16( <2 x double> %val, ptr %store ) {
; CHECK-LABEL: conv_v2f64_to_v8f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f64 d16, #-1.000000e+00
@@ -184,13 +184,13 @@ define void @conv_v2f64_to_v8f16( <2 x double> %val, <8 x half>* %store ) {
entry:
%v = fadd <2 x double> %val, <double 1.0, double -1.0>
%v1 = bitcast <2 x double> %v to <8 x half>
- %w = load <8 x half>, <8 x half>* %store
+ %w = load <8 x half>, ptr %store
%a = fadd <8 x half> %v1, %w
- store <8 x half> %a, <8 x half>* %store
+ store <8 x half> %a, ptr %store
ret void
}
-define void @conv_v4f32_to_v8f16( <4 x float> %a, <8 x half>* %store ) {
+define void @conv_v4f32_to_v8f16( <4 x float> %a, ptr %store ) {
; CHECK-LABEL: conv_v4f32_to_v8f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: adr r1, .LCPI8_0
@@ -215,13 +215,13 @@ define void @conv_v4f32_to_v8f16( <4 x float> %a, <8 x half>* %store ) {
entry:
%c = fadd <4 x float> %a, <float -1.0, float 1.0, float -1.0, float 1.0>
%v = bitcast <4 x float> %c to <8 x half>
- %w = load <8 x half>, <8 x half>* %store
+ %w = load <8 x half>, ptr %store
%z = fadd <8 x half> %v, %w
- store <8 x half> %z, <8 x half>* %store
+ store <8 x half> %z, ptr %store
ret void
}
-define void @conv_v4i32_to_v8f16( <4 x i32> %a, <8 x half>* %store ) {
+define void @conv_v4i32_to_v8f16( <4 x i32> %a, ptr %store ) {
; CHECK-LABEL: conv_v4i32_to_v8f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: adr r1, .LCPI9_0
@@ -246,13 +246,13 @@ define void @conv_v4i32_to_v8f16( <4 x i32> %a, <8 x half>* %store ) {
entry:
%c = add <4 x i32> %a, <i32 -1, i32 1, i32 -1, i32 1>
%v = bitcast <4 x i32> %c to <8 x half>
- %w = load <8 x half>, <8 x half>* %store
+ %w = load <8 x half>, ptr %store
%z = fadd <8 x half> %v, %w
- store <8 x half> %z, <8 x half>* %store
+ store <8 x half> %z, ptr %store
ret void
}
-define void @conv_v8i16_to_v8f16( <8 x i16> %a, <8 x half>* %store ) {
+define void @conv_v8i16_to_v8f16( <8 x i16> %a, ptr %store ) {
; CHECK-LABEL: conv_v8i16_to_v8f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: adr r1, .LCPI10_0
@@ -280,13 +280,13 @@ define void @conv_v8i16_to_v8f16( <8 x i16> %a, <8 x half>* %store ) {
entry:
%c = add <8 x i16> %a, <i16 -1, i16 1, i16 0, i16 7, i16 -1, i16 1, i16 0, i16 7>
%v = bitcast <8 x i16> %c to <8 x half>
- %w = load <8 x half>, <8 x half>* %store
+ %w = load <8 x half>, ptr %store
%z = fadd <8 x half> %v, %w
- store <8 x half> %z, <8 x half>* %store
+ store <8 x half> %z, ptr %store
ret void
}
-define void @conv_v16i8_to_v8f16( <16 x i8> %a, <8 x half>* %store ) {
+define void @conv_v16i8_to_v8f16( <16 x i8> %a, ptr %store ) {
; CHECK-LABEL: conv_v16i8_to_v8f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vrev64.8 q8, q0
@@ -302,13 +302,13 @@ define void @conv_v16i8_to_v8f16( <16 x i8> %a, <8 x half>* %store ) {
entry:
%c = add <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
%v = bitcast <16 x i8> %c to <8 x half>
- %w = load <8 x half>, <8 x half>* %store
+ %w = load <8 x half>, ptr %store
%z = fadd <8 x half> %v, %w
- store <8 x half> %z, <8 x half>* %store
+ store <8 x half> %z, ptr %store
ret void
}
-define void @conv_v4f16_to_i64( <4 x half> %a, i64* %store ) {
+define void @conv_v4f16_to_i64( <4 x half> %a, ptr %store ) {
; CHECK-LABEL: conv_v4f16_to_i64:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, .LCPI12_0
@@ -333,11 +333,11 @@ entry:
%z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>
%y = bitcast <4 x half> %z to i64
%w = add i64 %y, -1
- store i64 %w, i64* %store
+ store i64 %w, ptr %store
ret void
}
-define void @conv_v4f16_to_f64( <4 x half> %a, double* %store ) {
+define void @conv_v4f16_to_f64( <4 x half> %a, ptr %store ) {
; CHECK-LABEL: conv_v4f16_to_f64:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, .LCPI13_0
@@ -360,11 +360,11 @@ entry:
%z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>
%y = bitcast <4 x half> %z to double
%w = fadd double %y, -1.0
- store double %w, double* %store
+ store double %w, ptr %store
ret void
}
-define void @conv_v4f16_to_v2i32( <4 x half> %a, <2 x i32>* %store ) {
+define void @conv_v4f16_to_v2i32( <4 x half> %a, ptr %store ) {
; CHECK-LABEL: conv_v4f16_to_v2i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, .LCPI14_0
@@ -392,11 +392,11 @@ entry:
%z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>
%y = bitcast <4 x half> %z to <2 x i32>
%w = add <2 x i32> %y, <i32 -1, i32 1>
- store <2 x i32> %w, <2 x i32>* %store
+ store <2 x i32> %w, ptr %store
ret void
}
-define void @conv_v4f16_to_v2f32( <4 x half> %a, <2 x float>* %store ) {
+define void @conv_v4f16_to_v2f32( <4 x half> %a, ptr %store ) {
; CHECK-LABEL: conv_v4f16_to_v2f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, .LCPI15_0
@@ -424,11 +424,11 @@ entry:
%z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>
%y = bitcast <4 x half> %z to <2 x float>
%w = fadd <2 x float> %y, <float -1.0, float 1.0>
- store <2 x float> %w, <2 x float>* %store
+ store <2 x float> %w, ptr %store
ret void
}
-define void @conv_v4f16_to_v4i16( <4 x half> %a, <4 x i16>* %store ) {
+define void @conv_v4f16_to_v4i16( <4 x half> %a, ptr %store ) {
; CHECK-LABEL: conv_v4f16_to_v4i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, .LCPI16_0
@@ -457,11 +457,11 @@ entry:
%z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>
%y = bitcast <4 x half> %z to <4 x i16>
%w = add <4 x i16> %y, <i16 -1, i16 1, i16 0, i16 7>
- store <4 x i16> %w, <4 x i16>* %store
+ store <4 x i16> %w, ptr %store
ret void
}
-define void @conv_v4f16_to_v8f8( <4 x half> %a, <8 x i8>* %store ) {
+define void @conv_v4f16_to_v8f8( <4 x half> %a, ptr %store ) {
; CHECK-LABEL: conv_v4f16_to_v8f8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, .LCPI17_0
@@ -485,11 +485,11 @@ entry:
%z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>
%y = bitcast <4 x half> %z to <8 x i8>
%w = add <8 x i8> %y, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
- store <8 x i8> %w, <8 x i8>* %store
+ store <8 x i8> %w, ptr %store
ret void
}
-define void @conv_v8f16_to_i128( <8 x half> %a, i128* %store ) {
+define void @conv_v8f16_to_i128( <8 x half> %a, ptr %store ) {
; CHECK-LABEL: conv_v8f16_to_i128:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r11, lr}
@@ -524,11 +524,11 @@ entry:
%z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>
%y = bitcast <8 x half> %z to i128
%w = add i128 %y, -1
- store i128 %w, i128* %store
+ store i128 %w, ptr %store
ret void
}
-define void @conv_v8f16_to_v2f64( <8 x half> %a, <2 x double>* %store ) {
+define void @conv_v8f16_to_v2f64( <8 x half> %a, ptr %store ) {
; CHECK-LABEL: conv_v8f16_to_v2f64:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: adr r1, .LCPI19_0
@@ -558,11 +558,11 @@ entry:
%z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>
%y = bitcast <8 x half> %z to <2 x double>
%w = fadd <2 x double> %y, <double -1.0, double 1.0>
- store <2 x double> %w, <2 x double>* %store
+ store <2 x double> %w, ptr %store
ret void
}
-define void @conv_v8f16_to_v4i32( <8 x half> %a, <4 x i32>* %store ) {
+define void @conv_v8f16_to_v4i32( <8 x half> %a, ptr %store ) {
; CHECK-LABEL: conv_v8f16_to_v4i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: adr r1, .LCPI20_0
@@ -598,11 +598,11 @@ entry:
%z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>
%y = bitcast <8 x half> %z to <4 x i32>
%w = add <4 x i32> %y, <i32 -1, i32 1, i32 -1, i32 1>
- store <4 x i32> %w, <4 x i32>* %store
+ store <4 x i32> %w, ptr %store
ret void
}
-define void @conv_v8f16_to_v4f32( <8 x half> %a, <4 x float>* %store ) {
+define void @conv_v8f16_to_v4f32( <8 x half> %a, ptr %store ) {
; CHECK-LABEL: conv_v8f16_to_v4f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: adr r1, .LCPI21_0
@@ -638,11 +638,11 @@ entry:
%z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>
%y = bitcast <8 x half> %z to <4 x float>
%w = fadd <4 x float> %y, <float -1.0, float 1.0, float -1.0, float 1.0>
- store <4 x float> %w, <4 x float>* %store
+ store <4 x float> %w, ptr %store
ret void
}
-define void @conv_v8f16_to_v8i16( <8 x half> %a, <8 x i16>* %store ) {
+define void @conv_v8f16_to_v8i16( <8 x half> %a, ptr %store ) {
; CHECK-LABEL: conv_v8f16_to_v8i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: adr r1, .LCPI22_0
@@ -681,11 +681,11 @@ entry:
%z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>
%y = bitcast <8 x half> %z to <8 x i16>
%w = add <8 x i16> %y, <i16 -1, i16 1, i16 0, i16 7, i16 -1, i16 1, i16 0, i16 7>
- store <8 x i16> %w, <8 x i16>* %store
+ store <8 x i16> %w, ptr %store
ret void
}
-define void @conv_v8f16_to_v8f8( <8 x half> %a, <16 x i8>* %store ) {
+define void @conv_v8f16_to_v8f8( <8 x half> %a, ptr %store ) {
; CHECK-LABEL: conv_v8f16_to_v8f8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: adr r1, .LCPI23_0
@@ -714,6 +714,6 @@ entry:
%z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>
%y = bitcast <8 x half> %z to <16 x i8>
%w = add <16 x i8> %y, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
- store <16 x i8> %w, <16 x i8>* %store
+ store <16 x i8> %w, ptr %store
ret void
}
diff --git a/llvm/test/CodeGen/ARM/big-endian-neon-trunc-store.ll b/llvm/test/CodeGen/ARM/big-endian-neon-trunc-store.ll
index cbfc46ed255b3..f44607473a6d6 100644
--- a/llvm/test/CodeGen/ARM/big-endian-neon-trunc-store.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-neon-trunc-store.ll
@@ -1,26 +1,26 @@
; RUN: llc < %s -mtriple armeb-eabi -mattr v7,neon -o - | FileCheck %s
-define void @vector_trunc_store_2i64_to_2i16( <2 x i64>* %loadaddr, <2 x i16>* %storeaddr ) {
+define void @vector_trunc_store_2i64_to_2i16( ptr %loadaddr, ptr %storeaddr ) {
; CHECK-LABEL: vector_trunc_store_2i64_to_2i16:
; CHECK: vmovn.i64 [[REG:d[0-9]+]]
; CHECK: vrev32.16 [[REG]], [[REG]]
; CHECK: vuzp.16 [[REG]], [[REG2:d[0-9]+]]
; CHECK: vrev32.16 [[REG]], [[REG2]]
- %1 = load <2 x i64>, <2 x i64>* %loadaddr
+ %1 = load <2 x i64>, ptr %loadaddr
%2 = trunc <2 x i64> %1 to <2 x i16>
- store <2 x i16> %2, <2 x i16>* %storeaddr
+ store <2 x i16> %2, ptr %storeaddr
ret void
}
-define void @vector_trunc_store_4i32_to_4i8( <4 x i32>* %loadaddr, <4 x i8>* %storeaddr ) {
+define void @vector_trunc_store_4i32_to_4i8( ptr %loadaddr, ptr %storeaddr ) {
; CHECK-LABEL: vector_trunc_store_4i32_to_4i8:
; CHECK: vmovn.i32 [[REG:d[0-9]+]]
; CHECK: vrev16.8 [[REG]], [[REG]]
; CHECK: vuzp.8 [[REG]], [[REG2:d[0-9]+]]
; CHECK: vrev32.8 [[REG]], [[REG2]]
- %1 = load <4 x i32>, <4 x i32>* %loadaddr
+ %1 = load <4 x i32>, ptr %loadaddr
%2 = trunc <4 x i32> %1 to <4 x i8>
- store <4 x i8> %2, <4 x i8>* %storeaddr
+ store <4 x i8> %2, ptr %storeaddr
ret void
}
diff --git a/llvm/test/CodeGen/ARM/big-endian-ret-f64.ll b/llvm/test/CodeGen/ARM/big-endian-ret-f64.ll
index f83e0864100ca..1af38abe166fa 100644
--- a/llvm/test/CodeGen/ARM/big-endian-ret-f64.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-ret-f64.ll
@@ -6,7 +6,7 @@ define double @fn() {
; CHECK: ldr r0, [sp]
; CHECK: ldr r1, [sp, #4]
%r = alloca double, align 8
- %1 = load double, double* %r, align 8
+ %1 = load double, ptr %r, align 8
ret double %1
}
diff --git a/llvm/test/CodeGen/ARM/big-endian-vector-caller.ll b/llvm/test/CodeGen/ARM/big-endian-vector-caller.ll
index 7aaf4ae0bfb53..773d0bf0245a5 100644
--- a/llvm/test/CodeGen/ARM/big-endian-vector-caller.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-vector-caller.ll
@@ -3,7 +3,7 @@
; RUN: llc -mtriple armeb-eabi -mattr v7,neon -float-abi hard %s -o - | FileCheck %s -check-prefix HARD
declare i64 @test_i64_f64_helper(double %p)
-define void @test_i64_f64(double* %p, i64* %q) {
+define void @test_i64_f64(ptr %p, ptr %q) {
; SOFT-LABEL: test_i64_f64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -30,16 +30,16 @@ define void @test_i64_f64(double* %p, i64* %q) {
; HARD-NEXT: adc r0, r0, r0
; HARD-NEXT: strd r0, r1, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load double, double* %p
+ %1 = load double, ptr %p
%2 = fadd double %1, %1
%3 = call i64 @test_i64_f64_helper(double %2)
%4 = add i64 %3, %3
- store i64 %4, i64* %q
+ store i64 %4, ptr %q
ret void
}
declare i64 @test_i64_v1i64_helper(<1 x i64> %p)
-define void @test_i64_v1i64(<1 x i64>* %p, i64* %q) {
+define void @test_i64_v1i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_i64_v1i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -66,16 +66,16 @@ define void @test_i64_v1i64(<1 x i64>* %p, i64* %q) {
; HARD-NEXT: adc r0, r0, r0
; HARD-NEXT: strd r0, r1, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <1 x i64>, <1 x i64>* %p
+ %1 = load <1 x i64>, ptr %p
%2 = add <1 x i64> %1, %1
%3 = call i64 @test_i64_v1i64_helper(<1 x i64> %2)
%4 = add i64 %3, %3
- store i64 %4, i64* %q
+ store i64 %4, ptr %q
ret void
}
declare i64 @test_i64_v2f32_helper(<2 x float> %p)
-define void @test_i64_v2f32(<2 x float>* %p, i64* %q) {
+define void @test_i64_v2f32(ptr %p, ptr %q) {
; SOFT-LABEL: test_i64_v2f32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -106,16 +106,16 @@ define void @test_i64_v2f32(<2 x float>* %p, i64* %q) {
; HARD-NEXT: adc r0, r0, r0
; HARD-NEXT: strd r0, r1, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x float>, <2 x float>* %p
+ %1 = load <2 x float>, ptr %p
%2 = fadd <2 x float> %1, %1
%3 = call i64 @test_i64_v2f32_helper(<2 x float> %2)
%4 = add i64 %3, %3
- store i64 %4, i64* %q
+ store i64 %4, ptr %q
ret void
}
declare i64 @test_i64_v2i32_helper(<2 x i32> %p)
-define void @test_i64_v2i32(<2 x i32>* %p, i64* %q) {
+define void @test_i64_v2i32(ptr %p, ptr %q) {
; SOFT-LABEL: test_i64_v2i32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -146,16 +146,16 @@ define void @test_i64_v2i32(<2 x i32>* %p, i64* %q) {
; HARD-NEXT: adc r0, r0, r0
; HARD-NEXT: strd r0, r1, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x i32>, <2 x i32>* %p
+ %1 = load <2 x i32>, ptr %p
%2 = add <2 x i32> %1, %1
%3 = call i64 @test_i64_v2i32_helper(<2 x i32> %2)
%4 = add i64 %3, %3
- store i64 %4, i64* %q
+ store i64 %4, ptr %q
ret void
}
declare i64 @test_i64_v4i16_helper(<4 x i16> %p)
-define void @test_i64_v4i16(<4 x i16>* %p, i64* %q) {
+define void @test_i64_v4i16(ptr %p, ptr %q) {
; SOFT-LABEL: test_i64_v4i16:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -186,16 +186,16 @@ define void @test_i64_v4i16(<4 x i16>* %p, i64* %q) {
; HARD-NEXT: adc r0, r0, r0
; HARD-NEXT: strd r0, r1, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x i16>, <4 x i16>* %p
+ %1 = load <4 x i16>, ptr %p
%2 = add <4 x i16> %1, %1
%3 = call i64 @test_i64_v4i16_helper(<4 x i16> %2)
%4 = add i64 %3, %3
- store i64 %4, i64* %q
+ store i64 %4, ptr %q
ret void
}
declare i64 @test_i64_v8i8_helper(<8 x i8> %p)
-define void @test_i64_v8i8(<8 x i8>* %p, i64* %q) {
+define void @test_i64_v8i8(ptr %p, ptr %q) {
; SOFT-LABEL: test_i64_v8i8:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -226,16 +226,16 @@ define void @test_i64_v8i8(<8 x i8>* %p, i64* %q) {
; HARD-NEXT: adc r0, r0, r0
; HARD-NEXT: strd r0, r1, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <8 x i8>, <8 x i8>* %p
+ %1 = load <8 x i8>, ptr %p
%2 = add <8 x i8> %1, %1
%3 = call i64 @test_i64_v8i8_helper(<8 x i8> %2)
%4 = add i64 %3, %3
- store i64 %4, i64* %q
+ store i64 %4, ptr %q
ret void
}
declare double @test_f64_i64_helper(i64 %p)
-define void @test_f64_i64(i64* %p, double* %q) {
+define void @test_f64_i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_f64_i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -262,16 +262,16 @@ define void @test_f64_i64(i64* %p, double* %q) {
; HARD-NEXT: vadd.f64 d16, d0, d0
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load i64, i64* %p
+ %1 = load i64, ptr %p
%2 = add i64 %1, %1
%3 = call double @test_f64_i64_helper(i64 %2)
%4 = fadd double %3, %3
- store double %4, double* %q
+ store double %4, ptr %q
ret void
}
declare double @test_f64_v1i64_helper(<1 x i64> %p)
-define void @test_f64_v1i64(<1 x i64>* %p, double* %q) {
+define void @test_f64_v1i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_f64_v1i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -297,16 +297,16 @@ define void @test_f64_v1i64(<1 x i64>* %p, double* %q) {
; HARD-NEXT: vadd.f64 d16, d0, d0
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <1 x i64>, <1 x i64>* %p
+ %1 = load <1 x i64>, ptr %p
%2 = add <1 x i64> %1, %1
%3 = call double @test_f64_v1i64_helper(<1 x i64> %2)
%4 = fadd double %3, %3
- store double %4, double* %q
+ store double %4, ptr %q
ret void
}
declare double @test_f64_v2f32_helper(<2 x float> %p)
-define void @test_f64_v2f32(<2 x float>* %p, double* %q) {
+define void @test_f64_v2f32(ptr %p, ptr %q) {
; SOFT-LABEL: test_f64_v2f32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -336,16 +336,16 @@ define void @test_f64_v2f32(<2 x float>* %p, double* %q) {
; HARD-NEXT: vadd.f64 d16, d0, d0
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x float>, <2 x float>* %p
+ %1 = load <2 x float>, ptr %p
%2 = fadd <2 x float> %1, %1
%3 = call double @test_f64_v2f32_helper(<2 x float> %2)
%4 = fadd double %3, %3
- store double %4, double* %q
+ store double %4, ptr %q
ret void
}
declare double @test_f64_v2i32_helper(<2 x i32> %p)
-define void @test_f64_v2i32(<2 x i32>* %p, double* %q) {
+define void @test_f64_v2i32(ptr %p, ptr %q) {
; SOFT-LABEL: test_f64_v2i32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -375,16 +375,16 @@ define void @test_f64_v2i32(<2 x i32>* %p, double* %q) {
; HARD-NEXT: vadd.f64 d16, d0, d0
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x i32>, <2 x i32>* %p
+ %1 = load <2 x i32>, ptr %p
%2 = add <2 x i32> %1, %1
%3 = call double @test_f64_v2i32_helper(<2 x i32> %2)
%4 = fadd double %3, %3
- store double %4, double* %q
+ store double %4, ptr %q
ret void
}
declare double @test_f64_v4i16_helper(<4 x i16> %p)
-define void @test_f64_v4i16(<4 x i16>* %p, double* %q) {
+define void @test_f64_v4i16(ptr %p, ptr %q) {
; SOFT-LABEL: test_f64_v4i16:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -414,16 +414,16 @@ define void @test_f64_v4i16(<4 x i16>* %p, double* %q) {
; HARD-NEXT: vadd.f64 d16, d0, d0
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x i16>, <4 x i16>* %p
+ %1 = load <4 x i16>, ptr %p
%2 = add <4 x i16> %1, %1
%3 = call double @test_f64_v4i16_helper(<4 x i16> %2)
%4 = fadd double %3, %3
- store double %4, double* %q
+ store double %4, ptr %q
ret void
}
declare double @test_f64_v8i8_helper(<8 x i8> %p)
-define void @test_f64_v8i8(<8 x i8>* %p, double* %q) {
+define void @test_f64_v8i8(ptr %p, ptr %q) {
; SOFT-LABEL: test_f64_v8i8:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -453,16 +453,16 @@ define void @test_f64_v8i8(<8 x i8>* %p, double* %q) {
; HARD-NEXT: vadd.f64 d16, d0, d0
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <8 x i8>, <8 x i8>* %p
+ %1 = load <8 x i8>, ptr %p
%2 = add <8 x i8> %1, %1
%3 = call double @test_f64_v8i8_helper(<8 x i8> %2)
%4 = fadd double %3, %3
- store double %4, double* %q
+ store double %4, ptr %q
ret void
}
declare <1 x i64> @test_v1i64_i64_helper(i64 %p)
-define void @test_v1i64_i64(i64* %p, <1 x i64>* %q) {
+define void @test_v1i64_i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v1i64_i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -489,16 +489,16 @@ define void @test_v1i64_i64(i64* %p, <1 x i64>* %q) {
; HARD-NEXT: vadd.i64 d16, d0, d0
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load i64, i64* %p
+ %1 = load i64, ptr %p
%2 = add i64 %1, %1
%3 = call <1 x i64> @test_v1i64_i64_helper(i64 %2)
%4 = add <1 x i64> %3, %3
- store <1 x i64> %4, <1 x i64>* %q
+ store <1 x i64> %4, ptr %q
ret void
}
declare <1 x i64> @test_v1i64_f64_helper(double %p)
-define void @test_v1i64_f64(double* %p, <1 x i64>* %q) {
+define void @test_v1i64_f64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v1i64_f64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -524,16 +524,16 @@ define void @test_v1i64_f64(double* %p, <1 x i64>* %q) {
; HARD-NEXT: vadd.i64 d16, d0, d0
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load double, double* %p
+ %1 = load double, ptr %p
%2 = fadd double %1, %1
%3 = call <1 x i64> @test_v1i64_f64_helper(double %2)
%4 = add <1 x i64> %3, %3
- store <1 x i64> %4, <1 x i64>* %q
+ store <1 x i64> %4, ptr %q
ret void
}
declare <1 x i64> @test_v1i64_v2f32_helper(<2 x float> %p)
-define void @test_v1i64_v2f32(<2 x float>* %p, <1 x i64>* %q) {
+define void @test_v1i64_v2f32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v1i64_v2f32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -563,16 +563,16 @@ define void @test_v1i64_v2f32(<2 x float>* %p, <1 x i64>* %q) {
; HARD-NEXT: vadd.i64 d16, d0, d0
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x float>, <2 x float>* %p
+ %1 = load <2 x float>, ptr %p
%2 = fadd <2 x float> %1, %1
%3 = call <1 x i64> @test_v1i64_v2f32_helper(<2 x float> %2)
%4 = add <1 x i64> %3, %3
- store <1 x i64> %4, <1 x i64>* %q
+ store <1 x i64> %4, ptr %q
ret void
}
declare <1 x i64> @test_v1i64_v2i32_helper(<2 x i32> %p)
-define void @test_v1i64_v2i32(<2 x i32>* %p, <1 x i64>* %q) {
+define void @test_v1i64_v2i32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v1i64_v2i32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -602,16 +602,16 @@ define void @test_v1i64_v2i32(<2 x i32>* %p, <1 x i64>* %q) {
; HARD-NEXT: vadd.i64 d16, d0, d0
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x i32>, <2 x i32>* %p
+ %1 = load <2 x i32>, ptr %p
%2 = add <2 x i32> %1, %1
%3 = call <1 x i64> @test_v1i64_v2i32_helper(<2 x i32> %2)
%4 = add <1 x i64> %3, %3
- store <1 x i64> %4, <1 x i64>* %q
+ store <1 x i64> %4, ptr %q
ret void
}
declare <1 x i64> @test_v1i64_v4i16_helper(<4 x i16> %p)
-define void @test_v1i64_v4i16(<4 x i16>* %p, <1 x i64>* %q) {
+define void @test_v1i64_v4i16(ptr %p, ptr %q) {
; SOFT-LABEL: test_v1i64_v4i16:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -641,16 +641,16 @@ define void @test_v1i64_v4i16(<4 x i16>* %p, <1 x i64>* %q) {
; HARD-NEXT: vadd.i64 d16, d0, d0
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x i16>, <4 x i16>* %p
+ %1 = load <4 x i16>, ptr %p
%2 = add <4 x i16> %1, %1
%3 = call <1 x i64> @test_v1i64_v4i16_helper(<4 x i16> %2)
%4 = add <1 x i64> %3, %3
- store <1 x i64> %4, <1 x i64>* %q
+ store <1 x i64> %4, ptr %q
ret void
}
declare <1 x i64> @test_v1i64_v8i8_helper(<8 x i8> %p)
-define void @test_v1i64_v8i8(<8 x i8>* %p, <1 x i64>* %q) {
+define void @test_v1i64_v8i8(ptr %p, ptr %q) {
; SOFT-LABEL: test_v1i64_v8i8:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -680,16 +680,16 @@ define void @test_v1i64_v8i8(<8 x i8>* %p, <1 x i64>* %q) {
; HARD-NEXT: vadd.i64 d16, d0, d0
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <8 x i8>, <8 x i8>* %p
+ %1 = load <8 x i8>, ptr %p
%2 = add <8 x i8> %1, %1
%3 = call <1 x i64> @test_v1i64_v8i8_helper(<8 x i8> %2)
%4 = add <1 x i64> %3, %3
- store <1 x i64> %4, <1 x i64>* %q
+ store <1 x i64> %4, ptr %q
ret void
}
declare <2 x float> @test_v2f32_i64_helper(i64 %p)
-define void @test_v2f32_i64(i64* %p, <2 x float>* %q) {
+define void @test_v2f32_i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2f32_i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -720,16 +720,16 @@ define void @test_v2f32_i64(i64* %p, <2 x float>* %q) {
; HARD-NEXT: vrev64.32 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load i64, i64* %p
+ %1 = load i64, ptr %p
%2 = add i64 %1, %1
%3 = call <2 x float> @test_v2f32_i64_helper(i64 %2)
%4 = fadd <2 x float> %3, %3
- store <2 x float> %4, <2 x float>* %q
+ store <2 x float> %4, ptr %q
ret void
}
declare <2 x float> @test_v2f32_f64_helper(double %p)
-define void @test_v2f32_f64(double* %p, <2 x float>* %q) {
+define void @test_v2f32_f64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2f32_f64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -759,16 +759,16 @@ define void @test_v2f32_f64(double* %p, <2 x float>* %q) {
; HARD-NEXT: vrev64.32 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load double, double* %p
+ %1 = load double, ptr %p
%2 = fadd double %1, %1
%3 = call <2 x float> @test_v2f32_f64_helper(double %2)
%4 = fadd <2 x float> %3, %3
- store <2 x float> %4, <2 x float>* %q
+ store <2 x float> %4, ptr %q
ret void
}
declare <2 x float> @test_v2f32_v1i64_helper(<1 x i64> %p)
-define void @test_v2f32_v1i64(<1 x i64>* %p, <2 x float>* %q) {
+define void @test_v2f32_v1i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2f32_v1i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -798,16 +798,16 @@ define void @test_v2f32_v1i64(<1 x i64>* %p, <2 x float>* %q) {
; HARD-NEXT: vrev64.32 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <1 x i64>, <1 x i64>* %p
+ %1 = load <1 x i64>, ptr %p
%2 = add <1 x i64> %1, %1
%3 = call <2 x float> @test_v2f32_v1i64_helper(<1 x i64> %2)
%4 = fadd <2 x float> %3, %3
- store <2 x float> %4, <2 x float>* %q
+ store <2 x float> %4, ptr %q
ret void
}
declare <2 x float> @test_v2f32_v2i32_helper(<2 x i32> %p)
-define void @test_v2f32_v2i32(<2 x i32>* %p, <2 x float>* %q) {
+define void @test_v2f32_v2i32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2f32_v2i32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -841,16 +841,16 @@ define void @test_v2f32_v2i32(<2 x i32>* %p, <2 x float>* %q) {
; HARD-NEXT: vrev64.32 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x i32>, <2 x i32>* %p
+ %1 = load <2 x i32>, ptr %p
%2 = add <2 x i32> %1, %1
%3 = call <2 x float> @test_v2f32_v2i32_helper(<2 x i32> %2)
%4 = fadd <2 x float> %3, %3
- store <2 x float> %4, <2 x float>* %q
+ store <2 x float> %4, ptr %q
ret void
}
declare <2 x float> @test_v2f32_v4i16_helper(<4 x i16> %p)
-define void @test_v2f32_v4i16(<4 x i16>* %p, <2 x float>* %q) {
+define void @test_v2f32_v4i16(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2f32_v4i16:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -884,16 +884,16 @@ define void @test_v2f32_v4i16(<4 x i16>* %p, <2 x float>* %q) {
; HARD-NEXT: vrev64.32 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x i16>, <4 x i16>* %p
+ %1 = load <4 x i16>, ptr %p
%2 = add <4 x i16> %1, %1
%3 = call <2 x float> @test_v2f32_v4i16_helper(<4 x i16> %2)
%4 = fadd <2 x float> %3, %3
- store <2 x float> %4, <2 x float>* %q
+ store <2 x float> %4, ptr %q
ret void
}
declare <2 x float> @test_v2f32_v8i8_helper(<8 x i8> %p)
-define void @test_v2f32_v8i8(<8 x i8>* %p, <2 x float>* %q) {
+define void @test_v2f32_v8i8(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2f32_v8i8:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -927,16 +927,16 @@ define void @test_v2f32_v8i8(<8 x i8>* %p, <2 x float>* %q) {
; HARD-NEXT: vrev64.32 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <8 x i8>, <8 x i8>* %p
+ %1 = load <8 x i8>, ptr %p
%2 = add <8 x i8> %1, %1
%3 = call <2 x float> @test_v2f32_v8i8_helper(<8 x i8> %2)
%4 = fadd <2 x float> %3, %3
- store <2 x float> %4, <2 x float>* %q
+ store <2 x float> %4, ptr %q
ret void
}
declare <2 x i32> @test_v2i32_i64_helper(i64 %p)
-define void @test_v2i32_i64(i64* %p, <2 x i32>* %q) {
+define void @test_v2i32_i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2i32_i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -967,16 +967,16 @@ define void @test_v2i32_i64(i64* %p, <2 x i32>* %q) {
; HARD-NEXT: vrev64.32 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load i64, i64* %p
+ %1 = load i64, ptr %p
%2 = add i64 %1, %1
%3 = call <2 x i32> @test_v2i32_i64_helper(i64 %2)
%4 = add <2 x i32> %3, %3
- store <2 x i32> %4, <2 x i32>* %q
+ store <2 x i32> %4, ptr %q
ret void
}
declare <2 x i32> @test_v2i32_f64_helper(double %p)
-define void @test_v2i32_f64(double* %p, <2 x i32>* %q) {
+define void @test_v2i32_f64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2i32_f64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1006,16 +1006,16 @@ define void @test_v2i32_f64(double* %p, <2 x i32>* %q) {
; HARD-NEXT: vrev64.32 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load double, double* %p
+ %1 = load double, ptr %p
%2 = fadd double %1, %1
%3 = call <2 x i32> @test_v2i32_f64_helper(double %2)
%4 = add <2 x i32> %3, %3
- store <2 x i32> %4, <2 x i32>* %q
+ store <2 x i32> %4, ptr %q
ret void
}
declare <2 x i32> @test_v2i32_v1i64_helper(<1 x i64> %p)
-define void @test_v2i32_v1i64(<1 x i64>* %p, <2 x i32>* %q) {
+define void @test_v2i32_v1i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2i32_v1i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1045,16 +1045,16 @@ define void @test_v2i32_v1i64(<1 x i64>* %p, <2 x i32>* %q) {
; HARD-NEXT: vrev64.32 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <1 x i64>, <1 x i64>* %p
+ %1 = load <1 x i64>, ptr %p
%2 = add <1 x i64> %1, %1
%3 = call <2 x i32> @test_v2i32_v1i64_helper(<1 x i64> %2)
%4 = add <2 x i32> %3, %3
- store <2 x i32> %4, <2 x i32>* %q
+ store <2 x i32> %4, ptr %q
ret void
}
declare <2 x i32> @test_v2i32_v2f32_helper(<2 x float> %p)
-define void @test_v2i32_v2f32(<2 x float>* %p, <2 x i32>* %q) {
+define void @test_v2i32_v2f32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2i32_v2f32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1088,16 +1088,16 @@ define void @test_v2i32_v2f32(<2 x float>* %p, <2 x i32>* %q) {
; HARD-NEXT: vrev64.32 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x float>, <2 x float>* %p
+ %1 = load <2 x float>, ptr %p
%2 = fadd <2 x float> %1, %1
%3 = call <2 x i32> @test_v2i32_v2f32_helper(<2 x float> %2)
%4 = add <2 x i32> %3, %3
- store <2 x i32> %4, <2 x i32>* %q
+ store <2 x i32> %4, ptr %q
ret void
}
declare <2 x i32> @test_v2i32_v4i16_helper(<4 x i16> %p)
-define void @test_v2i32_v4i16(<4 x i16>* %p, <2 x i32>* %q) {
+define void @test_v2i32_v4i16(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2i32_v4i16:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1131,16 +1131,16 @@ define void @test_v2i32_v4i16(<4 x i16>* %p, <2 x i32>* %q) {
; HARD-NEXT: vrev64.32 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x i16>, <4 x i16>* %p
+ %1 = load <4 x i16>, ptr %p
%2 = add <4 x i16> %1, %1
%3 = call <2 x i32> @test_v2i32_v4i16_helper(<4 x i16> %2)
%4 = add <2 x i32> %3, %3
- store <2 x i32> %4, <2 x i32>* %q
+ store <2 x i32> %4, ptr %q
ret void
}
declare <2 x i32> @test_v2i32_v8i8_helper(<8 x i8> %p)
-define void @test_v2i32_v8i8(<8 x i8>* %p, <2 x i32>* %q) {
+define void @test_v2i32_v8i8(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2i32_v8i8:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1174,16 +1174,16 @@ define void @test_v2i32_v8i8(<8 x i8>* %p, <2 x i32>* %q) {
; HARD-NEXT: vrev64.32 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <8 x i8>, <8 x i8>* %p
+ %1 = load <8 x i8>, ptr %p
%2 = add <8 x i8> %1, %1
%3 = call <2 x i32> @test_v2i32_v8i8_helper(<8 x i8> %2)
%4 = add <2 x i32> %3, %3
- store <2 x i32> %4, <2 x i32>* %q
+ store <2 x i32> %4, ptr %q
ret void
}
declare <4 x i16> @test_v4i16_i64_helper(i64 %p)
-define void @test_v4i16_i64(i64* %p, <4 x i16>* %q) {
+define void @test_v4i16_i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4i16_i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1214,16 +1214,16 @@ define void @test_v4i16_i64(i64* %p, <4 x i16>* %q) {
; HARD-NEXT: vrev64.16 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load i64, i64* %p
+ %1 = load i64, ptr %p
%2 = add i64 %1, %1
%3 = call <4 x i16> @test_v4i16_i64_helper(i64 %2)
%4 = add <4 x i16> %3, %3
- store <4 x i16> %4, <4 x i16>* %q
+ store <4 x i16> %4, ptr %q
ret void
}
declare <4 x i16> @test_v4i16_f64_helper(double %p)
-define void @test_v4i16_f64(double* %p, <4 x i16>* %q) {
+define void @test_v4i16_f64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4i16_f64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1253,16 +1253,16 @@ define void @test_v4i16_f64(double* %p, <4 x i16>* %q) {
; HARD-NEXT: vrev64.16 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load double, double* %p
+ %1 = load double, ptr %p
%2 = fadd double %1, %1
%3 = call <4 x i16> @test_v4i16_f64_helper(double %2)
%4 = add <4 x i16> %3, %3
- store <4 x i16> %4, <4 x i16>* %q
+ store <4 x i16> %4, ptr %q
ret void
}
declare <4 x i16> @test_v4i16_v1i64_helper(<1 x i64> %p)
-define void @test_v4i16_v1i64(<1 x i64>* %p, <4 x i16>* %q) {
+define void @test_v4i16_v1i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4i16_v1i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1292,16 +1292,16 @@ define void @test_v4i16_v1i64(<1 x i64>* %p, <4 x i16>* %q) {
; HARD-NEXT: vrev64.16 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <1 x i64>, <1 x i64>* %p
+ %1 = load <1 x i64>, ptr %p
%2 = add <1 x i64> %1, %1
%3 = call <4 x i16> @test_v4i16_v1i64_helper(<1 x i64> %2)
%4 = add <4 x i16> %3, %3
- store <4 x i16> %4, <4 x i16>* %q
+ store <4 x i16> %4, ptr %q
ret void
}
declare <4 x i16> @test_v4i16_v2f32_helper(<2 x float> %p)
-define void @test_v4i16_v2f32(<2 x float>* %p, <4 x i16>* %q) {
+define void @test_v4i16_v2f32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4i16_v2f32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1335,16 +1335,16 @@ define void @test_v4i16_v2f32(<2 x float>* %p, <4 x i16>* %q) {
; HARD-NEXT: vrev64.16 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x float>, <2 x float>* %p
+ %1 = load <2 x float>, ptr %p
%2 = fadd <2 x float> %1, %1
%3 = call <4 x i16> @test_v4i16_v2f32_helper(<2 x float> %2)
%4 = add <4 x i16> %3, %3
- store <4 x i16> %4, <4 x i16>* %q
+ store <4 x i16> %4, ptr %q
ret void
}
declare <4 x i16> @test_v4i16_v2i32_helper(<2 x i32> %p)
-define void @test_v4i16_v2i32(<2 x i32>* %p, <4 x i16>* %q) {
+define void @test_v4i16_v2i32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4i16_v2i32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1378,16 +1378,16 @@ define void @test_v4i16_v2i32(<2 x i32>* %p, <4 x i16>* %q) {
; HARD-NEXT: vrev64.16 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x i32>, <2 x i32>* %p
+ %1 = load <2 x i32>, ptr %p
%2 = add <2 x i32> %1, %1
%3 = call <4 x i16> @test_v4i16_v2i32_helper(<2 x i32> %2)
%4 = add <4 x i16> %3, %3
- store <4 x i16> %4, <4 x i16>* %q
+ store <4 x i16> %4, ptr %q
ret void
}
declare <4 x i16> @test_v4i16_v8i8_helper(<8 x i8> %p)
-define void @test_v4i16_v8i8(<8 x i8>* %p, <4 x i16>* %q) {
+define void @test_v4i16_v8i8(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4i16_v8i8:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1421,16 +1421,16 @@ define void @test_v4i16_v8i8(<8 x i8>* %p, <4 x i16>* %q) {
; HARD-NEXT: vrev64.16 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <8 x i8>, <8 x i8>* %p
+ %1 = load <8 x i8>, ptr %p
%2 = add <8 x i8> %1, %1
%3 = call <4 x i16> @test_v4i16_v8i8_helper(<8 x i8> %2)
%4 = add <4 x i16> %3, %3
- store <4 x i16> %4, <4 x i16>* %q
+ store <4 x i16> %4, ptr %q
ret void
}
declare <8 x i8> @test_v8i8_i64_helper(i64 %p)
-define void @test_v8i8_i64(i64* %p, <8 x i8>* %q) {
+define void @test_v8i8_i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v8i8_i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1461,16 +1461,16 @@ define void @test_v8i8_i64(i64* %p, <8 x i8>* %q) {
; HARD-NEXT: vrev64.8 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load i64, i64* %p
+ %1 = load i64, ptr %p
%2 = add i64 %1, %1
%3 = call <8 x i8> @test_v8i8_i64_helper(i64 %2)
%4 = add <8 x i8> %3, %3
- store <8 x i8> %4, <8 x i8>* %q
+ store <8 x i8> %4, ptr %q
ret void
}
declare <8 x i8> @test_v8i8_f64_helper(double %p)
-define void @test_v8i8_f64(double* %p, <8 x i8>* %q) {
+define void @test_v8i8_f64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v8i8_f64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1500,16 +1500,16 @@ define void @test_v8i8_f64(double* %p, <8 x i8>* %q) {
; HARD-NEXT: vrev64.8 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load double, double* %p
+ %1 = load double, ptr %p
%2 = fadd double %1, %1
%3 = call <8 x i8> @test_v8i8_f64_helper(double %2)
%4 = add <8 x i8> %3, %3
- store <8 x i8> %4, <8 x i8>* %q
+ store <8 x i8> %4, ptr %q
ret void
}
declare <8 x i8> @test_v8i8_v1i64_helper(<1 x i64> %p)
-define void @test_v8i8_v1i64(<1 x i64>* %p, <8 x i8>* %q) {
+define void @test_v8i8_v1i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v8i8_v1i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1539,16 +1539,16 @@ define void @test_v8i8_v1i64(<1 x i64>* %p, <8 x i8>* %q) {
; HARD-NEXT: vrev64.8 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <1 x i64>, <1 x i64>* %p
+ %1 = load <1 x i64>, ptr %p
%2 = add <1 x i64> %1, %1
%3 = call <8 x i8> @test_v8i8_v1i64_helper(<1 x i64> %2)
%4 = add <8 x i8> %3, %3
- store <8 x i8> %4, <8 x i8>* %q
+ store <8 x i8> %4, ptr %q
ret void
}
declare <8 x i8> @test_v8i8_v2f32_helper(<2 x float> %p)
-define void @test_v8i8_v2f32(<2 x float>* %p, <8 x i8>* %q) {
+define void @test_v8i8_v2f32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v8i8_v2f32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1582,16 +1582,16 @@ define void @test_v8i8_v2f32(<2 x float>* %p, <8 x i8>* %q) {
; HARD-NEXT: vrev64.8 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x float>, <2 x float>* %p
+ %1 = load <2 x float>, ptr %p
%2 = fadd <2 x float> %1, %1
%3 = call <8 x i8> @test_v8i8_v2f32_helper(<2 x float> %2)
%4 = add <8 x i8> %3, %3
- store <8 x i8> %4, <8 x i8>* %q
+ store <8 x i8> %4, ptr %q
ret void
}
declare <8 x i8> @test_v8i8_v2i32_helper(<2 x i32> %p)
-define void @test_v8i8_v2i32(<2 x i32>* %p, <8 x i8>* %q) {
+define void @test_v8i8_v2i32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v8i8_v2i32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1625,16 +1625,16 @@ define void @test_v8i8_v2i32(<2 x i32>* %p, <8 x i8>* %q) {
; HARD-NEXT: vrev64.8 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x i32>, <2 x i32>* %p
+ %1 = load <2 x i32>, ptr %p
%2 = add <2 x i32> %1, %1
%3 = call <8 x i8> @test_v8i8_v2i32_helper(<2 x i32> %2)
%4 = add <8 x i8> %3, %3
- store <8 x i8> %4, <8 x i8>* %q
+ store <8 x i8> %4, ptr %q
ret void
}
declare <8 x i8> @test_v8i8_v4i16_helper(<4 x i16> %p)
-define void @test_v8i8_v4i16(<4 x i16>* %p, <8 x i8>* %q) {
+define void @test_v8i8_v4i16(ptr %p, ptr %q) {
; SOFT-LABEL: test_v8i8_v4i16:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1668,16 +1668,16 @@ define void @test_v8i8_v4i16(<4 x i16>* %p, <8 x i8>* %q) {
; HARD-NEXT: vrev64.8 d16, d16
; HARD-NEXT: vstr d16, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x i16>, <4 x i16>* %p
+ %1 = load <4 x i16>, ptr %p
%2 = add <4 x i16> %1, %1
%3 = call <8 x i8> @test_v8i8_v4i16_helper(<4 x i16> %2)
%4 = add <8 x i8> %3, %3
- store <8 x i8> %4, <8 x i8>* %q
+ store <8 x i8> %4, ptr %q
ret void
}
declare fp128 @test_f128_v2f64_helper(<2 x double> %p)
-define void @test_f128_v2f64(<2 x double>* %p, fp128* %q) {
+define void @test_f128_v2f64(ptr %p, ptr %q) {
; SOFT-LABEL: test_f128_v2f64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1713,16 +1713,16 @@ define void @test_f128_v2f64(<2 x double>* %p, fp128* %q) {
; HARD-NEXT: stm r4, {r0, r1, r2, r3}
; HARD-NEXT: add sp, sp, #16
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x double>, <2 x double>* %p
+ %1 = load <2 x double>, ptr %p
%2 = fadd <2 x double> %1, %1
%3 = call fp128 @test_f128_v2f64_helper(<2 x double> %2)
%4 = fadd fp128 %3, %3
- store fp128 %4, fp128* %q
+ store fp128 %4, ptr %q
ret void
}
declare fp128 @test_f128_v2i64_helper(<2 x i64> %p)
-define void @test_f128_v2i64(<2 x i64>* %p, fp128* %q) {
+define void @test_f128_v2i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_f128_v2i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1756,16 +1756,16 @@ define void @test_f128_v2i64(<2 x i64>* %p, fp128* %q) {
; HARD-NEXT: stm r4, {r0, r1, r2, r3}
; HARD-NEXT: add sp, sp, #16
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x i64>, <2 x i64>* %p
+ %1 = load <2 x i64>, ptr %p
%2 = add <2 x i64> %1, %1
%3 = call fp128 @test_f128_v2i64_helper(<2 x i64> %2)
%4 = fadd fp128 %3, %3
- store fp128 %4, fp128* %q
+ store fp128 %4, ptr %q
ret void
}
declare fp128 @test_f128_v4f32_helper(<4 x float> %p)
-define void @test_f128_v4f32(<4 x float>* %p, fp128* %q) {
+define void @test_f128_v4f32(ptr %p, ptr %q) {
; SOFT-LABEL: test_f128_v4f32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1803,16 +1803,16 @@ define void @test_f128_v4f32(<4 x float>* %p, fp128* %q) {
; HARD-NEXT: stm r4, {r0, r1, r2, r3}
; HARD-NEXT: add sp, sp, #16
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x float>, <4 x float>* %p
+ %1 = load <4 x float>, ptr %p
%2 = fadd <4 x float> %1, %1
%3 = call fp128 @test_f128_v4f32_helper(<4 x float> %2)
%4 = fadd fp128 %3, %3
- store fp128 %4, fp128* %q
+ store fp128 %4, ptr %q
ret void
}
declare fp128 @test_f128_v4i32_helper(<4 x i32> %p)
-define void @test_f128_v4i32(<4 x i32>* %p, fp128* %q) {
+define void @test_f128_v4i32(ptr %p, ptr %q) {
; SOFT-LABEL: test_f128_v4i32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1850,16 +1850,16 @@ define void @test_f128_v4i32(<4 x i32>* %p, fp128* %q) {
; HARD-NEXT: stm r4, {r0, r1, r2, r3}
; HARD-NEXT: add sp, sp, #16
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x i32>, <4 x i32>* %p
+ %1 = load <4 x i32>, ptr %p
%2 = add <4 x i32> %1, %1
%3 = call fp128 @test_f128_v4i32_helper(<4 x i32> %2)
%4 = fadd fp128 %3, %3
- store fp128 %4, fp128* %q
+ store fp128 %4, ptr %q
ret void
}
declare fp128 @test_f128_v8i16_helper(<8 x i16> %p)
-define void @test_f128_v8i16(<8 x i16>* %p, fp128* %q) {
+define void @test_f128_v8i16(ptr %p, ptr %q) {
; SOFT-LABEL: test_f128_v8i16:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1897,16 +1897,16 @@ define void @test_f128_v8i16(<8 x i16>* %p, fp128* %q) {
; HARD-NEXT: stm r4, {r0, r1, r2, r3}
; HARD-NEXT: add sp, sp, #16
; HARD-NEXT: pop {r4, pc}
- %1 = load <8 x i16>, <8 x i16>* %p
+ %1 = load <8 x i16>, ptr %p
%2 = add <8 x i16> %1, %1
%3 = call fp128 @test_f128_v8i16_helper(<8 x i16> %2)
%4 = fadd fp128 %3, %3
- store fp128 %4, fp128* %q
+ store fp128 %4, ptr %q
ret void
}
declare fp128 @test_f128_v16i8_helper(<16 x i8> %p)
-define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) {
+define void @test_f128_v16i8(ptr %p, ptr %q) {
; SOFT-LABEL: test_f128_v16i8:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -1944,16 +1944,16 @@ define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) {
; HARD-NEXT: stm r4, {r0, r1, r2, r3}
; HARD-NEXT: add sp, sp, #16
; HARD-NEXT: pop {r4, pc}
- %1 = load <16 x i8>, <16 x i8>* %p
+ %1 = load <16 x i8>, ptr %p
%2 = add <16 x i8> %1, %1
%3 = call fp128 @test_f128_v16i8_helper(<16 x i8> %2)
%4 = fadd fp128 %3, %3
- store fp128 %4, fp128* %q
+ store fp128 %4, ptr %q
ret void
}
declare <2 x double> @test_v2f64_f128_helper(fp128 %p)
-define void @test_v2f64_f128(fp128* %p, <2 x double>* %q) {
+define void @test_v2f64_f128(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2f64_f128:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r11, lr}
@@ -1995,17 +1995,17 @@ define void @test_v2f64_f128(fp128* %p, <2 x double>* %q) {
; HARD-NEXT: vst1.64 {d16, d17}, [r5]
; HARD-NEXT: add sp, sp, #16
; HARD-NEXT: pop {r4, r5, r11, pc}
- %1 = load fp128, fp128* %p
+ %1 = load fp128, ptr %p
%2 = fadd fp128 %1, %1
%3 = call <2 x double> @test_v2f64_f128_helper(fp128 %2)
%4 = fadd <2 x double> %3, %3
- store <2 x double> %4, <2 x double>* %q
+ store <2 x double> %4, ptr %q
ret void
}
declare <2 x double> @test_v2f64_v2i64_helper(<2 x i64> %p)
-define void @test_v2f64_v2i64(<2 x i64>* %p, <2 x double>* %q) {
+define void @test_v2f64_v2i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2f64_v2i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2035,16 +2035,16 @@ define void @test_v2f64_v2i64(<2 x i64>* %p, <2 x double>* %q) {
; HARD-NEXT: vadd.f64 d16, d0, d0
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x i64>, <2 x i64>* %p
+ %1 = load <2 x i64>, ptr %p
%2 = add <2 x i64> %1, %1
%3 = call <2 x double> @test_v2f64_v2i64_helper(<2 x i64> %2)
%4 = fadd <2 x double> %3, %3
- store <2 x double> %4, <2 x double>* %q
+ store <2 x double> %4, ptr %q
ret void
}
declare <2 x double> @test_v2f64_v4f32_helper(<4 x float> %p)
-define void @test_v2f64_v4f32(<4 x float>* %p, <2 x double>* %q) {
+define void @test_v2f64_v4f32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2f64_v4f32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2078,16 +2078,16 @@ define void @test_v2f64_v4f32(<4 x float>* %p, <2 x double>* %q) {
; HARD-NEXT: vadd.f64 d16, d0, d0
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x float>, <4 x float>* %p
+ %1 = load <4 x float>, ptr %p
%2 = fadd <4 x float> %1, %1
%3 = call <2 x double> @test_v2f64_v4f32_helper(<4 x float> %2)
%4 = fadd <2 x double> %3, %3
- store <2 x double> %4, <2 x double>* %q
+ store <2 x double> %4, ptr %q
ret void
}
declare <2 x double> @test_v2f64_v4i32_helper(<4 x i32> %p)
-define void @test_v2f64_v4i32(<4 x i32>* %p, <2 x double>* %q) {
+define void @test_v2f64_v4i32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2f64_v4i32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2121,16 +2121,16 @@ define void @test_v2f64_v4i32(<4 x i32>* %p, <2 x double>* %q) {
; HARD-NEXT: vadd.f64 d16, d0, d0
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x i32>, <4 x i32>* %p
+ %1 = load <4 x i32>, ptr %p
%2 = add <4 x i32> %1, %1
%3 = call <2 x double> @test_v2f64_v4i32_helper(<4 x i32> %2)
%4 = fadd <2 x double> %3, %3
- store <2 x double> %4, <2 x double>* %q
+ store <2 x double> %4, ptr %q
ret void
}
declare <2 x double> @test_v2f64_v8i16_helper(<8 x i16> %p)
-define void @test_v2f64_v8i16(<8 x i16>* %p, <2 x double>* %q) {
+define void @test_v2f64_v8i16(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2f64_v8i16:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2164,16 +2164,16 @@ define void @test_v2f64_v8i16(<8 x i16>* %p, <2 x double>* %q) {
; HARD-NEXT: vadd.f64 d16, d0, d0
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <8 x i16>, <8 x i16>* %p
+ %1 = load <8 x i16>, ptr %p
%2 = add <8 x i16> %1, %1
%3 = call <2 x double> @test_v2f64_v8i16_helper(<8 x i16> %2)
%4 = fadd <2 x double> %3, %3
- store <2 x double> %4, <2 x double>* %q
+ store <2 x double> %4, ptr %q
ret void
}
declare <2 x double> @test_v2f64_v16i8_helper(<16 x i8> %p)
-define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) {
+define void @test_v2f64_v16i8(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2f64_v16i8:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2207,16 +2207,16 @@ define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) {
; HARD-NEXT: vadd.f64 d16, d0, d0
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <16 x i8>, <16 x i8>* %p
+ %1 = load <16 x i8>, ptr %p
%2 = add <16 x i8> %1, %1
%3 = call <2 x double> @test_v2f64_v16i8_helper(<16 x i8> %2)
%4 = fadd <2 x double> %3, %3
- store <2 x double> %4, <2 x double>* %q
+ store <2 x double> %4, ptr %q
ret void
}
declare <2 x i64> @test_v2i64_f128_helper(fp128 %p)
-define void @test_v2i64_f128(fp128* %p, <2 x i64>* %q) {
+define void @test_v2i64_f128(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2i64_f128:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r11, lr}
@@ -2256,16 +2256,16 @@ define void @test_v2i64_f128(fp128* %p, <2 x i64>* %q) {
; HARD-NEXT: vst1.64 {d16, d17}, [r5]
; HARD-NEXT: add sp, sp, #16
; HARD-NEXT: pop {r4, r5, r11, pc}
- %1 = load fp128, fp128* %p
+ %1 = load fp128, ptr %p
%2 = fadd fp128 %1, %1
%3 = call <2 x i64> @test_v2i64_f128_helper(fp128 %2)
%4 = add <2 x i64> %3, %3
- store <2 x i64> %4, <2 x i64>* %q
+ store <2 x i64> %4, ptr %q
ret void
}
declare <2 x i64> @test_v2i64_v2f64_helper(<2 x double> %p)
-define void @test_v2i64_v2f64(<2 x double>* %p, <2 x i64>* %q) {
+define void @test_v2i64_v2f64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2i64_v2f64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2295,16 +2295,16 @@ define void @test_v2i64_v2f64(<2 x double>* %p, <2 x i64>* %q) {
; HARD-NEXT: vadd.i64 q8, q0, q0
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x double>, <2 x double>* %p
+ %1 = load <2 x double>, ptr %p
%2 = fadd <2 x double> %1, %1
%3 = call <2 x i64> @test_v2i64_v2f64_helper(<2 x double> %2)
%4 = add <2 x i64> %3, %3
- store <2 x i64> %4, <2 x i64>* %q
+ store <2 x i64> %4, ptr %q
ret void
}
declare <2 x i64> @test_v2i64_v4f32_helper(<4 x float> %p)
-define void @test_v2i64_v4f32(<4 x float>* %p, <2 x i64>* %q) {
+define void @test_v2i64_v4f32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2i64_v4f32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2336,16 +2336,16 @@ define void @test_v2i64_v4f32(<4 x float>* %p, <2 x i64>* %q) {
; HARD-NEXT: vadd.i64 q8, q0, q0
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x float>, <4 x float>* %p
+ %1 = load <4 x float>, ptr %p
%2 = fadd <4 x float> %1, %1
%3 = call <2 x i64> @test_v2i64_v4f32_helper(<4 x float> %2)
%4 = add <2 x i64> %3, %3
- store <2 x i64> %4, <2 x i64>* %q
+ store <2 x i64> %4, ptr %q
ret void
}
declare <2 x i64> @test_v2i64_v4i32_helper(<4 x i32> %p)
-define void @test_v2i64_v4i32(<4 x i32>* %p, <2 x i64>* %q) {
+define void @test_v2i64_v4i32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2i64_v4i32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2377,16 +2377,16 @@ define void @test_v2i64_v4i32(<4 x i32>* %p, <2 x i64>* %q) {
; HARD-NEXT: vadd.i64 q8, q0, q0
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x i32>, <4 x i32>* %p
+ %1 = load <4 x i32>, ptr %p
%2 = add <4 x i32> %1, %1
%3 = call <2 x i64> @test_v2i64_v4i32_helper(<4 x i32> %2)
%4 = add <2 x i64> %3, %3
- store <2 x i64> %4, <2 x i64>* %q
+ store <2 x i64> %4, ptr %q
ret void
}
declare <2 x i64> @test_v2i64_v8i16_helper(<8 x i16> %p)
-define void @test_v2i64_v8i16(<8 x i16>* %p, <2 x i64>* %q) {
+define void @test_v2i64_v8i16(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2i64_v8i16:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2418,16 +2418,16 @@ define void @test_v2i64_v8i16(<8 x i16>* %p, <2 x i64>* %q) {
; HARD-NEXT: vadd.i64 q8, q0, q0
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <8 x i16>, <8 x i16>* %p
+ %1 = load <8 x i16>, ptr %p
%2 = add <8 x i16> %1, %1
%3 = call <2 x i64> @test_v2i64_v8i16_helper(<8 x i16> %2)
%4 = add <2 x i64> %3, %3
- store <2 x i64> %4, <2 x i64>* %q
+ store <2 x i64> %4, ptr %q
ret void
}
declare <2 x i64> @test_v2i64_v16i8_helper(<16 x i8> %p)
-define void @test_v2i64_v16i8(<16 x i8>* %p, <2 x i64>* %q) {
+define void @test_v2i64_v16i8(ptr %p, ptr %q) {
; SOFT-LABEL: test_v2i64_v16i8:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2459,16 +2459,16 @@ define void @test_v2i64_v16i8(<16 x i8>* %p, <2 x i64>* %q) {
; HARD-NEXT: vadd.i64 q8, q0, q0
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <16 x i8>, <16 x i8>* %p
+ %1 = load <16 x i8>, ptr %p
%2 = add <16 x i8> %1, %1
%3 = call <2 x i64> @test_v2i64_v16i8_helper(<16 x i8> %2)
%4 = add <2 x i64> %3, %3
- store <2 x i64> %4, <2 x i64>* %q
+ store <2 x i64> %4, ptr %q
ret void
}
declare <4 x float> @test_v4f32_f128_helper(fp128 %p)
-define void @test_v4f32_f128(fp128* %p, <4 x float>* %q) {
+define void @test_v4f32_f128(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4f32_f128:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r11, lr}
@@ -2512,16 +2512,16 @@ define void @test_v4f32_f128(fp128* %p, <4 x float>* %q) {
; HARD-NEXT: vst1.64 {d16, d17}, [r5]
; HARD-NEXT: add sp, sp, #16
; HARD-NEXT: pop {r4, r5, r11, pc}
- %1 = load fp128, fp128* %p
+ %1 = load fp128, ptr %p
%2 = fadd fp128 %1, %1
%3 = call <4 x float> @test_v4f32_f128_helper(fp128 %2)
%4 = fadd <4 x float> %3, %3
- store <4 x float> %4, <4 x float>* %q
+ store <4 x float> %4, ptr %q
ret void
}
declare <4 x float> @test_v4f32_v2f64_helper(<2 x double> %p)
-define void @test_v4f32_v2f64(<2 x double>* %p, <4 x float>* %q) {
+define void @test_v4f32_v2f64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4f32_v2f64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2555,16 +2555,16 @@ define void @test_v4f32_v2f64(<2 x double>* %p, <4 x float>* %q) {
; HARD-NEXT: vrev64.32 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x double>, <2 x double>* %p
+ %1 = load <2 x double>, ptr %p
%2 = fadd <2 x double> %1, %1
%3 = call <4 x float> @test_v4f32_v2f64_helper(<2 x double> %2)
%4 = fadd <4 x float> %3, %3
- store <4 x float> %4, <4 x float>* %q
+ store <4 x float> %4, ptr %q
ret void
}
declare <4 x float> @test_v4f32_v2i64_helper(<2 x i64> %p)
-define void @test_v4f32_v2i64(<2 x i64>* %p, <4 x float>* %q) {
+define void @test_v4f32_v2i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4f32_v2i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2596,16 +2596,16 @@ define void @test_v4f32_v2i64(<2 x i64>* %p, <4 x float>* %q) {
; HARD-NEXT: vrev64.32 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x i64>, <2 x i64>* %p
+ %1 = load <2 x i64>, ptr %p
%2 = add <2 x i64> %1, %1
%3 = call <4 x float> @test_v4f32_v2i64_helper(<2 x i64> %2)
%4 = fadd <4 x float> %3, %3
- store <4 x float> %4, <4 x float>* %q
+ store <4 x float> %4, ptr %q
ret void
}
declare <4 x float> @test_v4f32_v4i32_helper(<4 x i32> %p)
-define void @test_v4f32_v4i32(<4 x i32>* %p, <4 x float>* %q) {
+define void @test_v4f32_v4i32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4f32_v4i32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2641,16 +2641,16 @@ define void @test_v4f32_v4i32(<4 x i32>* %p, <4 x float>* %q) {
; HARD-NEXT: vrev64.32 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x i32>, <4 x i32>* %p
+ %1 = load <4 x i32>, ptr %p
%2 = add <4 x i32> %1, %1
%3 = call <4 x float> @test_v4f32_v4i32_helper(<4 x i32> %2)
%4 = fadd <4 x float> %3, %3
- store <4 x float> %4, <4 x float>* %q
+ store <4 x float> %4, ptr %q
ret void
}
declare <4 x float> @test_v4f32_v8i16_helper(<8 x i16> %p)
-define void @test_v4f32_v8i16(<8 x i16>* %p, <4 x float>* %q) {
+define void @test_v4f32_v8i16(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4f32_v8i16:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2686,16 +2686,16 @@ define void @test_v4f32_v8i16(<8 x i16>* %p, <4 x float>* %q) {
; HARD-NEXT: vrev64.32 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <8 x i16>, <8 x i16>* %p
+ %1 = load <8 x i16>, ptr %p
%2 = add <8 x i16> %1, %1
%3 = call <4 x float> @test_v4f32_v8i16_helper(<8 x i16> %2)
%4 = fadd <4 x float> %3, %3
- store <4 x float> %4, <4 x float>* %q
+ store <4 x float> %4, ptr %q
ret void
}
declare <4 x float> @test_v4f32_v16i8_helper(<16 x i8> %p)
-define void @test_v4f32_v16i8(<16 x i8>* %p, <4 x float>* %q) {
+define void @test_v4f32_v16i8(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4f32_v16i8:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2731,16 +2731,16 @@ define void @test_v4f32_v16i8(<16 x i8>* %p, <4 x float>* %q) {
; HARD-NEXT: vrev64.32 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <16 x i8>, <16 x i8>* %p
+ %1 = load <16 x i8>, ptr %p
%2 = add <16 x i8> %1, %1
%3 = call <4 x float> @test_v4f32_v16i8_helper(<16 x i8> %2)
%4 = fadd <4 x float> %3, %3
- store <4 x float> %4, <4 x float>* %q
+ store <4 x float> %4, ptr %q
ret void
}
declare <4 x i32> @test_v4i32_f128_helper(fp128 %p)
-define void @test_v4i32_f128(fp128* %p, <4 x i32>* %q) {
+define void @test_v4i32_f128(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4i32_f128:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r11, lr}
@@ -2784,16 +2784,16 @@ define void @test_v4i32_f128(fp128* %p, <4 x i32>* %q) {
; HARD-NEXT: vst1.64 {d16, d17}, [r5]
; HARD-NEXT: add sp, sp, #16
; HARD-NEXT: pop {r4, r5, r11, pc}
- %1 = load fp128, fp128* %p
+ %1 = load fp128, ptr %p
%2 = fadd fp128 %1, %1
%3 = call <4 x i32> @test_v4i32_f128_helper(fp128 %2)
%4 = add <4 x i32> %3, %3
- store <4 x i32> %4, <4 x i32>* %q
+ store <4 x i32> %4, ptr %q
ret void
}
declare <4 x i32> @test_v4i32_v2f64_helper(<2 x double> %p)
-define void @test_v4i32_v2f64(<2 x double>* %p, <4 x i32>* %q) {
+define void @test_v4i32_v2f64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4i32_v2f64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2827,16 +2827,16 @@ define void @test_v4i32_v2f64(<2 x double>* %p, <4 x i32>* %q) {
; HARD-NEXT: vrev64.32 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x double>, <2 x double>* %p
+ %1 = load <2 x double>, ptr %p
%2 = fadd <2 x double> %1, %1
%3 = call <4 x i32> @test_v4i32_v2f64_helper(<2 x double> %2)
%4 = add <4 x i32> %3, %3
- store <4 x i32> %4, <4 x i32>* %q
+ store <4 x i32> %4, ptr %q
ret void
}
declare <4 x i32> @test_v4i32_v2i64_helper(<2 x i64> %p)
-define void @test_v4i32_v2i64(<2 x i64>* %p, <4 x i32>* %q) {
+define void @test_v4i32_v2i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4i32_v2i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2868,16 +2868,16 @@ define void @test_v4i32_v2i64(<2 x i64>* %p, <4 x i32>* %q) {
; HARD-NEXT: vrev64.32 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x i64>, <2 x i64>* %p
+ %1 = load <2 x i64>, ptr %p
%2 = add <2 x i64> %1, %1
%3 = call <4 x i32> @test_v4i32_v2i64_helper(<2 x i64> %2)
%4 = add <4 x i32> %3, %3
- store <4 x i32> %4, <4 x i32>* %q
+ store <4 x i32> %4, ptr %q
ret void
}
declare <4 x i32> @test_v4i32_v4f32_helper(<4 x float> %p)
-define void @test_v4i32_v4f32(<4 x float>* %p, <4 x i32>* %q) {
+define void @test_v4i32_v4f32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4i32_v4f32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2913,16 +2913,16 @@ define void @test_v4i32_v4f32(<4 x float>* %p, <4 x i32>* %q) {
; HARD-NEXT: vrev64.32 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x float>, <4 x float>* %p
+ %1 = load <4 x float>, ptr %p
%2 = fadd <4 x float> %1, %1
%3 = call <4 x i32> @test_v4i32_v4f32_helper(<4 x float> %2)
%4 = add <4 x i32> %3, %3
- store <4 x i32> %4, <4 x i32>* %q
+ store <4 x i32> %4, ptr %q
ret void
}
declare <4 x i32> @test_v4i32_v8i16_helper(<8 x i16> %p)
-define void @test_v4i32_v8i16(<8 x i16>* %p, <4 x i32>* %q) {
+define void @test_v4i32_v8i16(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4i32_v8i16:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -2958,16 +2958,16 @@ define void @test_v4i32_v8i16(<8 x i16>* %p, <4 x i32>* %q) {
; HARD-NEXT: vrev64.32 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <8 x i16>, <8 x i16>* %p
+ %1 = load <8 x i16>, ptr %p
%2 = add <8 x i16> %1, %1
%3 = call <4 x i32> @test_v4i32_v8i16_helper(<8 x i16> %2)
%4 = add <4 x i32> %3, %3
- store <4 x i32> %4, <4 x i32>* %q
+ store <4 x i32> %4, ptr %q
ret void
}
declare <4 x i32> @test_v4i32_v16i8_helper(<16 x i8> %p)
-define void @test_v4i32_v16i8(<16 x i8>* %p, <4 x i32>* %q) {
+define void @test_v4i32_v16i8(ptr %p, ptr %q) {
; SOFT-LABEL: test_v4i32_v16i8:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -3003,16 +3003,16 @@ define void @test_v4i32_v16i8(<16 x i8>* %p, <4 x i32>* %q) {
; HARD-NEXT: vrev64.32 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <16 x i8>, <16 x i8>* %p
+ %1 = load <16 x i8>, ptr %p
%2 = add <16 x i8> %1, %1
%3 = call <4 x i32> @test_v4i32_v16i8_helper(<16 x i8> %2)
%4 = add <4 x i32> %3, %3
- store <4 x i32> %4, <4 x i32>* %q
+ store <4 x i32> %4, ptr %q
ret void
}
declare <8 x i16> @test_v8i16_f128_helper(fp128 %p)
-define void @test_v8i16_f128(fp128* %p, <8 x i16>* %q) {
+define void @test_v8i16_f128(ptr %p, ptr %q) {
; SOFT-LABEL: test_v8i16_f128:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r11, lr}
@@ -3056,16 +3056,16 @@ define void @test_v8i16_f128(fp128* %p, <8 x i16>* %q) {
; HARD-NEXT: vst1.64 {d16, d17}, [r5]
; HARD-NEXT: add sp, sp, #16
; HARD-NEXT: pop {r4, r5, r11, pc}
- %1 = load fp128, fp128* %p
+ %1 = load fp128, ptr %p
%2 = fadd fp128 %1, %1
%3 = call <8 x i16> @test_v8i16_f128_helper(fp128 %2)
%4 = add <8 x i16> %3, %3
- store <8 x i16> %4, <8 x i16>* %q
+ store <8 x i16> %4, ptr %q
ret void
}
declare <8 x i16> @test_v8i16_v2f64_helper(<2 x double> %p)
-define void @test_v8i16_v2f64(<2 x double>* %p, <8 x i16>* %q) {
+define void @test_v8i16_v2f64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v8i16_v2f64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -3099,16 +3099,16 @@ define void @test_v8i16_v2f64(<2 x double>* %p, <8 x i16>* %q) {
; HARD-NEXT: vrev64.16 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x double>, <2 x double>* %p
+ %1 = load <2 x double>, ptr %p
%2 = fadd <2 x double> %1, %1
%3 = call <8 x i16> @test_v8i16_v2f64_helper(<2 x double> %2)
%4 = add <8 x i16> %3, %3
- store <8 x i16> %4, <8 x i16>* %q
+ store <8 x i16> %4, ptr %q
ret void
}
declare <8 x i16> @test_v8i16_v2i64_helper(<2 x i64> %p)
-define void @test_v8i16_v2i64(<2 x i64>* %p, <8 x i16>* %q) {
+define void @test_v8i16_v2i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v8i16_v2i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -3140,16 +3140,16 @@ define void @test_v8i16_v2i64(<2 x i64>* %p, <8 x i16>* %q) {
; HARD-NEXT: vrev64.16 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x i64>, <2 x i64>* %p
+ %1 = load <2 x i64>, ptr %p
%2 = add <2 x i64> %1, %1
%3 = call <8 x i16> @test_v8i16_v2i64_helper(<2 x i64> %2)
%4 = add <8 x i16> %3, %3
- store <8 x i16> %4, <8 x i16>* %q
+ store <8 x i16> %4, ptr %q
ret void
}
declare <8 x i16> @test_v8i16_v4f32_helper(<4 x float> %p)
-define void @test_v8i16_v4f32(<4 x float>* %p, <8 x i16>* %q) {
+define void @test_v8i16_v4f32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v8i16_v4f32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -3185,16 +3185,16 @@ define void @test_v8i16_v4f32(<4 x float>* %p, <8 x i16>* %q) {
; HARD-NEXT: vrev64.16 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x float>, <4 x float>* %p
+ %1 = load <4 x float>, ptr %p
%2 = fadd <4 x float> %1, %1
%3 = call <8 x i16> @test_v8i16_v4f32_helper(<4 x float> %2)
%4 = add <8 x i16> %3, %3
- store <8 x i16> %4, <8 x i16>* %q
+ store <8 x i16> %4, ptr %q
ret void
}
declare <8 x i16> @test_v8i16_v4i32_helper(<4 x i32> %p)
-define void @test_v8i16_v4i32(<4 x i32>* %p, <8 x i16>* %q) {
+define void @test_v8i16_v4i32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v8i16_v4i32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -3230,16 +3230,16 @@ define void @test_v8i16_v4i32(<4 x i32>* %p, <8 x i16>* %q) {
; HARD-NEXT: vrev64.16 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x i32>, <4 x i32>* %p
+ %1 = load <4 x i32>, ptr %p
%2 = add <4 x i32> %1, %1
%3 = call <8 x i16> @test_v8i16_v4i32_helper(<4 x i32> %2)
%4 = add <8 x i16> %3, %3
- store <8 x i16> %4, <8 x i16>* %q
+ store <8 x i16> %4, ptr %q
ret void
}
declare <8 x i16> @test_v8i16_v16i8_helper(<16 x i8> %p)
-define void @test_v8i16_v16i8(<16 x i8>* %p, <8 x i16>* %q) {
+define void @test_v8i16_v16i8(ptr %p, ptr %q) {
; SOFT-LABEL: test_v8i16_v16i8:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -3275,16 +3275,16 @@ define void @test_v8i16_v16i8(<16 x i8>* %p, <8 x i16>* %q) {
; HARD-NEXT: vrev64.16 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <16 x i8>, <16 x i8>* %p
+ %1 = load <16 x i8>, ptr %p
%2 = add <16 x i8> %1, %1
%3 = call <8 x i16> @test_v8i16_v16i8_helper(<16 x i8> %2)
%4 = add <8 x i16> %3, %3
- store <8 x i16> %4, <8 x i16>* %q
+ store <8 x i16> %4, ptr %q
ret void
}
declare <16 x i8> @test_v16i8_f128_helper(fp128 %p)
-define void @test_v16i8_f128(fp128* %p, <16 x i8>* %q) {
+define void @test_v16i8_f128(ptr %p, ptr %q) {
; SOFT-LABEL: test_v16i8_f128:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r11, lr}
@@ -3328,16 +3328,16 @@ define void @test_v16i8_f128(fp128* %p, <16 x i8>* %q) {
; HARD-NEXT: vst1.64 {d16, d17}, [r5]
; HARD-NEXT: add sp, sp, #16
; HARD-NEXT: pop {r4, r5, r11, pc}
- %1 = load fp128, fp128* %p
+ %1 = load fp128, ptr %p
%2 = fadd fp128 %1, %1
%3 = call <16 x i8> @test_v16i8_f128_helper(fp128 %2)
%4 = add <16 x i8> %3, %3
- store <16 x i8> %4, <16 x i8>* %q
+ store <16 x i8> %4, ptr %q
ret void
}
declare <16 x i8> @test_v16i8_v2f64_helper(<2 x double> %p)
-define void @test_v16i8_v2f64(<2 x double>* %p, <16 x i8>* %q) {
+define void @test_v16i8_v2f64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v16i8_v2f64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -3371,16 +3371,16 @@ define void @test_v16i8_v2f64(<2 x double>* %p, <16 x i8>* %q) {
; HARD-NEXT: vrev64.8 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x double>, <2 x double>* %p
+ %1 = load <2 x double>, ptr %p
%2 = fadd <2 x double> %1, %1
%3 = call <16 x i8> @test_v16i8_v2f64_helper(<2 x double> %2)
%4 = add <16 x i8> %3, %3
- store <16 x i8> %4, <16 x i8>* %q
+ store <16 x i8> %4, ptr %q
ret void
}
declare <16 x i8> @test_v16i8_v2i64_helper(<2 x i64> %p)
-define void @test_v16i8_v2i64(<2 x i64>* %p, <16 x i8>* %q) {
+define void @test_v16i8_v2i64(ptr %p, ptr %q) {
; SOFT-LABEL: test_v16i8_v2i64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -3412,16 +3412,16 @@ define void @test_v16i8_v2i64(<2 x i64>* %p, <16 x i8>* %q) {
; HARD-NEXT: vrev64.8 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <2 x i64>, <2 x i64>* %p
+ %1 = load <2 x i64>, ptr %p
%2 = add <2 x i64> %1, %1
%3 = call <16 x i8> @test_v16i8_v2i64_helper(<2 x i64> %2)
%4 = add <16 x i8> %3, %3
- store <16 x i8> %4, <16 x i8>* %q
+ store <16 x i8> %4, ptr %q
ret void
}
declare <16 x i8> @test_v16i8_v4f32_helper(<4 x float> %p)
-define void @test_v16i8_v4f32(<4 x float>* %p, <16 x i8>* %q) {
+define void @test_v16i8_v4f32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v16i8_v4f32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -3457,16 +3457,16 @@ define void @test_v16i8_v4f32(<4 x float>* %p, <16 x i8>* %q) {
; HARD-NEXT: vrev64.8 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x float>, <4 x float>* %p
+ %1 = load <4 x float>, ptr %p
%2 = fadd <4 x float> %1, %1
%3 = call <16 x i8> @test_v16i8_v4f32_helper(<4 x float> %2)
%4 = add <16 x i8> %3, %3
- store <16 x i8> %4, <16 x i8>* %q
+ store <16 x i8> %4, ptr %q
ret void
}
declare <16 x i8> @test_v16i8_v4i32_helper(<4 x i32> %p)
-define void @test_v16i8_v4i32(<4 x i32>* %p, <16 x i8>* %q) {
+define void @test_v16i8_v4i32(ptr %p, ptr %q) {
; SOFT-LABEL: test_v16i8_v4i32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -3502,16 +3502,16 @@ define void @test_v16i8_v4i32(<4 x i32>* %p, <16 x i8>* %q) {
; HARD-NEXT: vrev64.8 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <4 x i32>, <4 x i32>* %p
+ %1 = load <4 x i32>, ptr %p
%2 = add <4 x i32> %1, %1
%3 = call <16 x i8> @test_v16i8_v4i32_helper(<4 x i32> %2)
%4 = add <16 x i8> %3, %3
- store <16 x i8> %4, <16 x i8>* %q
+ store <16 x i8> %4, ptr %q
ret void
}
declare <16 x i8> @test_v16i8_v8i16_helper(<8 x i16> %p)
-define void @test_v16i8_v8i16(<8 x i16>* %p, <16 x i8>* %q) {
+define void @test_v16i8_v8i16(ptr %p, ptr %q) {
; SOFT-LABEL: test_v16i8_v8i16:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, lr}
@@ -3547,10 +3547,10 @@ define void @test_v16i8_v8i16(<8 x i16>* %p, <16 x i8>* %q) {
; HARD-NEXT: vrev64.8 q8, q8
; HARD-NEXT: vst1.64 {d16, d17}, [r4]
; HARD-NEXT: pop {r4, pc}
- %1 = load <8 x i16>, <8 x i16>* %p
+ %1 = load <8 x i16>, ptr %p
%2 = add <8 x i16> %1, %1
%3 = call <16 x i8> @test_v16i8_v8i16_helper(<8 x i16> %2)
%4 = add <16 x i8> %3, %3
- store <16 x i8> %4, <16 x i8>* %q
+ store <16 x i8> %4, ptr %q
ret void
}
diff --git a/llvm/test/CodeGen/ARM/bit-reverse-to-rbit.ll b/llvm/test/CodeGen/ARM/bit-reverse-to-rbit.ll
index cc1d6ca989947..4eb4a722e22ee 100644
--- a/llvm/test/CodeGen/ARM/bit-reverse-to-rbit.ll
+++ b/llvm/test/CodeGen/ARM/bit-reverse-to-rbit.ll
@@ -8,7 +8,7 @@
;CHECK-NOT: rbit
;RBIT: rbit
-define void @byte_reversal(i8* %p, i32 %n) {
+define void @byte_reversal(ptr %p, i32 %n) {
entry:
br label %for.cond
@@ -19,10 +19,10 @@ for.cond: ; preds = %for.body, %entry
for.body: ; preds = %for.cond
%0 = sext i32 %i.0 to i64
- %arrayidx = getelementptr inbounds i8, i8* %p, i64 %0
- %1 = load i8, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds i8, ptr %p, i64 %0
+ %1 = load i8, ptr %arrayidx, align 1
%or19 = call i8 @llvm.bitreverse.i8(i8 %1)
- store i8 %or19, i8* %arrayidx, align 1
+ store i8 %or19, ptr %arrayidx, align 1
%inc = add i32 %i.0, 1
br label %for.cond
diff --git a/llvm/test/CodeGen/ARM/branch-on-zero.ll b/llvm/test/CodeGen/ARM/branch-on-zero.ll
index 65fea323db0ca..575176fc013c6 100644
--- a/llvm/test/CodeGen/ARM/branch-on-zero.ll
+++ b/llvm/test/CodeGen/ARM/branch-on-zero.ll
@@ -4,7 +4,7 @@
; RUN: llc -mtriple thumbv8.1m.main-none-eabi -mattr=+mve,+lob -o - %s | FileCheck %s --check-prefix=CHECK-V81M
; RUN: llc -mtriple armv7a-none-eabi -o - %s | FileCheck %s --check-prefix=CHECK-V7A
-define i32 @test_lshr(i32* nocapture %x, i32* nocapture readonly %y, i32 %n) {
+define i32 @test_lshr(ptr nocapture %x, ptr nocapture readonly %y, i32 %n) {
; CHECK-V6M-LABEL: test_lshr:
; CHECK-V6M: @ %bb.0: @ %entry
; CHECK-V6M-NEXT: lsrs r2, r2, #2
@@ -75,13 +75,13 @@ entry:
while.body: ; preds = %entry, %while.body
%c.07 = phi i32 [ %dec, %while.body ], [ %shr, %entry ]
- %x.addr.06 = phi i32* [ %incdec.ptr1, %while.body ], [ %x, %entry ]
- %y.addr.05 = phi i32* [ %incdec.ptr, %while.body ], [ %y, %entry ]
- %incdec.ptr = getelementptr inbounds i32, i32* %y.addr.05, i32 1
- %0 = load i32, i32* %y.addr.05, align 4
+ %x.addr.06 = phi ptr [ %incdec.ptr1, %while.body ], [ %x, %entry ]
+ %y.addr.05 = phi ptr [ %incdec.ptr, %while.body ], [ %y, %entry ]
+ %incdec.ptr = getelementptr inbounds i32, ptr %y.addr.05, i32 1
+ %0 = load i32, ptr %y.addr.05, align 4
%mul = shl nsw i32 %0, 1
- %incdec.ptr1 = getelementptr inbounds i32, i32* %x.addr.06, i32 1
- store i32 %mul, i32* %x.addr.06, align 4
+ %incdec.ptr1 = getelementptr inbounds i32, ptr %x.addr.06, i32 1
+ store i32 %mul, ptr %x.addr.06, align 4
%dec = add nsw i32 %c.07, -1
%tobool.not = icmp eq i32 %dec, 0
br i1 %tobool.not, label %while.end, label %while.body
@@ -90,7 +90,7 @@ while.end: ; preds = %while.body, %entry
ret i32 0
}
-define i32 @test_lshr2(i32* nocapture %x, i32* nocapture readonly %y, i32 %n) {
+define i32 @test_lshr2(ptr nocapture %x, ptr nocapture readonly %y, i32 %n) {
; CHECK-V6M-LABEL: test_lshr2:
; CHECK-V6M: @ %bb.0: @ %entry
; CHECK-V6M-NEXT: lsrs r2, r2, #2
@@ -164,13 +164,13 @@ while.body.preheader: ; preds = %entry
while.body: ; preds = %while.body.preheader, %while.body
%c.07 = phi i32 [ %dec, %while.body ], [ %shr, %while.body.preheader ]
- %x.addr.06 = phi i32* [ %incdec.ptr1, %while.body ], [ %x, %while.body.preheader ]
- %y.addr.05 = phi i32* [ %incdec.ptr, %while.body ], [ %y, %while.body.preheader ]
- %incdec.ptr = getelementptr inbounds i32, i32* %y.addr.05, i32 1
- %0 = load i32, i32* %y.addr.05, align 4
+ %x.addr.06 = phi ptr [ %incdec.ptr1, %while.body ], [ %x, %while.body.preheader ]
+ %y.addr.05 = phi ptr [ %incdec.ptr, %while.body ], [ %y, %while.body.preheader ]
+ %incdec.ptr = getelementptr inbounds i32, ptr %y.addr.05, i32 1
+ %0 = load i32, ptr %y.addr.05, align 4
%mul = shl nsw i32 %0, 1
- %incdec.ptr1 = getelementptr inbounds i32, i32* %x.addr.06, i32 1
- store i32 %mul, i32* %x.addr.06, align 4
+ %incdec.ptr1 = getelementptr inbounds i32, ptr %x.addr.06, i32 1
+ store i32 %mul, ptr %x.addr.06, align 4
%dec = add nsw i32 %c.07, -1
%tobool.not = icmp eq i32 %dec, 0
br i1 %tobool.not, label %while.end, label %while.body
diff --git a/llvm/test/CodeGen/ARM/bswap16.ll b/llvm/test/CodeGen/ARM/bswap16.ll
index f046619f4e688..d84a4ce0acf77 100644
--- a/llvm/test/CodeGen/ARM/bswap16.ll
+++ b/llvm/test/CodeGen/ARM/bswap16.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=arm-darwin -mattr=v6 | FileCheck %s --check-prefixes=CHECK
; RUN: llc < %s -mtriple=thumb-darwin -mattr=v6 | FileCheck %s --check-prefixes=CHECK
-define void @test1(i16* nocapture %data) {
+define void @test1(ptr nocapture %data) {
; CHECK-LABEL: test1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r1, [r0]
@@ -10,13 +10,13 @@ define void @test1(i16* nocapture %data) {
; CHECK-NEXT: strh r1, [r0]
; CHECK-NEXT: bx lr
entry:
- %0 = load i16, i16* %data, align 2
+ %0 = load i16, ptr %data, align 2
%1 = tail call i16 @llvm.bswap.i16(i16 %0)
- store i16 %1, i16* %data, align 2
+ store i16 %1, ptr %data, align 2
ret void
}
-define void @test2(i16* nocapture %data, i16 zeroext %in) {
+define void @test2(ptr nocapture %data, i16 zeroext %in) {
; CHECK-LABEL: test2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: rev16 r1, r1
@@ -24,18 +24,18 @@ define void @test2(i16* nocapture %data, i16 zeroext %in) {
; CHECK-NEXT: bx lr
entry:
%0 = tail call i16 @llvm.bswap.i16(i16 %in)
- store i16 %0, i16* %data, align 2
+ store i16 %0, ptr %data, align 2
ret void
}
-define i16 @test3(i16* nocapture %data) {
+define i16 @test3(ptr nocapture %data) {
; CHECK-LABEL: test3:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r0, [r0]
; CHECK-NEXT: rev16 r0, r0
; CHECK-NEXT: bx lr
entry:
- %0 = load i16, i16* %data, align 2
+ %0 = load i16, ptr %data, align 2
%1 = tail call i16 @llvm.bswap.i16(i16 %0)
ret i16 %1
}
diff --git a/llvm/test/CodeGen/ARM/bx_fold.ll b/llvm/test/CodeGen/ARM/bx_fold.ll
index f6651ae8004ef..42fdd8dd028e5 100644
--- a/llvm/test/CodeGen/ARM/bx_fold.ll
+++ b/llvm/test/CodeGen/ARM/bx_fold.ll
@@ -1,13 +1,13 @@
; RUN: llc < %s -mtriple=armv5t-apple-darwin | FileCheck %s
-define void @test(i32 %Ptr, i8* %L) {
+define void @test(i32 %Ptr, ptr %L) {
entry:
br label %bb1
bb: ; preds = %bb1
%gep.upgrd.1 = zext i32 %indvar to i64 ; <i64> [#uses=1]
- %tmp7 = getelementptr i8, i8* %L, i64 %gep.upgrd.1 ; <i8*> [#uses=1]
- store i8 0, i8* %tmp7
+ %tmp7 = getelementptr i8, ptr %L, i64 %gep.upgrd.1 ; <ptr> [#uses=1]
+ store i8 0, ptr %tmp7
%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
br label %bb1
diff --git a/llvm/test/CodeGen/ARM/byval-align.ll b/llvm/test/CodeGen/ARM/byval-align.ll
index e3fe15c701066..00d3eda03a9a1 100644
--- a/llvm/test/CodeGen/ARM/byval-align.ll
+++ b/llvm/test/CodeGen/ARM/byval-align.ll
@@ -5,8 +5,8 @@
; simplifying refactoring; at the time of writing there were no actual APCS
; users of byval alignments > 4, so no real calls for ABI stability.
-; "byval align 16" can't fit in any regs with an i8* taking up r0.
-define i32 @test_align16(i8*, [4 x i32]* byval([4 x i32]) align 16 %b) {
+; "byval align 16" can't fit in any regs with an ptr taking up r0.
+define i32 @test_align16(ptr, ptr byval([4 x i32]) align 16 %b) {
; CHECK-LABEL: test_align16:
; CHECK-NOT: sub sp
; CHECK: push {r4, r7, lr}
@@ -15,14 +15,13 @@ define i32 @test_align16(i8*, [4 x i32]* byval([4 x i32]) align 16 %b) {
; CHECK: ldr r0, [r7, #8]
call void @bar()
- %valptr = getelementptr [4 x i32], [4 x i32]* %b, i32 0, i32 0
- %val = load i32, i32* %valptr
+ %val = load i32, ptr %b
ret i32 %val
}
; byval align 8 can, but we used to incorrectly set r7 here (miscalculating the
; space taken up by arg regs).
-define i32 @test_align8(i8*, [4 x i32]* byval([4 x i32]) align 8 %b) {
+define i32 @test_align8(ptr, ptr byval([4 x i32]) align 8 %b) {
; CHECK-LABEL: test_align8:
; CHECK: sub sp, #8
; CHECK: push {r4, r7, lr}
@@ -33,14 +32,13 @@ define i32 @test_align8(i8*, [4 x i32]* byval([4 x i32]) align 8 %b) {
; CHECK: ldr r0, [r7, #8]
call void @bar()
- %valptr = getelementptr [4 x i32], [4 x i32]* %b, i32 0, i32 0
- %val = load i32, i32* %valptr
+ %val = load i32, ptr %b
ret i32 %val
}
; "byval align 32" can't fit in regs no matter what: it would be misaligned
; unless the incoming stack was deliberately misaligned.
-define i32 @test_align32(i8*, [4 x i32]* byval([4 x i32]) align 32 %b) {
+define i32 @test_align32(ptr, ptr byval([4 x i32]) align 32 %b) {
; CHECK-LABEL: test_align32:
; CHECK-NOT: sub sp
; CHECK: push {r4, r7, lr}
@@ -49,8 +47,7 @@ define i32 @test_align32(i8*, [4 x i32]* byval([4 x i32]) align 32 %b) {
; CHECK: ldr r0, [r7, #8]
call void @bar()
- %valptr = getelementptr [4 x i32], [4 x i32]* %b, i32 0, i32 0
- %val = load i32, i32* %valptr
+ %val = load i32, ptr %b
ret i32 %val
}
@@ -67,7 +64,7 @@ define void @test_call_align16() {
; While we're here, make sure the caller also puts it at sp
; CHECK: mov r[[BASE:[0-9]+]], sp
; CHECK: vst1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]]
- call i32 @test_align16(i8* null, [4 x i32]* byval([4 x i32]) align 16 @var)
+ call i32 @test_align16(ptr null, ptr byval([4 x i32]) align 16 @var)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/byval_load_align.ll b/llvm/test/CodeGen/ARM/byval_load_align.ll
index 90eaa333bb0d5..c594bd38a0b31 100644
--- a/llvm/test/CodeGen/ARM/byval_load_align.ll
+++ b/llvm/test/CodeGen/ARM/byval_load_align.ll
@@ -16,11 +16,11 @@
; Function Attrs: nounwind ssp
define void @Client() #0 {
entry:
- tail call void @Logger(i8 signext 97, %struct.ModuleID* byval(%struct.ModuleID) @sID) #2
+ tail call void @Logger(i8 signext 97, ptr byval(%struct.ModuleID) @sID) #2
ret void
}
-declare void @Logger(i8 signext, %struct.ModuleID* byval(%struct.ModuleID)) #1
+declare void @Logger(i8 signext, ptr byval(%struct.ModuleID)) #1
attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/CodeGen/ARM/cache-intrinsic.ll b/llvm/test/CodeGen/ARM/cache-intrinsic.ll
index 12b55c7081dbc..571ce568a926e 100644
--- a/llvm/test/CodeGen/ARM/cache-intrinsic.ll
+++ b/llvm/test/CodeGen/ARM/cache-intrinsic.ll
@@ -9,18 +9,18 @@ target triple = "armv7--linux-gnueabihf"
define i32 @main() {
entry:
%retval = alloca i32, align 4
- store i32 0, i32* %retval
- %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0))
- %call1 = call i8* @strcpy(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str1, i32 0, i32 0)) #3
- call void @llvm.clear_cache(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds (i8, i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i32 32)) #3
- %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0))
+ store i32 0, ptr %retval
+ %call = call i32 (ptr, ...) @printf(ptr @.str, ptr @buffer)
+ %call1 = call ptr @strcpy(ptr @buffer, ptr @.str1) #3
+ call void @llvm.clear_cache(ptr @buffer, ptr getelementptr inbounds (i8, ptr @buffer, i32 32)) #3
+ %call2 = call i32 (ptr, ...) @printf(ptr @.str, ptr @buffer)
ret i32 0
}
; CHECK: __clear_cache
-declare i32 @printf(i8*, ...)
+declare i32 @printf(ptr, ...)
-declare i8* @strcpy(i8*, i8*)
+declare ptr @strcpy(ptr, ptr)
-declare void @llvm.clear_cache(i8*, i8*)
+declare void @llvm.clear_cache(ptr, ptr)
diff --git a/llvm/test/CodeGen/ARM/call-tc.ll b/llvm/test/CodeGen/ARM/call-tc.ll
index 3ebaa7b025c77..18d83bdc03e22 100644
--- a/llvm/test/CodeGen/ARM/call-tc.ll
+++ b/llvm/test/CodeGen/ARM/call-tc.ll
@@ -6,7 +6,7 @@
; Enable tailcall optimization for iOS 5.0
; rdar://9120031
- at t = weak global i32 ()* null ; <i32 ()**> [#uses=1]
+ at t = weak global ptr null ; <ptr> [#uses=1]
declare void @g(i32, i32, i32, i32)
@@ -24,7 +24,7 @@ define void @t2() "frame-pointer"="all" {
; CHECKT2D: ldr
; CHECKT2D-NEXT: ldr
; CHECKT2D-NEXT: bx r0
- %tmp = load i32 ()*, i32 ()** @t ; <i32 ()*> [#uses=1]
+ %tmp = load ptr, ptr @t ; <ptr> [#uses=1]
%tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0]
ret void
}
@@ -155,27 +155,27 @@ define i32 @t9() nounwind "frame-pointer"="all" {
; CHECKT2D: bl __ZN9MutexLockD1Ev
; CHECKT2D: b.w ___divsi3
%lock = alloca %class.MutexLock, align 1
- %1 = call %class.MutexLock* @_ZN9MutexLockC1Ev(%class.MutexLock* %lock)
- %2 = load i32, i32* @x, align 4
+ %1 = call ptr @_ZN9MutexLockC1Ev(ptr %lock)
+ %2 = load i32, ptr @x, align 4
%3 = sdiv i32 1000, %2
- %4 = call %class.MutexLock* @_ZN9MutexLockD1Ev(%class.MutexLock* %lock)
+ %4 = call ptr @_ZN9MutexLockD1Ev(ptr %lock)
ret i32 %3
}
-declare %class.MutexLock* @_ZN9MutexLockC1Ev(%class.MutexLock*) unnamed_addr nounwind align 2
+declare ptr @_ZN9MutexLockC1Ev(ptr) unnamed_addr nounwind align 2
-declare %class.MutexLock* @_ZN9MutexLockD1Ev(%class.MutexLock*) unnamed_addr nounwind align 2
+declare ptr @_ZN9MutexLockD1Ev(ptr) unnamed_addr nounwind align 2
; rdar://13827621
; Correctly preserve the input chain for the tailcall node in the bitcast case,
; otherwise the call to floorf is lost.
-define float @libcall_tc_test2(float* nocapture %a, float %b) "frame-pointer"="all" {
+define float @libcall_tc_test2(ptr nocapture %a, float %b) "frame-pointer"="all" {
; CHECKT2D-LABEL: libcall_tc_test2:
; CHECKT2D: bl _floorf
; CHECKT2D: b.w _truncf
- %1 = load float, float* %a, align 4
+ %1 = load float, ptr %a, align 4
%call = tail call float @floorf(float %1)
- store float %call, float* %a, align 4
+ store float %call, ptr %a, align 4
%call1 = tail call float @truncf(float %b)
ret float %call1
}
diff --git a/llvm/test/CodeGen/ARM/call.ll b/llvm/test/CodeGen/ARM/call.ll
index 05ea556e234cf..45e3e99b6d838 100644
--- a/llvm/test/CodeGen/ARM/call.ll
+++ b/llvm/test/CodeGen/ARM/call.ll
@@ -7,7 +7,7 @@
; RUN: llc -mtriple=armv6-linux-gnueabi -relocation-model=pic %s -o - \
; RUN: | FileCheck %s -check-prefix=CHECKELF
- at t = weak global i32 ()* null ; <i32 ()**> [#uses=1]
+ at t = weak global ptr null ; <ptr> [#uses=1]
declare void @g(i32, i32, i32, i32)
@@ -20,21 +20,20 @@ define void @f() {
define void @g.upgrd.1() {
; CHECKV4: mov lr, pc
; CHECKV5: blx
- %tmp = load i32 ()*, i32 ()** @t ; <i32 ()*> [#uses=1]
+ %tmp = load ptr, ptr @t ; <ptr> [#uses=1]
%tmp.upgrd.2 = call i32 %tmp( ) ; <i32> [#uses=0]
ret void
}
-define i32* @m_231b(i32, i32, i32*, i32*, i32*) nounwind {
+define ptr @m_231b(i32, i32, ptr, ptr, ptr) nounwind {
; CHECKV4: m_231b
; CHECKV4: bx r{{.*}}
BB0:
- %5 = inttoptr i32 %0 to i32* ; <i32*> [#uses=1]
- %t35 = load volatile i32, i32* %5 ; <i32> [#uses=1]
- %6 = inttoptr i32 %t35 to i32** ; <i32**> [#uses=1]
- %7 = getelementptr i32*, i32** %6, i32 86 ; <i32**> [#uses=1]
- %8 = load i32*, i32** %7 ; <i32*> [#uses=1]
- %9 = bitcast i32* %8 to i32* (i32, i32*, i32, i32*, i32*, i32*)* ; <i32* (i32, i32*, i32, i32*, i32*, i32*)*> [#uses=1]
- %10 = call i32* %9(i32 %0, i32* null, i32 %1, i32* %2, i32* %3, i32* %4) ; <i32*> [#uses=1]
- ret i32* %10
+ %5 = inttoptr i32 %0 to ptr ; <ptr> [#uses=1]
+ %t35 = load volatile i32, ptr %5 ; <i32> [#uses=1]
+ %6 = inttoptr i32 %t35 to ptr ; <ptr> [#uses=1]
+ %7 = getelementptr ptr, ptr %6, i32 86 ; <ptr> [#uses=1]
+ %8 = load ptr, ptr %7 ; <ptr> [#uses=1]
+ %9 = call ptr %8(i32 %0, ptr null, i32 %1, ptr %2, ptr %3, ptr %4) ; <ptr> [#uses=1]
+ ret ptr %9
}
diff --git a/llvm/test/CodeGen/ARM/call_nolink.ll b/llvm/test/CodeGen/ARM/call_nolink.ll
index 6a36a1e380734..336c1cc77ea30 100644
--- a/llvm/test/CodeGen/ARM/call_nolink.ll
+++ b/llvm/test/CodeGen/ARM/call_nolink.ll
@@ -1,11 +1,11 @@
; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
- %struct.anon = type { i32 (i32, i32, i32)*, i32, i32, [3 x i32], i8*, i8*, i8* }
- at r = external global [14 x i32] ; <[14 x i32]*> [#uses=4]
- at isa = external global [13 x %struct.anon] ; <[13 x %struct.anon]*> [#uses=1]
- at pgm = external global [2 x { i32, [3 x i32] }] ; <[2 x { i32, [3 x i32] }]*> [#uses=4]
- at numi = external global i32 ; <i32*> [#uses=1]
- at counter = external global [2 x i32] ; <[2 x i32]*> [#uses=1]
+ %struct.anon = type { ptr, i32, i32, [3 x i32], ptr, ptr, ptr }
+ at r = external global [14 x i32] ; <ptr> [#uses=4]
+ at isa = external global [13 x %struct.anon] ; <ptr> [#uses=1]
+ at pgm = external global [2 x { i32, [3 x i32] }] ; <ptr> [#uses=4]
+ at numi = external global i32 ; <ptr> [#uses=1]
+ at counter = external global [2 x i32] ; <ptr> [#uses=1]
; CHECK-LABEL: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i:
; CHECK-NOT: bx lr
@@ -22,37 +22,37 @@ bb115.i.i.bb115.i.i_crit_edge: ; preds = %bb115.i.i
bb115.i.i: ; preds = %bb115.i.i.bb115.i.i_crit_edge, %newFuncRoot
%i_addr.3210.0.i.i = phi i32 [ %tmp166.i.i, %bb115.i.i.bb115.i.i_crit_edge ], [ 0, %newFuncRoot ] ; <i32> [#uses=7]
- %tmp124.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 0 ; <i32*> [#uses=1]
- %tmp125.i.i = load i32, i32* %tmp124.i.i ; <i32> [#uses=1]
- %tmp126.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp125.i.i ; <i32*> [#uses=1]
- %tmp127.i.i = load i32, i32* %tmp126.i.i ; <i32> [#uses=1]
- %tmp131.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 1 ; <i32*> [#uses=1]
- %tmp132.i.i = load i32, i32* %tmp131.i.i ; <i32> [#uses=1]
- %tmp133.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp132.i.i ; <i32*> [#uses=1]
- %tmp134.i.i = load i32, i32* %tmp133.i.i ; <i32> [#uses=1]
- %tmp138.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 2 ; <i32*> [#uses=1]
- %tmp139.i.i = load i32, i32* %tmp138.i.i ; <i32> [#uses=1]
- %tmp140.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp139.i.i ; <i32*> [#uses=1]
- %tmp141.i.i = load i32, i32* %tmp140.i.i ; <i32> [#uses=1]
+ %tmp124.i.i = getelementptr [2 x { i32, [3 x i32] }], ptr @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 0 ; <ptr> [#uses=1]
+ %tmp125.i.i = load i32, ptr %tmp124.i.i ; <i32> [#uses=1]
+ %tmp126.i.i = getelementptr [14 x i32], ptr @r, i32 0, i32 %tmp125.i.i ; <ptr> [#uses=1]
+ %tmp127.i.i = load i32, ptr %tmp126.i.i ; <i32> [#uses=1]
+ %tmp131.i.i = getelementptr [2 x { i32, [3 x i32] }], ptr @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 1 ; <ptr> [#uses=1]
+ %tmp132.i.i = load i32, ptr %tmp131.i.i ; <i32> [#uses=1]
+ %tmp133.i.i = getelementptr [14 x i32], ptr @r, i32 0, i32 %tmp132.i.i ; <ptr> [#uses=1]
+ %tmp134.i.i = load i32, ptr %tmp133.i.i ; <i32> [#uses=1]
+ %tmp138.i.i = getelementptr [2 x { i32, [3 x i32] }], ptr @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 2 ; <ptr> [#uses=1]
+ %tmp139.i.i = load i32, ptr %tmp138.i.i ; <i32> [#uses=1]
+ %tmp140.i.i = getelementptr [14 x i32], ptr @r, i32 0, i32 %tmp139.i.i ; <ptr> [#uses=1]
+ %tmp141.i.i = load i32, ptr %tmp140.i.i ; <i32> [#uses=1]
%tmp143.i.i = add i32 %i_addr.3210.0.i.i, 12 ; <i32> [#uses=1]
- %tmp146.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 0 ; <i32*> [#uses=1]
- %tmp147.i.i = load i32, i32* %tmp146.i.i ; <i32> [#uses=1]
- %tmp149.i.i = getelementptr [13 x %struct.anon], [13 x %struct.anon]* @isa, i32 0, i32 %tmp147.i.i, i32 0 ; <i32 (i32, i32, i32)**> [#uses=1]
- %tmp150.i.i = load i32 (i32, i32, i32)*, i32 (i32, i32, i32)** %tmp149.i.i ; <i32 (i32, i32, i32)*> [#uses=1]
+ %tmp146.i.i = getelementptr [2 x { i32, [3 x i32] }], ptr @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 0 ; <ptr> [#uses=1]
+ %tmp147.i.i = load i32, ptr %tmp146.i.i ; <i32> [#uses=1]
+ %tmp149.i.i = getelementptr [13 x %struct.anon], ptr @isa, i32 0, i32 %tmp147.i.i, i32 0 ; <ptr> [#uses=1]
+ %tmp150.i.i = load ptr, ptr %tmp149.i.i ; <ptr> [#uses=1]
%tmp154.i.i = tail call i32 %tmp150.i.i( i32 %tmp127.i.i, i32 %tmp134.i.i, i32 %tmp141.i.i ) ; <i32> [#uses=1]
- %tmp155.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp143.i.i ; <i32*> [#uses=1]
- store i32 %tmp154.i.i, i32* %tmp155.i.i
- %tmp159.i.i = getelementptr [2 x i32], [2 x i32]* @counter, i32 0, i32 %i_addr.3210.0.i.i ; <i32*> [#uses=2]
- %tmp160.i.i = load i32, i32* %tmp159.i.i ; <i32> [#uses=1]
+ %tmp155.i.i = getelementptr [14 x i32], ptr @r, i32 0, i32 %tmp143.i.i ; <ptr> [#uses=1]
+ store i32 %tmp154.i.i, ptr %tmp155.i.i
+ %tmp159.i.i = getelementptr [2 x i32], ptr @counter, i32 0, i32 %i_addr.3210.0.i.i ; <ptr> [#uses=2]
+ %tmp160.i.i = load i32, ptr %tmp159.i.i ; <i32> [#uses=1]
%tmp161.i.i = add i32 %tmp160.i.i, 1 ; <i32> [#uses=1]
- store i32 %tmp161.i.i, i32* %tmp159.i.i
+ store i32 %tmp161.i.i, ptr %tmp159.i.i
%tmp166.i.i = add i32 %i_addr.3210.0.i.i, 1 ; <i32> [#uses=2]
- %tmp168.i.i = load i32, i32* @numi ; <i32> [#uses=1]
+ %tmp168.i.i = load i32, ptr @numi ; <i32> [#uses=1]
icmp slt i32 %tmp166.i.i, %tmp168.i.i ; <i1>:0 [#uses=1]
br i1 %0, label %bb115.i.i.bb115.i.i_crit_edge, label %bb115.i.i.bb170.i.i_crit_edge.exitStub
}
-define void @PR15520(void ()* %fn) {
+define void @PR15520(ptr %fn) {
call void %fn()
ret void
diff --git a/llvm/test/CodeGen/ARM/cfguard-checks.ll b/llvm/test/CodeGen/ARM/cfguard-checks.ll
index ed8bb78cd7c68..adf969118ec4f 100644
--- a/llvm/test/CodeGen/ARM/cfguard-checks.ll
+++ b/llvm/test/CodeGen/ARM/cfguard-checks.ll
@@ -11,9 +11,9 @@ declare i32 @target_func()
; Test that Control Flow Guard checks are not added on calls with the "guard_nocf" attribute.
define i32 @func_guard_nocf() #0 {
entry:
- %func_ptr = alloca i32 ()*, align 8
- store i32 ()* @target_func, i32 ()** %func_ptr, align 8
- %0 = load i32 ()*, i32 ()** %func_ptr, align 8
+ %func_ptr = alloca ptr, align 8
+ store ptr @target_func, ptr %func_ptr, align 8
+ %0 = load ptr, ptr %func_ptr, align 8
%1 = call arm_aapcs_vfpcc i32 %0() #1
ret i32 %1
@@ -30,9 +30,9 @@ attributes #1 = { "guard_nocf" }
; Test that Control Flow Guard checks are added even at -O0.
define i32 @func_optnone_cf() #2 {
entry:
- %func_ptr = alloca i32 ()*, align 8
- store i32 ()* @target_func, i32 ()** %func_ptr, align 8
- %0 = load i32 ()*, i32 ()** %func_ptr, align 8
+ %func_ptr = alloca ptr, align 8
+ store ptr @target_func, ptr %func_ptr, align 8
+ %0 = load ptr, ptr %func_ptr, align 8
%1 = call i32 %0()
ret i32 %1
@@ -55,9 +55,9 @@ attributes #2 = { noinline optnone "target-cpu"="cortex-a9" "target-features"="+
; Test that Control Flow Guard checks are correctly added in optimized code (common case).
define i32 @func_cf() #0 {
entry:
- %func_ptr = alloca i32 ()*, align 8
- store i32 ()* @target_func, i32 ()** %func_ptr, align 8
- %0 = load i32 ()*, i32 ()** %func_ptr, align 8
+ %func_ptr = alloca ptr, align 8
+ store ptr @target_func, ptr %func_ptr, align 8
+ %0 = load ptr, ptr %func_ptr, align 8
%1 = call i32 %0()
ret i32 %1
@@ -75,20 +75,20 @@ entry:
; Test that Control Flow Guard checks are correctly added on invoke instructions.
-define i32 @func_cf_invoke() #0 personality i8* bitcast (void ()* @h to i8*) {
+define i32 @func_cf_invoke() #0 personality ptr @h {
entry:
%0 = alloca i32, align 4
- %func_ptr = alloca i32 ()*, align 8
- store i32 ()* @target_func, i32 ()** %func_ptr, align 8
- %1 = load i32 ()*, i32 ()** %func_ptr, align 8
+ %func_ptr = alloca ptr, align 8
+ store ptr @target_func, ptr %func_ptr, align 8
+ %1 = load ptr, ptr %func_ptr, align 8
%2 = invoke i32 %1()
to label %invoke.cont unwind label %lpad
invoke.cont: ; preds = %entry
ret i32 %2
lpad: ; preds = %entry
- %tmp = landingpad { i8*, i32 }
- catch i8* null
+ %tmp = landingpad { ptr, i32 }
+ catch ptr null
ret i32 -1
; The call to __guard_check_icall_fptr should come immediately before the call to the target function.
@@ -117,23 +117,23 @@ declare void @h()
define i32 @func_cf_setjmp() #0 {
%1 = alloca i32, align 4
%2 = alloca i32, align 4
- store i32 0, i32* %1, align 4
- store i32 -1, i32* %2, align 4
- %3 = call i8* @llvm.frameaddress(i32 0)
- %4 = call i32 @_setjmp(i8* bitcast ([16 x %struct._SETJMP_FLOAT128]* @buf1 to i8*), i8* %3) #3
+ store i32 0, ptr %1, align 4
+ store i32 -1, ptr %2, align 4
+ %3 = call ptr @llvm.frameaddress(i32 0)
+ %4 = call i32 @_setjmp(ptr @buf1, ptr %3) #3
; CHECK-LABEL: func_cf_setjmp
; CHECK: bl _setjmp
; CHECK-NEXT: $cfgsj_func_cf_setjmp0:
- %5 = call i8* @llvm.frameaddress(i32 0)
- %6 = call i32 @_setjmp(i8* bitcast ([16 x %struct._SETJMP_FLOAT128]* @buf1 to i8*), i8* %5) #3
+ %5 = call ptr @llvm.frameaddress(i32 0)
+ %6 = call i32 @_setjmp(ptr @buf1, ptr %5) #3
; CHECK: bl _setjmp
; CHECK-NEXT: $cfgsj_func_cf_setjmp1:
- store i32 1, i32* %2, align 4
- %7 = load i32, i32* %2, align 4
+ store i32 1, ptr %2, align 4
+ %7 = load i32, ptr %2, align 4
ret i32 %7
; CHECK: .section .gljmp$y,"dr"
@@ -141,10 +141,10 @@ define i32 @func_cf_setjmp() #0 {
; CHECK-NEXT: .symidx $cfgsj_func_cf_setjmp1
}
-declare i8* @llvm.frameaddress(i32)
+declare ptr @llvm.frameaddress(i32)
; Function Attrs: returns_twice
-declare dso_local i32 @_setjmp(i8*, i8*) #3
+declare dso_local i32 @_setjmp(ptr, ptr) #3
attributes #3 = { returns_twice }
diff --git a/llvm/test/CodeGen/ARM/cfguard-module-flag.ll b/llvm/test/CodeGen/ARM/cfguard-module-flag.ll
index 4b6dedefc298a..3e8c9f4e2198a 100644
--- a/llvm/test/CodeGen/ARM/cfguard-module-flag.ll
+++ b/llvm/test/CodeGen/ARM/cfguard-module-flag.ll
@@ -11,9 +11,9 @@ declare void @target_func()
define void @func_in_module_without_cfguard() #0 {
entry:
- %func_ptr = alloca void ()*, align 8
- store void ()* @target_func, void ()** %func_ptr, align 8
- %0 = load void ()*, void ()** %func_ptr, align 8
+ %func_ptr = alloca ptr, align 8
+ store ptr @target_func, ptr %func_ptr, align 8
+ %0 = load ptr, ptr %func_ptr, align 8
call void %0()
ret void
diff --git a/llvm/test/CodeGen/ARM/cfi-alignment.ll b/llvm/test/CodeGen/ARM/cfi-alignment.ll
index 11add22426569..9974be2435758 100644
--- a/llvm/test/CodeGen/ARM/cfi-alignment.ll
+++ b/llvm/test/CodeGen/ARM/cfi-alignment.ll
@@ -29,7 +29,7 @@ define void @variadic_foo(i8, ...) {
; CHECK: .cfi_offset d9, -40
; CHECK: .cfi_offset d8, -48
call void asm sideeffect "", "~{d8},~{d9},~{d11}"()
- call void @llvm.va_start(i8* null)
+ call void @llvm.va_start(ptr null)
call void @bar()
ret void
}
@@ -45,4 +45,4 @@ define void @test_maintain_stack_align() {
}
declare void @bar()
-declare void @llvm.va_start(i8*) nounwind
+declare void @llvm.va_start(ptr) nounwind
diff --git a/llvm/test/CodeGen/ARM/clang-section.ll b/llvm/test/CodeGen/ARM/clang-section.ll
index c787d4817497b..4e896a2447dd4 100644
--- a/llvm/test/CodeGen/ARM/clang-section.ll
+++ b/llvm/test/CodeGen/ARM/clang-section.ll
@@ -25,23 +25,23 @@ target triple = "armv7-arm-none-eabi"
; Function Attrs: noinline nounwind
define i32 @foo() #4 {
entry:
- %0 = load i32, i32* @b, align 4
+ %0 = load i32, ptr @b, align 4
ret i32 %0
}
; Function Attrs: noinline
define i32 @goo() #5 {
entry:
- %call = call i32 @zoo(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZL1g, i32 0, i32 0), i32* @_ZZ3gooE7lstat_h)
+ %call = call i32 @zoo(ptr @_ZL1g, ptr @_ZZ3gooE7lstat_h)
ret i32 %call
}
-declare i32 @zoo(i32*, i32*) #6
+declare i32 @zoo(ptr, ptr) #6
; Function Attrs: noinline nounwind
define i32 @hoo() #7 {
entry:
- %0 = load i32, i32* @b, align 4
+ %0 = load i32, ptr @b, align 4
ret i32 %0
}
diff --git a/llvm/test/CodeGen/ARM/cmp-bool.ll b/llvm/test/CodeGen/ARM/cmp-bool.ll
index 9d83ee8c81a44..5c952c6ea9ce8 100644
--- a/llvm/test/CodeGen/ARM/cmp-bool.ll
+++ b/llvm/test/CodeGen/ARM/cmp-bool.ll
@@ -3,7 +3,7 @@
; RUN: llc -mtriple=armv6m < %s | FileCheck %s --check-prefix=THUMB
; RUN: llc -mtriple=armv7m < %s | FileCheck %s --check-prefix=THUMB2
-define void @bool_eq(i1 zeroext %a, i1 zeroext %b, void ()* nocapture %c) nounwind {
+define void @bool_eq(i1 zeroext %a, i1 zeroext %b, ptr nocapture %c) nounwind {
; ARM-LABEL: bool_eq:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: cmp r0, r1
@@ -40,7 +40,7 @@ if.end:
ret void
}
-define void @bool_ne(i1 zeroext %a, i1 zeroext %b, void ()* nocapture %c) nounwind {
+define void @bool_ne(i1 zeroext %a, i1 zeroext %b, ptr nocapture %c) nounwind {
; ARM-LABEL: bool_ne:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: cmp r0, r1
diff --git a/llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll b/llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll
index 67baec1810f28..32c66985f3bdc 100644
--- a/llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll
+++ b/llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll
@@ -15,10 +15,10 @@
define arm_aapcs_vfpcc i32 @main() #0 {
entry:
%retval = alloca i32, align 4
- store i32 0, i32* %retval, align 4
- %0 = load i64, i64* @z, align 8
- %1 = load i64, i64* @x, align 8
- %2 = cmpxchg i64* @y, i64 %0, i64 %1 seq_cst seq_cst
+ store i32 0, ptr %retval, align 4
+ %0 = load i64, ptr @z, align 8
+ %1 = load i64, ptr @x, align 8
+ %2 = cmpxchg ptr @y, i64 %0, i64 %1 seq_cst seq_cst
%3 = extractvalue { i64, i1 } %2, 1
ret i32 0
}
diff --git a/llvm/test/CodeGen/ARM/cmpxchg-O0.ll b/llvm/test/CodeGen/ARM/cmpxchg-O0.ll
index 898ccd229499f..28a64db1aeba4 100644
--- a/llvm/test/CodeGen/ARM/cmpxchg-O0.ll
+++ b/llvm/test/CodeGen/ARM/cmpxchg-O0.ll
@@ -5,7 +5,7 @@
; CHECK-T1-NOT: ldrex
; CHECK-T1-NOT: strex
-define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind {
+define { i8, i1 } @test_cmpxchg_8(ptr %addr, i8 %desired, i8 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_8:
; CHECK-DAG: mov [[ADDR:r[0-9]+]], r0
; CHECK-DAG: mov [[NEW:r[0-9]+]], r2
@@ -25,11 +25,11 @@ define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind {
; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]]
; CHECK: lsr{{(s)?}} {{r[0-9]+}}, [[CMP2]], #5
; CHECK: dmb ish
- %res = cmpxchg i8* %addr, i8 %desired, i8 %new seq_cst monotonic
+ %res = cmpxchg ptr %addr, i8 %desired, i8 %new seq_cst monotonic
ret { i8, i1 } %res
}
-define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind {
+define { i16, i1 } @test_cmpxchg_16(ptr %addr, i16 %desired, i16 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_16:
; CHECK-DAG: mov [[ADDR:r[0-9]+]], r0
; CHECK-DAG: mov [[NEW:r[0-9]+]], r2
@@ -49,11 +49,11 @@ define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind
; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]]
; CHECK: lsr{{(s)?}} {{r[0-9]+}}, [[CMP2]], #5
; CHECK: dmb ish
- %res = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst monotonic
+ %res = cmpxchg ptr %addr, i16 %desired, i16 %new seq_cst monotonic
ret { i16, i1 } %res
}
-define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind {
+define { i32, i1 } @test_cmpxchg_32(ptr %addr, i32 %desired, i32 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_32:
; CHECK-DAG: mov [[ADDR:r[0-9]+]], r0
; CHECK-DAG: mov [[NEW:r[0-9]+]], r2
@@ -72,11 +72,11 @@ define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind
; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]]
; CHECK: lsr{{(s)?}} {{r[0-9]+}}, [[CMP2]], #5
; CHECK: dmb ish
- %res = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
+ %res = cmpxchg ptr %addr, i32 %desired, i32 %new seq_cst monotonic
ret { i32, i1 } %res
}
-define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind {
+define { i64, i1 } @test_cmpxchg_64(ptr %addr, i64 %desired, i64 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_64:
; CHECK: mov [[ADDR:r[0-9]+]], r0
; CHECK: dmb ish
@@ -91,11 +91,11 @@ define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind
; CHECK: bne [[RETRY]]
; CHECK: [[DONE]]:
; CHECK: dmb ish
- %res = cmpxchg i64* %addr, i64 %desired, i64 %new seq_cst monotonic
+ %res = cmpxchg ptr %addr, i64 %desired, i64 %new seq_cst monotonic
ret { i64, i1 } %res
}
-define { i64, i1 } @test_nontrivial_args(i64* %addr, i64 %desired, i64 %new) {
+define { i64, i1 } @test_nontrivial_args(ptr %addr, i64 %desired, i64 %new) {
; CHECK-LABEL: test_nontrivial_args:
; CHECK: mov [[ADDR:r[0-9]+]], r0
; CHECK: dmb ish
@@ -113,7 +113,7 @@ define { i64, i1 } @test_nontrivial_args(i64* %addr, i64 %desired, i64 %new) {
%desired1 = add i64 %desired, 1
%new1 = add i64 %new, 1
- %res = cmpxchg i64* %addr, i64 %desired1, i64 %new1 seq_cst seq_cst
+ %res = cmpxchg ptr %addr, i64 %desired1, i64 %new1 seq_cst seq_cst
ret { i64, i1 } %res
}
@@ -124,6 +124,6 @@ define { i64, i1 } @test_nontrivial_args(i64* %addr, i64 %desired, i64 %new) {
; CHECK: strexd
; CHECK: bne
define void @test_cmpxchg_spillbug() {
- %v = cmpxchg i64* undef, i64 undef, i64 undef seq_cst seq_cst
+ %v = cmpxchg ptr undef, i64 undef, i64 undef seq_cst seq_cst
ret void
}
diff --git a/llvm/test/CodeGen/ARM/cmpxchg-idioms.ll b/llvm/test/CodeGen/ARM/cmpxchg-idioms.ll
index 1af80e7d0c871..4ff71b42d5db0 100644
--- a/llvm/test/CodeGen/ARM/cmpxchg-idioms.ll
+++ b/llvm/test/CodeGen/ARM/cmpxchg-idioms.ll
@@ -1,6 +1,6 @@
; RUN: llc -mtriple=thumbv7s-apple-ios7.0 -o - %s | FileCheck %s
-define i32 @test_return(i32* %p, i32 %oldval, i32 %newval) {
+define i32 @test_return(ptr %p, i32 %oldval, i32 %newval) {
; CHECK-LABEL: test_return:
; CHECK: ldrex [[LOADED:r[0-9]+]], [r0]
@@ -30,13 +30,13 @@ define i32 @test_return(i32* %p, i32 %oldval, i32 %newval) {
; CHECK: dmb ish
; CHECK: bx lr
- %pair = cmpxchg i32* %p, i32 %oldval, i32 %newval seq_cst seq_cst
+ %pair = cmpxchg ptr %p, i32 %oldval, i32 %newval seq_cst seq_cst
%success = extractvalue { i32, i1 } %pair, 1
%conv = zext i1 %success to i32
ret i32 %conv
}
-define i1 @test_return_bool(i8* %value, i8 %oldValue, i8 %newValue) {
+define i1 @test_return_bool(ptr %value, i8 %oldValue, i8 %newValue) {
; CHECK-LABEL: test_return_bool:
; CHECK: uxtb [[OLDBYTE:r[0-9]+]], r1
@@ -70,13 +70,13 @@ define i1 @test_return_bool(i8* %value, i8 %oldValue, i8 %newValue) {
; CHECK: bx lr
- %pair = cmpxchg i8* %value, i8 %oldValue, i8 %newValue acq_rel monotonic
+ %pair = cmpxchg ptr %value, i8 %oldValue, i8 %newValue acq_rel monotonic
%success = extractvalue { i8, i1 } %pair, 1
%failure = xor i1 %success, 1
ret i1 %failure
}
-define void @test_conditional(i32* %p, i32 %oldval, i32 %newval) {
+define void @test_conditional(ptr %p, i32 %oldval, i32 %newval) {
; CHECK-LABEL: test_conditional:
; CHECK: ldrex [[LOADED:r[0-9]+]], [r0]
@@ -104,7 +104,7 @@ define void @test_conditional(i32* %p, i32 %oldval, i32 %newval) {
; CHECK: dmb ish
; CHECK: b.w _bar
- %pair = cmpxchg i32* %p, i32 %oldval, i32 %newval seq_cst seq_cst
+ %pair = cmpxchg ptr %p, i32 %oldval, i32 %newval seq_cst seq_cst
%success = extractvalue { i32, i1 } %pair, 1
br i1 %success, label %true, label %false
diff --git a/llvm/test/CodeGen/ARM/cmpxchg-weak.ll b/llvm/test/CodeGen/ARM/cmpxchg-weak.ll
index 78800fc8bc423..9963f2d08ba52 100644
--- a/llvm/test/CodeGen/ARM/cmpxchg-weak.ll
+++ b/llvm/test/CodeGen/ARM/cmpxchg-weak.ll
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s
-define void @test_cmpxchg_weak(i32 *%addr, i32 %desired, i32 %new) {
+define void @test_cmpxchg_weak(ptr %addr, i32 %desired, i32 %new) {
; CHECK-LABEL: test_cmpxchg_weak:
; CHECK-NEXT: %bb.0:
; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r0]
@@ -23,13 +23,13 @@ define void @test_cmpxchg_weak(i32 *%addr, i32 %desired, i32 %new) {
; CHECK-NEXT: str r3, [r0]
; CHECK-NEXT: bx lr
;
- %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
+ %pair = cmpxchg weak ptr %addr, i32 %desired, i32 %new seq_cst monotonic
%oldval = extractvalue { i32, i1 } %pair, 0
- store i32 %oldval, i32* %addr
+ store i32 %oldval, ptr %addr
ret void
}
-define i1 @test_cmpxchg_weak_to_bool(i32, i32 *%addr, i32 %desired, i32 %new) {
+define i1 @test_cmpxchg_weak_to_bool(i32, ptr %addr, i32 %desired, i32 %new) {
; CHECK-LABEL: test_cmpxchg_weak_to_bool:
; CHECK-NEXT: %bb.0:
; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r1]
@@ -50,7 +50,7 @@ define i1 @test_cmpxchg_weak_to_bool(i32, i32 *%addr, i32 %desired, i32 %new) {
; CHECK-NEXT: clrex
; CHECK-NEXT: bx lr
;
- %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
+ %pair = cmpxchg weak ptr %addr, i32 %desired, i32 %new seq_cst monotonic
%success = extractvalue { i32, i1 } %pair, 1
ret i1 %success
}
diff --git a/llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll b/llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
index 5534532969636..606859db0a0ea 100644
--- a/llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
+++ b/llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
@@ -12,7 +12,7 @@
; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+mve.fp -float-abi=hard | \
; RUN: FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-BE
-define float @f1(float (float)* nocapture %fptr) #0 {
+define float @f1(ptr nocapture %fptr) #0 {
; CHECK-8M-LABEL: f1:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -65,7 +65,7 @@ entry:
attributes #0 = { "cmse_nonsecure_entry" nounwind }
attributes #1 = { nounwind }
-define double @d1(double (double)* nocapture %fptr) #0 {
+define double @d1(ptr nocapture %fptr) #0 {
; CHECK-8M-LE-LABEL: d1:
; CHECK-8M-LE: @ %bb.0: @ %entry
; CHECK-8M-LE-NEXT: push {r7, lr}
@@ -178,7 +178,7 @@ entry:
ret double %call
}
-define float @f2(float (float)* nocapture %fptr) #2 {
+define float @f2(ptr nocapture %fptr) #2 {
; CHECK-8M-LABEL: f2:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -236,7 +236,7 @@ entry:
attributes #2 = { nounwind }
attributes #3 = { "cmse_nonsecure_call" nounwind }
-define double @d2(double (double)* nocapture %fptr) #2 {
+define double @d2(ptr nocapture %fptr) #2 {
; CHECK-8M-LE-LABEL: d2:
; CHECK-8M-LE: @ %bb.0: @ %entry
; CHECK-8M-LE-NEXT: push {r7, lr}
@@ -359,7 +359,7 @@ entry:
ret double %call
}
-define float @f3(float (float)* nocapture %fptr) #4 {
+define float @f3(ptr nocapture %fptr) #4 {
; CHECK-8M-LABEL: f3:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -417,7 +417,7 @@ entry:
attributes #4 = { nounwind }
attributes #5 = { "cmse_nonsecure_call" nounwind }
-define double @d3(double (double)* nocapture %fptr) #4 {
+define double @d3(ptr nocapture %fptr) #4 {
; CHECK-8M-LE-LABEL: d3:
; CHECK-8M-LE: @ %bb.0: @ %entry
; CHECK-8M-LE-NEXT: push {r7, lr}
@@ -540,7 +540,7 @@ entry:
ret double %call
}
-define float @f4(float ()* nocapture %fptr) #6 {
+define float @f4(ptr nocapture %fptr) #6 {
; CHECK-8M-LABEL: f4:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -591,7 +591,7 @@ entry:
attributes #6 = { nounwind }
attributes #7 = { "cmse_nonsecure_call" nounwind }
-define double @d4(double ()* nocapture %fptr) #6 {
+define double @d4(ptr nocapture %fptr) #6 {
; CHECK-8M-LABEL: d4:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -639,7 +639,7 @@ entry:
ret double %call
}
-define void @fd(void (float, double)* %f, float %a, double %b) #8 {
+define void @fd(ptr %f, float %a, double %b) #8 {
; CHECK-8M-LABEL: fd:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -694,7 +694,7 @@ entry:
attributes #8 = { nounwind }
attributes #9 = { "cmse_nonsecure_call" nounwind }
-define void @fdff(void (float, double, float, float)* %f, float %a, double %b, float %c, float %d) #8 {
+define void @fdff(ptr %f, float %a, double %b, float %c, float %d) #8 {
; CHECK-8M-LABEL: fdff:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -747,7 +747,7 @@ entry:
ret void
}
-define void @fidififid(void (float, i32, double, i32, float, i32, float, i32, double)* %fu, float %a, i32 %b, double %c, i32 %d, float %e, i32 %f, float %g, i32 %h, double %i) #8 {
+define void @fidififid(ptr %fu, float %a, i32 %b, double %c, i32 %d, float %e, i32 %f, float %g, i32 %h, double %i) #8 {
; CHECK-8M-LABEL: fidififid:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -809,7 +809,7 @@ entry:
ret void
}
-define half @h1(half (half)* nocapture %hptr) "cmse_nonsecure_entry" nounwind {
+define half @h1(ptr nocapture %hptr) "cmse_nonsecure_entry" nounwind {
; CHECK-8M-LABEL: h1:
; CHECK-8M: @ %bb.0:
; CHECK-8M-NEXT: push {r7, lr}
@@ -888,7 +888,7 @@ define half @h1(half (half)* nocapture %hptr) "cmse_nonsecure_entry" nounwind {
ret half %call
}
-define half @h2(half (half)* nocapture %hptr) nounwind {
+define half @h2(ptr nocapture %hptr) nounwind {
; CHECK-8M-LABEL: h2:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -967,7 +967,7 @@ entry:
ret half %call
}
-define half @h3(half (half)* nocapture %hptr) nounwind {
+define half @h3(ptr nocapture %hptr) nounwind {
; CHECK-8M-LABEL: h3:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -1046,7 +1046,7 @@ entry:
ret half %call
}
-define half @h4(half ()* nocapture %hptr) nounwind {
+define half @h4(ptr nocapture %hptr) nounwind {
; CHECK-8M-LABEL: h4:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -1094,7 +1094,7 @@ entry:
ret half %call
}
-define half @h1_minsize(half (half)* nocapture %hptr) "cmse_nonsecure_entry" minsize nounwind {
+define half @h1_minsize(ptr nocapture %hptr) "cmse_nonsecure_entry" minsize nounwind {
; CHECK-8M-LABEL: h1_minsize:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -1165,7 +1165,7 @@ entry:
ret half %call
}
-define half @h1_arg(half (half)* nocapture %hptr, half %harg) nounwind {
+define half @h1_arg(ptr nocapture %hptr, half %harg) nounwind {
; CHECK-8M-LABEL: h1_arg:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
diff --git a/llvm/test/CodeGen/ARM/cmse-clear-float-hard2.ll b/llvm/test/CodeGen/ARM/cmse-clear-float-hard2.ll
index 715ef0bd58d5a..e586af22ace63 100644
--- a/llvm/test/CodeGen/ARM/cmse-clear-float-hard2.ll
+++ b/llvm/test/CodeGen/ARM/cmse-clear-float-hard2.ll
@@ -12,7 +12,7 @@
attributes #0 = { nounwind }
attributes #1 = { "cmse_nonsecure_call" nounwind }
-define void @fidififiddddff(void (float, i32, double, i32, float, i32, float, i32, double, double, double, double, float, float)* %fu, float %a, i32 %b, double %c, i32 %d, float %e, i32 %f, float %g, i32 %h, double %i, double %j, double %k, double %l, float %m, float %n) #0 {
+define void @fidififiddddff(ptr %fu, float %a, i32 %b, double %c, i32 %d, float %e, i32 %f, float %g, i32 %h, double %i, double %j, double %k, double %l, float %m, float %n) #0 {
; CHECK-V8-LE-LABEL: fidififiddddff:
; CHECK-V8-LE: @ %bb.0: @ %entry
; CHECK-V8-LE-NEXT: push {r7, lr}
diff --git a/llvm/test/CodeGen/ARM/cmse-clear-float-mve.ll b/llvm/test/CodeGen/ARM/cmse-clear-float-mve.ll
index 0da8080e9446b..3df150e953577 100644
--- a/llvm/test/CodeGen/ARM/cmse-clear-float-mve.ll
+++ b/llvm/test/CodeGen/ARM/cmse-clear-float-mve.ll
@@ -42,7 +42,7 @@ define <8 x i16> @f0() #1 {
; CHECK-HARD-NEXT: clrm {r0, r1, r2, r3, r12, apsr}
; CHECK-HARD-NEXT: bxns lr
entry:
- %call = call <8 x i16> bitcast (<8 x i16> (...)* @g0 to <8 x i16> ()*)() #0
+ %call = call <8 x i16> @g0() #0
ret <8 x i16> %call
}
@@ -77,7 +77,7 @@ define <4 x float> @f1() #1 {
; CHECK-HARD-NEXT: clrm {r0, r1, r2, r3, r12, apsr}
; CHECK-HARD-NEXT: bxns lr
entry:
- %call = call nnan ninf nsz <4 x float> bitcast (<4 x float> (...)* @g1 to <4 x float> ()*)() #0
+ %call = call nnan ninf nsz <4 x float> @g1() #0
ret <4 x float> %call
}
@@ -85,7 +85,7 @@ entry:
;; Test clearing around nonsecure calls
;;
-define void @f2(void (<8 x i16>)* nocapture %cb) #0 {
+define void @f2(ptr nocapture %cb) #0 {
; CHECK-SOFTFP-LABEL: f2:
; CHECK-SOFTFP: @ %bb.0: @ %entry
; CHECK-SOFTFP-NEXT: .save {r4, lr}
@@ -121,12 +121,12 @@ define void @f2(void (<8 x i16>)* nocapture %cb) #0 {
; CHECK-HARD-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
; CHECK-HARD-NEXT: pop {r4, pc}
entry:
- %call = tail call <8 x i16> bitcast (<8 x i16> (...)* @g0 to <8 x i16> ()*)() #0
+ %call = tail call <8 x i16> @g0() #0
tail call void %cb(<8 x i16> %call) #2
ret void
}
-define void @f3(void (<4 x float>)* nocapture %cb) #0 {
+define void @f3(ptr nocapture %cb) #0 {
; CHECK-SOFTFP-LABEL: f3:
; CHECK-SOFTFP: @ %bb.0: @ %entry
; CHECK-SOFTFP-NEXT: .save {r4, lr}
@@ -162,7 +162,7 @@ define void @f3(void (<4 x float>)* nocapture %cb) #0 {
; CHECK-HARD-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
; CHECK-HARD-NEXT: pop {r4, pc}
entry:
- %call = tail call nnan ninf nsz <4 x float> bitcast (<4 x float> (...)* @g1 to <4 x float> ()*)() #0
+ %call = tail call nnan ninf nsz <4 x float> @g1() #0
tail call void %cb(<4 x float> %call) #2
ret void
}
diff --git a/llvm/test/CodeGen/ARM/cmse-clear-float.ll b/llvm/test/CodeGen/ARM/cmse-clear-float.ll
index 356d13c16da32..b11b8d6118f01 100644
--- a/llvm/test/CodeGen/ARM/cmse-clear-float.ll
+++ b/llvm/test/CodeGen/ARM/cmse-clear-float.ll
@@ -13,7 +13,7 @@
; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+mve | \
; RUN: FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE
-define float @f1(float (float)* nocapture %fptr) #0 {
+define float @f1(ptr nocapture %fptr) #0 {
; CHECK-8M-LABEL: f1:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -69,7 +69,7 @@ entry:
attributes #0 = { "cmse_nonsecure_entry" nounwind }
attributes #1 = { nounwind }
-define double @d1(double (double)* nocapture %fptr) #0 {
+define double @d1(ptr nocapture %fptr) #0 {
; CHECK-8M-LE-LABEL: d1:
; CHECK-8M-LE: @ %bb.0: @ %entry
; CHECK-8M-LE-NEXT: push {r7, lr}
@@ -188,7 +188,7 @@ entry:
ret double %call
}
-define float @f2(float (float)* nocapture %fptr) #2 {
+define float @f2(ptr nocapture %fptr) #2 {
; CHECK-8M-LABEL: f2:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -241,7 +241,7 @@ entry:
attributes #2 = { nounwind }
attributes #3 = { "cmse_nonsecure_call" nounwind }
-define double @d2(double (double)* nocapture %fptr) #2 {
+define double @d2(ptr nocapture %fptr) #2 {
; CHECK-8M-LE-LABEL: d2:
; CHECK-8M-LE: @ %bb.0: @ %entry
; CHECK-8M-LE-NEXT: push {r7, lr}
@@ -354,7 +354,7 @@ entry:
ret double %call
}
-define float @f3(float (float)* nocapture %fptr) #4 {
+define float @f3(ptr nocapture %fptr) #4 {
; CHECK-8M-LABEL: f3:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -407,7 +407,7 @@ entry:
attributes #4 = { nounwind }
attributes #5 = { "cmse_nonsecure_call" nounwind }
-define double @d3(double (double)* nocapture %fptr) #4 {
+define double @d3(ptr nocapture %fptr) #4 {
; CHECK-8M-LE-LABEL: d3:
; CHECK-8M-LE: @ %bb.0: @ %entry
; CHECK-8M-LE-NEXT: push {r7, lr}
@@ -520,7 +520,7 @@ entry:
ret double %call
}
-define float @f4(float ()* nocapture %fptr) #6 {
+define float @f4(ptr nocapture %fptr) #6 {
; CHECK-8M-LABEL: f4:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -568,7 +568,7 @@ entry:
attributes #6 = { nounwind }
attributes #7 = { "cmse_nonsecure_call" nounwind }
-define double @d4(double ()* nocapture %fptr) #6 {
+define double @d4(ptr nocapture %fptr) #6 {
; CHECK-8M-LABEL: d4:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -613,7 +613,7 @@ entry:
ret double %call
}
-define void @fd(void (float, double)* %f, float %a, double %b) #8 {
+define void @fd(ptr %f, float %a, double %b) #8 {
; CHECK-8M-LABEL: fd:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
@@ -662,7 +662,7 @@ entry:
attributes #8 = { nounwind }
attributes #9 = { "cmse_nonsecure_call" nounwind }
-define float @f1_minsize(float (float)* nocapture %fptr) #10 {
+define float @f1_minsize(ptr nocapture %fptr) #10 {
; CHECK-8M-LABEL: f1_minsize:
; CHECK-8M: @ %bb.0: @ %entry
; CHECK-8M-NEXT: push {r7, lr}
diff --git a/llvm/test/CodeGen/ARM/cmse-clear.ll b/llvm/test/CodeGen/ARM/cmse-clear.ll
index eff08db51fe43..a20e33e1d891f 100644
--- a/llvm/test/CodeGen/ARM/cmse-clear.ll
+++ b/llvm/test/CodeGen/ARM/cmse-clear.ll
@@ -24,7 +24,7 @@
; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=mve | \
; RUN: FileCheck %s --check-prefix=CHECK-81M-SOFTFP
-define i32 @ns_entry(i32 (i32)* nocapture %fptr) #0 {
+define i32 @ns_entry(ptr nocapture %fptr) #0 {
; CHECK-8B-LABEL: ns_entry:
; CHECK-8B: @ %bb.0: @ %entry
; CHECK-8B-NEXT: push {r7, lr}
@@ -124,7 +124,7 @@ attributes #0 = { "cmse_nonsecure_entry" nounwind }
attributes #1 = { nounwind }
-define i32 @ns_call(i32 (i32)* nocapture %fptr) #2 {
+define i32 @ns_call(ptr nocapture %fptr) #2 {
; CHECK-8B-LABEL: ns_call:
; CHECK-8B: @ %bb.0: @ %entry
; CHECK-8B-NEXT: push {r7, lr}
@@ -253,7 +253,7 @@ attributes #2 = { nounwind }
attributes #3 = { "cmse_nonsecure_call" nounwind }
-define i32 @ns_tail_call(i32 (i32)* nocapture %fptr) #4 {
+define i32 @ns_tail_call(ptr nocapture %fptr) #4 {
; CHECK-8B-LABEL: ns_tail_call:
; CHECK-8B: @ %bb.0: @ %entry
; CHECK-8B-NEXT: push {r7, lr}
@@ -382,7 +382,7 @@ attributes #4 = { nounwind }
attributes #5 = { "cmse_nonsecure_call" nounwind }
-define void (i32, i32, i32, i32)* @ns_tail_call_many_args(void (i32, i32, i32, i32)* %f, i32 %a, i32 %b, i32 %c, i32 %d) #6 {
+define ptr @ns_tail_call_many_args(ptr %f, i32 %a, i32 %b, i32 %c, i32 %d) #6 {
; CHECK-8B-LABEL: ns_tail_call_many_args:
; CHECK-8B: @ %bb.0:
; CHECK-8B-NEXT: push {r4, r5, r7, lr}
@@ -520,14 +520,14 @@ define void (i32, i32, i32, i32)* @ns_tail_call_many_args(void (i32, i32, i32, i
; CHECK-81M-SOFTFP-NEXT: mov r0, r4
; CHECK-81M-SOFTFP-NEXT: pop {r4, pc}
tail call void %f(i32 %a, i32 %b, i32 %c, i32 %d) #7
- ret void (i32, i32, i32, i32)* %f
+ ret ptr %f
}
attributes #6 = { nounwind }
attributes #7 = { "cmse_nonsecure_call" nounwind }
-define i32 @ns_call_void(i32 %reg0, i32 ()* nocapture %fptr) #8 {
+define i32 @ns_call_void(i32 %reg0, ptr nocapture %fptr) #8 {
; CHECK-8B-LABEL: ns_call_void:
; CHECK-8B: @ %bb.0: @ %entry
; CHECK-8B-NEXT: push {r7, lr}
diff --git a/llvm/test/CodeGen/ARM/cmse-clrm-it-block.ll b/llvm/test/CodeGen/ARM/cmse-clrm-it-block.ll
index 377e5609d93fb..f51c4c83fba3f 100644
--- a/llvm/test/CodeGen/ARM/cmse-clrm-it-block.ll
+++ b/llvm/test/CodeGen/ARM/cmse-clrm-it-block.ll
@@ -1,12 +1,12 @@
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+8msecext %s -o - | FileCheck %s
-define hidden i32 @f(i32 %0, i32 (i32)* nocapture %1) local_unnamed_addr #0 {
+define hidden i32 @f(i32 %0, ptr nocapture %1) local_unnamed_addr #0 {
%3 = call i32 %1(i32 %0) #2
%4 = icmp eq i32 %3, 1
br i1 %4, label %6, label %5
5: ; preds = %2
- call void bitcast (void (...)* @g to void ()*)() #3
+ call void @g() #3
unreachable
6: ; preds = %2
diff --git a/llvm/test/CodeGen/ARM/cmse-cve-2021-35465-return.ll b/llvm/test/CodeGen/ARM/cmse-cve-2021-35465-return.ll
index c50aac8814eea..e1bd0c6717695 100644
--- a/llvm/test/CodeGen/ARM/cmse-cve-2021-35465-return.ll
+++ b/llvm/test/CodeGen/ARM/cmse-cve-2021-35465-return.ll
@@ -6,7 +6,7 @@
%indirect = type { double, double, double, double, double, double, double, double }
-define %indirect @func(%indirect (float, i32, double, i32, float, i32, float, i32, double, double, double, double, float, float)* %fu, float %a, i32 %b, double %c, i32 %d, float %e, i32 %f, float %g, i32 %h, double %i, double %j, double %k, double %l, float %m, float %n) {
+define %indirect @func(ptr %fu, float %a, i32 %b, double %c, i32 %d, float %e, i32 %f, float %g, i32 %h, double %i, double %j, double %k, double %l, float %m, float %n) {
; CHECK-8M-FP-CVE-2021-35465-LABEL: func:
; CHECK-8M-FP-CVE-2021-35465: @ %bb.0: @ %entry
; CHECK-8M-FP-CVE-2021-35465-NEXT: push {r7, lr}
diff --git a/llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll b/llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll
index 3557994b2d051..31a0b9814d7f1 100644
--- a/llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll
+++ b/llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll
@@ -35,7 +35,7 @@
; RUN: FileCheck %s --check-prefix=CHECK-81M-CVE-2021-35465
;
-define void @non_secure_call(void ()* %fptr) {
+define void @non_secure_call(ptr %fptr) {
; CHECK-8M-FP-CVE-2021-35465-LABEL: non_secure_call:
; CHECK-8M-FP-CVE-2021-35465: @ %bb.0:
; CHECK-8M-FP-CVE-2021-35465-NEXT: push {r7, lr}
diff --git a/llvm/test/CodeGen/ARM/cmse-errors.ll b/llvm/test/CodeGen/ARM/cmse-errors.ll
index 80a9caa04e714..091e16ecf4059 100644
--- a/llvm/test/CodeGen/ARM/cmse-errors.ll
+++ b/llvm/test/CodeGen/ARM/cmse-errors.ll
@@ -1,12 +1,11 @@
; RUN: not llc -mtriple=thumbv8m.main-eabi %s -o - 2>&1 | FileCheck %s
%struct.two_ints = type { i32, i32 }
-%struct.__va_list = type { i8* }
+%struct.__va_list = type { ptr }
-define void @test1(%struct.two_ints* noalias nocapture sret(%struct.two_ints) align 4 %agg.result) "cmse_nonsecure_entry" {
+define void @test1(ptr noalias nocapture sret(%struct.two_ints) align 4 %agg.result) "cmse_nonsecure_entry" {
entry:
- %0 = bitcast %struct.two_ints* %agg.result to i64*
- store i64 8589934593, i64* %0, align 4
+ store i64 8589934593, ptr %agg.result, align 4
ret void
}
; CHECK: error: {{.*}}test1{{.*}}: secure entry function would return value through pointer
@@ -17,7 +16,7 @@ entry:
}
; CHECK: error: {{.*}}test2{{.*}}: secure entry function requires arguments on stack
-define void @test3(void (i32, i32, i32, i32, i32)* nocapture %p) {
+define void @test3(ptr nocapture %p) {
entry:
tail call void %p(i32 1, i32 2, i32 3, i32 4, i32 5) "cmse_nonsecure_call"
ret void
@@ -25,43 +24,39 @@ entry:
; CHECK: error: {{.*}}test3{{.*}}: call to non-secure function would require passing arguments on stack
-define void @test4(void (%struct.two_ints*)* nocapture %p) {
+define void @test4(ptr nocapture %p) {
entry:
%r = alloca %struct.two_ints, align 4
- %0 = bitcast %struct.two_ints* %r to i8*
- call void %p(%struct.two_ints* nonnull sret(%struct.two_ints) align 4 %r) "cmse_nonsecure_call"
+ call void %p(ptr nonnull sret(%struct.two_ints) align 4 %r) "cmse_nonsecure_call"
ret void
}
; CHECK: error: {{.*}}test4{{.*}}: call to non-secure function would return value through pointer
-declare void @llvm.va_start(i8*) "nounwind"
+declare void @llvm.va_start(ptr) "nounwind"
-declare void @llvm.va_end(i8*) "nounwind"
+declare void @llvm.va_end(ptr) "nounwind"
define i32 @test5(i32 %a, ...) "cmse_nonsecure_entry" {
entry:
%vl = alloca %struct.__va_list, align 4
- %0 = bitcast %struct.__va_list* %vl to i8*
- call void @llvm.va_start(i8* nonnull %0)
- %1 = getelementptr inbounds %struct.__va_list, %struct.__va_list* %vl, i32 0, i32 0
- %argp.cur = load i8*, i8** %1, align 4
- %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
- store i8* %argp.next, i8** %1, align 4
- %2 = bitcast i8* %argp.cur to i32*
- %3 = load i32, i32* %2, align 4
- call void @llvm.va_end(i8* nonnull %0)
- ret i32 %3
+ call void @llvm.va_start(ptr nonnull %vl)
+ %argp.cur = load ptr, ptr %vl, align 4
+ %argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 4
+ store ptr %argp.next, ptr %vl, align 4
+ %0 = load i32, ptr %argp.cur, align 4
+ call void @llvm.va_end(ptr nonnull %vl)
+ ret i32 %0
}
; CHECK: error: {{.*}}test5{{.*}}: secure entry function must not be variadic
-define void @test6(void (i32, ...)* nocapture %p) {
+define void @test6(ptr nocapture %p) {
entry:
tail call void (i32, ...) %p(i32 1, i32 2, i32 3, i32 4, i32 5) "cmse_nonsecure_call"
ret void
}
; CHECK: error: {{.*}}test6{{.*}}: call to non-secure function would require passing arguments on stack
-define void @neg_test1(void (i32, ...)* nocapture %p) {
+define void @neg_test1(ptr nocapture %p) {
entry:
tail call void (i32, ...) %p(i32 1, i32 2, i32 3, i32 4) "cmse_nonsecure_call"
ret void
diff --git a/llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.ll b/llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.ll
index dc986c4b30a05..9f6a3155f0cab 100644
--- a/llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.ll
+++ b/llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.ll
@@ -1,14 +1,14 @@
; RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 --float-abi=hard %s -o - | \
; RUN: FileCheck %s
- at g = hidden local_unnamed_addr global float (...)* null, align 4
+ at g = hidden local_unnamed_addr global ptr null, align 4
@a = hidden local_unnamed_addr global float 0.000000e+00, align 4
define hidden void @f() local_unnamed_addr #0 {
entry:
- %0 = load float ()*, float ()** bitcast (float (...)** @g to float ()**), align 4
+ %0 = load ptr, ptr @g, align 4
%call = tail call nnan ninf nsz float %0() #1
- store float %call, float* @a, align 4
+ store float %call, ptr @a, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/cmse.ll b/llvm/test/CodeGen/ARM/cmse.ll
index 30deab1756975..46e9c86b4a1ff 100644
--- a/llvm/test/CodeGen/ARM/cmse.ll
+++ b/llvm/test/CodeGen/ARM/cmse.ll
@@ -13,7 +13,7 @@
; RUN: llc %s -o - -mtriple=thumbebv8.1m.main | \
; RUN: FileCheck %s --check-prefix=CHECK-81M
-define void @func1(void ()* nocapture %fptr) #0 {
+define void @func1(ptr nocapture %fptr) #0 {
; CHECK-8B-LABEL: func1:
; CHECK-8B: @ %bb.0: @ %entry
; CHECK-8B-NEXT: push {r7, lr}
@@ -117,7 +117,7 @@ entry:
attributes #0 = { "cmse_nonsecure_entry" nounwind }
attributes #1 = { "cmse_nonsecure_call" nounwind }
-define void @func2(void ()* nocapture %fptr) #2 {
+define void @func2(ptr nocapture %fptr) #2 {
; CHECK-8B-LABEL: func2:
; CHECK-8B: @ %bb.0: @ %entry
; CHECK-8B-NEXT: push {r7, lr}
@@ -276,7 +276,7 @@ entry:
ret void
}
-declare void @func51(i8 *);
+declare void @func51(ptr);
define void @func5() #4 {
; CHECK-8B-LABEL: func5:
@@ -344,7 +344,7 @@ define void @func5() #4 {
; CHECK-81M-NEXT: clrm {r0, r1, r2, r3, r12, apsr}
; CHECK-81M-NEXT: bxns lr
%1 = alloca i8, align 16
- call void @func51(i8* nonnull %1) #5
+ call void @func51(ptr nonnull %1) #5
ret void
}
diff --git a/llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll b/llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll
index 74598fba8307a..4d4853c2ad687 100644
--- a/llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll
+++ b/llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll
@@ -18,7 +18,7 @@ target triple = "thumbv7-apple-ios3.0.0"
; Function Attrs: nounwind ssp
define i32 @pr16110() #0 !dbg !15 {
for.cond1.preheader:
- store i32 0, i32* @c, align 4, !dbg !24
+ store i32 0, ptr @c, align 4, !dbg !24
br label %for.cond1.outer, !dbg !26
for.cond1: ; preds = %for.end9, %for.cond1.outer
@@ -27,9 +27,9 @@ for.cond1: ; preds = %for.end9, %for.cond
br i1 %cmp, label %for.body2, label %for.end9, !dbg !26
for.body2: ; preds = %for.cond1
- store i32 %storemerge11, i32* @b, align 4, !dbg !26
- tail call void @llvm.dbg.value(metadata i32* null, metadata !20, metadata !27), !dbg !28
- %0 = load i64, i64* @a, align 8, !dbg !29
+ store i32 %storemerge11, ptr @b, align 4, !dbg !26
+ tail call void @llvm.dbg.value(metadata ptr null, metadata !20, metadata !27), !dbg !28
+ %0 = load i64, ptr @a, align 8, !dbg !29
%xor = xor i64 %0, %e.1.ph, !dbg !29
%conv3 = trunc i64 %xor to i32, !dbg !29
tail call void @llvm.dbg.value(metadata i32 %conv3, metadata !19, metadata !27), !dbg !29
@@ -37,15 +37,15 @@ for.body2: ; preds = %for.cond1
br i1 %tobool4, label %land.end, label %land.rhs, !dbg !29
land.rhs: ; preds = %for.body2
- %call = tail call i32 bitcast (i32 (...)* @fn3 to i32 ()*)() #3, !dbg !29
+ %call = tail call i32 @fn3() #3, !dbg !29
%tobool5 = icmp ne i32 %call, 0, !dbg !29
br label %land.end
land.end: ; preds = %land.rhs, %for.body2
%1 = phi i1 [ false, %for.body2 ], [ %tobool5, %land.rhs ]
%land.ext = zext i1 %1 to i32
- %call6 = tail call i32 bitcast (i32 (...)* @fn2 to i32 (i32, i32*)*)(i32 %land.ext, i32* null) #3
- %2 = load i32, i32* @b, align 4, !dbg !26
+ %call6 = tail call i32 @fn2(i32 %land.ext, ptr null) #3
+ %2 = load i32, ptr @b, align 4, !dbg !26
%inc8 = add nsw i32 %2, 1, !dbg !26
%phitmp = and i64 %xor, 4294967295, !dbg !26
br label %for.cond1.outer, !dbg !26
@@ -53,7 +53,7 @@ land.end: ; preds = %land.rhs, %for.body
for.cond1.outer: ; preds = %land.end, %for.cond1.preheader
%storemerge11.ph = phi i32 [ %inc8, %land.end ], [ 0, %for.cond1.preheader ]
%e.1.ph = phi i64 [ %phitmp, %land.end ], [ 0, %for.cond1.preheader ]
- %3 = load i32, i32* @d, align 4, !dbg !30
+ %3 = load i32, ptr @d, align 4, !dbg !30
%tobool10 = icmp eq i32 %3, 0, !dbg !30
br label %for.cond1
@@ -61,7 +61,7 @@ for.end9: ; preds = %for.cond1
br i1 %tobool10, label %if.end, label %for.cond1, !dbg !30
if.end: ; preds = %for.end9
- store i32 %storemerge11, i32* @b, align 4, !dbg !26
+ store i32 %storemerge11, ptr @b, align 4, !dbg !26
ret i32 0, !dbg !31
}
diff --git a/llvm/test/CodeGen/ARM/coalesce-subregs.ll b/llvm/test/CodeGen/ARM/coalesce-subregs.ll
index c13af8a69cb1c..20821a5fbdc58 100644
--- a/llvm/test/CodeGen/ARM/coalesce-subregs.ll
+++ b/llvm/test/CodeGen/ARM/coalesce-subregs.ll
@@ -11,51 +11,45 @@ target triple = "thumbv7-apple-ios0.0.0"
; CHECK-NOT: vorr
; CHECK-NOT: vmov
; CHECK: vst2
-define void @f(float* %p, i32 %c) nounwind ssp {
+define void @f(ptr %p, i32 %c) nounwind ssp {
entry:
- %0 = bitcast float* %p to i8*
- %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0i8(i8* %0, i32 4)
+ %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0(ptr %p, i32 4)
%vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
- %add.ptr = getelementptr inbounds float, float* %p, i32 8
- %1 = bitcast float* %add.ptr to i8*
- tail call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %1, <4 x float> %vld221, <4 x float> undef, i32 4)
+ %add.ptr = getelementptr inbounds float, ptr %p, i32 8
+ tail call void @llvm.arm.neon.vst2.p0.v4f32(ptr %add.ptr, <4 x float> %vld221, <4 x float> undef, i32 4)
ret void
}
; CHECK: f1
; FIXME: This function still has copies.
-define void @f1(float* %p, i32 %c) nounwind ssp {
+define void @f1(ptr %p, i32 %c) nounwind ssp {
entry:
- %0 = bitcast float* %p to i8*
- %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0i8(i8* %0, i32 4)
+ %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0(ptr %p, i32 4)
%vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
- %add.ptr = getelementptr inbounds float, float* %p, i32 8
- %1 = bitcast float* %add.ptr to i8*
- %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0i8(i8* %1, i32 4)
+ %add.ptr = getelementptr inbounds float, ptr %p, i32 8
+ %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0(ptr %add.ptr, i32 4)
%vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0
- tail call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %1, <4 x float> %vld221, <4 x float> %vld2215, i32 4)
+ tail call void @llvm.arm.neon.vst2.p0.v4f32(ptr %add.ptr, <4 x float> %vld221, <4 x float> %vld2215, i32 4)
ret void
}
; CHECK: f2
; FIXME: This function still has copies.
-define void @f2(float* %p, i32 %c) nounwind ssp {
+define void @f2(ptr %p, i32 %c) nounwind ssp {
entry:
- %0 = bitcast float* %p to i8*
- %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0i8(i8* %0, i32 4)
+ %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0(ptr %p, i32 4)
%vld224 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
br label %do.body
do.body: ; preds = %do.body, %entry
%qq0.0.1.0 = phi <4 x float> [ %vld224, %entry ], [ %vld2216, %do.body ]
%c.addr.0 = phi i32 [ %c, %entry ], [ %dec, %do.body ]
- %p.addr.0 = phi float* [ %p, %entry ], [ %add.ptr, %do.body ]
- %add.ptr = getelementptr inbounds float, float* %p.addr.0, i32 8
- %1 = bitcast float* %add.ptr to i8*
- %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0i8(i8* %1, i32 4)
+ %p.addr.0 = phi ptr [ %p, %entry ], [ %add.ptr, %do.body ]
+ %add.ptr = getelementptr inbounds float, ptr %p.addr.0, i32 8
+ %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0(ptr %add.ptr, i32 4)
%vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0
%vld2216 = extractvalue { <4 x float>, <4 x float> } %vld22, 1
- tail call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %1, <4 x float> %qq0.0.1.0, <4 x float> %vld2215, i32 4)
+ tail call void @llvm.arm.neon.vst2.p0.v4f32(ptr %add.ptr, <4 x float> %qq0.0.1.0, <4 x float> %vld2215, i32 4)
%dec = add nsw i32 %c.addr.0, -1
%tobool = icmp eq i32 %dec, 0
br i1 %tobool, label %do.end, label %do.body
@@ -64,14 +58,14 @@ do.end: ; preds = %do.body
ret void
}
-declare { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0i8(i8*, i32) nounwind readonly
-declare void @llvm.arm.neon.vst2.p0i8.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind
+declare { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0(ptr, i32) nounwind readonly
+declare void @llvm.arm.neon.vst2.p0.v4f32(ptr, <4 x float>, <4 x float>, i32) nounwind
; CHECK: f3
; This function has lane insertions that span basic blocks.
; The trivial REG_SEQUENCE lowering can't handle that, but the coalescer can.
;
-; void f3(float *p, float *q) {
+; void f3(ptr p, ptr q) {
; float32x2_t x;
; x[1] = p[3];
; if (q)
@@ -83,62 +77,60 @@ declare void @llvm.arm.neon.vst2.p0i8.v4f32(i8*, <4 x float>, <4 x float>, i32)
;
; CHECK-NOT: vmov
; CHECK-NOT: vorr
-define void @f3(float* %p, float* %q) nounwind ssp {
+define void @f3(ptr %p, ptr %q) nounwind ssp {
entry:
- %arrayidx = getelementptr inbounds float, float* %p, i32 3
- %0 = load float, float* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds float, ptr %p, i32 3
+ %0 = load float, ptr %arrayidx, align 4
%vecins = insertelement <2 x float> undef, float %0, i32 1
- %tobool = icmp eq float* %q, null
+ %tobool = icmp eq ptr %q, null
br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry
- %1 = load float, float* %q, align 4
- %arrayidx2 = getelementptr inbounds float, float* %q, i32 1
- %2 = load float, float* %arrayidx2, align 4
+ %1 = load float, ptr %q, align 4
+ %arrayidx2 = getelementptr inbounds float, ptr %q, i32 1
+ %2 = load float, ptr %arrayidx2, align 4
%add = fadd float %1, %2
%vecins3 = insertelement <2 x float> %vecins, float %add, i32 0
br label %if.end
if.else: ; preds = %entry
- %arrayidx4 = getelementptr inbounds float, float* %p, i32 2
- %3 = load float, float* %arrayidx4, align 4
+ %arrayidx4 = getelementptr inbounds float, ptr %p, i32 2
+ %3 = load float, ptr %arrayidx4, align 4
%vecins5 = insertelement <2 x float> %vecins, float %3, i32 0
br label %if.end
if.end: ; preds = %if.else, %if.then
%x.0 = phi <2 x float> [ %vecins3, %if.then ], [ %vecins5, %if.else ]
- %add.ptr = getelementptr inbounds float, float* %p, i32 4
- %4 = bitcast float* %add.ptr to i8*
- tail call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %4, <2 x float> %x.0, i32 4)
+ %add.ptr = getelementptr inbounds float, ptr %p, i32 4
+ tail call void @llvm.arm.neon.vst1.p0.v2f32(ptr %add.ptr, <2 x float> %x.0, i32 4)
ret void
}
-declare void @llvm.arm.neon.vst1.p0i8.v2f32(i8*, <2 x float>, i32) nounwind
-declare <2 x float> @llvm.arm.neon.vld1.v2f32.p0i8(i8*, i32) nounwind readonly
+declare void @llvm.arm.neon.vst1.p0.v2f32(ptr, <2 x float>, i32) nounwind
+declare <2 x float> @llvm.arm.neon.vld1.v2f32.p0(ptr, i32) nounwind readonly
; CHECK: f4
; This function inserts a lane into a fully defined vector.
; The destination lane isn't read, so the subregs can coalesce.
; CHECK-NOT: vmov
; CHECK-NOT: vorr
-define void @f4(float* %p, float* %q) nounwind ssp {
+define void @f4(ptr %p, ptr %q) nounwind ssp {
entry:
- %0 = bitcast float* %p to i8*
- %vld1 = tail call <2 x float> @llvm.arm.neon.vld1.v2f32.p0i8(i8* %0, i32 4)
- %tobool = icmp eq float* %q, null
+ %vld1 = tail call <2 x float> @llvm.arm.neon.vld1.v2f32.p0(ptr %p, i32 4)
+ %tobool = icmp eq ptr %q, null
br i1 %tobool, label %if.end, label %if.then
if.then: ; preds = %entry
- %1 = load float, float* %q, align 4
- %arrayidx1 = getelementptr inbounds float, float* %q, i32 1
- %2 = load float, float* %arrayidx1, align 4
- %add = fadd float %1, %2
+ %0 = load float, ptr %q, align 4
+ %arrayidx1 = getelementptr inbounds float, ptr %q, i32 1
+ %1 = load float, ptr %arrayidx1, align 4
+ %add = fadd float %0, %1
%vecins = insertelement <2 x float> %vld1, float %add, i32 1
br label %if.end
if.end: ; preds = %entry, %if.then
%x.0 = phi <2 x float> [ %vecins, %if.then ], [ %vld1, %entry ]
- tail call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %0, <2 x float> %x.0, i32 4)
+ tail call void @llvm.arm.neon.vst1.p0.v2f32(ptr %p, <2 x float> %x.0, i32 4)
ret void
}
@@ -151,27 +143,26 @@ if.end: ; preds = %entry, %if.then
; We may leave the last insertelement in the if.end block.
; It is inserting the %add value into a dead lane, but %add causes interference
; in the entry block, and we don't do dead lane checks across basic blocks.
-define void @f5(float* %p, float* %q) nounwind ssp {
+define void @f5(ptr %p, ptr %q) nounwind ssp {
entry:
- %0 = bitcast float* %p to i8*
- %vld1 = tail call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* %0, i32 4)
+ %vld1 = tail call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr %p, i32 4)
%vecext = extractelement <4 x float> %vld1, i32 0
%vecext1 = extractelement <4 x float> %vld1, i32 1
%vecext2 = extractelement <4 x float> %vld1, i32 2
%vecext3 = extractelement <4 x float> %vld1, i32 3
%add = fadd float %vecext3, 1.000000e+00
- %tobool = icmp eq float* %q, null
+ %tobool = icmp eq ptr %q, null
br i1 %tobool, label %if.end, label %if.then
if.then: ; preds = %entry
- %arrayidx = getelementptr inbounds float, float* %q, i32 1
- %1 = load float, float* %arrayidx, align 4
- %add4 = fadd float %vecext, %1
- %2 = load float, float* %q, align 4
- %add6 = fadd float %vecext1, %2
- %arrayidx7 = getelementptr inbounds float, float* %q, i32 2
- %3 = load float, float* %arrayidx7, align 4
- %add8 = fadd float %vecext2, %3
+ %arrayidx = getelementptr inbounds float, ptr %q, i32 1
+ %0 = load float, ptr %arrayidx, align 4
+ %add4 = fadd float %vecext, %0
+ %1 = load float, ptr %q, align 4
+ %add6 = fadd float %vecext1, %1
+ %arrayidx7 = getelementptr inbounds float, ptr %q, i32 2
+ %2 = load float, ptr %arrayidx7, align 4
+ %add8 = fadd float %vecext2, %2
br label %if.end
if.end: ; preds = %entry, %if.then
@@ -182,13 +173,13 @@ if.end: ; preds = %entry, %if.then
%vecinit9 = insertelement <4 x float> %vecinit, float %b.0, i32 1
%vecinit10 = insertelement <4 x float> %vecinit9, float %c.0, i32 2
%vecinit11 = insertelement <4 x float> %vecinit10, float %add, i32 3
- tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %0, <4 x float> %vecinit11, i32 4)
+ tail call void @llvm.arm.neon.vst1.p0.v4f32(ptr %p, <4 x float> %vecinit11, i32 4)
ret void
}
-declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8*, i32) nounwind readonly
+declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr, i32) nounwind readonly
-declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v4f32(ptr, <4 x float>, i32) nounwind
; CHECK: pr13999
define void @pr13999() nounwind readonly {
@@ -216,7 +207,7 @@ loop.end:
}
; CHECK: pr14078
-define arm_aapcs_vfpcc i32 @pr14078(i8* nocapture %arg, i8* nocapture %arg1, i32 %arg2) nounwind uwtable readonly {
+define arm_aapcs_vfpcc i32 @pr14078(ptr nocapture %arg, ptr nocapture %arg1, i32 %arg2) nounwind uwtable readonly {
bb:
br i1 undef, label %bb31, label %bb3
@@ -231,7 +222,7 @@ bb3: ; preds = %bb12, %bb
br i1 undef, label %bb10, label %bb12
bb10: ; preds = %bb3
- %tmp11 = load <4 x float>, <4 x float>* undef, align 8
+ %tmp11 = load <4 x float>, ptr undef, align 8
br label %bb12
bb12: ; preds = %bb10, %bb3
@@ -268,7 +259,7 @@ declare <2 x float> @baz67(<2 x float>, <2 x float>) nounwind readnone
%struct.quux = type { <4 x float> }
; CHECK: pr14079
-define linkonce_odr arm_aapcs_vfpcc %struct.wombat.5 @pr14079(i8* nocapture %arg, i8* nocapture %arg1, i8* nocapture %arg2) nounwind uwtable inlinehint {
+define linkonce_odr arm_aapcs_vfpcc %struct.wombat.5 @pr14079(ptr nocapture %arg, ptr nocapture %arg1, ptr nocapture %arg2) nounwind uwtable inlinehint {
bb:
%tmp = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <1 x i32> zeroinitializer
%tmp3 = bitcast <1 x i64> %tmp to <2 x float>
@@ -294,7 +285,7 @@ bb:
; The shuffle in if.else3 must be preserved even though adjustCopiesBackFrom
; is tempted to remove it.
; CHECK: vorr d
-define internal void @adjustCopiesBackFrom(<2 x i64>* noalias nocapture sret(<2 x i64>) %agg.result, <2 x i64> %in) {
+define internal void @adjustCopiesBackFrom(ptr noalias nocapture sret(<2 x i64>) %agg.result, <2 x i64> %in) {
entry:
%0 = extractelement <2 x i64> %in, i32 0
%cmp = icmp slt i64 %0, 1
@@ -313,7 +304,7 @@ if.else3: ; preds = %entry
if.end4: ; preds = %if.else3, %if.then2
%result.2 = phi <2 x i64> [ %2, %if.then2 ], [ %3, %if.else3 ]
- store <2 x i64> %result.2, <2 x i64>* %agg.result, align 128
+ store <2 x i64> %result.2, ptr %agg.result, align 128
ret void
}
@@ -333,7 +324,7 @@ for.body: ; preds = %for.end, %entry
br i1 undef, label %for.body29, label %for.end
for.body29: ; preds = %for.body29, %for.body
- %0 = load <2 x double>, <2 x double>* null, align 1
+ %0 = load <2 x double>, ptr null, align 1
%splat40 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer
%mul41 = fmul <2 x double> undef, %splat40
%add42 = fadd <2 x double> undef, %mul41
@@ -351,7 +342,7 @@ for.end: ; preds = %for.body29, %for.bo
%add63 = fadd <2 x double> undef, %mul61
%add64 = fadd <2 x double> undef, %add63
%add67 = fadd <2 x double> undef, %add64
- store <2 x double> %add67, <2 x double>* undef, align 1
+ store <2 x double> %add67, ptr undef, align 1
br i1 undef, label %for.end70, label %for.body
for.end70: ; preds = %for.end, %entry
diff --git a/llvm/test/CodeGen/ARM/coff-no-dead-strip.ll b/llvm/test/CodeGen/ARM/coff-no-dead-strip.ll
index def81644bd5db..a129355d2ed11 100644
--- a/llvm/test/CodeGen/ARM/coff-no-dead-strip.ll
+++ b/llvm/test/CodeGen/ARM/coff-no-dead-strip.ll
@@ -4,7 +4,7 @@
@j = weak global i32 0
@k = internal global i32 0
- at llvm.used = appending global [3 x i8*] [i8* bitcast (i32* @i to i8*), i8* bitcast (i32* @j to i8*), i8* bitcast (i32* @k to i8*)]
+ at llvm.used = appending global [3 x ptr] [ptr @i, ptr @j, ptr @k]
; CHECK: .section .drectve
; CHECK: .ascii " /INCLUDE:i"
diff --git a/llvm/test/CodeGen/ARM/combine-vmovdrr.ll b/llvm/test/CodeGen/ARM/combine-vmovdrr.ll
index b3012bf842550..4411da790acb9 100644
--- a/llvm/test/CodeGen/ARM/combine-vmovdrr.ll
+++ b/llvm/test/CodeGen/ARM/combine-vmovdrr.ll
@@ -7,7 +7,7 @@ declare <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %shuffle.i.i307, <8 x i8> %shuffl
; The bitcasts force the values to go through the GPRs, whereas
; they are defined on VPRs and used on VPRs.
;
-define void @motivatingExample(<2 x i64>* %addr, <8 x i8>* %addr2) {
+define void @motivatingExample(ptr %addr, ptr %addr2) {
; CHECK-LABEL: motivatingExample:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -15,19 +15,19 @@ define void @motivatingExample(<2 x i64>* %addr, <8 x i8>* %addr2) {
; CHECK-NEXT: vtbl.8 d16, {d16, d17}, d18
; CHECK-NEXT: vstr d16, [r1]
; CHECK-NEXT: bx lr
- %shuffle.i.bc.i309 = load <2 x i64>, <2 x i64>* %addr
- %vtbl2.i25.i = load <8 x i8>, <8 x i8>* %addr2
+ %shuffle.i.bc.i309 = load <2 x i64>, ptr %addr
+ %vtbl2.i25.i = load <8 x i8>, ptr %addr2
%shuffle.i.extract.i310 = extractelement <2 x i64> %shuffle.i.bc.i309, i32 0
%shuffle.i27.extract.i311 = extractelement <2 x i64> %shuffle.i.bc.i309, i32 1
%tmp45 = bitcast i64 %shuffle.i.extract.i310 to <8 x i8>
%tmp46 = bitcast i64 %shuffle.i27.extract.i311 to <8 x i8>
%vtbl2.i25.i313 = tail call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp45, <8 x i8> %tmp46, <8 x i8> %vtbl2.i25.i)
- store <8 x i8> %vtbl2.i25.i313, <8 x i8>* %addr2
+ store <8 x i8> %vtbl2.i25.i313, ptr %addr2
ret void
}
; Check that we do not perform the transformation for dynamic index.
-define void @dynamicIndex(<2 x i64>* %addr, <8 x i8>* %addr2, i32 %index) {
+define void @dynamicIndex(ptr %addr, ptr %addr2, i32 %index) {
; CHECK-LABEL: dynamicIndex:
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r6, r7, lr}
@@ -58,20 +58,20 @@ define void @dynamicIndex(<2 x i64>* %addr, <8 x i8>* %addr2, i32 %index) {
; CHECK-NEXT: vstr d16, [r1]
; CHECK-NEXT: mov sp, r4
; CHECK-NEXT: pop {r4, r6, r7, pc}
- %shuffle.i.bc.i309 = load <2 x i64>, <2 x i64>* %addr
- %vtbl2.i25.i = load <8 x i8>, <8 x i8>* %addr2
+ %shuffle.i.bc.i309 = load <2 x i64>, ptr %addr
+ %vtbl2.i25.i = load <8 x i8>, ptr %addr2
%shuffle.i.extract.i310 = extractelement <2 x i64> %shuffle.i.bc.i309, i32 %index
%shuffle.i27.extract.i311 = extractelement <2 x i64> %shuffle.i.bc.i309, i32 1
%tmp45 = bitcast i64 %shuffle.i.extract.i310 to <8 x i8>
%tmp46 = bitcast i64 %shuffle.i27.extract.i311 to <8 x i8>
%vtbl2.i25.i313 = tail call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp45, <8 x i8> %tmp46, <8 x i8> %vtbl2.i25.i)
- store <8 x i8> %vtbl2.i25.i313, <8 x i8>* %addr2
+ store <8 x i8> %vtbl2.i25.i313, ptr %addr2
ret void
}
; Check that we do not perform the transformation when there are several uses
; of the result of the bitcast.
-define i64 @severalUses(<2 x i64>* %addr, <8 x i8>* %addr2) {
+define i64 @severalUses(ptr %addr, ptr %addr2) {
; CHECK-LABEL: severalUses:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -81,13 +81,13 @@ define i64 @severalUses(<2 x i64>* %addr, <8 x i8>* %addr2) {
; CHECK-NEXT: vstr d16, [r1]
; CHECK-NEXT: mov r1, r2
; CHECK-NEXT: bx lr
- %shuffle.i.bc.i309 = load <2 x i64>, <2 x i64>* %addr
- %vtbl2.i25.i = load <8 x i8>, <8 x i8>* %addr2
+ %shuffle.i.bc.i309 = load <2 x i64>, ptr %addr
+ %vtbl2.i25.i = load <8 x i8>, ptr %addr2
%shuffle.i.extract.i310 = extractelement <2 x i64> %shuffle.i.bc.i309, i32 0
%shuffle.i27.extract.i311 = extractelement <2 x i64> %shuffle.i.bc.i309, i32 1
%tmp45 = bitcast i64 %shuffle.i.extract.i310 to <8 x i8>
%tmp46 = bitcast i64 %shuffle.i27.extract.i311 to <8 x i8>
%vtbl2.i25.i313 = tail call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp45, <8 x i8> %tmp46, <8 x i8> %vtbl2.i25.i)
- store <8 x i8> %vtbl2.i25.i313, <8 x i8>* %addr2
+ store <8 x i8> %vtbl2.i25.i313, ptr %addr2
ret i64 %shuffle.i.extract.i310
}
diff --git a/llvm/test/CodeGen/ARM/commute-movcc.ll b/llvm/test/CodeGen/ARM/commute-movcc.ll
index 2978d317ad78e..0a276a50b3f2e 100644
--- a/llvm/test/CodeGen/ARM/commute-movcc.ll
+++ b/llvm/test/CodeGen/ARM/commute-movcc.ll
@@ -23,7 +23,7 @@
; CHECK: add{{(s|\.w)?}} [[IV:r[0-9]+]], {{.*}}#1
; CHECK: cmp [[IV]], #
-define i32 @f(i32* nocapture %a, i32 %Pref) nounwind ssp {
+define i32 @f(ptr nocapture %a, i32 %Pref) nounwind ssp {
entry:
br label %for.body
@@ -31,8 +31,8 @@ for.body: ; preds = %entry, %if.end8
%i.012 = phi i32 [ 0, %entry ], [ %inc, %if.end8 ]
%BestCost.011 = phi i32 [ -1, %entry ], [ %BestCost.1, %if.end8 ]
%BestIdx.010 = phi i32 [ 0, %entry ], [ %BestIdx.1, %if.end8 ]
- %arrayidx = getelementptr inbounds i32, i32* %a, i32 %i.012
- %0 = load i32, i32* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %a, i32 %i.012
+ %0 = load i32, ptr %arrayidx, align 4
%mul = mul i32 %0, %0
%sub = add nsw i32 %i.012, -5
%cmp2 = icmp eq i32 %sub, %Pref
@@ -53,7 +53,7 @@ if.else: ; preds = %for.body
if.end8: ; preds = %if.else, %if.then
%BestIdx.1 = phi i32 [ %i.0.BestIdx.0, %if.then ], [ %BestIdx.0.i.0, %if.else ]
%BestCost.1 = phi i32 [ %mul.BestCost.0, %if.then ], [ %BestCost.0.mul, %if.else ]
- store i32 %mul, i32* %arrayidx, align 4
+ store i32 %mul, ptr %arrayidx, align 4
%inc = add i32 %i.012, 1
%cmp = icmp eq i32 %inc, 11
br i1 %cmp, label %for.end, label %for.body
diff --git a/llvm/test/CodeGen/ARM/compare-call.ll b/llvm/test/CodeGen/ARM/compare-call.ll
index 47f20a28b8ac3..f3352c3e0310c 100644
--- a/llvm/test/CodeGen/ARM/compare-call.ll
+++ b/llvm/test/CodeGen/ARM/compare-call.ll
@@ -1,10 +1,10 @@
; RUN: llc -mtriple=arm-eabi -mattr=+v6,+vfp2 %s -o - | FileCheck %s
-define void @test3(float* %glob, i32 %X) {
+define void @test3(ptr %glob, i32 %X) {
entry:
- %tmp = load float, float* %glob ; <float> [#uses=1]
- %tmp2 = getelementptr float, float* %glob, i32 2 ; <float*> [#uses=1]
- %tmp3 = load float, float* %tmp2 ; <float> [#uses=1]
+ %tmp = load float, ptr %glob ; <float> [#uses=1]
+ %tmp2 = getelementptr float, ptr %glob, i32 2 ; <ptr> [#uses=1]
+ %tmp3 = load float, ptr %tmp2 ; <float> [#uses=1]
%tmp.upgrd.1 = fcmp ogt float %tmp, %tmp3 ; <i1> [#uses=1]
br i1 %tmp.upgrd.1, label %cond_true, label %UnifiedReturnBlock
diff --git a/llvm/test/CodeGen/ARM/constant-island-crash.ll b/llvm/test/CodeGen/ARM/constant-island-crash.ll
index 0d14caeaaed5b..e3ff8ad3eadda 100644
--- a/llvm/test/CodeGen/ARM/constant-island-crash.ll
+++ b/llvm/test/CodeGen/ARM/constant-island-crash.ll
@@ -7,9 +7,9 @@ target triple = "thumbv5e-none-linux-gnueabi"
%struct.blam = type { [4 x %struct.eggs], [6 x [15 x i16]], [6 x i32], i32, i32, i32, i32, i32, i32, %struct.eggs, [4 x %struct.eggs], [4 x %struct.eggs], [4 x i32], i32, i32, i32, [4 x %struct.eggs], [4 x %struct.eggs], i32, %struct.eggs, i32 }
%struct.eggs = type { i32, i32 }
-define void @spam(%struct.blam* %arg, i32 %arg1) {
+define void @spam(ptr %arg, i32 %arg1) {
bb:
- %tmp = getelementptr inbounds %struct.blam, %struct.blam* %arg, i32 undef, i32 2, i32 %arg1
+ %tmp = getelementptr inbounds %struct.blam, ptr %arg, i32 undef, i32 2, i32 %arg1
switch i32 %arg1, label %bb8 [
i32 0, label %bb2
i32 1, label %bb3
@@ -38,6 +38,6 @@ bb7: ; preds = %bb
unreachable
bb8: ; preds = %bb
- store i32 1, i32* %tmp, align 4
+ store i32 1, ptr %tmp, align 4
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/constantpool-align.ll b/llvm/test/CodeGen/ARM/constantpool-align.ll
index e8891ed31e20c..9f06d5ea9d80c 100644
--- a/llvm/test/CodeGen/ARM/constantpool-align.ll
+++ b/llvm/test/CodeGen/ARM/constantpool-align.ll
@@ -5,24 +5,24 @@ target triple = "thumbv7-arm-none-eabi"
; CHECK-LABEL: f:
; CHECK: vld1.64 {{.*}}, [r1:128]
; CHECK: .p2align 4
-define void @f(<4 x i32>* %p) {
- store <4 x i32> <i32 -1, i32 0, i32 0, i32 -1>, <4 x i32>* %p, align 4
+define void @f(ptr %p) {
+ store <4 x i32> <i32 -1, i32 0, i32 0, i32 -1>, ptr %p, align 4
ret void
}
; CHECK-LABEL: f_optsize:
; CHECK: vld1.64 {{.*}}, [r1]
; CHECK: .p2align 3
-define void @f_optsize(<4 x i32>* %p) optsize {
- store <4 x i32> <i32 -1, i32 0, i32 0, i32 -1>, <4 x i32>* %p, align 4
+define void @f_optsize(ptr %p) optsize {
+ store <4 x i32> <i32 -1, i32 0, i32 0, i32 -1>, ptr %p, align 4
ret void
}
; CHECK-LABEL: f_pgso:
; CHECK: vld1.64 {{.*}}, [r1]
; CHECK: .p2align 3
-define void @f_pgso(<4 x i32>* %p) !prof !14 {
- store <4 x i32> <i32 -1, i32 0, i32 0, i32 -1>, <4 x i32>* %p, align 4
+define void @f_pgso(ptr %p) !prof !14 {
+ store <4 x i32> <i32 -1, i32 0, i32 0, i32 -1>, ptr %p, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/constantpool-promote-dbg.ll b/llvm/test/CodeGen/ARM/constantpool-promote-dbg.ll
index 0b707386ff09b..246eeebd41f36 100644
--- a/llvm/test/CodeGen/ARM/constantpool-promote-dbg.ll
+++ b/llvm/test/CodeGen/ARM/constantpool-promote-dbg.ll
@@ -7,16 +7,16 @@ target triple = "thumbv7m--linux-gnu"
; CHECK-LABEL: fn1
; CHECK: .long .L.str
-define arm_aapcscc i8* @fn1() local_unnamed_addr #0 !dbg !8 {
+define arm_aapcscc ptr @fn1() local_unnamed_addr #0 !dbg !8 {
entry:
- ret i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), !dbg !14
+ ret ptr @.str, !dbg !14
}
; CHECK-LABEL: fn2
; CHECK: .long .L.str
-define arm_aapcscc i8* @fn2() local_unnamed_addr #0 !dbg !15 {
+define arm_aapcscc ptr @fn2() local_unnamed_addr #0 !dbg !15 {
entry:
- ret i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 1), !dbg !16
+ ret ptr getelementptr inbounds ([4 x i8], ptr @.str, i32 0, i32 1), !dbg !16
}
attributes #0 = { minsize norecurse nounwind optsize readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m3" "target-features"="+hwdiv,+soft-float,-crypto,-neon" "unsafe-fp-math"="false" "use-soft-float"="true" }
diff --git a/llvm/test/CodeGen/ARM/constantpool-promote-duplicate.ll b/llvm/test/CodeGen/ARM/constantpool-promote-duplicate.ll
index 70c4807a044f1..433467b01cbf0 100644
--- a/llvm/test/CodeGen/ARM/constantpool-promote-duplicate.ll
+++ b/llvm/test/CodeGen/ARM/constantpool-promote-duplicate.ll
@@ -11,9 +11,9 @@
; CHECK-DAG: const2:
; CHECK: .fnend
define void @test1() {
- %1 = load i32, i32* @const1, align 4
+ %1 = load i32, ptr @const1, align 4
call void @a(i32 %1)
- %2 = load i32, i32* @const2, align 4
+ %2 = load i32, ptr @const2, align 4
call void @a(i32 %2)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/constantpool-promote-ldrh.ll b/llvm/test/CodeGen/ARM/constantpool-promote-ldrh.ll
index 981366a473f0f..d214bde912893 100644
--- a/llvm/test/CodeGen/ARM/constantpool-promote-ldrh.ll
+++ b/llvm/test/CodeGen/ARM/constantpool-promote-ldrh.ll
@@ -12,10 +12,10 @@ target triple = "thumbv6m-arm-linux-gnueabi"
; CHECK: ldrh r{{[0-9]+}}, [[[base]]]
define hidden i32 @fn1() #0 {
entry:
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 undef, i8* align 2 bitcast ([4 x i16]* @fn1.a to i8*), i32 8, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 2 undef, ptr align 2 @fn1.a, i32 8, i1 false)
ret i32 undef
}
; Function Attrs: argmemonly nounwind
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1)
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture readonly, i32, i1)
attributes #0 = { "target-features"="+strict-align" }
diff --git a/llvm/test/CodeGen/ARM/constantpool-promote.ll b/llvm/test/CodeGen/ARM/constantpool-promote.ll
index 43196561f852e..c383b391db833 100644
--- a/llvm/test/CodeGen/ARM/constantpool-promote.ll
+++ b/llvm/test/CodeGen/ARM/constantpool-promote.ll
@@ -19,8 +19,8 @@
@.str5 = private unnamed_addr constant [2 x i8] c"s\00", align 1
@.arr1 = private unnamed_addr constant [2 x i16] [i16 3, i16 4], align 2
@.arr2 = private unnamed_addr constant [2 x i16] [i16 7, i16 8], align 2
- at .arr3 = private unnamed_addr constant [2 x i16*] [i16* null, i16* null], align 4
- at .ptr = private unnamed_addr constant [2 x i16*] [i16* getelementptr inbounds ([2 x i16], [2 x i16]* @.arr2, i32 0, i32 0), i16* null], align 2
+ at .arr3 = private unnamed_addr constant [2 x ptr] [ptr null, ptr null], align 4
+ at .ptr = private unnamed_addr constant [2 x ptr] [ptr @.arr2, ptr null], align 2
@.arr4 = private unnamed_addr constant [2 x i16] [i16 3, i16 4], align 16
@.arr5 = private unnamed_addr constant [2 x i16] [i16 3, i16 4], align 2
@.zerosize = private unnamed_addr constant [0 x i16] zeroinitializer, align 4
@@ -31,17 +31,17 @@
; CHECK: [[x]]:
; CHECK: .asciz "s\000\000"
define void @test1() #0 {
- tail call void @a(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i32 0, i32 0)) #2
+ tail call void @a(ptr @.str) #2
ret void
}
-declare void @a(i8*) #1
+declare void @a(ptr) #1
; CHECK-LABEL: @test2
; CHECK-NOT: .asci
; CHECK: .fnend
define void @test2() #0 {
- tail call void @a(i8* getelementptr inbounds ([69 x i8], [69 x i8]* @.str1, i32 0, i32 0)) #2
+ tail call void @a(ptr @.str1) #2
ret void
}
@@ -50,7 +50,7 @@ define void @test2() #0 {
; CHECK: [[x]]:
; CHECK: .asciz "this string is just right!\000"
define void @test3() #0 {
- tail call void @a(i8* getelementptr inbounds ([27 x i8], [27 x i8]* @.str2, i32 0, i32 0)) #2
+ tail call void @a(ptr @.str2) #2
ret void
}
@@ -60,34 +60,34 @@ define void @test3() #0 {
; CHECK: [[x]]:
; CHECK: .asciz "this string is used twice\000\000"
define void @test4() #0 {
- tail call void @a(i8* getelementptr inbounds ([26 x i8], [26 x i8]* @.str3, i32 0, i32 0)) #2
- tail call void @a(i8* getelementptr inbounds ([26 x i8], [26 x i8]* @.str3, i32 0, i32 0)) #2
+ tail call void @a(ptr @.str3) #2
+ tail call void @a(ptr @.str3) #2
ret void
}
; CHECK-LABEL: @test5a
; CHECK-NOT: adr
define void @test5a() #0 {
- tail call void @a(i8* getelementptr inbounds ([29 x i8], [29 x i8]* @.str4, i32 0, i32 0)) #2
+ tail call void @a(ptr @.str4) #2
ret void
}
define void @test5b() #0 {
- tail call void @b(i8* getelementptr inbounds ([29 x i8], [29 x i8]* @.str4, i32 0, i32 0)) #2
+ tail call void @b(ptr @.str4) #2
ret void
}
; CHECK-LABEL: @test6a
; CHECK: L.arr1
define void @test6a() #0 {
- tail call void @c(i16* getelementptr inbounds ([2 x i16], [2 x i16]* @.arr1, i32 0, i32 0)) #2
+ tail call void @c(ptr @.arr1) #2
ret void
}
; CHECK-LABEL: @test6b
; CHECK: L.arr1
define void @test6b() #0 {
- tail call void @c(i16* getelementptr inbounds ([2 x i16], [2 x i16]* @.arr1, i32 0, i32 0)) #2
+ tail call void @c(ptr @.arr1) #2
ret void
}
@@ -95,7 +95,7 @@ define void @test6b() #0 {
; CHECK-LABEL: @test7
; CHECK-NOT: adr
define void @test7() #0 {
- tail call void @c(i16* getelementptr inbounds ([2 x i16], [2 x i16]* @.arr2, i32 0, i32 0)) #2
+ tail call void @c(ptr @.arr2) #2
ret void
}
@@ -104,8 +104,8 @@ define void @test7() #0 {
; CHECK: .zero
; CHECK: .fnend
define void @test8() #0 {
- %a = load i16*, i16** getelementptr inbounds ([2 x i16*], [2 x i16*]* @.arr3, i32 0, i32 0)
- tail call void @c(i16* %a) #2
+ %a = load ptr, ptr @.arr3
+ tail call void @c(ptr %a) #2
ret void
}
@@ -115,8 +115,8 @@ define void @test8() #0 {
; CHECK-PIC: .long .L.ptr
; CHECK: .fnend
define void @test8a() #0 {
- %a = load i16*, i16** getelementptr inbounds ([2 x i16*], [2 x i16*]* @.ptr, i32 0, i32 0)
- tail call void @c(i16* %a) #2
+ %a = load ptr, ptr @.ptr
+ tail call void @c(ptr %a) #2
ret void
}
@@ -127,16 +127,14 @@ define void @test8a() #0 {
define void @fn1() "target-features"="+strict-align" {
entry:
%a = alloca [4 x i16], align 2
- %0 = bitcast [4 x i16]* %a to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 %0, i8* align 2 bitcast ([4 x i16]* @fn1.a to i8*), i32 8, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 2 %a, ptr align 2 @fn1.a, i32 8, i1 false)
ret void
}
define void @fn2() "target-features"="+strict-align" {
entry:
%a = alloca [8 x i8], align 2
- %0 = bitcast [8 x i8]* %a to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* bitcast ([8 x i8]* @fn2.a to i8*), i32 16, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr %a, ptr @fn2.a, i32 16, i1 false)
ret void
}
@@ -144,7 +142,7 @@ entry:
; CHECK-LABEL: @test9
; CHECK-NOT: adr
define void @test9() #0 {
- tail call void @c(i16* getelementptr inbounds ([2 x i16], [2 x i16]* @.arr4, i32 0, i32 0)) #2
+ tail call void @c(ptr @.arr4) #2
ret void
}
@@ -152,7 +150,7 @@ define void @test9() #0 {
; CHECK-LABEL: @pr32130
; CHECK-NOT: adr
define void @pr32130() #0 {
- tail call void @c(i16* getelementptr inbounds ([0 x i16], [0 x i16]* @.zerosize, i32 0, i32 0)) #2
+ tail call void @c(ptr @.zerosize) #2
ret void
}
@@ -163,8 +161,8 @@ define void @pr32130() #0 {
; CHECK-V7: ldrb{{(.w)?}} r{{[0-9]*}}, [[x:.*]]
; CHECK-V7: [[x]]:
; CHECK-V7: .asciz "s\000\000"
-define void @test10(i8* %a) local_unnamed_addr #0 {
- call void @llvm.memmove.p0i8.p0i8.i32(i8* align 1 %a, i8* align 1 getelementptr inbounds ([2 x i8], [2 x i8]* @.str5, i32 0, i32 0), i32 1, i1 false)
+define void @test10(ptr %a) local_unnamed_addr #0 {
+ call void @llvm.memmove.p0.p0.i32(ptr align 1 %a, ptr align 1 @.str5, i32 1, i1 false)
ret void
}
@@ -181,8 +179,8 @@ define void @test10(i8* %a) local_unnamed_addr #0 {
; CHECK-V7ARM: [[x]]:
; CHECK-V7ARM: .short 3
; CHECK-V7ARM: .short 4
-define void @test11(i16* %a) local_unnamed_addr #0 {
- call void @llvm.memmove.p0i16.p0i16.i32(i16* align 2 %a, i16* align 2 getelementptr inbounds ([2 x i16], [2 x i16]* @.arr5, i32 0, i32 0), i32 2, i1 false)
+define void @test11(ptr %a) local_unnamed_addr #0 {
+ call void @llvm.memmove.p0.p0.i32(ptr align 2 %a, ptr align 2 @.arr5, i32 2, i1 false)
ret void
}
@@ -191,17 +189,16 @@ define void @test11(i16* %a) local_unnamed_addr #0 {
; CHECK-LABEL: @test12
; CHECK-NOT: adr
define void @test12() local_unnamed_addr #0 {
- call void @d(<4 x i32>* @implicit_alignment_vector)
+ call void @d(ptr @implicit_alignment_vector)
ret void
}
-declare void @b(i8*) #1
-declare void @c(i16*) #1
-declare void @d(<4 x i32>*) #1
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1)
-declare void @llvm.memmove.p0i8.p0i8.i32(i8*, i8*, i32, i1) local_unnamed_addr
-declare void @llvm.memmove.p0i16.p0i16.i32(i16*, i16*, i32, i1) local_unnamed_addr
+declare void @b(ptr) #1
+declare void @c(ptr) #1
+declare void @d(ptr) #1
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture readonly, i32, i1)
+declare void @llvm.memmove.p0.p0.i32(ptr, ptr, i32, i1) local_unnamed_addr
attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/CodeGen/ARM/copy-by-struct-i32.ll b/llvm/test/CodeGen/ARM/copy-by-struct-i32.ll
index d3bc2d61fcb89..5d361861c27c5 100644
--- a/llvm/test/CodeGen/ARM/copy-by-struct-i32.ll
+++ b/llvm/test/CodeGen/ARM/copy-by-struct-i32.ll
@@ -9,7 +9,7 @@
%struct.anon = type { i32, i32, i32, i32, i32, i32, i32, %struct.f, i32, i64, i32 }
%struct.f = type { i32, i32, i32, i32, i32 }
-define arm_aapcscc void @s(i64* %q, %struct.anon* %p) {
+define arm_aapcscc void @s(ptr %q, ptr %p) {
; ASSEMBLY-LABEL: s:
; ASSEMBLY: @ %bb.0: @ %entry
; ASSEMBLY-NEXT: push {r4, r5, r11, lr}
@@ -52,9 +52,9 @@ define arm_aapcscc void @s(i64* %q, %struct.anon* %p) {
; ASSEMBLY-NEXT: add sp, sp, #136
; ASSEMBLY-NEXT: pop {r4, r5, r11, pc}
entry:
- %0 = load i64, i64* %q, align 8
+ %0 = load i64, ptr %q, align 8
%sub = add nsw i64 %0, -1
- tail call arm_aapcscc void bitcast (void (...)* @r to void (%struct.anon*, %struct.anon*, i64)*)(%struct.anon* byval(%struct.anon) nonnull align 8 %p, %struct.anon* byval(%struct.anon) nonnull align 8 %p, i64 %sub)
+ tail call arm_aapcscc void @r(ptr byval(%struct.anon) nonnull align 8 %p, ptr byval(%struct.anon) nonnull align 8 %p, i64 %sub)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/copy-cpsr.ll b/llvm/test/CodeGen/ARM/copy-cpsr.ll
index 8b7dc038fc929..615f4e6dcf123 100644
--- a/llvm/test/CodeGen/ARM/copy-cpsr.ll
+++ b/llvm/test/CodeGen/ARM/copy-cpsr.ll
@@ -16,7 +16,7 @@
; elided).
; + We want the chains to be long enough that duplicating them is expensive.
-define void @test_copy_cpsr(i128 %lhs, i128 %rhs, i128* %addr) {
+define void @test_copy_cpsr(i128 %lhs, i128 %rhs, ptr %addr) {
; CHECK-ARM: test_copy_cpsr:
; CHECK-THUMB: test_copy_cpsr:
@@ -29,13 +29,13 @@ define void @test_copy_cpsr(i128 %lhs, i128 %rhs, i128* %addr) {
; CHECK-THUMB: msr {{APSR|apsr}}_nzcvq, [[TMP]] @ encoding: [0x8{{[0-9a-f]}},0xf3,0x00,0x88]
%sum = add i128 %lhs, %rhs
- store volatile i128 %sum, i128* %addr
+ store volatile i128 %sum, ptr %addr
%rhs2.tmp1 = trunc i128 %rhs to i64
%rhs2 = zext i64 %rhs2.tmp1 to i128
%sum2 = add i128 %lhs, %rhs2
- store volatile i128 %sum2, i128* %addr
+ store volatile i128 %sum2, ptr %addr
ret void
}
diff --git a/llvm/test/CodeGen/ARM/copy-paired-reg.ll b/llvm/test/CodeGen/ARM/copy-paired-reg.ll
index 453fac4b1504c..91c551808eb79 100644
--- a/llvm/test/CodeGen/ARM/copy-paired-reg.ll
+++ b/llvm/test/CodeGen/ARM/copy-paired-reg.ll
@@ -5,13 +5,11 @@ define void @f() {
%a = alloca i8, i32 8, align 8
%b = alloca i8, i32 8, align 8
- %c = bitcast i8* %a to i64*
- %d = bitcast i8* %b to i64*
- store atomic i64 0, i64* %c seq_cst, align 8
- store atomic i64 0, i64* %d seq_cst, align 8
+ store atomic i64 0, ptr %a seq_cst, align 8
+ store atomic i64 0, ptr %b seq_cst, align 8
- %e = load atomic i64, i64* %d seq_cst, align 8
+ %e = load atomic i64, ptr %b seq_cst, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
index ddcd72d9d67ab..0e49a334e5a5b 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
@@ -22,13 +22,13 @@
; CHECK-NEXT: Data
; CHECK-SAME: Latency=0
define dso_local i32 @bar(i32 %a1, i32 %b1, i32 %c1) minsize optsize {
- %1 = load i32, i32* @a, align 4
- %2 = load i32, i32* @b, align 4
- %3 = load i32, i32* @c, align 4
+ %1 = load i32, ptr @a, align 4
+ %2 = load i32, ptr @b, align 4
+ %3 = load i32, ptr @c, align 4
- %ptr_after = getelementptr i32, i32* @a, i32 3
+ %ptr_after = getelementptr i32, ptr @a, i32 3
- %ptr_val = ptrtoint i32* %ptr_after to i32
+ %ptr_val = ptrtoint ptr %ptr_after to i32
%mul1 = mul i32 %ptr_val, %1
%mul2 = mul i32 %mul1, %2
%mul3 = mul i32 %mul2, %3
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll
index 1835870850eb3..359936320c605 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll
@@ -13,13 +13,13 @@
; CHECK-NEXT: Data
; CHECK-SAME: Latency=0
-define i32 @foo(i32* %a) nounwind optsize {
+define i32 @foo(ptr %a) nounwind optsize {
entry:
- %b = getelementptr i32, i32* %a, i32 1
- %c = getelementptr i32, i32* %a, i32 2
- %0 = load i32, i32* %a, align 4
- %1 = load i32, i32* %b, align 4
- %2 = load i32, i32* %c, align 4
+ %b = getelementptr i32, ptr %a, i32 1
+ %c = getelementptr i32, ptr %a, i32 2
+ %0 = load i32, ptr %a, align 4
+ %1 = load i32, ptr %b, align 4
+ %2 = load i32, ptr %c, align 4
%mul1 = mul i32 %0, %1
%mul2 = mul i32 %mul1, %2
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll
index 2ee5f75bec3a0..773ac326942b0 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll
@@ -13,19 +13,18 @@
; CHECK: Data
; CHECK-SAME: Latency=1
-define i32 @bar(i32 %v0, i32 %v1, i32 %v2, i32* %addr) {
+define i32 @bar(i32 %v0, i32 %v1, i32 %v2, ptr %addr) {
- %addr.1 = getelementptr i32, i32* %addr, i32 0
- store i32 %v0, i32* %addr.1
+ store i32 %v0, ptr %addr
- %addr.2 = getelementptr i32, i32* %addr, i32 1
- store i32 %v1, i32* %addr.2
+ %addr.2 = getelementptr i32, ptr %addr, i32 1
+ store i32 %v1, ptr %addr.2
- %addr.3 = getelementptr i32, i32* %addr, i32 2
- store i32 %v2, i32* %addr.3
+ %addr.3 = getelementptr i32, ptr %addr, i32 2
+ store i32 %v2, ptr %addr.3
- %ptr_after = getelementptr i32, i32* %addr, i32 3
- %val = ptrtoint i32* %ptr_after to i32
+ %ptr_after = getelementptr i32, ptr %addr, i32 3
+ %val = ptrtoint ptr %ptr_after to i32
%rv1 = mul i32 %val, %v0
%rv2 = mul i32 %rv1, %v1
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-stm.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-stm.ll
index 026a62f35201a..48362e8702301 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-stm.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-stm.ll
@@ -10,17 +10,17 @@
; CHECK: rdefs left
; CHECK-NEXT: Latency : 2
-define i32 @test_stm(i32 %v0, i32 %v1, i32* %addr) {
+define i32 @test_stm(i32 %v0, i32 %v1, ptr %addr) {
- %addr.1 = getelementptr i32, i32* %addr, i32 1
- store i32 %v0, i32* %addr.1
+ %addr.1 = getelementptr i32, ptr %addr, i32 1
+ store i32 %v0, ptr %addr.1
- %addr.2 = getelementptr i32, i32* %addr, i32 2
- store i32 %v1, i32* %addr.2
+ %addr.2 = getelementptr i32, ptr %addr, i32 2
+ store i32 %v1, ptr %addr.2
- %addr.3 = getelementptr i32, i32* %addr, i32 3
- %val = ptrtoint i32* %addr to i32
- store i32 %val, i32* %addr.3
+ %addr.3 = getelementptr i32, ptr %addr, i32 3
+ %val = ptrtoint ptr %addr to i32
+ store i32 %val, ptr %addr.3
%rv = add i32 %v0, %v1
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
index bf923eab4c89e..98416580afe2f 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
@@ -23,17 +23,17 @@
; CHECK-SAME: Latency=0
; CHECK-NEXT: Data
; CHECK-SAME: Latency=0
-define dso_local i32 @bar(i32* %iptr) minsize optsize {
- %1 = load double, double* @a, align 8
- %2 = load double, double* @b, align 8
- %3 = load double, double* @c, align 8
+define dso_local i32 @bar(ptr %iptr) minsize optsize {
+ %1 = load double, ptr @a, align 8
+ %2 = load double, ptr @b, align 8
+ %3 = load double, ptr @c, align 8
- %ptr_after = getelementptr double, double* @a, i32 3
+ %ptr_after = getelementptr double, ptr @a, i32 3
- %ptr_new_ival = ptrtoint double* %ptr_after to i32
- %ptr_new = inttoptr i32 %ptr_new_ival to i32*
+ %ptr_new_ival = ptrtoint ptr %ptr_after to i32
+ %ptr_new = inttoptr i32 %ptr_new_ival to ptr
- store i32 %ptr_new_ival, i32* %iptr, align 8
+ store i32 %ptr_new_ival, ptr %iptr, align 8
%v1 = fptoui double %1 to i32
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll
index ac208c65af28b..9c520d3154810 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll
@@ -15,13 +15,13 @@
; CHECK-NEXT: Data
; CHECK-SAME: Latency=0
-define double @foo(double* %a) nounwind optsize {
+define double @foo(ptr %a) nounwind optsize {
entry:
- %b = getelementptr double, double* %a, i32 1
- %c = getelementptr double, double* %a, i32 2
- %0 = load double, double* %a, align 4
- %1 = load double, double* %b, align 4
- %2 = load double, double* %c, align 4
+ %b = getelementptr double, ptr %a, i32 1
+ %c = getelementptr double, ptr %a, i32 2
+ %0 = load double, ptr %a, align 4
+ %1 = load double, ptr %b, align 4
+ %2 = load double, ptr %c, align 4
%mul1 = fmul double %0, %1
%mul2 = fmul double %mul1, %2
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
index afa43eac95c71..4ab035ab0d856 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
@@ -16,25 +16,25 @@
@b = dso_local global double 0.0, align 4
@c = dso_local global double 0.0, align 4
-define dso_local i32 @bar(double* %vptr, i32 %iv1, i32* %iptr) minsize {
+define dso_local i32 @bar(ptr %vptr, i32 %iv1, ptr %iptr) minsize {
- %vp2 = getelementptr double, double* %vptr, i32 1
- %vp3 = getelementptr double, double* %vptr, i32 2
+ %vp2 = getelementptr double, ptr %vptr, i32 1
+ %vp3 = getelementptr double, ptr %vptr, i32 2
- %v1 = load double, double* %vptr, align 8
- %v2 = load double, double* %vp2, align 8
- %v3 = load double, double* %vp3, align 8
+ %v1 = load double, ptr %vptr, align 8
+ %v2 = load double, ptr %vp2, align 8
+ %v3 = load double, ptr %vp3, align 8
- store double %v1, double* @a, align 8
- store double %v2, double* @b, align 8
- store double %v3, double* @c, align 8
+ store double %v1, ptr @a, align 8
+ store double %v2, ptr @b, align 8
+ store double %v3, ptr @c, align 8
- %ptr_after = getelementptr double, double* @a, i32 3
+ %ptr_after = getelementptr double, ptr @a, i32 3
- %ptr_new_ival = ptrtoint double* %ptr_after to i32
- %ptr_new = inttoptr i32 %ptr_new_ival to i32*
+ %ptr_new_ival = ptrtoint ptr %ptr_after to i32
+ %ptr_new = inttoptr i32 %ptr_new_ival to ptr
- store i32 %ptr_new_ival, i32* %iptr, align 8
+ store i32 %ptr_new_ival, ptr %iptr, align 8
%mul1 = mul i32 %ptr_new_ival, %iv1
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm.ll
index 5e9041ce08429..e61f349020c5e 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm.ll
@@ -13,10 +13,10 @@
@var = global %bigVec zeroinitializer
-define void @bar(%bigVec* %ptr) {
+define void @bar(ptr %ptr) {
- %tmp = load %bigVec, %bigVec* %ptr
- store %bigVec %tmp, %bigVec* @var
+ %tmp = load %bigVec, ptr %ptr
+ store %bigVec %tmp, ptr @var
ret void
}
diff --git a/llvm/test/CodeGen/ARM/crash-O0.ll b/llvm/test/CodeGen/ARM/crash-O0.ll
index 29110fcf3bd27..db946529d9c49 100644
--- a/llvm/test/CodeGen/ARM/crash-O0.ll
+++ b/llvm/test/CodeGen/ARM/crash-O0.ll
@@ -7,22 +7,21 @@ target triple = "armv6-apple-darwin10"
; This function would crash RegAllocFast because it tried to spill %CPSR.
define arm_apcscc void @clobber_cc() nounwind noinline ssp {
entry:
- %asmtmp = call %struct0 asm sideeffect "...", "=&r,=&r,r,Ir,r,~{cc},~{memory}"(i32* undef, i32 undef, i32 1) nounwind ; <%0> [#uses=0]
+ %asmtmp = call %struct0 asm sideeffect "...", "=&r,=&r,r,Ir,r,~{cc},~{memory}"(ptr undef, i32 undef, i32 1) nounwind ; <%0> [#uses=0]
unreachable
}
- at .str523 = private constant [256 x i8] c"<Unknown>\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 4 ; <[256 x i8]*> [#uses=1]
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
+ at .str523 = private constant [256 x i8] c"<Unknown>\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 4 ; <ptr> [#uses=1]
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
; This function uses the scavenger for an ADDri instruction.
; ARMBaseRegisterInfo::estimateRSStackSizeLimit must return a 255 limit.
define arm_apcscc void @scavence_ADDri() nounwind {
entry:
- %letter = alloca i8 ; <i8*> [#uses=0]
- %prodvers = alloca [256 x i8] ; <[256 x i8]*> [#uses=1]
- %buildver = alloca [256 x i8] ; <[256 x i8]*> [#uses=0]
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 undef, i8* align 1 getelementptr inbounds ([256 x i8], [256 x i8]* @.str523, i32 0, i32 0), i32 256, i1 false)
- %prodvers2 = bitcast [256 x i8]* %prodvers to i8* ; <i8*> [#uses=1]
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %prodvers2, i8* align 1 getelementptr inbounds ([256 x i8], [256 x i8]* @.str523, i32 0, i32 0), i32 256, i1 false)
+ %letter = alloca i8 ; <ptr> [#uses=0]
+ %prodvers = alloca [256 x i8] ; <ptr> [#uses=1]
+ %buildver = alloca [256 x i8] ; <ptr> [#uses=0]
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 undef, ptr align 1 @.str523, i32 256, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 %prodvers, ptr align 1 @.str523, i32 256, i1 false)
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/crash-greedy-v6.ll b/llvm/test/CodeGen/ARM/crash-greedy-v6.ll
index a0241d95a7c6f..2a7dd90f80273 100644
--- a/llvm/test/CodeGen/ARM/crash-greedy-v6.ll
+++ b/llvm/test/CodeGen/ARM/crash-greedy-v6.ll
@@ -4,7 +4,7 @@ target triple = "armv6-apple-ios"
; Reduced from 177.mesa. This test causes a live range split before an LDR_POST instruction.
; That requires leaveIntvBefore to be very accurate about the redefined value number.
-define internal void @sample_nearest_3d(i8* nocapture %tObj, i32 %n, float* nocapture %s, float* nocapture %t, float* nocapture %u, float* nocapture %lambda, i8* nocapture %red, i8* nocapture %green, i8* nocapture %blue, i8* nocapture %alpha) nounwind ssp {
+define internal void @sample_nearest_3d(ptr nocapture %tObj, i32 %n, ptr nocapture %s, ptr nocapture %t, ptr nocapture %u, ptr nocapture %lambda, ptr nocapture %red, ptr nocapture %green, ptr nocapture %blue, ptr nocapture %alpha) nounwind ssp {
entry:
br i1 undef, label %for.end, label %for.body.lr.ph
@@ -32,14 +32,14 @@ for.body: ; preds = %for.body, %for.body
; SOURCE-SCHED: cmp
; SOURCE-SCHED: bne
%i.031 = phi i32 [ 0, %for.body.lr.ph ], [ %0, %for.body ]
- %arrayidx11 = getelementptr float, float* %t, i32 %i.031
- %arrayidx15 = getelementptr float, float* %u, i32 %i.031
- %arrayidx19 = getelementptr i8, i8* %red, i32 %i.031
- %arrayidx22 = getelementptr i8, i8* %green, i32 %i.031
- %arrayidx25 = getelementptr i8, i8* %blue, i32 %i.031
- %arrayidx28 = getelementptr i8, i8* %alpha, i32 %i.031
- %tmp12 = load float, float* %arrayidx11, align 4
- tail call fastcc void @sample_3d_nearest(i8* %tObj, i8* undef, float undef, float %tmp12, float undef, i8* %arrayidx19, i8* %arrayidx22, i8* %arrayidx25, i8* %arrayidx28)
+ %arrayidx11 = getelementptr float, ptr %t, i32 %i.031
+ %arrayidx15 = getelementptr float, ptr %u, i32 %i.031
+ %arrayidx19 = getelementptr i8, ptr %red, i32 %i.031
+ %arrayidx22 = getelementptr i8, ptr %green, i32 %i.031
+ %arrayidx25 = getelementptr i8, ptr %blue, i32 %i.031
+ %arrayidx28 = getelementptr i8, ptr %alpha, i32 %i.031
+ %tmp12 = load float, ptr %arrayidx11, align 4
+ tail call fastcc void @sample_3d_nearest(ptr %tObj, ptr undef, float undef, float %tmp12, float undef, ptr %arrayidx19, ptr %arrayidx22, ptr %arrayidx25, ptr %arrayidx28)
%0 = add i32 %i.031, 1
%exitcond = icmp eq i32 %0, %n
br i1 %exitcond, label %for.end, label %for.body
@@ -48,5 +48,5 @@ for.end: ; preds = %for.body, %entry
ret void
}
-declare fastcc void @sample_3d_nearest(i8* nocapture, i8* nocapture, float, float, float, i8* nocapture, i8* nocapture, i8* nocapture, i8* nocapture) nounwind ssp
+declare fastcc void @sample_3d_nearest(ptr nocapture, ptr nocapture, float, float, float, ptr nocapture, ptr nocapture, ptr nocapture, ptr nocapture) nounwind ssp
diff --git a/llvm/test/CodeGen/ARM/crash-greedy.ll b/llvm/test/CodeGen/ARM/crash-greedy.ll
index bd0f85556b8f8..fd874242a6fef 100644
--- a/llvm/test/CodeGen/ARM/crash-greedy.ll
+++ b/llvm/test/CodeGen/ARM/crash-greedy.ll
@@ -7,7 +7,7 @@ target triple = "thumbv7-apple-darwin"
declare double @exp(double)
; CHECK: remat_subreg
-define void @remat_subreg(float* nocapture %x, i32* %y, i32 %n, i32 %z, float %c, float %lambda, float* nocapture %ret_f, float* nocapture %ret_df, i1 %cond) nounwind {
+define void @remat_subreg(ptr nocapture %x, ptr %y, i32 %n, i32 %z, float %c, float %lambda, ptr nocapture %ret_f, ptr nocapture %ret_df, i1 %cond) nounwind {
entry:
%conv16 = fpext float %lambda to double
%mul17 = fmul double %conv16, -1.000000e+00
@@ -43,7 +43,7 @@ for.end: ; preds = %cond.end
%div129 = fdiv double %add103, %add88
%add130 = fadd double %sub, %div129
%conv131 = fptrunc double %add130 to float
- store float %conv131, float* %ret_f, align 4
+ store float %conv131, ptr %ret_f, align 4
%mul139 = fmul double %div129, %div129
%div142 = fdiv double %add121, %add88
%sub143 = fsub double %mul139, %div142
@@ -55,7 +55,7 @@ for.end: ; preds = %cond.end
%div148 = fdiv double 1.000000e+00, %conv147
%sub149 = fsub double %sub143, %div148
%conv150 = fptrunc double %sub149 to float
- store float %conv150, float* %ret_df, align 4
+ store float %conv150, ptr %ret_df, align 4
ret void
}
@@ -76,7 +76,7 @@ if.then195: ; preds = %if.then84
%vecinit208 = insertelement <4 x float> %vecinit207, float 1.000000e+00, i32 2
%vecinit209 = insertelement <4 x float> %vecinit208, float 1.000000e+00, i32 3
%mul216 = fmul <4 x float> zeroinitializer, %vecinit209
- store <4 x float> %mul216, <4 x float>* undef, align 16
+ store <4 x float> %mul216, ptr undef, align 16
br label %if.end251
if.end251: ; preds = %if.then195, %if.then84, %entry
diff --git a/llvm/test/CodeGen/ARM/crash-on-pow2-shufflevector.ll b/llvm/test/CodeGen/ARM/crash-on-pow2-shufflevector.ll
index bc1a58536c0f4..8186f6c9b42fb 100644
--- a/llvm/test/CodeGen/ARM/crash-on-pow2-shufflevector.ll
+++ b/llvm/test/CodeGen/ARM/crash-on-pow2-shufflevector.ll
@@ -5,7 +5,7 @@
%struct.desc = type { i32, [7 x i32] }
-define i32 @foo(%struct.desc* %descs, i32 %num, i32 %cw) local_unnamed_addr #0 {
+define i32 @foo(ptr %descs, i32 %num, i32 %cw) local_unnamed_addr #0 {
; CHECK-LABEL: foo:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, [r0, #32]
@@ -13,8 +13,7 @@ define i32 @foo(%struct.desc* %descs, i32 %num, i32 %cw) local_unnamed_addr #0 {
; CHECK-NEXT: vmov.32 r0, d16[0]
; CHECK-NEXT: bx lr
entry:
- %descs.vec = bitcast %struct.desc* %descs to <16 x i32>*
- %wide.vec = load <16 x i32>, <16 x i32>* %descs.vec, align 4
+ %wide.vec = load <16 x i32>, ptr %descs, align 4
%strided.vec = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <2 x i32> <i32 0, i32 8>
%bin.rdx20 = add <2 x i32> %strided.vec, %strided.vec
%0 = extractelement <2 x i32> %bin.rdx20, i32 1
diff --git a/llvm/test/CodeGen/ARM/crash.ll b/llvm/test/CodeGen/ARM/crash.ll
index 3b7a897e10c06..1e74766175377 100644
--- a/llvm/test/CodeGen/ARM/crash.ll
+++ b/llvm/test/CodeGen/ARM/crash.ll
@@ -5,7 +5,7 @@
define void @func() nounwind {
entry:
- %tmp = load i32, i32* undef, align 4
+ %tmp = load i32, ptr undef, align 4
br label %bb1
bb1:
@@ -17,8 +17,8 @@ bb1:
bb2:
%tmp120 = add i32 %tmp119, 0
- %scevgep810.i = getelementptr %struct.foo, %struct.foo* null, i32 %tmp120, i32 1
- store i32 undef, i32* %scevgep810.i, align 4
+ %scevgep810.i = getelementptr %struct.foo, ptr null, i32 %tmp120, i32 1
+ store i32 undef, ptr %scevgep810.i, align 4
br i1 undef, label %bb2, label %bb3
bb3:
@@ -45,7 +45,7 @@ bb:
%tmp18 = bitcast i128 %tmp17 to <4 x float>
%tmp19 = bitcast <4 x float> %tmp18 to i128
%tmp20 = bitcast i128 %tmp19 to <4 x float>
- store <4 x float> %tmp20, <4 x float>* undef, align 16
+ store <4 x float> %tmp20, ptr undef, align 16
ret void
}
@@ -66,7 +66,7 @@ bb:
%tmp152 = bitcast i128 %tmp139 to <4 x float>
%tmp153 = bitcast <4 x float> %tmp152 to i128
%tmp154 = bitcast i128 %tmp153 to <4 x float>
- store <4 x float> %tmp154, <4 x float>* undef, align 16
+ store <4 x float> %tmp154, ptr undef, align 16
ret void
}
@@ -74,17 +74,17 @@ bb:
%A = type { %B }
%B = type { i32 }
-define void @_Z3Foov() ssp personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
+define void @_Z3Foov() ssp personality ptr @__gxx_personality_sj0 {
entry:
br i1 true, label %exit, label %false
false:
- invoke void undef(%A* undef)
+ invoke void undef(ptr undef)
to label %exit unwind label %lpad
lpad:
- %0 = landingpad { i8*, i32 }
- catch i8* null
+ %0 = landingpad { ptr, i32 }
+ catch ptr null
unreachable
exit:
diff --git a/llvm/test/CodeGen/ARM/cse-call.ll b/llvm/test/CodeGen/ARM/cse-call.ll
index f0175cbef4a75..3fc935bb321d3 100644
--- a/llvm/test/CodeGen/ARM/cse-call.ll
+++ b/llvm/test/CodeGen/ARM/cse-call.ll
@@ -12,10 +12,10 @@ target triple = "armv6-apple-ios0.0.0"
@F_floatmul.man1 = external global [200 x i8], align 1
@F_floatmul.man2 = external global [200 x i8], align 1
-declare i32 @strlen(i8* nocapture) nounwind readonly
+declare i32 @strlen(ptr nocapture) nounwind readonly
declare void @S_trimzeros(...)
-define i8* @F_floatmul(i8* %f1, i8* %f2, i32 %a, i32 %b) nounwind ssp {
+define ptr @F_floatmul(ptr %f1, ptr %f2, i32 %a, i32 %b) nounwind ssp {
entry:
%0 = icmp eq i32 %a, %b
br i1 %0, label %while.end42, label %while.body37
@@ -24,9 +24,9 @@ while.body37: ; preds = %while.body37, %entr
br i1 false, label %while.end42, label %while.body37
while.end42: ; preds = %while.body37, %entry
- %. = select i1 %0, i8* getelementptr inbounds ([200 x i8], [200 x i8]* @F_floatmul.man1, i32 0, i32 0), i8* getelementptr inbounds ([200 x i8], [200 x i8]* @F_floatmul.man2, i32 0, i32 0)
- %.92 = select i1 %0, i8* getelementptr inbounds ([200 x i8], [200 x i8]* @F_floatmul.man2, i32 0, i32 0), i8* getelementptr inbounds ([200 x i8], [200 x i8]* @F_floatmul.man1, i32 0, i32 0)
- tail call void bitcast (void (...)* @S_trimzeros to void (i8*)*)(i8* %.92) nounwind
- %call47 = tail call i32 @strlen(i8* %.) nounwind
+ %. = select i1 %0, ptr @F_floatmul.man1, ptr @F_floatmul.man2
+ %.92 = select i1 %0, ptr @F_floatmul.man2, ptr @F_floatmul.man1
+ tail call void @S_trimzeros(ptr %.92) nounwind
+ %call47 = tail call i32 @strlen(ptr %.) nounwind
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/cse-flags.ll b/llvm/test/CodeGen/ARM/cse-flags.ll
index c18e2fcb6039b..15bc841917929 100644
--- a/llvm/test/CodeGen/ARM/cse-flags.ll
+++ b/llvm/test/CodeGen/ARM/cse-flags.ll
@@ -10,9 +10,9 @@ target triple = "armv7--linux-gnueabihf"
; CHECK-NEXT: cmp r{{[0-9]+}}, #1{{$}}
; CHECK-NEXT: cmpne r[[T0]], #0{{$}}
; CHECK-NEXT: bne .LBB0_1{{$}}
-define i8* @h(i8* readonly %a, i32 %b, i32 %c) {
+define ptr @h(ptr readonly %a, i32 %b, i32 %c) {
entry:
- %0 = load i8, i8* %a, align 1
+ %0 = load i8, ptr %a, align 1
%tobool4 = icmp ne i8 %0, 0
%cmp5 = icmp ne i32 %b, 1
%1 = and i1 %cmp5, %tobool4
@@ -22,22 +22,22 @@ while.body.preheader: ; preds = %entry
br label %while.body
while.body: ; preds = %while.body.preheader, %while.body
- %a.addr.06 = phi i8* [ %incdec.ptr, %while.body ], [ %a, %while.body.preheader ]
- %call = tail call i32 bitcast (i32 (...)* @f to i32 ()*)()
- %incdec.ptr = getelementptr inbounds i8, i8* %a.addr.06, i32 1
- %2 = load i8, i8* %incdec.ptr, align 1
+ %a.addr.06 = phi ptr [ %incdec.ptr, %while.body ], [ %a, %while.body.preheader ]
+ %call = tail call i32 @f()
+ %incdec.ptr = getelementptr inbounds i8, ptr %a.addr.06, i32 1
+ %2 = load i8, ptr %incdec.ptr, align 1
%tobool = icmp ne i8 %2, 0
%cmp = icmp ne i32 %call, 1
%3 = and i1 %cmp, %tobool
br i1 %3, label %while.body, label %while.end.loopexit
while.end.loopexit: ; preds = %while.body
- %incdec.ptr.lcssa = phi i8* [ %incdec.ptr, %while.body ]
+ %incdec.ptr.lcssa = phi ptr [ %incdec.ptr, %while.body ]
br label %while.end
while.end: ; preds = %while.end.loopexit, %entry
- %a.addr.0.lcssa = phi i8* [ %a, %entry ], [ %incdec.ptr.lcssa, %while.end.loopexit ]
- ret i8* %a.addr.0.lcssa
+ %a.addr.0.lcssa = phi ptr [ %a, %entry ], [ %incdec.ptr.lcssa, %while.end.loopexit ]
+ ret ptr %a.addr.0.lcssa
}
declare i32 @f(...)
diff --git a/llvm/test/CodeGen/ARM/cse-ldrlit.ll b/llvm/test/CodeGen/ARM/cse-ldrlit.ll
index 4f369d0a78eab..d56abc49c128f 100644
--- a/llvm/test/CodeGen/ARM/cse-ldrlit.ll
+++ b/llvm/test/CodeGen/ARM/cse-ldrlit.ll
@@ -6,14 +6,14 @@
; RUN: llc -mtriple=arm-apple-none-macho -relocation-model=static -o - %s | FileCheck %s --check-prefix=CHECK-STATIC
@var = global [16 x i32] zeroinitializer
-declare void @bar(i32*)
+declare void @bar(ptr)
define void @foo() {
- %flag = load i32, i32* getelementptr inbounds([16 x i32], [16 x i32]* @var, i32 0, i32 1)
+ %flag = load i32, ptr getelementptr inbounds([16 x i32], ptr @var, i32 0, i32 1)
%tst = icmp eq i32 %flag, 0
br i1 %tst, label %true, label %false
true:
- tail call void @bar(i32* getelementptr inbounds([16 x i32], [16 x i32]* @var, i32 0, i32 4))
+ tail call void @bar(ptr getelementptr inbounds([16 x i32], ptr @var, i32 0, i32 4))
ret void
false:
ret void
diff --git a/llvm/test/CodeGen/ARM/cse-libcalls.ll b/llvm/test/CodeGen/ARM/cse-libcalls.ll
index 3e0d46c80ab14..14f67cfa8181f 100644
--- a/llvm/test/CodeGen/ARM/cse-libcalls.ll
+++ b/llvm/test/CodeGen/ARM/cse-libcalls.ll
@@ -10,7 +10,7 @@ target triple = "arm-apple-darwin8"
define double @u_f_nonbon(double %lambda) nounwind {
entry:
- %tmp19.i.i = load double, double* null, align 4 ; <double> [#uses=2]
+ %tmp19.i.i = load double, ptr null, align 4 ; <double> [#uses=2]
%tmp6.i = fcmp olt double %tmp19.i.i, 1.000000e+00 ; <i1> [#uses=1]
%dielectric.0.i = select i1 %tmp6.i, double 1.000000e+00, double %tmp19.i.i ; <double> [#uses=1]
%tmp10.i4 = fdiv double 0x4074C2D71F36262D, %dielectric.0.i ; <double> [#uses=1]
diff --git a/llvm/test/CodeGen/ARM/csr-split.ll b/llvm/test/CodeGen/ARM/csr-split.ll
index 199e9a8eed715..8db2a14041c58 100644
--- a/llvm/test/CodeGen/ARM/csr-split.ll
+++ b/llvm/test/CodeGen/ARM/csr-split.ll
@@ -5,7 +5,7 @@
@a = common dso_local local_unnamed_addr global i32 0, align 4
-define dso_local signext i32 @test1(i32* %b) local_unnamed_addr {
+define dso_local signext i32 @test1(ptr %b) local_unnamed_addr {
; CHECK-LABEL: test1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push {r4, lr}
@@ -25,15 +25,15 @@ define dso_local signext i32 @test1(i32* %b) local_unnamed_addr {
; CHECK-NEXT: .LCPI0_0:
; CHECK-NEXT: .long a
entry:
- %0 = load i32, i32* @a, align 4, !tbaa !2
+ %0 = load i32, ptr @a, align 4, !tbaa !2
%conv = sext i32 %0 to i64
- %1 = inttoptr i64 %conv to i32*
- %cmp = icmp eq i32* %1, %b
+ %1 = inttoptr i64 %conv to ptr
+ %cmp = icmp eq ptr %1, %b
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
- %call = tail call signext i32 bitcast (i32 (...)* @callVoid to i32 ()*)()
- %call2 = tail call signext i32 @callNonVoid(i32* %b)
+ %call = tail call signext i32 @callVoid()
+ %call2 = tail call signext i32 @callNonVoid(ptr %b)
br label %if.end
if.end: ; preds = %if.then, %entry
@@ -43,9 +43,9 @@ if.end: ; preds = %if.then, %entry
declare signext i32 @callVoid(...) local_unnamed_addr
-declare signext i32 @callNonVoid(i32*) local_unnamed_addr
+declare signext i32 @callNonVoid(ptr) local_unnamed_addr
-define dso_local signext i32 @test2(i32* %p1) local_unnamed_addr {
+define dso_local signext i32 @test2(ptr %p1) local_unnamed_addr {
; CHECK-LABEL: test2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push {r4, lr}
@@ -71,19 +71,19 @@ define dso_local signext i32 @test2(i32* %p1) local_unnamed_addr {
; CHECK-NEXT: .LCPI1_0:
; CHECK-NEXT: .long a
entry:
- %tobool = icmp eq i32* %p1, null
+ %tobool = icmp eq ptr %p1, null
br i1 %tobool, label %return, label %if.end
if.end: ; preds = %entry
- %0 = load i32, i32* @a, align 4, !tbaa !2
+ %0 = load i32, ptr @a, align 4, !tbaa !2
%conv = sext i32 %0 to i64
- %1 = inttoptr i64 %conv to i32*
- %cmp = icmp eq i32* %1, %p1
+ %1 = inttoptr i64 %conv to ptr
+ %cmp = icmp eq ptr %1, %p1
br i1 %cmp, label %if.then2, label %return
if.then2: ; preds = %if.end
- %call = tail call signext i32 bitcast (i32 (...)* @callVoid to i32 ()*)()
- %call3 = tail call signext i32 @callNonVoid(i32* nonnull %p1)
+ %call = tail call signext i32 @callVoid()
+ %call3 = tail call signext i32 @callNonVoid(ptr nonnull %p1)
br label %return
return: ; preds = %if.end, %entry, %if.then2
@@ -92,7 +92,7 @@ return: ; preds = %if.end, %entry, %if
}
-define dso_local i8* @test3(i8** nocapture %p1, i8 zeroext %p2) local_unnamed_addr {
+define dso_local ptr @test3(ptr nocapture %p1, i8 zeroext %p2) local_unnamed_addr {
; CHECK-LABEL: test3:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push {r4, r5, r11, lr}
@@ -109,20 +109,20 @@ define dso_local i8* @test3(i8** nocapture %p1, i8 zeroext %p2) local_unnamed_ad
; CHECK-NEXT: pop {r4, r5, r11, lr}
; CHECK-NEXT: mov pc, lr
entry:
- %0 = load i8*, i8** %p1, align 8, !tbaa !6
- %tobool = icmp eq i8* %0, null
+ %0 = load ptr, ptr %p1, align 8, !tbaa !6
+ %tobool = icmp eq ptr %0, null
br i1 %tobool, label %land.end, label %land.rhs
land.rhs: ; preds = %entry
- %call = tail call i8* @bar(i8* nonnull %0, i8 zeroext %p2)
- store i8* %call, i8** %p1, align 8, !tbaa !6
+ %call = tail call ptr @bar(ptr nonnull %0, i8 zeroext %p2)
+ store ptr %call, ptr %p1, align 8, !tbaa !6
br label %land.end
land.end: ; preds = %entry, %land.rhs
- ret i8* %0
+ ret ptr %0
}
-declare i8* @bar(i8*, i8 zeroext) local_unnamed_addr
+declare ptr @bar(ptr, i8 zeroext) local_unnamed_addr
!llvm.module.flags = !{!0}
diff --git a/llvm/test/CodeGen/ARM/ctor_order.ll b/llvm/test/CodeGen/ARM/ctor_order.ll
index ca14b3ac3f184..8023e842635dd 100644
--- a/llvm/test/CodeGen/ARM/ctor_order.ll
+++ b/llvm/test/CodeGen/ARM/ctor_order.ll
@@ -21,7 +21,7 @@
; GNUEABI: .long f152
- at llvm.global_ctors = appending global [2 x { i32, void ()*, i8* }] [ { i32, void ()*, i8* } { i32 151, void ()* @f151, i8* null }, { i32, void ()*, i8* } { i32 152, void ()* @f152, i8* null } ]
+ at llvm.global_ctors = appending global [2 x { i32, ptr, ptr }] [ { i32, ptr, ptr } { i32 151, ptr @f151, ptr null }, { i32, ptr, ptr } { i32 152, ptr @f152, ptr null } ]
define void @f151() {
entry:
diff --git a/llvm/test/CodeGen/ARM/ctors_dtors.ll b/llvm/test/CodeGen/ARM/ctors_dtors.ll
index 5778d3634e27d..b85d5c91abc49 100644
--- a/llvm/test/CodeGen/ARM/ctors_dtors.ll
+++ b/llvm/test/CodeGen/ARM/ctors_dtors.ll
@@ -17,8 +17,8 @@
; GNUEABI: .section .init_array,"aw",%init_array
; GNUEABI: .section .fini_array,"aw",%fini_array
- at llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [ { i32, void ()*, i8* } { i32 65535, void ()* @__mf_init, i8* null } ] ; <[1 x { i32, void ()*, i8* }]*> [#uses=0]
- at llvm.global_dtors = appending global [1 x { i32, void ()*, i8* }] [ { i32, void ()*, i8* } { i32 65535, void ()* @__mf_fini, i8* null } ] ; <[1 x { i32, void ()*, i8* }]*> [#uses=0]
+ at llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [ { i32, ptr, ptr } { i32 65535, ptr @__mf_init, ptr null } ] ; <ptr> [#uses=0]
+ at llvm.global_dtors = appending global [1 x { i32, ptr, ptr }] [ { i32, ptr, ptr } { i32 65535, ptr @__mf_fini, ptr null } ] ; <ptr> [#uses=0]
define void @__mf_init() {
entry:
diff --git a/llvm/test/CodeGen/ARM/cttz_vector.ll b/llvm/test/CodeGen/ARM/cttz_vector.ll
index f27c1e4b41733..a68b0b529cdf2 100644
--- a/llvm/test/CodeGen/ARM/cttz_vector.ll
+++ b/llvm/test/CodeGen/ARM/cttz_vector.ll
@@ -23,7 +23,7 @@ declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)
;------------------------------------------------------------------------------
-define void @test_v1i8(<1 x i8>* %p) {
+define void @test_v1i8(ptr %p) {
; CHECK-LABEL: test_v1i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrb r1, [r0]
@@ -32,13 +32,13 @@ define void @test_v1i8(<1 x i8>* %p) {
; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: strb r1, [r0]
; CHECK-NEXT: bx lr
- %a = load <1 x i8>, <1 x i8>* %p
+ %a = load <1 x i8>, ptr %p
%tmp = call <1 x i8> @llvm.cttz.v1i8(<1 x i8> %a, i1 false)
- store <1 x i8> %tmp, <1 x i8>* %p
+ store <1 x i8> %tmp, ptr %p
ret void
}
-define void @test_v2i8(<2 x i8>* %p) {
+define void @test_v2i8(ptr %p) {
; CHECK-LABEL: test_v2i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.16 {d16[0]}, [r0:16]
@@ -55,13 +55,13 @@ define void @test_v2i8(<2 x i8>* %p) {
; CHECK-NEXT: strb r1, [r0, #1]
; CHECK-NEXT: strb r2, [r0]
; CHECK-NEXT: bx lr
- %a = load <2 x i8>, <2 x i8>* %p
+ %a = load <2 x i8>, ptr %p
%tmp = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> %a, i1 false)
- store <2 x i8> %tmp, <2 x i8>* %p
+ store <2 x i8> %tmp, ptr %p
ret void
}
-define void @test_v4i8(<4 x i8>* %p) {
+define void @test_v4i8(ptr %p) {
; CHECK-LABEL: test_v4i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]
@@ -76,13 +76,13 @@ define void @test_v4i8(<4 x i8>* %p) {
; CHECK-NEXT: vuzp.8 d16, d17
; CHECK-NEXT: vst1.32 {d16[0]}, [r0:32]
; CHECK-NEXT: bx lr
- %a = load <4 x i8>, <4 x i8>* %p
+ %a = load <4 x i8>, ptr %p
%tmp = call <4 x i8> @llvm.cttz.v4i8(<4 x i8> %a, i1 false)
- store <4 x i8> %tmp, <4 x i8>* %p
+ store <4 x i8> %tmp, ptr %p
ret void
}
-define void @test_v8i8(<8 x i8>* %p) {
+define void @test_v8i8(ptr %p) {
; CHECK-LABEL: test_v8i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -93,13 +93,13 @@ define void @test_v8i8(<8 x i8>* %p) {
; CHECK-NEXT: vcnt.8 d16, d16
; CHECK-NEXT: vstr d16, [r0]
; CHECK-NEXT: bx lr
- %a = load <8 x i8>, <8 x i8>* %p
+ %a = load <8 x i8>, ptr %p
%tmp = call <8 x i8> @llvm.cttz.v8i8(<8 x i8> %a, i1 false)
- store <8 x i8> %tmp, <8 x i8>* %p
+ store <8 x i8> %tmp, ptr %p
ret void
}
-define void @test_v16i8(<16 x i8>* %p) {
+define void @test_v16i8(ptr %p) {
; CHECK-LABEL: test_v16i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -110,13 +110,13 @@ define void @test_v16i8(<16 x i8>* %p) {
; CHECK-NEXT: vcnt.8 q8, q8
; CHECK-NEXT: vst1.64 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
- %a = load <16 x i8>, <16 x i8>* %p
+ %a = load <16 x i8>, ptr %p
%tmp = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %a, i1 false)
- store <16 x i8> %tmp, <16 x i8>* %p
+ store <16 x i8> %tmp, ptr %p
ret void
}
-define void @test_v1i16(<1 x i16>* %p) {
+define void @test_v1i16(ptr %p) {
; CHECK-LABEL: test_v1i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrh r1, [r0]
@@ -125,13 +125,13 @@ define void @test_v1i16(<1 x i16>* %p) {
; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: strh r1, [r0]
; CHECK-NEXT: bx lr
- %a = load <1 x i16>, <1 x i16>* %p
+ %a = load <1 x i16>, ptr %p
%tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 false)
- store <1 x i16> %tmp, <1 x i16>* %p
+ store <1 x i16> %tmp, ptr %p
ret void
}
-define void @test_v2i16(<2 x i16>* %p) {
+define void @test_v2i16(ptr %p) {
; CHECK-LABEL: test_v2i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]
@@ -145,13 +145,13 @@ define void @test_v2i16(<2 x i16>* %p) {
; CHECK-NEXT: vuzp.16 d16, d17
; CHECK-NEXT: vst1.32 {d16[0]}, [r0:32]
; CHECK-NEXT: bx lr
- %a = load <2 x i16>, <2 x i16>* %p
+ %a = load <2 x i16>, ptr %p
%tmp = call <2 x i16> @llvm.cttz.v2i16(<2 x i16> %a, i1 false)
- store <2 x i16> %tmp, <2 x i16>* %p
+ store <2 x i16> %tmp, ptr %p
ret void
}
-define void @test_v4i16(<4 x i16>* %p) {
+define void @test_v4i16(ptr %p) {
; CHECK-LABEL: test_v4i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -163,13 +163,13 @@ define void @test_v4i16(<4 x i16>* %p) {
; CHECK-NEXT: vpaddl.u8 d16, d16
; CHECK-NEXT: vstr d16, [r0]
; CHECK-NEXT: bx lr
- %a = load <4 x i16>, <4 x i16>* %p
+ %a = load <4 x i16>, ptr %p
%tmp = call <4 x i16> @llvm.cttz.v4i16(<4 x i16> %a, i1 false)
- store <4 x i16> %tmp, <4 x i16>* %p
+ store <4 x i16> %tmp, ptr %p
ret void
}
-define void @test_v8i16(<8 x i16>* %p) {
+define void @test_v8i16(ptr %p) {
; CHECK-LABEL: test_v8i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -181,13 +181,13 @@ define void @test_v8i16(<8 x i16>* %p) {
; CHECK-NEXT: vpaddl.u8 q8, q8
; CHECK-NEXT: vst1.64 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
- %a = load <8 x i16>, <8 x i16>* %p
+ %a = load <8 x i16>, ptr %p
%tmp = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %a, i1 false)
- store <8 x i16> %tmp, <8 x i16>* %p
+ store <8 x i16> %tmp, ptr %p
ret void
}
-define void @test_v1i32(<1 x i32>* %p) {
+define void @test_v1i32(ptr %p) {
; CHECK-LABEL: test_v1i32:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r1, [r0]
@@ -195,13 +195,13 @@ define void @test_v1i32(<1 x i32>* %p) {
; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %a = load <1 x i32>, <1 x i32>* %p
+ %a = load <1 x i32>, ptr %p
%tmp = call <1 x i32> @llvm.cttz.v1i32(<1 x i32> %a, i1 false)
- store <1 x i32> %tmp, <1 x i32>* %p
+ store <1 x i32> %tmp, ptr %p
ret void
}
-define void @test_v2i32(<2 x i32>* %p) {
+define void @test_v2i32(ptr %p) {
; CHECK-LABEL: test_v2i32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -214,13 +214,13 @@ define void @test_v2i32(<2 x i32>* %p) {
; CHECK-NEXT: vpaddl.u16 d16, d16
; CHECK-NEXT: vstr d16, [r0]
; CHECK-NEXT: bx lr
- %a = load <2 x i32>, <2 x i32>* %p
+ %a = load <2 x i32>, ptr %p
%tmp = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a, i1 false)
- store <2 x i32> %tmp, <2 x i32>* %p
+ store <2 x i32> %tmp, ptr %p
ret void
}
-define void @test_v4i32(<4 x i32>* %p) {
+define void @test_v4i32(ptr %p) {
; CHECK-LABEL: test_v4i32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -233,13 +233,13 @@ define void @test_v4i32(<4 x i32>* %p) {
; CHECK-NEXT: vpaddl.u16 q8, q8
; CHECK-NEXT: vst1.64 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
- %a = load <4 x i32>, <4 x i32>* %p
+ %a = load <4 x i32>, ptr %p
%tmp = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 false)
- store <4 x i32> %tmp, <4 x i32>* %p
+ store <4 x i32> %tmp, ptr %p
ret void
}
-define void @test_v1i64(<1 x i64>* %p) {
+define void @test_v1i64(ptr %p) {
; CHECK-LABEL: test_v1i64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d16, #0x0
@@ -254,13 +254,13 @@ define void @test_v1i64(<1 x i64>* %p) {
; CHECK-NEXT: vpaddl.u32 d16, d16
; CHECK-NEXT: vstr d16, [r0]
; CHECK-NEXT: bx lr
- %a = load <1 x i64>, <1 x i64>* %p
+ %a = load <1 x i64>, ptr %p
%tmp = call <1 x i64> @llvm.cttz.v1i64(<1 x i64> %a, i1 false)
- store <1 x i64> %tmp, <1 x i64>* %p
+ store <1 x i64> %tmp, ptr %p
ret void
}
-define void @test_v2i64(<2 x i64>* %p) {
+define void @test_v2i64(ptr %p) {
; CHECK-LABEL: test_v2i64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q8, #0x0
@@ -275,15 +275,15 @@ define void @test_v2i64(<2 x i64>* %p) {
; CHECK-NEXT: vpaddl.u32 q8, q8
; CHECK-NEXT: vst1.64 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
- %a = load <2 x i64>, <2 x i64>* %p
+ %a = load <2 x i64>, ptr %p
%tmp = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 false)
- store <2 x i64> %tmp, <2 x i64>* %p
+ store <2 x i64> %tmp, ptr %p
ret void
}
;------------------------------------------------------------------------------
-define void @test_v1i8_zero_undef(<1 x i8>* %p) {
+define void @test_v1i8_zero_undef(ptr %p) {
; CHECK-LABEL: test_v1i8_zero_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrb r1, [r0]
@@ -291,13 +291,13 @@ define void @test_v1i8_zero_undef(<1 x i8>* %p) {
; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: strb r1, [r0]
; CHECK-NEXT: bx lr
- %a = load <1 x i8>, <1 x i8>* %p
+ %a = load <1 x i8>, ptr %p
%tmp = call <1 x i8> @llvm.cttz.v1i8(<1 x i8> %a, i1 true)
- store <1 x i8> %tmp, <1 x i8>* %p
+ store <1 x i8> %tmp, ptr %p
ret void
}
-define void @test_v2i8_zero_undef(<2 x i8>* %p) {
+define void @test_v2i8_zero_undef(ptr %p) {
; CHECK-LABEL: test_v2i8_zero_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.16 {d16[0]}, [r0:16]
@@ -313,13 +313,13 @@ define void @test_v2i8_zero_undef(<2 x i8>* %p) {
; CHECK-NEXT: strb r1, [r0, #1]
; CHECK-NEXT: strb r2, [r0]
; CHECK-NEXT: bx lr
- %a = load <2 x i8>, <2 x i8>* %p
+ %a = load <2 x i8>, ptr %p
%tmp = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> %a, i1 true)
- store <2 x i8> %tmp, <2 x i8>* %p
+ store <2 x i8> %tmp, ptr %p
ret void
}
-define void @test_v4i8_zero_undef(<4 x i8>* %p) {
+define void @test_v4i8_zero_undef(ptr %p) {
; CHECK-LABEL: test_v4i8_zero_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]
@@ -332,13 +332,13 @@ define void @test_v4i8_zero_undef(<4 x i8>* %p) {
; CHECK-NEXT: vuzp.8 d16, d17
; CHECK-NEXT: vst1.32 {d16[0]}, [r0:32]
; CHECK-NEXT: bx lr
- %a = load <4 x i8>, <4 x i8>* %p
+ %a = load <4 x i8>, ptr %p
%tmp = call <4 x i8> @llvm.cttz.v4i8(<4 x i8> %a, i1 true)
- store <4 x i8> %tmp, <4 x i8>* %p
+ store <4 x i8> %tmp, ptr %p
ret void
}
-define void @test_v8i8_zero_undef(<8 x i8>* %p) {
+define void @test_v8i8_zero_undef(ptr %p) {
; CHECK-LABEL: test_v8i8_zero_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -349,13 +349,13 @@ define void @test_v8i8_zero_undef(<8 x i8>* %p) {
; CHECK-NEXT: vcnt.8 d16, d16
; CHECK-NEXT: vstr d16, [r0]
; CHECK-NEXT: bx lr
- %a = load <8 x i8>, <8 x i8>* %p
+ %a = load <8 x i8>, ptr %p
%tmp = call <8 x i8> @llvm.cttz.v8i8(<8 x i8> %a, i1 true)
- store <8 x i8> %tmp, <8 x i8>* %p
+ store <8 x i8> %tmp, ptr %p
ret void
}
-define void @test_v16i8_zero_undef(<16 x i8>* %p) {
+define void @test_v16i8_zero_undef(ptr %p) {
; CHECK-LABEL: test_v16i8_zero_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -366,13 +366,13 @@ define void @test_v16i8_zero_undef(<16 x i8>* %p) {
; CHECK-NEXT: vcnt.8 q8, q8
; CHECK-NEXT: vst1.64 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
- %a = load <16 x i8>, <16 x i8>* %p
+ %a = load <16 x i8>, ptr %p
%tmp = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %a, i1 true)
- store <16 x i8> %tmp, <16 x i8>* %p
+ store <16 x i8> %tmp, ptr %p
ret void
}
-define void @test_v1i16_zero_undef(<1 x i16>* %p) {
+define void @test_v1i16_zero_undef(ptr %p) {
; CHECK-LABEL: test_v1i16_zero_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrh r1, [r0]
@@ -380,13 +380,13 @@ define void @test_v1i16_zero_undef(<1 x i16>* %p) {
; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: strh r1, [r0]
; CHECK-NEXT: bx lr
- %a = load <1 x i16>, <1 x i16>* %p
+ %a = load <1 x i16>, ptr %p
%tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 true)
- store <1 x i16> %tmp, <1 x i16>* %p
+ store <1 x i16> %tmp, ptr %p
ret void
}
-define void @test_v2i16_zero_undef(<2 x i16>* %p) {
+define void @test_v2i16_zero_undef(ptr %p) {
; CHECK-LABEL: test_v2i16_zero_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]
@@ -399,13 +399,13 @@ define void @test_v2i16_zero_undef(<2 x i16>* %p) {
; CHECK-NEXT: vuzp.16 d16, d17
; CHECK-NEXT: vst1.32 {d16[0]}, [r0:32]
; CHECK-NEXT: bx lr
- %a = load <2 x i16>, <2 x i16>* %p
+ %a = load <2 x i16>, ptr %p
%tmp = call <2 x i16> @llvm.cttz.v2i16(<2 x i16> %a, i1 true)
- store <2 x i16> %tmp, <2 x i16>* %p
+ store <2 x i16> %tmp, ptr %p
ret void
}
-define void @test_v4i16_zero_undef(<4 x i16>* %p) {
+define void @test_v4i16_zero_undef(ptr %p) {
; CHECK-LABEL: test_v4i16_zero_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -416,13 +416,13 @@ define void @test_v4i16_zero_undef(<4 x i16>* %p) {
; CHECK-NEXT: vsub.i16 d16, d17, d16
; CHECK-NEXT: vstr d16, [r0]
; CHECK-NEXT: bx lr
- %a = load <4 x i16>, <4 x i16>* %p
+ %a = load <4 x i16>, ptr %p
%tmp = call <4 x i16> @llvm.cttz.v4i16(<4 x i16> %a, i1 true)
- store <4 x i16> %tmp, <4 x i16>* %p
+ store <4 x i16> %tmp, ptr %p
ret void
}
-define void @test_v8i16_zero_undef(<8 x i16>* %p) {
+define void @test_v8i16_zero_undef(ptr %p) {
; CHECK-LABEL: test_v8i16_zero_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -433,13 +433,13 @@ define void @test_v8i16_zero_undef(<8 x i16>* %p) {
; CHECK-NEXT: vsub.i16 q8, q9, q8
; CHECK-NEXT: vst1.64 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
- %a = load <8 x i16>, <8 x i16>* %p
+ %a = load <8 x i16>, ptr %p
%tmp = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %a, i1 true)
- store <8 x i16> %tmp, <8 x i16>* %p
+ store <8 x i16> %tmp, ptr %p
ret void
}
-define void @test_v1i32_zero_undef(<1 x i32>* %p) {
+define void @test_v1i32_zero_undef(ptr %p) {
; CHECK-LABEL: test_v1i32_zero_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r1, [r0]
@@ -447,13 +447,13 @@ define void @test_v1i32_zero_undef(<1 x i32>* %p) {
; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %a = load <1 x i32>, <1 x i32>* %p
+ %a = load <1 x i32>, ptr %p
%tmp = call <1 x i32> @llvm.cttz.v1i32(<1 x i32> %a, i1 true)
- store <1 x i32> %tmp, <1 x i32>* %p
+ store <1 x i32> %tmp, ptr %p
ret void
}
-define void @test_v2i32_zero_undef(<2 x i32>* %p) {
+define void @test_v2i32_zero_undef(ptr %p) {
; CHECK-LABEL: test_v2i32_zero_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -464,13 +464,13 @@ define void @test_v2i32_zero_undef(<2 x i32>* %p) {
; CHECK-NEXT: vsub.i32 d16, d17, d16
; CHECK-NEXT: vstr d16, [r0]
; CHECK-NEXT: bx lr
- %a = load <2 x i32>, <2 x i32>* %p
+ %a = load <2 x i32>, ptr %p
%tmp = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a, i1 true)
- store <2 x i32> %tmp, <2 x i32>* %p
+ store <2 x i32> %tmp, ptr %p
ret void
}
-define void @test_v4i32_zero_undef(<4 x i32>* %p) {
+define void @test_v4i32_zero_undef(ptr %p) {
; CHECK-LABEL: test_v4i32_zero_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -481,13 +481,13 @@ define void @test_v4i32_zero_undef(<4 x i32>* %p) {
; CHECK-NEXT: vsub.i32 q8, q9, q8
; CHECK-NEXT: vst1.64 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
- %a = load <4 x i32>, <4 x i32>* %p
+ %a = load <4 x i32>, ptr %p
%tmp = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 true)
- store <4 x i32> %tmp, <4 x i32>* %p
+ store <4 x i32> %tmp, ptr %p
ret void
}
-define void @test_v1i64_zero_undef(<1 x i64>* %p) {
+define void @test_v1i64_zero_undef(ptr %p) {
; CHECK-LABEL: test_v1i64_zero_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d16, #0x0
@@ -502,13 +502,13 @@ define void @test_v1i64_zero_undef(<1 x i64>* %p) {
; CHECK-NEXT: vpaddl.u32 d16, d16
; CHECK-NEXT: vstr d16, [r0]
; CHECK-NEXT: bx lr
- %a = load <1 x i64>, <1 x i64>* %p
+ %a = load <1 x i64>, ptr %p
%tmp = call <1 x i64> @llvm.cttz.v1i64(<1 x i64> %a, i1 true)
- store <1 x i64> %tmp, <1 x i64>* %p
+ store <1 x i64> %tmp, ptr %p
ret void
}
-define void @test_v2i64_zero_undef(<2 x i64>* %p) {
+define void @test_v2i64_zero_undef(ptr %p) {
; CHECK-LABEL: test_v2i64_zero_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q8, #0x0
@@ -523,8 +523,8 @@ define void @test_v2i64_zero_undef(<2 x i64>* %p) {
; CHECK-NEXT: vpaddl.u32 q8, q8
; CHECK-NEXT: vst1.64 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
- %a = load <2 x i64>, <2 x i64>* %p
+ %a = load <2 x i64>, ptr %p
%tmp = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 true)
- store <2 x i64> %tmp, <2 x i64>* %p
+ store <2 x i64> %tmp, ptr %p
ret void
}
diff --git a/llvm/test/CodeGen/ARM/cxx-tlscc.ll b/llvm/test/CodeGen/ARM/cxx-tlscc.ll
index 649ed17db0586..d0c835f4382b7 100644
--- a/llvm/test/CodeGen/ARM/cxx-tlscc.ll
+++ b/llvm/test/CodeGen/ARM/cxx-tlscc.ll
@@ -18,9 +18,9 @@
%class.C = type { i32 }
@tC = internal thread_local global %class.C zeroinitializer, align 4
-declare %struct.S* @_ZN1SC1Ev(%struct.S* returned)
-declare %struct.S* @_ZN1SD1Ev(%struct.S* returned)
-declare i32 @_tlv_atexit(void (i8*)*, i8*, i8*)
+declare ptr @_ZN1SC1Ev(ptr returned)
+declare ptr @_ZN1SD1Ev(ptr returned)
+declare i32 @_tlv_atexit(ptr, ptr, ptr)
; Make sure Epilog does not overwrite an explicitly-handled CSR in CXX_FAST_TLS.
; THUMB-LABEL: _ZTW2sg
@@ -33,18 +33,18 @@ declare i32 @_tlv_atexit(void (i8*)*, i8*, i8*)
; THUMB: blx
; THUMB: r4
; THUMB: pop {{.*}}r4
-define cxx_fast_tlscc nonnull %struct.S* @_ZTW2sg() nounwind "frame-pointer"="all" {
- %.b.i = load i1, i1* @__tls_guard, align 1
+define cxx_fast_tlscc nonnull ptr @_ZTW2sg() nounwind "frame-pointer"="all" {
+ %.b.i = load i1, ptr @__tls_guard, align 1
br i1 %.b.i, label %__tls_init.exit, label %init.i
init.i:
- store i1 true, i1* @__tls_guard, align 1
- %call.i.i = tail call %struct.S* @_ZN1SC1Ev(%struct.S* nonnull @sg)
- %1 = tail call i32 @_tlv_atexit(void (i8*)* nonnull bitcast (%struct.S* (%struct.S*)* @_ZN1SD1Ev to void (i8*)*), i8* nonnull getelementptr inbounds (%struct.S, %struct.S* @sg, i64 0, i32 0), i8* nonnull @__dso_handle)
+ store i1 true, ptr @__tls_guard, align 1
+ %call.i.i = tail call ptr @_ZN1SC1Ev(ptr nonnull @sg)
+ %1 = tail call i32 @_tlv_atexit(ptr nonnull @_ZN1SD1Ev, ptr nonnull @sg, ptr nonnull @__dso_handle)
br label %__tls_init.exit
__tls_init.exit:
- ret %struct.S* @sg
+ ret ptr @sg
}
; CHECK-LABEL: _ZTW2sg
@@ -95,8 +95,8 @@ __tls_init.exit:
; CHECK-O0-NOT: vpop
; CHECK-O0-NOT: vldr
; CHECK-O0: pop
-define cxx_fast_tlscc nonnull i32* @_ZTW4sum1() nounwind "frame-pointer"="all" {
- ret i32* @sum1
+define cxx_fast_tlscc nonnull ptr @_ZTW4sum1() nounwind "frame-pointer"="all" {
+ ret ptr @sum1
}
; Make sure at O0, we don't generate spilling/reloading of the CSRs.
@@ -109,20 +109,20 @@ define cxx_fast_tlscc nonnull i32* @_ZTW4sum1() nounwind "frame-pointer"="all" {
; CHECK-O0-NOT: vldr
; CHECK-O0: pop
declare cxx_fast_tlscc void @tls_helper()
-define cxx_fast_tlscc %class.C* @tls_test2() #1 "frame-pointer"="all" {
+define cxx_fast_tlscc ptr @tls_test2() #1 "frame-pointer"="all" {
call cxx_fast_tlscc void @tls_helper()
- ret %class.C* @tC
+ ret ptr @tC
}
; Make sure we do not allow tail call when caller and callee have
diff erent
; calling conventions.
-declare %class.C* @_ZN1CD1Ev(%class.C* readnone returned %this)
+declare ptr @_ZN1CD1Ev(ptr readnone returned %this)
; CHECK-LABEL: tls_test
; CHECK: bl __tlv_atexit
define cxx_fast_tlscc void @__tls_test() "frame-pointer"="all" {
entry:
- store i32 0, i32* getelementptr inbounds (%class.C, %class.C* @tC, i64 0, i32 0), align 4
- %0 = tail call i32 @_tlv_atexit(void (i8*)* bitcast (%class.C* (%class.C*)* @_ZN1CD1Ev to void (i8*)*), i8* bitcast (%class.C* @tC to i8*), i8* nonnull @__dso_handle) #1
+ store i32 0, ptr @tC, align 4
+ %0 = tail call i32 @_tlv_atexit(ptr @_ZN1CD1Ev, ptr @tC, ptr nonnull @__dso_handle) #1
ret void
}
diff --git a/llvm/test/CodeGen/ARM/dag-combine-ldst.ll b/llvm/test/CodeGen/ARM/dag-combine-ldst.ll
index 077754ef013df..a03e372822f13 100644
--- a/llvm/test/CodeGen/ARM/dag-combine-ldst.ll
+++ b/llvm/test/CodeGen/ARM/dag-combine-ldst.ll
@@ -18,24 +18,24 @@ define i32 @main() {
bb:
%tmp = alloca i32, align 4
%tmp1 = alloca i32, align 4
- store i32 0, i32* %tmp, align 4
- store i32 0, i32* %tmp1, align 4
- %tmp2 = load i32, i32* %tmp1, align 4
+ store i32 0, ptr %tmp, align 4
+ store i32 0, ptr %tmp1, align 4
+ %tmp2 = load i32, ptr %tmp1, align 4
%tmp3 = add nsw i32 %tmp2, 2
- store i32 %tmp3, i32* %tmp1, align 4
- %tmp4 = load i32, i32* %tmp1, align 4
+ store i32 %tmp3, ptr %tmp1, align 4
+ %tmp4 = load i32, ptr %tmp1, align 4
%tmp5 = icmp eq i32 %tmp4, 2
br i1 %tmp5, label %bb6, label %bb7
bb6: ; preds = %bb
- store i32 0, i32* %tmp, align 4
+ store i32 0, ptr %tmp, align 4
br label %bb8
bb7: ; preds = %bb
- store i32 5, i32* %tmp, align 4
+ store i32 5, ptr %tmp, align 4
br label %bb8
bb8: ; preds = %bb7, %bb6
- %tmp9 = load i32, i32* %tmp, align 4
+ %tmp9 = load i32, ptr %tmp, align 4
ret i32 %tmp9
}
diff --git a/llvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll b/llvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
index 19e20881f8d17..a57411ba2cd6b 100644
--- a/llvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
+++ b/llvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
-define float @f(<4 x i16>* nocapture %in) {
+define float @f(ptr nocapture %in) {
; CHECK-LABEL: f:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.16 {d16}, [r0:64]
@@ -11,7 +11,7 @@ define float @f(<4 x i16>* nocapture %in) {
; CHECK-NEXT: vadd.f32 s0, s4, s2
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
- %1 = load <4 x i16>, <4 x i16>* %in
+ %1 = load <4 x i16>, ptr %in
%2 = uitofp <4 x i16> %1 to <4 x float>
%3 = extractelement <4 x float> %2, i32 0
%4 = extractelement <4 x float> %2, i32 1
@@ -23,7 +23,7 @@ define float @f(<4 x i16>* nocapture %in) {
ret float %7
}
-define float @g(<4 x i16>* nocapture %in) {
+define float @g(ptr nocapture %in) {
; CHECK-LABEL: g:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -32,14 +32,14 @@ define float @g(<4 x i16>* nocapture %in) {
; CHECK-NEXT: vcvt.f32.u32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
- %1 = load <4 x i16>, <4 x i16>* %in
+ %1 = load <4 x i16>, ptr %in
%2 = extractelement <4 x i16> %1, i32 0
%3 = uitofp i16 %2 to float
ret float %3
}
; Make sure we generate zext from <4 x i8> to <4 x 32>.
-define <4 x i32> @h(<4 x i8> *%in) {
+define <4 x i32> @h(ptr %in) {
; CHECK-LABEL: h:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]
@@ -53,7 +53,7 @@ define <4 x i32> @h(<4 x i8> *%in) {
; CHECK-NEXT: uxtb r2, r2
; CHECK-NEXT: uxtb r3, r3
; CHECK-NEXT: bx lr
- %1 = load <4 x i8>, <4 x i8>* %in, align 4
+ %1 = load <4 x i8>, ptr %in, align 4
%2 = extractelement <4 x i8> %1, i32 0
%3 = zext i8 %2 to i32
%4 = insertelement <4 x i32> undef, i32 %3, i32 0
@@ -69,7 +69,7 @@ define <4 x i32> @h(<4 x i8> *%in) {
ret <4 x i32> %13
}
-define float @i(<4 x i16>* nocapture %in) {
+define float @i(ptr nocapture %in) {
; CHECK-LABEL: i:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -78,13 +78,13 @@ define float @i(<4 x i16>* nocapture %in) {
; CHECK-NEXT: vcvt.f32.s32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
- %1 = load <4 x i16>, <4 x i16>* %in
+ %1 = load <4 x i16>, ptr %in
%2 = extractelement <4 x i16> %1, i32 0
%3 = sitofp i16 %2 to float
ret float %3
}
-define float @j(<8 x i8>* nocapture %in) {
+define float @j(ptr nocapture %in) {
; CHECK-LABEL: j:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -93,13 +93,13 @@ define float @j(<8 x i8>* nocapture %in) {
; CHECK-NEXT: vcvt.f32.u32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
- %1 = load <8 x i8>, <8 x i8>* %in
+ %1 = load <8 x i8>, ptr %in
%2 = extractelement <8 x i8> %1, i32 7
%3 = uitofp i8 %2 to float
ret float %3
}
-define float @k(<8 x i8>* nocapture %in) {
+define float @k(ptr nocapture %in) {
; CHECK-LABEL: k:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -108,7 +108,7 @@ define float @k(<8 x i8>* nocapture %in) {
; CHECK-NEXT: vcvt.f32.s32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
- %1 = load <8 x i8>, <8 x i8>* %in
+ %1 = load <8 x i8>, ptr %in
%2 = extractelement <8 x i8> %1, i32 7
%3 = sitofp i8 %2 to float
ret float %3
diff --git a/llvm/test/CodeGen/ARM/dagcombine-concatvector.ll b/llvm/test/CodeGen/ARM/dagcombine-concatvector.ll
index 578d80d1cef46..362f64b689a4a 100644
--- a/llvm/test/CodeGen/ARM/dagcombine-concatvector.ll
+++ b/llvm/test/CodeGen/ARM/dagcombine-concatvector.ll
@@ -10,7 +10,7 @@
; CHECK-BE: vmov {{d[0-9]+}}, [[REG]], r3
; CHECK: vst1.8 {{{d[0-9]+}}, {{d[0-9]+}}}, [r0]
; CHECK-NEXT: bx lr
-define void @test1(i8* %arg, [4 x i64] %vec.coerce) {
+define void @test1(ptr %arg, [4 x i64] %vec.coerce) {
bb:
%tmp = extractvalue [4 x i64] %vec.coerce, 0
%tmp2 = bitcast i64 %tmp to <8 x i8>
@@ -19,8 +19,8 @@ bb:
%tmp5 = bitcast i64 %tmp4 to <8 x i8>
%tmp6 = shufflevector <8 x i8> %tmp5, <8 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%tmp7 = shufflevector <16 x i8> %tmp6, <16 x i8> %tmp3, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- tail call void @llvm.arm.neon.vst1.p0i8.v16i8(i8* %arg, <16 x i8> %tmp7, i32 2)
+ tail call void @llvm.arm.neon.vst1.p0.v16i8(ptr %arg, <16 x i8> %tmp7, i32 2)
ret void
}
-declare void @llvm.arm.neon.vst1.p0i8.v16i8(i8*, <16 x i8>, i32)
+declare void @llvm.arm.neon.vst1.p0.v16i8(ptr, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/ARM/darwin-tls-preserved.ll b/llvm/test/CodeGen/ARM/darwin-tls-preserved.ll
index 4969fabfd9b3c..1deb9dd52fbcf 100644
--- a/llvm/test/CodeGen/ARM/darwin-tls-preserved.ll
+++ b/llvm/test/CodeGen/ARM/darwin-tls-preserved.ll
@@ -4,7 +4,7 @@
; r9 and r12 can be live across the asm, but those get clobbered by the TLS
; access (in a
diff erent BB to order it).
-define i32 @test_regs_preserved(i32* %ptr1, i32* %ptr2, i1 %tst1) {
+define i32 @test_regs_preserved(ptr %ptr1, ptr %ptr2, i1 %tst1) {
; CHECK-LABEL: test_regs_preserved:
; CHECK: str {{.*}}, [sp
; CHECK: mov {{.*}}, r12
@@ -13,12 +13,12 @@ entry:
br i1 %tst1, label %get_tls, label %done
get_tls:
- %val = load i32, i32* @tls_var
+ %val = load i32, ptr @tls_var
br label %done
done:
%res = phi i32 [%val, %get_tls], [0, %entry]
- store i32 42, i32* %ptr1
- store i32 42, i32* %ptr2
+ store i32 42, ptr %ptr1
+ store i32 42, ptr %ptr2
ret i32 %res
}
diff --git a/llvm/test/CodeGen/ARM/darwin-tls.ll b/llvm/test/CodeGen/ARM/darwin-tls.ll
index 1043cce6218b7..da56f93bb1b30 100644
--- a/llvm/test/CodeGen/ARM/darwin-tls.ll
+++ b/llvm/test/CodeGen/ARM/darwin-tls.ll
@@ -86,7 +86,7 @@ define i32 @test_local_tls() {
; ARM-LIT-STATIC-NEXT: .long _local_tls_var
- %val = load i32, i32* @local_tls_var, align 4
+ %val = load i32, ptr @local_tls_var, align 4
ret i32 %val
}
@@ -162,13 +162,13 @@ define i32 @test_external_tls() {
; ARM-LIT-STATIC: [[EXTERNAL_VAR_ADDR]]:
; ARM-LIT-STATIC-NEXT: .long _external_tls_var
- %val = load i32, i32* @external_tls_var, align 4
+ %val = load i32, ptr @external_tls_var, align 4
ret i32 %val
}
; Just need something to trigger an indirect reference to the var.
define i32 @use_hidden_external_tls() {
- %val = load i32, i32* @hidden_external_tls_var, align 4
+ %val = load i32, ptr @hidden_external_tls_var, align 4
ret i32 %val
}
diff --git a/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll b/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll
index e5d24253b9888..ad538e1b4c800 100644
--- a/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll
+++ b/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll
@@ -51,8 +51,8 @@ define i32 @test3() {
%retval = alloca i32, align 4
%tmp = alloca i32, align 4
%a = alloca [805306369 x i8], align 16
- store i32 0, i32* %tmp
- %tmp1 = load i32, i32* %tmp
+ store i32 0, ptr %tmp
+ %tmp1 = load i32, ptr %tmp
ret i32 %tmp1
}
diff --git a/llvm/test/CodeGen/ARM/debug-frame-no-debug.ll b/llvm/test/CodeGen/ARM/debug-frame-no-debug.ll
index 8f3965a32e620..aa976bc662dc0 100644
--- a/llvm/test/CodeGen/ARM/debug-frame-no-debug.ll
+++ b/llvm/test/CodeGen/ARM/debug-frame-no-debug.ll
@@ -34,16 +34,16 @@ declare void @_Z5printddddd(double, double, double, double, double)
define void @_Z4testiiiiiddddd(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e,
double %m, double %n, double %p,
- double %q, double %r) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+ double %q, double %r) personality ptr @__gxx_personality_v0 {
entry:
invoke void @_Z5printiiiii(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e)
to label %try.cont unwind label %lpad
lpad:
- %0 = landingpad { i8*, i32 }
- catch i8* null
- %1 = extractvalue { i8*, i32 } %0, 0
- %2 = tail call i8* @__cxa_begin_catch(i8* %1)
+ %0 = landingpad { ptr, i32 }
+ catch ptr null
+ %1 = extractvalue { ptr, i32 } %0, 0
+ %2 = tail call ptr @__cxa_begin_catch(ptr %1)
invoke void @_Z5printddddd(double %m, double %n, double %p,
double %q, double %r)
to label %invoke.cont2 unwind label %lpad1
@@ -56,27 +56,27 @@ try.cont:
ret void
lpad1:
- %3 = landingpad { i8*, i32 }
+ %3 = landingpad { ptr, i32 }
cleanup
invoke void @__cxa_end_catch()
to label %eh.resume unwind label %terminate.lpad
eh.resume:
- resume { i8*, i32 } %3
+ resume { ptr, i32 } %3
terminate.lpad:
- %4 = landingpad { i8*, i32 }
- catch i8* null
- %5 = extractvalue { i8*, i32 } %4, 0
- tail call void @__clang_call_terminate(i8* %5)
+ %4 = landingpad { ptr, i32 }
+ catch ptr null
+ %5 = extractvalue { ptr, i32 } %4, 0
+ tail call void @__clang_call_terminate(ptr %5)
unreachable
}
-declare void @__clang_call_terminate(i8*)
+declare void @__clang_call_terminate(ptr)
declare i32 @__gxx_personality_v0(...)
-declare i8* @__cxa_begin_catch(i8*)
+declare ptr @__cxa_begin_catch(ptr)
declare void @__cxa_end_catch()
diff --git a/llvm/test/CodeGen/ARM/debug-frame-vararg.ll b/llvm/test/CodeGen/ARM/debug-frame-vararg.ll
index c9dcc0b468d92..bd95dc45e9040 100644
--- a/llvm/test/CodeGen/ARM/debug-frame-vararg.ll
+++ b/llvm/test/CodeGen/ARM/debug-frame-vararg.ll
@@ -109,31 +109,29 @@
define i32 @sum(i32 %count, ...) !dbg !4 {
entry:
- %vl = alloca i8*, align 4
- %vl1 = bitcast i8** %vl to i8*
- call void @llvm.va_start(i8* %vl1)
+ %vl = alloca ptr, align 4
+ call void @llvm.va_start(ptr %vl)
%cmp4 = icmp sgt i32 %count, 0
br i1 %cmp4, label %for.body, label %for.end
for.body: ; preds = %entry, %for.body
%i.05 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
- %ap.cur = load i8*, i8** %vl, align 4
- %ap.next = getelementptr i8, i8* %ap.cur, i32 4
- store i8* %ap.next, i8** %vl, align 4
- %0 = bitcast i8* %ap.cur to i32*
- %1 = load i32, i32* %0, align 4
- %call = call i32 @foo(i32 %1) #1
+ %ap.cur = load ptr, ptr %vl, align 4
+ %ap.next = getelementptr i8, ptr %ap.cur, i32 4
+ store ptr %ap.next, ptr %vl, align 4
+ %0 = load i32, ptr %ap.cur, align 4
+ %call = call i32 @foo(i32 %0) #1
%inc = add nsw i32 %i.05, 1
%exitcond = icmp eq i32 %inc, %count
br i1 %exitcond, label %for.end, label %for.body
for.end: ; preds = %for.body, %entry
- call void @llvm.va_end(i8* %vl1)
+ call void @llvm.va_end(ptr %vl)
ret i32 undef
}
-declare void @llvm.va_start(i8*) nounwind
+declare void @llvm.va_start(ptr) nounwind
declare i32 @foo(i32)
-declare void @llvm.va_end(i8*) nounwind
+declare void @llvm.va_end(ptr) nounwind
diff --git a/llvm/test/CodeGen/ARM/debug-frame.ll b/llvm/test/CodeGen/ARM/debug-frame.ll
index b7660443a7d32..faeafdf45dc39 100644
--- a/llvm/test/CodeGen/ARM/debug-frame.ll
+++ b/llvm/test/CodeGen/ARM/debug-frame.ll
@@ -73,16 +73,16 @@ declare void @_Z5printddddd(double, double, double, double, double)
define void @_Z4testiiiiiddddd(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e,
double %m, double %n, double %p,
- double %q, double %r) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+ double %q, double %r) personality ptr @__gxx_personality_v0 {
entry:
invoke void @_Z5printiiiii(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e)
to label %try.cont unwind label %lpad
lpad:
- %0 = landingpad { i8*, i32 }
- catch i8* null
- %1 = extractvalue { i8*, i32 } %0, 0
- %2 = tail call i8* @__cxa_begin_catch(i8* %1)
+ %0 = landingpad { ptr, i32 }
+ catch ptr null
+ %1 = extractvalue { ptr, i32 } %0, 0
+ %2 = tail call ptr @__cxa_begin_catch(ptr %1)
invoke void @_Z5printddddd(double %m, double %n, double %p,
double %q, double %r)
to label %invoke.cont2 unwind label %lpad1
@@ -95,27 +95,27 @@ try.cont:
ret void
lpad1:
- %3 = landingpad { i8*, i32 }
+ %3 = landingpad { ptr, i32 }
cleanup
invoke void @__cxa_end_catch()
to label %eh.resume unwind label %terminate.lpad
eh.resume:
- resume { i8*, i32 } %3
+ resume { ptr, i32 } %3
terminate.lpad:
- %4 = landingpad { i8*, i32 }
- catch i8* null
- %5 = extractvalue { i8*, i32 } %4, 0
- tail call void @__clang_call_terminate(i8* %5)
+ %4 = landingpad { ptr, i32 }
+ catch ptr null
+ %5 = extractvalue { ptr, i32 } %4, 0
+ tail call void @__clang_call_terminate(ptr %5)
unreachable
}
-declare void @__clang_call_terminate(i8*)
+declare void @__clang_call_terminate(ptr)
declare i32 @__gxx_personality_v0(...)
-declare i8* @__cxa_begin_catch(i8*)
+declare ptr @__cxa_begin_catch(ptr)
declare void @__cxa_end_catch()
diff --git a/llvm/test/CodeGen/ARM/debug-info-arg.ll b/llvm/test/CodeGen/ARM/debug-info-arg.ll
index 579d04131782c..bb1127070394f 100644
--- a/llvm/test/CodeGen/ARM/debug-info-arg.ll
+++ b/llvm/test/CodeGen/ARM/debug-info-arg.ll
@@ -6,15 +6,15 @@ target triple = "thumbv7-apple-ios"
%struct.tag_s = type { i32, i32, i32 }
-define void @foo(%struct.tag_s* nocapture %this, %struct.tag_s* %c, i64 %x, i64 %y, %struct.tag_s* nocapture %ptr1, %struct.tag_s* nocapture %ptr2) nounwind ssp "frame-pointer"="all" !dbg !1 {
- tail call void @llvm.dbg.value(metadata %struct.tag_s* %this, metadata !5, metadata !DIExpression()), !dbg !20
- tail call void @llvm.dbg.value(metadata %struct.tag_s* %c, metadata !13, metadata !DIExpression()), !dbg !21
+define void @foo(ptr nocapture %this, ptr %c, i64 %x, i64 %y, ptr nocapture %ptr1, ptr nocapture %ptr2) nounwind ssp "frame-pointer"="all" !dbg !1 {
+ tail call void @llvm.dbg.value(metadata ptr %this, metadata !5, metadata !DIExpression()), !dbg !20
+ tail call void @llvm.dbg.value(metadata ptr %c, metadata !13, metadata !DIExpression()), !dbg !21
tail call void @llvm.dbg.value(metadata i64 %x, metadata !14, metadata !DIExpression()), !dbg !22
tail call void @llvm.dbg.value(metadata i64 %y, metadata !17, metadata !DIExpression()), !dbg !23
;CHECK: @DEBUG_VALUE: foo:y <- [DW_OP_plus_uconst 8] [$r7+0]
- tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr1, metadata !18, metadata !DIExpression()), !dbg !24
- tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr2, metadata !19, metadata !DIExpression()), !dbg !25
- %1 = icmp eq %struct.tag_s* %c, null, !dbg !26
+ tail call void @llvm.dbg.value(metadata ptr %ptr1, metadata !18, metadata !DIExpression()), !dbg !24
+ tail call void @llvm.dbg.value(metadata ptr %ptr2, metadata !19, metadata !DIExpression()), !dbg !25
+ %1 = icmp eq ptr %c, null, !dbg !26
br i1 %1, label %3, label %2, !dbg !26
; <label>:2 ; preds = %0
diff --git a/llvm/test/CodeGen/ARM/debug-info-branch-folding.ll b/llvm/test/CodeGen/ARM/debug-info-branch-folding.ll
index b3aca8c9f6811..ba71fdf54b26b 100644
--- a/llvm/test/CodeGen/ARM/debug-info-branch-folding.ll
+++ b/llvm/test/CodeGen/ARM/debug-info-branch-folding.ll
@@ -14,7 +14,7 @@ target triple = "thumbv7-apple-macosx10.6.7"
declare <4 x float> @test0001(float) nounwind readnone ssp
-define i32 @main(i32 %argc, i8** nocapture %argv, i1 %cond, <4 x float> %x) nounwind ssp !dbg !10 {
+define i32 @main(i32 %argc, ptr nocapture %argv, i1 %cond, <4 x float> %x) nounwind ssp !dbg !10 {
entry:
br label %for.body9
@@ -28,14 +28,14 @@ for.body9: ; preds = %for.body9, %entry
for.end54: ; preds = %for.body9
%tmp115 = extractelement <4 x float> %add19, i32 1
%conv6.i75 = fpext float %tmp115 to double, !dbg !45
- %call.i82 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45
+ %call.i82 = tail call i32 (ptr, ...) @printf(ptr @.str, double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45
%tmp116 = extractelement <4 x float> %add20, i32 1
%conv6.i76 = fpext float %tmp116 to double, !dbg !45
- %call.i83 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i76, double undef, double undef) nounwind, !dbg !45
+ %call.i83 = tail call i32 (ptr, ...) @printf(ptr @.str, double undef, double %conv6.i76, double undef, double undef) nounwind, !dbg !45
ret i32 0, !dbg !49
}
-declare i32 @printf(i8* nocapture, ...) nounwind
+declare i32 @printf(ptr nocapture, ...) nounwind
declare void @llvm.dbg.value(metadata, metadata, metadata) nounwind readnone
diff --git a/llvm/test/CodeGen/ARM/debug-info-no-frame.ll b/llvm/test/CodeGen/ARM/debug-info-no-frame.ll
index dc9ad81e9d55f..a2d669d41c72d 100644
--- a/llvm/test/CodeGen/ARM/debug-info-no-frame.ll
+++ b/llvm/test/CodeGen/ARM/debug-info-no-frame.ll
@@ -7,8 +7,8 @@ define void @need_cfi_def_cfa_offset() #0 !dbg !3 {
; CHECK: .cfi_def_cfa_offset 4
entry:
%Depth = alloca i32, align 4
- call void @llvm.dbg.declare(metadata i32* %Depth, metadata !9, metadata !10), !dbg !11
- store i32 2, i32* %Depth, align 4, !dbg !11
+ call void @llvm.dbg.declare(metadata ptr %Depth, metadata !9, metadata !10), !dbg !11
+ store i32 2, ptr %Depth, align 4, !dbg !11
ret void, !dbg !12
}
diff --git a/llvm/test/CodeGen/ARM/debug-info-qreg.ll b/llvm/test/CodeGen/ARM/debug-info-qreg.ll
index 67628dd2a3a2d..582d811d6fffe 100644
--- a/llvm/test/CodeGen/ARM/debug-info-qreg.ll
+++ b/llvm/test/CodeGen/ARM/debug-info-qreg.ll
@@ -17,7 +17,7 @@ target triple = "thumbv7-apple-macosx10.6.7"
declare <4 x float> @test0001(float) nounwind readnone ssp
-define i32 @main(i32 %argc, i8** nocapture %argv, <4 x float> %x, <4 x float> %y) nounwind ssp !dbg !10 {
+define i32 @main(i32 %argc, ptr nocapture %argv, <4 x float> %x, <4 x float> %y) nounwind ssp !dbg !10 {
entry:
br label %for.body9
@@ -29,11 +29,11 @@ for.end54: ; preds = %for.body9
tail call void @llvm.dbg.value(metadata <4 x float> %add19, metadata !27, metadata !DIExpression()), !dbg !39
%tmp115 = extractelement <4 x float> %add19, i32 1
%conv6.i75 = fpext float %tmp115 to double, !dbg !45
- %call.i82 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45
+ %call.i82 = tail call i32 (ptr, ...) @printf(ptr @.str, double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45
ret i32 0, !dbg !49
}
-declare i32 @printf(i8* nocapture, ...) nounwind
+declare i32 @printf(ptr nocapture, ...) nounwind
declare void @llvm.dbg.value(metadata, metadata, metadata) nounwind readnone
diff --git a/llvm/test/CodeGen/ARM/debug-segmented-stacks.ll b/llvm/test/CodeGen/ARM/debug-segmented-stacks.ll
index 91d583b2b45ff..06050cbe8f841 100644
--- a/llvm/test/CodeGen/ARM/debug-segmented-stacks.ll
+++ b/llvm/test/CodeGen/ARM/debug-segmented-stacks.ll
@@ -7,7 +7,7 @@
define void @test_basic() #0 !dbg !4 {
%mem = alloca i32, i32 10
- call void @dummy_use (i32* %mem, i32 10)
+ call void @dummy_use (ptr %mem, i32 10)
ret void
; ARM-linux: test_basic:
@@ -74,6 +74,6 @@ define void @test_basic() #0 !dbg !4 {
!33 = !DILocation(line: 13, scope: !4)
; Just to prevent the alloca from being optimized away
-declare void @dummy_use(i32*, i32)
+declare void @dummy_use(ptr, i32)
attributes #0 = { "split-stack" }
diff --git a/llvm/test/CodeGen/ARM/default-reloc.ll b/llvm/test/CodeGen/ARM/default-reloc.ll
index 0b80b73061bca..779951c55deeb 100644
--- a/llvm/test/CodeGen/ARM/default-reloc.ll
+++ b/llvm/test/CodeGen/ARM/default-reloc.ll
@@ -1,5 +1,5 @@
; RUN: llc -mtriple=armv7-linux-gnu -O0 < %s
@a = external global i32
-define i32* @get() {
- ret i32* @a
+define ptr @get() {
+ ret ptr @a
}
diff --git a/llvm/test/CodeGen/ARM/demanded-bits-and.ll b/llvm/test/CodeGen/ARM/demanded-bits-and.ll
index 42b6ca5e64479..ddfff681f30f6 100644
--- a/llvm/test/CodeGen/ARM/demanded-bits-and.ll
+++ b/llvm/test/CodeGen/ARM/demanded-bits-and.ll
@@ -4,7 +4,7 @@
; Make sure this doesn't hang, and there are no unnecessary
; "and" instructions.
-define dso_local void @f(i16* %p) {
+define dso_local void @f(ptr %p) {
; CHECK-LABEL: f:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .LBB0_1: @ %bb
@@ -22,7 +22,7 @@ entry:
br label %bb
bb:
- %_p_scalar_ = load i16, i16* %p, align 2
+ %_p_scalar_ = load i16, ptr %p, align 2
%p_and = and i16 %_p_scalar_, 255
%p_ = lshr i16 %_p_scalar_, 8
%p_add = add nuw nsw i16 %p_, 2
@@ -30,6 +30,6 @@ bb:
%p_add18 = add nuw nsw i16 %p_add14, %p_and
%p_add19 = add nuw nsw i16 %p_add18, %p_
%p_200 = lshr i16 %p_add19, 2
- store i16 %p_200, i16* %p, align 2
+ store i16 %p_200, ptr %p, align 2
br label %bb
}
diff --git a/llvm/test/CodeGen/ARM/divmod.ll b/llvm/test/CodeGen/ARM/divmod.ll
index ffc1ed09cbf0c..7011cbf076023 100644
--- a/llvm/test/CodeGen/ARM/divmod.ll
+++ b/llvm/test/CodeGen/ARM/divmod.ll
@@ -4,7 +4,7 @@
; rdar://12481395
-define void @foo(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp {
+define void @foo(i32 %x, i32 %y, ptr nocapture %P) nounwind ssp {
entry:
; A8-LABEL: foo:
; A8: bl ___divmodsi4
@@ -15,14 +15,14 @@ entry:
; SWIFT: mls
; SWIFT-NOT: bl __divmodsi4
%div = sdiv i32 %x, %y
- store i32 %div, i32* %P, align 4
+ store i32 %div, ptr %P, align 4
%rem = srem i32 %x, %y
- %arrayidx6 = getelementptr inbounds i32, i32* %P, i32 1
- store i32 %rem, i32* %arrayidx6, align 4
+ %arrayidx6 = getelementptr inbounds i32, ptr %P, i32 1
+ store i32 %rem, ptr %arrayidx6, align 4
ret void
}
-define void @bar(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp {
+define void @bar(i32 %x, i32 %y, ptr nocapture %P) nounwind ssp {
entry:
; A8-LABEL: bar:
; A8: bl ___udivmodsi4
@@ -33,10 +33,10 @@ entry:
; SWIFT: mls
; SWIFT-NOT: bl __udivmodsi4
%div = udiv i32 %x, %y
- store i32 %div, i32* %P, align 4
+ store i32 %div, ptr %P, align 4
%rem = urem i32 %x, %y
- %arrayidx6 = getelementptr inbounds i32, i32* %P, i32 1
- store i32 %rem, i32* %arrayidx6, align 4
+ %arrayidx6 = getelementptr inbounds i32, ptr %P, i32 1
+ store i32 %rem, ptr %arrayidx6, align 4
ret void
}
@@ -48,7 +48,7 @@ define void @do_indent(i32 %cols) nounwind {
entry:
; A8-LABEL: do_indent:
; SWIFT-LABEL: do_indent:
- %0 = load i32, i32* @flags, align 4
+ %0 = load i32, ptr @flags, align 4
%1 = and i32 %0, 67108864
%2 = icmp eq i32 %1, 0
br i1 %2, label %bb1, label %bb
@@ -58,22 +58,22 @@ bb:
; SWIFT: sdiv
; SWIFT: mls
; SWIFT-NOT: bl __divmodsi4
- %3 = load i32, i32* @tabsize, align 4
+ %3 = load i32, ptr @tabsize, align 4
%4 = srem i32 %cols, %3
%5 = sdiv i32 %cols, %3
- %6 = tail call i32 @llvm.objectsize.i32.p0i8(i8* null, i1 false)
- %7 = tail call i8* @__memset_chk(i8* null, i32 9, i32 %5, i32 %6) nounwind
+ %6 = tail call i32 @llvm.objectsize.i32.p0(ptr null, i1 false)
+ %7 = tail call ptr @__memset_chk(ptr null, i32 9, i32 %5, i32 %6) nounwind
br label %bb1
bb1:
%line_indent_len.0 = phi i32 [ %4, %bb ], [ 0, %entry ]
- %8 = getelementptr inbounds i8, i8* null, i32 %line_indent_len.0
- store i8 0, i8* %8, align 1
+ %8 = getelementptr inbounds i8, ptr null, i32 %line_indent_len.0
+ store i8 0, ptr %8, align 1
ret void
}
-declare i32 @llvm.objectsize.i32.p0i8(i8*, i1) nounwind readnone
-declare i8* @__memset_chk(i8*, i32, i32, i32) nounwind
+declare i32 @llvm.objectsize.i32.p0(ptr, i1) nounwind readnone
+declare ptr @__memset_chk(ptr, i32, i32, i32) nounwind
; rdar://11714607
define i32 @howmany(i32 %x, i32 %y) nounwind {
diff --git a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
index 3925c2704e7b7..c940158437fe4 100644
--- a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
+++ b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
@@ -35,28 +35,28 @@
; DISABLED-NOT: ldr{{.*}}]!
; DISABLED-NOT: str{{.*}}]!
-define void @test_qadd_2(i32* %a.array, i32* %b.array, i32* %out.array, i32 %N) {
+define void @test_qadd_2(ptr %a.array, ptr %b.array, ptr %out.array, i32 %N) {
entry:
br label %loop
loop:
%i = phi i32 [ 0, %entry ], [ %i.next, %loop ]
%idx.1 = phi i32 [ 0, %entry ], [ %idx.next, %loop ]
- %gep.a.1 = getelementptr inbounds i32, i32* %a.array, i32 %idx.1
- %a.1 = load i32, i32* %gep.a.1
- %gep.b.1 = getelementptr inbounds i32, i32* %b.array, i32 %idx.1
- %b.1 = load i32, i32* %gep.b.1
+ %gep.a.1 = getelementptr inbounds i32, ptr %a.array, i32 %idx.1
+ %a.1 = load i32, ptr %gep.a.1
+ %gep.b.1 = getelementptr inbounds i32, ptr %b.array, i32 %idx.1
+ %b.1 = load i32, ptr %gep.b.1
%qadd.1 = call i32 @llvm.arm.qadd(i32 %a.1, i32 %b.1)
- %addr.1 = getelementptr inbounds i32, i32* %out.array, i32 %idx.1
- store i32 %qadd.1, i32* %addr.1
+ %addr.1 = getelementptr inbounds i32, ptr %out.array, i32 %idx.1
+ store i32 %qadd.1, ptr %addr.1
%idx.2 = or i32 %idx.1, 1
- %gep.a.2 = getelementptr inbounds i32, i32* %a.array, i32 %idx.2
- %a.2 = load i32, i32* %gep.a.2
- %gep.b.2 = getelementptr inbounds i32, i32* %b.array, i32 %idx.2
- %b.2 = load i32, i32* %gep.b.2
+ %gep.a.2 = getelementptr inbounds i32, ptr %a.array, i32 %idx.2
+ %a.2 = load i32, ptr %gep.a.2
+ %gep.b.2 = getelementptr inbounds i32, ptr %b.array, i32 %idx.2
+ %b.2 = load i32, ptr %gep.b.2
%qadd.2 = call i32 @llvm.arm.qadd(i32 %a.2, i32 %b.2)
- %addr.2 = getelementptr inbounds i32, i32* %out.array, i32 %idx.2
- store i32 %qadd.2, i32* %addr.2
+ %addr.2 = getelementptr inbounds i32, ptr %out.array, i32 %idx.2
+ store i32 %qadd.2, ptr %addr.2
%i.next = add nsw nuw i32 %i, -2
%idx.next = add nsw nuw i32 %idx.1, 2
%cmp = icmp ult i32 %i.next, %N
@@ -90,28 +90,28 @@ exit:
; DISABLED-NOT: ldr{{.*}}]!
; DISABLED-NOT: str{{.*}}]!
-define void @test_qadd_2_backwards(i32* %a.array, i32* %b.array, i32* %out.array, i32 %N) {
+define void @test_qadd_2_backwards(ptr %a.array, ptr %b.array, ptr %out.array, i32 %N) {
entry:
br label %loop
loop:
%i = phi i32 [ 0, %entry ], [ %i.next, %loop ]
%idx.1 = phi i32 [ %N, %entry ], [ %idx.next, %loop ]
- %gep.a.1 = getelementptr inbounds i32, i32* %a.array, i32 %idx.1
- %a.1 = load i32, i32* %gep.a.1
- %gep.b.1 = getelementptr inbounds i32, i32* %b.array, i32 %idx.1
- %b.1 = load i32, i32* %gep.b.1
+ %gep.a.1 = getelementptr inbounds i32, ptr %a.array, i32 %idx.1
+ %a.1 = load i32, ptr %gep.a.1
+ %gep.b.1 = getelementptr inbounds i32, ptr %b.array, i32 %idx.1
+ %b.1 = load i32, ptr %gep.b.1
%qadd.1 = call i32 @llvm.arm.qadd(i32 %a.1, i32 %b.1)
- %addr.1 = getelementptr inbounds i32, i32* %out.array, i32 %idx.1
- store i32 %qadd.1, i32* %addr.1
+ %addr.1 = getelementptr inbounds i32, ptr %out.array, i32 %idx.1
+ store i32 %qadd.1, ptr %addr.1
%idx.2 = sub nsw nuw i32 %idx.1, 1
- %gep.a.2 = getelementptr inbounds i32, i32* %a.array, i32 %idx.2
- %a.2 = load i32, i32* %gep.a.2
- %gep.b.2 = getelementptr inbounds i32, i32* %b.array, i32 %idx.2
- %b.2 = load i32, i32* %gep.b.2
+ %gep.a.2 = getelementptr inbounds i32, ptr %a.array, i32 %idx.2
+ %a.2 = load i32, ptr %gep.a.2
+ %gep.b.2 = getelementptr inbounds i32, ptr %b.array, i32 %idx.2
+ %b.2 = load i32, ptr %gep.b.2
%qadd.2 = call i32 @llvm.arm.qadd(i32 %a.2, i32 %b.2)
- %addr.2 = getelementptr inbounds i32, i32* %out.array, i32 %idx.2
- store i32 %qadd.2, i32* %addr.2
+ %addr.2 = getelementptr inbounds i32, ptr %out.array, i32 %idx.2
+ store i32 %qadd.2, ptr %addr.2
%i.next = add nsw nuw i32 %i, -2
%idx.next = sub nsw nuw i32 %idx.1, 2
%cmp = icmp ult i32 %i.next, %N
@@ -144,36 +144,36 @@ exit:
; DISABLED-NOT: ldr{{.*}}]!
; DISABLED-NOT: str{{.*}}]!
-define void @test_qadd_3(i32* %a.array, i32* %b.array, i32* %out.array, i32 %N) {
+define void @test_qadd_3(ptr %a.array, ptr %b.array, ptr %out.array, i32 %N) {
entry:
br label %loop
loop:
%i = phi i32 [ 0, %entry ], [ %i.next, %loop ]
%idx.1 = phi i32 [ 0, %entry ], [ %idx.next, %loop ]
- %gep.a.1 = getelementptr inbounds i32, i32* %a.array, i32 %idx.1
- %a.1 = load i32, i32* %gep.a.1
- %gep.b.1 = getelementptr inbounds i32, i32* %b.array, i32 %idx.1
- %b.1 = load i32, i32* %gep.b.1
+ %gep.a.1 = getelementptr inbounds i32, ptr %a.array, i32 %idx.1
+ %a.1 = load i32, ptr %gep.a.1
+ %gep.b.1 = getelementptr inbounds i32, ptr %b.array, i32 %idx.1
+ %b.1 = load i32, ptr %gep.b.1
%qadd.1 = call i32 @llvm.arm.qadd(i32 %a.1, i32 %b.1)
- %addr.1 = getelementptr inbounds i32, i32* %out.array, i32 %idx.1
- store i32 %qadd.1, i32* %addr.1
+ %addr.1 = getelementptr inbounds i32, ptr %out.array, i32 %idx.1
+ store i32 %qadd.1, ptr %addr.1
%idx.2 = add nuw nsw i32 %idx.1, 1
- %gep.a.2 = getelementptr inbounds i32, i32* %a.array, i32 %idx.2
- %a.2 = load i32, i32* %gep.a.2
- %gep.b.2 = getelementptr inbounds i32, i32* %b.array, i32 %idx.2
- %b.2 = load i32, i32* %gep.b.2
+ %gep.a.2 = getelementptr inbounds i32, ptr %a.array, i32 %idx.2
+ %a.2 = load i32, ptr %gep.a.2
+ %gep.b.2 = getelementptr inbounds i32, ptr %b.array, i32 %idx.2
+ %b.2 = load i32, ptr %gep.b.2
%qadd.2 = call i32 @llvm.arm.qadd(i32 %a.2, i32 %b.2)
- %addr.2 = getelementptr inbounds i32, i32* %out.array, i32 %idx.2
- store i32 %qadd.2, i32* %addr.2
+ %addr.2 = getelementptr inbounds i32, ptr %out.array, i32 %idx.2
+ store i32 %qadd.2, ptr %addr.2
%idx.3 = add nuw nsw i32 %idx.1, 2
- %gep.a.3 = getelementptr inbounds i32, i32* %a.array, i32 %idx.3
- %a.3 = load i32, i32* %gep.a.3
- %gep.b.3 = getelementptr inbounds i32, i32* %b.array, i32 %idx.3
- %b.3 = load i32, i32* %gep.b.3
+ %gep.a.3 = getelementptr inbounds i32, ptr %a.array, i32 %idx.3
+ %a.3 = load i32, ptr %gep.a.3
+ %gep.b.3 = getelementptr inbounds i32, ptr %b.array, i32 %idx.3
+ %b.3 = load i32, ptr %gep.b.3
%qadd.3 = call i32 @llvm.arm.qadd(i32 %a.3, i32 %b.3)
- %addr.3 = getelementptr inbounds i32, i32* %out.array, i32 %idx.3
- store i32 %qadd.3, i32* %addr.3
+ %addr.3 = getelementptr inbounds i32, ptr %out.array, i32 %idx.3
+ store i32 %qadd.3, ptr %addr.3
%i.next = add nsw nuw i32 %i, -3
%idx.next = add nsw nuw i32 %idx.1, 3
%cmp = icmp ult i32 %i.next, %N
@@ -214,44 +214,44 @@ exit:
; DISABLED-NOT: ldr{{.*}}]!
; DISABLED-NOT: str{{.*}}]!
-define void @test_qadd_4(i32* %a.array, i32* %b.array, i32* %out.array, i32 %N) {
+define void @test_qadd_4(ptr %a.array, ptr %b.array, ptr %out.array, i32 %N) {
entry:
br label %loop
loop:
%i = phi i32 [ 0, %entry ], [ %i.next, %loop ]
%idx.1 = phi i32 [ 0, %entry ], [ %idx.next, %loop ]
- %gep.a.1 = getelementptr inbounds i32, i32* %a.array, i32 %idx.1
- %a.1 = load i32, i32* %gep.a.1
- %gep.b.1 = getelementptr inbounds i32, i32* %b.array, i32 %idx.1
- %b.1 = load i32, i32* %gep.b.1
+ %gep.a.1 = getelementptr inbounds i32, ptr %a.array, i32 %idx.1
+ %a.1 = load i32, ptr %gep.a.1
+ %gep.b.1 = getelementptr inbounds i32, ptr %b.array, i32 %idx.1
+ %b.1 = load i32, ptr %gep.b.1
%qadd.1 = call i32 @llvm.arm.qadd(i32 %a.1, i32 %b.1)
- %addr.1 = getelementptr inbounds i32, i32* %out.array, i32 %idx.1
- store i32 %qadd.1, i32* %addr.1
+ %addr.1 = getelementptr inbounds i32, ptr %out.array, i32 %idx.1
+ store i32 %qadd.1, ptr %addr.1
%idx.2 = or i32 %idx.1, 1
- %gep.a.2 = getelementptr inbounds i32, i32* %a.array, i32 %idx.2
- %a.2 = load i32, i32* %gep.a.2
- %gep.b.2 = getelementptr inbounds i32, i32* %b.array, i32 %idx.2
- %b.2 = load i32, i32* %gep.b.2
+ %gep.a.2 = getelementptr inbounds i32, ptr %a.array, i32 %idx.2
+ %a.2 = load i32, ptr %gep.a.2
+ %gep.b.2 = getelementptr inbounds i32, ptr %b.array, i32 %idx.2
+ %b.2 = load i32, ptr %gep.b.2
%qadd.2 = call i32 @llvm.arm.qadd(i32 %a.2, i32 %b.2)
- %addr.2 = getelementptr inbounds i32, i32* %out.array, i32 %idx.2
- store i32 %qadd.2, i32* %addr.2
+ %addr.2 = getelementptr inbounds i32, ptr %out.array, i32 %idx.2
+ store i32 %qadd.2, ptr %addr.2
%idx.3 = or i32 %idx.1, 2
- %gep.a.3 = getelementptr inbounds i32, i32* %a.array, i32 %idx.3
- %a.3 = load i32, i32* %gep.a.3
- %gep.b.3 = getelementptr inbounds i32, i32* %b.array, i32 %idx.3
- %b.3 = load i32, i32* %gep.b.3
+ %gep.a.3 = getelementptr inbounds i32, ptr %a.array, i32 %idx.3
+ %a.3 = load i32, ptr %gep.a.3
+ %gep.b.3 = getelementptr inbounds i32, ptr %b.array, i32 %idx.3
+ %b.3 = load i32, ptr %gep.b.3
%qadd.3 = call i32 @llvm.arm.qadd(i32 %a.3, i32 %b.3)
- %addr.3 = getelementptr inbounds i32, i32* %out.array, i32 %idx.3
- store i32 %qadd.3, i32* %addr.3
+ %addr.3 = getelementptr inbounds i32, ptr %out.array, i32 %idx.3
+ store i32 %qadd.3, ptr %addr.3
%idx.4 = or i32 %idx.1, 3
- %gep.a.4 = getelementptr inbounds i32, i32* %a.array, i32 %idx.4
- %a.4 = load i32, i32* %gep.a.4
- %gep.b.4 = getelementptr inbounds i32, i32* %b.array, i32 %idx.4
- %b.4 = load i32, i32* %gep.b.4
+ %gep.a.4 = getelementptr inbounds i32, ptr %a.array, i32 %idx.4
+ %a.4 = load i32, ptr %gep.a.4
+ %gep.b.4 = getelementptr inbounds i32, ptr %b.array, i32 %idx.4
+ %b.4 = load i32, ptr %gep.b.4
%qadd.4 = call i32 @llvm.arm.qadd(i32 %a.4, i32 %b.4)
- %addr.4 = getelementptr inbounds i32, i32* %out.array, i32 %idx.4
- store i32 %qadd.4, i32* %addr.4
+ %addr.4 = getelementptr inbounds i32, ptr %out.array, i32 %idx.4
+ store i32 %qadd.4, ptr %addr.4
%i.next = add nsw nuw i32 %i, -4
%idx.next = add nsw nuw i32 %idx.1, 4
%cmp = icmp ult i32 %i.next, %N
@@ -282,32 +282,28 @@ exit:
; DISABLED-NOT: ldr{{.*}}]!
; DISABLED-NOT: str{{.*}}]!
-define void @test_qadd16_2(i16* %a.array, i16* %b.array, i32* %out.array, i32 %N) {
+define void @test_qadd16_2(ptr %a.array, ptr %b.array, ptr %out.array, i32 %N) {
entry:
br label %loop
loop:
%i = phi i32 [ 0, %entry ], [ %i.next, %loop ]
%idx.1 = phi i32 [ 0, %entry ], [ %idx.next, %loop ]
- %gep.a.1 = getelementptr inbounds i16, i16* %a.array, i32 %idx.1
- %cast.a.1 = bitcast i16* %gep.a.1 to i32*
- %a.1 = load i32, i32* %cast.a.1
- %gep.b.1 = getelementptr inbounds i16, i16* %b.array, i32 %idx.1
- %cast.b.1 = bitcast i16* %gep.b.1 to i32*
- %b.1 = load i32, i32* %cast.b.1
+ %gep.a.1 = getelementptr inbounds i16, ptr %a.array, i32 %idx.1
+ %a.1 = load i32, ptr %gep.a.1
+ %gep.b.1 = getelementptr inbounds i16, ptr %b.array, i32 %idx.1
+ %b.1 = load i32, ptr %gep.b.1
%qadd.1 = call i32 @llvm.arm.qadd16(i32 %a.1, i32 %b.1)
- %addr.1 = getelementptr inbounds i32, i32* %out.array, i32 %idx.1
- store i32 %qadd.1, i32* %addr.1
+ %addr.1 = getelementptr inbounds i32, ptr %out.array, i32 %idx.1
+ store i32 %qadd.1, ptr %addr.1
%idx.2 = add nsw nuw i32 %idx.1, 2
- %gep.a.2 = getelementptr inbounds i16, i16* %a.array, i32 %idx.2
- %cast.a.2 = bitcast i16* %gep.a.2 to i32*
- %a.2 = load i32, i32* %cast.a.2
- %gep.b.2 = getelementptr inbounds i16, i16* %b.array, i32 %idx.2
- %cast.b.2 = bitcast i16* %gep.b.2 to i32*
- %b.2 = load i32, i32* %cast.b.2
+ %gep.a.2 = getelementptr inbounds i16, ptr %a.array, i32 %idx.2
+ %a.2 = load i32, ptr %gep.a.2
+ %gep.b.2 = getelementptr inbounds i16, ptr %b.array, i32 %idx.2
+ %b.2 = load i32, ptr %gep.b.2
%qadd.2 = call i32 @llvm.arm.qadd16(i32 %a.2, i32 %b.2)
- %addr.2 = getelementptr inbounds i32, i32* %out.array, i32 %idx.2
- store i32 %qadd.2, i32* %addr.2
+ %addr.2 = getelementptr inbounds i32, ptr %out.array, i32 %idx.2
+ store i32 %qadd.2, ptr %addr.2
%i.next = add nsw nuw i32 %i, -2
%idx.next = add nsw nuw i32 %idx.1, 4
%cmp = icmp ult i32 %i.next, %N
diff --git a/llvm/test/CodeGen/ARM/dwarf-frame.ll b/llvm/test/CodeGen/ARM/dwarf-frame.ll
index a15c9c50f5a21..cd811373ca273 100644
--- a/llvm/test/CodeGen/ARM/dwarf-frame.ll
+++ b/llvm/test/CodeGen/ARM/dwarf-frame.ll
@@ -1,11 +1,11 @@
; RUN: llc -mtriple armv7-unknown -frame-pointer=all -filetype=asm -o - %s | FileCheck %s --check-prefix=CHECK-NO-CFI
; RUN: llc -mtriple armv7-unknown -frame-pointer=all -filetype=asm -force-dwarf-frame-section -o - %s | FileCheck %s --check-prefix=CHECK-ALWAYS-CFI
-declare void @dummy_use(i32*, i32)
+declare void @dummy_use(ptr, i32)
define void @test_basic() #0 {
%mem = alloca i32, i32 10
- call void @dummy_use (i32* %mem, i32 10)
+ call void @dummy_use (ptr %mem, i32 10)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/dyn-stackalloc.ll b/llvm/test/CodeGen/ARM/dyn-stackalloc.ll
index b653acbd6a7f5..4c63484963722 100644
--- a/llvm/test/CodeGen/ARM/dyn-stackalloc.ll
+++ b/llvm/test/CodeGen/ARM/dyn-stackalloc.ll
@@ -1,12 +1,12 @@
; RUN: llc -mcpu=generic -mtriple=arm-eabi -verify-machineinstrs < %s | FileCheck %s
-%struct.comment = type { i8**, i32*, i32, i8* }
-%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
-%struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* }
+%struct.comment = type { ptr, ptr, i32, ptr }
+%struct.info = type { i32, i32, i32, i32, i32, i32, i32, ptr }
+%struct.state = type { i32, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, ptr }
@str215 = external global [2 x i8]
-define void @t1(%struct.state* %v) {
+define void @t1(ptr %v) {
; Make sure we generate:
; sub sp, sp, r1
@@ -19,50 +19,49 @@ define void @t1(%struct.state* %v) {
; CHECK-NOT: sub r{{[0-9]+}}, sp, [[REG1]]
; CHECK: sub sp, sp, [[REG1]]
- %tmp6 = load i32, i32* null
+ %tmp6 = load i32, ptr null
%tmp8 = alloca float, i32 %tmp6
- store i32 1, i32* null
+ store i32 1, ptr null
br i1 false, label %bb123.preheader, label %return
bb123.preheader: ; preds = %0
br i1 false, label %bb43, label %return
bb43: ; preds = %bb123.preheader
- call fastcc void @f1(float* %tmp8, float* null, i32 0)
- %tmp70 = load i32, i32* null
- %tmp85 = getelementptr float, float* %tmp8, i32 0
- call fastcc void @f2(float* null, float* null, float* %tmp85, i32 %tmp70)
+ call fastcc void @f1(ptr %tmp8, ptr null, i32 0)
+ %tmp70 = load i32, ptr null
+ call fastcc void @f2(ptr null, ptr null, ptr %tmp8, i32 %tmp70)
ret void
return: ; preds = %bb123.preheader, %0
ret void
}
-declare fastcc void @f1(float*, float*, i32)
+declare fastcc void @f1(ptr, ptr, i32)
-declare fastcc void @f2(float*, float*, float*, i32)
+declare fastcc void @f2(ptr, ptr, ptr, i32)
-define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) {
- %tmp1 = call i32 @strlen(i8* %tag)
- %tmp3 = call i32 @strlen(i8* %contents)
+define void @t2(ptr %vc, ptr %tag, ptr %contents) {
+ %tmp1 = call i32 @strlen(ptr %tag)
+ %tmp3 = call i32 @strlen(ptr %contents)
%tmp4 = add i32 %tmp1, 2
%tmp5 = add i32 %tmp4, %tmp3
%tmp6 = alloca i8, i32 %tmp5
- %tmp9 = call i8* @strcpy(i8* %tmp6, i8* %tag)
- %tmp6.len = call i32 @strlen(i8* %tmp6)
- %tmp6.indexed = getelementptr i8, i8* %tmp6, i32 %tmp6.len
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %tmp6.indexed, i8* align 1 getelementptr inbounds ([2 x i8], [2 x i8]* @str215, i32 0, i32 0), i32 2, i1 false)
- %tmp15 = call i8* @strcat(i8* %tmp6, i8* %contents)
- call fastcc void @comment_add(%struct.comment* %vc, i8* %tmp6)
+ %tmp9 = call ptr @strcpy(ptr %tmp6, ptr %tag)
+ %tmp6.len = call i32 @strlen(ptr %tmp6)
+ %tmp6.indexed = getelementptr i8, ptr %tmp6, i32 %tmp6.len
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 %tmp6.indexed, ptr align 1 @str215, i32 2, i1 false)
+ %tmp15 = call ptr @strcat(ptr %tmp6, ptr %contents)
+ call fastcc void @comment_add(ptr %vc, ptr %tmp6)
ret void
}
-declare i32 @strlen(i8*)
+declare i32 @strlen(ptr)
-declare i8* @strcat(i8*, i8*)
+declare ptr @strcat(ptr, ptr)
-declare fastcc void @comment_add(%struct.comment*, i8*)
+declare fastcc void @comment_add(ptr, ptr)
-declare i8* @strcpy(i8*, i8*)
+declare ptr @strcpy(ptr, ptr)
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
diff --git a/llvm/test/CodeGen/ARM/eh-dispcont.ll b/llvm/test/CodeGen/ARM/eh-dispcont.ll
index d6d93818a882e..893007cf2c723 100644
--- a/llvm/test/CodeGen/ARM/eh-dispcont.ll
+++ b/llvm/test/CodeGen/ARM/eh-dispcont.ll
@@ -5,21 +5,20 @@
; RUN: llc -mtriple thumbv6-apple-ios -relocation-model=static -o - %s | FileCheck %s -check-prefix=THUMB1-NOPIC -check-prefix=THUMB1
; RUN: llc -mtriple thumbv6-apple-ios -relocation-model=dynamic-no-pic -o - %s | FileCheck %s -check-prefix=THUMB1-NOPIC -check-prefix=THUMB1
- at _ZTIi = external constant i8*
+ at _ZTIi = external constant ptr
-define i32 @main() #0 personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
+define i32 @main() #0 personality ptr @__gxx_personality_sj0 {
entry:
- %exception = tail call i8* @__cxa_allocate_exception(i32 4) #1
- %0 = bitcast i8* %exception to i32*
- store i32 1, i32* %0, align 4
- invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null) #2
+ %exception = tail call ptr @__cxa_allocate_exception(i32 4) #1
+ store i32 1, ptr %exception, align 4
+ invoke void @__cxa_throw(ptr %exception, ptr @_ZTIi, ptr null) #2
to label %unreachable unwind label %lpad
lpad: ; preds = %entry
- %1 = landingpad { i8*, i32 }
- catch i8* null
- %2 = extractvalue { i8*, i32 } %1, 0
- %3 = tail call i8* @__cxa_begin_catch(i8* %2) #1
+ %0 = landingpad { ptr, i32 }
+ catch ptr null
+ %1 = extractvalue { ptr, i32 } %0, 0
+ %2 = tail call ptr @__cxa_begin_catch(ptr %1) #1
tail call void @__cxa_end_catch()
ret i32 0
@@ -27,11 +26,11 @@ unreachable: ; preds = %entry
unreachable
}
-declare i8* @__cxa_allocate_exception(i32)
+declare ptr @__cxa_allocate_exception(i32)
-declare void @__cxa_throw(i8*, i8*, i8*)
+declare void @__cxa_throw(ptr, ptr, ptr)
-declare i8* @__cxa_begin_catch(i8*)
+declare ptr @__cxa_begin_catch(ptr)
declare void @__cxa_end_catch()
diff --git a/llvm/test/CodeGen/ARM/eh-resume.ll b/llvm/test/CodeGen/ARM/eh-resume.ll
index 12fe2667b8f0c..53f444e7ba6ff 100644
--- a/llvm/test/CodeGen/ARM/eh-resume.ll
+++ b/llvm/test/CodeGen/ARM/eh-resume.ll
@@ -9,7 +9,7 @@ declare void @func()
declare i32 @__gxx_personality_sj0(...)
-define void @test0() personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
+define void @test0() personality ptr @__gxx_personality_sj0 {
entry:
invoke void @func()
to label %cont unwind label %lpad
@@ -18,9 +18,9 @@ cont:
ret void
lpad:
- %exn = landingpad { i8*, i32 }
+ %exn = landingpad { ptr, i32 }
cleanup
- resume { i8*, i32 } %exn
+ resume { ptr, i32 } %exn
}
; IOS: __Unwind_SjLj_Resume
diff --git a/llvm/test/CodeGen/ARM/eh-resume2.ll b/llvm/test/CodeGen/ARM/eh-resume2.ll
index d30b507255c4d..014d285284f9a 100644
--- a/llvm/test/CodeGen/ARM/eh-resume2.ll
+++ b/llvm/test/CodeGen/ARM/eh-resume2.ll
@@ -12,7 +12,7 @@ declare void @func()
declare i32 @__gcc_personality_v0(...)
-define void @test0() personality i8* bitcast (i32 (...)* @__gcc_personality_v0 to i8*) {
+define void @test0() personality ptr @__gcc_personality_v0 {
entry:
invoke void @func()
to label %cont unwind label %lpad
@@ -21,9 +21,9 @@ cont:
ret void
lpad:
- %exn = landingpad { i8*, i32 }
+ %exn = landingpad { ptr, i32 }
cleanup
- resume { i8*, i32 } %exn
+ resume { ptr, i32 } %exn
}
; IOS: __Unwind_SjLj_Resume
diff --git a/llvm/test/CodeGen/ARM/ehabi-filters.ll b/llvm/test/CodeGen/ARM/ehabi-filters.ll
index c2008cef94abf..3a08276c90a97 100644
--- a/llvm/test/CodeGen/ARM/ehabi-filters.ll
+++ b/llvm/test/CodeGen/ARM/ehabi-filters.ll
@@ -2,40 +2,39 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7-none-linux-gnueabi"
- at _ZTIi = external constant i8*
+ at _ZTIi = external constant ptr
declare void @_Z3foov() noreturn;
-declare i8* @__cxa_allocate_exception(i32)
+declare ptr @__cxa_allocate_exception(i32)
declare i32 @__gxx_personality_v0(...)
-declare void @__cxa_throw(i8*, i8*, i8*)
+declare void @__cxa_throw(ptr, ptr, ptr)
-declare void @__cxa_call_unexpected(i8*)
+declare void @__cxa_call_unexpected(ptr)
-define i32 @main() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+define i32 @main() personality ptr @__gxx_personality_v0 {
; CHECK-LABEL: main:
entry:
- %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind
- %0 = bitcast i8* %exception.i to i32*
- store i32 42, i32* %0, align 4
- invoke void @__cxa_throw(i8* %exception.i, i8* bitcast (i8** @_ZTIi to i8*), i8* null) noreturn
+ %exception.i = tail call ptr @__cxa_allocate_exception(i32 4) nounwind
+ store i32 42, ptr %exception.i, align 4
+ invoke void @__cxa_throw(ptr %exception.i, ptr @_ZTIi, ptr null) noreturn
to label %unreachable.i unwind label %lpad.i
lpad.i: ; preds = %entry
- %1 = landingpad { i8*, i32 }
- filter [1 x i8*] [i8* bitcast (i8** @_ZTIi to i8*)]
- catch i8* bitcast (i8** @_ZTIi to i8*)
+ %0 = landingpad { ptr, i32 }
+ filter [1 x ptr] [ptr @_ZTIi]
+ catch ptr @_ZTIi
; CHECK: .long _ZTIi(target2) @ TypeInfo 1
; CHECK: .long _ZTIi(target2) @ FilterInfo -1
- %2 = extractvalue { i8*, i32 } %1, 1
- %ehspec.fails.i = icmp slt i32 %2, 0
+ %1 = extractvalue { ptr, i32 } %0, 1
+ %ehspec.fails.i = icmp slt i32 %1, 0
br i1 %ehspec.fails.i, label %ehspec.unexpected.i, label %lpad.body
ehspec.unexpected.i: ; preds = %lpad.i
- %3 = extractvalue { i8*, i32 } %1, 0
- invoke void @__cxa_call_unexpected(i8* %3) noreturn
+ %2 = extractvalue { ptr, i32 } %0, 0
+ invoke void @__cxa_call_unexpected(ptr %2) noreturn
to label %.noexc unwind label %lpad
.noexc: ; preds = %ehspec.unexpected.i
@@ -45,29 +44,29 @@ unreachable.i: ; preds = %entry
unreachable
lpad: ; preds = %ehspec.unexpected.i
- %4 = landingpad { i8*, i32 }
- catch i8* bitcast (i8** @_ZTIi to i8*)
+ %3 = landingpad { ptr, i32 }
+ catch ptr @_ZTIi
br label %lpad.body
lpad.body: ; preds = %lpad.i, %lpad
- %eh.lpad-body = phi { i8*, i32 } [ %4, %lpad ], [ %1, %lpad.i ]
- %5 = extractvalue { i8*, i32 } %eh.lpad-body, 1
- %6 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) nounwind
- %matches = icmp eq i32 %5, %6
+ %eh.lpad-body = phi { ptr, i32 } [ %3, %lpad ], [ %0, %lpad.i ]
+ %4 = extractvalue { ptr, i32 } %eh.lpad-body, 1
+ %5 = tail call i32 @llvm.eh.typeid.for(ptr @_ZTIi) nounwind
+ %matches = icmp eq i32 %4, %5
br i1 %matches, label %try.cont, label %eh.resume
try.cont: ; preds = %lpad.body
- %7 = extractvalue { i8*, i32 } %eh.lpad-body, 0
- %8 = tail call i8* @__cxa_begin_catch(i8* %7) nounwind
+ %6 = extractvalue { ptr, i32 } %eh.lpad-body, 0
+ %7 = tail call ptr @__cxa_begin_catch(ptr %6) nounwind
tail call void @__cxa_end_catch() nounwind
ret i32 0
eh.resume: ; preds = %lpad.body
- resume { i8*, i32 } %eh.lpad-body
+ resume { ptr, i32 } %eh.lpad-body
}
-declare i32 @llvm.eh.typeid.for(i8*) nounwind readnone
+declare i32 @llvm.eh.typeid.for(ptr) nounwind readnone
-declare i8* @__cxa_begin_catch(i8*)
+declare ptr @__cxa_begin_catch(ptr)
declare void @__cxa_end_catch()
diff --git a/llvm/test/CodeGen/ARM/ehabi-handlerdata-nounwind.ll b/llvm/test/CodeGen/ARM/ehabi-handlerdata-nounwind.ll
index e38c69bc9c735..33f632869b8b7 100644
--- a/llvm/test/CodeGen/ARM/ehabi-handlerdata-nounwind.ll
+++ b/llvm/test/CodeGen/ARM/ehabi-handlerdata-nounwind.ll
@@ -21,19 +21,19 @@ declare void @throw_exception()
declare i32 @__gxx_personality_v0(...)
-declare i8* @__cxa_begin_catch(i8*)
+declare ptr @__cxa_begin_catch(ptr)
declare void @__cxa_end_catch()
-define void @test1() nounwind personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+define void @test1() nounwind personality ptr @__gxx_personality_v0 {
entry:
invoke void @throw_exception() to label %try.cont unwind label %lpad
lpad:
- %0 = landingpad { i8*, i32 }
- catch i8* null
- %1 = extractvalue { i8*, i32 } %0, 0
- %2 = tail call i8* @__cxa_begin_catch(i8* %1)
+ %0 = landingpad { ptr, i32 }
+ catch ptr null
+ %1 = extractvalue { ptr, i32 } %0, 0
+ %2 = tail call ptr @__cxa_begin_catch(ptr %1)
tail call void @__cxa_end_catch()
br label %try.cont
diff --git a/llvm/test/CodeGen/ARM/ehabi-handlerdata.ll b/llvm/test/CodeGen/ARM/ehabi-handlerdata.ll
index 2f4354983cac1..c89eed4a38936 100644
--- a/llvm/test/CodeGen/ARM/ehabi-handlerdata.ll
+++ b/llvm/test/CodeGen/ARM/ehabi-handlerdata.ll
@@ -19,19 +19,19 @@ declare void @throw_exception()
declare i32 @__gxx_personality_v0(...)
-declare i8* @__cxa_begin_catch(i8*)
+declare ptr @__cxa_begin_catch(ptr)
declare void @__cxa_end_catch()
-define void @test1() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+define void @test1() personality ptr @__gxx_personality_v0 {
entry:
invoke void @throw_exception() to label %try.cont unwind label %lpad
lpad:
- %0 = landingpad { i8*, i32 }
- catch i8* null
- %1 = extractvalue { i8*, i32 } %0, 0
- %2 = tail call i8* @__cxa_begin_catch(i8* %1)
+ %0 = landingpad { ptr, i32 }
+ catch ptr null
+ %1 = extractvalue { ptr, i32 } %0, 0
+ %2 = tail call ptr @__cxa_begin_catch(ptr %1)
tail call void @__cxa_end_catch()
br label %try.cont
diff --git a/llvm/test/CodeGen/ARM/ehabi.ll b/llvm/test/CodeGen/ARM/ehabi.ll
index 0b70f243d08d4..fea497076030f 100644
--- a/llvm/test/CodeGen/ARM/ehabi.ll
+++ b/llvm/test/CodeGen/ARM/ehabi.ll
@@ -113,16 +113,16 @@ declare void @_Z5printddddd(double, double, double, double, double)
define void @_Z4testiiiiiddddd(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e,
double %m, double %n, double %p,
- double %q, double %r) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+ double %q, double %r) personality ptr @__gxx_personality_v0 {
entry:
invoke void @_Z5printiiiii(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e)
to label %try.cont unwind label %lpad
lpad:
- %0 = landingpad { i8*, i32 }
- catch i8* null
- %1 = extractvalue { i8*, i32 } %0, 0
- %2 = tail call i8* @__cxa_begin_catch(i8* %1)
+ %0 = landingpad { ptr, i32 }
+ catch ptr null
+ %1 = extractvalue { ptr, i32 } %0, 0
+ %2 = tail call ptr @__cxa_begin_catch(ptr %1)
invoke void @_Z5printddddd(double %m, double %n, double %p,
double %q, double %r)
to label %invoke.cont2 unwind label %lpad1
@@ -135,27 +135,27 @@ try.cont:
ret void
lpad1:
- %3 = landingpad { i8*, i32 }
+ %3 = landingpad { ptr, i32 }
cleanup
invoke void @__cxa_end_catch()
to label %eh.resume unwind label %terminate.lpad
eh.resume:
- resume { i8*, i32 } %3
+ resume { ptr, i32 } %3
terminate.lpad:
- %4 = landingpad { i8*, i32 }
- catch i8* null
- %5 = extractvalue { i8*, i32 } %4, 0
- tail call void @__clang_call_terminate(i8* %5)
+ %4 = landingpad { ptr, i32 }
+ catch ptr null
+ %5 = extractvalue { ptr, i32 } %4, 0
+ tail call void @__clang_call_terminate(ptr %5)
unreachable
}
-declare void @__clang_call_terminate(i8*)
+declare void @__clang_call_terminate(ptr)
declare i32 @__gxx_personality_v0(...)
-declare i8* @__cxa_begin_catch(i8*)
+declare ptr @__cxa_begin_catch(ptr)
declare void @__cxa_end_catch()
diff --git a/llvm/test/CodeGen/ARM/elf-lcomm-align.ll b/llvm/test/CodeGen/ARM/elf-lcomm-align.ll
index a98b3c06f5e29..9ffdb73695754 100644
--- a/llvm/test/CodeGen/ARM/elf-lcomm-align.ll
+++ b/llvm/test/CodeGen/ARM/elf-lcomm-align.ll
@@ -11,5 +11,5 @@
; CHECK-NEXT: .comm x,4,4
define i32 @foo() nounwind {
- ret i32 sub (i32 ptrtoint (i8* @c to i32), i32 ptrtoint (i32* @x to i32))
+ ret i32 sub (i32 ptrtoint (ptr @c to i32), i32 ptrtoint (ptr @x to i32))
}
diff --git a/llvm/test/CodeGen/ARM/emit-big-cst.ll b/llvm/test/CodeGen/ARM/emit-big-cst.ll
index e0c6d4e893e1f..0f451f3450fff 100644
--- a/llvm/test/CodeGen/ARM/emit-big-cst.ll
+++ b/llvm/test/CodeGen/ARM/emit-big-cst.ll
@@ -11,10 +11,9 @@
@bigCst = internal constant i82 483673642326615442599424
-define void @accessBig(i64* %storage) {
- %addr = bitcast i64* %storage to i82*
- %bigLoadedCst = load volatile i82, i82* @bigCst
+define void @accessBig(ptr %storage) {
+ %bigLoadedCst = load volatile i82, ptr @bigCst
%tmp = add i82 %bigLoadedCst, 1
- store i82 %tmp, i82* %addr
+ store i82 %tmp, ptr %storage
ret void
}
diff --git a/llvm/test/CodeGen/ARM/emutls.ll b/llvm/test/CodeGen/ARM/emutls.ll
index 92b656d9ba095..832b9c58edb11 100644
--- a/llvm/test/CodeGen/ARM/emutls.ll
+++ b/llvm/test/CodeGen/ARM/emutls.ll
@@ -6,8 +6,8 @@
; Copied from X86/emutls.ll
; Use my_emutls_get_address like __emutls_get_address.
- at my_emutls_v_xyz = external global i8*, align 4
-declare i8* @my_emutls_get_address(i8*)
+ at my_emutls_v_xyz = external global ptr, align 4
+declare ptr @my_emutls_get_address(ptr)
define i32 @my_get_xyz() {
; ARM32-LABEL: my_get_xyz:
@@ -18,10 +18,9 @@ define i32 @my_get_xyz() {
; ARM32: .long my_emutls_v_xyz(GOT_PREL)
entry:
- %call = call i8* @my_emutls_get_address(i8* bitcast (i8** @my_emutls_v_xyz to i8*))
- %0 = bitcast i8* %call to i32*
- %1 = load i32, i32* %0, align 4
- ret i32 %1
+ %call = call ptr @my_emutls_get_address(ptr @my_emutls_v_xyz)
+ %0 = load i32, ptr %call, align 4
+ ret i32 %0
}
@i1 = thread_local global i32 15
@@ -41,11 +40,11 @@ define i32 @f1() {
; ARM32: .long __emutls_v.i1(GOT_PREL)
entry:
- %tmp1 = load i32, i32* @i1
+ %tmp1 = load i32, ptr @i1
ret i32 %tmp1
}
-define i32* @f2() {
+define ptr @f2() {
; ARM32-LABEL: f2:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
@@ -54,7 +53,7 @@ define i32* @f2() {
; ARM32: .long __emutls_v.i1(GOT_PREL)
entry:
- ret i32* @i1
+ ret ptr @i1
}
define i32 @f3() nounwind {
@@ -66,11 +65,11 @@ define i32 @f3() nounwind {
; ARM32: .long __emutls_v.i2(GOT_PREL)
entry:
- %tmp1 = load i32, i32* @i2
+ %tmp1 = load i32, ptr @i2
ret i32 %tmp1
}
-define i32* @f4() {
+define ptr @f4() {
; ARM32-LABEL: f4:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
@@ -79,7 +78,7 @@ define i32* @f4() {
; ARM32: .long __emutls_v.i2(GOT_PREL)
entry:
- ret i32* @i2
+ ret ptr @i2
}
define i32 @f5() nounwind {
@@ -91,11 +90,11 @@ define i32 @f5() nounwind {
; ARM32: .long __emutls_v.i3-
entry:
- %tmp1 = load i32, i32* @i3
+ %tmp1 = load i32, ptr @i3
ret i32 %tmp1
}
-define i32* @f6() {
+define ptr @f6() {
; ARM32-LABEL: f6:
; ARM32: ldr r0,
; ARM32: add r0, pc, r0
@@ -104,7 +103,7 @@ define i32* @f6() {
; ARM32: .long __emutls_v.i3-
entry:
- ret i32* @i3
+ ret ptr @i3
}
define i32 @f7() {
@@ -116,11 +115,11 @@ define i32 @f7() {
; ARM32: .long __emutls_v.i4-(.LPC
entry:
- %tmp1 = load i32, i32* @i4
+ %tmp1 = load i32, ptr @i4
ret i32 %tmp1
}
-define i32* @f8() {
+define ptr @f8() {
; ARM32-LABEL: f8:
; ARM32: ldr r0,
; ARM32: add r0, pc, r0
@@ -129,7 +128,7 @@ define i32* @f8() {
; ARM32: .long __emutls_v.i4-(.LPC
entry:
- ret i32* @i4
+ ret ptr @i4
}
define i32 @f9() {
@@ -140,11 +139,11 @@ define i32 @f9() {
; ARM32-NEXT: ldr r0, [r0]
entry:
- %tmp1 = load i32, i32* @i5
+ %tmp1 = load i32, ptr @i5
ret i32 %tmp1
}
-define i32* @f10() {
+define ptr @f10() {
; ARM32-LABEL: f10:
; ARM32: ldr r0,
; ARM32: add r0, pc, r0
@@ -152,7 +151,7 @@ define i32* @f10() {
; ARM32-NEXT: pop
entry:
- ret i32* @i5
+ ret ptr @i5
}
define i16 @f11() {
@@ -163,7 +162,7 @@ define i16 @f11() {
; ARM32-NEXT: ldrh r0, [r0]
entry:
- %tmp1 = load i16, i16* @s1
+ %tmp1 = load i16, ptr @s1
ret i16 %tmp1
}
@@ -175,7 +174,7 @@ define i32 @f12() {
; ARM32-NEXT: ldrsh r0, [r0]
entry:
- %tmp1 = load i16, i16* @s1
+ %tmp1 = load i16, ptr @s1
%tmp2 = sext i16 %tmp1 to i32
ret i32 %tmp2
}
@@ -189,7 +188,7 @@ define i8 @f13() {
; ARM32-NEXT: pop
entry:
- %tmp1 = load i8, i8* @b1
+ %tmp1 = load i8, ptr @b1
ret i8 %tmp1
}
@@ -202,7 +201,7 @@ define i32 @f14() {
; ARM32-NEXT: pop
entry:
- %tmp1 = load i8, i8* @b1
+ %tmp1 = load i8, ptr @b1
%tmp2 = sext i8 %tmp1 to i32
ret i32 %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/emutls1.ll b/llvm/test/CodeGen/ARM/emutls1.ll
index 18d32646e15d9..4280a74e26c31 100644
--- a/llvm/test/CodeGen/ARM/emutls1.ll
+++ b/llvm/test/CodeGen/ARM/emutls1.ll
@@ -17,15 +17,15 @@
; PIC-NOT: _aeabi_read_tp
; PIC-NOT: _tls_get_addr
- at i = thread_local global i32 15 ; <i32*> [#uses=2]
+ at i = thread_local global i32 15 ; <ptr> [#uses=2]
define i32 @f() {
entry:
- %tmp1 = load i32, i32* @i ; <i32> [#uses=1]
+ %tmp1 = load i32, ptr @i ; <i32> [#uses=1]
ret i32 %tmp1
}
-define i32* @g() {
+define ptr @g() {
entry:
- ret i32* @i
+ ret ptr @i
}
diff --git a/llvm/test/CodeGen/ARM/emutls_generic.ll b/llvm/test/CodeGen/ARM/emutls_generic.ll
index 8bf0ab3012442..47a4839a35ebc 100644
--- a/llvm/test/CodeGen/ARM/emutls_generic.ll
+++ b/llvm/test/CodeGen/ARM/emutls_generic.ll
@@ -28,19 +28,19 @@
@external_y = thread_local global i8 7, align 2
@internal_y = internal thread_local global i64 9, align 16
-define i32* @get_external_x() {
+define ptr @get_external_x() {
entry:
- ret i32* @external_x
+ ret ptr @external_x
}
-define i8* @get_external_y() {
+define ptr @get_external_y() {
entry:
- ret i8* @external_y
+ ret ptr @external_y
}
-define i64* @get_internal_y() {
+define ptr @get_internal_y() {
entry:
- ret i64* @internal_y
+ ret ptr @internal_y
}
; ARM_32-LABEL: get_external_x:
diff --git a/llvm/test/CodeGen/ARM/execute-only-big-stack-frame.ll b/llvm/test/CodeGen/ARM/execute-only-big-stack-frame.ll
index 5e4e718020e7f..439f1a433346a 100644
--- a/llvm/test/CodeGen/ARM/execute-only-big-stack-frame.ll
+++ b/llvm/test/CodeGen/ARM/execute-only-big-stack-frame.ll
@@ -40,9 +40,9 @@ define i8 @test_big_stack_frame() {
entry:
%s1 = alloca i8
%buffer = alloca [65528 x i8], align 1
- call void @foo(i8* %s1)
- %load = load i8, i8* %s1
+ call void @foo(ptr %s1)
+ %load = load i8, ptr %s1
ret i8 %load
}
-declare void @foo(i8*)
+declare void @foo(ptr)
diff --git a/llvm/test/CodeGen/ARM/execute-only.ll b/llvm/test/CodeGen/ARM/execute-only.ll
index 169f44c7ffa6b..364c539238c8c 100644
--- a/llvm/test/CodeGen/ARM/execute-only.ll
+++ b/llvm/test/CodeGen/ARM/execute-only.ll
@@ -13,7 +13,7 @@ define i32 @global() minsize {
; CHECK: movw [[GLOBDEST:r[0-9]+]], :lower16:var
; CHECK: movt [[GLOBDEST]], :upper16:var
- %val = load i32, i32* @var
+ %val = load i32, ptr @var
ret i32 %val
}
@@ -77,10 +77,10 @@ return: ; preds = %entry, %sw.bb8, %sw
@.str = private unnamed_addr constant [4 x i8] c"FOO\00", align 1
-define hidden i8* @string_literal() {
+define hidden ptr @string_literal() {
entry:
; CHECK-LABEL: string_literal:
; CHECK-NOT: .asciz
; CHECK: .fnend
- ret i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0)
+ ret ptr @.str
}
diff --git a/llvm/test/CodeGen/ARM/expand-pseudos.ll b/llvm/test/CodeGen/ARM/expand-pseudos.ll
index 78c3fe0efbfb7..25538f2c1a83d 100644
--- a/llvm/test/CodeGen/ARM/expand-pseudos.ll
+++ b/llvm/test/CodeGen/ARM/expand-pseudos.ll
@@ -12,20 +12,18 @@ target triple = "thumbv7-unknown-linux-android23"
%"union.v8::internal::Operand::Value" = type { i32, [20 x i8] }
%"class.v8::internal::wasm::LiftoffAssembler" = type {}
-declare void @_ZN2v88internal9Assembler3addENS0_8RegisterES2_RKNS0_7OperandENS0_4SBitENS0_9ConditionE(%"class.v8::internal::Assembler"*, [1 x i32], [1 x i32], %"class.v8::internal::Operand"*, i32, i32)
+declare void @_ZN2v88internal9Assembler3addENS0_8RegisterES2_RKNS0_7OperandENS0_4SBitENS0_9ConditionE(ptr, [1 x i32], [1 x i32], ptr, i32, i32)
; Function Attrs: ssp
-define void @_ZN2v88internal4wasm16LiftoffAssembler13emit_i32_addiENS0_8RegisterES3_i(%"class.v8::internal::wasm::LiftoffAssembler"* %0, [1 x i32] %1, [1 x i32] %2, i32 %3) #0 {
+define void @_ZN2v88internal4wasm16LiftoffAssembler13emit_i32_addiENS0_8RegisterES3_i(ptr %0, [1 x i32] %1, [1 x i32] %2, i32 %3) #0 {
%5 = alloca %"class.v8::internal::Operand", align 8
- %6 = bitcast %"class.v8::internal::wasm::LiftoffAssembler"* %0 to %"class.v8::internal::Assembler"*
- %7 = bitcast %"class.v8::internal::Operand"* %5 to i8*
- %8 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
- %9 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
- %10 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
- %11 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
- %12 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5, i32 0, i32 4, i32 0
- store i32 %3, i32* %12, align 4
- call void @_ZN2v88internal9Assembler3addENS0_8RegisterES2_RKNS0_7OperandENS0_4SBitENS0_9ConditionE(%"class.v8::internal::Assembler"* %6, [1 x i32] %1, [1 x i32] %2, %"class.v8::internal::Operand"* %5, i32 0, i32 2)
+ %6 = getelementptr %"class.v8::internal::Operand", ptr %5
+ %7 = getelementptr %"class.v8::internal::Operand", ptr %5
+ %8 = getelementptr %"class.v8::internal::Operand", ptr %5
+ %9 = getelementptr %"class.v8::internal::Operand", ptr %5
+ %10 = getelementptr %"class.v8::internal::Operand", ptr %5, i32 0, i32 4, i32 0
+ store i32 %3, ptr %10, align 4
+ call void @_ZN2v88internal9Assembler3addENS0_8RegisterES2_RKNS0_7OperandENS0_4SBitENS0_9ConditionE(ptr %0, [1 x i32] %1, [1 x i32] %2, ptr %5, i32 0, i32 2)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/extload-knownzero.ll b/llvm/test/CodeGen/ARM/extload-knownzero.ll
index da340f7a94316..009a47ca513e8 100644
--- a/llvm/test/CodeGen/ARM/extload-knownzero.ll
+++ b/llvm/test/CodeGen/ARM/extload-knownzero.ll
@@ -1,14 +1,14 @@
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
; rdar://12771555
-define void @foo(i16* %ptr, i32 %a) nounwind {
+define void @foo(ptr %ptr, i32 %a) nounwind {
entry:
; CHECK-LABEL: foo:
%tmp1 = icmp ult i32 %a, 100
br i1 %tmp1, label %bb1, label %bb2
bb1:
; CHECK: ldrh
- %tmp2 = load i16, i16* %ptr, align 2
+ %tmp2 = load i16, ptr %ptr, align 2
br label %bb2
bb2:
; CHECK-NOT: uxth
diff --git a/llvm/test/CodeGen/ARM/extloadi1.ll b/llvm/test/CodeGen/ARM/extloadi1.ll
index a67859d60d190..3d4d04f37f6d8 100644
--- a/llvm/test/CodeGen/ARM/extloadi1.ll
+++ b/llvm/test/CodeGen/ARM/extloadi1.ll
@@ -1,10 +1,10 @@
; RUN: llc -mtriple=arm-eabi %s -o /dev/null
- at handler_installed.6144.b = external global i1 ; <i1*> [#uses=1]
+ at handler_installed.6144.b = external global i1 ; <ptr> [#uses=1]
define void @__mf_sigusr1_respond() {
entry:
- %tmp8.b = load i1, i1* @handler_installed.6144.b ; <i1> [#uses=1]
+ %tmp8.b = load i1, ptr @handler_installed.6144.b ; <i1> [#uses=1]
br i1 false, label %cond_true7, label %cond_next
cond_next: ; preds = %entry
diff --git a/llvm/test/CodeGen/ARM/fast-call-frame-restore.ll b/llvm/test/CodeGen/ARM/fast-call-frame-restore.ll
index 5aba7b38ab927..4496af8075b37 100644
--- a/llvm/test/CodeGen/ARM/fast-call-frame-restore.ll
+++ b/llvm/test/CodeGen/ARM/fast-call-frame-restore.ll
@@ -1,6 +1,6 @@
; RUN: llc -mtriple=armv7-linux-gnueabi %s -o - | FileCheck %s
-declare void @bar(i8*, i32, i32, i32, i32)
+declare void @bar(ptr, i32, i32, i32, i32)
define void @foo(i32 %amt) optnone noinline {
br label %next
@@ -10,7 +10,7 @@ next:
br label %next1
next1:
- call void @bar(i8* %mem, i32 undef, i32 undef, i32 undef, i32 undef)
+ call void @bar(ptr %mem, i32 undef, i32 undef, i32 undef, i32 undef)
; CHECK: sub sp, sp, #8
; CHECK: bl bar
; CHECK: add sp, sp, #8
diff --git a/llvm/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll b/llvm/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll
index d759d2d52c368..8a0431677d6d4 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll
@@ -9,49 +9,49 @@
@A = common global [3 x [3 x %struct.A]] zeroinitializer, align 4
@B = common global [2 x [2 x [2 x %struct.B]]] zeroinitializer, align 4
-define i32* @t1() nounwind {
+define ptr @t1() nounwind {
entry:
; ARM: t1
; THUMB: t1
- %addr = alloca i32*, align 4
- store i32* getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]], [2 x [2 x [2 x [2 x [2 x i32]]]]]* @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), i32** %addr, align 4
+ %addr = alloca ptr, align 4
+ store ptr getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]], ptr @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), ptr %addr, align 4
; ARM: add r0, r0, #124
; THUMB: adds r0, #124
- %0 = load i32*, i32** %addr, align 4
- ret i32* %0
+ %0 = load ptr, ptr %addr, align 4
+ ret ptr %0
}
-define i32* @t2() nounwind {
+define ptr @t2() nounwind {
entry:
; ARM: t2
; THUMB: t2
- %addr = alloca i32*, align 4
- store i32* getelementptr inbounds ([3 x [3 x %struct.A]], [3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4
+ %addr = alloca ptr, align 4
+ store ptr getelementptr inbounds ([3 x [3 x %struct.A]], ptr @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), ptr %addr, align 4
; ARM: movw [[R:r[0-9]+]], #1148
; ARM: add r0, r{{[0-9]+}}, [[R]]
; THUMB: addw r0, r0, #1148
- %0 = load i32*, i32** %addr, align 4
- ret i32* %0
+ %0 = load ptr, ptr %addr, align 4
+ ret ptr %0
}
-define i32* @t3() nounwind {
+define ptr @t3() nounwind {
entry:
; ARM: t3
; THUMB: t3
- %addr = alloca i32*, align 4
- store i32* getelementptr inbounds ([3 x [3 x %struct.A]], [3 x [3 x %struct.A]]* @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), i32** %addr, align 4
+ %addr = alloca ptr, align 4
+ store ptr getelementptr inbounds ([3 x [3 x %struct.A]], ptr @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), ptr %addr, align 4
; ARM: add r0, r0, #140
; THUMB: adds r0, #140
- %0 = load i32*, i32** %addr, align 4
- ret i32* %0
+ %0 = load ptr, ptr %addr, align 4
+ ret ptr %0
}
-define i32* @t4() nounwind {
+define ptr @t4() nounwind {
entry:
; ARM: t4
; THUMB: t4
- %addr = alloca i32*, align 4
- store i32* getelementptr inbounds ([2 x [2 x [2 x %struct.B]]], [2 x [2 x [2 x %struct.B]]]* @B, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 3, i32 1, i32 2, i32 1), i32** %addr, align 4
+ %addr = alloca ptr, align 4
+ store ptr getelementptr inbounds ([2 x [2 x [2 x %struct.B]]], ptr @B, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 3, i32 1, i32 2, i32 1), ptr %addr, align 4
; ARM-NOT: movw r{{[0-9]}}, #1060
; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #4
; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #132
@@ -61,6 +61,6 @@ entry:
; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #4
; ARM: movw r{{[0-9]}}, #1284
; THUMB: addw r{{[0-9]}}, r{{[0-9]}}, #1284
- %0 = load i32*, i32** %addr, align 4
- ret i32* %0
+ %0 = load ptr, ptr %addr, align 4
+ ret ptr %0
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-align.ll b/llvm/test/CodeGen/ARM/fast-isel-align.ll
index 9dab0abedb64f..e7741155e6bf1 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-align.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-align.ll
@@ -21,7 +21,7 @@
; Check unaligned stores
%struct.anon = type <{ float }>
- at a = common global %struct.anon* null, align 4
+ at a = common global ptr null, align 4
define void @unaligned_store(float %x, float %y) nounwind {
entry:
@@ -34,9 +34,8 @@ entry:
; THUMB: str [[REG]], [{{r[0-9]+}}]
%add = fadd float %x, %y
- %0 = load %struct.anon*, %struct.anon** @a, align 4
- %x1 = getelementptr inbounds %struct.anon, %struct.anon* %0, i32 0, i32 0
- store float %add, float* %x1, align 1
+ %0 = load ptr, ptr @a, align 4
+ store float %add, ptr %0, align 1
ret void
}
@@ -51,7 +50,7 @@ entry:
; ARM: @word_aligned_f64_store
; THUMB: @word_aligned_f64_store
%add = fadd double %a, %b
- store double %add, double* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @foo_unpacked, i32 0, i32 0), align 4
+ store double %add, ptr @foo_unpacked, align 4
; ARM: vstr d16, [r0]
; THUMB: vstr d16, [r0]
ret void
@@ -60,15 +59,15 @@ entry:
; Check unaligned loads of floats
%class.TAlignTest = type <{ i16, float }>
-define zeroext i1 @unaligned_f32_load(%class.TAlignTest* %this) nounwind align 2 {
+define zeroext i1 @unaligned_f32_load(ptr %this) nounwind align 2 {
entry:
; ARM: @unaligned_f32_load
; THUMB: @unaligned_f32_load
- %0 = alloca %class.TAlignTest*, align 4
- store %class.TAlignTest* %this, %class.TAlignTest** %0, align 4
- %1 = load %class.TAlignTest*, %class.TAlignTest** %0
- %2 = getelementptr inbounds %class.TAlignTest, %class.TAlignTest* %1, i32 0, i32 1
- %3 = load float, float* %2, align 1
+ %0 = alloca ptr, align 4
+ store ptr %this, ptr %0, align 4
+ %1 = load ptr, ptr %0
+ %2 = getelementptr inbounds %class.TAlignTest, ptr %1, i32 0, i32 1
+ %3 = load float, ptr %2, align 1
%4 = fcmp une float %3, 0.000000e+00
; ARM: ldr r[[R:[0-9]+]], [r0, #2]
; ARM: vmov s0, r[[R]]
@@ -79,7 +78,7 @@ entry:
ret i1 %4
}
-define void @unaligned_i16_store(i16 %x, i16* %y) nounwind {
+define void @unaligned_i16_store(i16 %x, ptr %y) nounwind {
entry:
; ARM-STRICT-ALIGN: @unaligned_i16_store
; ARM-STRICT-ALIGN: strb
@@ -89,11 +88,11 @@ entry:
; THUMB-STRICT-ALIGN: strb
; THUMB-STRICT-ALIGN: strb
- store i16 %x, i16* %y, align 1
+ store i16 %x, ptr %y, align 1
ret void
}
-define i16 @unaligned_i16_load(i16* %x) nounwind {
+define i16 @unaligned_i16_load(ptr %x) nounwind {
entry:
; ARM-STRICT-ALIGN: @unaligned_i16_load
; ARM-STRICT-ALIGN: ldrb
@@ -103,11 +102,11 @@ entry:
; THUMB-STRICT-ALIGN: ldrb
; THUMB-STRICT-ALIGN: ldrb
- %0 = load i16, i16* %x, align 1
+ %0 = load i16, ptr %x, align 1
ret i16 %0
}
-define void @unaligned_i32_store(i32 %x, i32* %y) nounwind {
+define void @unaligned_i32_store(i32 %x, ptr %y) nounwind {
entry:
; ARM-STRICT-ALIGN: @unaligned_i32_store
; ARM-STRICT-ALIGN: strb
@@ -121,11 +120,11 @@ entry:
; THUMB-STRICT-ALIGN: strb
; THUMB-STRICT-ALIGN: strb
- store i32 %x, i32* %y, align 1
+ store i32 %x, ptr %y, align 1
ret void
}
-define i32 @unaligned_i32_load(i32* %x) nounwind {
+define i32 @unaligned_i32_load(ptr %x) nounwind {
entry:
; ARM-STRICT-ALIGN: @unaligned_i32_load
; ARM-STRICT-ALIGN: ldrb
@@ -139,6 +138,6 @@ entry:
; THUMB-STRICT-ALIGN: ldrb
; THUMB-STRICT-ALIGN: ldrb
- %0 = load i32, i32* %x, align 1
+ %0 = load i32, ptr %x, align 1
ret i32 %0
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-binary.ll b/llvm/test/CodeGen/ARM/fast-isel-binary.ll
index 3211fd6f24228..169709287cb5a 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-binary.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-binary.ll
@@ -12,7 +12,7 @@ entry:
%0 = add i1 %a, %b
; ARM: add r0, r0, r1
; THUMB: add r0, r1
- store i1 %0, i1* %a.addr, align 4
+ store i1 %0, ptr %a.addr, align 4
ret void
}
@@ -24,7 +24,7 @@ entry:
%0 = add i8 %a, %b
; ARM: add r0, r0, r1
; THUMB: add r0, r1
- store i8 %0, i8* %a.addr, align 4
+ store i8 %0, ptr %a.addr, align 4
ret void
}
@@ -36,7 +36,7 @@ entry:
%0 = add i16 %a, %b
; ARM: add r0, r0, r1
; THUMB: add r0, r1
- store i16 %0, i16* %a.addr, align 4
+ store i16 %0, ptr %a.addr, align 4
ret void
}
@@ -50,7 +50,7 @@ entry:
%0 = or i1 %a, %b
; ARM: orr r0, r0, r1
; THUMB: orrs r0, r1
- store i1 %0, i1* %a.addr, align 4
+ store i1 %0, ptr %a.addr, align 4
ret void
}
@@ -62,7 +62,7 @@ entry:
%0 = or i8 %a, %b
; ARM: orr r0, r0, r1
; THUMB: orrs r0, r1
- store i8 %0, i8* %a.addr, align 4
+ store i8 %0, ptr %a.addr, align 4
ret void
}
@@ -74,7 +74,7 @@ entry:
%0 = or i16 %a, %b
; ARM: orr r0, r0, r1
; THUMB: orrs r0, r1
- store i16 %0, i16* %a.addr, align 4
+ store i16 %0, ptr %a.addr, align 4
ret void
}
@@ -88,7 +88,7 @@ entry:
%0 = sub i1 %a, %b
; ARM: sub r0, r0, r1
; THUMB: subs r0, r0, r1
- store i1 %0, i1* %a.addr, align 4
+ store i1 %0, ptr %a.addr, align 4
ret void
}
@@ -100,7 +100,7 @@ entry:
%0 = sub i8 %a, %b
; ARM: sub r0, r0, r1
; THUMB: subs r0, r0, r1
- store i8 %0, i8* %a.addr, align 4
+ store i8 %0, ptr %a.addr, align 4
ret void
}
@@ -112,6 +112,6 @@ entry:
%0 = sub i16 %a, %b
; ARM: sub r0, r0, r1
; THUMB: subs r0, r0, r1
- store i16 %0, i16* %a.addr, align 4
+ store i16 %0, ptr %a.addr, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-call.ll b/llvm/test/CodeGen/ARM/fast-isel-call.ll
index 1c4ef0d7b1c4f..eaf1850e62042 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-call.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-call.ll
@@ -160,9 +160,9 @@ define void @foo3() uwtable {
; THUMB: {{(movt r[0-9]+, :upper16:_?bar0)|(ldr r[0-9]+, \[r[0-9]+\])}}
; THUMB: movs {{r[0-9]+}}, #0
; THUMB: blx {{r[0-9]+}}
- %fptr = alloca i32 (i32)*, align 8
- store i32 (i32)* @bar0, i32 (i32)** %fptr, align 8
- %1 = load i32 (i32)*, i32 (i32)** %fptr, align 8
+ %fptr = alloca ptr, align 8
+ store ptr @bar0, ptr %fptr, align 8
+ %1 = load ptr, ptr %fptr, align 8
%call = call i32 %1(i32 0)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-conversion.ll b/llvm/test/CodeGen/ARM/fast-isel-conversion.ll
index 46b5e78fb6626..509d7ba7a51f8 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-conversion.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-conversion.ll
@@ -14,7 +14,7 @@ entry:
; THUMB: vcvt.f32.s32 s0, s0
%b.addr = alloca float, align 4
%conv = sitofp i32 %a to float
- store float %conv, float* %b.addr, align 4
+ store float %conv, ptr %b.addr, align 4
ret void
}
@@ -30,7 +30,7 @@ entry:
; THUMB: vcvt.f32.s32 s0, s0
%b.addr = alloca float, align 4
%conv = sitofp i16 %a to float
- store float %conv, float* %b.addr, align 4
+ store float %conv, ptr %b.addr, align 4
ret void
}
@@ -46,7 +46,7 @@ entry:
; THUMB: vcvt.f32.s32 s0, s0
%b.addr = alloca float, align 4
%conv = sitofp i8 %a to float
- store float %conv, float* %b.addr, align 4
+ store float %conv, ptr %b.addr, align 4
ret void
}
@@ -60,7 +60,7 @@ entry:
; THUMB: vcvt.f64.s32 d16, s0
%b.addr = alloca double, align 8
%conv = sitofp i32 %a to double
- store double %conv, double* %b.addr, align 8
+ store double %conv, ptr %b.addr, align 8
ret void
}
@@ -76,7 +76,7 @@ entry:
; THUMB: vcvt.f64.s32 d16, s0
%b.addr = alloca double, align 8
%conv = sitofp i16 %a to double
- store double %conv, double* %b.addr, align 8
+ store double %conv, ptr %b.addr, align 8
ret void
}
@@ -92,7 +92,7 @@ entry:
; THUMB: vcvt.f64.s32 d16, s0
%b.addr = alloca double, align 8
%conv = sitofp i8 %a to double
- store double %conv, double* %b.addr, align 8
+ store double %conv, ptr %b.addr, align 8
ret void
}
@@ -108,7 +108,7 @@ entry:
; THUMB: vcvt.f32.u32 s0, s0
%b.addr = alloca float, align 4
%conv = uitofp i32 %a to float
- store float %conv, float* %b.addr, align 4
+ store float %conv, ptr %b.addr, align 4
ret void
}
@@ -124,7 +124,7 @@ entry:
; THUMB: vcvt.f32.u32 s0, s0
%b.addr = alloca float, align 4
%conv = uitofp i16 %a to float
- store float %conv, float* %b.addr, align 4
+ store float %conv, ptr %b.addr, align 4
ret void
}
@@ -140,7 +140,7 @@ entry:
; THUMB: vcvt.f32.u32 s0, s0
%b.addr = alloca float, align 4
%conv = uitofp i8 %a to float
- store float %conv, float* %b.addr, align 4
+ store float %conv, ptr %b.addr, align 4
ret void
}
@@ -154,7 +154,7 @@ entry:
; THUMB: vcvt.f64.u32 d16, s0
%b.addr = alloca double, align 8
%conv = uitofp i32 %a to double
- store double %conv, double* %b.addr, align 8
+ store double %conv, ptr %b.addr, align 8
ret void
}
@@ -170,7 +170,7 @@ entry:
; THUMB: vcvt.f64.u32 d16, s0
%b.addr = alloca double, align 8
%conv = uitofp i16 %a to double
- store double %conv, double* %b.addr, align 8
+ store double %conv, ptr %b.addr, align 8
ret void
}
@@ -186,7 +186,7 @@ entry:
; THUMB: vcvt.f64.u32 d16, s0
%b.addr = alloca double, align 8
%conv = uitofp i8 %a to double
- store double %conv, double* %b.addr, align 8
+ store double %conv, ptr %b.addr, align 8
ret void
}
@@ -200,7 +200,7 @@ entry:
; THUMB: vcvt.s32.f32 s0, s0
%b.addr = alloca i32, align 4
%conv = fptosi float %a to i32
- store i32 %conv, i32* %b.addr, align 4
+ store i32 %conv, ptr %b.addr, align 4
ret void
}
@@ -212,7 +212,7 @@ entry:
; THUMB: vcvt.s32.f64 s0, d16
%b.addr = alloca i32, align 8
%conv = fptosi double %a to i32
- store i32 %conv, i32* %b.addr, align 8
+ store i32 %conv, ptr %b.addr, align 8
ret void
}
@@ -226,7 +226,7 @@ entry:
; THUMB: vcvt.u32.f32 s0, s0
%b.addr = alloca i32, align 4
%conv = fptoui float %a to i32
- store i32 %conv, i32* %b.addr, align 4
+ store i32 %conv, ptr %b.addr, align 4
ret void
}
@@ -238,6 +238,6 @@ entry:
; THUMB: vcvt.u32.f64 s0, d16
%b.addr = alloca i32, align 8
%conv = fptoui double %a to i32
- store i32 %conv, i32* %b.addr, align 8
+ store i32 %conv, ptr %b.addr, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-crash.ll b/llvm/test/CodeGen/ARM/fast-isel-crash.ll
index 885ca69834d32..66fae55fce3b3 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-crash.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-crash.ll
@@ -5,7 +5,7 @@
@__md0 = external global [137 x i8]
-define internal void @stretch(<4 x i8> addrspace(1)* %src, <4 x i8> addrspace(1)* %dst, i32 %width, i32 %height, i32 %iLS, i32 %oLS, <2 x float> %c, <4 x float> %param) nounwind {
+define internal void @stretch(ptr addrspace(1) %src, ptr addrspace(1) %dst, i32 %width, i32 %height, i32 %iLS, i32 %oLS, <2 x float> %c, <4 x float> %param) nounwind {
entry:
ret void
}
@@ -15,8 +15,8 @@ entry:
ret i32 undef
}
-define void @wrap(i8 addrspace(1)* addrspace(1)* %arglist, i32 addrspace(1)* %gtid) nounwind ssp {
+define void @wrap(ptr addrspace(1) %arglist, ptr addrspace(1) %gtid) nounwind ssp {
entry:
- call void @stretch(<4 x i8> addrspace(1)* undef, <4 x i8> addrspace(1)* undef, i32 undef, i32 undef, i32 undef, i32 undef, <2 x float> undef, <4 x float> undef)
+ call void @stretch(ptr addrspace(1) undef, ptr addrspace(1) undef, i32 undef, i32 undef, i32 undef, i32 undef, <2 x float> undef, <4 x float> undef)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-deadcode.ll b/llvm/test/CodeGen/ARM/fast-isel-deadcode.ll
index d66a81c7cdb21..ae9062c7ba9f2 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-deadcode.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-deadcode.ll
@@ -3,7 +3,7 @@
; Target-specific selector can't properly handle the double because it isn't
; being passed via a register, so the materialized arguments become dead code.
-define i32 @main(i32 %argc, i8** %argv) nounwind {
+define i32 @main(i32 %argc, ptr %argv) nounwind {
entry:
; THUMB: main
call void @printArgsNoRet(i32 1, float 0x4000CCCCC0000000, i8 signext 99, double 4.100000e+00)
diff --git a/llvm/test/CodeGen/ARM/fast-isel-fold.ll b/llvm/test/CodeGen/ARM/fast-isel-fold.ll
index 37e93c0a70188..50f37c13a2068 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-fold.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-fold.ll
@@ -14,7 +14,7 @@ define void @t1() nounwind uwtable ssp {
; THUMB: ldrb
; THUMB-NOT: uxtb
; THUMB-NOT: and{{.*}}, #255
- %1 = load i8, i8* @a, align 1
+ %1 = load i8, ptr @a, align 1
call void @foo1(i8 zeroext %1)
ret void
}
@@ -26,7 +26,7 @@ define void @t2() nounwind uwtable ssp {
; THUMB: t2
; THUMB: ldrh
; THUMB-NOT: uxth
- %1 = load i16, i16* @b, align 2
+ %1 = load i16, ptr @b, align 2
call void @foo2(i16 zeroext %1)
ret void
}
@@ -43,7 +43,7 @@ define i32 @t3() nounwind uwtable ssp {
; THUMB: ldrb
; THUMB-NOT: uxtb
; THUMB-NOT: and{{.*}}, #255
- %1 = load i8, i8* @a, align 1
+ %1 = load i8, ptr @a, align 1
%2 = zext i8 %1 to i32
ret i32 %2
}
@@ -55,7 +55,7 @@ define i32 @t4() nounwind uwtable ssp {
; THUMB: t4
; THUMB: ldrh
; THUMB-NOT: uxth
- %1 = load i16, i16* @b, align 2
+ %1 = load i16, ptr @b, align 2
%2 = zext i16 %1 to i32
ret i32 %2
}
@@ -67,7 +67,7 @@ define i32 @t5() nounwind uwtable ssp {
; THUMB: t5
; THUMB: ldrsh
; THUMB-NOT: sxth
- %1 = load i16, i16* @b, align 2
+ %1 = load i16, ptr @b, align 2
%2 = sext i16 %1 to i32
ret i32 %2
}
@@ -79,7 +79,7 @@ define i32 @t6() nounwind uwtable ssp {
; THUMB: t6
; THUMB: ldrsb
; THUMB-NOT: sxtb
- %1 = load i8, i8* @a, align 2
+ %1 = load i8, ptr @a, align 2
%2 = sext i8 %1 to i32
ret i32 %2
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-frameaddr.ll b/llvm/test/CodeGen/ARM/fast-isel-frameaddr.ll
index ff00cd887fbdd..e29ddd52f3d02 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-frameaddr.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-frameaddr.ll
@@ -3,7 +3,7 @@
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=DARWIN-THUMB2
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=thumbv7-linux-gnueabi | FileCheck %s --check-prefix=LINUX-THUMB2
-define i8* @frameaddr_index0() nounwind {
+define ptr @frameaddr_index0() nounwind {
entry:
; DARWIN-ARM-LABEL: frameaddr_index0:
; DARWIN-ARM: push {r7, lr}
@@ -25,11 +25,11 @@ entry:
; LINUX-THUMB2: mov r7, sp
; LINUX-THUMB2: mov r0, r7
- %0 = call i8* @llvm.frameaddress(i32 0)
- ret i8* %0
+ %0 = call ptr @llvm.frameaddress(i32 0)
+ ret ptr %0
}
-define i8* @frameaddr_index1() nounwind {
+define ptr @frameaddr_index1() nounwind {
entry:
; DARWIN-ARM-LABEL: frameaddr_index1:
; DARWIN-ARM: push {r7, lr}
@@ -52,11 +52,11 @@ entry:
; LINUX-THUMB2: mov r0, r7
; LINUX-THUMB2: ldr r0, [r0]
- %0 = call i8* @llvm.frameaddress(i32 1)
- ret i8* %0
+ %0 = call ptr @llvm.frameaddress(i32 1)
+ ret ptr %0
}
-define i8* @frameaddr_index3() nounwind {
+define ptr @frameaddr_index3() nounwind {
entry:
; DARWIN-ARM-LABEL: frameaddr_index3:
; DARWIN-ARM: push {r7, lr}
@@ -87,8 +87,8 @@ entry:
; LINUX-THUMB2: ldr r0, [r0]
; LINUX-THUMB2: ldr r0, [r0]
- %0 = call i8* @llvm.frameaddress(i32 3)
- ret i8* %0
+ %0 = call ptr @llvm.frameaddress(i32 3)
+ ret ptr %0
}
-declare i8* @llvm.frameaddress(i32) nounwind readnone
+declare ptr @llvm.frameaddress(i32) nounwind readnone
diff --git a/llvm/test/CodeGen/ARM/fast-isel-indirectbr.ll b/llvm/test/CodeGen/ARM/fast-isel-indirectbr.ll
index 91648d36a6946..2569b82ed86a6 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-indirectbr.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-indirectbr.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
-define void @t1(i8* %x) {
+define void @t1(ptr %x) {
entry:
; ARM: t1
; THUMB: t1
@@ -12,7 +12,7 @@ L0:
br label %L1
L1:
- indirectbr i8* %x, [ label %L0, label %L1 ]
+ indirectbr ptr %x, [ label %L0, label %L1 ]
; ARM: bx r0
; THUMB: mov pc, r0
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll b/llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
index 359ff73ef31be..72deb2612d47f 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
@@ -44,11 +44,11 @@ define void @t1() nounwind ssp {
; THUMB-LONG: movt r3, :upper16:L_memset$non_lazy_ptr
; THUMB-LONG: ldr r3, [r3]
; THUMB-LONG: blx r3
- call void @llvm.memset.p0i8.i32(i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @message1, i32 0, i32 5), i8 64, i32 10, i1 false)
+ call void @llvm.memset.p0.i32(ptr align 4 getelementptr inbounds ([60 x i8], ptr @message1, i32 0, i32 5), i8 64, i32 10, i1 false)
ret void
}
-declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) nounwind
+declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) nounwind
define void @t2() nounwind ssp {
; ARM-LABEL: t2:
@@ -89,11 +89,11 @@ define void @t2() nounwind ssp {
; THUMB-LONG: movt r3, :upper16:L_memcpy$non_lazy_ptr
; THUMB-LONG: ldr r3, [r3]
; THUMB-LONG: blx r3
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 17, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 4 getelementptr inbounds ([60 x i8], ptr @temp, i32 0, i32 4), ptr align 4 getelementptr inbounds ([60 x i8], ptr @temp, i32 0, i32 16), i32 17, i1 false)
ret void
}
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
define void @t3() nounwind ssp {
; ARM-LABEL: t3:
@@ -134,7 +134,7 @@ define void @t3() nounwind ssp {
; THUMB-LONG: movt r3, :upper16:L_memmove$non_lazy_ptr
; THUMB-LONG: ldr r3, [r3]
; THUMB-LONG: blx r3
- call void @llvm.memmove.p0i8.p0i8.i32(i8* align 1 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 1 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false)
+ call void @llvm.memmove.p0.p0.i32(ptr align 1 getelementptr inbounds ([60 x i8], ptr @temp, i32 0, i32 4), ptr align 1 getelementptr inbounds ([60 x i8], ptr @temp, i32 0, i32 16), i32 10, i1 false)
ret void
}
@@ -166,11 +166,11 @@ define void @t4() nounwind ssp {
; THUMB: ldrh [[REG4:r[0-9]+]], [[[REG1]], #24]
; THUMB: strh [[REG4]], [[[REG1]], #12]
; THUMB: bx lr
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 4 getelementptr inbounds ([60 x i8], ptr @temp, i32 0, i32 4), ptr align 4 getelementptr inbounds ([60 x i8], ptr @temp, i32 0, i32 16), i32 10, i1 false)
ret void
}
-declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
+declare void @llvm.memmove.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
define void @t5() nounwind ssp {
; ARM-LABEL: t5:
@@ -208,7 +208,7 @@ define void @t5() nounwind ssp {
; THUMB: ldrh [[REG6:r[0-9]+]], [[[REG1]], #24]
; THUMB: strh [[REG6]], [[[REG1]], #12]
; THUMB: bx lr
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 2 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 2 getelementptr inbounds ([60 x i8], ptr @temp, i32 0, i32 4), ptr align 2 getelementptr inbounds ([60 x i8], ptr @temp, i32 0, i32 16), i32 10, i1 false)
ret void
}
@@ -268,14 +268,14 @@ define void @t6() nounwind ssp {
; THUMB: ldrb [[REG11:r[0-9]+]], [[[REG0]], #25]
; THUMB: strb [[REG11]], [[[REG0]], #13]
; THUMB: bx lr
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 1 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 getelementptr inbounds ([60 x i8], ptr @temp, i32 0, i32 4), ptr align 1 getelementptr inbounds ([60 x i8], ptr @temp, i32 0, i32 16), i32 10, i1 false)
ret void
}
; rdar://13202135
define void @t7() nounwind ssp {
; Just make sure this doesn't assert when we have an odd length and an alignment of 2.
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 2 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 3, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 2 getelementptr inbounds ([60 x i8], ptr @temp, i32 0, i32 4), ptr align 2 getelementptr inbounds ([60 x i8], ptr @temp, i32 0, i32 16), i32 3, i1 false)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll b/llvm/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll
index cce914b094f7d..cbe629e3dfd4d 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll
@@ -1,55 +1,55 @@
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM
-define i32 @t1(i32* nocapture %ptr) nounwind readonly {
+define i32 @t1(ptr nocapture %ptr) nounwind readonly {
entry:
; ARM: t1
- %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 1
- %0 = load i32, i32* %add.ptr, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %ptr, i32 1
+ %0 = load i32, ptr %add.ptr, align 4
; ARM: ldr r{{[0-9]}}, [r0, #4]
ret i32 %0
}
-define i32 @t2(i32* nocapture %ptr) nounwind readonly {
+define i32 @t2(ptr nocapture %ptr) nounwind readonly {
entry:
; ARM: t2
- %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 63
- %0 = load i32, i32* %add.ptr, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %ptr, i32 63
+ %0 = load i32, ptr %add.ptr, align 4
; ARM: ldr.w r{{[0-9]}}, [r0, #252]
ret i32 %0
}
-define zeroext i16 @t3(i16* nocapture %ptr) nounwind readonly {
+define zeroext i16 @t3(ptr nocapture %ptr) nounwind readonly {
entry:
; ARM: t3
- %add.ptr = getelementptr inbounds i16, i16* %ptr, i16 1
- %0 = load i16, i16* %add.ptr, align 4
+ %add.ptr = getelementptr inbounds i16, ptr %ptr, i16 1
+ %0 = load i16, ptr %add.ptr, align 4
; ARM: ldrh r{{[0-9]}}, [r0, #2]
ret i16 %0
}
-define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly {
+define zeroext i16 @t4(ptr nocapture %ptr) nounwind readonly {
entry:
; ARM: t4
- %add.ptr = getelementptr inbounds i16, i16* %ptr, i16 63
- %0 = load i16, i16* %add.ptr, align 4
+ %add.ptr = getelementptr inbounds i16, ptr %ptr, i16 63
+ %0 = load i16, ptr %add.ptr, align 4
; ARM: ldrh.w r{{[0-9]}}, [r0, #126]
ret i16 %0
}
-define zeroext i8 @t5(i8* nocapture %ptr) nounwind readonly {
+define zeroext i8 @t5(ptr nocapture %ptr) nounwind readonly {
entry:
; ARM: t5
- %add.ptr = getelementptr inbounds i8, i8* %ptr, i8 1
- %0 = load i8, i8* %add.ptr, align 4
+ %add.ptr = getelementptr inbounds i8, ptr %ptr, i8 1
+ %0 = load i8, ptr %add.ptr, align 4
; ARM: ldrb r{{[0-9]}}, [r0, #1]
ret i8 %0
}
-define zeroext i8 @t6(i8* nocapture %ptr) nounwind readonly {
+define zeroext i8 @t6(ptr nocapture %ptr) nounwind readonly {
entry:
; ARM: t6
- %add.ptr = getelementptr inbounds i8, i8* %ptr, i8 63
- %0 = load i8, i8* %add.ptr, align 4
+ %add.ptr = getelementptr inbounds i8, ptr %ptr, i8 63
+ %0 = load i8, ptr %add.ptr, align 4
; ARM: ldrb.w r{{[0-9]}}, [r0, #63]
ret i8 %0
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll b/llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
index 512796d42b009..bb4db8706a19e 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
@@ -1,111 +1,111 @@
; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
-define i32 @t1(i32* nocapture %ptr) nounwind readonly {
+define i32 @t1(ptr nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t1:
- %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -1
- %0 = load i32, i32* %add.ptr, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %ptr, i32 -1
+ %0 = load i32, ptr %add.ptr, align 4
; THUMB: ldr r{{[0-9]}}, [r0, #-4]
ret i32 %0
}
-define i32 @t2(i32* nocapture %ptr) nounwind readonly {
+define i32 @t2(ptr nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t2:
- %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -63
- %0 = load i32, i32* %add.ptr, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %ptr, i32 -63
+ %0 = load i32, ptr %add.ptr, align 4
; THUMB: ldr r{{[0-9]}}, [r0, #-252]
ret i32 %0
}
-define i32 @t3(i32* nocapture %ptr) nounwind readonly {
+define i32 @t3(ptr nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t3:
- %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -64
- %0 = load i32, i32* %add.ptr, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %ptr, i32 -64
+ %0 = load i32, ptr %add.ptr, align 4
; THUMB: ldr r{{[0-9]}}, [r0]
ret i32 %0
}
-define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly {
+define zeroext i16 @t4(ptr nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t4:
- %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -1
- %0 = load i16, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %ptr, i32 -1
+ %0 = load i16, ptr %add.ptr, align 2
; THUMB: ldrh r{{[0-9]}}, [r0, #-2]
ret i16 %0
}
-define zeroext i16 @t5(i16* nocapture %ptr) nounwind readonly {
+define zeroext i16 @t5(ptr nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t5:
- %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -127
- %0 = load i16, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %ptr, i32 -127
+ %0 = load i16, ptr %add.ptr, align 2
; THUMB: ldrh r{{[0-9]}}, [r0, #-254]
ret i16 %0
}
-define zeroext i16 @t6(i16* nocapture %ptr) nounwind readonly {
+define zeroext i16 @t6(ptr nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t6:
- %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -128
- %0 = load i16, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %ptr, i32 -128
+ %0 = load i16, ptr %add.ptr, align 2
; THUMB: ldrh r{{[0-9]}}, [r0]
ret i16 %0
}
-define zeroext i8 @t7(i8* nocapture %ptr) nounwind readonly {
+define zeroext i8 @t7(ptr nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t7:
- %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -1
- %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %ptr, i32 -1
+ %0 = load i8, ptr %add.ptr, align 1
; THUMB: ldrb r{{[0-9]}}, [r0, #-1]
ret i8 %0
}
-define zeroext i8 @t8(i8* nocapture %ptr) nounwind readonly {
+define zeroext i8 @t8(ptr nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t8:
- %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -255
- %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %ptr, i32 -255
+ %0 = load i8, ptr %add.ptr, align 1
; THUMB: ldrb r{{[0-9]}}, [r0, #-255]
ret i8 %0
}
-define zeroext i8 @t9(i8* nocapture %ptr) nounwind readonly {
+define zeroext i8 @t9(ptr nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t9:
- %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -256
- %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %ptr, i32 -256
+ %0 = load i8, ptr %add.ptr, align 1
; THUMB: ldrb r{{[0-9]}}, [r0]
ret i8 %0
}
-define void @t10(i32* nocapture %ptr) nounwind {
+define void @t10(ptr nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t10:
- %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -1
- store i32 0, i32* %add.ptr, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %ptr, i32 -1
+ store i32 0, ptr %add.ptr, align 4
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: str r{{[0-9]}}, [[[REG]], #-4]
ret void
}
-define void @t11(i32* nocapture %ptr) nounwind {
+define void @t11(ptr nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t11:
- %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -63
- store i32 0, i32* %add.ptr, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %ptr, i32 -63
+ store i32 0, ptr %add.ptr, align 4
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: str r{{[0-9]}}, [[[REG]], #-252]
ret void
}
-define void @t12(i32* nocapture %ptr) nounwind {
+define void @t12(ptr nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t12:
- %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -64
- store i32 0, i32* %add.ptr, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %ptr, i32 -64
+ store i32 0, ptr %add.ptr, align 4
; THUMB: mov [[PTR:r[0-9]+]], r0
; THUMB: movs [[VAL:r[0-9]+]], #0
; THUMB: movw [[REG:r[0-9]+]], #65280
@@ -115,31 +115,31 @@ entry:
ret void
}
-define void @t13(i16* nocapture %ptr) nounwind {
+define void @t13(ptr nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t13:
- %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -1
- store i16 0, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %ptr, i32 -1
+ store i16 0, ptr %add.ptr, align 2
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strh r{{[0-9]}}, [[[REG]], #-2]
ret void
}
-define void @t14(i16* nocapture %ptr) nounwind {
+define void @t14(ptr nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t14:
- %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -127
- store i16 0, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %ptr, i32 -127
+ store i16 0, ptr %add.ptr, align 2
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strh r{{[0-9]}}, [[[REG]], #-254]
ret void
}
-define void @t15(i16* nocapture %ptr) nounwind {
+define void @t15(ptr nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t15:
- %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -128
- store i16 0, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %ptr, i32 -128
+ store i16 0, ptr %add.ptr, align 2
; THUMB: mov [[PTR:r[0-9]+]], r0
; THUMB: movs [[VAL:r[0-9]+]], #0
; THUMB: movw [[REG:r[0-9]+]], #65280
@@ -149,31 +149,31 @@ entry:
ret void
}
-define void @t16(i8* nocapture %ptr) nounwind {
+define void @t16(ptr nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t16:
- %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -1
- store i8 0, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %ptr, i32 -1
+ store i8 0, ptr %add.ptr, align 1
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strb r{{[0-9]}}, [[[REG]], #-1]
ret void
}
-define void @t17(i8* nocapture %ptr) nounwind {
+define void @t17(ptr nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t17:
- %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -255
- store i8 0, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %ptr, i32 -255
+ store i8 0, ptr %add.ptr, align 1
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strb r{{[0-9]}}, [[[REG]], #-255]
ret void
}
-define void @t18(i8* nocapture %ptr) nounwind {
+define void @t18(ptr nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t18:
- %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -256
- store i8 0, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %ptr, i32 -256
+ store i8 0, ptr %add.ptr, align 1
; THUMB: mov [[PTR:r[0-9]+]], r0
; THUMB: movs [[VAL]], #0
; THUMB: movw [[REG:r[0-9]+]], #65280
diff --git a/llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll b/llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
index 9da10ffc4fe13..e701aaf59070e 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
@@ -2,86 +2,86 @@
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
; rdar://10418009
-define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp {
+define zeroext i16 @t1(ptr nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM-LABEL: t1:
- %add.ptr = getelementptr inbounds i16, i16* %a, i64 -8
- %0 = load i16, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %a, i64 -8
+ %0 = load i16, ptr %add.ptr, align 2
; ARM: ldrh r0, [r0, #-16]
ret i16 %0
}
-define zeroext i16 @t2(i16* nocapture %a) nounwind uwtable readonly ssp {
+define zeroext i16 @t2(ptr nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM-LABEL: t2:
- %add.ptr = getelementptr inbounds i16, i16* %a, i64 -16
- %0 = load i16, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %a, i64 -16
+ %0 = load i16, ptr %add.ptr, align 2
; ARM: ldrh r0, [r0, #-32]
ret i16 %0
}
-define zeroext i16 @t3(i16* nocapture %a) nounwind uwtable readonly ssp {
+define zeroext i16 @t3(ptr nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM-LABEL: t3:
- %add.ptr = getelementptr inbounds i16, i16* %a, i64 -127
- %0 = load i16, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %a, i64 -127
+ %0 = load i16, ptr %add.ptr, align 2
; ARM: ldrh r0, [r0, #-254]
ret i16 %0
}
-define zeroext i16 @t4(i16* nocapture %a) nounwind uwtable readonly ssp {
+define zeroext i16 @t4(ptr nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM-LABEL: t4:
- %add.ptr = getelementptr inbounds i16, i16* %a, i64 -128
- %0 = load i16, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %a, i64 -128
+ %0 = load i16, ptr %add.ptr, align 2
; ARM: mvn r{{[1-9]}}, #255
; ARM: add r0, r0, r{{[1-9]}}
; ARM: ldrh r0, [r0]
ret i16 %0
}
-define zeroext i16 @t5(i16* nocapture %a) nounwind uwtable readonly ssp {
+define zeroext i16 @t5(ptr nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM-LABEL: t5:
- %add.ptr = getelementptr inbounds i16, i16* %a, i64 8
- %0 = load i16, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %a, i64 8
+ %0 = load i16, ptr %add.ptr, align 2
; ARM: ldrh r0, [r0, #16]
ret i16 %0
}
-define zeroext i16 @t6(i16* nocapture %a) nounwind uwtable readonly ssp {
+define zeroext i16 @t6(ptr nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM-LABEL: t6:
- %add.ptr = getelementptr inbounds i16, i16* %a, i64 16
- %0 = load i16, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %a, i64 16
+ %0 = load i16, ptr %add.ptr, align 2
; ARM: ldrh r0, [r0, #32]
ret i16 %0
}
-define zeroext i16 @t7(i16* nocapture %a) nounwind uwtable readonly ssp {
+define zeroext i16 @t7(ptr nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM-LABEL: t7:
- %add.ptr = getelementptr inbounds i16, i16* %a, i64 127
- %0 = load i16, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %a, i64 127
+ %0 = load i16, ptr %add.ptr, align 2
; ARM: ldrh r0, [r0, #254]
ret i16 %0
}
-define zeroext i16 @t8(i16* nocapture %a) nounwind uwtable readonly ssp {
+define zeroext i16 @t8(ptr nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM-LABEL: t8:
- %add.ptr = getelementptr inbounds i16, i16* %a, i64 128
- %0 = load i16, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %a, i64 128
+ %0 = load i16, ptr %add.ptr, align 2
; ARM: add r0, r0, #256
; ARM: ldrh r0, [r0]
ret i16 %0
}
-define void @t9(i16* nocapture %a) nounwind uwtable ssp {
+define void @t9(ptr nocapture %a) nounwind uwtable ssp {
entry:
; ARM-LABEL: t9:
- %add.ptr = getelementptr inbounds i16, i16* %a, i64 -8
- store i16 0, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %a, i64 -8
+ store i16 0, ptr %add.ptr, align 2
; ARM: movw [[REG0:r[0-9]+]], #0
; ARM: strh [[REG0]], [{{r[0-9]+}}, #-16]
ret void
@@ -89,11 +89,11 @@ entry:
; mvn r1, #255
; strh r2, [r0, r1]
-define void @t10(i16* nocapture %a) nounwind uwtable ssp {
+define void @t10(ptr nocapture %a) nounwind uwtable ssp {
entry:
; ARM-LABEL: t10:
- %add.ptr = getelementptr inbounds i16, i16* %a, i64 -128
- store i16 0, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %a, i64 -128
+ store i16 0, ptr %add.ptr, align 2
; ARM: mov r1, r0
; ARM: movw [[REG1:r[0-9]+]], #0
; ARM: mvn [[REG2:r[0-9]+]], #255
@@ -102,11 +102,11 @@ entry:
ret void
}
-define void @t11(i16* nocapture %a) nounwind uwtable ssp {
+define void @t11(ptr nocapture %a) nounwind uwtable ssp {
entry:
; ARM-LABEL: t11:
- %add.ptr = getelementptr inbounds i16, i16* %a, i64 8
- store i16 0, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %a, i64 8
+ store i16 0, ptr %add.ptr, align 2
; ARM: movw [[REG1:r[0-9]+]], #0
; ARM: strh [[REG1]], [{{r[0-9]+}}, #16]
ret void
@@ -114,11 +114,11 @@ entry:
; mov r1, #256
; strh r2, [r0, r1]
-define void @t12(i16* nocapture %a) nounwind uwtable ssp {
+define void @t12(ptr nocapture %a) nounwind uwtable ssp {
entry:
; ARM-LABEL: t12:
- %add.ptr = getelementptr inbounds i16, i16* %a, i64 128
- store i16 0, i16* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i16, ptr %a, i64 128
+ store i16 0, ptr %add.ptr, align 2
; ARM: mov r1, r0
; ARM: movw [[REG1:r[0-9]+]], #0
; ARM: add [[REG0:r[0-9]+]], r1, #256
@@ -126,29 +126,29 @@ entry:
ret void
}
-define signext i8 @t13(i8* nocapture %a) nounwind uwtable readonly ssp {
+define signext i8 @t13(ptr nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM-LABEL: t13:
- %add.ptr = getelementptr inbounds i8, i8* %a, i64 -8
- %0 = load i8, i8* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i8, ptr %a, i64 -8
+ %0 = load i8, ptr %add.ptr, align 2
; ARM: ldrsb r0, [r0, #-8]
ret i8 %0
}
-define signext i8 @t14(i8* nocapture %a) nounwind uwtable readonly ssp {
+define signext i8 @t14(ptr nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM-LABEL: t14:
- %add.ptr = getelementptr inbounds i8, i8* %a, i64 -255
- %0 = load i8, i8* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i8, ptr %a, i64 -255
+ %0 = load i8, ptr %add.ptr, align 2
; ARM: ldrsb r0, [r0, #-255]
ret i8 %0
}
-define signext i8 @t15(i8* nocapture %a) nounwind uwtable readonly ssp {
+define signext i8 @t15(ptr nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM-LABEL: t15:
- %add.ptr = getelementptr inbounds i8, i8* %a, i64 -256
- %0 = load i8, i8* %add.ptr, align 2
+ %add.ptr = getelementptr inbounds i8, ptr %a, i64 -256
+ %0 = load i8, ptr %add.ptr, align 2
; ARM: mvn r{{[1-9]}}, #255
; ARM: add r0, r0, r{{[1-9]}}
; ARM: ldrsb r0, [r0]
diff --git a/llvm/test/CodeGen/ARM/fast-isel-load-store-verify.ll b/llvm/test/CodeGen/ARM/fast-isel-load-store-verify.ll
index acf10c8b719e9..82b3db2d4a837 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-load-store-verify.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-load-store-verify.ll
@@ -17,7 +17,7 @@ define i8 @t1() nounwind uwtable ssp {
; ALL: @t1
; ALL: ldrb
; ALL: add
- %1 = load i8, i8* @a, align 1
+ %1 = load i8, ptr @a, align 1
%2 = add nsw i8 %1, 1
ret i8 %2
}
@@ -26,7 +26,7 @@ define i16 @t2() nounwind uwtable ssp {
; ALL: @t2
; ALL: ldrh
; ALL: add
- %1 = load i16, i16* @b, align 2
+ %1 = load i16, ptr @b, align 2
%2 = add nsw i16 %1, 1
ret i16 %2
}
@@ -35,7 +35,7 @@ define i32 @t3() nounwind uwtable ssp {
; ALL: @t3
; ALL: ldr
; ALL: add
- %1 = load i32, i32* @c, align 4
+ %1 = load i32, ptr @c, align 4
%2 = add nsw i32 %1, 1
ret i32 %2
}
@@ -47,7 +47,7 @@ define void @t4(i8 %v) nounwind uwtable ssp {
; ALL: add
; ALL: strb
%1 = add nsw i8 %v, 1
- store i8 %1, i8* @a, align 1
+ store i8 %1, ptr @a, align 1
ret void
}
@@ -56,7 +56,7 @@ define void @t5(i16 %v) nounwind uwtable ssp {
; ALL: add
; ALL: strh
%1 = add nsw i16 %v, 1
- store i16 %1, i16* @b, align 2
+ store i16 %1, ptr @b, align 2
ret void
}
@@ -65,6 +65,6 @@ define void @t6(i32 %v) nounwind uwtable ssp {
; ALL: add
; ALL: str
%1 = add nsw i32 %v, 1
- store i32 %1, i32* @c, align 4
+ store i32 %1, ptr @c, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-pic.ll b/llvm/test/CodeGen/ARM/fast-isel-pic.ll
index 4cee5a7eba90b..c4d460701331d 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-pic.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-pic.ll
@@ -27,7 +27,7 @@ entry:
; ARMv7-ELF: .LPC
; ARMv7-ELF-NEXT: ldr r[[reg2]], [pc, r[[reg2]]]
; ARMv7-ELF: ldr r[[reg2]], [r[[reg2]]]
- %tmp = load i32, i32* @g
+ %tmp = load i32, ptr @g
ret i32 %tmp
}
@@ -57,6 +57,6 @@ entry:
; ARMv7-ELF: .LPC
; ARMv7-ELF: ldr r[[reg6:[0-9]+]], [pc, r[[reg5]]]
; ARMv7-ELF: ldr r0, [r[[reg5]]]
- %tmp = load i32, i32* @i
+ %tmp = load i32, ptr @i
ret i32 %tmp
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-pie.ll b/llvm/test/CodeGen/ARM/fast-isel-pie.ll
index 0d9b4ae198aac..ede867f84c982 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-pie.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-pie.ll
@@ -2,7 +2,7 @@
@var = dso_local global i32 42
-define dso_local i32* @foo() {
+define dso_local ptr @foo() {
; CHECK: foo:
; CHECK: ldr r0, .L[[POOL:.*]]
; CHECK-NEXT: .L[[ADDR:.*]]:
@@ -12,7 +12,7 @@ define dso_local i32* @foo() {
; CHECK: .L[[POOL]]:
; CHECK-NEXT: .long var-(.L[[ADDR]]+8)
- ret i32* @var
+ ret ptr @var
}
!llvm.module.flags = !{!0}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-pred.ll b/llvm/test/CodeGen/ARM/fast-isel-pred.ll
index ae8b67d7157b6..6c7d13c1823e5 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-pred.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-pred.ll
@@ -6,54 +6,52 @@ entry:
%retval = alloca i32, align 4
%X = alloca <4 x i32>, align 16
%Y = alloca <4 x float>, align 16
- store i32 0, i32* %retval
- %tmp = load <4 x i32>, <4 x i32>* %X, align 16
- call void @__aa(<4 x i32> %tmp, i8* null, i32 3, <4 x float>* %Y)
- %0 = load i32, i32* %retval
+ store i32 0, ptr %retval
+ %tmp = load <4 x i32>, ptr %X, align 16
+ call void @__aa(<4 x i32> %tmp, ptr null, i32 3, ptr %Y)
+ %0 = load i32, ptr %retval
ret i32 %0
}
-define internal void @__aa(<4 x i32> %v, i8* %p, i32 %offset, <4 x float>* %constants) nounwind inlinehint ssp {
+define internal void @__aa(<4 x i32> %v, ptr %p, i32 %offset, ptr %constants) nounwind inlinehint ssp {
entry:
%__a.addr.i = alloca <4 x i32>, align 16
%v.addr = alloca <4 x i32>, align 16
- %p.addr = alloca i8*, align 4
+ %p.addr = alloca ptr, align 4
%offset.addr = alloca i32, align 4
- %constants.addr = alloca <4 x float>*, align 4
- store <4 x i32> %v, <4 x i32>* %v.addr, align 16
- store i8* %p, i8** %p.addr, align 4
- store i32 %offset, i32* %offset.addr, align 4
- store <4 x float>* %constants, <4 x float>** %constants.addr, align 4
- %tmp = load <4 x i32>, <4 x i32>* %v.addr, align 16
- store <4 x i32> %tmp, <4 x i32>* %__a.addr.i, align 16
- %tmp.i = load <4 x i32>, <4 x i32>* %__a.addr.i, align 16
+ %constants.addr = alloca ptr, align 4
+ store <4 x i32> %v, ptr %v.addr, align 16
+ store ptr %p, ptr %p.addr, align 4
+ store i32 %offset, ptr %offset.addr, align 4
+ store ptr %constants, ptr %constants.addr, align 4
+ %tmp = load <4 x i32>, ptr %v.addr, align 16
+ store <4 x i32> %tmp, ptr %__a.addr.i, align 16
+ %tmp.i = load <4 x i32>, ptr %__a.addr.i, align 16
%0 = bitcast <4 x i32> %tmp.i to <16 x i8>
%1 = bitcast <16 x i8> %0 to <4 x i32>
%vcvt.i = sitofp <4 x i32> %1 to <4 x float>
- %tmp1 = load i8*, i8** %p.addr, align 4
- %tmp2 = load i32, i32* %offset.addr, align 4
- %tmp3 = load <4 x float>*, <4 x float>** %constants.addr, align 4
- call void @__bb(<4 x float> %vcvt.i, i8* %tmp1, i32 %tmp2, <4 x float>* %tmp3)
+ %tmp1 = load ptr, ptr %p.addr, align 4
+ %tmp2 = load i32, ptr %offset.addr, align 4
+ %tmp3 = load ptr, ptr %constants.addr, align 4
+ call void @__bb(<4 x float> %vcvt.i, ptr %tmp1, i32 %tmp2, ptr %tmp3)
ret void
}
-define internal void @__bb(<4 x float> %v, i8* %p, i32 %offset, <4 x float>* %constants) nounwind inlinehint ssp {
+define internal void @__bb(<4 x float> %v, ptr %p, i32 %offset, ptr %constants) nounwind inlinehint ssp {
entry:
%v.addr = alloca <4 x float>, align 16
- %p.addr = alloca i8*, align 4
+ %p.addr = alloca ptr, align 4
%offset.addr = alloca i32, align 4
- %constants.addr = alloca <4 x float>*, align 4
+ %constants.addr = alloca ptr, align 4
%data = alloca i64, align 4
- store <4 x float> %v, <4 x float>* %v.addr, align 16
- store i8* %p, i8** %p.addr, align 4
- store i32 %offset, i32* %offset.addr, align 4
- store <4 x float>* %constants, <4 x float>** %constants.addr, align 4
- %tmp = load i64, i64* %data, align 4
- %tmp1 = load i8*, i8** %p.addr, align 4
- %tmp2 = load i32, i32* %offset.addr, align 4
- %add.ptr = getelementptr i8, i8* %tmp1, i32 %tmp2
- %0 = bitcast i8* %add.ptr to i64*
- %arrayidx = getelementptr inbounds i64, i64* %0, i32 0
- store i64 %tmp, i64* %arrayidx
+ store <4 x float> %v, ptr %v.addr, align 16
+ store ptr %p, ptr %p.addr, align 4
+ store i32 %offset, ptr %offset.addr, align 4
+ store ptr %constants, ptr %constants.addr, align 4
+ %tmp = load i64, ptr %data, align 4
+ %tmp1 = load ptr, ptr %p.addr, align 4
+ %tmp2 = load i32, ptr %offset.addr, align 4
+ %add.ptr = getelementptr i8, ptr %tmp1, i32 %tmp2
+ store i64 %tmp, ptr %add.ptr
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-redefinition.ll b/llvm/test/CodeGen/ARM/fast-isel-redefinition.ll
index a1c8657cb8117..2abf3c7a5885f 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-redefinition.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-redefinition.ll
@@ -4,8 +4,8 @@
target triple = "thumbv7-apple-macosx10.6.7"
-define i32 @f(i32* %x) nounwind ssp {
- %y = getelementptr inbounds i32, i32* %x, i32 5000
- %tmp103 = load i32, i32* %y, align 4
+define i32 @f(ptr %x) nounwind ssp {
+ %y = getelementptr inbounds i32, ptr %x, i32 5000
+ %tmp103 = load i32, ptr %y, align 4
ret i32 %tmp103
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-remat-same-constant.ll b/llvm/test/CodeGen/ARM/fast-isel-remat-same-constant.ll
index d64cf8022ed4f..de591ef06d10d 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-remat-same-constant.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-remat-same-constant.ll
@@ -16,12 +16,12 @@ target triple = "thumbv7-apple-ios8.0.0"
@tr4x4 = external global %struct.RD_8x8DATA, align 4
; Function Attrs: noreturn
-declare void @foo(i16*, i16*) #0
+declare void @foo(ptr, ptr) #0
; Function Attrs: minsize
define i32 @test() #1 {
bb:
- call void @foo(i16* getelementptr inbounds (%struct.RD_8x8DATA, %struct.RD_8x8DATA* @tr8x8, i32 0, i32 10, i32 0, i32 0), i16* getelementptr inbounds (%struct.RD_8x8DATA, %struct.RD_8x8DATA* @tr4x4, i32 0, i32 10, i32 0, i32 0))
+ call void @foo(ptr getelementptr inbounds (%struct.RD_8x8DATA, ptr @tr8x8, i32 0, i32 10, i32 0, i32 0), ptr getelementptr inbounds (%struct.RD_8x8DATA, ptr @tr4x4, i32 0, i32 10, i32 0, i32 0))
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-static.ll b/llvm/test/CodeGen/ARM/fast-isel-static.ll
index 200387cf8926f..6c607269d3a33 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-static.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-static.ll
@@ -3,30 +3,30 @@
; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s
-define void @myadd(float* %sum, float* %addend) nounwind {
+define void @myadd(ptr %sum, ptr %addend) nounwind {
entry:
- %sum.addr = alloca float*, align 4
- %addend.addr = alloca float*, align 4
- store float* %sum, float** %sum.addr, align 4
- store float* %addend, float** %addend.addr, align 4
- %tmp = load float*, float** %sum.addr, align 4
- %tmp1 = load float, float* %tmp
- %tmp2 = load float*, float** %addend.addr, align 4
- %tmp3 = load float, float* %tmp2
+ %sum.addr = alloca ptr, align 4
+ %addend.addr = alloca ptr, align 4
+ store ptr %sum, ptr %sum.addr, align 4
+ store ptr %addend, ptr %addend.addr, align 4
+ %tmp = load ptr, ptr %sum.addr, align 4
+ %tmp1 = load float, ptr %tmp
+ %tmp2 = load ptr, ptr %addend.addr, align 4
+ %tmp3 = load float, ptr %tmp2
%add = fadd float %tmp1, %tmp3
- %tmp4 = load float*, float** %sum.addr, align 4
- store float %add, float* %tmp4
+ %tmp4 = load ptr, ptr %sum.addr, align 4
+ store float %add, ptr %tmp4
ret void
}
-define i32 @main(i32 %argc, i8** %argv) nounwind {
+define i32 @main(i32 %argc, ptr %argv) nounwind {
entry:
%ztot = alloca float, align 4
%z = alloca float, align 4
- store float 0.000000e+00, float* %ztot, align 4
- store float 1.000000e+00, float* %z, align 4
+ store float 0.000000e+00, ptr %ztot, align 4
+ store float 1.000000e+00, ptr %z, align 4
; CHECK-LONG: blx r
; CHECK-NORM: bl {{_?}}myadd
- call void @myadd(float* %ztot, float* %z)
+ call void @myadd(ptr %ztot, ptr %z)
ret i32 0
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-update-valuemap-for-extract.ll b/llvm/test/CodeGen/ARM/fast-isel-update-valuemap-for-extract.ll
index 18d60fee189f9..82a04063ae3cb 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-update-valuemap-for-extract.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-update-valuemap-for-extract.ll
@@ -11,14 +11,13 @@ target triple = "thumbv7-apple-ios8.0.0"
%struct.node = type opaque
-declare void @foo([4 x i32], %struct.node*)
+declare void @foo([4 x i32], ptr)
-define void @test([4 x i32] %xpic.coerce, %struct.node* %t) {
+define void @test([4 x i32] %xpic.coerce, ptr %t) {
bb:
%tmp29 = extractvalue [4 x i32] %xpic.coerce, 0
- %tmp40 = bitcast %struct.node* %t to [8 x %struct.node*]*
- %tmp41 = getelementptr inbounds [8 x %struct.node*], [8 x %struct.node*]* %tmp40, i32 0, i32 %tmp29
- %tmp42 = load %struct.node*, %struct.node** %tmp41, align 4
- call void @foo([4 x i32] %xpic.coerce, %struct.node* %tmp42)
+ %tmp41 = getelementptr inbounds [8 x ptr], ptr %t, i32 0, i32 %tmp29
+ %tmp42 = load ptr, ptr %tmp41, align 4
+ call void @foo([4 x i32] %xpic.coerce, ptr %tmp42)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-vaddd.ll b/llvm/test/CodeGen/ARM/fast-isel-vaddd.ll
index 2aa269a9774dc..a75134d287720 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-vaddd.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-vaddd.ll
@@ -11,23 +11,22 @@ target triple = "thumbv7s-apple-ios8.0.0"
; CHECK: vadd.f64
; CHECK: vadd.f64
-define i32 @main(i32 %argc, i8** nocapture readnone %Argv, <2 x double> %tmp31) {
+define i32 @main(i32 %argc, ptr nocapture readnone %Argv, <2 x double> %tmp31) {
bb:
%Ad = alloca %union.DV, align 16
- %tmp32 = getelementptr inbounds %union.DV, %union.DV* %Ad, i32 0, i32 0
%tmp33 = fadd <2 x double> %tmp31, %tmp31
br label %bb37
bb37: ; preds = %bb37, %bb
%i.02 = phi i32 [ 0, %bb ], [ %tmp38, %bb37 ]
- store <2 x double> %tmp33, <2 x double>* %tmp32, align 16
+ store <2 x double> %tmp33, ptr %Ad, align 16
%tmp38 = add nuw nsw i32 %i.02, 1
%exitcond = icmp eq i32 %tmp38, 500000
br i1 %exitcond, label %bb39, label %bb37
bb39: ; preds = %bb37
- call fastcc void @printDV(%union.DV* %Ad)
+ call fastcc void @printDV(ptr %Ad)
ret i32 0
}
-declare hidden fastcc void @printDV(%union.DV* nocapture readonly)
+declare hidden fastcc void @printDV(ptr nocapture readonly)
diff --git a/llvm/test/CodeGen/ARM/fast-isel-vararg.ll b/llvm/test/CodeGen/ARM/fast-isel-vararg.ll
index 078bd466e1905..5cbdc7fb8faee 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-vararg.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-vararg.ll
@@ -10,11 +10,11 @@ entry:
%m = alloca i32, align 4
%n = alloca i32, align 4
%tmp = alloca i32, align 4
- %0 = load i32, i32* %i, align 4
- %1 = load i32, i32* %j, align 4
- %2 = load i32, i32* %k, align 4
- %3 = load i32, i32* %m, align 4
- %4 = load i32, i32* %n, align 4
+ %0 = load i32, ptr %i, align 4
+ %1 = load i32, ptr %j, align 4
+ %2 = load i32, ptr %k, align 4
+ %3 = load i32, ptr %m, align 4
+ %4 = load i32, ptr %n, align 4
; ARM: VarArg
; ARM: mov [[FP:r[0-9]+]], sp
; ARM: sub sp, sp, #32
@@ -37,8 +37,8 @@ entry:
; THUMB: str.w [[Rb]], [sp, #4]
; THUMB: bl {{_?}}CallVariadic
%call = call i32 (i32, ...) @CallVariadic(i32 5, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4)
- store i32 %call, i32* %tmp, align 4
- %5 = load i32, i32* %tmp, align 4
+ store i32 %call, ptr %tmp, align 4
+ %5 = load i32, ptr %tmp, align 4
ret i32 %5
}
diff --git a/llvm/test/CodeGen/ARM/fast-isel.ll b/llvm/test/CodeGen/ARM/fast-isel.ll
index ebb9d0e9103fb..2cc458ea9bb66 100644
--- a/llvm/test/CodeGen/ARM/fast-isel.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel.ll
@@ -7,10 +7,10 @@ define i32 @test0(i32 %a, i32 %b) nounwind {
entry:
%a.addr = alloca i32, align 4
%b.addr = alloca i32, align 4
- store i32 %a, i32* %a.addr
- store i32 %b, i32* %b.addr
- %tmp = load i32, i32* %a.addr
- %tmp1 = load i32, i32* %b.addr
+ store i32 %a, ptr %a.addr
+ store i32 %b, ptr %b.addr
+ %tmp = load i32, ptr %a.addr
+ %tmp1 = load i32, ptr %b.addr
%add = add nsw i32 %tmp, %tmp1
ret i32 %add
}
@@ -34,13 +34,13 @@ ret void
}
; Check some simple operations with immediates
-define void @test2(i32 %tmp, i32* %ptr) nounwind {
+define void @test2(i32 %tmp, ptr %ptr) nounwind {
; THUMB-LABEL: test2:
; ARM-LABEL: test2:
b1:
%a = add i32 %tmp, 4096
- store i32 %a, i32* %ptr
+ store i32 %a, ptr %ptr
br label %b2
; THUMB: add.w {{.*}} #4096
@@ -48,7 +48,7 @@ b1:
b2:
%b = add i32 %tmp, 4095
- store i32 %b, i32* %ptr
+ store i32 %b, ptr %ptr
br label %b3
; THUMB: addw {{.*}} #4095
; ARM: movw {{.*}} #4095
@@ -56,14 +56,14 @@ b2:
b3:
%c = or i32 %tmp, 4
- store i32 %c, i32* %ptr
+ store i32 %c, ptr %ptr
ret void
; THUMB: orr {{.*}} #4
; ARM: orr {{.*}} #4
}
-define void @test3(i32 %tmp, i32* %ptr1, i16* %ptr2, i8* %ptr3) nounwind {
+define void @test3(i32 %tmp, ptr %ptr1, ptr %ptr2, ptr %ptr3) nounwind {
; THUMB-LABEL: test3:
; ARM-LABEL: test3:
@@ -72,11 +72,11 @@ bb1:
%a2 = trunc i16 %a1 to i8
%a3 = trunc i8 %a2 to i1
%a4 = zext i1 %a3 to i8
- store i8 %a4, i8* %ptr3
+ store i8 %a4, ptr %ptr3
%a5 = zext i8 %a4 to i16
- store i16 %a5, i16* %ptr2
+ store i16 %a5, ptr %ptr2
%a6 = zext i16 %a5 to i32
- store i32 %a6, i32* %ptr1
+ store i32 %a6, ptr %ptr1
br label %bb2
; THUMB: and
@@ -93,11 +93,11 @@ bb1:
bb2:
%b1 = trunc i32 %tmp to i16
%b2 = trunc i16 %b1 to i8
- store i8 %b2, i8* %ptr3
+ store i8 %b2, ptr %ptr3
%b3 = sext i8 %b2 to i16
- store i16 %b3, i16* %ptr2
+ store i16 %b3, ptr %ptr2
%b4 = sext i16 %b3 to i32
- store i32 %b4, i32* %ptr1
+ store i32 %b4, ptr %ptr1
br label %bb3
; THUMB: strb
@@ -110,14 +110,14 @@ bb2:
; ARM: sxth
bb3:
- %c1 = load i8, i8* %ptr3
- %c2 = load i16, i16* %ptr2
- %c3 = load i32, i32* %ptr1
+ %c1 = load i8, ptr %ptr3
+ %c2 = load i16, ptr %ptr2
+ %c3 = load i32, ptr %ptr1
%c4 = zext i8 %c1 to i32
%c5 = sext i16 %c2 to i32
%c6 = add i32 %c4, %c5
%c7 = sub i32 %c3, %c6
- store i32 %c7, i32* %ptr1
+ store i32 %c7, ptr %ptr1
ret void
; THUMB: ldrb
@@ -138,9 +138,9 @@ bb3:
@test4g = external global i32
define void @test4() {
- %a = load i32, i32* @test4g
+ %a = load i32, ptr @test4g
%b = add i32 %a, 1
- store i32 %b, i32* @test4g
+ store i32 %b, ptr @test4g
ret void
diff --git a/llvm/test/CodeGen/ARM/fast-tail-call.ll b/llvm/test/CodeGen/ARM/fast-tail-call.ll
index c93028bad50cb..2a1a410d04157 100644
--- a/llvm/test/CodeGen/ARM/fast-tail-call.ll
+++ b/llvm/test/CodeGen/ARM/fast-tail-call.ll
@@ -5,12 +5,12 @@
; which led (via a convoluted route) to DAG nodes after a TC_RETURN that
; couldn't possibly work.
-declare i8* @g(i8*)
+declare ptr @g(ptr)
-define i8* @f(i8* %a) {
+define ptr @f(ptr %a) {
entry:
- %0 = tail call i8* @g(i8* %a)
- ret i8* %0
+ %0 = tail call ptr @g(ptr %a)
+ ret ptr %0
; CHECK: b g
; CHECK-NOT: ldr
; CHECK-NOT: str
diff --git a/llvm/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll b/llvm/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll
index 232ab50c3ee55..07edb698801bd 100644
--- a/llvm/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll
+++ b/llvm/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll
@@ -2,17 +2,17 @@
; sext(a) + sext(b) != sext(a + b)
; RUN: llc -mtriple=armv7-apple-ios %s -O0 -o - | FileCheck %s
-define zeroext i8 @gep_promotion(i8* %ptr) nounwind uwtable ssp {
+define zeroext i8 @gep_promotion(ptr %ptr) nounwind uwtable ssp {
entry:
- %ptr.addr = alloca i8*, align 8
+ %ptr.addr = alloca ptr, align 8
%add = add i8 64, 64 ; 0x40 + 0x40
- %0 = load i8*, i8** %ptr.addr, align 8
+ %0 = load ptr, ptr %ptr.addr, align 8
; CHECK-LABEL: _gep_promotion:
; CHECK: ldrb {{r[0-9]+}}, {{\[r[0-9]+\]}}
- %arrayidx = getelementptr inbounds i8, i8* %0, i8 %add
+ %arrayidx = getelementptr inbounds i8, ptr %0, i8 %add
- %1 = load i8, i8* %arrayidx, align 1
+ %1 = load i8, ptr %arrayidx, align 1
ret i8 %1
}
diff --git a/llvm/test/CodeGen/ARM/flag-crash.ll b/llvm/test/CodeGen/ARM/flag-crash.ll
index 66eb8a51c18a2..83a6b2470c51a 100644
--- a/llvm/test/CodeGen/ARM/flag-crash.ll
+++ b/llvm/test/CodeGen/ARM/flag-crash.ll
@@ -3,25 +3,24 @@
%struct.gs_matrix = type { float, i32, float, i32, float, i32, float, i32, float, i32, float, i32 }
-define fastcc void @func(%struct.gs_matrix* nocapture %pm1) nounwind {
+define fastcc void @func(ptr nocapture %pm1) nounwind {
entry:
- %0 = getelementptr inbounds %struct.gs_matrix, %struct.gs_matrix* %pm1, i32 0, i32 6
- %1 = load float, float* %0, align 4
- %2 = getelementptr inbounds %struct.gs_matrix, %struct.gs_matrix* %pm1, i32 0, i32 8
- %3 = load float, float* %2, align 4
- %4 = getelementptr inbounds %struct.gs_matrix, %struct.gs_matrix* %pm1, i32 0, i32 2
- %5 = bitcast float* %4 to i32*
- %6 = load i32, i32* %5, align 4
- %7 = or i32 0, %6
- %.mask = and i32 %7, 2147483647
- %8 = icmp eq i32 %.mask, 0
- br i1 %8, label %bb, label %bb11
+ %0 = getelementptr inbounds %struct.gs_matrix, ptr %pm1, i32 0, i32 6
+ %1 = load float, ptr %0, align 4
+ %2 = getelementptr inbounds %struct.gs_matrix, ptr %pm1, i32 0, i32 8
+ %3 = load float, ptr %2, align 4
+ %4 = getelementptr inbounds %struct.gs_matrix, ptr %pm1, i32 0, i32 2
+ %5 = load i32, ptr %4, align 4
+ %6 = or i32 0, %5
+ %.mask = and i32 %6, 2147483647
+ %7 = icmp eq i32 %.mask, 0
+ br i1 %7, label %bb, label %bb11
bb:
ret void
bb11:
- %9 = fmul float %1, undef
- %10 = fmul float %3, undef
+ %8 = fmul float %1, undef
+ %9 = fmul float %3, undef
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fmacs.ll b/llvm/test/CodeGen/ARM/fmacs.ll
index 140ab933d0cde..005caf654c085 100644
--- a/llvm/test/CodeGen/ARM/fmacs.ll
+++ b/llvm/test/CodeGen/ARM/fmacs.ll
@@ -72,7 +72,7 @@ entry:
; It's possible to make use of fp vmla / vmls on Cortex-A9.
; rdar://8659675
-define void @t4(float %acc1, float %a, float %b, float %acc2, float %c, float* %P1, float* %P2) {
+define void @t4(float %acc1, float %a, float %b, float %acc2, float %c, ptr %P1, ptr %P2) {
entry:
; A8-LABEL: t4:
; A8: vmul.f32
@@ -92,8 +92,8 @@ entry:
%1 = fadd float %acc1, %0
%2 = fmul float %a, %c
%3 = fadd float %acc2, %2
- store float %1, float* %P1
- store float %3, float* %P2
+ store float %1, ptr %P1
+ store float %3, ptr %P2
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fnegs.ll b/llvm/test/CodeGen/ARM/fnegs.ll
index 875fc00f5dddc..435a600822e4d 100644
--- a/llvm/test/CodeGen/ARM/fnegs.ll
+++ b/llvm/test/CodeGen/ARM/fnegs.ll
@@ -19,9 +19,9 @@
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - \
; RUN: | FileCheck %s -check-prefix=CORTEXA9
-define float @test1(float* %a) {
+define float @test1(ptr %a) {
entry:
- %0 = load float, float* %a, align 4 ; <float> [#uses=2]
+ %0 = load float, ptr %a, align 4 ; <float> [#uses=2]
%1 = fsub float -0.000000e+00, %0 ; <float> [#uses=2]
%2 = fpext float %1 to double ; <double> [#uses=1]
%3 = fcmp olt double %2, 1.234000e+00 ; <i1> [#uses=1]
@@ -46,9 +46,9 @@ entry:
; CORTEXA9-LABEL: test1:
; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}}
-define float @test2(float* %a) {
+define float @test2(ptr %a) {
entry:
- %0 = load float, float* %a, align 4 ; <float> [#uses=2]
+ %0 = load float, ptr %a, align 4 ; <float> [#uses=2]
%1 = fneg float %0 ; <float> [#uses=2]
%2 = fpext float %1 to double ; <double> [#uses=1]
%3 = fcmp olt double %2, 1.234000e+00 ; <i1> [#uses=1]
diff --git a/llvm/test/CodeGen/ARM/fold-sext-sextload.ll b/llvm/test/CodeGen/ARM/fold-sext-sextload.ll
index 0d6ecfc2b2128..2141c127039b2 100644
--- a/llvm/test/CodeGen/ARM/fold-sext-sextload.ll
+++ b/llvm/test/CodeGen/ARM/fold-sext-sextload.ll
@@ -1,7 +1,7 @@
; RUN: llc -debugify-and-strip-all-safe=0 -mtriple armv7 %s -stop-before=livedebugvalues -o - | FileCheck %s
-define <4 x i8> @i(<4 x i8>*, <4 x i8>) !dbg !8 {
- %3 = load <4 x i8>, <4 x i8>* %0, align 4, !dbg !14
+define <4 x i8> @i(ptr, <4 x i8>) !dbg !8 {
+ %3 = load <4 x i8>, ptr %0, align 4, !dbg !14
; CHECK: $[[reg:.*]] = VLD1LNd32 {{.*}} debug-location !14 :: (load (s32) from %ir.0)
; CHECK: VMOVLsv8i16 {{.*}} $[[reg]], {{.*}} debug-location !14
; CHECK: VMOVLsv4i32 {{.*}} $[[reg]], {{.*}} debug-location !14
diff --git a/llvm/test/CodeGen/ARM/fold-stack-adjust.ll b/llvm/test/CodeGen/ARM/fold-stack-adjust.ll
index e22aa882404bd..2a5666801f706 100644
--- a/llvm/test/CodeGen/ARM/fold-stack-adjust.ll
+++ b/llvm/test/CodeGen/ARM/fold-stack-adjust.ll
@@ -6,7 +6,7 @@
; RUN: llc -mtriple=thumbv7-apple-darwin-ios -frame-pointer=all < %s -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK-FNSTART,CHECK-IOS
; RUN: llc -mtriple=thumbv7--linux-gnueabi -frame-pointer=all < %s -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK-FNSTART,CHECK-LINUX
-declare void @bar(i8*)
+declare void @bar(ptr)
%bigVec = type [2 x double]
@@ -38,7 +38,7 @@ define void @check_simple() minsize {
; CHECK-IOS: pop {r0, r1, r2, r3, r7, pc}
%var = alloca i8, i32 16
- call void @bar(i8* %var)
+ call void @bar(ptr %var)
ret void
}
@@ -51,7 +51,7 @@ define i32 @check_simple_ret() minsize {
; CHECK: pop {r2, r3, r7, pc}
%var = alloca i8, i32 8
- call void @bar(i8* %var)
+ call void @bar(ptr %var)
ret i32 0
}
@@ -63,7 +63,7 @@ define void @check_simple_too_big() minsize {
; CHECK: add sp,
; CHECK: pop {r7, pc}
%var = alloca i8, i32 64
- call void @bar(i8* %var)
+ call void @bar(ptr %var)
ret void
}
@@ -93,8 +93,8 @@ define void @check_vfp_fold() minsize {
%var = alloca i8, i32 16
- call void asm "", "r,~{d8},~{d9}"(i8* %var)
- call void @bar(i8* %var)
+ call void asm "", "r,~{d8},~{d9}"(ptr %var)
+ call void @bar(ptr %var)
ret void
}
@@ -110,7 +110,7 @@ define i64 @check_no_return_clobber() minsize {
; CHECK: pop {r7, pc}
%var = alloca i8, i32 20
- call void @bar(i8* %var)
+ call void @bar(ptr %var)
ret i64 0
}
@@ -126,9 +126,9 @@ define arm_aapcs_vfpcc double @check_vfp_no_return_clobber() minsize {
%var = alloca i8, i32 64
- %tmp = load %bigVec, %bigVec* @var
- call void @bar(i8* %var)
- store %bigVec %tmp, %bigVec* @var
+ %tmp = load %bigVec, ptr @var
+ call void @bar(ptr %var)
+ store %bigVec %tmp, ptr @var
ret double 1.0
}
@@ -158,11 +158,11 @@ define void @test_fold_point(i1 %tst) minsize {
; We want a long-lived floating register so that a callee-saved dN is used and
; there's both a vpop and a pop.
- %live_val = load double, double* @dbl
+ %live_val = load double, ptr @dbl
br i1 %tst, label %true, label %end
true:
- call void @bar(i8* %var)
- store double %live_val, double* @dbl
+ call void @bar(ptr %var)
+ store double %live_val, ptr @dbl
br label %end
end:
; We want the epilogue to be the only thing in a basic block so that we hit
@@ -188,20 +188,20 @@ define void @test_varsize(...) minsize {
; CHECK: bx lr
%var = alloca i8, i32 8
- call void @llvm.va_start(i8* %var)
- call void @bar(i8* %var)
+ call void @llvm.va_start(ptr %var)
+ call void @bar(ptr %var)
ret void
}
-%"MyClass" = type { i8*, i32, i32, float, float, float, [2 x i8], i32, i32* }
+%"MyClass" = type { ptr, i32, i32, float, float, float, [2 x i8], i32, ptr }
declare float @foo()
declare void @bar3()
-declare %"MyClass"* @bar2(%"MyClass"* returned, i16*, i32, float, float, i32, i32, i1 zeroext, i1 zeroext, i32)
+declare ptr @bar2(ptr returned, ptr, i32, float, float, i32, i32, i1 zeroext, i1 zeroext, i32)
-define fastcc float @check_vfp_no_return_clobber2(i16* %r, i16* %chars, i32 %length, i1 zeroext %flag) minsize {
+define fastcc float @check_vfp_no_return_clobber2(ptr %r, ptr %chars, i32 %length, i1 zeroext %flag) minsize {
entry:
; CHECK-FNSTART-LABEL: check_vfp_no_return_clobber2
; CHECK-LINUX: vpush {d0, d1, d2, d3, d4, d5, d6, d7, d8}
@@ -210,9 +210,9 @@ entry:
; CHECK-LINUX: add sp
; CHECK-LINUX: vpop {d8}
%run = alloca %"MyClass", align 4
- %call = call %"MyClass"* @bar2(%"MyClass"* %run, i16* %chars, i32 %length, float 0.000000e+00, float 0.000000e+00, i32 1, i32 1, i1 zeroext false, i1 zeroext true, i32 3)
+ %call = call ptr @bar2(ptr %run, ptr %chars, i32 %length, float 0.000000e+00, float 0.000000e+00, i32 1, i32 1, i1 zeroext false, i1 zeroext true, i32 3)
%call1 = call float @foo()
- %cmp = icmp eq %"MyClass"* %run, null
+ %cmp = icmp eq ptr %run, null
br i1 %cmp, label %exit, label %if.then
if.then: ; preds = %entry
@@ -223,7 +223,7 @@ exit: ; preds = %if.then, %entry
ret float %call1
}
-declare void @use_arr(i32*)
+declare void @use_arr(ptr)
define void @test_fold_reuse() minsize {
; CHECK-FNSTART-LABEL: test_fold_reuse:
; CHECK: push.w {r4, r7, r8, lr}
@@ -233,7 +233,7 @@ define void @test_fold_reuse() minsize {
; CHECK: pop.w {r4, r7, r8, pc}
%arr = alloca i8, i32 24
call void asm sideeffect "", "~{r8},~{r4}"()
- call void @bar(i8* %arr)
+ call void @bar(ptr %arr)
ret void
}
@@ -245,8 +245,8 @@ define void @test_long_fn() minsize nounwind optsize {
; CHECK-T1-NOFP: pop {r3, pc}
entry:
%z = alloca i32, align 4
- call void asm sideeffect ".space 3000", "r"(i32* nonnull %z)
+ call void asm sideeffect ".space 3000", "r"(ptr nonnull %z)
ret void
}
-declare void @llvm.va_start(i8*) nounwind
+declare void @llvm.va_start(ptr) nounwind
diff --git a/llvm/test/CodeGen/ARM/fold-zext-zextload.ll b/llvm/test/CodeGen/ARM/fold-zext-zextload.ll
index b9b08e4d6c527..be160dc791cd9 100644
--- a/llvm/test/CodeGen/ARM/fold-zext-zextload.ll
+++ b/llvm/test/CodeGen/ARM/fold-zext-zextload.ll
@@ -1,7 +1,7 @@
; RUN: llc -debugify-and-strip-all-safe=0 -mtriple armv7 %s -stop-before=livedebugvalues -o - | FileCheck %s
-define <4 x i8> @i(<4 x i8>*, <4 x i8>) !dbg !8 {
- %3 = load <4 x i8>, <4 x i8>* %0, align 4, !dbg !14
+define <4 x i8> @i(ptr, <4 x i8>) !dbg !8 {
+ %3 = load <4 x i8>, ptr %0, align 4, !dbg !14
; CHECK: $[[reg:.*]] = VLD1LNd32 {{.*}} debug-location !14 :: (load (s32) from %ir.0)
; CHECK-NEXT: VMOVLuv8i16 {{.*}} $[[reg]], {{.*}} debug-location !14
; CHECK-NEXT: VMOVLuv4i32 {{.*}} $[[reg]], {{.*}} debug-location !14
diff --git a/llvm/test/CodeGen/ARM/fp-intrinsics.ll b/llvm/test/CodeGen/ARM/fp-intrinsics.ll
index 5b81982f652ba..64b22a5cc71bc 100644
--- a/llvm/test/CodeGen/ARM/fp-intrinsics.ll
+++ b/llvm/test/CodeGen/ARM/fp-intrinsics.ll
@@ -77,13 +77,13 @@ define i32 @fptosi_f32(float %x) #0 {
; CHECK-NOSP: bl __aeabi_f2iz
; CHECK-SP: vcvt.s32.f32
; FIXME-CHECK-SP: vcvt.s32.f32
-define void @fptosi_f32_twice(float %arg, i32* %ptr) #0 {
+define void @fptosi_f32_twice(float %arg, ptr %ptr) #0 {
entry:
%conv = call i32 @llvm.experimental.constrained.fptosi.f32(float %arg, metadata !"fpexcept.strict") #0
- store i32 %conv, i32* %ptr, align 4
+ store i32 %conv, ptr %ptr, align 4
%conv1 = call i32 @llvm.experimental.constrained.fptosi.f32(float %arg, metadata !"fpexcept.strict") #0
- %idx = getelementptr inbounds i32, i32* %ptr, i32 1
- store i32 %conv1, i32* %idx, align 4
+ %idx = getelementptr inbounds i32, ptr %ptr, i32 1
+ store i32 %conv1, ptr %idx, align 4
ret void
}
@@ -100,13 +100,13 @@ define i32 @fptoui_f32(float %x) #0 {
; CHECK-NOSP: bl __aeabi_f2uiz
; FIXME-CHECK-SP: vcvt.u32.f32
; FIXME-CHECK-SP: vcvt.u32.f32
-define void @fptoui_f32_twice(float %arg, i32* %ptr) #0 {
+define void @fptoui_f32_twice(float %arg, ptr %ptr) #0 {
entry:
%conv = call i32 @llvm.experimental.constrained.fptoui.f32(float %arg, metadata !"fpexcept.strict") #0
- store i32 %conv, i32* %ptr, align 4
+ store i32 %conv, ptr %ptr, align 4
%conv1 = call i32 @llvm.experimental.constrained.fptoui.f32(float %arg, metadata !"fpexcept.strict") #0
- %idx = getelementptr inbounds i32, i32* %ptr, i32 1
- store i32 %conv1, i32* %idx, align 4
+ %idx = getelementptr inbounds i32, ptr %ptr, i32 1
+ store i32 %conv1, ptr %idx, align 4
ret void
}
@@ -982,13 +982,13 @@ define double @fpext_f32(float %x) #0 {
; CHECK-NODP: bl __aeabi_f2d
; CHECK-DP: vcvt.f64.f32
; FIXME-CHECK-DP: vcvt.f64.f32
-define void @fpext_f32_twice(float %arg, double* %ptr) #0 {
+define void @fpext_f32_twice(float %arg, ptr %ptr) #0 {
entry:
%conv1 = call double @llvm.experimental.constrained.fpext.f64.f32(float %arg, metadata !"fpexcept.strict") #0
- store double %conv1, double* %ptr, align 8
+ store double %conv1, ptr %ptr, align 8
%conv2 = call double @llvm.experimental.constrained.fpext.f64.f32(float %arg, metadata !"fpexcept.strict") #0
- %idx = getelementptr inbounds double, double* %ptr, i32 1
- store double %conv2, double* %idx, align 8
+ %idx = getelementptr inbounds double, ptr %ptr, i32 1
+ store double %conv2, ptr %idx, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fp-only-sp.ll b/llvm/test/CodeGen/ARM/fp-only-sp.ll
index ebfa41a8294de..4309271bc5dd8 100644
--- a/llvm/test/CodeGen/ARM/fp-only-sp.ll
+++ b/llvm/test/CodeGen/ARM/fp-only-sp.ll
@@ -2,61 +2,61 @@
; RUN: llc -mtriple=thumbv7em-apple-macho -mcpu=cortex-m4 %s -o - | FileCheck %s
; Note: vldr and vstr really do have 64-bit variants even with -fp64
-define void @test_load_store(double* %addr) {
+define void @test_load_store(ptr %addr) {
; CHECK-LABEL: test_load_store:
; CHECK: vldr [[TMP:d[0-9]+]], [r0]
; CHECK: vstr [[TMP]], [r0]
- %val = load volatile double, double* %addr
- store volatile double %val, double* %addr
+ %val = load volatile double, ptr %addr
+ store volatile double %val, ptr %addr
ret void
}
-define void @test_cmp(double %l, double %r, i1* %addr.dst) {
+define void @test_cmp(double %l, double %r, ptr %addr.dst) {
; CHECK-LABEL: test_cmp:
; CHECK: bl ___eqdf2
%res = fcmp oeq double %l, %r
- store i1 %res, i1* %addr.dst
+ store i1 %res, ptr %addr.dst
ret void
}
-define void @test_ext(float %in, double* %addr) {
+define void @test_ext(float %in, ptr %addr) {
; CHECK-LABEL: test_ext:
; CHECK: bl ___extendsfdf2
%res = fpext float %in to double
- store double %res, double* %addr
+ store double %res, ptr %addr
ret void
}
-define void @test_trunc(double %in, float* %addr) {
+define void @test_trunc(double %in, ptr %addr) {
; CHECK-LABEL: test_trunc:
; CHECK: bl ___truncdfsf2
%res = fptrunc double %in to float
- store float %res, float* %addr
+ store float %res, ptr %addr
ret void
}
-define void @test_itofp(i32 %in, double* %addr) {
+define void @test_itofp(i32 %in, ptr %addr) {
; CHECK-LABEL: test_itofp:
; CHECK: bl ___floatsidf
%res = sitofp i32 %in to double
- store double %res, double* %addr
+ store double %res, ptr %addr
; %res = fptoui double %tmp to i32
ret void
}
-define i32 @test_fptoi(double* %addr) {
+define i32 @test_fptoi(ptr %addr) {
; CHECK-LABEL: test_fptoi:
; CHECK: bl ___fixunsdfsi
- %val = load double, double* %addr
+ %val = load double, ptr %addr
%res = fptoui double %val to i32
ret i32 %res
}
-define void @test_binop(double* %addr) {
+define void @test_binop(ptr %addr) {
; CHECK-LABEL: test_binop:
; CHECK: bl ___adddf3
- %in = load double, double* %addr
+ %in = load double, ptr %addr
%res = fadd double %in, %in
- store double %res, double* %addr
+ store double %res, ptr %addr
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fp.ll b/llvm/test/CodeGen/ARM/fp.ll
index cc47e3baddad7..3295c504a0601 100644
--- a/llvm/test/CodeGen/ARM/fp.ll
+++ b/llvm/test/CodeGen/ARM/fp.ll
@@ -40,12 +40,12 @@ entry:
ret float %tmp
}
-define double @h(double* %v) {
+define double @h(ptr %v) {
;CHECK-LABEL: h:
;CHECK: vldr
;CHECK-NEXT: vmov
entry:
- %tmp = load double, double* %v ; <double> [#uses=1]
+ %tmp = load double, ptr %v ; <double> [#uses=1]
ret double %tmp
}
diff --git a/llvm/test/CodeGen/ARM/fp16-bitcast.ll b/llvm/test/CodeGen/ARM/fp16-bitcast.ll
index 997d3603437d8..c1d99248d2f38 100644
--- a/llvm/test/CodeGen/ARM/fp16-bitcast.ll
+++ b/llvm/test/CodeGen/ARM/fp16-bitcast.ll
@@ -74,7 +74,7 @@ entry:
ret half %add
}
-define half @load_i16(i16 *%hp) {
+define half @load_i16(ptr %hp) {
; CHECK-VFPV4-SOFT-LABEL: load_i16:
; CHECK-VFPV4-SOFT: @ %bb.0: @ %entry
; CHECK-VFPV4-SOFT-NEXT: vmov.f32 s0, #1.000000e+00
@@ -111,20 +111,20 @@ define half @load_i16(i16 *%hp) {
; CHECK-FP16-HARD-NEXT: vadd.f16 s0, s2, s0
; CHECK-FP16-HARD-NEXT: bx lr
entry:
- %h = load i16, i16 *%hp, align 2
+ %h = load i16, ptr %hp, align 2
%hc = bitcast i16 %h to half
%add = fadd half %hc, 1.0
ret half %add
}
-define i16 @load_f16(half *%hp) {
+define i16 @load_f16(ptr %hp) {
; CHECK-LABEL: load_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r0, [r0]
; CHECK-NEXT: adds r0, #1
; CHECK-NEXT: bx lr
entry:
- %h = load half, half *%hp, align 2
+ %h = load half, ptr %hp, align 2
%hc = bitcast half %h to i16
%add = add i16 %hc, 1
ret i16 %add
diff --git a/llvm/test/CodeGen/ARM/fp16-frame-lowering.ll b/llvm/test/CodeGen/ARM/fp16-frame-lowering.ll
index a9ffc3928e931..86e5128cc4bf4 100644
--- a/llvm/test/CodeGen/ARM/fp16-frame-lowering.ll
+++ b/llvm/test/CodeGen/ARM/fp16-frame-lowering.ll
@@ -8,15 +8,15 @@ define void @foo(i32 %count) {
entry:
%half_alloca = alloca half, align 2
; CHECK: vstr.16 {{s[0-9]+}}, [{{r[0-9]+}}, #-10]
- store half 0.0, half* %half_alloca
- call void @bar(half* %half_alloca)
+ store half 0.0, ptr %half_alloca
+ call void @bar(ptr %half_alloca)
; A variable-sized alloca to force the above store to use the frame pointer
; instead of the stack pointer, and so need a negative offset.
%var_alloca = alloca i32, i32 %count
- call void @baz(i32* %var_alloca)
+ call void @baz(ptr %var_alloca)
ret void
}
-declare void @bar(half*)
-declare void @baz(i32*)
+declare void @bar(ptr)
+declare void @baz(ptr)
diff --git a/llvm/test/CodeGen/ARM/fp16-fullfp16.ll b/llvm/test/CodeGen/ARM/fp16-fullfp16.ll
index c6db4d3ae47e4..7381d517505e8 100644
--- a/llvm/test/CodeGen/ARM/fp16-fullfp16.ll
+++ b/llvm/test/CodeGen/ARM/fp16-fullfp16.ll
@@ -1,63 +1,63 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple armv8a-none-none-eabihf -mattr=fullfp16 -asm-verbose=false < %s | FileCheck %s
-define void @test_fadd(half* %p, half* %q) {
+define void @test_fadd(ptr %p, ptr %q) {
; CHECK-LABEL: test_fadd:
; CHECK: vldr.16 s0, [r1]
; CHECK-NEXT: vldr.16 s2, [r0]
; CHECK-NEXT: vadd.f16 s0, s2, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = fadd half %a, %b
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_fsub(half* %p, half* %q) {
+define void @test_fsub(ptr %p, ptr %q) {
; CHECK-LABEL: test_fsub:
; CHECK: vldr.16 s0, [r1]
; CHECK-NEXT: vldr.16 s2, [r0]
; CHECK-NEXT: vsub.f16 s0, s2, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = fsub half %a, %b
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_fmul(half* %p, half* %q) {
+define void @test_fmul(ptr %p, ptr %q) {
; CHECK-LABEL: test_fmul:
; CHECK: vldr.16 s0, [r1]
; CHECK-NEXT: vldr.16 s2, [r0]
; CHECK-NEXT: vmul.f16 s0, s2, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = fmul half %a, %b
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_fdiv(half* %p, half* %q) {
+define void @test_fdiv(ptr %p, ptr %q) {
; CHECK-LABEL: test_fdiv:
; CHECK: vldr.16 s0, [r1]
; CHECK-NEXT: vldr.16 s2, [r0]
; CHECK-NEXT: vdiv.f16 s0, s2, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = fdiv half %a, %b
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define arm_aapcs_vfpcc void @test_frem(half* %p, half* %q) {
+define arm_aapcs_vfpcc void @test_frem(ptr %p, ptr %q) {
; CHECK-LABEL: test_frem:
; CHECK: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
@@ -70,166 +70,166 @@ define arm_aapcs_vfpcc void @test_frem(half* %p, half* %q) {
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vstr.16 s0, [r4]
; CHECK-NEXT: pop {r4, pc}
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = frem half %a, %b
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_load_store(half* %p, half* %q) {
+define void @test_load_store(ptr %p, ptr %q) {
; CHECK-LABEL: test_load_store:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
- store half %a, half* %q
+ %a = load half, ptr %p, align 2
+ store half %a, ptr %q
ret void
}
-define i32 @test_fptosi_i32(half* %p) {
+define i32 @test_fptosi_i32(ptr %p) {
; CHECK-LABEL: test_fptosi_i32:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vcvt.s32.f16 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = fptosi half %a to i32
ret i32 %r
}
; FIXME
-;define i64 @test_fptosi_i64(half* %p) {
-; %a = load half, half* %p, align 2
+;define i64 @test_fptosi_i64(ptr %p) {
+; %a = load half, ptr %p, align 2
; %r = fptosi half %a to i64
; ret i64 %r
;}
-define i32 @test_fptoui_i32(half* %p) {
+define i32 @test_fptoui_i32(ptr %p) {
; CHECK-LABEL: test_fptoui_i32:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vcvt.u32.f16 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = fptoui half %a to i32
ret i32 %r
}
; FIXME
-;define i64 @test_fptoui_i64(half* %p) {
-; %a = load half, half* %p, align 2
+;define i64 @test_fptoui_i64(ptr %p) {
+; %a = load half, ptr %p, align 2
; %r = fptoui half %a to i64
; ret i64 %r
;}
-define void @test_sitofp_i32(i32 %a, half* %p) {
+define void @test_sitofp_i32(i32 %a, ptr %p) {
; CHECK-LABEL: test_sitofp_i32:
; CHECK: vmov s0, r0
; CHECK-NEXT: vcvt.f16.s32 s0, s0
; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: bx lr
%r = sitofp i32 %a to half
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_uitofp_i32(i32 %a, half* %p) {
+define void @test_uitofp_i32(i32 %a, ptr %p) {
; CHECK-LABEL: test_uitofp_i32:
; CHECK: vmov s0, r0
; CHECK-NEXT: vcvt.f16.u32 s0, s0
; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: bx lr
%r = uitofp i32 %a to half
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
; FIXME
-;define void @test_sitofp_i64(i64 %a, half* %p) {
+;define void @test_sitofp_i64(i64 %a, ptr %p) {
; %r = sitofp i64 %a to half
-; store half %r, half* %p
+; store half %r, ptr %p
; ret void
;}
; FIXME
-;define void @test_uitofp_i64(i64 %a, half* %p) {
+;define void @test_uitofp_i64(i64 %a, ptr %p) {
; %r = uitofp i64 %a to half
-; store half %r, half* %p
+; store half %r, ptr %p
; ret void
;}
-define void @test_fptrunc_float(float %f, half* %p) {
+define void @test_fptrunc_float(float %f, ptr %p) {
; CHECK-LABEL: test_fptrunc_float:
; CHECK: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
%a = fptrunc float %f to half
- store half %a, half* %p
+ store half %a, ptr %p
ret void
}
-define void @test_fptrunc_double(double %d, half* %p) {
+define void @test_fptrunc_double(double %d, ptr %p) {
; CHECK-LABEL: test_fptrunc_double:
; CHECK: vcvtb.f16.f64 s0, d0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
%a = fptrunc double %d to half
- store half %a, half* %p
+ store half %a, ptr %p
ret void
}
-define float @test_fpextend_float(half* %p) {
+define float @test_fpextend_float(ptr %p) {
; CHECK-LABEL: test_fpextend_float:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = fpext half %a to float
ret float %r
}
-define double @test_fpextend_double(half* %p) {
+define double @test_fpextend_double(ptr %p) {
; CHECK-LABEL: test_fpextend_double:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vcvtb.f64.f16 d0, s0
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = fpext half %a to double
ret double %r
}
-define i16 @test_bitcast_halftoi16(half* %p) {
+define i16 @test_bitcast_halftoi16(ptr %p) {
; CHECK-LABEL: test_bitcast_halftoi16:
; CHECK: ldrh r0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = bitcast half %a to i16
ret i16 %r
}
-define void @test_bitcast_i16tohalf(i16 %a, half* %p) {
+define void @test_bitcast_i16tohalf(i16 %a, ptr %p) {
; CHECK-LABEL: test_bitcast_i16tohalf:
; CHECK: strh r0, [r1]
; CHECK-NEXT: bx lr
%r = bitcast i16 %a to half
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_sqrt(half* %p) {
+define void @test_sqrt(ptr %p) {
; CHECK-LABEL: test_sqrt:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vsqrt.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.sqrt.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_fpowi(half* %p, i32 %b) {
+define void @test_fpowi(ptr %p, i32 %b) {
; CHECK-LABEL: test_fpowi:
; CHECK: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
@@ -241,13 +241,13 @@ define void @test_fpowi(half* %p, i32 %b) {
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vstr.16 s0, [r4]
; CHECK-NEXT: pop {r4, pc}
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.powi.f16.i32(half %a, i32 %b)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_sin(half* %p) {
+define void @test_sin(ptr %p) {
; CHECK-LABEL: test_sin:
; CHECK: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
@@ -258,13 +258,13 @@ define void @test_sin(half* %p) {
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vstr.16 s0, [r4]
; CHECK-NEXT: pop {r4, pc}
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.sin.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_cos(half* %p) {
+define void @test_cos(ptr %p) {
; CHECK-LABEL: test_cos:
; CHECK: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
@@ -275,13 +275,13 @@ define void @test_cos(half* %p) {
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vstr.16 s0, [r4]
; CHECK-NEXT: pop {r4, pc}
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.cos.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_pow(half* %p, half* %q) {
+define void @test_pow(ptr %p, ptr %q) {
; CHECK-LABEL: test_pow:
; CHECK: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
@@ -294,14 +294,14 @@ define void @test_pow(half* %p, half* %q) {
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vstr.16 s0, [r4]
; CHECK-NEXT: pop {r4, pc}
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = call half @llvm.pow.f16(half %a, half %b)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_exp(half* %p) {
+define void @test_exp(ptr %p) {
; CHECK-LABEL: test_exp:
; CHECK: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
@@ -312,13 +312,13 @@ define void @test_exp(half* %p) {
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vstr.16 s0, [r4]
; CHECK-NEXT: pop {r4, pc}
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.exp.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_exp2(half* %p) {
+define void @test_exp2(ptr %p) {
; CHECK-LABEL: test_exp2:
; CHECK: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
@@ -329,13 +329,13 @@ define void @test_exp2(half* %p) {
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vstr.16 s0, [r4]
; CHECK-NEXT: pop {r4, pc}
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.exp2.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_log(half* %p) {
+define void @test_log(ptr %p) {
; CHECK-LABEL: test_log:
; CHECK: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
@@ -346,13 +346,13 @@ define void @test_log(half* %p) {
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vstr.16 s0, [r4]
; CHECK-NEXT: pop {r4, pc}
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.log.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_log10(half* %p) {
+define void @test_log10(ptr %p) {
; CHECK-LABEL: test_log10:
; CHECK: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
@@ -363,13 +363,13 @@ define void @test_log10(half* %p) {
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vstr.16 s0, [r4]
; CHECK-NEXT: pop {r4, pc}
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.log10.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_log2(half* %p) {
+define void @test_log2(ptr %p) {
; CHECK-LABEL: test_log2:
; CHECK: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
@@ -380,13 +380,13 @@ define void @test_log2(half* %p) {
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vstr.16 s0, [r4]
; CHECK-NEXT: pop {r4, pc}
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.log2.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_fma(half* %p, half* %q, half* %r) {
+define void @test_fma(ptr %p, ptr %q, ptr %r) {
; CHECK-LABEL: test_fma:
; CHECK: vldr.16 s0, [r1]
; CHECK-NEXT: vldr.16 s2, [r0]
@@ -394,55 +394,55 @@ define void @test_fma(half* %p, half* %q, half* %r) {
; CHECK-NEXT: vfma.f16 s4, s2, s0
; CHECK-NEXT: vstr.16 s4, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
- %c = load half, half* %r, align 2
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
+ %c = load half, ptr %r, align 2
%v = call half @llvm.fma.f16(half %a, half %b, half %c)
- store half %v, half* %p
+ store half %v, ptr %p
ret void
}
-define void @test_fabs(half* %p) {
+define void @test_fabs(ptr %p) {
; CHECK-LABEL: test_fabs:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vabs.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.fabs.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_minnum(half* %p, half* %q) {
+define void @test_minnum(ptr %p, ptr %q) {
; CHECK-LABEL: test_minnum:
; CHECK: vldr.16 s0, [r1]
; CHECK-NEXT: vldr.16 s2, [r0]
; CHECK-NEXT: vminnm.f16 s0, s2, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = call half @llvm.minnum.f16(half %a, half %b)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_maxnum(half* %p, half* %q) {
+define void @test_maxnum(ptr %p, ptr %q) {
; CHECK-LABEL: test_maxnum:
; CHECK: vldr.16 s0, [r1]
; CHECK-NEXT: vldr.16 s2, [r0]
; CHECK-NEXT: vmaxnm.f16 s0, s2, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = call half @llvm.maxnum.f16(half %a, half %b)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_minimum(half* %p) {
+define void @test_minimum(ptr %p) {
; CHECK-LABEL: test_minimum:
; CHECK: vldr.16 s2, [r0]
; CHECK-NEXT: vmov.f16 s0, #1.000000e+00
@@ -451,14 +451,14 @@ define void @test_minimum(half* %p) {
; CHECK-NEXT: vselge.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%c = fcmp ult half %a, 1.0
%r = select i1 %c, half %a, half 1.0
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_maximum(half* %p) {
+define void @test_maximum(ptr %p) {
; CHECK-LABEL: test_maximum:
; CHECK: vldr.16 s2, [r0]
; CHECK-NEXT: vmov.f16 s0, #1.000000e+00
@@ -467,14 +467,14 @@ define void @test_maximum(half* %p) {
; CHECK-NEXT: vselge.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%c = fcmp ugt half %a, 1.0
%r = select i1 %c, half %a, half 1.0
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_copysign(half* %p, half* %q) {
+define void @test_copysign(ptr %p, ptr %q) {
; CHECK-LABEL: test_copysign:
; CHECK: .pad #4
; CHECK-NEXT: sub sp, sp, #4
@@ -489,86 +489,86 @@ define void @test_copysign(half* %p, half* %q) {
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: add sp, sp, #4
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = call half @llvm.copysign.f16(half %a, half %b)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_floor(half* %p) {
+define void @test_floor(ptr %p) {
; CHECK-LABEL: test_floor:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vrintm.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.floor.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_ceil(half* %p) {
+define void @test_ceil(ptr %p) {
; CHECK-LABEL: test_ceil:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vrintp.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.ceil.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_trunc(half* %p) {
+define void @test_trunc(ptr %p) {
; CHECK-LABEL: test_trunc:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vrintz.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.trunc.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_rint(half* %p) {
+define void @test_rint(ptr %p) {
; CHECK-LABEL: test_rint:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vrintx.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.rint.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_nearbyint(half* %p) {
+define void @test_nearbyint(ptr %p) {
; CHECK-LABEL: test_nearbyint:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vrintr.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.nearbyint.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_round(half* %p) {
+define void @test_round(ptr %p) {
; CHECK-LABEL: test_round:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vrinta.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
+ %a = load half, ptr %p, align 2
%r = call half @llvm.round.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
-define void @test_fmuladd(half* %p, half* %q, half* %r) {
+define void @test_fmuladd(ptr %p, ptr %q, ptr %r) {
; CHECK-LABEL: test_fmuladd:
; CHECK: vldr.16 s0, [r1]
; CHECK-NEXT: vldr.16 s2, [r0]
@@ -576,11 +576,11 @@ define void @test_fmuladd(half* %p, half* %q, half* %r) {
; CHECK-NEXT: vfma.f16 s4, s2, s0
; CHECK-NEXT: vstr.16 s4, [r0]
; CHECK-NEXT: bx lr
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
- %c = load half, half* %r, align 2
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
+ %c = load half, ptr %r, align 2
%v = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
- store half %v, half* %p
+ store half %v, ptr %p
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll b/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll
index fe9f7b13506c1..6f1f40729bd60 100644
--- a/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll
+++ b/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll
@@ -4,7 +4,7 @@
; Check generated fp16 fused MAC and MLS.
-define arm_aapcs_vfpcc void @fusedMACTest2(half *%a1, half *%a2, half *%a3) {
+define arm_aapcs_vfpcc void @fusedMACTest2(ptr %a1, ptr %a2, ptr %a3) {
; CHECK-LABEL: fusedMACTest2:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r1]
@@ -24,16 +24,16 @@ define arm_aapcs_vfpcc void @fusedMACTest2(half *%a1, half *%a2, half *%a3) {
; DONT-FUSE-NEXT: vstr.16 s0, [r0]
; DONT-FUSE-NEXT: bx lr
- %f1 = load half, half *%a1, align 2
- %f2 = load half, half *%a2, align 2
- %f3 = load half, half *%a3, align 2
+ %f1 = load half, ptr %a1, align 2
+ %f2 = load half, ptr %a2, align 2
+ %f3 = load half, ptr %a3, align 2
%1 = fmul half %f1, %f2
%2 = fadd half %1, %f3
- store half %2, half *%a1, align 2
+ store half %2, ptr %a1, align 2
ret void
}
-define arm_aapcs_vfpcc void @fusedMACTest4(half *%a1, half *%a2, half *%a3) {
+define arm_aapcs_vfpcc void @fusedMACTest4(ptr %a1, ptr %a2, ptr %a3) {
; CHECK-LABEL: fusedMACTest4:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -53,16 +53,16 @@ define arm_aapcs_vfpcc void @fusedMACTest4(half *%a1, half *%a2, half *%a3) {
; DONT-FUSE-NEXT: vstr.16 s0, [r0]
; DONT-FUSE-NEXT: bx lr
- %f1 = load half, half *%a1, align 2
- %f2 = load half, half *%a2, align 2
- %f3 = load half, half *%a3, align 2
+ %f1 = load half, ptr %a1, align 2
+ %f2 = load half, ptr %a2, align 2
+ %f3 = load half, ptr %a3, align 2
%1 = fmul half %f2, %f3
%2 = fsub half %f1, %1
- store half %2, half *%a1, align 2
+ store half %2, ptr %a1, align 2
ret void
}
-define arm_aapcs_vfpcc void @fusedMACTest6(half *%a1, half *%a2, half *%a3) {
+define arm_aapcs_vfpcc void @fusedMACTest6(ptr %a1, ptr %a2, ptr %a3) {
; CHECK-LABEL: fusedMACTest6:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r1]
@@ -82,17 +82,17 @@ define arm_aapcs_vfpcc void @fusedMACTest6(half *%a1, half *%a2, half *%a3) {
; DONT-FUSE-NEXT: vstr.16 s0, [r0]
; DONT-FUSE-NEXT: bx lr
- %f1 = load half, half *%a1, align 2
- %f2 = load half, half *%a2, align 2
- %f3 = load half, half *%a3, align 2
+ %f1 = load half, ptr %a1, align 2
+ %f2 = load half, ptr %a2, align 2
+ %f3 = load half, ptr %a3, align 2
%1 = fmul half %f1, %f2
%2 = fsub half -0.0, %1
%3 = fsub half %2, %f3
- store half %3, half *%a1, align 2
+ store half %3, ptr %a1, align 2
ret void
}
-define arm_aapcs_vfpcc void @fusedMACTest8(half *%a1, half *%a2, half *%a3) {
+define arm_aapcs_vfpcc void @fusedMACTest8(ptr %a1, ptr %a2, ptr %a3) {
; CHECK-LABEL: fusedMACTest8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r1]
@@ -112,16 +112,16 @@ define arm_aapcs_vfpcc void @fusedMACTest8(half *%a1, half *%a2, half *%a3) {
; DONT-FUSE-NEXT: vstr.16 s0, [r0]
; DONT-FUSE-NEXT: bx lr
- %f1 = load half, half *%a1, align 2
- %f2 = load half, half *%a2, align 2
- %f3 = load half, half *%a3, align 2
+ %f1 = load half, ptr %a1, align 2
+ %f2 = load half, ptr %a2, align 2
+ %f3 = load half, ptr %a3, align 2
%1 = fmul half %f1, %f2
%2 = fsub half %1, %f3
- store half %2, half *%a1, align 2
+ store half %2, ptr %a1, align 2
ret void
}
-define arm_aapcs_vfpcc void @test_fma_f16(half *%aa, half *%bb, half *%cc) nounwind readnone ssp {
+define arm_aapcs_vfpcc void @test_fma_f16(ptr %aa, ptr %bb, ptr %cc) nounwind readnone ssp {
; CHECK-LABEL: test_fma_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr.16 s0, [r1]
@@ -140,15 +140,15 @@ define arm_aapcs_vfpcc void @test_fma_f16(half *%aa, half *%bb, half *%cc) nounw
; DONT-FUSE-NEXT: vstr.16 s4, [r0]
; DONT-FUSE-NEXT: bx lr
entry:
- %a = load half, half *%aa, align 2
- %b = load half, half *%bb, align 2
- %c = load half, half *%cc, align 2
+ %a = load half, ptr %aa, align 2
+ %b = load half, ptr %bb, align 2
+ %c = load half, ptr %cc, align 2
%tmp1 = tail call half @llvm.fma.f16(half %a, half %b, half %c) nounwind readnone
- store half %tmp1, half *%aa, align 2
+ store half %tmp1, ptr %aa, align 2
ret void
}
-define arm_aapcs_vfpcc void @test_fnms_f16(half *%aa, half *%bb, half *%cc) nounwind readnone ssp {
+define arm_aapcs_vfpcc void @test_fnms_f16(ptr %aa, ptr %bb, ptr %cc) nounwind readnone ssp {
; CHECK-LABEL: test_fnms_f16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r1]
@@ -167,16 +167,16 @@ define arm_aapcs_vfpcc void @test_fnms_f16(half *%aa, half *%bb, half *%cc) noun
; DONT-FUSE-NEXT: vstr.16 s4, [r0]
; DONT-FUSE-NEXT: bx lr
- %a = load half, half *%aa, align 2
- %b = load half, half *%bb, align 2
- %c = load half, half *%cc, align 2
+ %a = load half, ptr %aa, align 2
+ %b = load half, ptr %bb, align 2
+ %c = load half, ptr %cc, align 2
%tmp2 = fsub half -0.0, %c
%tmp3 = tail call half @llvm.fma.f16(half %a, half %b, half %c) nounwind readnone
- store half %tmp3, half *%aa, align 2
+ store half %tmp3, ptr %aa, align 2
ret void
}
-define arm_aapcs_vfpcc void @test_fma_const_fold(half *%aa, half *%bb) nounwind {
+define arm_aapcs_vfpcc void @test_fma_const_fold(ptr %aa, ptr %bb) nounwind {
; CHECK-LABEL: test_fma_const_fold:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r1]
@@ -193,14 +193,14 @@ define arm_aapcs_vfpcc void @test_fma_const_fold(half *%aa, half *%bb) nounwind
; DONT-FUSE-NEXT: vstr.16 s0, [r0]
; DONT-FUSE-NEXT: bx lr
- %a = load half, half *%aa, align 2
- %b = load half, half *%bb, align 2
+ %a = load half, ptr %aa, align 2
+ %b = load half, ptr %bb, align 2
%ret = call half @llvm.fma.f16(half %a, half 1.0, half %b)
- store half %ret, half *%aa, align 2
+ store half %ret, ptr %aa, align 2
ret void
}
-define arm_aapcs_vfpcc void @test_fma_canonicalize(half *%aa, half *%bb) nounwind {
+define arm_aapcs_vfpcc void @test_fma_canonicalize(ptr %aa, ptr %bb) nounwind {
; CHECK-LABEL: test_fma_canonicalize:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r0]
@@ -219,14 +219,14 @@ define arm_aapcs_vfpcc void @test_fma_canonicalize(half *%aa, half *%bb) nounwin
; DONT-FUSE-NEXT: vstr.16 s2, [r0]
; DONT-FUSE-NEXT: bx lr
- %a = load half, half *%aa, align 2
- %b = load half, half *%bb, align 2
+ %a = load half, ptr %aa, align 2
+ %b = load half, ptr %bb, align 2
%ret = call half @llvm.fma.f16(half 2.0, half %a, half %b)
- store half %ret, half *%aa, align 2
+ store half %ret, ptr %aa, align 2
ret void
}
-define arm_aapcs_vfpcc void @fms1(half *%a1, half *%a2, half *%a3) {
+define arm_aapcs_vfpcc void @fms1(ptr %a1, ptr %a2, ptr %a3) {
; CHECK-LABEL: fms1:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r1]
@@ -245,16 +245,16 @@ define arm_aapcs_vfpcc void @fms1(half *%a1, half *%a2, half *%a3) {
; DONT-FUSE-NEXT: vstr.16 s4, [r0]
; DONT-FUSE-NEXT: bx lr
- %f1 = load half, half *%a1, align 2
- %f2 = load half, half *%a2, align 2
- %f3 = load half, half *%a3, align 2
+ %f1 = load half, ptr %a1, align 2
+ %f2 = load half, ptr %a2, align 2
+ %f3 = load half, ptr %a3, align 2
%s = fsub half -0.0, %f1
%ret = call half @llvm.fma.f16(half %s, half %f2, half %f3)
- store half %ret, half *%a1, align 2
+ store half %ret, ptr %a1, align 2
ret void
}
-define arm_aapcs_vfpcc void @fms2(half *%a1, half *%a2, half *%a3) {
+define arm_aapcs_vfpcc void @fms2(ptr %a1, ptr %a2, ptr %a3) {
; CHECK-LABEL: fms2:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r1]
@@ -273,16 +273,16 @@ define arm_aapcs_vfpcc void @fms2(half *%a1, half *%a2, half *%a3) {
; DONT-FUSE-NEXT: vstr.16 s4, [r0]
; DONT-FUSE-NEXT: bx lr
- %f1 = load half, half *%a1, align 2
- %f2 = load half, half *%a2, align 2
- %f3 = load half, half *%a3, align 2
+ %f1 = load half, ptr %a1, align 2
+ %f2 = load half, ptr %a2, align 2
+ %f3 = load half, ptr %a3, align 2
%s = fsub half -0.0, %f1
%ret = call half @llvm.fma.f16(half %f2, half %s, half %f3)
- store half %ret, half *%a1, align 2
+ store half %ret, ptr %a1, align 2
ret void
}
-define arm_aapcs_vfpcc void @fnma1(half *%a1, half *%a2, half *%a3) {
+define arm_aapcs_vfpcc void @fnma1(ptr %a1, ptr %a2, ptr %a3) {
; CHECK-LABEL: fnma1:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r1]
@@ -301,16 +301,16 @@ define arm_aapcs_vfpcc void @fnma1(half *%a1, half *%a2, half *%a3) {
; DONT-FUSE-NEXT: vstr.16 s4, [r0]
; DONT-FUSE-NEXT: bx lr
- %f1 = load half, half *%a1, align 2
- %f2 = load half, half *%a2, align 2
- %f3 = load half, half *%a3, align 2
+ %f1 = load half, ptr %a1, align 2
+ %f2 = load half, ptr %a2, align 2
+ %f3 = load half, ptr %a3, align 2
%fma = call half @llvm.fma.f16(half %f1, half %f2, half %f3)
%n1 = fsub half -0.0, %fma
- store half %n1, half *%a1, align 2
+ store half %n1, ptr %a1, align 2
ret void
}
-define arm_aapcs_vfpcc void @fnma2(half *%a1, half *%a2, half *%a3) {
+define arm_aapcs_vfpcc void @fnma2(ptr %a1, ptr %a2, ptr %a3) {
; CHECK-LABEL: fnma2:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r1]
@@ -329,17 +329,17 @@ define arm_aapcs_vfpcc void @fnma2(half *%a1, half *%a2, half *%a3) {
; DONT-FUSE-NEXT: vstr.16 s4, [r0]
; DONT-FUSE-NEXT: bx lr
- %f1 = load half, half *%a1, align 2
- %f2 = load half, half *%a2, align 2
- %f3 = load half, half *%a3, align 2
+ %f1 = load half, ptr %a1, align 2
+ %f2 = load half, ptr %a2, align 2
+ %f3 = load half, ptr %a3, align 2
%n1 = fsub half -0.0, %f1
%n3 = fsub half -0.0, %f3
%ret = call half @llvm.fma.f16(half %n1, half %f2, half %n3)
- store half %ret, half *%a1, align 2
+ store half %ret, ptr %a1, align 2
ret void
}
-define arm_aapcs_vfpcc void @fnms1(half *%a1, half *%a2, half *%a3) {
+define arm_aapcs_vfpcc void @fnms1(ptr %a1, ptr %a2, ptr %a3) {
; CHECK-LABEL: fnms1:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r1]
@@ -358,16 +358,16 @@ define arm_aapcs_vfpcc void @fnms1(half *%a1, half *%a2, half *%a3) {
; DONT-FUSE-NEXT: vstr.16 s4, [r0]
; DONT-FUSE-NEXT: bx lr
- %f1 = load half, half *%a1, align 2
- %f2 = load half, half *%a2, align 2
- %f3 = load half, half *%a3, align 2
+ %f1 = load half, ptr %a1, align 2
+ %f2 = load half, ptr %a2, align 2
+ %f3 = load half, ptr %a3, align 2
%n3 = fsub half -0.0, %f3
%ret = call half @llvm.fma.f16(half %f1, half %f2, half %n3)
- store half %ret, half *%a1, align 2
+ store half %ret, ptr %a1, align 2
ret void
}
-define arm_aapcs_vfpcc void @fnms2(half *%a1, half *%a2, half *%a3) {
+define arm_aapcs_vfpcc void @fnms2(ptr %a1, ptr %a2, ptr %a3) {
; CHECK-LABEL: fnms2:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r1]
@@ -386,17 +386,17 @@ define arm_aapcs_vfpcc void @fnms2(half *%a1, half *%a2, half *%a3) {
; DONT-FUSE-NEXT: vstr.16 s4, [r0]
; DONT-FUSE-NEXT: bx lr
- %f1 = load half, half *%a1, align 2
- %f2 = load half, half *%a2, align 2
- %f3 = load half, half *%a3, align 2
+ %f1 = load half, ptr %a1, align 2
+ %f2 = load half, ptr %a2, align 2
+ %f3 = load half, ptr %a3, align 2
%n1 = fsub half -0.0, %f1
%fma = call half @llvm.fma.f16(half %n1, half %f2, half %f3)
%n = fsub half -0.0, %fma
- store half %n, half *%a1, align 2
+ store half %n, ptr %a1, align 2
ret void
}
-define arm_aapcs_vfpcc void @fnms3(half *%a1, half *%a2, half *%a3) {
+define arm_aapcs_vfpcc void @fnms3(ptr %a1, ptr %a2, ptr %a3) {
; CHECK-LABEL: fnms3:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r0]
@@ -415,13 +415,13 @@ define arm_aapcs_vfpcc void @fnms3(half *%a1, half *%a2, half *%a3) {
; DONT-FUSE-NEXT: vstr.16 s4, [r0]
; DONT-FUSE-NEXT: bx lr
- %f1 = load half, half *%a1, align 2
- %f2 = load half, half *%a2, align 2
- %f3 = load half, half *%a3, align 2
+ %f1 = load half, ptr %a1, align 2
+ %f2 = load half, ptr %a2, align 2
+ %f3 = load half, ptr %a3, align 2
%n2 = fsub half -0.0, %f2
%fma = call half @llvm.fma.f16(half %f1, half %n2, half %f3)
%n1 = fsub half -0.0, %fma
- store half %n1, half *%a1, align 2
+ store half %n1, ptr %a1, align 2
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fp16-instructions.ll b/llvm/test/CodeGen/ARM/fp16-instructions.ll
index 5e3e4469fcc09..8477cb7e02b23 100644
--- a/llvm/test/CodeGen/ARM/fp16-instructions.ll
+++ b/llvm/test/CodeGen/ARM/fp16-instructions.ll
@@ -196,7 +196,7 @@ entry:
br label %for.cond
for.cond:
- %0 = load half, half* %f, align 2
+ %0 = load half, ptr %f, align 2
%cmp = fcmp nnan ninf nsz ole half %0, 0xH6800
br i1 %cmp, label %for.body, label %for.end
@@ -692,8 +692,8 @@ entry:
}
; 35. VSELEQ
-define half @select_cc1(half* %a0) {
- %1 = load half, half* %a0
+define half @select_cc1(ptr %a0) {
+ %1 = load half, ptr %a0
%2 = fcmp nsz oeq half %1, 0xH0001
%3 = select i1 %2, half 0xHC000, half 0xH0002
ret half %3
@@ -719,8 +719,8 @@ define half @select_cc1(half* %a0) {
; be encoded as an FP16 immediate need to be added here.
;
; 36. VSELGE
-define half @select_cc_ge1(half* %a0) {
- %1 = load half, half* %a0
+define half @select_cc_ge1(ptr %a0) {
+ %1 = load half, ptr %a0
%2 = fcmp nsz oge half %1, 0xH0001
%3 = select i1 %2, half 0xHC000, half 0xH0002
ret half %3
@@ -741,8 +741,8 @@ define half @select_cc_ge1(half* %a0) {
; CHECK-SOFTFP-FP16-T32-NEXT: vmovge.f32 s{{.}}, s{{.}}
}
-define half @select_cc_ge2(half* %a0) {
- %1 = load half, half* %a0
+define half @select_cc_ge2(ptr %a0) {
+ %1 = load half, ptr %a0
%2 = fcmp nsz ole half %1, 0xH0001
%3 = select i1 %2, half 0xHC000, half 0xH0002
ret half %3
@@ -763,8 +763,8 @@ define half @select_cc_ge2(half* %a0) {
; CHECK-SOFTFP-FP16-T32-NEXT: vmovls.f32 s{{.}}, s{{.}}
}
-define half @select_cc_ge3(half* %a0) {
- %1 = load half, half* %a0
+define half @select_cc_ge3(ptr %a0) {
+ %1 = load half, ptr %a0
%2 = fcmp nsz ugt half %1, 0xH0001
%3 = select i1 %2, half 0xHC000, half 0xH0002
ret half %3
@@ -785,8 +785,8 @@ define half @select_cc_ge3(half* %a0) {
; CHECK-SOFTFP-FP16-T32-NEXT: vmovhi.f32 s{{.}}, s{{.}}
}
-define half @select_cc_ge4(half* %a0) {
- %1 = load half, half* %a0
+define half @select_cc_ge4(ptr %a0) {
+ %1 = load half, ptr %a0
%2 = fcmp nsz ult half %1, 0xH0001
%3 = select i1 %2, half 0xHC000, half 0xH0002
ret half %3
@@ -808,8 +808,8 @@ define half @select_cc_ge4(half* %a0) {
}
; 37. VSELGT
-define half @select_cc_gt1(half* %a0) {
- %1 = load half, half* %a0
+define half @select_cc_gt1(ptr %a0) {
+ %1 = load half, ptr %a0
%2 = fcmp nsz ogt half %1, 0xH0001
%3 = select i1 %2, half 0xHC000, half 0xH0002
ret half %3
@@ -830,8 +830,8 @@ define half @select_cc_gt1(half* %a0) {
; CHECK-SOFTFP-FP16-T32-NEXT: vmovgt.f32 s{{.}}, s{{.}}
}
-define half @select_cc_gt2(half* %a0) {
- %1 = load half, half* %a0
+define half @select_cc_gt2(ptr %a0) {
+ %1 = load half, ptr %a0
%2 = fcmp nsz uge half %1, 0xH0001
%3 = select i1 %2, half 0xHC000, half 0xH0002
ret half %3
@@ -852,8 +852,8 @@ define half @select_cc_gt2(half* %a0) {
; CHECK-SOFTFP-FP16-T32-NEXT: vmovpl.f32 s{{.}}, s{{.}}
}
-define half @select_cc_gt3(half* %a0) {
- %1 = load half, half* %a0
+define half @select_cc_gt3(ptr %a0) {
+ %1 = load half, ptr %a0
%2 = fcmp nsz ule half %1, 0xH0001
%3 = select i1 %2, half 0xHC000, half 0xH0002
ret half %3
@@ -874,8 +874,8 @@ define half @select_cc_gt3(half* %a0) {
; CHECK-SOFTFP-FP16-T32-NEXT: vmovle.f32 s{{.}}, s{{.}}
}
-define half @select_cc_gt4(half* %a0) {
- %1 = load half, half* %a0
+define half @select_cc_gt4(ptr %a0) {
+ %1 = load half, ptr %a0
%2 = fcmp nsz olt half %1, 0xH0001
%3 = select i1 %2, half 0xHC000, half 0xH0002
ret half %3
@@ -1009,9 +1009,8 @@ entry:
%S = alloca half, align 2
%tmp.0.extract.trunc = trunc i32 %A.coerce to i16
%0 = bitcast i16 %tmp.0.extract.trunc to half
- %S.0.S.0..sroa_cast = bitcast half* %S to i8*
- store volatile half 0xH3C00, half* %S, align 2
- %S.0.S.0. = load volatile half, half* %S, align 2
+ store volatile half 0xH3C00, ptr %S, align 2
+ %S.0.S.0. = load volatile half, ptr %S, align 2
%add = fadd half %S.0.S.0., %0
%1 = bitcast half %add to i16
%tmp2.0.insert.ext = zext i16 %1 to i32
@@ -1031,12 +1030,12 @@ define i32 @fn1() {
entry:
%coerce = alloca half, align 2
%tmp2 = alloca i32, align 4
- store half 0xH7C00, half* %coerce, align 2
- %0 = load i32, i32* %tmp2, align 4
- %call = call i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 %0)
- store half 0xH7C00, half* %coerce, align 2
- %1 = load i32, i32* %tmp2, align 4
- %call3 = call i32 bitcast (i32 (...)* @fn3 to i32 (i32)*)(i32 %1)
+ store half 0xH7C00, ptr %coerce, align 2
+ %0 = load i32, ptr %tmp2, align 4
+ %call = call i32 @fn2(i32 %0)
+ store half 0xH7C00, ptr %coerce, align 2
+ %1 = load i32, ptr %tmp2, align 4
+ %call3 = call i32 @fn3(i32 %1)
ret i32 %call3
; CHECK-SPILL-RELOAD-LABEL: fn1:
diff --git a/llvm/test/CodeGen/ARM/fp16-load-store.ll b/llvm/test/CodeGen/ARM/fp16-load-store.ll
index 272827135b72e..01297ef22561a 100644
--- a/llvm/test/CodeGen/ARM/fp16-load-store.ll
+++ b/llvm/test/CodeGen/ARM/fp16-load-store.ll
@@ -1,105 +1,103 @@
; RUN: llc < %s -mtriple armv8a--none-eabi -mattr=+fullfp16 | FileCheck %s
-define void @load_zero(half* %in, half* %out) {
+define void @load_zero(ptr %in, ptr %out) {
entry:
; CHECK-LABEL: load_zero:
; CHECK: vldr.16 {{s[0-9]+}}, [r0]
- %arrayidx = getelementptr inbounds half, half* %in, i32 0
- %load = load half, half* %arrayidx, align 2
- store half %load, half* %out
+ %load = load half, ptr %in, align 2
+ store half %load, ptr %out
ret void
}
-define void @load_255(half* %in, half* %out) {
+define void @load_255(ptr %in, ptr %out) {
entry:
; CHECK-LABEL: load_255:
; CHECK: vldr.16 {{s[0-9]+}}, [r0, #510]
- %arrayidx = getelementptr inbounds half, half* %in, i32 255
- %load = load half, half* %arrayidx, align 2
- store half %load, half* %out
+ %arrayidx = getelementptr inbounds half, ptr %in, i32 255
+ %load = load half, ptr %arrayidx, align 2
+ store half %load, ptr %out
ret void
}
-define void @load_256(half* %in, half* %out) {
+define void @load_256(ptr %in, ptr %out) {
entry:
; CHECK-LABEL: load_256:
; CHECK: add [[ADDR:r[0-9]+]], r0, #512
; CHECK: vldr.16 {{s[0-9]+}}, [[[ADDR]]]
- %arrayidx = getelementptr inbounds half, half* %in, i32 256
- %load = load half, half* %arrayidx, align 2
- store half %load, half* %out
+ %arrayidx = getelementptr inbounds half, ptr %in, i32 256
+ %load = load half, ptr %arrayidx, align 2
+ store half %load, ptr %out
ret void
}
-define void @load_neg_255(half* %in, half* %out) {
+define void @load_neg_255(ptr %in, ptr %out) {
entry:
; CHECK-LABEL: load_neg_255:
; CHECK: vldr.16 {{s[0-9]+}}, [r0, #-510]
- %arrayidx = getelementptr inbounds half, half* %in, i32 -255
- %load = load half, half* %arrayidx, align 2
- store half %load, half* %out
+ %arrayidx = getelementptr inbounds half, ptr %in, i32 -255
+ %load = load half, ptr %arrayidx, align 2
+ store half %load, ptr %out
ret void
}
-define void @load_neg_256(half* %in, half* %out) {
+define void @load_neg_256(ptr %in, ptr %out) {
entry:
; CHECK-LABEL: load_neg_256:
; CHECK: sub [[ADDR:r[0-9]+]], r0, #512
; CHECK: vldr.16 {{s[0-9]+}}, [[[ADDR]]]
- %arrayidx = getelementptr inbounds half, half* %in, i32 -256
- %load = load half, half* %arrayidx, align 2
- store half %load, half* %out
+ %arrayidx = getelementptr inbounds half, ptr %in, i32 -256
+ %load = load half, ptr %arrayidx, align 2
+ store half %load, ptr %out
ret void
}
-define void @store_zero(half* %in, half* %out) {
+define void @store_zero(ptr %in, ptr %out) {
entry:
; CHECK-LABEL: store_zero:
- %load = load half, half* %in, align 2
+ %load = load half, ptr %in, align 2
; CHECK: vstr.16 {{s[0-9]+}}, [r1]
- %arrayidx = getelementptr inbounds half, half* %out, i32 0
- store half %load, half* %arrayidx
+ store half %load, ptr %out
ret void
}
-define void @store_255(half* %in, half* %out) {
+define void @store_255(ptr %in, ptr %out) {
entry:
; CHECK-LABEL: store_255:
- %load = load half, half* %in, align 2
+ %load = load half, ptr %in, align 2
; CHECK: vstr.16 {{s[0-9]+}}, [r1, #510]
- %arrayidx = getelementptr inbounds half, half* %out, i32 255
- store half %load, half* %arrayidx
+ %arrayidx = getelementptr inbounds half, ptr %out, i32 255
+ store half %load, ptr %arrayidx
ret void
}
-define void @store_256(half* %in, half* %out) {
+define void @store_256(ptr %in, ptr %out) {
entry:
; CHECK-LABEL: store_256:
- %load = load half, half* %in, align 2
+ %load = load half, ptr %in, align 2
; CHECK: add [[ADDR:r[0-9]+]], r1, #512
; CHECK: vstr.16 {{s[0-9]+}}, [[[ADDR]]]
- %arrayidx = getelementptr inbounds half, half* %out, i32 256
- store half %load, half* %arrayidx
+ %arrayidx = getelementptr inbounds half, ptr %out, i32 256
+ store half %load, ptr %arrayidx
ret void
}
-define void @store_neg_255(half* %in, half* %out) {
+define void @store_neg_255(ptr %in, ptr %out) {
entry:
; CHECK-LABEL: store_neg_255:
- %load = load half, half* %in, align 2
+ %load = load half, ptr %in, align 2
; CHECK: vstr.16 {{s[0-9]+}}, [r1, #-510]
- %arrayidx = getelementptr inbounds half, half* %out, i32 -255
- store half %load, half* %arrayidx
+ %arrayidx = getelementptr inbounds half, ptr %out, i32 -255
+ store half %load, ptr %arrayidx
ret void
}
-define void @store_neg_256(half* %in, half* %out) {
+define void @store_neg_256(ptr %in, ptr %out) {
entry:
; CHECK-LABEL: store_neg_256:
- %load = load half, half* %in, align 2
+ %load = load half, ptr %in, align 2
; CHECK: sub [[ADDR:r[0-9]+]], r1, #512
; CHECK: vstr.16 {{s[0-9]+}}, [[[ADDR]]]
- %arrayidx = getelementptr inbounds half, half* %out, i32 -256
- store half %load, half* %arrayidx
+ %arrayidx = getelementptr inbounds half, ptr %out, i32 -256
+ store half %load, ptr %arrayidx
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fp16-no-condition.ll b/llvm/test/CodeGen/ARM/fp16-no-condition.ll
index 8e21ecc19e7ab..edfa61f773f9d 100644
--- a/llvm/test/CodeGen/ARM/fp16-no-condition.ll
+++ b/llvm/test/CodeGen/ARM/fp16-no-condition.ll
@@ -3,19 +3,19 @@
; Require the vmul.f16 not to be predicated, because it's illegal to
; do so with fp16 instructions
-define half @conditional_fmul_f16(half* %p) {
+define half @conditional_fmul_f16(ptr %p) {
; CHECK-LABEL: conditional_fmul_f16:
; CHECK: vmul.f16
entry:
- %p1 = getelementptr half, half* %p, i32 1
- %a = load half, half* %p, align 2
- %threshold = load half, half* %p1, align 2
+ %p1 = getelementptr half, ptr %p, i32 1
+ %a = load half, ptr %p, align 2
+ %threshold = load half, ptr %p1, align 2
%flag = fcmp ogt half %a, %threshold
br i1 %flag, label %mul, label %out
mul:
- %p2 = getelementptr half, half* %p, i32 2
- %mult = load half, half* %p2, align 2
+ %p2 = getelementptr half, ptr %p, i32 2
+ %mult = load half, ptr %p2, align 2
%b = fmul half %a, %mult
br label %out
@@ -26,19 +26,19 @@ out:
; Expect that the corresponding vmul.f32 _will_ be predicated (to make
; sure the previous test is really testing something)
-define float @conditional_fmul_f32(float* %p) {
+define float @conditional_fmul_f32(ptr %p) {
; CHECK-LABEL: conditional_fmul_f32:
; CHECK: vmulgt.f32
entry:
- %p1 = getelementptr float, float* %p, i32 1
- %a = load float, float* %p, align 2
- %threshold = load float, float* %p1, align 2
+ %p1 = getelementptr float, ptr %p, i32 1
+ %a = load float, ptr %p, align 2
+ %threshold = load float, ptr %p1, align 2
%flag = fcmp ogt float %a, %threshold
br i1 %flag, label %mul, label %out
mul:
- %p2 = getelementptr float, float* %p, i32 2
- %mult = load float, float* %p2, align 2
+ %p2 = getelementptr float, ptr %p, i32 2
+ %mult = load float, ptr %p2, align 2
%b = fmul float %a, %mult
br label %out
@@ -49,15 +49,15 @@ out:
; Require the two comparisons to be done with unpredicated vcmp.f16
; instructions (again, it is illegal to predicate them)
-define void @chained_comparisons_f16(half* %p) {
+define void @chained_comparisons_f16(ptr %p) {
; CHECK-LABEL: chained_comparisons_f16:
; CHECK: vcmp.f16
; CHECK: vcmp.f16
entry:
- %p1 = getelementptr half, half* %p, i32 1
+ %p1 = getelementptr half, ptr %p, i32 1
- %a = load half, half* %p, align 2
- %b = load half, half* %p1, align 2
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %p1, align 2
%aflag = fcmp oeq half %a, 0xH0000
%bflag = fcmp oeq half %b, 0xH0000
@@ -74,15 +74,15 @@ out:
; Again, do the corresponding test with 32-bit floats and check that
; the second comparison _is_ predicated on the result of the first.
-define void @chained_comparisons_f32(float* %p) {
+define void @chained_comparisons_f32(ptr %p) {
; CHECK-LABEL: chained_comparisons_f32:
; CHECK: vcmp.f32
; CHECK: vcmpne.f32
entry:
- %p1 = getelementptr float, float* %p, i32 1
+ %p1 = getelementptr float, ptr %p, i32 1
- %a = load float, float* %p, align 2
- %b = load float, float* %p1, align 2
+ %a = load float, ptr %p, align 2
+ %b = load float, ptr %p1, align 2
%aflag = fcmp oeq float %a, 0x00000000
%bflag = fcmp oeq float %b, 0x00000000
diff --git a/llvm/test/CodeGen/ARM/fp16-promote.ll b/llvm/test/CodeGen/ARM/fp16-promote.ll
index 9cfddc60ff0c2..15e7caa51083f 100644
--- a/llvm/test/CodeGen/ARM/fp16-promote.ll
+++ b/llvm/test/CodeGen/ARM/fp16-promote.ll
@@ -14,11 +14,11 @@ target triple = "armv7---eabihf"
; CHECK-NOVFP: bl __aeabi_fadd
; CHECK-FP16: vcvtb.f16.f32
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_fadd(half* %p, half* %q) #0 {
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+define void @test_fadd(ptr %p, ptr %q) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = fadd half %a, %b
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -31,11 +31,11 @@ define void @test_fadd(half* %p, half* %q) #0 {
; CHECK-NOVFP: bl __aeabi_fsub
; CHECK-FP16: vcvtb.f16.f32
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_fsub(half* %p, half* %q) #0 {
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+define void @test_fsub(ptr %p, ptr %q) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = fsub half %a, %b
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -48,11 +48,11 @@ define void @test_fsub(half* %p, half* %q) #0 {
; CHECK-NOVFP: bl __aeabi_fmul
; CHECK-FP16: vcvtb.f16.f32
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_fmul(half* %p, half* %q) #0 {
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+define void @test_fmul(ptr %p, ptr %q) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = fmul half %a, %b
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -65,11 +65,11 @@ define void @test_fmul(half* %p, half* %q) #0 {
; CHECK-NOVFP: bl __aeabi_fdiv
; CHECK-FP16: vcvtb.f16.f32
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_fdiv(half* %p, half* %q) #0 {
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+define void @test_fdiv(ptr %p, ptr %q) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = fdiv half %a, %b
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -81,11 +81,11 @@ define void @test_fdiv(half* %p, half* %q) #0 {
; CHECK-LIBCALL: bl fmodf
; CHECK-FP16: vcvtb.f16.f32
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_frem(half* %p, half* %q) #0 {
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+define void @test_frem(ptr %p, ptr %q) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = frem half %a, %b
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -93,9 +93,9 @@ define void @test_frem(half* %p, half* %q) #0 {
; CHECK-ALL-NEXT: .fnstart
; CHECK-ALL: ldrh {{r[0-9]+}}, [{{r[0-9]+}}]
; CHECK-ALL: strh {{r[0-9]+}}, [{{r[0-9]+}}]
-define void @test_load_store(half* %p, half* %q) #0 {
- %a = load half, half* %p, align 2
- store half %a, half* %q
+define void @test_load_store(ptr %p, ptr %q) #0 {
+ %a = load half, ptr %p, align 2
+ store half %a, ptr %q
ret void
}
@@ -153,11 +153,11 @@ define half @test_tailcall_flipped(half %a, half %b) #0 {
; CHECK-ALL: movne {{r[0-9]+}}, {{r[0-9]+}}
; CHECK-ALL: ldrh {{r[0-9]+}}, [{{r[0-9]+}}]
; CHECK-ALL: strh {{r[0-9]+}}, [{{r[0-9]+}}]
-define void @test_select(half* %p, half* %q, i1 zeroext %c) #0 {
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+define void @test_select(ptr %p, ptr %q, i1 zeroext %c) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = select i1 %c, half %a, half %b
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -174,9 +174,9 @@ define void @test_select(half* %p, half* %q, i1 zeroext %c) #0 {
; CHECK-VFP-NEXT: movwne
; CHECK-NOVFP-NEXT: clz r0, r0
; CHECK-NOVFP-NEXT: lsr r0, r0, #5
-define i1 @test_fcmp_une(half* %p, half* %q) #0 {
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+define i1 @test_fcmp_une(ptr %p, ptr %q) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = fcmp une half %a, %b
ret i1 %r
}
@@ -190,9 +190,9 @@ define i1 @test_fcmp_une(half* %p, half* %q) #0 {
; CHECK-NOVFP: bl __aeabi_fcmpeq
; CHECK-FP16: vmrs APSR_nzcv, fpscr
; CHECK-LIBCALL: movw{{ne|eq}}
-define i1 @test_fcmp_ueq(half* %p, half* %q) #0 {
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+define i1 @test_fcmp_ueq(ptr %p, ptr %q) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = fcmp ueq half %a, %b
ret i1 %r
}
@@ -208,20 +208,20 @@ define i1 @test_fcmp_ueq(half* %p, half* %q) #0 {
; CHECK-VFP: movmi
; CHECK-VFP: str
; CHECK-NOVFP: str
-define void @test_br_cc(half* %p, half* %q, i32* %p1, i32* %p2) #0 {
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+define void @test_br_cc(ptr %p, ptr %q, ptr %p1, ptr %p2) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%c = fcmp uge half %a, %b
br i1 %c, label %then, label %else
then:
- store i32 0, i32* %p1
+ store i32 0, ptr %p1
ret void
else:
- store i32 0, i32* %p2
+ store i32 0, ptr %p2
ret void
}
-declare i1 @test_dummy(half* %p) #0
+declare i1 @test_dummy(ptr %p) #0
; CHECK-ALL-LABEL: test_phi:
; CHECK-FP16: vcvtb.f32.f16
; CHECK-FP16: [[LOOP:.LBB[1-9_]+]]:
@@ -235,17 +235,17 @@ declare i1 @test_dummy(half* %p) #0
; CHECK-LIBCALL: bl test_dummy
; CHECK-LIBCALL: bne [[LOOP]]
; CHECK-LIBCALL-VFP: bl __aeabi_f2h
-define void @test_phi(half* %p) #0 {
+define void @test_phi(ptr %p) #0 {
entry:
- %a = load half, half* %p
+ %a = load half, ptr %p
br label %loop
loop:
%r = phi half [%a, %entry], [%b, %loop]
- %b = load half, half* %p
- %c = call i1 @test_dummy(half* %p)
+ %b = load half, ptr %p
+ %c = call i1 @test_dummy(ptr %p)
br i1 %c, label %loop, label %return
return:
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -254,8 +254,8 @@ return:
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-VFP: vcvt.s32.f32
; CHECK-NOVFP: bl __aeabi_f2iz
-define i32 @test_fptosi_i32(half* %p) #0 {
- %a = load half, half* %p, align 2
+define i32 @test_fptosi_i32(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%r = fptosi half %a to i32
ret i32 %r
}
@@ -264,8 +264,8 @@ define i32 @test_fptosi_i32(half* %p) #0 {
; CHECK-FP16: vcvtb.f32.f16
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-ALL: bl __aeabi_f2lz
-define i64 @test_fptosi_i64(half* %p) #0 {
- %a = load half, half* %p, align 2
+define i64 @test_fptosi_i64(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%r = fptosi half %a to i64
ret i64 %r
}
@@ -275,8 +275,8 @@ define i64 @test_fptosi_i64(half* %p) #0 {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-VFP: vcvt.u32.f32
; CHECK-NOVFP: bl __aeabi_f2uiz
-define i32 @test_fptoui_i32(half* %p) #0 {
- %a = load half, half* %p, align 2
+define i32 @test_fptoui_i32(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%r = fptoui half %a to i32
ret i32 %r
}
@@ -285,8 +285,8 @@ define i32 @test_fptoui_i32(half* %p) #0 {
; CHECK-FP16: vcvtb.f32.f16
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-ALL: bl __aeabi_f2ulz
-define i64 @test_fptoui_i64(half* %p) #0 {
- %a = load half, half* %p, align 2
+define i64 @test_fptoui_i64(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%r = fptoui half %a to i64
ret i64 %r
}
@@ -296,9 +296,9 @@ define i64 @test_fptoui_i64(half* %p) #0 {
; CHECK-NOVFP: bl __aeabi_i2f
; CHECK-FP16: vcvtb.f16.f32
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_sitofp_i32(i32 %a, half* %p) #0 {
+define void @test_sitofp_i32(i32 %a, ptr %p) #0 {
%r = sitofp i32 %a to half
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -307,9 +307,9 @@ define void @test_sitofp_i32(i32 %a, half* %p) #0 {
; CHECK-NOVFP: bl __aeabi_ui2f
; CHECK-FP16: vcvtb.f16.f32
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_uitofp_i32(i32 %a, half* %p) #0 {
+define void @test_uitofp_i32(i32 %a, ptr %p) #0 {
%r = uitofp i32 %a to half
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -317,9 +317,9 @@ define void @test_uitofp_i32(i32 %a, half* %p) #0 {
; CHECK-ALL: bl __aeabi_l2f
; CHECK-FP16: vcvtb.f16.f32
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_sitofp_i64(i64 %a, half* %p) #0 {
+define void @test_sitofp_i64(i64 %a, ptr %p) #0 {
%r = sitofp i64 %a to half
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -327,9 +327,9 @@ define void @test_sitofp_i64(i64 %a, half* %p) #0 {
; CHECK-ALL: bl __aeabi_ul2f
; CHECK-FP16: vcvtb.f16.f32
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_uitofp_i64(i64 %a, half* %p) #0 {
+define void @test_uitofp_i64(i64 %a, ptr %p) #0 {
%r = uitofp i64 %a to half
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -337,9 +337,9 @@ define void @test_uitofp_i64(i64 %a, half* %p) #0 {
; CHECK-FP16: vcvtb.f16.f32
; CHECK-LIBCALL-LABEL: test_fptrunc_float:
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_fptrunc_float(float %f, half* %p) #0 {
+define void @test_fptrunc_float(float %f, ptr %p) #0 {
%a = fptrunc float %f to half
- store half %a, half* %p
+ store half %a, ptr %p
ret void
}
@@ -347,9 +347,9 @@ define void @test_fptrunc_float(float %f, half* %p) #0 {
; CHECK-FP16: bl __aeabi_d2h
; CHECK-LIBCALL-LABEL: test_fptrunc_double:
; CHECK-LIBCALL: bl __aeabi_d2h
-define void @test_fptrunc_double(double %d, half* %p) #0 {
+define void @test_fptrunc_double(double %d, ptr %p) #0 {
%a = fptrunc double %d to half
- store half %a, half* %p
+ store half %a, ptr %p
ret void
}
@@ -357,8 +357,8 @@ define void @test_fptrunc_double(double %d, half* %p) #0 {
; CHECK-FP16: vcvtb.f32.f16
; CHECK-LIBCALL-LABEL: test_fpextend_float:
; CHECK-LIBCALL: bl __aeabi_h2f
-define float @test_fpextend_float(half* %p) {
- %a = load half, half* %p, align 2
+define float @test_fpextend_float(ptr %p) {
+ %a = load half, ptr %p, align 2
%r = fpext half %a to float
ret float %r
}
@@ -369,8 +369,8 @@ define float @test_fpextend_float(half* %p) {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-VFP: vcvt.f64.f32
; CHECK-NOVFP: bl __aeabi_f2d
-define double @test_fpextend_double(half* %p) {
- %a = load half, half* %p, align 2
+define double @test_fpextend_double(ptr %p) {
+ %a = load half, ptr %p, align 2
%r = fpext half %a to double
ret double %r
}
@@ -379,8 +379,8 @@ define double @test_fpextend_double(half* %p) {
; CHECK-ALL-NEXT: .fnstart
; CHECK-ALL-NEXT: ldrh r0, [r0]
; CHECK-ALL-NEXT: bx lr
-define i16 @test_bitcast_halftoi16(half* %p) #0 {
- %a = load half, half* %p, align 2
+define i16 @test_bitcast_halftoi16(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%r = bitcast half %a to i16
ret i16 %r
}
@@ -389,9 +389,9 @@ define i16 @test_bitcast_halftoi16(half* %p) #0 {
; CHECK-ALL-NEXT: .fnstart
; CHECK-ALL-NEXT: strh r0, [r1]
; CHECK-ALL-NEXT: bx lr
-define void @test_bitcast_i16tohalf(i16 %a, half* %p) #0 {
+define void @test_bitcast_i16tohalf(i16 %a, ptr %p) #0 {
%r = bitcast i16 %a to half
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -426,10 +426,10 @@ declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #0
; CHECK-LIBCALL-VFP: vsqrt.f32
; CHECK-NOVFP: bl sqrtf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_sqrt(half* %p) #0 {
- %a = load half, half* %p, align 2
+define void @test_sqrt(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.sqrt.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -441,10 +441,10 @@ define void @test_sqrt(half* %p) #0 {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl __powisf2
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_fpowi(half* %p, i32 %b) #0 {
- %a = load half, half* %p, align 2
+define void @test_fpowi(ptr %p, i32 %b) #0 {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.powi.f16.i32(half %a, i32 %b)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -456,10 +456,10 @@ define void @test_fpowi(half* %p, i32 %b) #0 {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl sinf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_sin(half* %p) #0 {
- %a = load half, half* %p, align 2
+define void @test_sin(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.sin.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -471,10 +471,10 @@ define void @test_sin(half* %p) #0 {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl cosf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_cos(half* %p) #0 {
- %a = load half, half* %p, align 2
+define void @test_cos(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.cos.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -488,11 +488,11 @@ define void @test_cos(half* %p) #0 {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl powf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_pow(half* %p, half* %q) #0 {
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+define void @test_pow(ptr %p, ptr %q) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = call half @llvm.pow.f16(half %a, half %b)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -504,10 +504,10 @@ define void @test_pow(half* %p, half* %q) #0 {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl powf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_cbrt(half* %p) #0 {
- %a = load half, half* %p, align 2
+define void @test_cbrt(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.pow.f16(half %a, half 0x3FD5540000000000)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -519,10 +519,10 @@ define void @test_cbrt(half* %p) #0 {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl expf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_exp(half* %p) #0 {
- %a = load half, half* %p, align 2
+define void @test_exp(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.exp.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -534,10 +534,10 @@ define void @test_exp(half* %p) #0 {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl exp2f
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_exp2(half* %p) #0 {
- %a = load half, half* %p, align 2
+define void @test_exp2(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.exp2.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -549,10 +549,10 @@ define void @test_exp2(half* %p) #0 {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl logf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_log(half* %p) #0 {
- %a = load half, half* %p, align 2
+define void @test_log(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.log.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -564,10 +564,10 @@ define void @test_log(half* %p) #0 {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl log10f
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_log10(half* %p) #0 {
- %a = load half, half* %p, align 2
+define void @test_log10(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.log10.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -579,10 +579,10 @@ define void @test_log10(half* %p) #0 {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl log2f
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_log2(half* %p) #0 {
- %a = load half, half* %p, align 2
+define void @test_log2(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.log2.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -598,12 +598,12 @@ define void @test_log2(half* %p) #0 {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl fmaf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_fma(half* %p, half* %q, half* %r) #0 {
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
- %c = load half, half* %r, align 2
+define void @test_fma(ptr %p, ptr %q, ptr %r) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
+ %c = load half, ptr %r, align 2
%v = call half @llvm.fma.f16(half %a, half %b, half %c)
- store half %v, half* %p
+ store half %v, ptr %p
ret void
}
@@ -615,10 +615,10 @@ define void @test_fma(half* %p, half* %q, half* %r) #0 {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bic
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_fabs(half* %p) {
- %a = load half, half* %p, align 2
+define void @test_fabs(ptr %p) {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.fabs.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -632,11 +632,11 @@ define void @test_fabs(half* %p) {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl fminf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_minnum(half* %p, half* %q) #0 {
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+define void @test_minnum(ptr %p, ptr %q) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = call half @llvm.minnum.f16(half %a, half %b)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -650,11 +650,11 @@ define void @test_minnum(half* %p, half* %q) #0 {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl fmaxf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_maxnum(half* %p, half* %q) #0 {
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+define void @test_maxnum(ptr %p, ptr %q) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = call half @llvm.maxnum.f16(half %a, half %b)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -670,11 +670,11 @@ define void @test_maxnum(half* %p, half* %q) #0 {
; CHECK-NOVFP: bl __aeabi_fcmpge
; CHECK-FP16: vcvtb.f16.f32
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_minimum(half* %p) #0 {
- %a = load half, half* %p, align 2
+define void @test_minimum(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%c = fcmp ult half %a, 1.0
%r = select i1 %c, half %a, half 1.0
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -690,11 +690,11 @@ define void @test_minimum(half* %p) #0 {
; CHECK-NOVFP: bl __aeabi_fcmple
; CHECK-FP16: vcvtb.f16.f32
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_maximum(half* %p) #0 {
- %a = load half, half* %p, align 2
+define void @test_maximum(ptr %p) #0 {
+ %a = load half, ptr %p, align 2
%c = fcmp ugt half %a, 1.0
%r = select i1 %c, half %a, half 1.0
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -737,11 +737,11 @@ define void @test_maximum(half* %p) #0 {
; CHECK-NOVFP: and
; CHECK-NOVFP: bic
; CHECK-NOVFP: orr
-define void @test_copysign(half* %p, half* %q) #0 {
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
+define void @test_copysign(ptr %p, ptr %q) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
%r = call half @llvm.copysign.f16(half %a, half %b)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -753,10 +753,10 @@ define void @test_copysign(half* %p, half* %q) #0 {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl floorf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_floor(half* %p) {
- %a = load half, half* %p, align 2
+define void @test_floor(ptr %p) {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.floor.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -768,10 +768,10 @@ define void @test_floor(half* %p) {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl ceilf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_ceil(half* %p) {
- %a = load half, half* %p, align 2
+define void @test_ceil(ptr %p) {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.ceil.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -783,10 +783,10 @@ define void @test_ceil(half* %p) {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl truncf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_trunc(half* %p) {
- %a = load half, half* %p, align 2
+define void @test_trunc(ptr %p) {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.trunc.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -798,10 +798,10 @@ define void @test_trunc(half* %p) {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl rintf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_rint(half* %p) {
- %a = load half, half* %p, align 2
+define void @test_rint(ptr %p) {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.rint.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -813,10 +813,10 @@ define void @test_rint(half* %p) {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl nearbyintf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_nearbyint(half* %p) {
- %a = load half, half* %p, align 2
+define void @test_nearbyint(ptr %p) {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.nearbyint.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -828,10 +828,10 @@ define void @test_nearbyint(half* %p) {
; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl roundf
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_round(half* %p) {
- %a = load half, half* %p, align 2
+define void @test_round(ptr %p) {
+ %a = load half, ptr %p, align 2
%r = call half @llvm.round.f16(half %a)
- store half %r, half* %p
+ store half %r, ptr %p
ret void
}
@@ -848,12 +848,12 @@ define void @test_round(half* %p) {
; CHECK-LIBCALL-VFP: vmla.f32
; CHECK-NOVFP: bl __aeabi_fmul
; CHECK-LIBCALL: bl __aeabi_f2h
-define void @test_fmuladd(half* %p, half* %q, half* %r) #0 {
- %a = load half, half* %p, align 2
- %b = load half, half* %q, align 2
- %c = load half, half* %r, align 2
+define void @test_fmuladd(ptr %p, ptr %q, ptr %r) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load half, ptr %q, align 2
+ %c = load half, ptr %r, align 2
%v = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
- store half %v, half* %p
+ store half %v, ptr %p
ret void
}
@@ -895,11 +895,11 @@ define void @test_fmuladd(half* %p, half* %q, half* %r) #0 {
; CHECK-NOVFP-DAG: strh
; CHECK-ALL: add sp, sp, #8
-define void @test_insertelement(half* %p, <4 x half>* %q, i32 %i) #0 {
- %a = load half, half* %p, align 2
- %b = load <4 x half>, <4 x half>* %q, align 8
+define void @test_insertelement(ptr %p, ptr %q, i32 %i) #0 {
+ %a = load half, ptr %p, align 2
+ %b = load <4 x half>, ptr %q, align 8
%c = insertelement <4 x half> %b, half %a, i32 %i
- store <4 x half> %c, <4 x half>* %q
+ store <4 x half> %c, ptr %q
ret void
}
@@ -922,10 +922,10 @@ define void @test_insertelement(half* %p, <4 x half>* %q, i32 %i) #0 {
; CHECK-NOVFP: ldrh
; CHECK-NOVFP: strh
; CHECK-NOVFP: ldrh
-define void @test_extractelement(half* %p, <4 x half>* %q, i32 %i) #0 {
- %a = load <4 x half>, <4 x half>* %q, align 8
+define void @test_extractelement(ptr %p, ptr %q, i32 %i) #0 {
+ %a = load <4 x half>, ptr %q, align 8
%b = extractelement <4 x half> %a, i32 %i
- store half %b, half* %p
+ store half %b, ptr %p
ret void
}
@@ -938,11 +938,11 @@ define void @test_extractelement(half* %p, <4 x half>* %q, i32 %i) #0 {
; CHECK-ALL-DAG: ldrh
; CHECK-ALL-DAG: strh
; CHECK-ALL-DAG: str
-define void @test_insertvalue(%struct.dummy* %p, half* %q) {
- %a = load %struct.dummy, %struct.dummy* %p
- %b = load half, half* %q
+define void @test_insertvalue(ptr %p, ptr %q) {
+ %a = load %struct.dummy, ptr %p
+ %b = load half, ptr %q
%c = insertvalue %struct.dummy %a, half %b, 1
- store %struct.dummy %c, %struct.dummy* %p
+ store %struct.dummy %c, ptr %p
ret void
}
@@ -950,10 +950,10 @@ define void @test_insertvalue(%struct.dummy* %p, half* %q) {
; CHECK-ALL: .fnstart
; CHECK-ALL: ldrh
; CHECK-ALL: strh
-define void @test_extractvalue(%struct.dummy* %p, half* %q) {
- %a = load %struct.dummy, %struct.dummy* %p
+define void @test_extractvalue(ptr %p, ptr %q) {
+ %a = load %struct.dummy, ptr %p
%b = extractvalue %struct.dummy %a, 1
- store half %b, half* %q
+ store half %b, ptr %q
ret void
}
@@ -961,8 +961,8 @@ define void @test_extractvalue(%struct.dummy* %p, half* %q) {
; CHECK-VFP-LIBCALL: bl __aeabi_h2f
; CHECK-NOVFP-DAG: ldr
; CHECK-NOVFP-DAG: ldrh
-define %struct.dummy @test_struct_return(%struct.dummy* %p) {
- %a = load %struct.dummy, %struct.dummy* %p
+define %struct.dummy @test_struct_return(ptr %p) {
+ %a = load %struct.dummy, ptr %p
ret %struct.dummy %a
}
diff --git a/llvm/test/CodeGen/ARM/fp16-v3.ll b/llvm/test/CodeGen/ARM/fp16-v3.ll
index 085503e80c7f2..522cb129b5df1 100644
--- a/llvm/test/CodeGen/ARM/fp16-v3.ll
+++ b/llvm/test/CodeGen/ARM/fp16-v3.ll
@@ -17,22 +17,22 @@ target triple = "armv7a--none-eabi"
; CHECK-DAG: vmov [[DREG:d[0-9]+]], [[RREG3]], [[RREG2]]
; CHECK-DAG: vst1.32 {[[DREG]][0]}, [r0:32]
; CHECK-NEXT: bx lr
-define void @test_vec3(<3 x half>* %arr, i32 %i) #0 {
+define void @test_vec3(ptr %arr, i32 %i) #0 {
%H = sitofp i32 %i to half
%S = fadd half %H, 0xH4A00
%1 = insertelement <3 x half> undef, half %S, i32 0
%2 = insertelement <3 x half> %1, half %S, i32 1
%3 = insertelement <3 x half> %2, half %S, i32 2
- store <3 x half> %3, <3 x half>* %arr, align 8
+ store <3 x half> %3, ptr %arr, align 8
ret void
}
; CHECK-LABEL: test_bitcast:
; CHECK: pkhbt
; CHECK: uxth
-define void @test_bitcast(<3 x half> %inp, <3 x i16>* %arr) #0 {
+define void @test_bitcast(<3 x half> %inp, ptr %arr) #0 {
%bc = bitcast <3 x half> %inp to <3 x i16>
- store <3 x i16> %bc, <3 x i16>* %arr, align 8
+ store <3 x i16> %bc, ptr %arr, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fp16-vld.ll b/llvm/test/CodeGen/ARM/fp16-vld.ll
index 5052b99e6c9da..549546e37fc82 100644
--- a/llvm/test/CodeGen/ARM/fp16-vld.ll
+++ b/llvm/test/CodeGen/ARM/fp16-vld.ll
@@ -3,7 +3,7 @@
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv8.2a-arm-unknown-eabihf"
-define dso_local void @vec8(half* nocapture readonly %V, i32 %N) local_unnamed_addr #0 {
+define dso_local void @vec8(ptr nocapture readonly %V, i32 %N) local_unnamed_addr #0 {
; CHECK: .LBB0_1:
; CHECK-NEXT: vld1.16 {d16, d17}, [r0]!
; CHECK-NEXT: subs r1, r1, #8
@@ -13,9 +13,8 @@ entry:
vector.body:
%index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
- %0 = getelementptr inbounds half, half* %V, i32 %index
- %1 = bitcast half* %0 to <8 x half>*
- %wide.load = load volatile <8 x half>, <8 x half>* %1, align 2
+ %0 = getelementptr inbounds half, ptr %V, i32 %index
+ %wide.load = load volatile <8 x half>, ptr %0, align 2
%index.next = add i32 %index, 8
%cmp = icmp eq i32 %index.next, %N
br i1 %cmp, label %byeblock, label %vector.body
@@ -24,7 +23,7 @@ byeblock:
ret void
}
-define dso_local void @vec4(half* nocapture readonly %V, i32 %N) local_unnamed_addr #0 {
+define dso_local void @vec4(ptr nocapture readonly %V, i32 %N) local_unnamed_addr #0 {
; CHECK: .LBB1_1:
; CHECK-NEXT: vld1.16 {d16}, [r0]!
; CHECK-NEXT: subs r1, r1, #4
@@ -34,9 +33,8 @@ entry:
vector.body:
%index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
- %0 = getelementptr inbounds half, half* %V, i32 %index
- %1 = bitcast half* %0 to <4 x half>*
- %wide.load = load volatile <4 x half>, <4 x half>* %1, align 2
+ %0 = getelementptr inbounds half, ptr %V, i32 %index
+ %wide.load = load volatile <4 x half>, ptr %0, align 2
%index.next = add i32 %index, 4
%cmp = icmp eq i32 %index.next, %N
br i1 %cmp, label %byeblock, label %vector.body
diff --git a/llvm/test/CodeGen/ARM/fp16-vldlane-vstlane.ll b/llvm/test/CodeGen/ARM/fp16-vldlane-vstlane.ll
index 2a7358323af71..0cdff23841475 100644
--- a/llvm/test/CodeGen/ARM/fp16-vldlane-vstlane.ll
+++ b/llvm/test/CodeGen/ARM/fp16-vldlane-vstlane.ll
@@ -1,56 +1,56 @@
; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=hard -O1 < %s | FileCheck %s
; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=soft -O1 < %s | FileCheck %s
-define <4 x half> @vld1d_lane_f16(half* %pa, <4 x half> %v4) nounwind {
+define <4 x half> @vld1d_lane_f16(ptr %pa, <4 x half> %v4) nounwind {
; CHECK-LABEL: vld1d_lane_f16:
; CHECK: vld1.16 {d{{[0-9]+}}[3]}, [r0:16]
entry:
- %a = load half, half* %pa
+ %a = load half, ptr %pa
%res = insertelement <4 x half> %v4, half %a, i32 3
ret <4 x half> %res
}
-define <8 x half> @vld1q_lane_f16_1(half* %pa, <8 x half> %v8) nounwind {
+define <8 x half> @vld1q_lane_f16_1(ptr %pa, <8 x half> %v8) nounwind {
; CHECK-LABEL: vld1q_lane_f16_1:
; CHECK: vld1.16 {d{{[0-9]+}}[1]}, [r0:16]
entry:
- %a = load half, half* %pa
+ %a = load half, ptr %pa
%res = insertelement <8 x half> %v8, half %a, i32 1
ret <8 x half> %res
}
-define <8 x half> @vld1q_lane_f16_7(half* %pa, <8 x half> %v8) nounwind {
+define <8 x half> @vld1q_lane_f16_7(ptr %pa, <8 x half> %v8) nounwind {
; CHECK-LABEL: vld1q_lane_f16_7:
; CHECK: vld1.16 {d{{[0-9]+}}[3]}, [r0:16]
entry:
- %a = load half, half* %pa
+ %a = load half, ptr %pa
%res = insertelement <8 x half> %v8, half %a, i32 7
ret <8 x half> %res
}
-define void @vst1d_lane_f16(half* %pa, <4 x half> %v4) nounwind {
+define void @vst1d_lane_f16(ptr %pa, <4 x half> %v4) nounwind {
; CHECK-LABEL: vst1d_lane_f16:
; CHECK: vst1.16 {d{{[0-9]+}}[3]}, [r0:16]
entry:
%a = extractelement <4 x half> %v4, i32 3
- store half %a, half* %pa
+ store half %a, ptr %pa
ret void
}
-define void @vst1q_lane_f16_7(half* %pa, <8 x half> %v8) nounwind {
+define void @vst1q_lane_f16_7(ptr %pa, <8 x half> %v8) nounwind {
; CHECK-LABEL: vst1q_lane_f16_7:
; CHECK: vst1.16 {d{{[0-9]+}}[3]}, [r0:16]
entry:
%a = extractelement <8 x half> %v8, i32 7
- store half %a, half* %pa
+ store half %a, ptr %pa
ret void
}
-define void @vst1q_lane_f16_1(half* %pa, <8 x half> %v8) nounwind {
+define void @vst1q_lane_f16_1(ptr %pa, <8 x half> %v8) nounwind {
; CHECK-LABEL: vst1q_lane_f16_1:
; CHECK: vst1.16 {d{{[0-9]+}}[1]}, [r0:16]
entry:
%a = extractelement <8 x half> %v8, i32 1
- store half %a, half* %pa
+ store half %a, ptr %pa
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fp16.ll b/llvm/test/CodeGen/ARM/fp16.ll
index 04e02bfd493dd..dc35fa34f42c1 100644
--- a/llvm/test/CodeGen/ARM/fp16.ll
+++ b/llvm/test/CodeGen/ARM/fp16.ll
@@ -23,8 +23,8 @@ target triple = "armv7---eabihf"
define void @foo() nounwind {
; CHECK-LABEL: foo:
entry:
- %0 = load i16, i16* @x, align 2
- %1 = load i16, i16* @y, align 2
+ %0 = load i16, ptr @x, align 2
+ %1 = load i16, ptr @y, align 2
%2 = tail call float @llvm.convert.from.fp16.f32(i16 %0)
; CHECK-HARDFLOAT-EABI: __aeabi_h2f
; CHECK-HARDFLOAT-GNU: __gnu_h2f_ieee
@@ -47,7 +47,7 @@ entry:
; CHECK-ARMV8: vcvtb.f16.f32
; CHECK-SOFTFLOAT-EABI: __aeabi_f2h
; CHECK-SOFTFLOAT-GNU: __gnu_f2h_ieee
- store i16 %5, i16* @x, align 2
+ store i16 %5, ptr @x, align 2
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fpclamptosat.ll b/llvm/test/CodeGen/ARM/fpclamptosat.ll
index 18fa1ad2f1323..91c1a21964309 100644
--- a/llvm/test/CodeGen/ARM/fpclamptosat.ll
+++ b/llvm/test/CodeGen/ARM/fpclamptosat.ll
@@ -4865,7 +4865,7 @@ entry:
}
-define void @unroll_maxmin(i32* nocapture %0, float* nocapture readonly %1, i32 %2) {
+define void @unroll_maxmin(ptr nocapture %0, ptr nocapture readonly %1, i32 %2) {
; SOFT-LABEL: unroll_maxmin:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
@@ -5035,8 +5035,8 @@ define void @unroll_maxmin(i32* nocapture %0, float* nocapture readonly %1, i32
5: ; preds = %5, %3
%6 = phi i32 [ 0, %3 ], [ %28, %5 ]
- %7 = getelementptr inbounds float, float* %1, i32 %6
- %8 = load float, float* %7, align 4
+ %7 = getelementptr inbounds float, ptr %1, i32 %6
+ %8 = load float, ptr %7, align 4
%9 = fmul float %8, 0x41E0000000000000
%10 = fptosi float %9 to i64
%11 = icmp slt i64 %10, 2147483647
@@ -5044,11 +5044,11 @@ define void @unroll_maxmin(i32* nocapture %0, float* nocapture readonly %1, i32
%13 = icmp sgt i64 %12, -2147483648
%14 = select i1 %13, i64 %12, i64 -2147483648
%15 = trunc i64 %14 to i32
- %16 = getelementptr inbounds i32, i32* %0, i32 %6
- store i32 %15, i32* %16, align 4
+ %16 = getelementptr inbounds i32, ptr %0, i32 %6
+ store i32 %15, ptr %16, align 4
%17 = or i32 %6, 1
- %18 = getelementptr inbounds float, float* %1, i32 %17
- %19 = load float, float* %18, align 4
+ %18 = getelementptr inbounds float, ptr %1, i32 %17
+ %19 = load float, ptr %18, align 4
%20 = fmul float %19, 0x41E0000000000000
%21 = fptosi float %20 to i64
%22 = icmp slt i64 %21, 2147483647
@@ -5056,14 +5056,14 @@ define void @unroll_maxmin(i32* nocapture %0, float* nocapture readonly %1, i32
%24 = icmp sgt i64 %23, -2147483648
%25 = select i1 %24, i64 %23, i64 -2147483648
%26 = trunc i64 %25 to i32
- %27 = getelementptr inbounds i32, i32* %0, i32 %17
- store i32 %26, i32* %27, align 4
+ %27 = getelementptr inbounds i32, ptr %0, i32 %17
+ store i32 %26, ptr %27, align 4
%28 = add nuw nsw i32 %6, 2
%29 = icmp eq i32 %28, 1024
br i1 %29, label %4, label %5
}
-define void @unroll_minmax(i32* nocapture %0, float* nocapture readonly %1, i32 %2) {
+define void @unroll_minmax(ptr nocapture %0, ptr nocapture readonly %1, i32 %2) {
; SOFT-LABEL: unroll_minmax:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
@@ -5231,8 +5231,8 @@ define void @unroll_minmax(i32* nocapture %0, float* nocapture readonly %1, i32
5: ; preds = %5, %3
%6 = phi i32 [ 0, %3 ], [ %28, %5 ]
- %7 = getelementptr inbounds float, float* %1, i32 %6
- %8 = load float, float* %7, align 4
+ %7 = getelementptr inbounds float, ptr %1, i32 %6
+ %8 = load float, ptr %7, align 4
%9 = fmul float %8, 0x41E0000000000000
%10 = fptosi float %9 to i64
%11 = icmp sgt i64 %10, -2147483648
@@ -5240,11 +5240,11 @@ define void @unroll_minmax(i32* nocapture %0, float* nocapture readonly %1, i32
%13 = icmp slt i64 %12, 2147483647
%14 = select i1 %13, i64 %12, i64 2147483647
%15 = trunc i64 %14 to i32
- %16 = getelementptr inbounds i32, i32* %0, i32 %6
- store i32 %15, i32* %16, align 4
+ %16 = getelementptr inbounds i32, ptr %0, i32 %6
+ store i32 %15, ptr %16, align 4
%17 = or i32 %6, 1
- %18 = getelementptr inbounds float, float* %1, i32 %17
- %19 = load float, float* %18, align 4
+ %18 = getelementptr inbounds float, ptr %1, i32 %17
+ %19 = load float, ptr %18, align 4
%20 = fmul float %19, 0x41E0000000000000
%21 = fptosi float %20 to i64
%22 = icmp sgt i64 %21, -2147483648
@@ -5252,8 +5252,8 @@ define void @unroll_minmax(i32* nocapture %0, float* nocapture readonly %1, i32
%24 = icmp slt i64 %23, 2147483647
%25 = select i1 %24, i64 %23, i64 2147483647
%26 = trunc i64 %25 to i32
- %27 = getelementptr inbounds i32, i32* %0, i32 %17
- store i32 %26, i32* %27, align 4
+ %27 = getelementptr inbounds i32, ptr %0, i32 %17
+ store i32 %26, ptr %27, align 4
%28 = add nuw nsw i32 %6, 2
%29 = icmp eq i32 %28, 1024
br i1 %29, label %4, label %5
diff --git a/llvm/test/CodeGen/ARM/fpcmp-opt.ll b/llvm/test/CodeGen/ARM/fpcmp-opt.ll
index a828541094507..447e470b2363a 100644
--- a/llvm/test/CodeGen/ARM/fpcmp-opt.ll
+++ b/llvm/test/CodeGen/ARM/fpcmp-opt.ll
@@ -5,7 +5,7 @@
; rdar://10964603
; Disable this optimization unless we know one of them is zero.
-define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
+define arm_apcscc i32 @t1(ptr %a, ptr %b) nounwind {
entry:
; CHECK-LABEL: t1:
; CHECK: vldr [[S0:s[0-9]+]],
@@ -13,8 +13,8 @@ entry:
; CHECK: vcmp.f32 [[S1]], [[S0]]
; CHECK: vmrs APSR_nzcv, fpscr
; CHECK: beq
- %0 = load float, float* %a
- %1 = load float, float* %b
+ %0 = load float, ptr %a
+ %1 = load float, ptr %b
%2 = fcmp une float %0, %1
br i1 %2, label %bb1, label %bb2
@@ -29,7 +29,7 @@ bb2:
; If one side is zero, the other size sign bit is masked off to allow
; +0.0 == -0.0
-define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
+define arm_apcscc i32 @t2(ptr %a, ptr %b) nounwind {
entry:
; CHECK-LABEL: t2:
; CHECK-NOT: vldr
@@ -41,7 +41,7 @@ entry:
; CHECK-NOT: vcmp.f32
; CHECK-NOT: vmrs
; CHECK: bne
- %0 = load double, double* %a
+ %0 = load double, ptr %a
%1 = fcmp oeq double %0, 0.000000e+00
br i1 %1, label %bb1, label %bb2
@@ -54,7 +54,7 @@ bb2:
ret i32 %3
}
-define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
+define arm_apcscc i32 @t3(ptr %a, ptr %b) nounwind {
entry:
; CHECK-LABEL: t3:
; CHECK-NOT: vldr
@@ -64,7 +64,7 @@ entry:
; CHECK-NOT: vcmp.f32
; CHECK-NOT: vmrs
; CHECK: bne
- %0 = load float, float* %a
+ %0 = load float, ptr %a
%1 = fcmp oeq float %0, 0.000000e+00
br i1 %1, label %bb1, label %bb2
diff --git a/llvm/test/CodeGen/ARM/fpmem.ll b/llvm/test/CodeGen/ARM/fpmem.ll
index 23fbea911e5e1..44abbd2e99283 100644
--- a/llvm/test/CodeGen/ARM/fpmem.ll
+++ b/llvm/test/CodeGen/ARM/fpmem.ll
@@ -6,36 +6,36 @@ define float @f1(float %a) {
ret float 0.000000e+00
}
-define float @f2(float* %v, float %u) {
+define float @f2(ptr %v, float %u) {
; CHECK-LABEL: f2:
; CHECK: vldr{{.*}}[
- %tmp = load float, float* %v ; <float> [#uses=1]
+ %tmp = load float, ptr %v ; <float> [#uses=1]
%tmp1 = fadd float %tmp, %u ; <float> [#uses=1]
ret float %tmp1
}
-define float @f2offset(float* %v, float %u) {
+define float @f2offset(ptr %v, float %u) {
; CHECK-LABEL: f2offset:
; CHECK: vldr{{.*}}, #4]
- %addr = getelementptr float, float* %v, i32 1
- %tmp = load float, float* %addr
+ %addr = getelementptr float, ptr %v, i32 1
+ %tmp = load float, ptr %addr
%tmp1 = fadd float %tmp, %u
ret float %tmp1
}
-define float @f2noffset(float* %v, float %u) {
+define float @f2noffset(ptr %v, float %u) {
; CHECK-LABEL: f2noffset:
; CHECK: vldr{{.*}}, #-4]
- %addr = getelementptr float, float* %v, i32 -1
- %tmp = load float, float* %addr
+ %addr = getelementptr float, ptr %v, i32 -1
+ %tmp = load float, ptr %addr
%tmp1 = fadd float %tmp, %u
ret float %tmp1
}
-define void @f3(float %a, float %b, float* %v) {
+define void @f3(float %a, float %b, ptr %v) {
; CHECK-LABEL: f3:
; CHECK: vstr{{.*}}[
%tmp = fadd float %a, %b ; <float> [#uses=1]
- store float %tmp, float* %v
+ store float %tmp, ptr %v
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fpscr-intrinsics.ll b/llvm/test/CodeGen/ARM/fpscr-intrinsics.ll
index 5cefc6255b051..02455f97dd090 100644
--- a/llvm/test/CodeGen/ARM/fpscr-intrinsics.ll
+++ b/llvm/test/CodeGen/ARM/fpscr-intrinsics.ll
@@ -12,7 +12,7 @@ entry:
br i1 %tobool, label %if.then, label %if.end
if.then: ; preds = %entry
- store double 5.000000e-01, double* @a, align 8
+ store double 5.000000e-01, ptr @a, align 8
br label %if.end
if.end: ; preds = %if.then, %entry
@@ -20,17 +20,17 @@ if.end: ; preds = %if.then, %entry
}
; Function Attrs: nounwind
-define void @fn1(i32* nocapture %p) local_unnamed_addr {
+define void @fn1(ptr nocapture %p) local_unnamed_addr {
entry:
; CHECK: vmrs r{{[0-9]+}}, fpscr
%0 = tail call i32 @llvm.arm.get.fpscr()
- store i32 %0, i32* %p, align 4
+ store i32 %0, ptr %p, align 4
; CHECK: vmsr fpscr, r{{[0-9]+}}
tail call void @llvm.arm.set.fpscr(i32 1)
; CHECK: vmrs r{{[0-9]+}}, fpscr
%1 = tail call i32 @llvm.arm.get.fpscr()
- %arrayidx1 = getelementptr inbounds i32, i32* %p, i32 1
- store i32 %1, i32* %arrayidx1, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %p, i32 1
+ store i32 %1, ptr %arrayidx1, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fptoi-sat-store.ll b/llvm/test/CodeGen/ARM/fptoi-sat-store.ll
index b007115130b99..67edf9855f372 100644
--- a/llvm/test/CodeGen/ARM/fptoi-sat-store.ll
+++ b/llvm/test/CodeGen/ARM/fptoi-sat-store.ll
@@ -8,7 +8,7 @@ declare i32 @llvm.fptosi.sat.i32.f32(float)
declare i32 @llvm.fptoui.sat.i32.f64(double)
declare i32 @llvm.fptoui.sat.i32.f32(float)
-define void @test_signed_i32_f32(i32* %d, float %f) nounwind {
+define void @test_signed_i32_f32(ptr %d, float %f) nounwind {
; SOFT-LABEL: test_signed_i32_f32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
@@ -66,11 +66,11 @@ define void @test_signed_i32_f32(i32* %d, float %f) nounwind {
; VFP-NEXT: vstr s0, [r0]
; VFP-NEXT: bx lr
%r = call i32 @llvm.fptosi.sat.i32.f32(float %f)
- store i32 %r, i32* %d, align 4
+ store i32 %r, ptr %d, align 4
ret void
}
-define void @test_signed_i32_f64(i32* %d, double %f) nounwind {
+define void @test_signed_i32_f64(ptr %d, double %f) nounwind {
; SOFT-LABEL: test_signed_i32_f64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
@@ -150,11 +150,11 @@ define void @test_signed_i32_f64(i32* %d, double %f) nounwind {
; FP16-NEXT: vstr s0, [r0]
; FP16-NEXT: bx lr
%r = call i32 @llvm.fptosi.sat.i32.f64(double %f)
- store i32 %r, i32* %d, align 4
+ store i32 %r, ptr %d, align 4
ret void
}
-define void @test_unsigned_i32_f32(i32* %d, float %f) nounwind {
+define void @test_unsigned_i32_f32(ptr %d, float %f) nounwind {
; SOFT-LABEL: test_unsigned_i32_f32:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
@@ -200,11 +200,11 @@ define void @test_unsigned_i32_f32(i32* %d, float %f) nounwind {
; VFP-NEXT: vstr s0, [r0]
; VFP-NEXT: bx lr
%r = call i32 @llvm.fptoui.sat.i32.f32(float %f)
- store i32 %r, i32* %d, align 4
+ store i32 %r, ptr %d, align 4
ret void
}
-define void @test_unsigned_i32_f64(i32* %d, double %f) nounwind {
+define void @test_unsigned_i32_f64(ptr %d, double %f) nounwind {
; SOFT-LABEL: test_unsigned_i32_f64:
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
@@ -266,6 +266,6 @@ define void @test_unsigned_i32_f64(i32* %d, double %f) nounwind {
; FP16-NEXT: vstr s0, [r0]
; FP16-NEXT: bx lr
%r = call i32 @llvm.fptoui.sat.i32.f64(double %f)
- store i32 %r, i32* %d, align 4
+ store i32 %r, ptr %d, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fptoint.ll b/llvm/test/CodeGen/ARM/fptoint.ll
index 6cbb30b23fbeb..6db1095d259c2 100644
--- a/llvm/test/CodeGen/ARM/fptoint.ll
+++ b/llvm/test/CodeGen/ARM/fptoint.ll
@@ -1,47 +1,47 @@
; RUN: llc -mtriple=arm-eabi -arm-atomic-cfg-tidy=0 -mattr=+v6,+vfp2 %s -o - | FileCheck %s
- at i = weak global i32 0 ; <i32*> [#uses=2]
- at u = weak global i32 0 ; <i32*> [#uses=2]
+ at i = weak global i32 0 ; <ptr> [#uses=2]
+ at u = weak global i32 0 ; <ptr> [#uses=2]
-define i32 @foo1(float *%x) {
- %tmp1 = load float, float* %x
+define i32 @foo1(ptr %x) {
+ %tmp1 = load float, ptr %x
%tmp2 = bitcast float %tmp1 to i32
ret i32 %tmp2
}
-define i64 @foo2(double *%x) {
- %tmp1 = load double, double* %x
+define i64 @foo2(ptr %x) {
+ %tmp1 = load double, ptr %x
%tmp2 = bitcast double %tmp1 to i64
ret i64 %tmp2
}
define void @foo5(float %x) {
%tmp1 = fptosi float %x to i32
- store i32 %tmp1, i32* @i
+ store i32 %tmp1, ptr @i
ret void
}
define void @foo6(float %x) {
%tmp1 = fptoui float %x to i32
- store i32 %tmp1, i32* @u
+ store i32 %tmp1, ptr @u
ret void
}
define void @foo7(double %x) {
%tmp1 = fptosi double %x to i32
- store i32 %tmp1, i32* @i
+ store i32 %tmp1, ptr @i
ret void
}
define void @foo8(double %x) {
%tmp1 = fptoui double %x to i32
- store i32 %tmp1, i32* @u
+ store i32 %tmp1, ptr @u
ret void
}
define void @foo9(double %x) {
%tmp = fptoui double %x to i16
- store i16 %tmp, i16* null
+ store i16 %tmp, ptr null
ret void
}
; CHECK-LABEL: foo9:
diff --git a/llvm/test/CodeGen/ARM/frame-chain.ll b/llvm/test/CodeGen/ARM/frame-chain.ll
index c6fede461919f..a0f03e51b4613 100644
--- a/llvm/test/CodeGen/ARM/frame-chain.ll
+++ b/llvm/test/CodeGen/ARM/frame-chain.ll
@@ -48,8 +48,8 @@ define dso_local noundef i32 @leaf(i32 noundef %0) {
; LEAF-NOFP-AAPCS-NEXT: add sp, sp, #4
; LEAF-NOFP-AAPCS-NEXT: mov pc, lr
%2 = alloca i32, align 4
- store i32 %0, i32* %2, align 4
- %3 = load i32, i32* %2, align 4
+ store i32 %0, ptr %2, align 4
+ %3 = load i32, ptr %2, align 4
%4 = add nsw i32 %3, 4
ret i32 %4
}
@@ -111,14 +111,14 @@ define dso_local noundef i32 @non_leaf(i32 noundef %0) {
; NOFP-AAPCS-NEXT: pop {r11, lr}
; NOFP-AAPCS-NEXT: mov pc, lr
%2 = alloca i32, align 4
- store i32 %0, i32* %2, align 4
- %3 = load i32, i32* %2, align 4
+ store i32 %0, ptr %2, align 4
+ %3 = load i32, ptr %2, align 4
%4 = call noundef i32 @leaf(i32 noundef %3)
%5 = add nsw i32 %4, 1
ret i32 %5
}
-declare i8* @llvm.stacksave()
+declare ptr @llvm.stacksave()
define dso_local void @required_fp(i32 %0, i32 %1) {
; LEAF-FP-LABEL: required_fp:
; LEAF-FP: @ %bb.0:
@@ -209,15 +209,15 @@ define dso_local void @required_fp(i32 %0, i32 %1) {
; LEAF-NOFP-AAPCS-NEXT: mov pc, lr
%3 = alloca i32, align 4
%4 = alloca i32, align 4
- %5 = alloca i8*, align 8
+ %5 = alloca ptr, align 8
%6 = alloca i64, align 8
- store i32 %0, i32* %3, align 4
- store i32 %1, i32* %4, align 4
- %7 = load i32, i32* %3, align 4
+ store i32 %0, ptr %3, align 4
+ store i32 %1, ptr %4, align 4
+ %7 = load i32, ptr %3, align 4
%8 = zext i32 %7 to i64
- %9 = call i8* @llvm.stacksave()
- store i8* %9, i8** %5, align 8
+ %9 = call ptr @llvm.stacksave()
+ store ptr %9, ptr %5, align 8
%10 = alloca i32, i64 %8, align 4
- store i64 %8, i64* %6, align 8
+ store i64 %8, ptr %6, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/frame-register.ll b/llvm/test/CodeGen/ARM/frame-register.ll
index c008b21a2909c..0e2f140d66b3d 100644
--- a/llvm/test/CodeGen/ARM/frame-register.ll
+++ b/llvm/test/CodeGen/ARM/frame-register.ll
@@ -16,13 +16,13 @@ define i32 @calleer(i32 %i) {
entry:
%i.addr = alloca i32, align 4
%j = alloca i32, align 4
- store i32 %i, i32* %i.addr, align 4
- %0 = load i32, i32* %i.addr, align 4
+ store i32 %i, ptr %i.addr, align 4
+ %0 = load i32, ptr %i.addr, align 4
%add = add nsw i32 %0, 1
- store i32 %add, i32* %j, align 4
- %1 = load i32, i32* %j, align 4
+ store i32 %add, ptr %j, align 4
+ %1 = load i32, ptr %j, align 4
call void @callee(i32 %1)
- %2 = load i32, i32* %j, align 4
+ %2 = load i32, ptr %j, align 4
%add1 = add nsw i32 %2, 1
ret i32 %add1
}
diff --git a/llvm/test/CodeGen/ARM/func-argpassing-endian.ll b/llvm/test/CodeGen/ARM/func-argpassing-endian.ll
index dc50ce6eb77b5..8e93f3a20d1c2 100644
--- a/llvm/test/CodeGen/ARM/func-argpassing-endian.ll
+++ b/llvm/test/CodeGen/ARM/func-argpassing-endian.ll
@@ -20,7 +20,7 @@ define void @arg_longint( i64 %val ) {
; CHECK-BE-NEXT: str r1, [r0]
; CHECK-BE-NEXT: bx lr
%tmp = trunc i64 %val to i32
- store i32 %tmp, i32* @var32
+ store i32 %tmp, ptr @var32
ret void
}
@@ -31,7 +31,7 @@ define void @arg_double( double %val ) {
; CHECK-NEXT: movt r2, :upper16:vardouble
; CHECK-NEXT: strd r0, r1, [r2]
; CHECK-NEXT: bx lr
- store double %val, double* @vardouble
+ store double %val, ptr @vardouble
ret void
}
@@ -53,7 +53,7 @@ define void @arg_v4i32(<4 x i32> %vec ) {
; CHECK-BE-NEXT: vst1.32 {d16[0]}, [r0:32]
; CHECK-BE-NEXT: bx lr
%tmp = extractelement <4 x i32> %vec, i32 0
- store i32 %tmp, i32* @var32
+ store i32 %tmp, ptr @var32
ret void
}
@@ -65,7 +65,7 @@ define void @arg_v2f64(<2 x double> %vec ) {
; CHECK-NEXT: strd r0, r1, [r2]
; CHECK-NEXT: bx lr
%tmp = extractelement <2 x double> %vec, i32 0
- store double %tmp, double* @vardouble
+ store double %tmp, ptr @vardouble
ret void
}
@@ -211,7 +211,7 @@ define void @caller_return_longint() {
; CHECK-BE-NEXT: pop {r11, pc}
%val = call i64 @return_longint()
%tmp = trunc i64 %val to i32
- store i32 %tmp, i32* @var32
+ store i32 %tmp, ptr @var32
ret void
}
@@ -253,7 +253,7 @@ define void @caller_return_double() {
; CHECK-BE-NEXT: .long 1374389535
%val = call double @return_double( )
%tmp = fadd double %val, 3.14
- store double %tmp, double* @vardouble
+ store double %tmp, ptr @vardouble
ret void
}
@@ -269,6 +269,6 @@ define void @caller_return_v2f64() {
; CHECK-NEXT: pop {r11, pc}
%val = call <2 x double> @return_v2f64( )
%tmp = extractelement <2 x double> %val, i32 0
- store double %tmp, double* @vardouble
+ store double %tmp, ptr @vardouble
ret void
}
diff --git a/llvm/test/CodeGen/ARM/fusedMAC.ll b/llvm/test/CodeGen/ARM/fusedMAC.ll
index 493e71c9f6273..a6a02f689f3a9 100644
--- a/llvm/test/CodeGen/ARM/fusedMAC.ll
+++ b/llvm/test/CodeGen/ARM/fusedMAC.ll
@@ -150,10 +150,10 @@ entry:
ret double %tmp2
}
-define arm_aapcs_vfpcc float @test_fnms_f32(float %a, float %b, float* %c) nounwind readnone ssp {
+define arm_aapcs_vfpcc float @test_fnms_f32(float %a, float %b, ptr %c) nounwind readnone ssp {
; CHECK: test_fnms_f32
; CHECK: vfnms.f32
- %tmp1 = load float, float* %c, align 4
+ %tmp1 = load float, ptr %c, align 4
%tmp2 = fsub float -0.0, %tmp1
%tmp3 = tail call float @llvm.fma.f32(float %a, float %b, float %tmp2) nounwind readnone
ret float %tmp3
@@ -216,13 +216,13 @@ define arm_aapcs_vfpcc float @test_fma_canonicalize(float %a, float %b) nounwind
}
; Check that very wide vector fma's can be split into legal fma's.
-define arm_aapcs_vfpcc void @test_fma_v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float>* %p) nounwind readnone ssp {
+define arm_aapcs_vfpcc void @test_fma_v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c, ptr %p) nounwind readnone ssp {
; CHECK: test_fma_v8f32
; CHECK: vfma.f32
; CHECK: vfma.f32
entry:
%call = tail call <8 x float> @llvm.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c) nounwind readnone
- store <8 x float> %call, <8 x float>* %p, align 16
+ store <8 x float> %call, ptr %p, align 16
ret void
}
diff --git a/llvm/test/CodeGen/ARM/gep-imm.ll b/llvm/test/CodeGen/ARM/gep-imm.ll
index 20218725f8a40..d7a048bd38913 100644
--- a/llvm/test/CodeGen/ARM/gep-imm.ll
+++ b/llvm/test/CodeGen/ARM/gep-imm.ll
@@ -3,7 +3,7 @@
; RUN: llc -mtriple=thumbv7m-none-eabi < %s | FileCheck %s --check-prefix=CHECKV7M
; RUN: llc -mtriple=thumbv7a-none-eabi < %s | FileCheck %s --check-prefix=CHECKV7A
-define void @small(i32 %a, i32 %b, i32 *%c, i32* %d) {
+define void @small(i32 %a, i32 %b, ptr %c, ptr %d) {
; CHECKV6M-LABEL: small:
; CHECKV6M: @ %bb.0: @ %entry
; CHECKV6M-NEXT: str r1, [r3, #120]
@@ -25,16 +25,16 @@ define void @small(i32 %a, i32 %b, i32 *%c, i32* %d) {
; CHECKV7A-NEXT: str r0, [r2, #80]
; CHECKV7A-NEXT: bx lr
entry:
- %arrayidx = getelementptr inbounds i32, i32* %d, i32 20
- store i32 %a, i32* %arrayidx, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %d, i32 30
- store i32 %b, i32* %arrayidx1, align 4
- %arrayidx2 = getelementptr inbounds i32, i32* %c, i32 20
- store i32 %a, i32* %arrayidx2, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %d, i32 20
+ store i32 %a, ptr %arrayidx, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %d, i32 30
+ store i32 %b, ptr %arrayidx1, align 4
+ %arrayidx2 = getelementptr inbounds i32, ptr %c, i32 20
+ store i32 %a, ptr %arrayidx2, align 4
ret void
}
-define void @large(i32 %a, i32 %b, i32 *%c, i32* %d) {
+define void @large(i32 %a, i32 %b, ptr %c, ptr %d) {
; CHECKV6M-LABEL: large:
; CHECKV6M: @ %bb.0: @ %entry
; CHECKV6M-NEXT: .save {r4, lr}
@@ -69,16 +69,16 @@ define void @large(i32 %a, i32 %b, i32 *%c, i32* %d) {
; CHECKV7A-NEXT: str.w r0, [r2, r12]
; CHECKV7A-NEXT: bx lr
entry:
- %arrayidx = getelementptr inbounds i32, i32* %d, i32 2000
- store i32 %a, i32* %arrayidx, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %d, i32 3000
- store i32 %b, i32* %arrayidx1, align 4
- %arrayidx2 = getelementptr inbounds i32, i32* %c, i32 2000
- store i32 %a, i32* %arrayidx2, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %d, i32 2000
+ store i32 %a, ptr %arrayidx, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %d, i32 3000
+ store i32 %b, ptr %arrayidx1, align 4
+ %arrayidx2 = getelementptr inbounds i32, ptr %c, i32 2000
+ store i32 %a, ptr %arrayidx2, align 4
ret void
}
-define void @huge(i32 %a, i32 %b, i32 *%c, i32* %d) {
+define void @huge(i32 %a, i32 %b, ptr %c, ptr %d) {
; CHECKV6M-LABEL: huge:
; CHECKV6M: @ %bb.0: @ %entry
; CHECKV6M-NEXT: .save {r4, lr}
@@ -118,11 +118,11 @@ define void @huge(i32 %a, i32 %b, i32 *%c, i32* %d) {
; CHECKV7A-NEXT: str r0, [r2, r1]
; CHECKV7A-NEXT: bx lr
entry:
- %arrayidx = getelementptr inbounds i32, i32* %d, i32 200000
- store i32 %a, i32* %arrayidx, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %d, i32 300000
- store i32 %b, i32* %arrayidx1, align 4
- %arrayidx2 = getelementptr inbounds i32, i32* %c, i32 200000
- store i32 %a, i32* %arrayidx2, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %d, i32 200000
+ store i32 %a, ptr %arrayidx, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %d, i32 300000
+ store i32 %b, ptr %arrayidx1, align 4
+ %arrayidx2 = getelementptr inbounds i32, ptr %c, i32 200000
+ store i32 %a, ptr %arrayidx2, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/gep-optimization.ll b/llvm/test/CodeGen/ARM/gep-optimization.ll
index ce5af66d56cea..b33a9ba333d88 100644
--- a/llvm/test/CodeGen/ARM/gep-optimization.ll
+++ b/llvm/test/CodeGen/ARM/gep-optimization.ll
@@ -11,22 +11,22 @@
; CHECK-AT2: mla r0, r1, [[REG1]], r0
; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
; CHECK-T1: adds r0, r0, [[REG2]]
-define i32* @calc_1d(i32* %p, i32 %n) {
+define ptr @calc_1d(ptr %p, i32 %n) {
entry:
%mul = mul nsw i32 %n, 21
- %add.ptr = getelementptr inbounds i32, i32* %p, i32 %mul
- ret i32* %add.ptr
+ %add.ptr = getelementptr inbounds i32, ptr %p, i32 %mul
+ ret ptr %add.ptr
}
; CHECK-LABEL: load_1d:
; CHECK: mov{{s?}} [[REG1:r[0-9]+]], #84
; CHECK: mul{{s?}} [[REG2:r[0-9]+]],{{( r1,)?}} [[REG1]]{{(, r1)?}}
; CHECK: ldr r0, [r0, [[REG2]]]
-define i32 @load_1d(i32* %p, i32 %n) #1 {
+define i32 @load_1d(ptr %p, i32 %n) #1 {
entry:
%mul = mul nsw i32 %n, 21
- %arrayidx = getelementptr inbounds i32, i32* %p, i32 %mul
- %0 = load i32, i32* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %p, i32 %mul
+ %0 = load i32, ptr %arrayidx, align 4
ret i32 %0
}
@@ -35,22 +35,22 @@ entry:
; CHECK-AT2: mla r0, r1, [[REG1]], r0
; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
; CHECK-T1: adds r0, r0, [[REG2]]
-define i32* @calc_2d_a([100 x i32]* %p, i32 %n) {
+define ptr @calc_2d_a(ptr %p, i32 %n) {
entry:
%mul = mul nsw i32 %n, 21
- %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32]* %p, i32 0, i32 %mul
- ret i32* %arrayidx1
+ %arrayidx1 = getelementptr inbounds [100 x i32], ptr %p, i32 0, i32 %mul
+ ret ptr %arrayidx1
}
; CHECK-LABEL: load_2d_a:
; CHECK: mov{{s?}} [[REG1:r[0-9]+]], #84
; CHECK: mul{{s?}} [[REG2:r[0-9]+]],{{( r1,)?}} [[REG1]]{{(, r1)?}}
; CHECK: ldr r0, [r0, [[REG2]]]
-define i32 @load_2d_a([100 x i32]* %p, i32 %n) #1 {
+define i32 @load_2d_a(ptr %p, i32 %n) #1 {
entry:
%mul = mul nsw i32 %n, 21
- %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32]* %p, i32 0, i32 %mul
- %0 = load i32, i32* %arrayidx1, align 4
+ %arrayidx1 = getelementptr inbounds [100 x i32], ptr %p, i32 0, i32 %mul
+ %0 = load i32, ptr %arrayidx1, align 4
ret i32 %0
}
@@ -59,19 +59,19 @@ entry:
; CHECK-AT2: mla r0, r1, [[REG1]], r0
; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
; CHECK-T1: adds r0, r0, [[REG2]]
-define i32* @calc_2d_b([21 x i32]* %p, i32 %n) {
+define ptr @calc_2d_b(ptr %p, i32 %n) {
entry:
- %arrayidx1 = getelementptr inbounds [21 x i32], [21 x i32]* %p, i32 %n, i32 0
- ret i32* %arrayidx1
+ %arrayidx1 = getelementptr inbounds [21 x i32], ptr %p, i32 %n, i32 0
+ ret ptr %arrayidx1
}
; CHECK-LABEL: load_2d_b:
; CHECK: mov{{s?}} [[REG1:r[0-9]+]], #84
; CHECK: mul{{s?}} [[REG2:r[0-9]+]],{{( r1,)?}} [[REG1]]{{(, r1)?}}
; CHECK: ldr r0, [r0, [[REG2]]]
-define i32 @load_2d_b([21 x i32]* %p, i32 %n) {
+define i32 @load_2d_b(ptr %p, i32 %n) {
entry:
- %arrayidx1 = getelementptr inbounds [21 x i32], [21 x i32]* %p, i32 %n, i32 0
- %0 = load i32, i32* %arrayidx1, align 4
+ %arrayidx1 = getelementptr inbounds [21 x i32], ptr %p, i32 %n, i32 0
+ %0 = load i32, ptr %arrayidx1, align 4
ret i32 %0
}
diff --git a/llvm/test/CodeGen/ARM/ghc-tcreturn-lowered.ll b/llvm/test/CodeGen/ARM/ghc-tcreturn-lowered.ll
index f34f8f1a66c13..46729730898cf 100644
--- a/llvm/test/CodeGen/ARM/ghc-tcreturn-lowered.ll
+++ b/llvm/test/CodeGen/ARM/ghc-tcreturn-lowered.ll
@@ -10,12 +10,12 @@ define ghccc void @test_direct_tail() {
ret void
}
- at ind_func = global void()* zeroinitializer
+ at ind_func = global ptr zeroinitializer
define ghccc void @test_indirect_tail() {
; CHECK-LABEL: test_indirect_tail:
; CHECK: bx {{r[0-9]+}}
- %func = load void()*, void()** @ind_func
+ %func = load ptr, ptr @ind_func
tail call ghccc void() %func()
ret void
}
diff --git a/llvm/test/CodeGen/ARM/global-merge-1.ll b/llvm/test/CodeGen/ARM/global-merge-1.ll
index 68b346ec9f010..46e9d969bd6ac 100644
--- a/llvm/test/CodeGen/ARM/global-merge-1.ll
+++ b/llvm/test/CodeGen/ARM/global-merge-1.ll
@@ -31,26 +31,26 @@ target triple = "thumbv7-apple-ios3.0.0"
; Function Attrs: nounwind ssp
define internal void @initialize() #0 {
- %1 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
- store i32 %1, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 0), align 4, !tbaa !1
- %2 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
- store i32 %2, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 0), align 4, !tbaa !1
- %3 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
- store i32 %3, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 1), align 4, !tbaa !1
- %4 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
- store i32 %4, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 1), align 4, !tbaa !1
- %5 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
- store i32 %5, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 2), align 4, !tbaa !1
- %6 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
- store i32 %6, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 2), align 4, !tbaa !1
- %7 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
- store i32 %7, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 3), align 4, !tbaa !1
- %8 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
- store i32 %8, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 3), align 4, !tbaa !1
- %9 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
- store i32 %9, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 4), align 4, !tbaa !1
- %10 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
- store i32 %10, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 4), align 4, !tbaa !1
+ %1 = tail call i32 @calc() #3
+ store i32 %1, ptr @bar, align 4, !tbaa !1
+ %2 = tail call i32 @calc() #3
+ store i32 %2, ptr @baz, align 4, !tbaa !1
+ %3 = tail call i32 @calc() #3
+ store i32 %3, ptr getelementptr inbounds ([5 x i32], ptr @bar, i32 0, i32 1), align 4, !tbaa !1
+ %4 = tail call i32 @calc() #3
+ store i32 %4, ptr getelementptr inbounds ([5 x i32], ptr @baz, i32 0, i32 1), align 4, !tbaa !1
+ %5 = tail call i32 @calc() #3
+ store i32 %5, ptr getelementptr inbounds ([5 x i32], ptr @bar, i32 0, i32 2), align 4, !tbaa !1
+ %6 = tail call i32 @calc() #3
+ store i32 %6, ptr getelementptr inbounds ([5 x i32], ptr @baz, i32 0, i32 2), align 4, !tbaa !1
+ %7 = tail call i32 @calc() #3
+ store i32 %7, ptr getelementptr inbounds ([5 x i32], ptr @bar, i32 0, i32 3), align 4, !tbaa !1
+ %8 = tail call i32 @calc() #3
+ store i32 %8, ptr getelementptr inbounds ([5 x i32], ptr @baz, i32 0, i32 3), align 4, !tbaa !1
+ %9 = tail call i32 @calc() #3
+ store i32 %9, ptr getelementptr inbounds ([5 x i32], ptr @bar, i32 0, i32 4), align 4, !tbaa !1
+ %10 = tail call i32 @calc() #3
+ store i32 %10, ptr getelementptr inbounds ([5 x i32], ptr @baz, i32 0, i32 4), align 4, !tbaa !1
ret void
}
@@ -58,20 +58,20 @@ declare i32 @calc(...) #1
; Function Attrs: nounwind ssp
define internal void @calculate() #0 {
- %1 = load <4 x i32>, <4 x i32>* bitcast ([5 x i32]* @bar to <4 x i32>*), align 4
- %2 = load <4 x i32>, <4 x i32>* bitcast ([5 x i32]* @baz to <4 x i32>*), align 4
+ %1 = load <4 x i32>, ptr @bar, align 4
+ %2 = load <4 x i32>, ptr @baz, align 4
%3 = mul <4 x i32> %2, %1
- store <4 x i32> %3, <4 x i32>* bitcast ([5 x i32]* @foo to <4 x i32>*), align 4
- %4 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 4), align 4, !tbaa !1
- %5 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 4), align 4, !tbaa !1
+ store <4 x i32> %3, ptr @foo, align 4
+ %4 = load i32, ptr getelementptr inbounds ([5 x i32], ptr @bar, i32 0, i32 4), align 4, !tbaa !1
+ %5 = load i32, ptr getelementptr inbounds ([5 x i32], ptr @baz, i32 0, i32 4), align 4, !tbaa !1
%6 = mul nsw i32 %5, %4
- store i32 %6, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i32 0, i32 4), align 4, !tbaa !1
+ store i32 %6, ptr getelementptr inbounds ([5 x i32], ptr @foo, i32 0, i32 4), align 4, !tbaa !1
ret void
}
; Function Attrs: nounwind readnone ssp
-define internal i32* @returnFoo() #2 {
- ret i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i32 0, i32 0)
+define internal ptr @returnFoo() #2 {
+ ret ptr @foo
}
attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/CodeGen/ARM/global-merge-alignment.ll b/llvm/test/CodeGen/ARM/global-merge-alignment.ll
index 2e4ee065bfc8d..c828dbc9edabf 100644
--- a/llvm/test/CodeGen/ARM/global-merge-alignment.ll
+++ b/llvm/test/CodeGen/ARM/global-merge-alignment.ll
@@ -3,7 +3,7 @@
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv7em-arm-none-eabi"
- at f = dso_local local_unnamed_addr global [4 x i32*] zeroinitializer, align 4
+ at f = dso_local local_unnamed_addr global [4 x ptr] zeroinitializer, align 4
@d = dso_local local_unnamed_addr global i64 0, align 8
;CHECK: .section .bss..L_MergedGlobals,"aw",%nobits
@@ -14,9 +14,9 @@ target triple = "thumbv7em-arm-none-eabi"
define dso_local i32 @func_1() {
- %1 = load i64, i64* @d, align 8
- %2 = load i32*, i32** getelementptr inbounds ([4 x i32*], [4 x i32*]* @f, i32 0, i32 0), align 4
- %3 = load i32, i32* %2, align 4
+ %1 = load i64, ptr @d, align 8
+ %2 = load ptr, ptr @f, align 4
+ %3 = load i32, ptr %2, align 4
%4 = trunc i64 %1 to i32
%5 = add i32 %3, %4
ret i32 %5
diff --git a/llvm/test/CodeGen/ARM/global-merge-dllexport.ll b/llvm/test/CodeGen/ARM/global-merge-dllexport.ll
index 8d027f290a0e2..89e8a859b9393 100644
--- a/llvm/test/CodeGen/ARM/global-merge-dllexport.ll
+++ b/llvm/test/CodeGen/ARM/global-merge-dllexport.ll
@@ -7,8 +7,8 @@ define void @f1(i32 %a1, i32 %a2) {
; CHECK: f1:
; CHECK: movw [[REG1:r[0-9]+]], :lower16:.L_MergedGlobals
; CHECK: movt [[REG1]], :upper16:.L_MergedGlobals
- store i32 %a1, i32* @x, align 4
- store i32 %a2, i32* @y, align 4
+ store i32 %a1, ptr @x, align 4
+ store i32 %a2, ptr @y, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/global-merge-external-2.ll b/llvm/test/CodeGen/ARM/global-merge-external-2.ll
index e0945e91b4d06..602533e045e0b 100644
--- a/llvm/test/CodeGen/ARM/global-merge-external-2.ll
+++ b/llvm/test/CodeGen/ARM/global-merge-external-2.ll
@@ -18,8 +18,8 @@ define dso_local void @f1(i32 %a1, i32 %a2) {
;CHECK-WIN32: f1:
;CHECK-WIN32: movw [[REG1:r[0-9]+]], :lower16:.L_MergedGlobals
;CHECK-WIN32: movt [[REG1]], :upper16:.L_MergedGlobals
- store i32 %a1, i32* @x, align 4
- store i32 %a2, i32* @y, align 4
+ store i32 %a1, ptr @x, align 4
+ store i32 %a2, ptr @y, align 4
ret void
}
@@ -37,8 +37,8 @@ define dso_local void @g1(i32 %a1, i32 %a2) {
;CHECK-WIN32: movt [[REG2]], :upper16:z
;CHECK-WIN32: movw [[REG3:r[0-9]+]], :lower16:.L_MergedGlobals
;CHECK-WIN32: movt [[REG3]], :upper16:.L_MergedGlobals
- store i32 %a1, i32* @y, align 4
- store i32 %a2, i32* @z, align 4
+ store i32 %a1, ptr @y, align 4
+ store i32 %a2, ptr @z, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/global-merge-external.ll b/llvm/test/CodeGen/ARM/global-merge-external.ll
index f6796a2b05584..364659b36bb9a 100644
--- a/llvm/test/CodeGen/ARM/global-merge-external.ll
+++ b/llvm/test/CodeGen/ARM/global-merge-external.ll
@@ -18,8 +18,8 @@ define dso_local void @f1(i32 %a1, i32 %a2) {
;CHECK-WIN32: f1:
;CHECK-WIN32: movw [[REG1:r[0-9]+]], :lower16:.L_MergedGlobals
;CHECK-WIN32: movt [[REG1]], :upper16:.L_MergedGlobals
- store i32 %a1, i32* @x, align 4
- store i32 %a2, i32* @y, align 4
+ store i32 %a1, ptr @x, align 4
+ store i32 %a2, ptr @y, align 4
ret void
}
@@ -32,8 +32,8 @@ define dso_local void @g1(i32 %a1, i32 %a2) {
;CHECK-WIN32: g1:
;CHECK-WIN32: movw [[REG2:r[0-9]+]], :lower16:.L_MergedGlobals
;CHECK-WIN32: movt [[REG2]], :upper16:.L_MergedGlobals
- store i32 %a1, i32* @y, align 4
- store i32 %a2, i32* @z, align 4
+ store i32 %a1, ptr @y, align 4
+ store i32 %a2, ptr @z, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/global-merge.ll b/llvm/test/CodeGen/ARM/global-merge.ll
index b02832234a726..d206cde4b40d7 100644
--- a/llvm/test/CodeGen/ARM/global-merge.ll
+++ b/llvm/test/CodeGen/ARM/global-merge.ll
@@ -9,28 +9,28 @@
; Global variables marked with "used" attribute must be kept
; CHECK: g8
@g8 = internal global i32 0
- at llvm.used = appending global [1 x i8*] [i8* bitcast (i32* @g8 to i8*)], section "llvm.metadata"
+ at llvm.used = appending global [1 x ptr] [ptr @g8], section "llvm.metadata"
; Global used in landing pad instruction must be kept
; CHECK: ZTIi
- at _ZTIi = internal global i8* null
+ at _ZTIi = internal global ptr null
-define i32 @_Z9exceptioni(i32 %arg) personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
+define i32 @_Z9exceptioni(i32 %arg) personality ptr @__gxx_personality_sj0 {
bb:
%tmp = invoke i32 @_Z14throwSomethingi(i32 %arg)
to label %bb9 unwind label %bb1
bb1: ; preds = %bb
- %tmp2 = landingpad { i8*, i32 }
- catch i8* bitcast (i8** @_ZTIi to i8*)
- %tmp3 = extractvalue { i8*, i32 } %tmp2, 1
- %tmp4 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*))
+ %tmp2 = landingpad { ptr, i32 }
+ catch ptr @_ZTIi
+ %tmp3 = extractvalue { ptr, i32 } %tmp2, 1
+ %tmp4 = tail call i32 @llvm.eh.typeid.for(ptr @_ZTIi)
%tmp5 = icmp eq i32 %tmp3, %tmp4
br i1 %tmp5, label %bb6, label %bb10
bb6: ; preds = %bb1
- %tmp7 = extractvalue { i8*, i32 } %tmp2, 0
- %tmp8 = tail call i8* @__cxa_begin_catch(i8* %tmp7)
+ %tmp7 = extractvalue { ptr, i32 } %tmp2, 0
+ %tmp8 = tail call ptr @__cxa_begin_catch(ptr %tmp7)
tail call void @__cxa_end_catch()
br label %bb9
@@ -39,16 +39,16 @@ bb9: ; preds = %bb6, %bb
ret i32 %res.0
bb10: ; preds = %bb1
- resume { i8*, i32 } %tmp2
+ resume { ptr, i32 } %tmp2
}
declare i32 @_Z14throwSomethingi(i32)
declare i32 @__gxx_personality_sj0(...)
-declare i32 @llvm.eh.typeid.for(i8*)
+declare i32 @llvm.eh.typeid.for(ptr)
-declare i8* @__cxa_begin_catch(i8*)
+declare ptr @__cxa_begin_catch(ptr)
declare void @__cxa_end_catch()
diff --git a/llvm/test/CodeGen/ARM/globals.ll b/llvm/test/CodeGen/ARM/globals.ll
index 399d5208ae2cd..3a36d16d53501 100644
--- a/llvm/test/CodeGen/ARM/globals.ll
+++ b/llvm/test/CodeGen/ARM/globals.ll
@@ -6,7 +6,7 @@
@G = external global i32
define i32 @test1() {
- %tmp = load i32, i32* @G
+ %tmp = load i32, ptr @G
ret i32 %tmp
}
diff --git a/llvm/test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll b/llvm/test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll
index 00027119f9e00..3513693ee7975 100644
--- a/llvm/test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll
+++ b/llvm/test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll
@@ -5,26 +5,26 @@
; generate thumb instructions. Previously we were inserting an ARM
; STMIA which happened to have the same encoding.
-define void @foo(i64* %addr) {
- %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
- %val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
- %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
- %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
- %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
- %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
- %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
+define void @foo(ptr %addr) {
+ %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)
+ %val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)
+ %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)
+ %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)
+ %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)
+ %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)
+ %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)
; Make sure we are actually creating the Thumb versions of the spill
; instructions.
; CHECK: t2STRDi8
; CHECK: t2LDRDi8
- store volatile i64 %val1, i64* %addr
- store volatile i64 %val2, i64* %addr
- store volatile i64 %val3, i64* %addr
- store volatile i64 %val4, i64* %addr
- store volatile i64 %val5, i64* %addr
- store volatile i64 %val6, i64* %addr
- store volatile i64 %val7, i64* %addr
+ store volatile i64 %val1, ptr %addr
+ store volatile i64 %val2, ptr %addr
+ store volatile i64 %val3, ptr %addr
+ store volatile i64 %val4, ptr %addr
+ store volatile i64 %val5, ptr %addr
+ store volatile i64 %val6, ptr %addr
+ store volatile i64 %val7, ptr %addr
ret void
}
diff --git a/llvm/test/CodeGen/ARM/gpr-paired-spill.ll b/llvm/test/CodeGen/ARM/gpr-paired-spill.ll
index 797b147d5d016..9ea0d38651d88 100644
--- a/llvm/test/CodeGen/ARM/gpr-paired-spill.ll
+++ b/llvm/test/CodeGen/ARM/gpr-paired-spill.ll
@@ -2,14 +2,14 @@
; RUN: llc -mtriple=armv4-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITHOUT-LDRD
; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITH-LDRD
-define void @foo(i64* %addr) {
- %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
- %val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
- %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
- %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
- %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
- %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
- %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
+define void @foo(ptr %addr) {
+ %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)
+ %val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)
+ %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)
+ %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)
+ %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)
+ %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)
+ %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)
; Key point is that enough 64-bit paired GPR values are live that
; one of them has to be spilled. This used to cause an abort because
@@ -33,12 +33,12 @@ define void @foo(i64* %addr) {
; CHECK-WITHOUT-LDRD-DAG: ldm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
; CHECK-WITHOUT-LDRD-DAG: ldm sp, {r{{[0-9]+}}, r{{[0-9]+}}}
- store volatile i64 %val1, i64* %addr
- store volatile i64 %val2, i64* %addr
- store volatile i64 %val3, i64* %addr
- store volatile i64 %val4, i64* %addr
- store volatile i64 %val5, i64* %addr
- store volatile i64 %val6, i64* %addr
- store volatile i64 %val7, i64* %addr
+ store volatile i64 %val1, ptr %addr
+ store volatile i64 %val2, ptr %addr
+ store volatile i64 %val3, ptr %addr
+ store volatile i64 %val4, ptr %addr
+ store volatile i64 %val5, ptr %addr
+ store volatile i64 %val6, ptr %addr
+ store volatile i64 %val7, ptr %addr
ret void
}
diff --git a/llvm/test/CodeGen/ARM/gv-stubs-crash.ll b/llvm/test/CodeGen/ARM/gv-stubs-crash.ll
index b1e6e4f7b1787..0bdfeca0eb625 100644
--- a/llvm/test/CodeGen/ARM/gv-stubs-crash.ll
+++ b/llvm/test/CodeGen/ARM/gv-stubs-crash.ll
@@ -1,36 +1,36 @@
; RUN: llc < %s -mtriple=thumbv7-apple-ios -relocation-model=pic
; <rdar://problem/10336715>
- at Exn = external hidden unnamed_addr constant { i8*, i8* }
+ at Exn = external hidden unnamed_addr constant { ptr, ptr }
-define hidden void @func(i32* %this, i32* %e) optsize align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
- %e.ld = load i32, i32* %e, align 4
- %inv = invoke zeroext i1 @func2(i32* %this, i32 %e.ld) optsize
+define hidden void @func(ptr %this, ptr %e) optsize align 2 personality ptr @__gxx_personality_sj0 {
+ %e.ld = load i32, ptr %e, align 4
+ %inv = invoke zeroext i1 @func2(ptr %this, i32 %e.ld) optsize
to label %ret unwind label %lpad
ret:
ret void
lpad:
- %lp = landingpad { i8*, i32 }
- catch i8* bitcast ({ i8*, i8* }* @Exn to i8*)
+ %lp = landingpad { ptr, i32 }
+ catch ptr @Exn
br label %.loopexit4
.loopexit4:
- %exn = call i8* @__cxa_allocate_exception(i32 8) nounwind
- call void @__cxa_throw(i8* %exn, i8* bitcast ({ i8*, i8* }* @Exn to i8*), i8* bitcast (void (i32*)* @dtor to i8*)) noreturn
+ %exn = call ptr @__cxa_allocate_exception(i32 8) nounwind
+ call void @__cxa_throw(ptr %exn, ptr @Exn, ptr @dtor) noreturn
unreachable
resume:
- resume { i8*, i32 } %lp
+ resume { ptr, i32 } %lp
}
-declare hidden zeroext i1 @func2(i32*, i32) optsize align 2
+declare hidden zeroext i1 @func2(ptr, i32) optsize align 2
-declare i8* @__cxa_allocate_exception(i32)
+declare ptr @__cxa_allocate_exception(i32)
declare i32 @__gxx_personality_sj0(...)
-declare void @dtor(i32*) optsize
+declare void @dtor(ptr) optsize
-declare void @__cxa_throw(i8*, i8*, i8*)
+declare void @__cxa_throw(ptr, ptr, ptr)
diff --git a/llvm/test/CodeGen/ARM/half.ll b/llvm/test/CodeGen/ARM/half.ll
index 21ac4f927c6ce..9b53dc77f2273 100644
--- a/llvm/test/CodeGen/ARM/half.ll
+++ b/llvm/test/CodeGen/ARM/half.ll
@@ -8,44 +8,44 @@
; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+mve.fp,+fp64 | FileCheck %s --check-prefix=CHECK-V8
; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-V8-SP
-define void @test_load_store(half* %in, half* %out) {
+define void @test_load_store(ptr %in, ptr %out) {
; CHECK-LABEL: test_load_store:
; CHECK: ldrh [[TMP:r[0-9]+]], [r0]
; CHECK: strh [[TMP]], [r1]
- %val = load half, half* %in
- store half %val, half* %out
+ %val = load half, ptr %in
+ store half %val, ptr %out
ret void
}
-define i16 @test_bitcast_from_half(half* %addr) {
+define i16 @test_bitcast_from_half(ptr %addr) {
; CHECK-LABEL: test_bitcast_from_half:
; CHECK: ldrh r0, [r0]
- %val = load half, half* %addr
+ %val = load half, ptr %addr
%val_int = bitcast half %val to i16
ret i16 %val_int
}
-define void @test_bitcast_to_half(half* %addr, i16 %in) {
+define void @test_bitcast_to_half(ptr %addr, i16 %in) {
; CHECK-LABEL: test_bitcast_to_half:
; CHECK: strh r1, [r0]
%val_fp = bitcast i16 %in to half
- store half %val_fp, half* %addr
+ store half %val_fp, ptr %addr
ret void
}
-define float @test_extend32(half* %addr) {
+define float @test_extend32(ptr %addr) {
; CHECK-LABEL: test_extend32:
; CHECK-OLD: b.w ___extendhfsf2
; CHECK-F16: vcvtb.f32.f16
; CHECK-V8: vcvtb.f32.f16
; CHECK-V8-SP: vcvtb.f32.f16
- %val16 = load half, half* %addr
+ %val16 = load half, ptr %addr
%val32 = fpext half %val16 to float
ret float %val32
}
-define double @test_extend64(half* %addr) {
+define double @test_extend64(ptr %addr) {
; CHECK-LABEL: test_extend64:
; CHECK-OLD: bl ___extendhfsf2
@@ -55,12 +55,12 @@ define double @test_extend64(half* %addr) {
; CHECK-V8: vcvtb.f64.f16
; CHECK-V8-SP: vcvtb.f32.f16
; CHECK-V8-SP: bl __aeabi_f2d
- %val16 = load half, half* %addr
+ %val16 = load half, ptr %addr
%val32 = fpext half %val16 to double
ret double %val32
}
-define void @test_trunc32(float %in, half* %addr) {
+define void @test_trunc32(float %in, ptr %addr) {
; CHECK-LABEL: test_trunc32:
; CHECK-OLD: bl ___truncsfhf2
@@ -68,11 +68,11 @@ define void @test_trunc32(float %in, half* %addr) {
; CHECK-V8: vcvtb.f16.f32
; CHECK-V8-SP: vcvtb.f16.f32
%val16 = fptrunc float %in to half
- store half %val16, half* %addr
+ store half %val16, ptr %addr
ret void
}
-define void @test_trunc64(double %in, half* %addr) {
+define void @test_trunc64(double %in, ptr %addr) {
; CHECK-LABEL: test_trunc64:
; CHECK-OLD: bl ___truncdfhf2
@@ -80,6 +80,6 @@ define void @test_trunc64(double %in, half* %addr) {
; CHECK-V8: vcvtb.f16.f64
; CHECK-V8-SP: bl __aeabi_d2h
%val16 = fptrunc double %in to half
- store half %val16, half* %addr
+ store half %val16, ptr %addr
ret void
}
diff --git a/llvm/test/CodeGen/ARM/hello.ll b/llvm/test/CodeGen/ARM/hello.ll
index 429a6b0efac65..09dd9205c8715 100644
--- a/llvm/test/CodeGen/ARM/hello.ll
+++ b/llvm/test/CodeGen/ARM/hello.ll
@@ -10,11 +10,11 @@
@str = internal constant [12 x i8] c"Hello World\00"
define i32 @main() "frame-pointer"="all" {
- %tmp = call i32 @puts( i8* getelementptr ([12 x i8], [12 x i8]* @str, i32 0, i64 0) ) ; <i32> [#uses=0]
+ %tmp = call i32 @puts( ptr @str ) ; <i32> [#uses=0]
ret i32 0
}
-declare i32 @puts(i8*)
+declare i32 @puts(ptr)
; CHECK-LABEL: main
; CHECK-NOT: mov
diff --git a/llvm/test/CodeGen/ARM/hidden-vis-2.ll b/llvm/test/CodeGen/ARM/hidden-vis-2.ll
index a104f354295d9..b642d5937c6d4 100644
--- a/llvm/test/CodeGen/ARM/hidden-vis-2.ll
+++ b/llvm/test/CodeGen/ARM/hidden-vis-2.ll
@@ -1,12 +1,12 @@
; RUN: llc < %s -relocation-model=dynamic-no-pic -mtriple=arm-apple-darwin | FileCheck %s
- at x = weak hidden global i32 0 ; <i32*> [#uses=1]
+ at x = weak hidden global i32 0 ; <ptr> [#uses=1]
define i32 @t() nounwind readonly {
entry:
; CHECK-LABEL: t:
; CHECK: ldr
; CHECK-NEXT: ldr
- %0 = load i32, i32* @x, align 4 ; <i32> [#uses=1]
+ %0 = load i32, ptr @x, align 4 ; <i32> [#uses=1]
ret i32 %0
}
diff --git a/llvm/test/CodeGen/ARM/hidden-vis-3.ll b/llvm/test/CodeGen/ARM/hidden-vis-3.ll
index 148502686a1a1..0a5f525eddb11 100644
--- a/llvm/test/CodeGen/ARM/hidden-vis-3.ll
+++ b/llvm/test/CodeGen/ARM/hidden-vis-3.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -relocation-model=dynamic-no-pic -mtriple=arm-apple-darwin9 | FileCheck %s
- at x = external hidden global i32 ; <i32*> [#uses=1]
- at y = extern_weak hidden global i32 ; <i32*> [#uses=1]
+ at x = external hidden global i32 ; <ptr> [#uses=1]
+ at y = extern_weak hidden global i32 ; <ptr> [#uses=1]
define i32 @t() nounwind readonly {
entry:
@@ -11,8 +11,8 @@ entry:
; CHECK: LCPI0_1:
; CHECK-NEXT: .long L_y$non_lazy_ptr
- %0 = load i32, i32* @x, align 4 ; <i32> [#uses=1]
- %1 = load i32, i32* @y, align 4 ; <i32> [#uses=1]
+ %0 = load i32, ptr @x, align 4 ; <i32> [#uses=1]
+ %1 = load i32, ptr @y, align 4 ; <i32> [#uses=1]
%2 = add i32 %1, %0 ; <i32> [#uses=1]
ret i32 %2
}
diff --git a/llvm/test/CodeGen/ARM/i64_volatile_load_store.ll b/llvm/test/CodeGen/ARM/i64_volatile_load_store.ll
index ae54256b7a285..590313431ac6b 100644
--- a/llvm/test/CodeGen/ARM/i64_volatile_load_store.ll
+++ b/llvm/test/CodeGen/ARM/i64_volatile_load_store.ll
@@ -24,8 +24,8 @@ entry:
; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], [[[ADDR0]], #4]
; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #4]
; CHECK-ARMV4T-NEXT: str [[R1]], [[[ADDR1]]]
- %0 = load volatile i64, i64* @x, align 8
- store volatile i64 %0, i64* @y, align 8
+ %0 = load volatile i64, ptr @x, align 8
+ store volatile i64 %0, ptr @y, align 8
ret void
}
@@ -48,8 +48,8 @@ entry:
; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], [[[ADDR0]]]
; CHECK-ARMV4T-NEXT: str [[R1]], [[[ADDR1]]]
; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #-4]
- %0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 -4) to i64*), align 8
- store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 -4) to i64*), align 8
+ %0 = load volatile i64, ptr getelementptr (i8, ptr @x, i32 -4), align 8
+ store volatile i64 %0, ptr getelementptr (i8, ptr @y, i32 -4), align 8
ret void
}
@@ -70,8 +70,8 @@ define void @test_offset_1() {
; CHECK-ARMV4T-NEXT: str [[R1]], [[[ADDR1]], #259]
; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #255]
entry:
- %0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 255) to i64*), align 8
- store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 255) to i64*), align 8
+ %0 = load volatile i64, ptr getelementptr (i8, ptr @x, i32 255), align 8
+ store volatile i64 %0, ptr getelementptr (i8, ptr @y, i32 255), align 8
ret void
}
@@ -96,8 +96,8 @@ define void @test_offset_2() {
; CHECK-ARMV4T-NEXT: str [[R1]], [[[ADDR1]], #260]
; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #256]
entry:
- %0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 256) to i64*), align 8
- store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 256) to i64*), align 8
+ %0 = load volatile i64, ptr getelementptr (i8, ptr @x, i32 256), align 8
+ store volatile i64 %0, ptr getelementptr (i8, ptr @y, i32 256), align 8
ret void
}
@@ -122,8 +122,8 @@ define void @test_offset_3() {
; CHECK-ARMV4T-NEXT: str [[R1]], [[[ADDR1]], #1024]
; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #1020]
entry:
- %0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 1020) to i64*), align 8
- store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 1020) to i64*), align 8
+ %0 = load volatile i64, ptr getelementptr (i8, ptr @x, i32 1020), align 8
+ store volatile i64 %0, ptr getelementptr (i8, ptr @y, i32 1020), align 8
ret void
}
@@ -150,8 +150,8 @@ define void @test_offset_4() {
; CHECK-ARMV4T-NEXT: str [[R1]], [[[ADDR1]], #1028]
; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #1024]
entry:
- %0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 1024) to i64*), align 8
- store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 1024) to i64*), align 8
+ %0 = load volatile i64, ptr getelementptr (i8, ptr @x, i32 1024), align 8
+ store volatile i64 %0, ptr getelementptr (i8, ptr @y, i32 1024), align 8
ret void
}
@@ -182,10 +182,10 @@ define i64 @test_stack() {
; CHECK-ARMV4T-NEXT: bx lr
entry:
%a = alloca [10 x i64], align 8
- %arrayidx = getelementptr inbounds [10 x i64], [10 x i64]* %a, i32 0, i32 1
- store volatile i64 1, i64* %arrayidx, align 8
- %arrayidx1 = getelementptr inbounds [10 x i64], [10 x i64]* %a, i32 0, i32 1
- %0 = load volatile i64, i64* %arrayidx1, align 8
+ %arrayidx = getelementptr inbounds [10 x i64], ptr %a, i32 0, i32 1
+ store volatile i64 1, ptr %arrayidx, align 8
+ %arrayidx1 = getelementptr inbounds [10 x i64], ptr %a, i32 0, i32 1
+ %0 = load volatile i64, ptr %arrayidx1, align 8
ret i64 %0
}
diff --git a/llvm/test/CodeGen/ARM/ifconv-kills.ll b/llvm/test/CodeGen/ARM/ifconv-kills.ll
index 3a458e4819367..886efeb48723a 100644
--- a/llvm/test/CodeGen/ARM/ifconv-kills.ll
+++ b/llvm/test/CodeGen/ARM/ifconv-kills.ll
@@ -2,23 +2,23 @@
declare i32 @f(i32 %p0, i32 %p1)
-define i32 @foo(i32* %ptr) {
+define i32 @foo(ptr %ptr) {
entry:
- %cmp = icmp ne i32* %ptr, null
+ %cmp = icmp ne ptr %ptr, null
br i1 %cmp, label %if.then, label %if.else
; present something which can be easily if-converted
if.then:
; %R0 should be killed here
- %valt = load i32, i32* %ptr, align 4
+ %valt = load i32, ptr %ptr, align 4
br label %return
if.else:
; %R0 should be killed here, however after if-conversion the %R0 kill
; has to be removed because if.then will follow after this and still
; read it.
- %addr = getelementptr inbounds i32, i32* %ptr, i32 4
- %vale = load i32, i32* %addr, align 4
+ %addr = getelementptr inbounds i32, ptr %ptr, i32 4
+ %vale = load i32, ptr %addr, align 4
br label %return
return:
diff --git a/llvm/test/CodeGen/ARM/ifconv-regmask.ll b/llvm/test/CodeGen/ARM/ifconv-regmask.ll
index 2144ca6e40749..6e4afd9202696 100644
--- a/llvm/test/CodeGen/ARM/ifconv-regmask.ll
+++ b/llvm/test/CodeGen/ARM/ifconv-regmask.ll
@@ -7,7 +7,7 @@
; Function Attrs: nounwind ssp
define i32 @sfu() {
entry:
- %bf.load = load i32, i32* getelementptr inbounds (%union.opcode, %union.opcode* @opcode, i32 0, i32 0), align 4
+ %bf.load = load i32, ptr @opcode, align 4
%bf.lshr = lshr i32 %bf.load, 26
%bf.clear = and i32 %bf.lshr, 7
switch i32 %bf.clear, label %return [
diff --git a/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll b/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
index 6e5db3ffa5c2b..d4dc75a8f8bce 100644
--- a/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
+++ b/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
@@ -6,10 +6,10 @@
%classK = type { i8, %classF }
%classF = type { i8 }
%classL = type { %classG, i32, i32 }
-%classG = type { %classL* }
+%classG = type { ptr }
%classM2 = type { %classL }
-define zeroext i1 @test(%classK* %this, %classL* nocapture readnone %p0, %classM2* nocapture readnone %p1, %classM2* nocapture readnone %p2, i32 %a0) align 2 {
+define zeroext i1 @test(ptr %this, ptr nocapture readnone %p0, ptr nocapture readnone %p1, ptr nocapture readnone %p2, i32 %a0) align 2 {
entry:
br i1 undef, label %for.end, label %for.body
@@ -27,7 +27,7 @@ for.body:
br i1 undef, label %for.cond.backedge, label %lor.lhs.false.i, !prof !1
for.cond.backedge:
- %tobool = icmp eq %classL* %p0, null
+ %tobool = icmp eq ptr %p0, null
br i1 %tobool, label %for.end, label %for.body
lor.lhs.false.i:
@@ -43,21 +43,21 @@ for.end:
br i1 %tobool.i.i9, label %if.else.i.i, label %if.then.i.i
if.then.i.i:
- store %classL* null, %classL** undef, align 4
+ store ptr null, ptr undef, align 4
br label %_ZN1M6spliceEv.exit
if.else.i.i:
- store %classL* null, %classL** null, align 4
+ store ptr null, ptr null, align 4
br label %_ZN1M6spliceEv.exit
_ZN1M6spliceEv.exit:
- %LIS = getelementptr inbounds %classK, %classK* %this, i32 0, i32 1
- call void @_ZN1F10handleMoveEb(%classF* %LIS, i1 zeroext false)
+ %LIS = getelementptr inbounds %classK, ptr %this, i32 0, i32 1
+ call void @_ZN1F10handleMoveEb(ptr %LIS, i1 zeroext false)
unreachable
}
-declare %classL* @_ZN1M1JI1LS1_EcvPS1_Ev(%classM2*)
-declare void @_ZN1F10handleMoveEb(%classF*, i1 zeroext)
+declare ptr @_ZN1M1JI1LS1_EcvPS1_Ev(ptr)
+declare void @_ZN1F10handleMoveEb(ptr, i1 zeroext)
declare void @_Z3fn1v()
!0 = !{!"clang version 3.5"}
diff --git a/llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll b/llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll
index 71dcb018b1803..f16668bd29f23 100644
--- a/llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll
+++ b/llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll
@@ -1,18 +1,18 @@
; RUN: llc < %s -mtriple=thumbv8 -stop-after=if-converter -arm-atomic-cfg-tidy=0 -arm-restrict-it | FileCheck %s
-%struct.S = type { i8* (i8*)*, [1 x i8] }
-define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly {
+%struct.S = type { ptr, [1 x i8] }
+define internal zeroext i8 @bar(ptr %x, ptr nocapture %y) nounwind readonly {
entry:
- %0 = getelementptr inbounds %struct.S, %struct.S* %x, i32 0, i32 1, i32 0
- %1 = load i8, i8* %0, align 1
+ %0 = getelementptr inbounds %struct.S, ptr %x, i32 0, i32 1, i32 0
+ %1 = load i8, ptr %0, align 1
%2 = zext i8 %1 to i32
%3 = and i32 %2, 112
%4 = icmp eq i32 %3, 0
br i1 %4, label %return, label %bb
bb:
- %5 = getelementptr inbounds %struct.S, %struct.S* %y, i32 0, i32 1, i32 0
- %6 = load i8, i8* %5, align 1
+ %5 = getelementptr inbounds %struct.S, ptr %y, i32 0, i32 1, i32 0
+ %6 = load i8, ptr %5, align 1
%7 = zext i8 %6 to i32
%8 = and i32 %7, 112
%9 = icmp eq i32 %8, 0
@@ -30,7 +30,7 @@ bb3:
br i1 %v11, label %bb4, label %return, !prof !1
bb4:
- %v12 = ptrtoint %struct.S* %x to i32
+ %v12 = ptrtoint ptr %x to i32
%phitmp = trunc i32 %v12 to i8
ret i8 %phitmp
diff --git a/llvm/test/CodeGen/ARM/ifcvt-dead-def.ll b/llvm/test/CodeGen/ARM/ifcvt-dead-def.ll
index fedbcfb09ebd8..747b071266139 100644
--- a/llvm/test/CodeGen/ARM/ifcvt-dead-def.ll
+++ b/llvm/test/CodeGen/ARM/ifcvt-dead-def.ll
@@ -19,25 +19,24 @@ target triple = "thumbv7-unknown-unknown"
; CHECK: ldrh
; Function Attrs: minsize nounwind optsize ssp
-define i32 @test(%struct.ref_s* %pref1, %struct.ref_s* %pref2, %struct.gs_color_s** %tmp152) #0 {
+define i32 @test(ptr %pref1, ptr %pref2, ptr %tmp152) #0 {
bb:
%nref = alloca %struct.ref_s, align 4
- %tmp46 = call %struct.ref_s* @name_string_ref(%struct.ref_s* %pref1, %struct.ref_s* %nref) #2
- %tmp153 = load %struct.gs_color_s*, %struct.gs_color_s** %tmp152, align 4
- %tmp154 = bitcast %struct.ref_s* %pref2 to %struct.gs_color_s**
- %tmp155 = load %struct.gs_color_s*, %struct.gs_color_s** %tmp154, align 4
- %tmp162 = getelementptr inbounds %struct.gs_color_s, %struct.gs_color_s* %tmp153, i32 0, i32 1
- %tmp163 = load i16, i16* %tmp162, align 2
- %tmp164 = getelementptr inbounds %struct.gs_color_s, %struct.gs_color_s* %tmp155, i32 0, i32 1
- %tmp165 = load i16, i16* %tmp164, align 2
+ %tmp46 = call ptr @name_string_ref(ptr %pref1, ptr %nref) #2
+ %tmp153 = load ptr, ptr %tmp152, align 4
+ %tmp155 = load ptr, ptr %pref2, align 4
+ %tmp162 = getelementptr inbounds %struct.gs_color_s, ptr %tmp153, i32 0, i32 1
+ %tmp163 = load i16, ptr %tmp162, align 2
+ %tmp164 = getelementptr inbounds %struct.gs_color_s, ptr %tmp155, i32 0, i32 1
+ %tmp165 = load i16, ptr %tmp164, align 2
%tmp166 = icmp eq i16 %tmp163, %tmp165
br i1 %tmp166, label %bb167, label %bb173
bb167: ; preds = %bb
- %tmp168 = getelementptr inbounds %struct.gs_color_s, %struct.gs_color_s* %tmp153, i32 0, i32 2
- %tmp169 = load i16, i16* %tmp168, align 2
- %tmp170 = getelementptr inbounds %struct.gs_color_s, %struct.gs_color_s* %tmp155, i32 0, i32 2
- %tmp171 = load i16, i16* %tmp170, align 2
+ %tmp168 = getelementptr inbounds %struct.gs_color_s, ptr %tmp153, i32 0, i32 2
+ %tmp169 = load i16, ptr %tmp168, align 2
+ %tmp170 = getelementptr inbounds %struct.gs_color_s, ptr %tmp155, i32 0, i32 2
+ %tmp171 = load i16, ptr %tmp170, align 2
%tmp172 = icmp eq i16 %tmp169, %tmp171
br label %bb173
@@ -48,7 +47,7 @@ bb173: ; preds = %bb167, %bb
}
; Function Attrs: minsize optsize
-declare %struct.ref_s* @name_string_ref(%struct.ref_s*, %struct.ref_s*) #1
+declare ptr @name_string_ref(ptr, ptr) #1
attributes #0 = { minsize nounwind optsize }
attributes #1 = { minsize optsize }
diff --git a/llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll b/llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll
index bffdf3c095100..1ee5f0e051a93 100644
--- a/llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll
+++ b/llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false -stop-after=if-converter | FileCheck --check-prefix=CHECK-PROB %s
declare i32 @foo(i32)
-declare i8* @bar(i32, i8*, i8*)
+declare ptr @bar(i32, ptr, ptr)
; Verify that we don't try to iteratively re-ifconvert a block with a
; (predicated) indirectbr terminator.
@@ -14,7 +14,7 @@ declare i8* @bar(i32, i8*, i8*)
; CHECK-PROB: bb.2{{[0-9a-zA-Z.]*}}:
; CHECK-PROB: successors: %bb.3(0x40000000), %bb.4(0x40000000)
-define i32 @test(i32 %a, i32 %a2, i32* %p, i32* %p2) "frame-pointer"="all" {
+define i32 @test(i32 %a, i32 %a2, ptr %p, ptr %p2) "frame-pointer"="all" {
; CHECK-LABEL: test:
; CHECK: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: add r7, sp, #12
@@ -69,22 +69,22 @@ define i32 @test(i32 %a, i32 %a2, i32* %p, i32* %p2) "frame-pointer"="all" {
; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
; CHECK-NEXT: .p2align 2
entry:
- %dst1 = call i8* @bar(i32 1, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2))
- %dst2 = call i8* @bar(i32 2, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2))
- %dst3 = call i8* @bar(i32 3, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2))
+ %dst1 = call ptr @bar(i32 1, ptr blockaddress(@test, %bb1), ptr blockaddress(@test, %bb2))
+ %dst2 = call ptr @bar(i32 2, ptr blockaddress(@test, %bb1), ptr blockaddress(@test, %bb2))
+ %dst3 = call ptr @bar(i32 3, ptr blockaddress(@test, %bb1), ptr blockaddress(@test, %bb2))
%cc1 = icmp eq i32 %a, 21
br i1 %cc1, label %cc1t, label %cc1f
cc1t:
- store i32 %a, i32* %p
- indirectbr i8* %dst3, [label %bb1, label %bb2]
+ store i32 %a, ptr %p
+ indirectbr ptr %dst3, [label %bb1, label %bb2]
cc1f:
%cc2 = icmp ne i32 %a2, 42
br i1 %cc2, label %cc2t, label %bb1
cc2t:
- store i32 %a, i32* %p2
- indirectbr i8* %dst1, [label %bb1, label %bb2]
+ store i32 %a, ptr %p2
+ indirectbr ptr %dst1, [label %bb1, label %bb2]
bb1:
%ret_bb1 = call i32 @foo(i32 1234)
diff --git a/llvm/test/CodeGen/ARM/ifcvt-regmask-noreturn.ll b/llvm/test/CodeGen/ARM/ifcvt-regmask-noreturn.ll
index a0a0bd60b6e6b..4dc71bc90dcdc 100644
--- a/llvm/test/CodeGen/ARM/ifcvt-regmask-noreturn.ll
+++ b/llvm/test/CodeGen/ARM/ifcvt-regmask-noreturn.ll
@@ -3,7 +3,7 @@
target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
target triple = "thumbv7s-apple-ios8.0.0"
- at debw = external global i8*, align 4
+ at debw = external global ptr, align 4
; This test ensures that the stack_chk call correctly puts implicit uses/defs for the registers
; live across it when if converting. This will be R0 which is passed to the call to free at the end
@@ -15,25 +15,25 @@ target triple = "thumbv7s-apple-ios8.0.0"
; CHECK: stack_chk_fail
; Function Attrs: ssp
-define void @test(i32 %argc, i8** nocapture readonly %argv, i32* %ptr, i32 %val) #0 {
+define void @test(i32 %argc, ptr nocapture readonly %argv, ptr %ptr, i32 %val) #0 {
entry:
%count.i = alloca [256 x i32], align 4
%cmp284.i = icmp eq i32 %val, 0
br i1 %cmp284.i, label %for.end31.i, label %for.body21.i
for.body21.i: ; preds = %entry
- %arrayidx23.i = getelementptr inbounds [256 x i32], [256 x i32]* %count.i, i32 0, i32 1
- %tmp20 = load i32, i32* %arrayidx23.i, align 4, !tbaa !0
- store i32 %tmp20, i32* %ptr, align 4, !tbaa !0
+ %arrayidx23.i = getelementptr inbounds [256 x i32], ptr %count.i, i32 0, i32 1
+ %tmp20 = load i32, ptr %arrayidx23.i, align 4, !tbaa !0
+ store i32 %tmp20, ptr %ptr, align 4, !tbaa !0
br label %for.end31.i
for.end31.i: ; preds = %for.body21.i, %entry
- %tmp21 = load i8*, i8** @debw, align 4, !tbaa !4
- tail call void @free(i8* %tmp21)
+ %tmp21 = load ptr, ptr @debw, align 4, !tbaa !4
+ tail call void @free(ptr %tmp21)
ret void
}
-declare void @free(i8* nocapture)
+declare void @free(ptr nocapture)
attributes #0 = { ssp "stack-protector-buffer-size"="8" }
diff --git a/llvm/test/CodeGen/ARM/ifcvt10.ll b/llvm/test/CodeGen/ARM/ifcvt10.ll
index 9da13557751b6..76ad456daa111 100644
--- a/llvm/test/CodeGen/ARM/ifcvt10.ll
+++ b/llvm/test/CodeGen/ARM/ifcvt10.ll
@@ -4,7 +4,7 @@
; micro-coded and would have long issue latency even if predicated on
; false predicate.
-define void @t(double %a, double %b, double %c, double %d, i32* nocapture %solutions, double* nocapture %x) nounwind "frame-pointer"="all" {
+define void @t(double %a, double %b, double %c, double %d, ptr nocapture %solutions, ptr nocapture %x) nounwind "frame-pointer"="all" {
entry:
; CHECK-LABEL: t:
; CHECK: vpop {d8}
@@ -15,18 +15,18 @@ entry:
if.then: ; preds = %entry
%mul73 = fmul double %a, 0.000000e+00
%sub76 = fsub double %mul73, %mul73
- store double %sub76, double* undef, align 4
+ store double %sub76, ptr undef, align 4
%call88 = tail call double @cos(double 0.000000e+00) nounwind
%mul89 = fmul double %call88, %call88
%sub92 = fsub double %mul89, %mul89
- store double %sub92, double* undef, align 4
+ store double %sub92, ptr undef, align 4
ret void
if.else: ; preds = %entry
%tmp101 = tail call double @llvm.pow.f64(double undef, double 0x3FD5555555555555)
%add112 = fadd double %tmp101, %tmp101
%mul118 = fmul double %add112, %add112
- store double 0.000000e+00, double* %x, align 4
+ store double 0.000000e+00, ptr %x, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/ifcvt11.ll b/llvm/test/CodeGen/ARM/ifcvt11.ll
index 7d577065a6d2d..370e05d927032 100644
--- a/llvm/test/CodeGen/ARM/ifcvt11.ll
+++ b/llvm/test/CodeGen/ARM/ifcvt11.ll
@@ -5,7 +5,7 @@
%struct.xyz_t = type { double, double, double }
-define i32 @effie(i32 %tsets, %struct.xyz_t* nocapture %p, i32 %a, i32 %b, i32 %c) nounwind readonly noinline {
+define i32 @effie(i32 %tsets, ptr nocapture %p, i32 %a, i32 %b, i32 %c) nounwind readonly noinline {
; CHECK-LABEL: effie:
entry:
%0 = icmp sgt i32 %tsets, 0
@@ -21,10 +21,10 @@ bb: ; preds = %bb4, %bb.nph
; CHECK: vmrs APSR_nzcv, fpscr
%r.19 = phi i32 [ 0, %bb.nph ], [ %r.0, %bb4 ]
%n.08 = phi i32 [ 0, %bb.nph ], [ %10, %bb4 ]
- %scevgep10 = getelementptr inbounds %struct.xyz_t, %struct.xyz_t* %p, i32 %n.08, i32 0
- %scevgep11 = getelementptr %struct.xyz_t, %struct.xyz_t* %p, i32 %n.08, i32 1
- %3 = load double, double* %scevgep10, align 4
- %4 = load double, double* %scevgep11, align 4
+ %scevgep10 = getelementptr inbounds %struct.xyz_t, ptr %p, i32 %n.08, i32 0
+ %scevgep11 = getelementptr %struct.xyz_t, ptr %p, i32 %n.08, i32 1
+ %3 = load double, ptr %scevgep10, align 4
+ %4 = load double, ptr %scevgep11, align 4
%5 = fcmp uge double %3, %4
br i1 %5, label %bb3, label %bb1
@@ -34,8 +34,8 @@ bb1: ; preds = %bb
; CHECK-NOT: vmrsmi
; CHECK: vcmp.f64
; CHECK: vmrs APSR_nzcv, fpscr
- %scevgep12 = getelementptr %struct.xyz_t, %struct.xyz_t* %p, i32 %n.08, i32 2
- %6 = load double, double* %scevgep12, align 4
+ %scevgep12 = getelementptr %struct.xyz_t, ptr %p, i32 %n.08, i32 2
+ %6 = load double, ptr %scevgep12, align 4
%7 = fcmp uge double %3, %6
br i1 %7, label %bb3, label %bb2
diff --git a/llvm/test/CodeGen/ARM/ifcvt5.ll b/llvm/test/CodeGen/ARM/ifcvt5.ll
index 11b88ed51d178..dc9a3400b691a 100644
--- a/llvm/test/CodeGen/ARM/ifcvt5.ll
+++ b/llvm/test/CodeGen/ARM/ifcvt5.ll
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=swift | FileCheck %s -check-prefix=SWIFT
; rdar://8402126
- at x = external global i32* ; <i32**> [#uses=1]
+ at x = external global ptr ; <ptr> [#uses=1]
define void @foo(i32 %a) "frame-pointer"="all" {
; A8-LABEL: foo:
@@ -26,8 +26,8 @@ define void @foo(i32 %a) "frame-pointer"="all" {
; SWIFT-NEXT: str r0, [r1]
; SWIFT-NEXT: bx lr
entry:
- %tmp = load i32*, i32** @x ; <i32*> [#uses=1]
- store i32 %a, i32* %tmp
+ %tmp = load ptr, ptr @x ; <ptr> [#uses=1]
+ store i32 %a, ptr %tmp
ret void
}
diff --git a/llvm/test/CodeGen/ARM/ifcvt7.ll b/llvm/test/CodeGen/ARM/ifcvt7.ll
index ed443a1814e62..431c4aa209cfe 100644
--- a/llvm/test/CodeGen/ARM/ifcvt7.ll
+++ b/llvm/test/CodeGen/ARM/ifcvt7.ll
@@ -1,28 +1,28 @@
; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
; FIXME: Need post-ifcvt branch folding to get rid of the extra br at end of BB1.
- %struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }
+ %struct.quad_struct = type { i32, i32, ptr, ptr, ptr, ptr, ptr }
-define fastcc i32 @CountTree(%struct.quad_struct* %tree) {
+define fastcc i32 @CountTree(ptr %tree) {
; CHECK: cmpeq
entry:
br label %tailrecurse
tailrecurse: ; preds = %bb, %entry
- %tmp6 = load %struct.quad_struct*, %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1]
- %tmp9 = load %struct.quad_struct*, %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=2]
- %tmp12 = load %struct.quad_struct*, %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1]
- %tmp14 = icmp eq %struct.quad_struct* null, null ; <i1> [#uses=1]
- %tmp17 = icmp eq %struct.quad_struct* %tmp6, null ; <i1> [#uses=1]
- %tmp23 = icmp eq %struct.quad_struct* %tmp9, null ; <i1> [#uses=1]
- %tmp29 = icmp eq %struct.quad_struct* %tmp12, null ; <i1> [#uses=1]
+ %tmp6 = load ptr, ptr null ; <ptr> [#uses=1]
+ %tmp9 = load ptr, ptr null ; <ptr> [#uses=2]
+ %tmp12 = load ptr, ptr null ; <ptr> [#uses=1]
+ %tmp14 = icmp eq ptr null, null ; <i1> [#uses=1]
+ %tmp17 = icmp eq ptr %tmp6, null ; <i1> [#uses=1]
+ %tmp23 = icmp eq ptr %tmp9, null ; <i1> [#uses=1]
+ %tmp29 = icmp eq ptr %tmp12, null ; <i1> [#uses=1]
%bothcond = and i1 %tmp17, %tmp14 ; <i1> [#uses=1]
%bothcond1 = and i1 %bothcond, %tmp23 ; <i1> [#uses=1]
%bothcond2 = and i1 %bothcond1, %tmp29 ; <i1> [#uses=1]
br i1 %bothcond2, label %return, label %bb
bb: ; preds = %tailrecurse
- %tmp41 = tail call fastcc i32 @CountTree( %struct.quad_struct* %tmp9 ) ; <i32> [#uses=0]
+ %tmp41 = tail call fastcc i32 @CountTree( ptr %tmp9 ) ; <i32> [#uses=0]
br label %tailrecurse
return: ; preds = %tailrecurse
diff --git a/llvm/test/CodeGen/ARM/ifcvt8.ll b/llvm/test/CodeGen/ARM/ifcvt8.ll
index e8b7f6926396e..016d4a6b43e07 100644
--- a/llvm/test/CodeGen/ARM/ifcvt8.ll
+++ b/llvm/test/CodeGen/ARM/ifcvt8.ll
@@ -1,15 +1,15 @@
; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
- %struct.SString = type { i8*, i32, i32 }
+ %struct.SString = type { ptr, i32, i32 }
declare void @abort()
-define fastcc void @t(%struct.SString* %word, i8 signext %c) {
+define fastcc void @t(ptr %word, i8 signext %c) {
; CHECK-NOT: pop
; CHECK: bxne
; CHECK-NOT: pop
entry:
- %tmp1 = icmp eq %struct.SString* %word, null ; <i1> [#uses=1]
+ %tmp1 = icmp eq ptr %word, null ; <i1> [#uses=1]
br i1 %tmp1, label %cond_true, label %cond_false
cond_true: ; preds = %entry
diff --git a/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll b/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
index cf07cf572523e..5dbf8dd86b891 100644
--- a/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
+++ b/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=arm-eabi | FileCheck %s -check-prefix=LE
; RUN: llc < %s -mtriple=armeb-eabi | FileCheck %s -check-prefix=BE
-define void @i24_or(i24* %a) {
+define void @i24_or(ptr %a) {
; LE-LABEL: i24_or:
; LE: @ %bb.0:
; LE-NEXT: ldrh r1, [r0]
@@ -20,13 +20,13 @@ define void @i24_or(i24* %a) {
; BE-NEXT: lsr r1, r1, #8
; BE-NEXT: strh r1, [r0]
; BE-NEXT: mov pc, lr
- %aa = load i24, i24* %a, align 1
+ %aa = load i24, ptr %a, align 1
%b = or i24 %aa, 384
- store i24 %b, i24* %a, align 1
+ store i24 %b, ptr %a, align 1
ret void
}
-define void @i24_and_or(i24* %a) {
+define void @i24_and_or(ptr %a) {
; LE-LABEL: i24_and_or:
; LE: @ %bb.0:
; LE-NEXT: ldrh r1, [r0]
@@ -43,14 +43,14 @@ define void @i24_and_or(i24* %a) {
; BE-NEXT: orr r1, r1, #1
; BE-NEXT: strh r1, [r0]
; BE-NEXT: mov pc, lr
- %b = load i24, i24* %a, align 1
+ %b = load i24, ptr %a, align 1
%c = and i24 %b, -128
%d = or i24 %c, 384
- store i24 %d, i24* %a, align 1
+ store i24 %d, ptr %a, align 1
ret void
}
-define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
+define void @i24_insert_bit(ptr %a, i1 zeroext %bit) {
; LE-LABEL: i24_insert_bit:
; LE: @ %bb.0:
; LE-NEXT: mov r3, #255
@@ -72,15 +72,15 @@ define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
; BE-NEXT: strh r1, [r0]
; BE-NEXT: mov pc, lr
%extbit = zext i1 %bit to i24
- %b = load i24, i24* %a, align 1
+ %b = load i24, ptr %a, align 1
%extbit.shl = shl nuw nsw i24 %extbit, 13
%c = and i24 %b, -8193
%d = or i24 %c, %extbit.shl
- store i24 %d, i24* %a, align 1
+ store i24 %d, ptr %a, align 1
ret void
}
-define void @i56_or(i56* %a) {
+define void @i56_or(ptr %a) {
; LE-LABEL: i56_or:
; LE: @ %bb.0:
; LE-NEXT: ldr r1, [r0]
@@ -101,13 +101,13 @@ define void @i56_or(i56* %a) {
; BE-NEXT: lsr r0, r0, #8
; BE-NEXT: strh r0, [r1]
; BE-NEXT: mov pc, lr
- %aa = load i56, i56* %a
+ %aa = load i56, ptr %a
%b = or i56 %aa, 384
- store i56 %b, i56* %a
+ store i56 %b, ptr %a
ret void
}
-define void @i56_and_or(i56* %a) {
+define void @i56_and_or(ptr %a) {
; LE-LABEL: i56_and_or:
; LE: @ %bb.0:
; LE-NEXT: ldr r1, [r0]
@@ -125,14 +125,14 @@ define void @i56_and_or(i56* %a) {
; BE-NEXT: strh r1, [r0]
; BE-NEXT: mov pc, lr
- %b = load i56, i56* %a, align 1
+ %b = load i56, ptr %a, align 1
%c = and i56 %b, -128
%d = or i56 %c, 384
- store i56 %d, i56* %a, align 1
+ store i56 %d, ptr %a, align 1
ret void
}
-define void @i56_insert_bit(i56* %a, i1 zeroext %bit) {
+define void @i56_insert_bit(ptr %a, i1 zeroext %bit) {
; LE-LABEL: i56_insert_bit:
; LE: @ %bb.0:
; LE-NEXT: ldr r2, [r0]
@@ -152,11 +152,11 @@ define void @i56_insert_bit(i56* %a, i1 zeroext %bit) {
; BE-NEXT: strh r1, [r0]
; BE-NEXT: mov pc, lr
%extbit = zext i1 %bit to i56
- %b = load i56, i56* %a, align 1
+ %b = load i56, ptr %a, align 1
%extbit.shl = shl nuw nsw i56 %extbit, 13
%c = and i56 %b, -8193
%d = or i56 %c, %extbit.shl
- store i56 %d, i56* %a, align 1
+ store i56 %d, ptr %a, align 1
ret void
}
diff --git a/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll b/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll
index 766b3d7ca4335..028ab99977c3d 100644
--- a/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll
+++ b/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll
@@ -1,14 +1,14 @@
; RUN: llc -mtriple=arm-eabi %s -o /dev/null
; RUN: llc -mtriple=arm-linux %s -o /dev/null
-define void @foo(<8 x float>* %f, <8 x float>* %g, <4 x i64>* %y)
+define void @foo(ptr %f, ptr %g, ptr %y)
{
- %h = load <8 x float>, <8 x float>* %f
+ %h = load <8 x float>, ptr %f
%i = fmul <8 x float> %h, <float 0x3FF19999A0000000, float 0x400A666660000000, float 0x40119999A0000000, float 0x40159999A0000000, float 0.5, float 0x3FE3333340000000, float 0x3FE6666660000000, float 0x3FE99999A0000000>
%m = bitcast <8 x float> %i to <4 x i64>
- %z = load <4 x i64>, <4 x i64>* %y
+ %z = load <4 x i64>, ptr %y
%n = mul <4 x i64> %z, %m
%p = bitcast <4 x i64> %n to <8 x float>
- store <8 x float> %p, <8 x float>* %g
+ store <8 x float> %p, ptr %g
ret void
}
diff --git a/llvm/test/CodeGen/ARM/indexed-mem.ll b/llvm/test/CodeGen/ARM/indexed-mem.ll
index 295bb377d732c..6e81a25dd1551 100644
--- a/llvm/test/CodeGen/ARM/indexed-mem.ll
+++ b/llvm/test/CodeGen/ARM/indexed-mem.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=thumbv8m.main %s -o - | FileCheck %s --check-prefix=CHECK-V8M
; RUN: llc -mtriple=armv8 %s -o - | FileCheck %s --check-prefix=CHECK-V8A
-define i32* @pre_inc_ldr(i32* %base, i32 %a) {
+define ptr @pre_inc_ldr(ptr %base, i32 %a) {
; CHECK-V8M-LABEL: pre_inc_ldr:
; CHECK-V8M: @ %bb.0:
; CHECK-V8M-NEXT: ldr r2, [r0, #4]!
@@ -16,15 +16,15 @@ define i32* @pre_inc_ldr(i32* %base, i32 %a) {
; CHECK-V8A-NEXT: add r1, r2, r1
; CHECK-V8A-NEXT: str r1, [r0, #4]
; CHECK-V8A-NEXT: bx lr
- %addr = getelementptr i32, i32* %base, i32 1
- %ld = load i32, i32* %addr
- %addr.1 = getelementptr i32, i32* %base, i32 2
+ %addr = getelementptr i32, ptr %base, i32 1
+ %ld = load i32, ptr %addr
+ %addr.1 = getelementptr i32, ptr %base, i32 2
%res = add i32 %ld, %a
- store i32 %res, i32* %addr.1
- ret i32* %addr
+ store i32 %res, ptr %addr.1
+ ret ptr %addr
}
-define i32* @pre_dec_ldr(i32* %base, i32 %a) {
+define ptr @pre_dec_ldr(ptr %base, i32 %a) {
; CHECK-V8M-LABEL: pre_dec_ldr:
; CHECK-V8M: @ %bb.0:
; CHECK-V8M-NEXT: ldr r2, [r0, #-4]!
@@ -38,15 +38,15 @@ define i32* @pre_dec_ldr(i32* %base, i32 %a) {
; CHECK-V8A-NEXT: add r1, r2, r1
; CHECK-V8A-NEXT: str r1, [r0, #12]
; CHECK-V8A-NEXT: bx lr
- %addr = getelementptr i32, i32* %base, i32 -1
- %ld = load i32, i32* %addr
- %addr.1 = getelementptr i32, i32* %base, i32 2
+ %addr = getelementptr i32, ptr %base, i32 -1
+ %ld = load i32, ptr %addr
+ %addr.1 = getelementptr i32, ptr %base, i32 2
%res = add i32 %ld, %a
- store i32 %res, i32* %addr.1
- ret i32* %addr
+ store i32 %res, ptr %addr.1
+ ret ptr %addr
}
-define i32* @post_inc_ldr(i32* %base, i32* %addr.2, i32 %a) {
+define ptr @post_inc_ldr(ptr %base, ptr %addr.2, i32 %a) {
; CHECK-V8M-LABEL: post_inc_ldr:
; CHECK-V8M: @ %bb.0:
; CHECK-V8M-NEXT: ldr r3, [r0], #4
@@ -60,15 +60,14 @@ define i32* @post_inc_ldr(i32* %base, i32* %addr.2, i32 %a) {
; CHECK-V8A-NEXT: add r2, r3, r2
; CHECK-V8A-NEXT: str r2, [r1]
; CHECK-V8A-NEXT: bx lr
- %addr = getelementptr i32, i32* %base, i32 0
- %ld = load i32, i32* %addr
- %addr.1 = getelementptr i32, i32* %base, i32 1
+ %ld = load i32, ptr %base
+ %addr.1 = getelementptr i32, ptr %base, i32 1
%res = add i32 %ld, %a
- store i32 %res, i32* %addr.2
- ret i32* %addr.1
+ store i32 %res, ptr %addr.2
+ ret ptr %addr.1
}
-define i32* @post_dec_ldr(i32* %base, i32* %addr.2, i32 %a) {
+define ptr @post_dec_ldr(ptr %base, ptr %addr.2, i32 %a) {
; CHECK-V8M-LABEL: post_dec_ldr:
; CHECK-V8M: @ %bb.0:
; CHECK-V8M-NEXT: ldr r3, [r0], #-4
@@ -82,15 +81,14 @@ define i32* @post_dec_ldr(i32* %base, i32* %addr.2, i32 %a) {
; CHECK-V8A-NEXT: add r2, r3, r2
; CHECK-V8A-NEXT: str r2, [r1]
; CHECK-V8A-NEXT: bx lr
- %addr = getelementptr i32, i32* %base, i32 0
- %ld = load i32, i32* %addr
- %addr.1 = getelementptr i32, i32* %base, i32 -1
+ %ld = load i32, ptr %base
+ %addr.1 = getelementptr i32, ptr %base, i32 -1
%res = add i32 %ld, %a
- store i32 %res, i32* %addr.2
- ret i32* %addr.1
+ store i32 %res, ptr %addr.2
+ ret ptr %addr.1
}
-define i32* @pre_inc_str(i32* %base, i32 %a, i32 %b) {
+define ptr @pre_inc_str(ptr %base, i32 %a, i32 %b) {
; CHECK-V8M-LABEL: pre_inc_str:
; CHECK-V8M: @ %bb.0:
; CHECK-V8M-NEXT: add r1, r2
@@ -102,13 +100,13 @@ define i32* @pre_inc_str(i32* %base, i32 %a, i32 %b) {
; CHECK-V8A-NEXT: add r1, r1, r2
; CHECK-V8A-NEXT: str r1, [r0, #4]!
; CHECK-V8A-NEXT: bx lr
- %addr.1 = getelementptr i32, i32* %base, i32 1
+ %addr.1 = getelementptr i32, ptr %base, i32 1
%res = add i32 %a, %b
- store i32 %res, i32* %addr.1
- ret i32* %addr.1
+ store i32 %res, ptr %addr.1
+ ret ptr %addr.1
}
-define i32* @pre_dec_str(i32* %base, i32 %a, i32 %b) {
+define ptr @pre_dec_str(ptr %base, i32 %a, i32 %b) {
; CHECK-V8M-LABEL: pre_dec_str:
; CHECK-V8M: @ %bb.0:
; CHECK-V8M-NEXT: add r1, r2
@@ -121,12 +119,12 @@ define i32* @pre_dec_str(i32* %base, i32 %a, i32 %b) {
; CHECK-V8A-NEXT: str r1, [r0, #-4]!
; CHECK-V8A-NEXT: bx lr
%res = add i32 %a, %b
- %addr.1 = getelementptr i32, i32* %base, i32 -1
- store i32 %res, i32* %addr.1
- ret i32* %addr.1
+ %addr.1 = getelementptr i32, ptr %base, i32 -1
+ store i32 %res, ptr %addr.1
+ ret ptr %addr.1
}
-define i32* @post_inc_str(i32* %base, i32 %a, i32 %b) {
+define ptr @post_inc_str(ptr %base, i32 %a, i32 %b) {
; CHECK-V8M-LABEL: post_inc_str:
; CHECK-V8M: @ %bb.0:
; CHECK-V8M-NEXT: add r1, r2
@@ -138,13 +136,13 @@ define i32* @post_inc_str(i32* %base, i32 %a, i32 %b) {
; CHECK-V8A-NEXT: add r1, r1, r2
; CHECK-V8A-NEXT: str r1, [r0], #4
; CHECK-V8A-NEXT: bx lr
- %addr.1 = getelementptr i32, i32* %base, i32 1
+ %addr.1 = getelementptr i32, ptr %base, i32 1
%res = add i32 %a, %b
- store i32 %res, i32* %base
- ret i32* %addr.1
+ store i32 %res, ptr %base
+ ret ptr %addr.1
}
-define i32* @post_dec_str(i32* %base, i32 %a, i32 %b) {
+define ptr @post_dec_str(ptr %base, i32 %a, i32 %b) {
; CHECK-V8M-LABEL: post_dec_str:
; CHECK-V8M: @ %bb.0:
; CHECK-V8M-NEXT: add r1, r2
@@ -156,14 +154,14 @@ define i32* @post_dec_str(i32* %base, i32 %a, i32 %b) {
; CHECK-V8A-NEXT: add r1, r1, r2
; CHECK-V8A-NEXT: str r1, [r0], #-4
; CHECK-V8A-NEXT: bx lr
- %addr.1 = getelementptr i32, i32* %base, i32 -1
+ %addr.1 = getelementptr i32, ptr %base, i32 -1
%res = add i32 %a, %b
- store i32 %res, i32* %base
- ret i32* %addr.1
+ store i32 %res, ptr %base
+ ret ptr %addr.1
}
; TODO: Generate ldrd
-define i32* @pre_inc_ldrd(i32* %base) {
+define ptr @pre_inc_ldrd(ptr %base) {
; CHECK-V8M-LABEL: pre_inc_ldrd:
; CHECK-V8M: @ %bb.0:
; CHECK-V8M-NEXT: ldr r1, [r0, #4]!
@@ -179,18 +177,18 @@ define i32* @pre_inc_ldrd(i32* %base) {
; CHECK-V8A-NEXT: add r1, r1, r2
; CHECK-V8A-NEXT: str r1, [r0, #8]
; CHECK-V8A-NEXT: bx lr
- %addr = getelementptr i32, i32* %base, i32 1
- %addr.1 = getelementptr i32, i32* %base, i32 2
- %addr.2 = getelementptr i32, i32* %base, i32 3
- %ld = load i32, i32* %addr
- %ld.1 = load i32, i32* %addr.1
+ %addr = getelementptr i32, ptr %base, i32 1
+ %addr.1 = getelementptr i32, ptr %base, i32 2
+ %addr.2 = getelementptr i32, ptr %base, i32 3
+ %ld = load i32, ptr %addr
+ %ld.1 = load i32, ptr %addr.1
%res = add i32 %ld, %ld.1
- store i32 %res, i32* %addr.2
- ret i32* %addr
+ store i32 %res, ptr %addr.2
+ ret ptr %addr
}
; TODO: Generate ldrd
-define i32* @pre_dec_ldrd(i32* %base) {
+define ptr @pre_dec_ldrd(ptr %base) {
; CHECK-V8M-LABEL: pre_dec_ldrd:
; CHECK-V8M: @ %bb.0:
; CHECK-V8M-NEXT: ldr r1, [r0, #-4]!
@@ -206,18 +204,18 @@ define i32* @pre_dec_ldrd(i32* %base) {
; CHECK-V8A-NEXT: add r1, r1, r2
; CHECK-V8A-NEXT: str r1, [r0, #-8]
; CHECK-V8A-NEXT: bx lr
- %addr = getelementptr i32, i32* %base, i32 -1
- %addr.1 = getelementptr i32, i32* %base, i32 -2
- %addr.2 = getelementptr i32, i32* %base, i32 -3
- %ld = load i32, i32* %addr
- %ld.1 = load i32, i32* %addr.1
+ %addr = getelementptr i32, ptr %base, i32 -1
+ %addr.1 = getelementptr i32, ptr %base, i32 -2
+ %addr.2 = getelementptr i32, ptr %base, i32 -3
+ %ld = load i32, ptr %addr
+ %ld.1 = load i32, ptr %addr.1
%res = add i32 %ld, %ld.1
- store i32 %res, i32* %addr.2
- ret i32* %addr
+ store i32 %res, ptr %addr.2
+ ret ptr %addr
}
; TODO: Generate post inc
-define i32* @post_inc_ldrd(i32* %base, i32* %addr.3) {
+define ptr @post_inc_ldrd(ptr %base, ptr %addr.3) {
; CHECK-V8M-LABEL: post_inc_ldrd:
; CHECK-V8M: @ %bb.0:
; CHECK-V8M-NEXT: ldrd r2, r3, [r0], #8
@@ -231,17 +229,16 @@ define i32* @post_inc_ldrd(i32* %base, i32* %addr.3) {
; CHECK-V8A-NEXT: add r2, r2, r3
; CHECK-V8A-NEXT: str r2, [r1]
; CHECK-V8A-NEXT: bx lr
- %addr = getelementptr i32, i32* %base, i32 0
- %ld = load i32, i32* %addr
- %addr.1 = getelementptr i32, i32* %base, i32 1
- %ld.1 = load i32, i32* %addr.1
- %addr.2 = getelementptr i32, i32* %base, i32 2
+ %ld = load i32, ptr %base
+ %addr.1 = getelementptr i32, ptr %base, i32 1
+ %ld.1 = load i32, ptr %addr.1
+ %addr.2 = getelementptr i32, ptr %base, i32 2
%res = add i32 %ld, %ld.1
- store i32 %res, i32* %addr.3
- ret i32* %addr.2
+ store i32 %res, ptr %addr.3
+ ret ptr %addr.2
}
-define i32* @pre_inc_str_multi(i32* %base) {
+define ptr @pre_inc_str_multi(ptr %base) {
; CHECK-V8M-LABEL: pre_inc_str_multi:
; CHECK-V8M: @ %bb.0:
; CHECK-V8M-NEXT: ldrd r1, r2, [r0]
@@ -255,17 +252,16 @@ define i32* @pre_inc_str_multi(i32* %base) {
; CHECK-V8A-NEXT: add r1, r1, r2
; CHECK-V8A-NEXT: str r1, [r0, #8]!
; CHECK-V8A-NEXT: bx lr
- %addr = getelementptr i32, i32* %base, i32 0
- %addr.1 = getelementptr i32, i32* %base, i32 1
- %ld = load i32, i32* %addr
- %ld.1 = load i32, i32* %addr.1
+ %addr.1 = getelementptr i32, ptr %base, i32 1
+ %ld = load i32, ptr %base
+ %ld.1 = load i32, ptr %addr.1
%res = add i32 %ld, %ld.1
- %addr.2 = getelementptr i32, i32* %base, i32 2
- store i32 %res, i32* %addr.2
- ret i32* %addr.2
+ %addr.2 = getelementptr i32, ptr %base, i32 2
+ store i32 %res, ptr %addr.2
+ ret ptr %addr.2
}
-define i32* @pre_dec_str_multi(i32* %base) {
+define ptr @pre_dec_str_multi(ptr %base) {
; CHECK-V8M-LABEL: pre_dec_str_multi:
; CHECK-V8M: @ %bb.0:
; CHECK-V8M-NEXT: ldrd r1, r2, [r0]
@@ -279,17 +275,16 @@ define i32* @pre_dec_str_multi(i32* %base) {
; CHECK-V8A-NEXT: add r1, r1, r2
; CHECK-V8A-NEXT: str r1, [r0, #-4]!
; CHECK-V8A-NEXT: bx lr
- %addr = getelementptr i32, i32* %base, i32 0
- %addr.1 = getelementptr i32, i32* %base, i32 1
- %ld = load i32, i32* %addr
- %ld.1 = load i32, i32* %addr.1
+ %addr.1 = getelementptr i32, ptr %base, i32 1
+ %ld = load i32, ptr %base
+ %ld.1 = load i32, ptr %addr.1
%res = add i32 %ld, %ld.1
- %addr.2 = getelementptr i32, i32* %base, i32 -1
- store i32 %res, i32* %addr.2
- ret i32* %addr.2
+ %addr.2 = getelementptr i32, ptr %base, i32 -1
+ store i32 %res, ptr %addr.2
+ ret ptr %addr.2
}
-define i32* @illegal_pre_inc_store_1(i32* %base) {
+define ptr @illegal_pre_inc_store_1(ptr %base) {
; CHECK-V8M-LABEL: illegal_pre_inc_store_1:
; CHECK-V8M: @ %bb.0: @ %entry
; CHECK-V8M-NEXT: str r0, [r0, #8]
@@ -302,13 +297,13 @@ define i32* @illegal_pre_inc_store_1(i32* %base) {
; CHECK-V8A-NEXT: add r0, r0, #8
; CHECK-V8A-NEXT: bx lr
entry:
- %ptr.to.use = getelementptr i32, i32* %base, i32 2
- %ptr.to.store = ptrtoint i32* %base to i32
- store i32 %ptr.to.store, i32* %ptr.to.use, align 4
- ret i32* %ptr.to.use
+ %ptr.to.use = getelementptr i32, ptr %base, i32 2
+ %ptr.to.store = ptrtoint ptr %base to i32
+ store i32 %ptr.to.store, ptr %ptr.to.use, align 4
+ ret ptr %ptr.to.use
}
-define i32* @legal_pre_inc_store_needs_copy_1(i32* %base) {
+define ptr @legal_pre_inc_store_needs_copy_1(ptr %base) {
; CHECK-V8M-LABEL: legal_pre_inc_store_needs_copy_1:
; CHECK-V8M: @ %bb.0: @ %entry
; CHECK-V8M-NEXT: add.w r1, r0, #8
@@ -323,13 +318,13 @@ define i32* @legal_pre_inc_store_needs_copy_1(i32* %base) {
; CHECK-V8A-NEXT: mov r0, r1
; CHECK-V8A-NEXT: bx lr
entry:
- %ptr.to.use = getelementptr i32, i32* %base, i32 2
- %ptr.to.store = ptrtoint i32* %ptr.to.use to i32
- store i32 %ptr.to.store, i32* %ptr.to.use, align 4
- ret i32* %ptr.to.use
+ %ptr.to.use = getelementptr i32, ptr %base, i32 2
+ %ptr.to.store = ptrtoint ptr %ptr.to.use to i32
+ store i32 %ptr.to.store, ptr %ptr.to.use, align 4
+ ret ptr %ptr.to.use
}
-define i32* @legal_pre_inc_store_needs_copy_2(i32 %base) {
+define ptr @legal_pre_inc_store_needs_copy_2(i32 %base) {
; CHECK-V8M-LABEL: legal_pre_inc_store_needs_copy_2:
; CHECK-V8M: @ %bb.0: @ %entry
; CHECK-V8M-NEXT: str r0, [r0, #8]
@@ -342,8 +337,8 @@ define i32* @legal_pre_inc_store_needs_copy_2(i32 %base) {
; CHECK-V8A-NEXT: add r0, r0, #8
; CHECK-V8A-NEXT: bx lr
entry:
- %ptr = inttoptr i32 %base to i32*
- %ptr.to.use = getelementptr i32, i32* %ptr, i32 2
- store i32 %base, i32* %ptr.to.use, align 4
- ret i32* %ptr.to.use
+ %ptr = inttoptr i32 %base to ptr
+ %ptr.to.use = getelementptr i32, ptr %ptr, i32 2
+ store i32 %base, ptr %ptr.to.use, align 4
+ ret ptr %ptr.to.use
}
diff --git a/llvm/test/CodeGen/ARM/indirect-hidden.ll b/llvm/test/CodeGen/ARM/indirect-hidden.ll
index eb0302834879a..90b4ffdd1cd1e 100644
--- a/llvm/test/CodeGen/ARM/indirect-hidden.ll
+++ b/llvm/test/CodeGen/ARM/indirect-hidden.ll
@@ -3,12 +3,12 @@
@var = external global i32
@var_hidden = external hidden global i32
-define i32* @get_var() {
- ret i32* @var
+define ptr @get_var() {
+ ret ptr @var
}
-define i32* @get_var_hidden() {
- ret i32* @var_hidden
+define ptr @get_var_hidden() {
+ ret ptr @var_hidden
}
; CHECK: .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers
diff --git a/llvm/test/CodeGen/ARM/indirect-reg-input.ll b/llvm/test/CodeGen/ARM/indirect-reg-input.ll
index 4c2c77d6bcf40..90dd4a9040b06 100644
--- a/llvm/test/CodeGen/ARM/indirect-reg-input.ll
+++ b/llvm/test/CodeGen/ARM/indirect-reg-input.ll
@@ -6,9 +6,8 @@
%struct.my_stack = type { %struct.myjmp_buf }
%struct.myjmp_buf = type { [6 x i32] }
-define void @switch_to_stack(%struct.my_stack* %stack) nounwind {
+define void @switch_to_stack(ptr %stack) nounwind {
entry:
- %regs = getelementptr inbounds %struct.my_stack, %struct.my_stack* %stack, i32 0, i32 0
- tail call void asm "\0A", "=*r,*0"(%struct.myjmp_buf* elementtype(%struct.myjmp_buf) %regs, %struct.myjmp_buf* elementtype(%struct.myjmp_buf) %regs)
+ tail call void asm "\0A", "=*r,*0"(ptr elementtype(%struct.myjmp_buf) %stack, ptr elementtype(%struct.myjmp_buf) %stack)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/indirectbr-2.ll b/llvm/test/CodeGen/ARM/indirectbr-2.ll
index ca068db1db0e4..3f9226c5be22a 100644
--- a/llvm/test/CodeGen/ARM/indirectbr-2.ll
+++ b/llvm/test/CodeGen/ARM/indirectbr-2.ll
@@ -2,7 +2,7 @@
; <rdar://problem/12529625>
@foo = global i32 34879, align 4
- at DWJumpTable2808 = global [2 x i32] [i32 sub (i32 ptrtoint (i8* blockaddress(@func, %14) to i32), i32 ptrtoint (i8* blockaddress(@func, %4) to i32)), i32 sub (i32 ptrtoint (i8* blockaddress(@func, %13) to i32), i32 ptrtoint (i8* blockaddress(@func, %4) to i32))]
+ at DWJumpTable2808 = global [2 x i32] [i32 sub (i32 ptrtoint (ptr blockaddress(@func, %14) to i32), i32 ptrtoint (ptr blockaddress(@func, %4) to i32)), i32 sub (i32 ptrtoint (ptr blockaddress(@func, %13) to i32), i32 ptrtoint (ptr blockaddress(@func, %4) to i32))]
@0 = internal constant [45 x i8] c"func XXXXXXXXXXX :: bb xxxxxxxxxxxxxxxxxxxx\0A\00"
; The indirect branch has the two destinations as successors. The lone PHI
@@ -15,7 +15,7 @@
define i32 @func() nounwind ssp {
%1 = alloca i32, align 4
- %2 = load i32, i32* @foo, align 4
+ %2 = load i32, ptr @foo, align 4
%3 = icmp eq i32 %2, 34879
br label %4
@@ -23,17 +23,17 @@ define i32 @func() nounwind ssp {
%5 = zext i1 %3 to i32
%6 = mul i32 %5, 287
%7 = add i32 %6, 2
- %8 = getelementptr [2 x i32], [2 x i32]* @DWJumpTable2808, i32 0, i32 %5
- %9 = load i32, i32* %8
- %10 = add i32 %9, ptrtoint (i8* blockaddress(@func, %4) to i32)
- %11 = inttoptr i32 %10 to i8*
- %12 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([45 x i8], [45 x i8]* @0, i32 0, i32 0))
- indirectbr i8* %11, [label %13, label %14]
+ %8 = getelementptr [2 x i32], ptr @DWJumpTable2808, i32 0, i32 %5
+ %9 = load i32, ptr %8
+ %10 = add i32 %9, ptrtoint (ptr blockaddress(@func, %4) to i32)
+ %11 = inttoptr i32 %10 to ptr
+ %12 = call i32 (ptr, ...) @printf(ptr @0)
+ indirectbr ptr %11, [label %13, label %14]
; <label>:13 ; preds = %4
%tmp14 = phi i32 [ %7, %4 ]
- store i32 23958, i32* @foo, align 4
- %tmp15 = load i32, i32* %1, align 4
+ store i32 23958, ptr @foo, align 4
+ %tmp15 = load i32, ptr %1, align 4
%tmp16 = icmp eq i32 %tmp15, 0
%tmp17 = zext i1 %tmp16 to i32
%tmp21 = add i32 %tmp17, %tmp14
@@ -43,4 +43,4 @@ define i32 @func() nounwind ssp {
ret i32 42
}
-declare i32 @printf(i8*, ...)
+declare i32 @printf(ptr, ...)
diff --git a/llvm/test/CodeGen/ARM/indirectbr-3.ll b/llvm/test/CodeGen/ARM/indirectbr-3.ll
index 126663316007c..948e5a8615432 100644
--- a/llvm/test/CodeGen/ARM/indirectbr-3.ll
+++ b/llvm/test/CodeGen/ARM/indirectbr-3.ll
@@ -25,7 +25,7 @@ define i32 @preserve_blocks(i32 %x) {
; CHECK-NOT: 1 ifcvt - Number of diamond if-conversions performed
entry:
%c2 = icmp slt i32 %x, 3
- %blockaddr = select i1 %c2, i8* blockaddress(@preserve_blocks, %ibt1), i8* blockaddress(@preserve_blocks, %ibt2)
+ %blockaddr = select i1 %c2, ptr blockaddress(@preserve_blocks, %ibt1), ptr blockaddress(@preserve_blocks, %ibt2)
%c1 = icmp eq i32 %x, 0
br i1 %c1, label %pre_ib, label %nextblock
@@ -39,5 +39,5 @@ ibt2:
ret i32 1
pre_ib:
- indirectbr i8* %blockaddr, [ label %ibt1, label %ibt2 ]
+ indirectbr ptr %blockaddr, [ label %ibt1, label %ibt2 ]
}
diff --git a/llvm/test/CodeGen/ARM/indirectbr.ll b/llvm/test/CodeGen/ARM/indirectbr.ll
index 68ad606b01cef..b38c42e2b3b56 100644
--- a/llvm/test/CodeGen/ARM/indirectbr.ll
+++ b/llvm/test/CodeGen/ARM/indirectbr.ll
@@ -3,8 +3,8 @@
; RUN: llc < %s -relocation-model=static -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=THUMB2
; RUN: llc < %s -relocation-model=static -mtriple=thumbv8-apple-darwin | FileCheck %s -check-prefix=THUMB2
- at nextaddr = global i8* null ; <i8**> [#uses=2]
- at C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
+ at nextaddr = global ptr null ; <ptr> [#uses=2]
+ at C.0.2070 = private constant [5 x ptr] [ptr blockaddress(@foo, %L1), ptr blockaddress(@foo, %L2), ptr blockaddress(@foo, %L3), ptr blockaddress(@foo, %L4), ptr blockaddress(@foo, %L5)] ; <ptr> [#uses=1]
define internal i32 @foo(i32 %i) nounwind {
; ARM-LABEL: foo:
@@ -16,8 +16,8 @@ entry:
; THUMB: [[NEXTADDR_PCBASE:LPC0_[0-9]]]:
; THUMB: add r[[NEXTADDR_REG]], pc
- %0 = load i8*, i8** @nextaddr, align 4 ; <i8*> [#uses=2]
- %1 = icmp eq i8* %0, null ; <i1> [#uses=1]
+ %0 = load ptr, ptr @nextaddr, align 4 ; <ptr> [#uses=2]
+ %1 = icmp eq ptr %0, null ; <i1> [#uses=1]
; indirect branch gets duplicated here
; ARM: bx
; THUMB: mov pc,
@@ -25,14 +25,14 @@ entry:
br i1 %1, label %bb3, label %bb2
bb2: ; preds = %entry, %bb3
- %gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1]
+ %gotovar.4.0 = phi ptr [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <ptr> [#uses=1]
; ARM: bx
; THUMB: mov pc,
- indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
+ indirectbr ptr %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
bb3: ; preds = %entry
- %2 = getelementptr inbounds [5 x i8*], [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1]
- %gotovar.4.0.pre = load i8*, i8** %2, align 4 ; <i8*> [#uses=1]
+ %2 = getelementptr inbounds [5 x ptr], ptr @C.0.2070, i32 0, i32 %i ; <ptr> [#uses=1]
+ %gotovar.4.0.pre = load ptr, ptr %2, align 4 ; <ptr> [#uses=1]
br label %bb2
L5: ; preds = %bb2
@@ -69,7 +69,7 @@ L1: ; preds = %L2, %bb2
; THUMB2-LABEL: %L1
; THUMB2: ldr [[R2:r[0-9]+]], LCPI
; THUMB2-NEXT: str{{(.w)?}} [[R2]]
- store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
+ store ptr blockaddress(@foo, %L5), ptr @nextaddr, align 4
ret i32 %res.3
}
; ARM: .long Ltmp0-(LPC{{.*}}+8)
diff --git a/llvm/test/CodeGen/ARM/inline-asm-clobber.ll b/llvm/test/CodeGen/ARM/inline-asm-clobber.ll
index cb2069c20bf6f..7b1331f3f1e84 100644
--- a/llvm/test/CodeGen/ARM/inline-asm-clobber.ll
+++ b/llvm/test/CodeGen/ARM/inline-asm-clobber.ll
@@ -22,6 +22,6 @@ define void @foo() nounwind {
define i32 @bar(i32 %i) {
%vla = alloca i32, i32 %i, align 4
tail call void asm sideeffect "mov r7, #1", "~{r11}"()
- %1 = load volatile i32, i32* %vla, align 4
+ %1 = load volatile i32, ptr %vla, align 4
ret i32 %1
}
diff --git a/llvm/test/CodeGen/ARM/inline-asm-multilevel-gep.ll b/llvm/test/CodeGen/ARM/inline-asm-multilevel-gep.ll
index 145db14959a52..475a2670d3e00 100644
--- a/llvm/test/CodeGen/ARM/inline-asm-multilevel-gep.ll
+++ b/llvm/test/CodeGen/ARM/inline-asm-multilevel-gep.ll
@@ -7,6 +7,6 @@
define void @bar() {
; access foo[1][1]
; CHECK: @ foo+12
- tail call void asm sideeffect "@ ${0:c}", "i"(i32* getelementptr inbounds ([2 x [2 x i32]], [2 x [2 x i32]]* @foo, i64 0, i64 1, i64 1))
+ tail call void asm sideeffect "@ ${0:c}", "i"(ptr getelementptr inbounds ([2 x [2 x i32]], ptr @foo, i64 0, i64 1, i64 1))
ret void
}
diff --git a/llvm/test/CodeGen/ARM/inline-diagnostics.ll b/llvm/test/CodeGen/ARM/inline-diagnostics.ll
index 036053c580eee..215a897a972a5 100644
--- a/llvm/test/CodeGen/ARM/inline-diagnostics.ll
+++ b/llvm/test/CodeGen/ARM/inline-diagnostics.ll
@@ -7,9 +7,8 @@ define float @inline_func(float %f1, float %f2) #0 {
%c1 = alloca %struct.float4, align 4
%c2 = alloca %struct.float4, align 4
%c3 = alloca %struct.float4, align 4
- call void asm sideeffect "vmul.f32 ${2:q}, ${0:q}, ${1:q}", "=*r,=*r,*w"(%struct.float4* elementtype(%struct.float4) %c1, %struct.float4* elementtype(%struct.float4) %c2, %struct.float4* elementtype(%struct.float4) %c3) #1, !srcloc !1
- %x = getelementptr inbounds %struct.float4, %struct.float4* %c3, i32 0, i32 0
- %1 = load float, float* %x, align 4
+ call void asm sideeffect "vmul.f32 ${2:q}, ${0:q}, ${1:q}", "=*r,=*r,*w"(ptr elementtype(%struct.float4) %c1, ptr elementtype(%struct.float4) %c2, ptr elementtype(%struct.float4) %c3) #1, !srcloc !1
+ %1 = load float, ptr %c3, align 4
ret float %1
}
diff --git a/llvm/test/CodeGen/ARM/inlineasm-64bit.ll b/llvm/test/CodeGen/ARM/inlineasm-64bit.ll
index 8b68cad328471..1a0c8c7d9a58e 100644
--- a/llvm/test/CodeGen/ARM/inlineasm-64bit.ll
+++ b/llvm/test/CodeGen/ARM/inlineasm-64bit.ll
@@ -1,16 +1,16 @@
; RUN: llc < %s -O3 -mtriple=arm-linux-gnueabi -no-integrated-as | FileCheck %s
; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs -no-integrated-as < %s | FileCheck %s
; check if regs are passing correctly
-define void @i64_write(i64* %p, i64 %val) nounwind {
+define void @i64_write(ptr %p, i64 %val) nounwind {
; CHECK-LABEL: i64_write:
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
- %1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A teq $0, #0\0A bne 1b", "=&r,=*Qo,r,r,~{cc}"(i64* elementtype(i64) %p, i64* %p, i64 %val) nounwind
+ %1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A teq $0, #0\0A bne 1b", "=&r,=*Qo,r,r,~{cc}"(ptr elementtype(i64) %p, ptr %p, i64 %val) nounwind
ret void
}
; check if register allocation can reuse the registers
-define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind {
+define void @multi_writes(ptr %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind {
entry:
; CHECK-LABEL: multi_writes:
; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
@@ -34,36 +34,36 @@ entry:
; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
- tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
- %incdec.ptr = getelementptr inbounds i64, i64* %p, i32 1
- tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
- tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
+ tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(ptr %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
+ %incdec.ptr = getelementptr inbounds i64, ptr %p, i32 1
+ tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(ptr %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
+ tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(ptr %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
ret void
}
; check if callee-saved registers used by inline asm are saved/restored
-define void @foo(i64* %p, i64 %i) nounwind {
+define void @foo(ptr %p, i64 %i) nounwind {
; CHECK-LABEL:foo:
; CHECK: {{push|push.w}} {{{r[4-9]|r10|r11}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
; CHECK: {{pop|pop.w}} {{{r[4-9]|r10|r11}}
- %1 = tail call { i64, i64 } asm sideeffect "@ atomic64_set\0A1: ldrexd $0, ${0:H}, [$3]\0Aldrexd $1, ${1:H}, [$3]\0A strexd $0, $4, ${4:H}, [$3]\0A teq $0, #0\0A bne 1b", "=&r,=&r,=*Qo,r,r,~{cc}"(i64* elementtype(i64) %p, i64* %p, i64 %i) nounwind
+ %1 = tail call { i64, i64 } asm sideeffect "@ atomic64_set\0A1: ldrexd $0, ${0:H}, [$3]\0Aldrexd $1, ${1:H}, [$3]\0A strexd $0, $4, ${4:H}, [$3]\0A teq $0, #0\0A bne 1b", "=&r,=&r,=*Qo,r,r,~{cc}"(ptr elementtype(i64) %p, ptr %p, i64 %i) nounwind
ret void
}
; return *p;
-define i64 @ldrd_test(i64* %p) nounwind {
+define i64 @ldrd_test(ptr %p) nounwind {
; CHECK-LABEL: ldrd_test:
- %1 = tail call i64 asm "ldrd $0, ${0:H}, [$1]", "=r,r"(i64* %p) nounwind
+ %1 = tail call i64 asm "ldrd $0, ${0:H}, [$1]", "=r,r"(ptr %p) nounwind
ret i64 %1
}
-define i64 @QR_test(i64* %p) nounwind {
+define i64 @QR_test(ptr %p) nounwind {
; CHECK-LABEL: QR_test:
; CHECK: ldrd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
- %1 = tail call i64 asm "ldrd ${0:Q}, ${0:R}, [$1]", "=r,r"(i64* %p) nounwind
+ %1 = tail call i64 asm "ldrd ${0:Q}, ${0:R}, [$1]", "=r,r"(ptr %p) nounwind
ret i64 %1
}
@@ -75,14 +75,14 @@ define i64 @defuse_test(i64 %p) nounwind {
}
; *p = (hi << 32) | lo;
-define void @strd_test(i64* %p, i32 %lo, i32 %hi) nounwind {
+define void @strd_test(ptr %p, i32 %lo, i32 %hi) nounwind {
; CHECK-LABEL: strd_test:
; CHECK: strd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
%1 = zext i32 %hi to i64
%2 = shl nuw i64 %1, 32
%3 = sext i32 %lo to i64
%4 = or i64 %2, %3
- tail call void asm sideeffect "strd $0, ${0:H}, [$1]", "r,r"(i64 %4, i64* %p) nounwind
+ tail call void asm sideeffect "strd $0, ${0:H}, [$1]", "r,r"(i64 %4, ptr %p) nounwind
ret void
}
@@ -91,7 +91,7 @@ define i64 @tied_64bit_test(i64 %in) nounwind {
; CHECK-LABEL: tied_64bit_test:
; CHECK: OUT([[OUTREG:r[0-9]+]]), IN([[OUTREG]])
%addr = alloca i64
- call void asm "OUT($0), IN($1)", "=*rm,0"(i64* elementtype(i64) %addr, i64 %in)
+ call void asm "OUT($0), IN($1)", "=*rm,0"(ptr elementtype(i64) %addr, i64 %in)
ret i64 %in
}
diff --git a/llvm/test/CodeGen/ARM/inlineasm-output-template.ll b/llvm/test/CodeGen/ARM/inlineasm-output-template.ll
index 0d9300da79c98..c0680f3777f26 100644
--- a/llvm/test/CodeGen/ARM/inlineasm-output-template.ll
+++ b/llvm/test/CodeGen/ARM/inlineasm-output-template.ll
@@ -13,7 +13,7 @@ define dso_local i32 @test_inlineasm_c_output_template0() {
; CHECK: @TEST baz
@baz = internal global i32 0, align 4
define dso_local i32 @test_inlineasm_c_output_template2() {
- tail call void asm sideeffect "@TEST ${0:c}", "i"(i32* nonnull @baz)
+ tail call void asm sideeffect "@TEST ${0:c}", "i"(ptr nonnull @baz)
ret i32 42
}
diff --git a/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-arm.ll b/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-arm.ll
index 92c6e1696b999..a98132cc5f083 100644
--- a/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-arm.ll
+++ b/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-arm.ll
@@ -2,8 +2,8 @@
;RUN: llc -mtriple=armv7-linux-gnueabi < %s | FileCheck %s -check-prefix=ASM
;RUN: llc -mtriple=armv7-apple-darwin < %s | FileCheck %s -check-prefix=ASM
-define hidden i32 @bah(i8* %start) #0 align 2 {
- %1 = ptrtoint i8* %start to i32
+define hidden i32 @bah(ptr %start) #0 align 2 {
+ %1 = ptrtoint ptr %start to i32
%2 = tail call i32 asm sideeffect "@ Enter THUMB Mode\0A\09adr r3, 2f+1 \0A\09bx r3 \0A\09.code 16 \0A2: push {r7} \0A\09mov r7, $4 \0A\09svc 0x0 \0A\09pop {r7} \0A\09", "={r0},{r0},{r1},{r2},r,~{r3}"(i32 %1, i32 %1, i32 0, i32 983042) #3
%3 = add i32 %1, 1
ret i32 %3
diff --git a/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-thumb.ll b/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-thumb.ll
index aca757454772b..3308d5f46478e 100644
--- a/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-thumb.ll
+++ b/llvm/test/CodeGen/ARM/inlineasm-switch-mode-oneway-from-thumb.ll
@@ -2,8 +2,8 @@
;RUN: llc -mtriple=thumbv7-linux-gnueabi < %s | FileCheck %s -check-prefix=ASM
;RUN: llc -mtriple=thumbv7-apple-darwin < %s | FileCheck %s -check-prefix=ASM
-define hidden i32 @bah(i8* %start) #0 align 2 {
- %1 = ptrtoint i8* %start to i32
+define hidden i32 @bah(ptr %start) #0 align 2 {
+ %1 = ptrtoint ptr %start to i32
%2 = tail call i32 asm sideeffect "@ Enter ARM Mode \0A\09adr r3, 1f \0A\09bx r3 \0A\09.align 2 \0A\09.code 32 \0A1: push {r7} \0A\09mov r7, $4 \0A\09svc 0x0 \0A\09pop {r7} \0A\09", "={r0},{r0},{r1},{r2},r,~{r3}"(i32 %1, i32 %1, i32 0, i32 983042) #3
%3 = add i32 %1, 1
ret i32 %3
diff --git a/llvm/test/CodeGen/ARM/inlineasm-switch-mode.ll b/llvm/test/CodeGen/ARM/inlineasm-switch-mode.ll
index 252f5c8d6a77e..c0148d7b35389 100644
--- a/llvm/test/CodeGen/ARM/inlineasm-switch-mode.ll
+++ b/llvm/test/CodeGen/ARM/inlineasm-switch-mode.ll
@@ -1,7 +1,7 @@
;RUN: llc -mtriple=thumbv7-linux-gnueabi < %s | llvm-mc -triple=thumbv7-linux-gnueabi -filetype=obj | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
-define hidden i32 @bah(i8* %start) #0 align 2 {
- %1 = ptrtoint i8* %start to i32
+define hidden i32 @bah(ptr %start) #0 align 2 {
+ %1 = ptrtoint ptr %start to i32
%2 = tail call i32 asm sideeffect "@ Enter ARM Mode \0A\09adr r3, 1f \0A\09bx r3 \0A\09.align 2 \0A\09.code 32 \0A1: push {r7} \0A\09mov r7, $4 \0A\09svc 0x0 \0A\09pop {r7} \0A\09@ Enter THUMB Mode\0A\09adr r3, 2f+1 \0A\09bx r3 \0A\09.code 16 \0A2: \0A\09", "={r0},{r0},{r1},{r2},r,~{r3}"(i32 %1, i32 %1, i32 0, i32 983042) #3
%3 = add i32 %1, 1
ret i32 %3
diff --git a/llvm/test/CodeGen/ARM/inlineasm3.ll b/llvm/test/CodeGen/ARM/inlineasm3.ll
index c318cdfca36ff..5589885bd1745 100644
--- a/llvm/test/CodeGen/ARM/inlineasm3.ll
+++ b/llvm/test/CodeGen/ARM/inlineasm3.ll
@@ -10,7 +10,7 @@ entry:
; CHECK: vmov.32 d30[0],
; CHECK: vmov q8, q15
%tmp = alloca %struct.int32x4_t, align 16
- call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* elementtype(%struct.int32x4_t) %tmp, i32 8192) nounwind
+ call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(ptr elementtype(%struct.int32x4_t) %tmp, i32 8192) nounwind
ret void
}
@@ -27,11 +27,11 @@ entry:
; Radar 9306086
-%0 = type { <8 x i8>, <16 x i8>* }
+%0 = type { <8 x i8>, ptr }
define hidden void @conv4_8_E() nounwind {
entry:
-%asmtmp31 = call %0 asm "vld1.u8 {$0}, [$1:128]!\0A", "=w,=r,1"(<16 x i8>* undef) nounwind
+%asmtmp31 = call %0 asm "vld1.u8 {$0}, [$1:128]!\0A", "=w,=r,1"(ptr undef) nounwind
unreachable
}
@@ -48,7 +48,7 @@ ret i32 0
@k.2126 = internal unnamed_addr global float 1.000000e+00
define i32 @t4() nounwind {
entry:
-call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}"(float* elementtype(float) @k.2126) nounwind
+call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}"(ptr elementtype(float) @k.2126) nounwind
ret i32 0
}
@@ -56,7 +56,7 @@ ret i32 0
define i32 @t5() nounwind {
entry:
-call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* elementtype(float) @k.2126) nounwind
+call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(ptr elementtype(float) @k.2126) nounwind
ret i32 0
}
@@ -102,23 +102,23 @@ entry:
; Radar 9866494
-define void @t10(i8* %f, i32 %g) nounwind {
+define void @t10(ptr %f, i32 %g) nounwind {
entry:
; CHECK: t10
; CHECK: str r1, [r0]
- %f.addr = alloca i8*, align 4
- store i8* %f, i8** %f.addr, align 4
- call void asm "str $1, $0", "=*Q,r"(i8** elementtype(i8*) %f.addr, i32 %g) nounwind
+ %f.addr = alloca ptr, align 4
+ store ptr %f, ptr %f.addr, align 4
+ call void asm "str $1, $0", "=*Q,r"(ptr elementtype(ptr) %f.addr, i32 %g) nounwind
ret void
}
; Radar 10551006
-define <4 x i32> @t11(i32* %p) nounwind {
+define <4 x i32> @t11(ptr %p) nounwind {
entry:
; CHECK: t11
; CHECK: vld1.s32 {d16[], d17[]}, [r0]
- %0 = tail call <4 x i32> asm "vld1.s32 {${0:e}[], ${0:f}[]}, [$1]", "=w,r"(i32* %p) nounwind
+ %0 = tail call <4 x i32> asm "vld1.s32 {${0:e}[], ${0:f}[]}, [$1]", "=w,r"(ptr %p) nounwind
ret <4 x i32> %0
}
@@ -129,6 +129,6 @@ define i32 @fn1() local_unnamed_addr nounwind {
entry:
; CHECK: mov [[addr:r[0-9]+]], #5
; CHECK: ldrh {{.*}}[[addr]]
- %0 = tail call i32 asm "ldrh $0, $1", "=r,*Q"(i8* elementtype(i8) inttoptr (i32 5 to i8*)) nounwind
+ %0 = tail call i32 asm "ldrh $0, $1", "=r,*Q"(ptr elementtype(i8) inttoptr (i32 5 to ptr)) nounwind
ret i32 %0
}
diff --git a/llvm/test/CodeGen/ARM/interrupt-attr.ll b/llvm/test/CodeGen/ARM/interrupt-attr.ll
index 794f672534dc3..f4b920ee521b4 100644
--- a/llvm/test/CodeGen/ARM/interrupt-attr.ll
+++ b/llvm/test/CodeGen/ARM/interrupt-attr.ll
@@ -65,8 +65,8 @@ define arm_aapcscc void @fiq_fn() alignstack(8) "interrupt"="FIQ" {
; CHECK-A-THUMB-LABEL: fiq_fn:
; CHECK-M-LABEL: fiq_fn:
- %val = load volatile [16 x i32], [16 x i32]* @bigvar
- store volatile [16 x i32] %val, [16 x i32]* @bigvar
+ %val = load volatile [16 x i32], ptr @bigvar
+ store volatile [16 x i32] %val, ptr @bigvar
ret void
}
@@ -81,8 +81,8 @@ define arm_aapcscc void @swi_fn() alignstack(8) "interrupt"="SWI" {
; CHECK-A: pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr}
; CHECK-A: subs pc, lr, #0
- %val = load volatile [16 x i32], [16 x i32]* @bigvar
- store volatile [16 x i32] %val, [16 x i32]* @bigvar
+ %val = load volatile [16 x i32], ptr @bigvar
+ store volatile [16 x i32] %val, ptr @bigvar
ret void
}
@@ -126,9 +126,9 @@ define arm_aapcscc void @floating_fn() alignstack(8) "interrupt"="IRQ" {
; CHECK-A-NOT: vstr
; CHECK-A-NOT: vstm
; CHECK-A: vadd.f64 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
- %lhs = load volatile double, double* @var
- %rhs = load volatile double, double* @var
+ %lhs = load volatile double, ptr @var
+ %rhs = load volatile double, ptr @var
%sum = fadd double %lhs, %rhs
- store double %sum, double* @var
+ store double %sum, ptr @var
ret void
}
diff --git a/llvm/test/CodeGen/ARM/interval-update-remat.ll b/llvm/test/CodeGen/ARM/interval-update-remat.ll
index 9d343321d1fe3..2822269d62dff 100644
--- a/llvm/test/CodeGen/ARM/interval-update-remat.ll
+++ b/llvm/test/CodeGen/ARM/interval-update-remat.ll
@@ -17,14 +17,14 @@ target triple = "thumbv7-apple-ios9.0.0"
%class.TestCompletionCallback.9.234.284.1309.2334 = type { %class.TestCompletionCallbackTemplate.8.233.283.1308.2333, i32 }
%class.TestCompletionCallbackTemplate.8.233.283.1308.2333 = type { i32 }
%class.AssertionResult.24.249.299.1324.2349 = type { i8, %class.scoped_ptr.23.248.298.1323.2348 }
-%class.scoped_ptr.23.248.298.1323.2348 = type { %class.Trans_NS___1_basic_string.18.243.293.1318.2343* }
+%class.scoped_ptr.23.248.298.1323.2348 = type { ptr }
%class.Trans_NS___1_basic_string.18.243.293.1318.2343 = type { %class.Trans_NS___1___libcpp_compressed_pair_imp.17.242.292.1317.2342 }
%class.Trans_NS___1___libcpp_compressed_pair_imp.17.242.292.1317.2342 = type { %"struct.Trans_NS___1_basic_string<char, int, int>::__rep.16.241.291.1316.2341" }
%"struct.Trans_NS___1_basic_string<char, int, int>::__rep.16.241.291.1316.2341" = type { %"struct.Trans_NS___1_basic_string<char, int, int>::__long.15.240.290.1315.2340" }
%"struct.Trans_NS___1_basic_string<char, int, int>::__long.15.240.290.1315.2340" = type { i64, i32 }
%class.AssertHelper.10.235.285.1310.2335 = type { i8 }
%class.Message.13.238.288.1313.2338 = type { %class.scoped_ptr.0.12.237.287.1312.2337 }
-%class.scoped_ptr.0.12.237.287.1312.2337 = type { %"class.(anonymous namespace)::basic_stringstream.11.236.286.1311.2336"* }
+%class.scoped_ptr.0.12.237.287.1312.2337 = type { ptr }
%"class.(anonymous namespace)::basic_stringstream.11.236.286.1311.2336" = type { i8 }
%class.scoped_refptr.19.244.294.1319.2344 = type { i8 }
%class.BoundNetLog.20.245.295.1320.2345 = type { i32 }
@@ -35,7 +35,7 @@ target triple = "thumbv7-apple-ios9.0.0"
@.str = private unnamed_addr constant [1 x i8] zeroinitializer, align 1
-define void @_ZN53SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test6m_fn10Ev(%class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326* %this) align 2 {
+define void @_ZN53SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test6m_fn10Ev(ptr %this) align 2 {
entry:
%socket_data = alloca %class.StaticSocketDataProvider.6.231.281.1306.2331, align 1
%agg.tmp = alloca %struct.MockConnect.5.230.280.1305.2330, align 1
@@ -46,14 +46,13 @@ entry:
%ref.tmp = alloca %class.Trans_NS___1_basic_string.18.243.293.1318.2343, align 4
%agg.tmp16 = alloca %class.scoped_refptr.19.244.294.1319.2344, align 1
%agg.tmp18 = alloca %class.BoundNetLog.20.245.295.1320.2345, align 4
- %call2 = call %class.StaticSocketDataProvider.6.231.281.1306.2331* @_ZN24StaticSocketDataProviderC1EP13MockReadWritejS1_j(%class.StaticSocketDataProvider.6.231.281.1306.2331* nonnull %socket_data, %struct.MockReadWrite.7.232.282.1307.2332* undef, i32 1, %struct.MockReadWrite.7.232.282.1307.2332* null, i32 0)
- %call3 = call %struct.MockConnect.5.230.280.1305.2330* @_ZN11MockConnectC1Ev(%struct.MockConnect.5.230.280.1305.2330* nonnull %agg.tmp)
- call void @_ZN24StaticSocketDataProvider5m_fn8E11MockConnect(%class.StaticSocketDataProvider.6.231.281.1306.2331* nonnull %socket_data, %struct.MockConnect.5.230.280.1305.2330* nonnull %agg.tmp)
- %call5 = call %class.TestCompletionCallback.9.234.284.1309.2334* @_ZN22TestCompletionCallbackC1Ev(%class.TestCompletionCallback.9.234.284.1309.2334* nonnull %callback)
- %transport_socket_pool_ = getelementptr inbounds %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326, %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326* %this, i32 0, i32 0
- %call6 = call i32 @_ZN29MockTransportClientSocketPool5m_fn9Ev(%class.MockTransportClientSocketPool.0.225.275.1300.2325* %transport_socket_pool_)
- call void @_Z11CmpHelperEQPcS_xx(%class.AssertionResult.24.249.299.1324.2349* nonnull sret(%class.AssertionResult.24.249.299.1324.2349) %gtest_ar, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i64 0, i64 undef)
- %tmp = load i8, i8* undef, align 4
+ %call2 = call ptr @_ZN24StaticSocketDataProviderC1EP13MockReadWritejS1_j(ptr nonnull %socket_data, ptr undef, i32 1, ptr null, i32 0)
+ %call3 = call ptr @_ZN11MockConnectC1Ev(ptr nonnull %agg.tmp)
+ call void @_ZN24StaticSocketDataProvider5m_fn8E11MockConnect(ptr nonnull %socket_data, ptr nonnull %agg.tmp)
+ %call5 = call ptr @_ZN22TestCompletionCallbackC1Ev(ptr nonnull %callback)
+ %call6 = call i32 @_ZN29MockTransportClientSocketPool5m_fn9Ev(ptr %this)
+ call void @_Z11CmpHelperEQPcS_xx(ptr nonnull sret(%class.AssertionResult.24.249.299.1324.2349) %gtest_ar, ptr @.str, ptr @.str, i64 0, i64 undef)
+ %tmp = load i8, ptr undef, align 4
%tobool.i = icmp eq i8 %tmp, 0
br i1 %tobool.i, label %if.else, label %if.end
@@ -61,102 +60,100 @@ if.else: ; preds = %entry
br i1 undef, label %_ZN15AssertionResult5m_fn6Ev.exit, label %cond.true.i
cond.true.i: ; preds = %if.else
- %call4.i = call i8* @_ZN25Trans_NS___1_basic_stringIciiE5m_fn1Ev(%class.Trans_NS___1_basic_string.18.243.293.1318.2343* nonnull undef)
+ %call4.i = call ptr @_ZN25Trans_NS___1_basic_stringIciiE5m_fn1Ev(ptr nonnull undef)
br label %_ZN15AssertionResult5m_fn6Ev.exit
_ZN15AssertionResult5m_fn6Ev.exit: ; preds = %cond.true.i, %if.else
- %cond.i = phi i8* [ %call4.i, %cond.true.i ], [ getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), %if.else ]
- %call9 = call %class.AssertHelper.10.235.285.1310.2335* @_ZN12AssertHelperC1EPKc(%class.AssertHelper.10.235.285.1310.2335* nonnull %temp.lvalue, i8* %cond.i)
- %call11 = call %class.Message.13.238.288.1313.2338* @_ZN7MessageC1Ev(%class.Message.13.238.288.1313.2338* nonnull %agg.tmp10)
- call void @_ZN12AssertHelperaSE7Message(%class.AssertHelper.10.235.285.1310.2335* nonnull %temp.lvalue, %class.Message.13.238.288.1313.2338* nonnull %agg.tmp10)
+ %cond.i = phi ptr [ %call4.i, %cond.true.i ], [ @.str, %if.else ]
+ %call9 = call ptr @_ZN12AssertHelperC1EPKc(ptr nonnull %temp.lvalue, ptr %cond.i)
+ %call11 = call ptr @_ZN7MessageC1Ev(ptr nonnull %agg.tmp10)
+ call void @_ZN12AssertHelperaSE7Message(ptr nonnull %temp.lvalue, ptr nonnull %agg.tmp10)
%call.i.i.i.i27 = call zeroext i1 @_Z6IsTruev()
%brmerge = or i1 false, undef
br i1 %brmerge, label %_ZN7MessageD1Ev.exit33, label %delete.notnull.i.i.i.i32
delete.notnull.i.i.i.i32: ; preds = %_ZN15AssertionResult5m_fn6Ev.exit
- %call.i.i.i.i.i.i31 = call %"class.(anonymous namespace)::basic_iostream.22.247.297.1322.2347"* @_ZN12_GLOBAL__N_114basic_iostreamD2Ev(%"class.(anonymous namespace)::basic_iostream.22.247.297.1322.2347"* undef)
- call void @_ZdlPv(i8* undef)
+ %call.i.i.i.i.i.i31 = call ptr @_ZN12_GLOBAL__N_114basic_iostreamD2Ev(ptr undef)
+ call void @_ZdlPv(ptr undef)
br label %_ZN7MessageD1Ev.exit33
_ZN7MessageD1Ev.exit33: ; preds = %delete.notnull.i.i.i.i32, %_ZN15AssertionResult5m_fn6Ev.exit
- %call13 = call %class.AssertHelper.10.235.285.1310.2335* @_ZN12AssertHelperD1Ev(%class.AssertHelper.10.235.285.1310.2335* nonnull %temp.lvalue)
+ %call13 = call ptr @_ZN12AssertHelperD1Ev(ptr nonnull %temp.lvalue)
br label %if.end
if.end: ; preds = %_ZN7MessageD1Ev.exit33, %entry
- %message_.i.i = getelementptr inbounds %class.AssertionResult.24.249.299.1324.2349, %class.AssertionResult.24.249.299.1324.2349* %gtest_ar, i32 0, i32 1
- %call.i.i.i = call %class.scoped_ptr.23.248.298.1323.2348* @_ZN10scoped_ptrI25Trans_NS___1_basic_stringIciiEED2Ev(%class.scoped_ptr.23.248.298.1323.2348* %message_.i.i)
- call void @llvm.memset.p0i8.i32(i8* align 4 null, i8 0, i32 12, i1 false)
- call void @_ZN25Trans_NS___1_basic_stringIciiE5m_fn2Ev(%class.Trans_NS___1_basic_string.18.243.293.1318.2343* nonnull %ref.tmp)
- call void @_Z19CreateSOCKSv5Paramsv(%class.scoped_refptr.19.244.294.1319.2344* nonnull sret(%class.scoped_refptr.19.244.294.1319.2344) %agg.tmp16)
- %callback_.i = getelementptr inbounds %class.TestCompletionCallback.9.234.284.1309.2334, %class.TestCompletionCallback.9.234.284.1309.2334* %callback, i32 0, i32 1
- %pool_ = getelementptr inbounds %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326, %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326* %this, i32 0, i32 1
- %tmp1 = getelementptr inbounds %class.BoundNetLog.20.245.295.1320.2345, %class.BoundNetLog.20.245.295.1320.2345* %agg.tmp18, i32 0, i32 0
- store i32 0, i32* %tmp1, align 4
- call void @_ZN18ClientSocketHandle5m_fn3IPiEEvRK25Trans_NS___1_basic_stringIciiE13scoped_refptr15RequestPriorityN16ClientSocketPool13RespectLimitsERiT_11BoundNetLog(%class.ClientSocketHandle.14.239.289.1314.2339* nonnull undef, %class.Trans_NS___1_basic_string.18.243.293.1318.2343* nonnull dereferenceable(12) %ref.tmp, %class.scoped_refptr.19.244.294.1319.2344* nonnull %agg.tmp16, i32 0, i32 1, i32* nonnull dereferenceable(4) %callback_.i, i32* %pool_, %class.BoundNetLog.20.245.295.1320.2345* nonnull %agg.tmp18)
- %call19 = call %class.BoundNetLog.20.245.295.1320.2345* @_ZN11BoundNetLogD1Ev(%class.BoundNetLog.20.245.295.1320.2345* nonnull %agg.tmp18)
- call void @_Z11CmpHelperEQPcS_xx(%class.AssertionResult.24.249.299.1324.2349* nonnull sret(%class.AssertionResult.24.249.299.1324.2349) undef, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i64 -1, i64 0)
+ %message_.i.i = getelementptr inbounds %class.AssertionResult.24.249.299.1324.2349, ptr %gtest_ar, i32 0, i32 1
+ %call.i.i.i = call ptr @_ZN10scoped_ptrI25Trans_NS___1_basic_stringIciiEED2Ev(ptr %message_.i.i)
+ call void @llvm.memset.p0.i32(ptr align 4 null, i8 0, i32 12, i1 false)
+ call void @_ZN25Trans_NS___1_basic_stringIciiE5m_fn2Ev(ptr nonnull %ref.tmp)
+ call void @_Z19CreateSOCKSv5Paramsv(ptr nonnull sret(%class.scoped_refptr.19.244.294.1319.2344) %agg.tmp16)
+ %callback_.i = getelementptr inbounds %class.TestCompletionCallback.9.234.284.1309.2334, ptr %callback, i32 0, i32 1
+ %pool_ = getelementptr inbounds %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326, ptr %this, i32 0, i32 1
+ store i32 0, ptr %agg.tmp18, align 4
+ call void @_ZN18ClientSocketHandle5m_fn3IPiEEvRK25Trans_NS___1_basic_stringIciiE13scoped_refptr15RequestPriorityN16ClientSocketPool13RespectLimitsERiT_11BoundNetLog(ptr nonnull undef, ptr nonnull dereferenceable(12) %ref.tmp, ptr nonnull %agg.tmp16, i32 0, i32 1, ptr nonnull dereferenceable(4) %callback_.i, ptr %pool_, ptr nonnull %agg.tmp18)
+ %call19 = call ptr @_ZN11BoundNetLogD1Ev(ptr nonnull %agg.tmp18)
+ call void @_Z11CmpHelperEQPcS_xx(ptr nonnull sret(%class.AssertionResult.24.249.299.1324.2349) undef, ptr @.str, ptr @.str, i64 -1, i64 0)
br i1 undef, label %if.then.i.i.i.i, label %_ZN7MessageD1Ev.exit
if.then.i.i.i.i: ; preds = %if.end
- %tmp2 = load %"class.(anonymous namespace)::basic_stringstream.11.236.286.1311.2336"*, %"class.(anonymous namespace)::basic_stringstream.11.236.286.1311.2336"** undef, align 4
+ %tmp2 = load ptr, ptr undef, align 4
br label %_ZN7MessageD1Ev.exit
_ZN7MessageD1Ev.exit: ; preds = %if.then.i.i.i.i, %if.end
- %connect_.i.i = getelementptr inbounds %class.StaticSocketDataProvider.6.231.281.1306.2331, %class.StaticSocketDataProvider.6.231.281.1306.2331* %socket_data, i32 0, i32 1
- %tmp3 = bitcast %struct.MockConnect.5.230.280.1305.2330* %connect_.i.i to %"class.(anonymous namespace)::__vector_base.21.246.296.1321.2346"*
- %call.i.i.i.i.i.i.i.i.i.i = call %"class.(anonymous namespace)::__vector_base.21.246.296.1321.2346"* @_ZN12_GLOBAL__N_113__vector_baseD2Ev(%"class.(anonymous namespace)::__vector_base.21.246.296.1321.2346"* %tmp3)
+ %connect_.i.i = getelementptr inbounds %class.StaticSocketDataProvider.6.231.281.1306.2331, ptr %socket_data, i32 0, i32 1
+ %call.i.i.i.i.i.i.i.i.i.i = call ptr @_ZN12_GLOBAL__N_113__vector_baseD2Ev(ptr %connect_.i.i)
ret void
}
; Function Attrs: argmemonly nounwind
-declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #0
+declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #0
-declare %class.StaticSocketDataProvider.6.231.281.1306.2331* @_ZN24StaticSocketDataProviderC1EP13MockReadWritejS1_j(%class.StaticSocketDataProvider.6.231.281.1306.2331* returned, %struct.MockReadWrite.7.232.282.1307.2332*, i32, %struct.MockReadWrite.7.232.282.1307.2332*, i32) unnamed_addr
+declare ptr @_ZN24StaticSocketDataProviderC1EP13MockReadWritejS1_j(ptr returned, ptr, i32, ptr, i32) unnamed_addr
-declare void @_ZN24StaticSocketDataProvider5m_fn8E11MockConnect(%class.StaticSocketDataProvider.6.231.281.1306.2331*, %struct.MockConnect.5.230.280.1305.2330*)
+declare void @_ZN24StaticSocketDataProvider5m_fn8E11MockConnect(ptr, ptr)
-declare %struct.MockConnect.5.230.280.1305.2330* @_ZN11MockConnectC1Ev(%struct.MockConnect.5.230.280.1305.2330* returned) unnamed_addr
+declare ptr @_ZN11MockConnectC1Ev(ptr returned) unnamed_addr
-declare %class.TestCompletionCallback.9.234.284.1309.2334* @_ZN22TestCompletionCallbackC1Ev(%class.TestCompletionCallback.9.234.284.1309.2334* returned) unnamed_addr
+declare ptr @_ZN22TestCompletionCallbackC1Ev(ptr returned) unnamed_addr
-declare i32 @_ZN29MockTransportClientSocketPool5m_fn9Ev(%class.MockTransportClientSocketPool.0.225.275.1300.2325*)
+declare i32 @_ZN29MockTransportClientSocketPool5m_fn9Ev(ptr)
-declare %class.AssertHelper.10.235.285.1310.2335* @_ZN12AssertHelperC1EPKc(%class.AssertHelper.10.235.285.1310.2335* returned, i8*) unnamed_addr
+declare ptr @_ZN12AssertHelperC1EPKc(ptr returned, ptr) unnamed_addr
-declare void @_ZN12AssertHelperaSE7Message(%class.AssertHelper.10.235.285.1310.2335*, %class.Message.13.238.288.1313.2338*)
+declare void @_ZN12AssertHelperaSE7Message(ptr, ptr)
-declare %class.Message.13.238.288.1313.2338* @_ZN7MessageC1Ev(%class.Message.13.238.288.1313.2338* returned) unnamed_addr
+declare ptr @_ZN7MessageC1Ev(ptr returned) unnamed_addr
-declare %class.AssertHelper.10.235.285.1310.2335* @_ZN12AssertHelperD1Ev(%class.AssertHelper.10.235.285.1310.2335* returned) unnamed_addr
+declare ptr @_ZN12AssertHelperD1Ev(ptr returned) unnamed_addr
; Function Attrs: argmemonly nounwind
-declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #0
+declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #0
-declare void @_ZN18ClientSocketHandle5m_fn3IPiEEvRK25Trans_NS___1_basic_stringIciiE13scoped_refptr15RequestPriorityN16ClientSocketPool13RespectLimitsERiT_11BoundNetLog(%class.ClientSocketHandle.14.239.289.1314.2339*, %class.Trans_NS___1_basic_string.18.243.293.1318.2343* dereferenceable(12), %class.scoped_refptr.19.244.294.1319.2344*, i32, i32, i32* dereferenceable(4), i32*, %class.BoundNetLog.20.245.295.1320.2345*)
+declare void @_ZN18ClientSocketHandle5m_fn3IPiEEvRK25Trans_NS___1_basic_stringIciiE13scoped_refptr15RequestPriorityN16ClientSocketPool13RespectLimitsERiT_11BoundNetLog(ptr, ptr dereferenceable(12), ptr, i32, i32, ptr dereferenceable(4), ptr, ptr)
-declare void @_Z19CreateSOCKSv5Paramsv(%class.scoped_refptr.19.244.294.1319.2344* sret(%class.scoped_refptr.19.244.294.1319.2344))
+declare void @_Z19CreateSOCKSv5Paramsv(ptr sret(%class.scoped_refptr.19.244.294.1319.2344))
; Function Attrs: argmemonly nounwind
-declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) #0
+declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) #0
-declare %class.BoundNetLog.20.245.295.1320.2345* @_ZN11BoundNetLogD1Ev(%class.BoundNetLog.20.245.295.1320.2345* returned) unnamed_addr
+declare ptr @_ZN11BoundNetLogD1Ev(ptr returned) unnamed_addr
-declare %class.scoped_refptr.19.244.294.1319.2344* @_ZN13scoped_refptrD1Ev(%class.scoped_refptr.19.244.294.1319.2344* returned) unnamed_addr
+declare ptr @_ZN13scoped_refptrD1Ev(ptr returned) unnamed_addr
-declare %"class.(anonymous namespace)::__vector_base.21.246.296.1321.2346"* @_ZN12_GLOBAL__N_113__vector_baseD2Ev(%"class.(anonymous namespace)::__vector_base.21.246.296.1321.2346"* returned) unnamed_addr
+declare ptr @_ZN12_GLOBAL__N_113__vector_baseD2Ev(ptr returned) unnamed_addr
-declare i8* @_ZN25Trans_NS___1_basic_stringIciiE5m_fn1Ev(%class.Trans_NS___1_basic_string.18.243.293.1318.2343*)
+declare ptr @_ZN25Trans_NS___1_basic_stringIciiE5m_fn1Ev(ptr)
declare zeroext i1 @_Z6IsTruev()
-declare void @_ZdlPv(i8*)
+declare void @_ZdlPv(ptr)
-declare %"class.(anonymous namespace)::basic_iostream.22.247.297.1322.2347"* @_ZN12_GLOBAL__N_114basic_iostreamD2Ev(%"class.(anonymous namespace)::basic_iostream.22.247.297.1322.2347"* returned) unnamed_addr
+declare ptr @_ZN12_GLOBAL__N_114basic_iostreamD2Ev(ptr returned) unnamed_addr
-declare %class.scoped_ptr.23.248.298.1323.2348* @_ZN10scoped_ptrI25Trans_NS___1_basic_stringIciiEED2Ev(%class.scoped_ptr.23.248.298.1323.2348* readonly returned) unnamed_addr align 2
+declare ptr @_ZN10scoped_ptrI25Trans_NS___1_basic_stringIciiEED2Ev(ptr readonly returned) unnamed_addr align 2
-declare void @_Z11CmpHelperEQPcS_xx(%class.AssertionResult.24.249.299.1324.2349* sret(%class.AssertionResult.24.249.299.1324.2349), i8*, i8*, i64, i64)
+declare void @_Z11CmpHelperEQPcS_xx(ptr sret(%class.AssertionResult.24.249.299.1324.2349), ptr, ptr, i64, i64)
-declare void @_ZN25Trans_NS___1_basic_stringIciiE5m_fn2Ev(%class.Trans_NS___1_basic_string.18.243.293.1318.2343*)
+declare void @_ZN25Trans_NS___1_basic_stringIciiE5m_fn2Ev(ptr)
attributes #0 = { argmemonly nounwind }
diff --git a/llvm/test/CodeGen/ARM/intrinsics-cmse.ll b/llvm/test/CodeGen/ARM/intrinsics-cmse.ll
index be4fed19665a5..b07e908d948ad 100644
--- a/llvm/test/CodeGen/ARM/intrinsics-cmse.ll
+++ b/llvm/test/CodeGen/ARM/intrinsics-cmse.ll
@@ -1,45 +1,45 @@
; RUN: llc < %s -mtriple=thumbv8m.base | FileCheck %s
; RUN: llc < %s -mtriple=thumbebv8m.base | FileCheck %s
-define i32 @test_tt(i8* readnone %p) #0 {
+define i32 @test_tt(ptr readnone %p) #0 {
entry:
- %0 = tail call i32 @llvm.arm.cmse.tt(i8* %p)
+ %0 = tail call i32 @llvm.arm.cmse.tt(ptr %p)
ret i32 %0
}
; CHECK-LABEL: test_tt:
; CHECK: tt r{{[0-9]+}}, r{{[0-9]+}}
-declare i32 @llvm.arm.cmse.tt(i8*) #1
+declare i32 @llvm.arm.cmse.tt(ptr) #1
-define i32 @test_ttt(i8* readnone %p) #0 {
+define i32 @test_ttt(ptr readnone %p) #0 {
entry:
- %0 = tail call i32 @llvm.arm.cmse.ttt(i8* %p)
+ %0 = tail call i32 @llvm.arm.cmse.ttt(ptr %p)
ret i32 %0
}
; CHECK-LABEL: test_ttt:
; CHECK: ttt r{{[0-9]+}}, r{{[0-9]+}}
-declare i32 @llvm.arm.cmse.ttt(i8*) #1
+declare i32 @llvm.arm.cmse.ttt(ptr) #1
-define i32 @test_tta(i8* readnone %p) #0 {
+define i32 @test_tta(ptr readnone %p) #0 {
entry:
- %0 = tail call i32 @llvm.arm.cmse.tta(i8* %p)
+ %0 = tail call i32 @llvm.arm.cmse.tta(ptr %p)
ret i32 %0
}
; CHECK-LABEL: test_tta:
; CHECK: tta r{{[0-9]+}}, r{{[0-9]+}}
-declare i32 @llvm.arm.cmse.tta(i8*) #1
+declare i32 @llvm.arm.cmse.tta(ptr) #1
-define i32 @test_ttat(i8* readnone %p) #0 {
+define i32 @test_ttat(ptr readnone %p) #0 {
entry:
- %0 = tail call i32 @llvm.arm.cmse.ttat(i8* %p)
+ %0 = tail call i32 @llvm.arm.cmse.ttat(ptr %p)
ret i32 %0
}
; CHECK-LABEL: test_ttat:
; CHECK: ttat r{{[0-9]+}}, r{{[0-9]+}}
-declare i32 @llvm.arm.cmse.ttat(i8*) #1
+declare i32 @llvm.arm.cmse.ttat(ptr) #1
attributes #0 = { nounwind readnone "target-features"="+8msecext"}
attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll b/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll
index 5352471238f9c..75c3ca26d12bb 100644
--- a/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll
+++ b/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s
-define void @coproc(i8* %i) nounwind {
+define void @coproc(ptr %i) nounwind {
entry:
; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4
%0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
@@ -19,21 +19,21 @@ entry:
; CHECK: cdp2 p7, #3, c1, c1, c1, #5
tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
; CHECK: ldc p7, c3, [r{{[0-9]+}}]
- tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind
+ tail call void @llvm.arm.ldc(i32 7, i32 3, ptr %i) nounwind
; CHECK: ldcl p7, c3, [r{{[0-9]+}}]
- tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind
+ tail call void @llvm.arm.ldcl(i32 7, i32 3, ptr %i) nounwind
; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
- tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind
+ tail call void @llvm.arm.ldc2(i32 7, i32 3, ptr %i) nounwind
; CHECK: ldc2l p7, c3, [r{{[0-9]+}}]
- tail call void @llvm.arm.ldc2l(i32 7, i32 3, i8* %i) nounwind
+ tail call void @llvm.arm.ldc2l(i32 7, i32 3, ptr %i) nounwind
; CHECK: stc p7, c3, [r{{[0-9]+}}]
- tail call void @llvm.arm.stc(i32 7, i32 3, i8* %i) nounwind
+ tail call void @llvm.arm.stc(i32 7, i32 3, ptr %i) nounwind
; CHECK: stcl p7, c3, [r{{[0-9]+}}]
- tail call void @llvm.arm.stcl(i32 7, i32 3, i8* %i) nounwind
+ tail call void @llvm.arm.stcl(i32 7, i32 3, ptr %i) nounwind
; CHECK: stc2 p7, c3, [r{{[0-9]+}}]
- tail call void @llvm.arm.stc2(i32 7, i32 3, i8* %i) nounwind
+ tail call void @llvm.arm.stc2(i32 7, i32 3, ptr %i) nounwind
; CHECK: stc2l p7, c3, [r{{[0-9]+}}]
- tail call void @llvm.arm.stc2l(i32 7, i32 3, i8* %i) nounwind
+ tail call void @llvm.arm.stc2l(i32 7, i32 3, ptr %i) nounwind
; CHECK: mrrc p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3
%2 = tail call { i32, i32 } @llvm.arm.mrrc(i32 1, i32 2, i32 3) nounwind
; CHECK: mrrc2 p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3
@@ -41,21 +41,21 @@ entry:
ret void
}
-declare void @llvm.arm.ldc(i32, i32, i8*) nounwind
+declare void @llvm.arm.ldc(i32, i32, ptr) nounwind
-declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind
+declare void @llvm.arm.ldcl(i32, i32, ptr) nounwind
-declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
+declare void @llvm.arm.ldc2(i32, i32, ptr) nounwind
-declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
+declare void @llvm.arm.ldc2l(i32, i32, ptr) nounwind
-declare void @llvm.arm.stc(i32, i32, i8*) nounwind
+declare void @llvm.arm.stc(i32, i32, ptr) nounwind
-declare void @llvm.arm.stcl(i32, i32, i8*) nounwind
+declare void @llvm.arm.stcl(i32, i32, ptr) nounwind
-declare void @llvm.arm.stc2(i32, i32, i8*) nounwind
+declare void @llvm.arm.stc2(i32, i32, ptr) nounwind
-declare void @llvm.arm.stc2l(i32, i32, i8*) nounwind
+declare void @llvm.arm.stc2l(i32, i32, ptr) nounwind
declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/intrinsics-crypto.ll b/llvm/test/CodeGen/ARM/intrinsics-crypto.ll
index 6e5efd85a347b..bb54f6b81b483 100644
--- a/llvm/test/CodeGen/ARM/intrinsics-crypto.ll
+++ b/llvm/test/CodeGen/ARM/intrinsics-crypto.ll
@@ -1,8 +1,8 @@
; RUN: llc < %s -mtriple=armv8 -mattr=+crypto | FileCheck %s
-define arm_aapcs_vfpcc <16 x i8> @test_aesde(<16 x i8>* %a, <16 x i8> *%b) {
- %tmp = load <16 x i8>, <16 x i8>* %a
- %tmp2 = load <16 x i8>, <16 x i8>* %b
+define arm_aapcs_vfpcc <16 x i8> @test_aesde(ptr %a, ptr %b) {
+ %tmp = load <16 x i8>, ptr %a
+ %tmp2 = load <16 x i8>, ptr %b
%tmp3 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %tmp, <16 x i8> %tmp2)
; CHECK: aesd.8 q{{[0-9]+}}, q{{[0-9]+}}
%tmp4 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %tmp3, <16 x i8> %tmp2)
@@ -14,10 +14,10 @@ define arm_aapcs_vfpcc <16 x i8> @test_aesde(<16 x i8>* %a, <16 x i8> *%b) {
ret <16 x i8> %tmp6
}
-define arm_aapcs_vfpcc <4 x i32> @test_sha(<4 x i32> *%a, <4 x i32> *%b, <4 x i32> *%c) {
- %tmp = load <4 x i32>, <4 x i32>* %a
- %tmp2 = load <4 x i32>, <4 x i32>* %b
- %tmp3 = load <4 x i32>, <4 x i32>* %c
+define arm_aapcs_vfpcc <4 x i32> @test_sha(ptr %a, ptr %b, ptr %c) {
+ %tmp = load <4 x i32>, ptr %a
+ %tmp2 = load <4 x i32>, ptr %b
+ %tmp3 = load <4 x i32>, ptr %c
%scalar = extractelement <4 x i32> %tmp, i32 0
%resscalar = call i32 @llvm.arm.neon.sha1h(i32 %scalar)
%res1 = insertelement <4 x i32> undef, i32 %resscalar, i32 0
diff --git a/llvm/test/CodeGen/ARM/intrinsics-memory-barrier.ll b/llvm/test/CodeGen/ARM/intrinsics-memory-barrier.ll
index 5626d38aae4b4..56a3e53a49c2f 100644
--- a/llvm/test/CodeGen/ARM/intrinsics-memory-barrier.ll
+++ b/llvm/test/CodeGen/ARM/intrinsics-memory-barrier.ll
@@ -13,39 +13,39 @@ define void @test() {
; instructions around DMB.
; Failure to do so, two STRs will collapse into one STRD.
; CHECK-LABEL: test_dmb_reordering
-define void @test_dmb_reordering(i32 %a, i32 %b, i32* %d) {
- store i32 %a, i32* %d ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}]
+define void @test_dmb_reordering(i32 %a, i32 %b, ptr %d) {
+ store i32 %a, ptr %d ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}]
call void @llvm.arm.dmb(i32 15) ; CHECK: dmb sy
- %d1 = getelementptr i32, i32* %d, i32 1
- store i32 %b, i32* %d1 ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4]
+ %d1 = getelementptr i32, ptr %d, i32 1
+ store i32 %b, ptr %d1 ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4]
ret void
}
; Similarly for DSB.
; CHECK-LABEL: test_dsb_reordering
-define void @test_dsb_reordering(i32 %a, i32 %b, i32* %d) {
- store i32 %a, i32* %d ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}]
+define void @test_dsb_reordering(i32 %a, i32 %b, ptr %d) {
+ store i32 %a, ptr %d ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}]
call void @llvm.arm.dsb(i32 15) ; CHECK: dsb sy
- %d1 = getelementptr i32, i32* %d, i32 1
- store i32 %b, i32* %d1 ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4]
+ %d1 = getelementptr i32, ptr %d, i32 1
+ store i32 %b, ptr %d1 ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4]
ret void
}
; And ISB.
; CHECK-LABEL: test_isb_reordering
-define void @test_isb_reordering(i32 %a, i32 %b, i32* %d) {
- store i32 %a, i32* %d ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}]
+define void @test_isb_reordering(i32 %a, i32 %b, ptr %d) {
+ store i32 %a, ptr %d ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}]
call void @llvm.arm.isb(i32 15) ; CHECK: isb sy
- %d1 = getelementptr i32, i32* %d, i32 1
- store i32 %b, i32* %d1 ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4]
+ %d1 = getelementptr i32, ptr %d, i32 1
+ store i32 %b, ptr %d1 ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4]
ret void
}
diff --git a/llvm/test/CodeGen/ARM/invoke-donothing-assert.ll b/llvm/test/CodeGen/ARM/invoke-donothing-assert.ll
index c6489e3a4ce50..02474b723acf2 100644
--- a/llvm/test/CodeGen/ARM/invoke-donothing-assert.ll
+++ b/llvm/test/CodeGen/ARM/invoke-donothing-assert.ll
@@ -4,7 +4,7 @@
; <rdar://problem/13228754> & <rdar://problem/13316637>
; CHECK: .globl _foo
-define void @foo() personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
+define void @foo() personality ptr @__gxx_personality_sj0 {
invoke.cont:
invoke void @callA()
to label %invoke.cont25 unwind label %lpad2
@@ -20,21 +20,21 @@ invoke.cont75:
ret void
lpad2:
- %0 = landingpad { i8*, i32 }
+ %0 = landingpad { ptr, i32 }
cleanup
br label %eh.resume
lpad15:
- %1 = landingpad { i8*, i32 }
+ %1 = landingpad { ptr, i32 }
cleanup
br label %eh.resume
eh.resume:
- resume { i8*, i32 } zeroinitializer
+ resume { ptr, i32 } zeroinitializer
}
; CHECK: .globl _bar
-define linkonce_odr void @bar(i32* %a) personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
+define linkonce_odr void @bar(ptr %a) personality ptr @__gxx_personality_sj0 {
if.end.i.i.i:
invoke void @llvm.donothing()
to label %call.i.i.i.noexc unwind label %eh.resume
@@ -46,9 +46,9 @@ new.notnull.i.i:
br label %cleanup
cleanup:
- %0 = load i32, i32* %a, align 4
+ %0 = load i32, ptr %a, align 4
%inc294 = add nsw i32 %0, 4
- store i32 %inc294, i32* %a, align 4
+ store i32 %inc294, ptr %a, align 4
br i1 false, label %_ZN3lol5ArrayIivvvvvvvED1Ev.exit, label %delete.notnull.i.i.i1409
delete.notnull.i.i.i1409:
@@ -58,13 +58,13 @@ _ZN3lol5ArrayIivvvvvvvED1Ev.exit:
ret void
eh.resume:
- %1 = landingpad { i8*, i32 }
+ %1 = landingpad { ptr, i32 }
cleanup
- %2 = extractvalue { i8*, i32 } %1, 0
- %3 = extractvalue { i8*, i32 } %1, 1
- %lpad.val = insertvalue { i8*, i32 } undef, i8* %2, 0
- %lpad.val395 = insertvalue { i8*, i32 } %lpad.val, i32 %3, 1
- resume { i8*, i32 } %lpad.val395
+ %2 = extractvalue { ptr, i32 } %1, 0
+ %3 = extractvalue { ptr, i32 } %1, 1
+ %lpad.val = insertvalue { ptr, i32 } undef, ptr %2, 0
+ %lpad.val395 = insertvalue { ptr, i32 } %lpad.val, i32 %3, 1
+ resume { ptr, i32 } %lpad.val395
}
declare void @callA()
diff --git a/llvm/test/CodeGen/ARM/ipra-reg-usage.ll b/llvm/test/CodeGen/ARM/ipra-reg-usage.ll
index 03a85d8a183a0..c92839020f832 100644
--- a/llvm/test/CodeGen/ARM/ipra-reg-usage.ll
+++ b/llvm/test/CodeGen/ARM/ipra-reg-usage.ll
@@ -12,7 +12,7 @@ define void @foo()#0 {
ret void
}
- at llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @foo to i8*)]
+ at llvm.used = appending global [1 x ptr] [ptr @foo]
declare void @bar2()
attributes #0 = {nounwind}
diff --git a/llvm/test/CodeGen/ARM/isel-v8i32-crash.ll b/llvm/test/CodeGen/ARM/isel-v8i32-crash.ll
index 57279d0ba9832..27534a6d2c587 100644
--- a/llvm/test/CodeGen/ARM/isel-v8i32-crash.ll
+++ b/llvm/test/CodeGen/ARM/isel-v8i32-crash.ll
@@ -12,14 +12,12 @@ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
; CHECK: func:
; CHECK: vcvt.s32.f32 q[[R:[0-9]]], q[[R]], #3
-define void @func(i16* nocapture %pb, float* nocapture readonly %pf) #0 {
+define void @func(ptr nocapture %pb, ptr nocapture readonly %pf) #0 {
entry:
- %0 = bitcast float* %pf to <8 x float>*
- %1 = load <8 x float>, <8 x float>* %0, align 4
- %2 = fmul <8 x float> %1, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
- %3 = fptosi <8 x float> %2 to <8 x i16>
- %4 = bitcast i16* %pb to <8 x i16>*
- store <8 x i16> %3, <8 x i16>* %4, align 2
+ %0 = load <8 x float>, ptr %pf, align 4
+ %1 = fmul <8 x float> %0, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
+ %2 = fptosi <8 x float> %1 to <8 x i16>
+ store <8 x i16> %2, ptr %pb, align 2
ret void
}
diff --git a/llvm/test/CodeGen/ARM/krait-cpu-div-attribute.ll b/llvm/test/CodeGen/ARM/krait-cpu-div-attribute.ll
index 5b589ab979c58..f4844bbb90307 100644
--- a/llvm/test/CodeGen/ARM/krait-cpu-div-attribute.ll
+++ b/llvm/test/CodeGen/ARM/krait-cpu-div-attribute.ll
@@ -25,12 +25,12 @@ entry:
%a = alloca i32, align 4
%b = alloca i32, align 4
%c = alloca i32, align 4
- store i32 0, i32* %retval
- store volatile i32 100, i32* %b, align 4
- store volatile i32 32, i32* %c, align 4
- %0 = load volatile i32, i32* %b, align 4
- %1 = load volatile i32, i32* %c, align 4
+ store i32 0, ptr %retval
+ store volatile i32 100, ptr %b, align 4
+ store volatile i32 32, ptr %c, align 4
+ %0 = load volatile i32, ptr %b, align 4
+ %1 = load volatile i32, ptr %c, align 4
%div = sdiv i32 %0, %1
- store volatile i32 %div, i32* %a, align 4
+ store volatile i32 %div, ptr %a, align 4
ret i32 0
}
diff --git a/llvm/test/CodeGen/ARM/large-stack.ll b/llvm/test/CodeGen/ARM/large-stack.ll
index e2d4de341ec23..52a006bd5a116 100644
--- a/llvm/test/CodeGen/ARM/large-stack.ll
+++ b/llvm/test/CodeGen/ARM/large-stack.ll
@@ -14,7 +14,7 @@ define i32 @test3() {
%retval = alloca i32, align 4
%tmp = alloca i32, align 4
%a = alloca [805306369 x i8], align 16
- store i32 0, i32* %tmp
- %tmp1 = load i32, i32* %tmp
+ store i32 0, ptr %tmp
+ %tmp1 = load i32, ptr %tmp
ret i32 %tmp1
}
diff --git a/llvm/test/CodeGen/ARM/ldaex-stlex.ll b/llvm/test/CodeGen/ARM/ldaex-stlex.ll
index fc9dded9e875d..6f45a5076f6a3 100644
--- a/llvm/test/CodeGen/ARM/ldaex-stlex.ll
+++ b/llvm/test/CodeGen/ARM/ldaex-stlex.ll
@@ -5,9 +5,9 @@
; CHECK-LABEL: f0:
; CHECK: ldaexd
-define i64 @f0(i8* %p) nounwind readonly {
+define i64 @f0(ptr %p) nounwind readonly {
entry:
- %ldaexd = tail call %0 @llvm.arm.ldaexd(i8* %p)
+ %ldaexd = tail call %0 @llvm.arm.ldaexd(ptr %p)
%0 = extractvalue %0 %ldaexd, 1
%1 = extractvalue %0 %ldaexd, 0
%2 = zext i32 %0 to i64
@@ -19,24 +19,24 @@ entry:
; CHECK-LABEL: f1:
; CHECK: stlexd
-define i32 @f1(i8* %ptr, i64 %val) nounwind {
+define i32 @f1(ptr %ptr, i64 %val) nounwind {
entry:
%tmp4 = trunc i64 %val to i32
%tmp6 = lshr i64 %val, 32
%tmp7 = trunc i64 %tmp6 to i32
- %stlexd = tail call i32 @llvm.arm.stlexd(i32 %tmp4, i32 %tmp7, i8* %ptr)
+ %stlexd = tail call i32 @llvm.arm.stlexd(i32 %tmp4, i32 %tmp7, ptr %ptr)
ret i32 %stlexd
}
-declare %0 @llvm.arm.ldaexd(i8*) nounwind readonly
-declare i32 @llvm.arm.stlexd(i32, i32, i8*) nounwind
+declare %0 @llvm.arm.ldaexd(ptr) nounwind readonly
+declare i32 @llvm.arm.stlexd(i32, i32, ptr) nounwind
; CHECK-LABEL: test_load_i8:
; CHECK: ldaexb r0, [r0]
; CHECK-NOT: uxtb
; CHECK-NOT: and
-define zeroext i8 @test_load_i8(i8* %addr) {
- %val = call i32 @llvm.arm.ldaex.p0i8(i8* elementtype(i8) %addr)
+define zeroext i8 @test_load_i8(ptr %addr) {
+ %val = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i8) %addr)
%val8 = trunc i32 %val to i8
ret i8 %val8
}
@@ -45,48 +45,44 @@ define zeroext i8 @test_load_i8(i8* %addr) {
; CHECK: ldaexh r0, [r0]
; CHECK-NOT: uxth
; CHECK-NOT: and
-define zeroext i16 @test_load_i16(i16* %addr) {
- %val = call i32 @llvm.arm.ldaex.p0i16(i16* elementtype(i16) %addr)
+define zeroext i16 @test_load_i16(ptr %addr) {
+ %val = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i16) %addr)
%val16 = trunc i32 %val to i16
ret i16 %val16
}
; CHECK-LABEL: test_load_i32:
; CHECK: ldaex r0, [r0]
-define i32 @test_load_i32(i32* %addr) {
- %val = call i32 @llvm.arm.ldaex.p0i32(i32* elementtype(i32) %addr)
+define i32 @test_load_i32(ptr %addr) {
+ %val = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %addr)
ret i32 %val
}
-declare i32 @llvm.arm.ldaex.p0i8(i8*) nounwind readonly
-declare i32 @llvm.arm.ldaex.p0i16(i16*) nounwind readonly
-declare i32 @llvm.arm.ldaex.p0i32(i32*) nounwind readonly
+declare i32 @llvm.arm.ldaex.p0(ptr) nounwind readonly
; CHECK-LABEL: test_store_i8:
; CHECK-NOT: uxtb
; CHECK: stlexb r0, r1, [r2]
-define i32 @test_store_i8(i32, i8 %val, i8* %addr) {
+define i32 @test_store_i8(i32, i8 %val, ptr %addr) {
%extval = zext i8 %val to i32
- %res = call i32 @llvm.arm.stlex.p0i8(i32 %extval, i8* elementtype(i8) %addr)
+ %res = call i32 @llvm.arm.stlex.p0(i32 %extval, ptr elementtype(i8) %addr)
ret i32 %res
}
; CHECK-LABEL: test_store_i16:
; CHECK-NOT: uxth
; CHECK: stlexh r0, r1, [r2]
-define i32 @test_store_i16(i32, i16 %val, i16* %addr) {
+define i32 @test_store_i16(i32, i16 %val, ptr %addr) {
%extval = zext i16 %val to i32
- %res = call i32 @llvm.arm.stlex.p0i16(i32 %extval, i16* elementtype(i16) %addr)
+ %res = call i32 @llvm.arm.stlex.p0(i32 %extval, ptr elementtype(i16) %addr)
ret i32 %res
}
; CHECK-LABEL: test_store_i32:
; CHECK: stlex r0, r1, [r2]
-define i32 @test_store_i32(i32, i32 %val, i32* %addr) {
- %res = call i32 @llvm.arm.stlex.p0i32(i32 %val, i32* elementtype(i32) %addr)
+define i32 @test_store_i32(i32, i32 %val, ptr %addr) {
+ %res = call i32 @llvm.arm.stlex.p0(i32 %val, ptr elementtype(i32) %addr)
ret i32 %res
}
-declare i32 @llvm.arm.stlex.p0i8(i32, i8*) nounwind
-declare i32 @llvm.arm.stlex.p0i16(i32, i16*) nounwind
-declare i32 @llvm.arm.stlex.p0i32(i32, i32*) nounwind
+declare i32 @llvm.arm.stlex.p0(i32, ptr) nounwind
diff --git a/llvm/test/CodeGen/ARM/ldc2l.ll b/llvm/test/CodeGen/ARM/ldc2l.ll
index bdfcbbf7df255..691635ddec7dc 100644
--- a/llvm/test/CodeGen/ARM/ldc2l.ll
+++ b/llvm/test/CodeGen/ARM/ldc2l.ll
@@ -2,10 +2,10 @@
; RUN: not --crash llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ldc2l
-define void @ldc2l(i8* %i) nounwind {
+define void @ldc2l(ptr %i) nounwind {
entry:
- call void @llvm.arm.ldc2l(i32 1, i32 2, i8* %i) nounwind
+ call void @llvm.arm.ldc2l(i32 1, i32 2, ptr %i) nounwind
ret void
}
-declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
+declare void @llvm.arm.ldc2l(i32, i32, ptr) nounwind
diff --git a/llvm/test/CodeGen/ARM/ldm-base-writeback.ll b/llvm/test/CodeGen/ARM/ldm-base-writeback.ll
index 4c2ff7bbbba15..9344036a0506d 100644
--- a/llvm/test/CodeGen/ARM/ldm-base-writeback.ll
+++ b/llvm/test/CodeGen/ARM/ldm-base-writeback.ll
@@ -10,9 +10,9 @@ target triple = "armv7--linux-gnu"
; CHECK-LABEL: bar:
; CHECK: ldm r{{[0-9]}}!, {r0, r{{[0-9]}}, r{{[0-9]}}}
define dso_local void @bar(i32 %a1, i32 %b1, i32 %c1) minsize optsize {
- %1 = load i32, i32* @a, align 4
- %2 = load i32, i32* @b, align 4
- %3 = load i32, i32* @c, align 4
+ %1 = load i32, ptr @a, align 4
+ %2 = load i32, ptr @b, align 4
+ %3 = load i32, ptr @c, align 4
%4 = tail call i32 @baz(i32 %1, i32 %3) minsize optsize
%5 = tail call i32 @baz(i32 %2, i32 %3) minsize optsize
ret void
diff --git a/llvm/test/CodeGen/ARM/ldm-stm-base-materialization.ll b/llvm/test/CodeGen/ARM/ldm-stm-base-materialization.ll
index 755619e8b3ee2..1d90dd67ecb7c 100644
--- a/llvm/test/CodeGen/ARM/ldm-stm-base-materialization.ll
+++ b/llvm/test/CodeGen/ARM/ldm-stm-base-materialization.ll
@@ -2,27 +2,25 @@
; Thumb1 (thumbv6m) is tested in tests/Thumb
- at a = external global i32*
- at b = external global i32*
+ at a = external global ptr
+ at b = external global ptr
; Function Attrs: nounwind
define void @foo24() #0 {
entry:
; CHECK-LABEL: foo24:
-; We use '[rl0-9]*' to allow 'r0'..'r12', 'lr'
+; We use 'ptr' to allow 'r0'..'r12', 'lr'
; CHECK: movt [[LB:[rl0-9]+]], :upper16:b
; CHECK: movt [[SB:[rl0-9]+]], :upper16:a
; CHECK: add [[NLB:[rl0-9]+]], [[LB]], #4
; CHECK: add [[NSB:[rl0-9]+]], [[SB]], #4
; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]], [[R5:[rl0-9]+]], [[R6:[rl0-9]+]]}
; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]], [[R6]]}
- %0 = load i32*, i32** @a, align 4
- %arrayidx = getelementptr inbounds i32, i32* %0, i32 1
- %1 = bitcast i32* %arrayidx to i8*
- %2 = load i32*, i32** @b, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %2, i32 1
- %3 = bitcast i32* %arrayidx1 to i8*
- tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %1, i8* align 4 %3, i32 24, i1 false)
+ %0 = load ptr, ptr @a, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %0, i32 1
+ %1 = load ptr, ptr @b, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %1, i32 1
+ tail call void @llvm.memcpy.p0.p0.i32(ptr align 4 %arrayidx, ptr align 4 %arrayidx1, i32 24, i1 false)
ret void
}
@@ -37,13 +35,11 @@ entry:
; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]]}
; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
- %0 = load i32*, i32** @a, align 4
- %arrayidx = getelementptr inbounds i32, i32* %0, i32 1
- %1 = bitcast i32* %arrayidx to i8*
- %2 = load i32*, i32** @b, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %2, i32 1
- %3 = bitcast i32* %arrayidx1 to i8*
- tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %1, i8* align 4 %3, i32 28, i1 false)
+ %0 = load ptr, ptr @a, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %0, i32 1
+ %1 = load ptr, ptr @b, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %1, i32 1
+ tail call void @llvm.memcpy.p0.p0.i32(ptr align 4 %arrayidx, ptr align 4 %arrayidx1, i32 28, i1 false)
ret void
}
@@ -58,13 +54,11 @@ entry:
; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
- %0 = load i32*, i32** @a, align 4
- %arrayidx = getelementptr inbounds i32, i32* %0, i32 1
- %1 = bitcast i32* %arrayidx to i8*
- %2 = load i32*, i32** @b, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %2, i32 1
- %3 = bitcast i32* %arrayidx1 to i8*
- tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %1, i8* align 4 %3, i32 32, i1 false)
+ %0 = load ptr, ptr @a, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %0, i32 1
+ %1 = load ptr, ptr @b, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %1, i32 1
+ tail call void @llvm.memcpy.p0.p0.i32(ptr align 4 %arrayidx, ptr align 4 %arrayidx1, i32 32, i1 false)
ret void
}
@@ -79,15 +73,13 @@ entry:
; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]], [[R5:[rl0-9]+]]}
; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]]}
- %0 = load i32*, i32** @a, align 4
- %arrayidx = getelementptr inbounds i32, i32* %0, i32 1
- %1 = bitcast i32* %arrayidx to i8*
- %2 = load i32*, i32** @b, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %2, i32 1
- %3 = bitcast i32* %arrayidx1 to i8*
- tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %1, i8* align 4 %3, i32 36, i1 false)
+ %0 = load ptr, ptr @a, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %0, i32 1
+ %1 = load ptr, ptr @b, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %1, i32 1
+ tail call void @llvm.memcpy.p0.p0.i32(ptr align 4 %arrayidx, ptr align 4 %arrayidx1, i32 36, i1 false)
ret void
}
; Function Attrs: nounwind
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1) #1
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture readonly, i32, i1) #1
diff --git a/llvm/test/CodeGen/ARM/ldm-stm-i256.ll b/llvm/test/CodeGen/ARM/ldm-stm-i256.ll
index 151c42e0e1585..20cb3fbfb3529 100644
--- a/llvm/test/CodeGen/ARM/ldm-stm-i256.ll
+++ b/llvm/test/CodeGen/ARM/ldm-stm-i256.ll
@@ -7,15 +7,15 @@
; FIXME: We could merge more loads/stores with regalloc hints.
; FIXME: Fix scheduling so we don't have 16 live registers.
-define void @f(i256* nocapture %a, i256* nocapture %b, i256* nocapture %cc, i256* nocapture %dd) nounwind uwtable noinline ssp {
+define void @f(ptr nocapture %a, ptr nocapture %b, ptr nocapture %cc, ptr nocapture %dd) nounwind uwtable noinline ssp {
entry:
- %c = load i256, i256* %cc
- %d = load i256, i256* %dd
+ %c = load i256, ptr %cc
+ %d = load i256, ptr %dd
%add = add nsw i256 %c, %d
- store i256 %add, i256* %a, align 8
+ store i256 %add, ptr %a, align 8
%or = or i256 %c, 1606938044258990275541962092341162602522202993782792835301376
%add6 = add nsw i256 %or, %d
- store i256 %add6, i256* %b, align 8
+ store i256 %add6, ptr %b, align 8
ret void
; CHECK-DAG: ldm r2
; CHECK-DAG: ldr {{.*}}, [r3]
diff --git a/llvm/test/CodeGen/ARM/ldm.ll b/llvm/test/CodeGen/ARM/ldm.ll
index 65e972f4e1b40..2f7486020890d 100644
--- a/llvm/test/CodeGen/ARM/ldm.ll
+++ b/llvm/test/CodeGen/ARM/ldm.ll
@@ -1,15 +1,15 @@
; RUN: llc < %s -mtriple=armv7-apple-ios3.0 | FileCheck %s
; RUN: llc < %s -mtriple=armv4t-apple-ios3.0 | FileCheck %s -check-prefix=V4T
- at X = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
+ at X = external global [0 x i32] ; <ptr> [#uses=5]
define i32 @t1() {
; CHECK-LABEL: t1:
; CHECK: pop
; V4T-LABEL: t1:
; V4T: pop
- %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1]
- %tmp3 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
+ %tmp = load i32, ptr @X ; <i32> [#uses=1]
+ %tmp3 = load i32, ptr getelementptr ([0 x i32], ptr @X, i32 0, i32 1) ; <i32> [#uses=1]
%tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 ) ; <i32> [#uses=1]
ret i32 %tmp4
}
@@ -19,9 +19,9 @@ define i32 @t2() {
; CHECK: pop
; V4T-LABEL: t2:
; V4T: pop
- %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
- %tmp3 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
- %tmp5 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 4) ; <i32> [#uses=1]
+ %tmp = load i32, ptr getelementptr ([0 x i32], ptr @X, i32 0, i32 2) ; <i32> [#uses=1]
+ %tmp3 = load i32, ptr getelementptr ([0 x i32], ptr @X, i32 0, i32 3) ; <i32> [#uses=1]
+ %tmp5 = load i32, ptr getelementptr ([0 x i32], ptr @X, i32 0, i32 4) ; <i32> [#uses=1]
%tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1]
ret i32 %tmp6
}
@@ -34,9 +34,9 @@ define i32 @t3() {
; V4T: ldmib
; V4T: pop
; V4T-NEXT: bx lr
- %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
- %tmp3 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
- %tmp5 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
+ %tmp = load i32, ptr getelementptr ([0 x i32], ptr @X, i32 0, i32 1) ; <i32> [#uses=1]
+ %tmp3 = load i32, ptr getelementptr ([0 x i32], ptr @X, i32 0, i32 2) ; <i32> [#uses=1]
+ %tmp5 = load i32, ptr getelementptr ([0 x i32], ptr @X, i32 0, i32 3) ; <i32> [#uses=1]
%tmp6 = call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1]
ret i32 %tmp6
}
diff --git a/llvm/test/CodeGen/ARM/ldr.ll b/llvm/test/CodeGen/ARM/ldr.ll
index bd4de5de669cd..50c239ae43e4e 100644
--- a/llvm/test/CodeGen/ARM/ldr.ll
+++ b/llvm/test/CodeGen/ARM/ldr.ll
@@ -1,29 +1,29 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
-define i32 @f1(i32* %v) {
+define i32 @f1(ptr %v) {
; CHECK-LABEL: f1:
; CHECK: ldr r0
entry:
- %tmp = load i32, i32* %v
+ %tmp = load i32, ptr %v
ret i32 %tmp
}
-define i32 @f2(i32* %v) {
+define i32 @f2(ptr %v) {
; CHECK-LABEL: f2:
; CHECK: ldr r0
entry:
- %tmp2 = getelementptr i32, i32* %v, i32 1023
- %tmp = load i32, i32* %tmp2
+ %tmp2 = getelementptr i32, ptr %v, i32 1023
+ %tmp = load i32, ptr %tmp2
ret i32 %tmp
}
-define i32 @f3(i32* %v) {
+define i32 @f3(ptr %v) {
; CHECK-LABEL: f3:
; CHECK: mov
; CHECK: ldr r0
entry:
- %tmp2 = getelementptr i32, i32* %v, i32 1024
- %tmp = load i32, i32* %tmp2
+ %tmp2 = getelementptr i32, ptr %v, i32 1024
+ %tmp = load i32, ptr %tmp2
ret i32 %tmp
}
@@ -33,8 +33,8 @@ define i32 @f4(i32 %base) {
; CHECK: ldr r0
entry:
%tmp1 = sub i32 %base, 128
- %tmp2 = inttoptr i32 %tmp1 to i32*
- %tmp3 = load i32, i32* %tmp2
+ %tmp2 = inttoptr i32 %tmp1 to ptr
+ %tmp3 = load i32, ptr %tmp2
ret i32 %tmp3
}
@@ -43,8 +43,8 @@ define i32 @f5(i32 %base, i32 %offset) {
; CHECK: ldr r0
entry:
%tmp1 = add i32 %base, %offset
- %tmp2 = inttoptr i32 %tmp1 to i32*
- %tmp3 = load i32, i32* %tmp2
+ %tmp2 = inttoptr i32 %tmp1 to ptr
+ %tmp3 = load i32, ptr %tmp2
ret i32 %tmp3
}
@@ -54,8 +54,8 @@ define i32 @f6(i32 %base, i32 %offset) {
entry:
%tmp1 = shl i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
- %tmp3 = inttoptr i32 %tmp2 to i32*
- %tmp4 = load i32, i32* %tmp3
+ %tmp3 = inttoptr i32 %tmp2 to ptr
+ %tmp4 = load i32, ptr %tmp3
ret i32 %tmp4
}
@@ -65,7 +65,7 @@ define i32 @f7(i32 %base, i32 %offset) {
entry:
%tmp1 = lshr i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
- %tmp3 = inttoptr i32 %tmp2 to i32*
- %tmp4 = load i32, i32* %tmp3
+ %tmp3 = inttoptr i32 %tmp2 to ptr
+ %tmp4 = load i32, ptr %tmp3
ret i32 %tmp4
}
diff --git a/llvm/test/CodeGen/ARM/ldr_ext.ll b/llvm/test/CodeGen/ARM/ldr_ext.ll
index 15efb50c9a9ac..5dcc2d09e7ae0 100644
--- a/llvm/test/CodeGen/ARM/ldr_ext.ll
+++ b/llvm/test/CodeGen/ARM/ldr_ext.ll
@@ -1,29 +1,29 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
-define i32 @test1(i8* %t1) nounwind {
+define i32 @test1(ptr %t1) nounwind {
; CHECK: ldrb
- %tmp.u = load i8, i8* %t1
+ %tmp.u = load i8, ptr %t1
%tmp1.s = zext i8 %tmp.u to i32
ret i32 %tmp1.s
}
-define i32 @test2(i16* %t1) nounwind {
+define i32 @test2(ptr %t1) nounwind {
; CHECK: ldrh
- %tmp.u = load i16, i16* %t1
+ %tmp.u = load i16, ptr %t1
%tmp1.s = zext i16 %tmp.u to i32
ret i32 %tmp1.s
}
-define i32 @test3(i8* %t0) nounwind {
+define i32 @test3(ptr %t0) nounwind {
; CHECK: ldrsb
- %tmp.s = load i8, i8* %t0
+ %tmp.s = load i8, ptr %t0
%tmp1.s = sext i8 %tmp.s to i32
ret i32 %tmp1.s
}
-define i32 @test4(i16* %t0) nounwind {
+define i32 @test4(ptr %t0) nounwind {
; CHECK: ldrsh
- %tmp.s = load i16, i16* %t0
+ %tmp.s = load i16, ptr %t0
%tmp1.s = sext i16 %tmp.s to i32
ret i32 %tmp1.s
}
@@ -31,7 +31,7 @@ define i32 @test4(i16* %t0) nounwind {
define i32 @test5() nounwind {
; CHECK: mov r0, #0
; CHECK: ldrsh
- %tmp.s = load i16, i16* null
+ %tmp.s = load i16, ptr null
%tmp1.s = sext i16 %tmp.s to i32
ret i32 %tmp1.s
}
diff --git a/llvm/test/CodeGen/ARM/ldr_frame.ll b/llvm/test/CodeGen/ARM/ldr_frame.ll
index 24c10b42a445a..2a41b25486d05 100644
--- a/llvm/test/CodeGen/ARM/ldr_frame.ll
+++ b/llvm/test/CodeGen/ARM/ldr_frame.ll
@@ -4,8 +4,7 @@
; CHECK-NOT: mov
define i32 @f1() {
%buf = alloca [32 x i32], align 4
- %tmp = getelementptr [32 x i32], [32 x i32]* %buf, i32 0, i32 0
- %tmp1 = load i32, i32* %tmp
+ %tmp1 = load i32, ptr %buf
ret i32 %tmp1
}
@@ -13,8 +12,7 @@ define i32 @f1() {
; CHECK-NOT: mov
define i32 @f2() {
%buf = alloca [32 x i8], align 4
- %tmp = getelementptr [32 x i8], [32 x i8]* %buf, i32 0, i32 0
- %tmp1 = load i8, i8* %tmp
+ %tmp1 = load i8, ptr %buf
%tmp2 = zext i8 %tmp1 to i32
ret i32 %tmp2
}
@@ -23,8 +21,8 @@ define i32 @f2() {
; CHECK-NOT: mov
define i32 @f3() {
%buf = alloca [32 x i32], align 4
- %tmp = getelementptr [32 x i32], [32 x i32]* %buf, i32 0, i32 32
- %tmp1 = load i32, i32* %tmp
+ %tmp = getelementptr [32 x i32], ptr %buf, i32 0, i32 32
+ %tmp1 = load i32, ptr %tmp
ret i32 %tmp1
}
@@ -32,8 +30,8 @@ define i32 @f3() {
; CHECK-NOT: mov
define i32 @f4() {
%buf = alloca [32 x i8], align 4
- %tmp = getelementptr [32 x i8], [32 x i8]* %buf, i32 0, i32 2
- %tmp1 = load i8, i8* %tmp
+ %tmp = getelementptr [32 x i8], ptr %buf, i32 0, i32 2
+ %tmp1 = load i8, ptr %tmp
%tmp2 = zext i8 %tmp1 to i32
ret i32 %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/ldr_post.ll b/llvm/test/CodeGen/ARM/ldr_post.ll
index 139c6f45e5204..c64fef9b89621 100644
--- a/llvm/test/CodeGen/ARM/ldr_post.ll
+++ b/llvm/test/CodeGen/ARM/ldr_post.ll
@@ -6,8 +6,8 @@
; CHECK-NOT: ldr
define i32 @test1(i32 %a, i32 %b, i32 %c) {
%tmp1 = mul i32 %a, %b ; <i32> [#uses=2]
- %tmp2 = inttoptr i32 %tmp1 to i32* ; <i32*> [#uses=1]
- %tmp3 = load i32, i32* %tmp2 ; <i32> [#uses=1]
+ %tmp2 = inttoptr i32 %tmp1 to ptr ; <ptr> [#uses=1]
+ %tmp3 = load i32, ptr %tmp2 ; <i32> [#uses=1]
%tmp4 = sub i32 %tmp1, %c ; <i32> [#uses=1]
%tmp5 = mul i32 %tmp4, %tmp3 ; <i32> [#uses=1]
ret i32 %tmp5
@@ -18,8 +18,8 @@ define i32 @test1(i32 %a, i32 %b, i32 %c) {
; CHECK-NOT: ldr
define i32 @test2(i32 %a, i32 %b) {
%tmp1 = mul i32 %a, %b ; <i32> [#uses=2]
- %tmp2 = inttoptr i32 %tmp1 to i32* ; <i32*> [#uses=1]
- %tmp3 = load i32, i32* %tmp2 ; <i32> [#uses=1]
+ %tmp2 = inttoptr i32 %tmp1 to ptr ; <ptr> [#uses=1]
+ %tmp3 = load i32, ptr %tmp2 ; <i32> [#uses=1]
%tmp4 = sub i32 %tmp1, 16 ; <i32> [#uses=1]
%tmp5 = mul i32 %tmp4, %tmp3 ; <i32> [#uses=1]
ret i32 %tmp5
diff --git a/llvm/test/CodeGen/ARM/ldr_pre.ll b/llvm/test/CodeGen/ARM/ldr_pre.ll
index c6c76e2228366..bf6dcf391125a 100644
--- a/llvm/test/CodeGen/ARM/ldr_pre.ll
+++ b/llvm/test/CodeGen/ARM/ldr_pre.ll
@@ -4,11 +4,11 @@
; CHECK-LABEL: test1:
; CHECK: ldr {{.*!}}
; CHECK-NOT: ldr
-define i32* @test1(i32* %X, i32* %dest) {
- %Y = getelementptr i32, i32* %X, i32 4 ; <i32*> [#uses=2]
- %A = load i32, i32* %Y ; <i32> [#uses=1]
- store i32 %A, i32* %dest
- ret i32* %Y
+define ptr @test1(ptr %X, ptr %dest) {
+ %Y = getelementptr i32, ptr %X, i32 4 ; <ptr> [#uses=2]
+ %A = load i32, ptr %Y ; <i32> [#uses=1]
+ store i32 %A, ptr %dest
+ ret ptr %Y
}
; CHECK-LABEL: test2:
@@ -16,8 +16,8 @@ define i32* @test1(i32* %X, i32* %dest) {
; CHECK-NOT: ldr
define i32 @test2(i32 %a, i32 %b, i32 %c) {
%tmp1 = sub i32 %a, %b ; <i32> [#uses=2]
- %tmp2 = inttoptr i32 %tmp1 to i32* ; <i32*> [#uses=1]
- %tmp3 = load i32, i32* %tmp2 ; <i32> [#uses=1]
+ %tmp2 = inttoptr i32 %tmp1 to ptr ; <ptr> [#uses=1]
+ %tmp3 = load i32, ptr %tmp2 ; <i32> [#uses=1]
%tmp4 = sub i32 %tmp1, %c ; <i32> [#uses=1]
%tmp5 = add i32 %tmp4, %tmp3 ; <i32> [#uses=1]
ret i32 %tmp5
diff --git a/llvm/test/CodeGen/ARM/ldrcppic.ll b/llvm/test/CodeGen/ARM/ldrcppic.ll
index c7727290d842b..0a4c8abcad6c4 100644
--- a/llvm/test/CodeGen/ARM/ldrcppic.ll
+++ b/llvm/test/CodeGen/ARM/ldrcppic.ll
@@ -23,8 +23,8 @@ define dso_local fastcc void @_ZN15UsecaseSelector26IsAllowedImplDefinedFormatE1
br i1 undef, label %4, label %13
; <label>:4: ; preds = %3
- %5 = getelementptr inbounds [16 x i32], [16 x i32]* bitcast (<{ i32, i32, i32, i32, [12 x i32] }>* @_ZN15UsecaseSelector25AllowedImplDefinedFormatsE to [16 x i32]*), i32 0, i32 undef
- %6 = load i32, i32* %5, align 4
+ %5 = getelementptr inbounds [16 x i32], ptr bitcast (<{ i32, i32, i32, i32, [12 x i32] }>* @_ZN15UsecaseSelector25AllowedImplDefinedFormatsE to ptr), i32 0, i32 undef
+ %6 = load i32, ptr %5, align 4
%7 = icmp eq i32 10, %6
br i1 %7, label %9, label %8
diff --git a/llvm/test/CodeGen/ARM/ldrd-memoper.ll b/llvm/test/CodeGen/ARM/ldrd-memoper.ll
index 8501ee0af19d0..dfeddd7b93d08 100644
--- a/llvm/test/CodeGen/ARM/ldrd-memoper.ll
+++ b/llvm/test/CodeGen/ARM/ldrd-memoper.ll
@@ -3,13 +3,13 @@
; REQUIRES: asserts
; PR8113: ARMLoadStoreOptimizer must preserve memoperands.
- at b = external global i64*
+ at b = external global ptr
; CHECK: Formed {{.*}} t2LDRD{{.*}} (load (s32) from %ir.0), (load (s32) from %ir.0 + 4)
define i64 @t(i64 %a) nounwind readonly {
entry:
- %0 = load i64*, i64** @b, align 4
- %1 = load i64, i64* %0, align 4
+ %0 = load ptr, ptr @b, align 4
+ %1 = load i64, ptr %0, align 4
%2 = mul i64 %1, %a
ret i64 %2
}
diff --git a/llvm/test/CodeGen/ARM/ldrd.ll b/llvm/test/CodeGen/ARM/ldrd.ll
index 3b3724fd7b7ba..cf5c2dfe5ef60 100644
--- a/llvm/test/CodeGen/ARM/ldrd.ll
+++ b/llvm/test/CodeGen/ARM/ldrd.ll
@@ -9,10 +9,10 @@
; Magic ARM pair hints works best with linearscan / fast.
- at b = external global i64*
+ at b = external global ptr
; We use the following two to force values into specific registers.
-declare i64* @get_ptr()
+declare ptr @get_ptr()
declare void @use_i64(i64 %v)
define void @test_ldrd(i64 %a) nounwind readonly "frame-pointer"="all" {
@@ -24,8 +24,8 @@ define void @test_ldrd(i64 %a) nounwind readonly "frame-pointer"="all" {
; M3-NOT: ldrd r[[REGNUM:[0-9]+]], {{r[0-9]+}}, [r[[REGNUM]]]
; CONSERVATIVE-NOT: ldrd
; NORMAL: bl{{x?}} _use_i64
- %ptr = call i64* @get_ptr()
- %v = load i64, i64* %ptr, align 8
+ %ptr = call ptr @get_ptr()
+ %v = load i64, ptr %ptr, align 8
call void @use_i64(i64 %v)
ret void
}
@@ -49,7 +49,7 @@ define void @test_ldrd(i64 %a) nounwind readonly "frame-pointer"="all" {
; GREEDY: %bb
; GREEDY: ldrd
; GREEDY: str
-define void @f(i32* nocapture %a, i32* nocapture %b, i32 %n) nounwind "frame-pointer"="all" {
+define void @f(ptr nocapture %a, ptr nocapture %b, i32 %n) nounwind "frame-pointer"="all" {
entry:
%0 = add nsw i32 %n, -1 ; <i32> [#uses=2]
%1 = icmp sgt i32 %0, 0 ; <i1> [#uses=1]
@@ -57,14 +57,14 @@ entry:
bb: ; preds = %bb, %entry
%i.03 = phi i32 [ %tmp, %bb ], [ 0, %entry ] ; <i32> [#uses=3]
- %scevgep = getelementptr i32, i32* %a, i32 %i.03 ; <i32*> [#uses=1]
- %scevgep4 = getelementptr i32, i32* %b, i32 %i.03 ; <i32*> [#uses=1]
+ %scevgep = getelementptr i32, ptr %a, i32 %i.03 ; <ptr> [#uses=1]
+ %scevgep4 = getelementptr i32, ptr %b, i32 %i.03 ; <ptr> [#uses=1]
%tmp = add i32 %i.03, 1 ; <i32> [#uses=3]
- %scevgep5 = getelementptr i32, i32* %a, i32 %tmp ; <i32*> [#uses=1]
- %2 = load i32, i32* %scevgep, align 4 ; <i32> [#uses=1]
- %3 = load i32, i32* %scevgep5, align 4 ; <i32> [#uses=1]
+ %scevgep5 = getelementptr i32, ptr %a, i32 %tmp ; <ptr> [#uses=1]
+ %2 = load i32, ptr %scevgep, align 4 ; <i32> [#uses=1]
+ %3 = load i32, ptr %scevgep5, align 4 ; <i32> [#uses=1]
%4 = add nsw i32 %3, %2 ; <i32> [#uses=1]
- store i32 %4, i32* %scevgep4, align 4
+ store i32 %4, ptr %scevgep4, align 4
%exitcond = icmp eq i32 %tmp, %0 ; <i1> [#uses=1]
br i1 %exitcond, label %return, label %bb
@@ -89,12 +89,11 @@ entry:
; A8-NEXT: str [[FIELD2]], [[[BASE]]]
; CONSERVATIVE-NOT: ldrd
%orig_blocks = alloca [256 x i16], align 2
- %0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start.p0i8(i64 512, i8* %0) nounwind
- %tmp1 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 1), align 4
- %tmp2 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 2), align 4
+ %tmp1 = load i32, ptr getelementptr inbounds (%struct.Test, ptr @TestVar, i32 0, i32 1), align 4
+ %tmp2 = load i32, ptr getelementptr inbounds (%struct.Test, ptr @TestVar, i32 0, i32 2), align 4
%add = add nsw i32 %tmp2, %tmp1
- store i32 %add, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 0), align 4
- call void @llvm.lifetime.end.p0i8(i64 512, i8* %0) nounwind
+ store i32 %add, ptr @TestVar, align 4
+ call void @llvm.lifetime.end.p0(i64 512, ptr %orig_blocks) nounwind
ret void
}
@@ -105,12 +104,11 @@ declare void @extfunc(i32, i32, i32, i32)
; A8: ldrd
; CHECK: bl{{x?}} _extfunc
; A8: pop
-define void @Func2(i32* %p) "frame-pointer"="all" {
+define void @Func2(ptr %p) "frame-pointer"="all" {
entry:
- %addr0 = getelementptr i32, i32* %p, i32 0
- %addr1 = getelementptr i32, i32* %p, i32 1
- %v0 = load i32, i32* %addr0
- %v1 = load i32, i32* %addr1
+ %addr1 = getelementptr i32, ptr %p, i32 1
+ %v0 = load i32, ptr %p
+ %v1 = load i32, ptr %addr1
; try to force %v0/%v1 into non-adjacent registers
call void @extfunc(i32 %v0, i32 0, i32 0, i32 %v1)
ret void
@@ -138,18 +136,18 @@ define void @strd_spill_ldrd_reload(i32 %v0, i32 %v1) "frame-pointer"="all" {
ret void
}
-declare void @extfunc2(i32*, i32, i32)
+declare void @extfunc2(ptr, i32, i32)
; CHECK-LABEL: ldrd_postupdate_dec:
; NORMAL: ldrd r1, r2, [r0], #-8
; CONSERVATIVE-NOT: ldrd
; CHECK: bl{{x?}} _extfunc
-define void @ldrd_postupdate_dec(i32* %p0) "frame-pointer"="all" {
- %p0.1 = getelementptr i32, i32* %p0, i32 1
- %v0 = load i32, i32* %p0
- %v1 = load i32, i32* %p0.1
- %p1 = getelementptr i32, i32* %p0, i32 -2
- call void @extfunc2(i32* %p1, i32 %v0, i32 %v1)
+define void @ldrd_postupdate_dec(ptr %p0) "frame-pointer"="all" {
+ %p0.1 = getelementptr i32, ptr %p0, i32 1
+ %v0 = load i32, ptr %p0
+ %v1 = load i32, ptr %p0.1
+ %p1 = getelementptr i32, ptr %p0, i32 -2
+ call void @extfunc2(ptr %p1, i32 %v0, i32 %v1)
ret void
}
@@ -157,12 +155,12 @@ define void @ldrd_postupdate_dec(i32* %p0) "frame-pointer"="all" {
; NORMAL: ldrd r1, r2, [r0], #8
; CONSERVATIVE-NOT: ldrd
; CHECK: bl{{x?}} _extfunc
-define void @ldrd_postupdate_inc(i32* %p0) "frame-pointer"="all" {
- %p0.1 = getelementptr i32, i32* %p0, i32 1
- %v0 = load i32, i32* %p0
- %v1 = load i32, i32* %p0.1
- %p1 = getelementptr i32, i32* %p0, i32 2
- call void @extfunc2(i32* %p1, i32 %v0, i32 %v1)
+define void @ldrd_postupdate_inc(ptr %p0) "frame-pointer"="all" {
+ %p0.1 = getelementptr i32, ptr %p0, i32 1
+ %v0 = load i32, ptr %p0
+ %v1 = load i32, ptr %p0.1
+ %p1 = getelementptr i32, ptr %p0, i32 2
+ call void @extfunc2(ptr %p1, i32 %v0, i32 %v1)
ret void
}
@@ -170,24 +168,24 @@ define void @ldrd_postupdate_inc(i32* %p0) "frame-pointer"="all" {
; NORMAL: strd r1, r2, [r0], #-8
; CONSERVATIVE-NOT: strd
; CHECK: bx lr
-define i32* @strd_postupdate_dec(i32* %p0, i32 %v0, i32 %v1) "frame-pointer"="all" {
- %p0.1 = getelementptr i32, i32* %p0, i32 1
- store i32 %v0, i32* %p0
- store i32 %v1, i32* %p0.1
- %p1 = getelementptr i32, i32* %p0, i32 -2
- ret i32* %p1
+define ptr @strd_postupdate_dec(ptr %p0, i32 %v0, i32 %v1) "frame-pointer"="all" {
+ %p0.1 = getelementptr i32, ptr %p0, i32 1
+ store i32 %v0, ptr %p0
+ store i32 %v1, ptr %p0.1
+ %p1 = getelementptr i32, ptr %p0, i32 -2
+ ret ptr %p1
}
; CHECK-LABEL: strd_postupdate_inc:
; NORMAL: strd r1, r2, [r0], #8
; CONSERVATIVE-NOT: strd
; CHECK: bx lr
-define i32* @strd_postupdate_inc(i32* %p0, i32 %v0, i32 %v1) "frame-pointer"="all" {
- %p0.1 = getelementptr i32, i32* %p0, i32 1
- store i32 %v0, i32* %p0
- store i32 %v1, i32* %p0.1
- %p1 = getelementptr i32, i32* %p0, i32 2
- ret i32* %p1
+define ptr @strd_postupdate_inc(ptr %p0, i32 %v0, i32 %v1) "frame-pointer"="all" {
+ %p0.1 = getelementptr i32, ptr %p0, i32 1
+ store i32 %v0, ptr %p0
+ store i32 %v1, ptr %p0.1
+ %p1 = getelementptr i32, ptr %p0, i32 2
+ ret ptr %p1
}
; CHECK-LABEL: ldrd_strd_aa:
@@ -197,68 +195,58 @@ define i32* @strd_postupdate_inc(i32* %p0, i32 %v0, i32 %v1) "frame-pointer"="al
; CONSERVATIVE-NOT: strd
; CHECK: bx lr
-define void @ldrd_strd_aa(i32* noalias nocapture %x, i32* noalias nocapture readonly %y) {
+define void @ldrd_strd_aa(ptr noalias nocapture %x, ptr noalias nocapture readonly %y) {
entry:
- %0 = load i32, i32* %y, align 4
- store i32 %0, i32* %x, align 4
- %arrayidx2 = getelementptr inbounds i32, i32* %y, i32 1
- %1 = load i32, i32* %arrayidx2, align 4
- %arrayidx3 = getelementptr inbounds i32, i32* %x, i32 1
- store i32 %1, i32* %arrayidx3, align 4
+ %0 = load i32, ptr %y, align 4
+ store i32 %0, ptr %x, align 4
+ %arrayidx2 = getelementptr inbounds i32, ptr %y, i32 1
+ %1 = load i32, ptr %arrayidx2, align 4
+ %arrayidx3 = getelementptr inbounds i32, ptr %x, i32 1
+ store i32 %1, ptr %arrayidx3, align 4
ret void
}
; CHECK-LABEL: bitcast_ptr_ldr
; CHECK-NOT: ldrd
-define i32 @bitcast_ptr_ldr(i16* %In) {
+define i32 @bitcast_ptr_ldr(ptr %In) {
entry:
- %0 = bitcast i16* %In to i32*
- %in.addr.0 = getelementptr inbounds i32, i32* %0, i32 0
- %in.addr.1 = getelementptr inbounds i32, i32* %0, i32 1
- %1 = load i32, i32* %in.addr.0, align 2
- %2 = load i32, i32* %in.addr.1, align 2
- %mul = mul i32 %1, %2
+ %in.addr.1 = getelementptr inbounds i32, ptr %In, i32 1
+ %0 = load i32, ptr %In, align 2
+ %1 = load i32, ptr %in.addr.1, align 2
+ %mul = mul i32 %0, %1
ret i32 %mul
}
; CHECK-LABEL: bitcast_gep_ldr
; CHECK-NOT: ldrd
-define i32 @bitcast_gep_ldr(i16* %In) {
+define i32 @bitcast_gep_ldr(ptr %In) {
entry:
- %in.addr.0 = getelementptr inbounds i16, i16* %In, i32 0
- %in.addr.1 = getelementptr inbounds i16, i16* %In, i32 2
- %cast.0 = bitcast i16* %in.addr.0 to i32*
- %cast.1 = bitcast i16* %in.addr.1 to i32*
- %0 = load i32, i32* %cast.0, align 2
- %1 = load i32, i32* %cast.1, align 2
+ %in.addr.1 = getelementptr inbounds i16, ptr %In, i32 2
+ %0 = load i32, ptr %In, align 2
+ %1 = load i32, ptr %in.addr.1, align 2
%mul = mul i32 %0, %1
ret i32 %mul
}
; CHECK-LABEL: bitcast_ptr_str
; CHECK-NOT: strd
-define void @bitcast_ptr_str(i32 %arg0, i32 %arg1, i16* %out) {
+define void @bitcast_ptr_str(i32 %arg0, i32 %arg1, ptr %out) {
entry:
- %0 = bitcast i16* %out to i32*
- %out.addr.0 = getelementptr inbounds i32, i32* %0, i32 0
- %out.addr.1 = getelementptr inbounds i32, i32* %0, i32 1
- store i32 %arg0, i32* %out.addr.0, align 2
- store i32 %arg1, i32* %out.addr.1, align 2
+ %out.addr.1 = getelementptr inbounds i32, ptr %out, i32 1
+ store i32 %arg0, ptr %out, align 2
+ store i32 %arg1, ptr %out.addr.1, align 2
ret void
}
; CHECK-LABEL: bitcast_gep_str
; CHECK-NOT: strd
-define void @bitcast_gep_str(i32 %arg0, i32 %arg1, i16* %out) {
+define void @bitcast_gep_str(i32 %arg0, i32 %arg1, ptr %out) {
entry:
- %out.addr.0 = getelementptr inbounds i16, i16* %out, i32 0
- %out.addr.1 = getelementptr inbounds i16, i16* %out, i32 2
- %cast.0 = bitcast i16* %out.addr.0 to i32*
- %cast.1 = bitcast i16* %out.addr.1 to i32*
- store i32 %arg0, i32* %cast.0, align 2
- store i32 %arg1, i32* %cast.1, align 2
+ %out.addr.1 = getelementptr inbounds i16, ptr %out, i32 2
+ store i32 %arg0, ptr %out, align 2
+ store i32 %arg1, ptr %out.addr.1, align 2
ret void
}
-declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) nounwind
-declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) nounwind
+declare void @llvm.lifetime.start.p0(i64, ptr nocapture) nounwind
+declare void @llvm.lifetime.end.p0(i64, ptr nocapture) nounwind
diff --git a/llvm/test/CodeGen/ARM/ldrd_ifcvt.ll b/llvm/test/CodeGen/ARM/ldrd_ifcvt.ll
index e4c92a2c3b1d8..c7939345f1428 100644
--- a/llvm/test/CodeGen/ARM/ldrd_ifcvt.ll
+++ b/llvm/test/CodeGen/ARM/ldrd_ifcvt.ll
@@ -8,7 +8,7 @@
; CHECK: ldrdne
; CHECK: ldrdne
-define void @c(i64* %b) noreturn nounwind {
+define void @c(ptr %b) noreturn nounwind {
entry:
br label %for.cond
@@ -18,7 +18,7 @@ for.cond: ; preds = %land.end.3, %entry
br i1 %tobool.not, label %land.end, label %land.rhs
land.rhs: ; preds = %for.cond
- %0 = load volatile i64, i64* %b, align 8
+ %0 = load volatile i64, ptr %b, align 8
br label %land.end
land.end: ; preds = %land.rhs, %for.cond
@@ -28,7 +28,7 @@ land.end: ; preds = %land.rhs, %for.cond
br i1 %tobool.not.1, label %land.end.1, label %land.rhs.1
land.rhs.1: ; preds = %land.end
- %1 = load volatile i64, i64* %b, align 8
+ %1 = load volatile i64, ptr %b, align 8
br label %land.end.1
land.end.1: ; preds = %land.rhs.1, %land.end
@@ -38,7 +38,7 @@ land.end.1: ; preds = %land.rhs.1, %land.e
br i1 %tobool.not.2, label %land.end.2, label %land.rhs.2
land.rhs.2: ; preds = %land.end.1
- %2 = load volatile i64, i64* %b, align 8
+ %2 = load volatile i64, ptr %b, align 8
br label %land.end.2
land.end.2: ; preds = %land.rhs.2, %land.end.1
@@ -48,7 +48,7 @@ land.end.2: ; preds = %land.rhs.2, %land.e
br i1 %tobool.not.3, label %land.end.3, label %land.rhs.3
land.rhs.3: ; preds = %land.end.2
- %3 = load volatile i64, i64* %b, align 8
+ %3 = load volatile i64, ptr %b, align 8
br label %land.end.3
land.end.3: ; preds = %land.rhs.3, %land.end.2
diff --git a/llvm/test/CodeGen/ARM/ldrex-frame-size.ll b/llvm/test/CodeGen/ARM/ldrex-frame-size.ll
index 8766e024649c5..14974d2fbfd56 100644
--- a/llvm/test/CodeGen/ARM/ldrex-frame-size.ll
+++ b/llvm/test/CodeGen/ARM/ldrex-frame-size.ll
@@ -15,8 +15,8 @@ define void @test_large_frame() {
%ptr = alloca i32, i32 252
- %addr = getelementptr i32, i32* %ptr, i32 1
- call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
+ %addr = getelementptr i32, ptr %ptr, i32 1
+ call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %addr)
ret void
}
@@ -28,9 +28,9 @@ define void @test_small_frame() {
%ptr = alloca i32, i32 251
- %addr = getelementptr i32, i32* %ptr, i32 1
- call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
+ %addr = getelementptr i32, ptr %ptr, i32 1
+ call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %addr)
ret void
}
-declare i32 @llvm.arm.ldrex.p0i32(i32*)
+declare i32 @llvm.arm.ldrex.p0(ptr)
diff --git a/llvm/test/CodeGen/ARM/ldst-f32-2-i32.ll b/llvm/test/CodeGen/ARM/ldst-f32-2-i32.ll
index 2f83d9660127e..771662f30bb85 100644
--- a/llvm/test/CodeGen/ARM/ldst-f32-2-i32.ll
+++ b/llvm/test/CodeGen/ARM/ldst-f32-2-i32.ll
@@ -3,7 +3,7 @@
; Check if the f32 load / store pair are optimized to i32 load / store.
; rdar://8944252
-define void @t(i32 %width, float* nocapture %src, float* nocapture %dst, i32 %index) nounwind {
+define void @t(i32 %width, ptr nocapture %src, ptr nocapture %dst, i32 %index) nounwind {
; CHECK-LABEL: t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #0
@@ -17,18 +17,16 @@ define void @t(i32 %width, float* nocapture %src, float* nocapture %dst, i32 %in
; CHECK-NEXT: @ %bb.2: @ %return
; CHECK-NEXT: bx lr
entry:
- %src6 = bitcast float* %src to i8*
%0 = icmp eq i32 %width, 0
br i1 %0, label %return, label %bb
bb:
%j.05 = phi i32 [ %2, %bb ], [ 0, %entry ]
%tmp = mul i32 %j.05, %index
- %uglygep = getelementptr i8, i8* %src6, i32 %tmp
- %src_addr.04 = bitcast i8* %uglygep to float*
- %dst_addr.03 = getelementptr float, float* %dst, i32 %j.05
- %1 = load float, float* %src_addr.04, align 4
- store float %1, float* %dst_addr.03, align 4
+ %uglygep = getelementptr i8, ptr %src, i32 %tmp
+ %dst_addr.03 = getelementptr float, ptr %dst, i32 %j.05
+ %1 = load float, ptr %uglygep, align 4
+ store float %1, ptr %dst_addr.03, align 4
%2 = add i32 %j.05, 1
%exitcond = icmp eq i32 %2, %width
br i1 %exitcond, label %return, label %bb
@@ -52,14 +50,14 @@ declare void @_Z3fooddddddddddddddd(float, float, float, float, float, float, fl
; Because this test function is trying to pass float argument by stack,
; it can be optimized to i32 load / store
define signext i32 @test() {
-%1 = load float, float* @a1, align 4
-%2 = load float, float* @a2, align 4
-%3 = load float, float* @a3, align 4
-%4 = load float, float* @a4, align 4
-%5 = load float, float* @a5, align 4
-%6 = load float, float* @a6, align 4
-%7 = load float, float* @a7, align 4
-%8 = load float, float* @a8, align 4
+%1 = load float, ptr @a1, align 4
+%2 = load float, ptr @a2, align 4
+%3 = load float, ptr @a3, align 4
+%4 = load float, ptr @a4, align 4
+%5 = load float, ptr @a5, align 4
+%6 = load float, ptr @a6, align 4
+%7 = load float, ptr @a7, align 4
+%8 = load float, ptr @a8, align 4
tail call void @_Z3fooddddddddddddddd(float %1, float %2, float %3, float %4, float %5, float %6, float %7, float %8)
ret i32 0
}
diff --git a/llvm/test/CodeGen/ARM/ldstrex-m.ll b/llvm/test/CodeGen/ARM/ldstrex-m.ll
index 713fb9e3df011..67628b71b3706 100644
--- a/llvm/test/CodeGen/ARM/ldstrex-m.ll
+++ b/llvm/test/CodeGen/ARM/ldstrex-m.ll
@@ -4,53 +4,53 @@
; CHECK-LABEL: f0:
; CHECK-NOT: ldrexd
-define i64 @f0(i64* %p) nounwind readonly {
+define i64 @f0(ptr %p) nounwind readonly {
entry:
- %0 = load atomic i64, i64* %p seq_cst, align 8
+ %0 = load atomic i64, ptr %p seq_cst, align 8
ret i64 %0
}
; CHECK-LABEL: f1:
; CHECK-NOT: strexd
-define void @f1(i64* %p) nounwind readonly {
+define void @f1(ptr %p) nounwind readonly {
entry:
- store atomic i64 0, i64* %p seq_cst, align 8
+ store atomic i64 0, ptr %p seq_cst, align 8
ret void
}
; CHECK-LABEL: f2:
; CHECK-NOT: ldrexd
; CHECK-NOT: strexd
-define i64 @f2(i64* %p) nounwind readonly {
+define i64 @f2(ptr %p) nounwind readonly {
entry:
- %0 = atomicrmw add i64* %p, i64 1 seq_cst
+ %0 = atomicrmw add ptr %p, i64 1 seq_cst
ret i64 %0
}
; CHECK-LABEL: f3:
; CHECK-V7: ldr
; CHECK-V8: lda
-define i32 @f3(i32* %p) nounwind readonly {
+define i32 @f3(ptr %p) nounwind readonly {
entry:
- %0 = load atomic i32, i32* %p seq_cst, align 4
+ %0 = load atomic i32, ptr %p seq_cst, align 4
ret i32 %0
}
; CHECK-LABEL: f4:
; CHECK-V7: ldrb
; CHECK-V8: ldab
-define i8 @f4(i8* %p) nounwind readonly {
+define i8 @f4(ptr %p) nounwind readonly {
entry:
- %0 = load atomic i8, i8* %p seq_cst, align 4
+ %0 = load atomic i8, ptr %p seq_cst, align 4
ret i8 %0
}
; CHECK-LABEL: f5:
; CHECK-V7: str
; CHECK-V8: stl
-define void @f5(i32* %p) nounwind readonly {
+define void @f5(ptr %p) nounwind readonly {
entry:
- store atomic i32 0, i32* %p seq_cst, align 4
+ store atomic i32 0, ptr %p seq_cst, align 4
ret void
}
@@ -59,8 +59,8 @@ entry:
; CHECK-V7: strex
; CHECK-V8: ldaex
; CHECK-V8: stlex
-define i32 @f6(i32* %p) nounwind readonly {
+define i32 @f6(ptr %p) nounwind readonly {
entry:
- %0 = atomicrmw add i32* %p, i32 1 seq_cst
+ %0 = atomicrmw add ptr %p, i32 1 seq_cst
ret i32 %0
}
diff --git a/llvm/test/CodeGen/ARM/ldstrex.ll b/llvm/test/CodeGen/ARM/ldstrex.ll
index 7c97163854f15..614008fe394de 100644
--- a/llvm/test/CodeGen/ARM/ldstrex.ll
+++ b/llvm/test/CodeGen/ARM/ldstrex.ll
@@ -7,9 +7,9 @@
; CHECK-LABEL: f0:
; CHECK: ldrexd
-define i64 @f0(i8* %p) nounwind readonly {
+define i64 @f0(ptr %p) nounwind readonly {
entry:
- %ldrexd = tail call %0 @llvm.arm.ldrexd(i8* %p)
+ %ldrexd = tail call %0 @llvm.arm.ldrexd(ptr %p)
%0 = extractvalue %0 %ldrexd, 1
%1 = extractvalue %0 %ldrexd, 0
%2 = zext i32 %0 to i64
@@ -21,24 +21,24 @@ entry:
; CHECK-LABEL: f1:
; CHECK: strexd
-define i32 @f1(i8* %ptr, i64 %val) nounwind {
+define i32 @f1(ptr %ptr, i64 %val) nounwind {
entry:
%tmp4 = trunc i64 %val to i32
%tmp6 = lshr i64 %val, 32
%tmp7 = trunc i64 %tmp6 to i32
- %strexd = tail call i32 @llvm.arm.strexd(i32 %tmp4, i32 %tmp7, i8* %ptr)
+ %strexd = tail call i32 @llvm.arm.strexd(i32 %tmp4, i32 %tmp7, ptr %ptr)
ret i32 %strexd
}
-declare %0 @llvm.arm.ldrexd(i8*) nounwind readonly
-declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
+declare %0 @llvm.arm.ldrexd(ptr) nounwind readonly
+declare i32 @llvm.arm.strexd(i32, i32, ptr) nounwind
; CHECK-LABEL: test_load_i8:
; CHECK: ldrexb r0, [r0]
; CHECK-NOT: uxtb
; CHECK-NOT: and
-define zeroext i8 @test_load_i8(i8* %addr) {
- %val = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %addr)
+define zeroext i8 @test_load_i8(ptr %addr) {
+ %val = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %addr)
%val8 = trunc i32 %val to i8
ret i8 %val8
}
@@ -47,51 +47,47 @@ define zeroext i8 @test_load_i8(i8* %addr) {
; CHECK: ldrexh r0, [r0]
; CHECK-NOT: uxth
; CHECK-NOT: and
-define zeroext i16 @test_load_i16(i16* %addr) {
- %val = call i32 @llvm.arm.ldrex.p0i16(i16* elementtype(i16) %addr)
+define zeroext i16 @test_load_i16(ptr %addr) {
+ %val = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %addr)
%val16 = trunc i32 %val to i16
ret i16 %val16
}
; CHECK-LABEL: test_load_i32:
; CHECK: ldrex r0, [r0]
-define i32 @test_load_i32(i32* %addr) {
- %val = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
+define i32 @test_load_i32(ptr %addr) {
+ %val = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %addr)
ret i32 %val
}
-declare i32 @llvm.arm.ldrex.p0i8(i8*) nounwind readonly
-declare i32 @llvm.arm.ldrex.p0i16(i16*) nounwind readonly
-declare i32 @llvm.arm.ldrex.p0i32(i32*) nounwind readonly
+declare i32 @llvm.arm.ldrex.p0(ptr) nounwind readonly
; CHECK-LABEL: test_store_i8:
; CHECK-NOT: uxtb
; CHECK: strexb r0, r1, [r2]
-define i32 @test_store_i8(i32, i8 %val, i8* %addr) {
+define i32 @test_store_i8(i32, i8 %val, ptr %addr) {
%extval = zext i8 %val to i32
- %res = call i32 @llvm.arm.strex.p0i8(i32 %extval, i8* elementtype(i8) %addr)
+ %res = call i32 @llvm.arm.strex.p0(i32 %extval, ptr elementtype(i8) %addr)
ret i32 %res
}
; CHECK-LABEL: test_store_i16:
; CHECK-NOT: uxth
; CHECK: strexh r0, r1, [r2]
-define i32 @test_store_i16(i32, i16 %val, i16* %addr) {
+define i32 @test_store_i16(i32, i16 %val, ptr %addr) {
%extval = zext i16 %val to i32
- %res = call i32 @llvm.arm.strex.p0i16(i32 %extval, i16* elementtype(i16) %addr)
+ %res = call i32 @llvm.arm.strex.p0(i32 %extval, ptr elementtype(i16) %addr)
ret i32 %res
}
; CHECK-LABEL: test_store_i32:
; CHECK: strex r0, r1, [r2]
-define i32 @test_store_i32(i32, i32 %val, i32* %addr) {
- %res = call i32 @llvm.arm.strex.p0i32(i32 %val, i32* elementtype(i32) %addr)
+define i32 @test_store_i32(i32, i32 %val, ptr %addr) {
+ %res = call i32 @llvm.arm.strex.p0(i32 %val, ptr elementtype(i32) %addr)
ret i32 %res
}
-declare i32 @llvm.arm.strex.p0i8(i32, i8*) nounwind
-declare i32 @llvm.arm.strex.p0i16(i32, i16*) nounwind
-declare i32 @llvm.arm.strex.p0i32(i32, i32*) nounwind
+declare i32 @llvm.arm.strex.p0(i32, ptr) nounwind
; CHECK-LABEL: test_clear:
; CHECK: clrex
@@ -102,39 +98,36 @@ define void @test_clear() {
declare void @llvm.arm.clrex() nounwind
- at base = global i32* null
+ at base = global ptr null
define void @excl_addrmode() {
; CHECK-T2ADDRMODE-LABEL: excl_addrmode:
- %base1020 = load i32*, i32** @base
- %offset1020 = getelementptr i32, i32* %base1020, i32 255
- call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %offset1020)
- call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %offset1020)
+ %base1020 = load ptr, ptr @base
+ %offset1020 = getelementptr i32, ptr %base1020, i32 255
+ call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %offset1020)
+ call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %offset1020)
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [{{r[0-9]+}}, #1020]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}, #1020]
- %base1024 = load i32*, i32** @base
- %offset1024 = getelementptr i32, i32* %base1024, i32 256
- call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %offset1024)
- call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %offset1024)
+ %base1024 = load ptr, ptr @base
+ %offset1024 = getelementptr i32, ptr %base1024, i32 256
+ call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %offset1024)
+ call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %offset1024)
; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], {{r[0-9]+}}, #1024
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
- %base1 = load i32*, i32** @base
- %addr8 = bitcast i32* %base1 to i8*
- %offset1_8 = getelementptr i8, i8* %addr8, i32 1
- %offset1 = bitcast i8* %offset1_8 to i32*
- call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %offset1)
- call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %offset1)
+ %base1 = load ptr, ptr @base
+ %offset1_8 = getelementptr i8, ptr %base1, i32 1
+ call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %offset1_8)
+ call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %offset1_8)
; CHECK-T2ADDRMODE: adds r[[ADDR:[0-9]+]], #1
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
%local = alloca i8, i32 1024
- %local32 = bitcast i8* %local to i32*
- call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %local32)
- call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %local32)
+ call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %local)
+ call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %local)
; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
@@ -146,17 +139,15 @@ define void @test_excl_addrmode_folded() {
; CHECK-LABEL: test_excl_addrmode_folded:
%local = alloca i8, i32 4096
- %local.0 = getelementptr i8, i8* %local, i32 4
- %local32.0 = bitcast i8* %local.0 to i32*
- call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %local32.0)
- call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %local32.0)
+ %local.0 = getelementptr i8, ptr %local, i32 4
+ call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %local.0)
+ call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %local.0)
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #4]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #4]
- %local.1 = getelementptr i8, i8* %local, i32 1020
- %local32.1 = bitcast i8* %local.1 to i32*
- call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %local32.1)
- call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %local32.1)
+ %local.1 = getelementptr i8, ptr %local, i32 1020
+ call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %local.1)
+ call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %local.1)
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #1020]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #1020]
@@ -167,10 +158,9 @@ define void @test_excl_addrmode_range() {
; CHECK-LABEL: test_excl_addrmode_range:
%local = alloca i8, i32 4096
- %local.0 = getelementptr i8, i8* %local, i32 1024
- %local32.0 = bitcast i8* %local.0 to i32*
- call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %local32.0)
- call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %local32.0)
+ %local.0 = getelementptr i8, ptr %local, i32 1024
+ call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %local.0)
+ call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %local.0)
; CHECK-T2ADDRMODE: mov r[[TMP:[0-9]+]], sp
; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], r[[TMP]], #1024
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
@@ -183,10 +173,9 @@ define void @test_excl_addrmode_align() {
; CHECK-LABEL: test_excl_addrmode_align:
%local = alloca i8, i32 4096
- %local.0 = getelementptr i8, i8* %local, i32 2
- %local32.0 = bitcast i8* %local.0 to i32*
- call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %local32.0)
- call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %local32.0)
+ %local.0 = getelementptr i8, ptr %local, i32 2
+ call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %local.0)
+ call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %local.0)
; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp
; CHECK-T2ADDRMODE: adds r[[ADDR:[0-9]+]], #2
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
@@ -199,10 +188,9 @@ define void @test_excl_addrmode_sign() {
; CHECK-LABEL: test_excl_addrmode_sign:
%local = alloca i8, i32 4096
- %local.0 = getelementptr i8, i8* %local, i32 -4
- %local32.0 = bitcast i8* %local.0 to i32*
- call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %local32.0)
- call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %local32.0)
+ %local.0 = getelementptr i8, ptr %local, i32 -4
+ call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %local.0)
+ call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %local.0)
; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp
; CHECK-T2ADDRMODE: subs r[[ADDR:[0-9]+]], #4
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
@@ -216,10 +204,9 @@ define void @test_excl_addrmode_combination() {
%local = alloca i8, i32 4096
%unused = alloca i8, i32 64
- %local.0 = getelementptr i8, i8* %local, i32 4
- %local32.0 = bitcast i8* %local.0 to i32*
- call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %local32.0)
- call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %local32.0)
+ %local.0 = getelementptr i8, ptr %local, i32 4
+ call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %local.0)
+ call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %local.0)
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #68]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #68]
@@ -229,12 +216,12 @@ define void @test_excl_addrmode_combination() {
; LLVM should know, even across basic blocks, that ldrex is setting the high
; bits of its i32 to 0. There should be no zero-extend operation.
-define zeroext i8 @test_cross_block_zext_i8(i1 %tst, i8* %addr) {
+define zeroext i8 @test_cross_block_zext_i8(i1 %tst, ptr %addr) {
; CHECK: test_cross_block_zext_i8:
; CHECK-NOT: uxtb
; CHECK-NOT: and
; CHECK: bx lr
- %val = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %addr)
+ %val = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %addr)
br i1 %tst, label %end, label %mid
mid:
ret i8 42
diff --git a/llvm/test/CodeGen/ARM/legalize-bitcast.ll b/llvm/test/CodeGen/ARM/legalize-bitcast.ll
index 67ea37aa35033..5b989a099c815 100644
--- a/llvm/test/CodeGen/ARM/legalize-bitcast.ll
+++ b/llvm/test/CodeGen/ARM/legalize-bitcast.ll
@@ -29,7 +29,7 @@ define i32 @vec_to_int() {
; CHECK-NEXT: pop {r4}
; CHECK-NEXT: bx lr
bb.0:
- %vec6 = load <6 x i16>, <6 x i16>* @vec6_p, align 1
+ %vec6 = load <6 x i16>, ptr @vec6_p, align 1
br label %bb.1
bb.1:
diff --git a/llvm/test/CodeGen/ARM/legalize-fneg.ll b/llvm/test/CodeGen/ARM/legalize-fneg.ll
index f7578ae98fa2d..e4de8a9ed8ac0 100644
--- a/llvm/test/CodeGen/ARM/legalize-fneg.ll
+++ b/llvm/test/CodeGen/ARM/legalize-fneg.ll
@@ -5,7 +5,7 @@
; RUN: | FileCheck --check-prefixes=NOLIB %s
; Check Y = FNEG(X) -> Y = X ^ sign mask and no lib call is generated.
-define void @test1(float* %a, float* %b) {
+define void @test1(ptr %a, ptr %b) {
; ARM-LABEL: test1:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldr r1, [r1]
@@ -16,13 +16,13 @@ define void @test1(float* %a, float* %b) {
; NOLIB: eor
; NOLIB-NOT: bl __aeabi_fsub
entry:
- %0 = load float, float* %b
+ %0 = load float, ptr %b
%neg = fneg float %0
- store float %neg, float* %a
+ store float %neg, ptr %a
ret void
}
-define void @test2(double* %a, double* %b) {
+define void @test2(ptr %a, ptr %b) {
; ARM-LABEL: test2:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldr r2, [r1]
@@ -35,13 +35,13 @@ define void @test2(double* %a, double* %b) {
; NOLIB: eor
; NOLIB-NOT: bl __aeabi_dsub
entry:
- %0 = load double, double* %b
+ %0 = load double, ptr %b
%neg = fneg double %0
- store double %neg, double* %a
+ store double %neg, ptr %a
ret void
}
-define void @test3(fp128* %a, fp128* %b) {
+define void @test3(ptr %a, ptr %b) {
; ARM-LABEL: test3:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldm r1, {r2, r3, r12}
@@ -54,8 +54,8 @@ define void @test3(fp128* %a, fp128* %b) {
; NOLIB: eor
; NOLIB-NOT: bl __subtf3
entry:
- %0 = load fp128, fp128* %b
+ %0 = load fp128, ptr %b
%neg = fneg fp128 %0
- store fp128 %neg, fp128* %a
+ store fp128 %neg, ptr %a
ret void
}
diff --git a/llvm/test/CodeGen/ARM/legalize-unaligned-load.ll b/llvm/test/CodeGen/ARM/legalize-unaligned-load.ll
index 3defd7623e92a..d7c70f2d9ee60 100644
--- a/llvm/test/CodeGen/ARM/legalize-unaligned-load.ll
+++ b/llvm/test/CodeGen/ARM/legalize-unaligned-load.ll
@@ -11,25 +11,22 @@
; CHECK: ldr
; CHECK: str
; CHECK: {{bx|pop.*pc}}
-define i32 @get_set_complex({ float, float }* noalias nocapture %retptr,
- { i8*, i32 }** noalias nocapture readnone %excinfo,
- i8* noalias nocapture readnone %env,
- [38 x i8]* nocapture %arg.rec,
+define i32 @get_set_complex(ptr noalias nocapture %retptr,
+ ptr noalias nocapture readnone %excinfo,
+ ptr noalias nocapture readnone %env,
+ ptr nocapture %arg.rec,
float %arg.val.0, float %arg.val.1)
{
entry:
%inserted.real = insertvalue { float, float } undef, float %arg.val.0, 0
%inserted.imag = insertvalue { float, float } %inserted.real, float %arg.val.1, 1
- %.15 = getelementptr inbounds [38 x i8], [38 x i8]* %arg.rec, i32 0, i32 10
- %.16 = bitcast i8* %.15 to { float, float }*
- %.17 = bitcast i8* %.15 to float*
- %.18 = load float, float* %.17, align 1
- %.19 = getelementptr inbounds [38 x i8], [38 x i8]* %arg.rec, i32 0, i32 14
- %tmp = bitcast i8* %.19 to float*
- %.20 = load float, float* %tmp, align 1
+ %.15 = getelementptr inbounds [38 x i8], ptr %arg.rec, i32 0, i32 10
+ %.18 = load float, ptr %.15, align 1
+ %.19 = getelementptr inbounds [38 x i8], ptr %arg.rec, i32 0, i32 14
+ %.20 = load float, ptr %.19, align 1
%inserted.real.1 = insertvalue { float, float } undef, float %.18, 0
%inserted.imag.1 = insertvalue { float, float } %inserted.real.1, float %.20, 1
- store { float, float } %inserted.imag, { float, float }* %.16, align 1
- store { float, float } %inserted.imag.1, { float, float }* %retptr, align 4
+ store { float, float } %inserted.imag, ptr %.15, align 1
+ store { float, float } %inserted.imag.1, ptr %retptr, align 4
ret i32 0
}
diff --git a/llvm/test/CodeGen/ARM/litpool-licm.ll b/llvm/test/CodeGen/ARM/litpool-licm.ll
index 923971d1afe19..f1a029b83f831 100644
--- a/llvm/test/CodeGen/ARM/litpool-licm.ll
+++ b/llvm/test/CodeGen/ARM/litpool-licm.ll
@@ -26,12 +26,12 @@ entry:
loop:
%i = phi i32 [ %inc, %next ], [ 0, %entry ]
- %val = load i32, i32* @var
+ %val = load i32, ptr @var
%tst = icmp eq i32 %val, 0
br i1 %tst, label %next, label %call
call:
- tail call void @foo(i32* nonnull @var) #2
+ tail call void @foo(ptr nonnull @var) #2
br label %next
next:
@@ -43,4 +43,4 @@ done:
ret void
}
-declare void @foo(i32*)
+declare void @foo(ptr)
diff --git a/llvm/test/CodeGen/ARM/load-address-masked.ll b/llvm/test/CodeGen/ARM/load-address-masked.ll
index 65cc31104bc95..f15523cbad85d 100644
--- a/llvm/test/CodeGen/ARM/load-address-masked.ll
+++ b/llvm/test/CodeGen/ARM/load-address-masked.ll
@@ -7,7 +7,7 @@ target triple = "armv4t-unknown-linux-gnueabi"
define i32 @foo() {
entry:
- ret i32 and (i32 ptrtoint (i32* @a to i32), i32 255)
+ ret i32 and (i32 ptrtoint (ptr @a to i32), i32 255)
}
; CHECK-LABEL: foo:
diff --git a/llvm/test/CodeGen/ARM/load-arm.ll b/llvm/test/CodeGen/ARM/load-arm.ll
index 3807424ece81a..225b092e98024 100644
--- a/llvm/test/CodeGen/ARM/load-arm.ll
+++ b/llvm/test/CodeGen/ARM/load-arm.ll
@@ -8,20 +8,20 @@
; CHECK-LABEL: addrmode_cse_mutation:
; CHECK: {{mul|muls}} [[OFFSET:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
; CHECK: {{ldrb|ldrb.w}} {{r[0-9]+}}, [r0, [[OFFSET]], lsl #3]
-define i32 @addrmode_cse_mutation(i8* %base, i32 %count) {
+define i32 @addrmode_cse_mutation(ptr %base, i32 %count) {
%offset = mul i32 %count, 277288
- %ptr = getelementptr i8, i8* %base, i32 %offset
- %val = load volatile i8, i8* %ptr
+ %ptr = getelementptr i8, ptr %base, i32 %offset
+ %val = load volatile i8, ptr %ptr
%res = mul i32 %count, 34661
ret i32 %res
}
; CHECK-LABEL: addrmode_cse_multi_use:
; CHECK-NOT: {{ldrb|ldrb.w}} {{r[0-9]+}}, [{{r[0-9]+}}, {{r[0-9]+}}, lsl #3]
-define i32 @addrmode_cse_multi_use(i8* %base, i32 %count) {
+define i32 @addrmode_cse_multi_use(ptr %base, i32 %count) {
%offset = mul i32 %count, 277288
- %ptr = getelementptr i8, i8* %base, i32 %offset
- %val = load volatile i8, i8* %ptr
+ %ptr = getelementptr i8, ptr %base, i32 %offset
+ %val = load volatile i8, ptr %ptr
%res = mul i32 %count, 34661
%res.1 = add i32 %res, %offset
ret i32 %res.1
diff --git a/llvm/test/CodeGen/ARM/load-combine-big-endian.ll b/llvm/test/CodeGen/ARM/load-combine-big-endian.ll
index 010f22df64fdc..4b6d14efd0ecb 100644
--- a/llvm/test/CodeGen/ARM/load-combine-big-endian.ll
+++ b/llvm/test/CodeGen/ARM/load-combine-big-endian.ll
@@ -4,9 +4,9 @@
; RUN: llc < %s -mtriple=thumbv6meb-none-eabi | FileCheck %s --check-prefix=CHECK-THUMBv6
; RUN: llc < %s -mtriple=thumbv6meb-none-eabi | FileCheck %s --check-prefix=CHECK-THUMBv7
-; i8* p; // p is 4 byte aligned
+; ptr p; // p is 4 byte aligned
; ((i32) p[0] << 24) | ((i32) p[1] << 16) | ((i32) p[2] << 8) | (i32) p[3]
-define i32 @load_i32_by_i8_big_endian(i32* %arg) {
+define i32 @load_i32_by_i8_big_endian(ptr %arg) {
; CHECK-LABEL: load_i32_by_i8_big_endian:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0]
@@ -27,30 +27,29 @@ define i32 @load_i32_by_i8_big_endian(i32* %arg) {
; CHECK-THUMBv7-NEXT: ldr r0, [r0]
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = load i8, i8* %tmp, align 4
+ %tmp1 = load i8, ptr %arg, align 4
%tmp2 = zext i8 %tmp1 to i32
%tmp3 = shl nuw nsw i32 %tmp2, 24
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 16
%tmp8 = or i32 %tmp7, %tmp3
- %tmp9 = getelementptr inbounds i8, i8* %tmp, i32 2
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i32 2
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i32
%tmp12 = shl nuw nsw i32 %tmp11, 8
%tmp13 = or i32 %tmp8, %tmp12
- %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 3
- %tmp15 = load i8, i8* %tmp14, align 1
+ %tmp14 = getelementptr inbounds i8, ptr %arg, i32 3
+ %tmp15 = load i8, ptr %tmp14, align 1
%tmp16 = zext i8 %tmp15 to i32
%tmp17 = or i32 %tmp13, %tmp16
ret i32 %tmp17
}
-; i8* p; // p is 4 byte aligned
+; ptr p; // p is 4 byte aligned
; (i32) p[0] | ((i32) p[1] << 8) | ((i32) p[2] << 16) | ((i32) p[3] << 24)
-define i32 @load_i32_by_i8_bswap(i32* %arg) {
+define i32 @load_i32_by_i8_bswap(ptr %arg) {
; BSWAP is not supported by 32 bit target
; CHECK-LABEL: load_i32_by_i8_bswap:
; CHECK: @ %bb.0:
@@ -82,31 +81,29 @@ define i32 @load_i32_by_i8_bswap(i32* %arg) {
; CHECK-THUMBv7-NEXT: rev r0, r0
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
- %tmp2 = load i8, i8* %tmp1, align 4
+ %tmp2 = load i8, ptr %arg, align 4
%tmp3 = zext i8 %tmp2 to i32
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 8
%tmp8 = or i32 %tmp7, %tmp3
- %tmp9 = getelementptr inbounds i8, i8* %tmp, i32 2
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i32 2
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i32
%tmp12 = shl nuw nsw i32 %tmp11, 16
%tmp13 = or i32 %tmp8, %tmp12
- %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 3
- %tmp15 = load i8, i8* %tmp14, align 1
+ %tmp14 = getelementptr inbounds i8, ptr %arg, i32 3
+ %tmp15 = load i8, ptr %tmp14, align 1
%tmp16 = zext i8 %tmp15 to i32
%tmp17 = shl nuw nsw i32 %tmp16, 24
%tmp18 = or i32 %tmp13, %tmp17
ret i32 %tmp18
}
-; i8* p; // p is 4 byte aligned
+; ptr p; // p is 4 byte aligned
; ((i32) (((i16) p[0] << 8) | (i16) p[1]) << 16) | (i32) (((i16) p[3] << 8) | (i16) p[4])
-define i32 @load_i32_by_i16_by_i8_big_endian(i32* %arg) {
+define i32 @load_i32_by_i16_by_i8_big_endian(ptr %arg) {
; CHECK-LABEL: load_i32_by_i16_by_i8_big_endian:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0]
@@ -127,19 +124,18 @@ define i32 @load_i32_by_i16_by_i8_big_endian(i32* %arg) {
; CHECK-THUMBv7-NEXT: ldr r0, [r0]
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = load i8, i8* %tmp, align 4
+ %tmp1 = load i8, ptr %arg, align 4
%tmp2 = zext i8 %tmp1 to i16
- %tmp3 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp4 = load i8, i8* %tmp3, align 1
+ %tmp3 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp4 = load i8, ptr %tmp3, align 1
%tmp5 = zext i8 %tmp4 to i16
%tmp6 = shl nuw nsw i16 %tmp2, 8
%tmp7 = or i16 %tmp6, %tmp5
- %tmp8 = getelementptr inbounds i8, i8* %tmp, i32 2
- %tmp9 = load i8, i8* %tmp8, align 1
+ %tmp8 = getelementptr inbounds i8, ptr %arg, i32 2
+ %tmp9 = load i8, ptr %tmp8, align 1
%tmp10 = zext i8 %tmp9 to i16
- %tmp11 = getelementptr inbounds i8, i8* %tmp, i32 3
- %tmp12 = load i8, i8* %tmp11, align 1
+ %tmp11 = getelementptr inbounds i8, ptr %arg, i32 3
+ %tmp12 = load i8, ptr %tmp11, align 1
%tmp13 = zext i8 %tmp12 to i16
%tmp14 = shl nuw nsw i16 %tmp10, 8
%tmp15 = or i16 %tmp14, %tmp13
@@ -150,9 +146,9 @@ define i32 @load_i32_by_i16_by_i8_big_endian(i32* %arg) {
ret i32 %tmp19
}
-; i16* p; // p is 4 byte aligned
+; ptr p; // p is 4 byte aligned
; ((i32) p[0] << 16) | (i32) p[1]
-define i32 @load_i32_by_i16(i32* %arg) {
+define i32 @load_i32_by_i16(ptr %arg) {
; CHECK-LABEL: load_i32_by_i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0]
@@ -173,21 +169,20 @@ define i32 @load_i32_by_i16(i32* %arg) {
; CHECK-THUMBv7-NEXT: ldr r0, [r0]
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i16*
- %tmp1 = load i16, i16* %tmp, align 4
+ %tmp1 = load i16, ptr %arg, align 4
%tmp2 = zext i16 %tmp1 to i32
- %tmp3 = getelementptr inbounds i16, i16* %tmp, i32 1
- %tmp4 = load i16, i16* %tmp3, align 1
+ %tmp3 = getelementptr inbounds i16, ptr %arg, i32 1
+ %tmp4 = load i16, ptr %tmp3, align 1
%tmp5 = zext i16 %tmp4 to i32
%tmp6 = shl nuw nsw i32 %tmp2, 16
%tmp7 = or i32 %tmp6, %tmp5
ret i32 %tmp7
}
-; i16* p_16; // p_16 is 4 byte aligned
-; i8* p_8 = (i8*) p_16;
+; ptr p_16; // p_16 is 4 byte aligned
+; ptr p_8 = (ptr) p_16;
; (i32) (p_16[0] << 16) | ((i32) p[2] << 8) | (i32) p[3]
-define i32 @load_i32_by_i16_i8(i32* %arg) {
+define i32 @load_i32_by_i16_i8(ptr %arg) {
; CHECK-LABEL: load_i32_by_i16_i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0]
@@ -208,26 +203,24 @@ define i32 @load_i32_by_i16_i8(i32* %arg) {
; CHECK-THUMBv7-NEXT: ldr r0, [r0]
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i16*
- %tmp1 = bitcast i32* %arg to i8*
- %tmp2 = load i16, i16* %tmp, align 4
+ %tmp2 = load i16, ptr %arg, align 4
%tmp3 = zext i16 %tmp2 to i32
%tmp4 = shl nuw nsw i32 %tmp3, 16
- %tmp5 = getelementptr inbounds i8, i8* %tmp1, i32 2
- %tmp6 = load i8, i8* %tmp5, align 1
+ %tmp5 = getelementptr inbounds i8, ptr %arg, i32 2
+ %tmp6 = load i8, ptr %tmp5, align 1
%tmp7 = zext i8 %tmp6 to i32
%tmp8 = shl nuw nsw i32 %tmp7, 8
- %tmp9 = getelementptr inbounds i8, i8* %tmp1, i32 3
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i32 3
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i32
%tmp12 = or i32 %tmp8, %tmp11
%tmp13 = or i32 %tmp12, %tmp4
ret i32 %tmp13
}
-; i8* p; // p is 8 byte aligned
+; ptr p; // p is 8 byte aligned
; (i64) p[0] | ((i64) p[1] << 8) | ((i64) p[2] << 16) | ((i64) p[3] << 24) | ((i64) p[4] << 32) | ((i64) p[5] << 40) | ((i64) p[6] << 48) | ((i64) p[7] << 56)
-define i64 @load_i64_by_i8_bswap(i64* %arg) {
+define i64 @load_i64_by_i8_bswap(ptr %arg) {
; CHECK-LABEL: load_i64_by_i8_bswap:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r1, [r0]
@@ -270,50 +263,49 @@ define i64 @load_i64_by_i8_bswap(i64* %arg) {
; CHECK-THUMBv7-NEXT: rev r1, r1
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i64* %arg to i8*
- %tmp1 = load i8, i8* %tmp, align 8
+ %tmp1 = load i8, ptr %arg, align 8
%tmp2 = zext i8 %tmp1 to i64
- %tmp3 = getelementptr inbounds i8, i8* %tmp, i64 1
- %tmp4 = load i8, i8* %tmp3, align 1
+ %tmp3 = getelementptr inbounds i8, ptr %arg, i64 1
+ %tmp4 = load i8, ptr %tmp3, align 1
%tmp5 = zext i8 %tmp4 to i64
%tmp6 = shl nuw nsw i64 %tmp5, 8
%tmp7 = or i64 %tmp6, %tmp2
- %tmp8 = getelementptr inbounds i8, i8* %tmp, i64 2
- %tmp9 = load i8, i8* %tmp8, align 1
+ %tmp8 = getelementptr inbounds i8, ptr %arg, i64 2
+ %tmp9 = load i8, ptr %tmp8, align 1
%tmp10 = zext i8 %tmp9 to i64
%tmp11 = shl nuw nsw i64 %tmp10, 16
%tmp12 = or i64 %tmp7, %tmp11
- %tmp13 = getelementptr inbounds i8, i8* %tmp, i64 3
- %tmp14 = load i8, i8* %tmp13, align 1
+ %tmp13 = getelementptr inbounds i8, ptr %arg, i64 3
+ %tmp14 = load i8, ptr %tmp13, align 1
%tmp15 = zext i8 %tmp14 to i64
%tmp16 = shl nuw nsw i64 %tmp15, 24
%tmp17 = or i64 %tmp12, %tmp16
- %tmp18 = getelementptr inbounds i8, i8* %tmp, i64 4
- %tmp19 = load i8, i8* %tmp18, align 1
+ %tmp18 = getelementptr inbounds i8, ptr %arg, i64 4
+ %tmp19 = load i8, ptr %tmp18, align 1
%tmp20 = zext i8 %tmp19 to i64
%tmp21 = shl nuw nsw i64 %tmp20, 32
%tmp22 = or i64 %tmp17, %tmp21
- %tmp23 = getelementptr inbounds i8, i8* %tmp, i64 5
- %tmp24 = load i8, i8* %tmp23, align 1
+ %tmp23 = getelementptr inbounds i8, ptr %arg, i64 5
+ %tmp24 = load i8, ptr %tmp23, align 1
%tmp25 = zext i8 %tmp24 to i64
%tmp26 = shl nuw nsw i64 %tmp25, 40
%tmp27 = or i64 %tmp22, %tmp26
- %tmp28 = getelementptr inbounds i8, i8* %tmp, i64 6
- %tmp29 = load i8, i8* %tmp28, align 1
+ %tmp28 = getelementptr inbounds i8, ptr %arg, i64 6
+ %tmp29 = load i8, ptr %tmp28, align 1
%tmp30 = zext i8 %tmp29 to i64
%tmp31 = shl nuw nsw i64 %tmp30, 48
%tmp32 = or i64 %tmp27, %tmp31
- %tmp33 = getelementptr inbounds i8, i8* %tmp, i64 7
- %tmp34 = load i8, i8* %tmp33, align 1
+ %tmp33 = getelementptr inbounds i8, ptr %arg, i64 7
+ %tmp34 = load i8, ptr %tmp33, align 1
%tmp35 = zext i8 %tmp34 to i64
%tmp36 = shl nuw i64 %tmp35, 56
%tmp37 = or i64 %tmp32, %tmp36
ret i64 %tmp37
}
-; i8* p; // p is 8 byte aligned
+; ptr p; // p is 8 byte aligned
; ((i64) p[0] << 56) | ((i64) p[1] << 48) | ((i64) p[2] << 40) | ((i64) p[3] << 32) | ((i64) p[4] << 24) | ((i64) p[5] << 16) | ((i64) p[6] << 8) | (i64) p[7]
-define i64 @load_i64_by_i8(i64* %arg) {
+define i64 @load_i64_by_i8(ptr %arg) {
; CHECK-LABEL: load_i64_by_i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r2, [r0]
@@ -340,50 +332,49 @@ define i64 @load_i64_by_i8(i64* %arg) {
; CHECK-THUMBv7-NEXT: mov r0, r2
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i64* %arg to i8*
- %tmp1 = load i8, i8* %tmp, align 8
+ %tmp1 = load i8, ptr %arg, align 8
%tmp2 = zext i8 %tmp1 to i64
%tmp3 = shl nuw i64 %tmp2, 56
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i64 1
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i64 1
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i64
%tmp7 = shl nuw nsw i64 %tmp6, 48
%tmp8 = or i64 %tmp7, %tmp3
- %tmp9 = getelementptr inbounds i8, i8* %tmp, i64 2
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i64 2
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i64
%tmp12 = shl nuw nsw i64 %tmp11, 40
%tmp13 = or i64 %tmp8, %tmp12
- %tmp14 = getelementptr inbounds i8, i8* %tmp, i64 3
- %tmp15 = load i8, i8* %tmp14, align 1
+ %tmp14 = getelementptr inbounds i8, ptr %arg, i64 3
+ %tmp15 = load i8, ptr %tmp14, align 1
%tmp16 = zext i8 %tmp15 to i64
%tmp17 = shl nuw nsw i64 %tmp16, 32
%tmp18 = or i64 %tmp13, %tmp17
- %tmp19 = getelementptr inbounds i8, i8* %tmp, i64 4
- %tmp20 = load i8, i8* %tmp19, align 1
+ %tmp19 = getelementptr inbounds i8, ptr %arg, i64 4
+ %tmp20 = load i8, ptr %tmp19, align 1
%tmp21 = zext i8 %tmp20 to i64
%tmp22 = shl nuw nsw i64 %tmp21, 24
%tmp23 = or i64 %tmp18, %tmp22
- %tmp24 = getelementptr inbounds i8, i8* %tmp, i64 5
- %tmp25 = load i8, i8* %tmp24, align 1
+ %tmp24 = getelementptr inbounds i8, ptr %arg, i64 5
+ %tmp25 = load i8, ptr %tmp24, align 1
%tmp26 = zext i8 %tmp25 to i64
%tmp27 = shl nuw nsw i64 %tmp26, 16
%tmp28 = or i64 %tmp23, %tmp27
- %tmp29 = getelementptr inbounds i8, i8* %tmp, i64 6
- %tmp30 = load i8, i8* %tmp29, align 1
+ %tmp29 = getelementptr inbounds i8, ptr %arg, i64 6
+ %tmp30 = load i8, ptr %tmp29, align 1
%tmp31 = zext i8 %tmp30 to i64
%tmp32 = shl nuw nsw i64 %tmp31, 8
%tmp33 = or i64 %tmp28, %tmp32
- %tmp34 = getelementptr inbounds i8, i8* %tmp, i64 7
- %tmp35 = load i8, i8* %tmp34, align 1
+ %tmp34 = getelementptr inbounds i8, ptr %arg, i64 7
+ %tmp35 = load i8, ptr %tmp34, align 1
%tmp36 = zext i8 %tmp35 to i64
%tmp37 = or i64 %tmp33, %tmp36
ret i64 %tmp37
}
-; i8* p; // p[1] is 4 byte aligned
+; ptr p; // p[1] is 4 byte aligned
; (i32) p[1] | ((i32) p[2] << 8) | ((i32) p[3] << 16) | ((i32) p[4] << 24)
-define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
+define i32 @load_i32_by_i8_nonzero_offset(ptr %arg) {
; CHECK-LABEL: load_i32_by_i8_nonzero_offset:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0, #1]
@@ -417,31 +408,30 @@ define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp2 = load i8, i8* %tmp1, align 4
+ %tmp1 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp2 = load i8, ptr %tmp1, align 4
%tmp3 = zext i8 %tmp2 to i32
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 2
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 2
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 8
%tmp8 = or i32 %tmp7, %tmp3
- %tmp9 = getelementptr inbounds i8, i8* %tmp, i32 3
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i32 3
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i32
%tmp12 = shl nuw nsw i32 %tmp11, 16
%tmp13 = or i32 %tmp8, %tmp12
- %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 4
- %tmp15 = load i8, i8* %tmp14, align 1
+ %tmp14 = getelementptr inbounds i8, ptr %arg, i32 4
+ %tmp15 = load i8, ptr %tmp14, align 1
%tmp16 = zext i8 %tmp15 to i32
%tmp17 = shl nuw nsw i32 %tmp16, 24
%tmp18 = or i32 %tmp13, %tmp17
ret i32 %tmp18
}
-; i8* p; // p[-4] is 4 byte aligned
+; ptr p; // p[-4] is 4 byte aligned
; (i32) p[-4] | ((i32) p[-3] << 8) | ((i32) p[-2] << 16) | ((i32) p[-1] << 24)
-define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
+define i32 @load_i32_by_i8_neg_offset(ptr %arg) {
; CHECK-LABEL: load_i32_by_i8_neg_offset:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0, #-4]
@@ -475,31 +465,30 @@ define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 -4
- %tmp2 = load i8, i8* %tmp1, align 4
+ %tmp1 = getelementptr inbounds i8, ptr %arg, i32 -4
+ %tmp2 = load i8, ptr %tmp1, align 4
%tmp3 = zext i8 %tmp2 to i32
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 -3
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 -3
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 8
%tmp8 = or i32 %tmp7, %tmp3
- %tmp9 = getelementptr inbounds i8, i8* %tmp, i32 -2
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i32 -2
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i32
%tmp12 = shl nuw nsw i32 %tmp11, 16
%tmp13 = or i32 %tmp8, %tmp12
- %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 -1
- %tmp15 = load i8, i8* %tmp14, align 1
+ %tmp14 = getelementptr inbounds i8, ptr %arg, i32 -1
+ %tmp15 = load i8, ptr %tmp14, align 1
%tmp16 = zext i8 %tmp15 to i32
%tmp17 = shl nuw nsw i32 %tmp16, 24
%tmp18 = or i32 %tmp13, %tmp17
ret i32 %tmp18
}
-; i8* p; // p[1] is 4 byte aligned
+; ptr p; // p[1] is 4 byte aligned
; (i32) p[4] | ((i32) p[3] << 8) | ((i32) p[2] << 16) | ((i32) p[1] << 24)
-define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
+define i32 @load_i32_by_i8_nonzero_offset_bswap(ptr %arg) {
; CHECK-LABEL: load_i32_by_i8_nonzero_offset_bswap:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0, #1]
@@ -523,31 +512,30 @@ define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 4
- %tmp2 = load i8, i8* %tmp1, align 1
+ %tmp1 = getelementptr inbounds i8, ptr %arg, i32 4
+ %tmp2 = load i8, ptr %tmp1, align 1
%tmp3 = zext i8 %tmp2 to i32
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 3
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 3
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 8
%tmp8 = or i32 %tmp7, %tmp3
- %tmp9 = getelementptr inbounds i8, i8* %tmp, i32 2
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i32 2
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i32
%tmp12 = shl nuw nsw i32 %tmp11, 16
%tmp13 = or i32 %tmp8, %tmp12
- %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp15 = load i8, i8* %tmp14, align 4
+ %tmp14 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp15 = load i8, ptr %tmp14, align 4
%tmp16 = zext i8 %tmp15 to i32
%tmp17 = shl nuw nsw i32 %tmp16, 24
%tmp18 = or i32 %tmp13, %tmp17
ret i32 %tmp18
}
-; i8* p; // p[-4] is 4 byte aligned
+; ptr p; // p[-4] is 4 byte aligned
; (i32) p[-1] | ((i32) p[-2] << 8) | ((i32) p[-3] << 16) | ((i32) p[-4] << 24)
-define i32 @load_i32_by_i8_neg_offset_bswap(i32* %arg) {
+define i32 @load_i32_by_i8_neg_offset_bswap(ptr %arg) {
; CHECK-LABEL: load_i32_by_i8_neg_offset_bswap:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0, #-4]
@@ -571,22 +559,21 @@ define i32 @load_i32_by_i8_neg_offset_bswap(i32* %arg) {
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 -1
- %tmp2 = load i8, i8* %tmp1, align 1
+ %tmp1 = getelementptr inbounds i8, ptr %arg, i32 -1
+ %tmp2 = load i8, ptr %tmp1, align 1
%tmp3 = zext i8 %tmp2 to i32
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 -2
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 -2
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 8
%tmp8 = or i32 %tmp7, %tmp3
- %tmp9 = getelementptr inbounds i8, i8* %tmp, i32 -3
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i32 -3
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i32
%tmp12 = shl nuw nsw i32 %tmp11, 16
%tmp13 = or i32 %tmp8, %tmp12
- %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 -4
- %tmp15 = load i8, i8* %tmp14, align 4
+ %tmp14 = getelementptr inbounds i8, ptr %arg, i32 -4
+ %tmp15 = load i8, ptr %tmp14, align 4
%tmp16 = zext i8 %tmp15 to i32
%tmp17 = shl nuw nsw i32 %tmp16, 24
%tmp18 = or i32 %tmp13, %tmp17
@@ -595,9 +582,9 @@ define i32 @load_i32_by_i8_neg_offset_bswap(i32* %arg) {
declare i16 @llvm.bswap.i16(i16)
-; i16* p; // p is 4 byte aligned
+; ptr p; // p is 4 byte aligned
; (i32) bswap(p[0]) | (i32) bswap(p[1] << 16)
-define i32 @load_i32_by_bswap_i16(i32* %arg) {
+define i32 @load_i32_by_bswap_i16(ptr %arg) {
; CHECK-LABEL: load_i32_by_bswap_i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0]
@@ -629,12 +616,11 @@ define i32 @load_i32_by_bswap_i16(i32* %arg) {
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i16*
- %tmp1 = load i16, i16* %tmp, align 4
+ %tmp1 = load i16, ptr %arg, align 4
%tmp11 = call i16 @llvm.bswap.i16(i16 %tmp1)
%tmp2 = zext i16 %tmp11 to i32
- %tmp3 = getelementptr inbounds i16, i16* %tmp, i32 1
- %tmp4 = load i16, i16* %tmp3, align 1
+ %tmp3 = getelementptr inbounds i16, ptr %arg, i32 1
+ %tmp4 = load i16, ptr %tmp3, align 1
%tmp41 = call i16 @llvm.bswap.i16(i16 %tmp4)
%tmp5 = zext i16 %tmp41 to i32
%tmp6 = shl nuw nsw i32 %tmp5, 16
@@ -642,9 +628,9 @@ define i32 @load_i32_by_bswap_i16(i32* %arg) {
ret i32 %tmp7
}
-; i16* p; // p is 4 byte aligned
+; ptr p; // p is 4 byte aligned
; (i32) p[1] | (sext(p[0] << 16) to i32)
-define i32 @load_i32_by_sext_i16(i32* %arg) {
+define i32 @load_i32_by_sext_i16(ptr %arg) {
; CHECK-LABEL: load_i32_by_sext_i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0]
@@ -664,21 +650,20 @@ define i32 @load_i32_by_sext_i16(i32* %arg) {
; CHECK-THUMBv7: @ %bb.0:
; CHECK-THUMBv7-NEXT: ldr r0, [r0]
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i16*
- %tmp1 = load i16, i16* %tmp, align 4
+ %tmp1 = load i16, ptr %arg, align 4
%tmp2 = sext i16 %tmp1 to i32
- %tmp3 = getelementptr inbounds i16, i16* %tmp, i32 1
- %tmp4 = load i16, i16* %tmp3, align 1
+ %tmp3 = getelementptr inbounds i16, ptr %arg, i32 1
+ %tmp4 = load i16, ptr %tmp3, align 1
%tmp5 = zext i16 %tmp4 to i32
%tmp6 = shl nuw nsw i32 %tmp2, 16
%tmp7 = or i32 %tmp6, %tmp5
ret i32 %tmp7
}
-; i8* arg; i32 i;
+; ptr arg; i32 i;
; p = arg + 12;
; (i32) p[i] | ((i32) p[i + 1] << 8) | ((i32) p[i + 2] << 16) | ((i32) p[i + 3] << 24)
-define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
+define i32 @load_i32_by_i8_base_offset_index(ptr %arg, i32 %i) {
; CHECK-LABEL: load_i32_by_i8_base_offset_index:
; CHECK: @ %bb.0:
; CHECK-NEXT: add r0, r0, r1
@@ -715,36 +700,36 @@ define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
%tmp = add nuw nsw i32 %i, 3
%tmp2 = add nuw nsw i32 %i, 2
%tmp3 = add nuw nsw i32 %i, 1
- %tmp4 = getelementptr inbounds i8, i8* %arg, i64 12
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i64 12
%tmp5 = zext i32 %i to i64
- %tmp6 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp5
- %tmp7 = load i8, i8* %tmp6, align 4
+ %tmp6 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp5
+ %tmp7 = load i8, ptr %tmp6, align 4
%tmp8 = zext i8 %tmp7 to i32
%tmp9 = zext i32 %tmp3 to i64
- %tmp10 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp9
- %tmp11 = load i8, i8* %tmp10, align 1
+ %tmp10 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp9
+ %tmp11 = load i8, ptr %tmp10, align 1
%tmp12 = zext i8 %tmp11 to i32
%tmp13 = shl nuw nsw i32 %tmp12, 8
%tmp14 = or i32 %tmp13, %tmp8
%tmp15 = zext i32 %tmp2 to i64
- %tmp16 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp15
- %tmp17 = load i8, i8* %tmp16, align 1
+ %tmp16 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp15
+ %tmp17 = load i8, ptr %tmp16, align 1
%tmp18 = zext i8 %tmp17 to i32
%tmp19 = shl nuw nsw i32 %tmp18, 16
%tmp20 = or i32 %tmp14, %tmp19
%tmp21 = zext i32 %tmp to i64
- %tmp22 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp21
- %tmp23 = load i8, i8* %tmp22, align 1
+ %tmp22 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp21
+ %tmp23 = load i8, ptr %tmp22, align 1
%tmp24 = zext i8 %tmp23 to i32
%tmp25 = shl nuw i32 %tmp24, 24
%tmp26 = or i32 %tmp20, %tmp25
ret i32 %tmp26
}
-; i8* arg; i32 i;
+; ptr arg; i32 i;
; p = arg + 12;
; (i32) p[i + 1] | ((i32) p[i + 2] << 8) | ((i32) p[i + 3] << 16) | ((i32) p[i + 4] << 24)
-define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
+define i32 @load_i32_by_i8_base_offset_index_2(ptr %arg, i32 %i) {
; CHECK-LABEL: load_i32_by_i8_base_offset_index_2:
; CHECK: @ %bb.0:
; CHECK-NEXT: add r0, r1, r0
@@ -784,36 +769,36 @@ define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
%tmp = add nuw nsw i32 %i, 4
%tmp2 = add nuw nsw i32 %i, 3
%tmp3 = add nuw nsw i32 %i, 2
- %tmp4 = getelementptr inbounds i8, i8* %arg, i64 12
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i64 12
%tmp5 = add nuw nsw i32 %i, 1
%tmp27 = zext i32 %tmp5 to i64
- %tmp28 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp27
- %tmp29 = load i8, i8* %tmp28, align 4
+ %tmp28 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp27
+ %tmp29 = load i8, ptr %tmp28, align 4
%tmp30 = zext i8 %tmp29 to i32
%tmp31 = zext i32 %tmp3 to i64
- %tmp32 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp31
- %tmp33 = load i8, i8* %tmp32, align 1
+ %tmp32 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp31
+ %tmp33 = load i8, ptr %tmp32, align 1
%tmp34 = zext i8 %tmp33 to i32
%tmp35 = shl nuw nsw i32 %tmp34, 8
%tmp36 = or i32 %tmp35, %tmp30
%tmp37 = zext i32 %tmp2 to i64
- %tmp38 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp37
- %tmp39 = load i8, i8* %tmp38, align 1
+ %tmp38 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp37
+ %tmp39 = load i8, ptr %tmp38, align 1
%tmp40 = zext i8 %tmp39 to i32
%tmp41 = shl nuw nsw i32 %tmp40, 16
%tmp42 = or i32 %tmp36, %tmp41
%tmp43 = zext i32 %tmp to i64
- %tmp44 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp43
- %tmp45 = load i8, i8* %tmp44, align 1
+ %tmp44 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp43
+ %tmp45 = load i8, ptr %tmp44, align 1
%tmp46 = zext i8 %tmp45 to i32
%tmp47 = shl nuw i32 %tmp46, 24
%tmp48 = or i32 %tmp42, %tmp47
ret i32 %tmp48
}
-; i8* p; // p is 2 byte aligned
+; ptr p; // p is 2 byte aligned
; (i32) p[0] | ((i32) p[1] << 8)
-define i32 @zext_load_i32_by_i8(i32* %arg) {
+define i32 @zext_load_i32_by_i8(ptr %arg) {
; CHECK-LABEL: zext_load_i32_by_i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrb r1, [r0]
@@ -839,21 +824,19 @@ define i32 @zext_load_i32_by_i8(i32* %arg) {
; CHECK-THUMBv7-NEXT: rev16 r0, r0
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
- %tmp2 = load i8, i8* %tmp1, align 2
+ %tmp2 = load i8, ptr %arg, align 2
%tmp3 = zext i8 %tmp2 to i32
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 8
%tmp8 = or i32 %tmp7, %tmp3
ret i32 %tmp8
}
-; i8* p; // p is 2 byte aligned
+; ptr p; // p is 2 byte aligned
; ((i32) p[0] << 8) | ((i32) p[1] << 16)
-define i32 @zext_load_i32_by_i8_shl_8(i32* %arg) {
+define i32 @zext_load_i32_by_i8_shl_8(ptr %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_shl_8:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrb r1, [r0]
@@ -888,22 +871,20 @@ define i32 @zext_load_i32_by_i8_shl_8(i32* %arg) {
; CHECK-THUMBv7-NEXT: adds r0, r0, r1
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
- %tmp2 = load i8, i8* %tmp1, align 2
+ %tmp2 = load i8, ptr %arg, align 2
%tmp3 = zext i8 %tmp2 to i32
%tmp30 = shl nuw nsw i32 %tmp3, 8
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 16
%tmp8 = or i32 %tmp7, %tmp30
ret i32 %tmp8
}
-; i8* p; // p is 2 byte aligned
+; ptr p; // p is 2 byte aligned
; ((i32) p[0] << 16) | ((i32) p[1] << 24)
-define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
+define i32 @zext_load_i32_by_i8_shl_16(ptr %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_shl_16:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrb r1, [r0]
@@ -938,22 +919,20 @@ define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
; CHECK-THUMBv7-NEXT: adds r0, r0, r1
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
- %tmp2 = load i8, i8* %tmp1, align 2
+ %tmp2 = load i8, ptr %arg, align 2
%tmp3 = zext i8 %tmp2 to i32
%tmp30 = shl nuw nsw i32 %tmp3, 16
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 24
%tmp8 = or i32 %tmp7, %tmp30
ret i32 %tmp8
}
-; i8* p; // p is 2 byte aligned
+; ptr p; // p is 2 byte aligned
; (i32) p[1] | ((i32) p[0] << 8)
-define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
+define i32 @zext_load_i32_by_i8_bswap(ptr %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_bswap:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrh r0, [r0]
@@ -974,21 +953,19 @@ define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
; CHECK-THUMBv7-NEXT: ldrh r0, [r0]
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp2 = load i8, i8* %tmp1, align 1
+ %tmp1 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp2 = load i8, ptr %tmp1, align 1
%tmp3 = zext i8 %tmp2 to i32
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 0
- %tmp5 = load i8, i8* %tmp4, align 2
+ %tmp5 = load i8, ptr %arg, align 2
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 8
%tmp8 = or i32 %tmp7, %tmp3
ret i32 %tmp8
}
-; i8* p; // p is 2 byte aligned
+; ptr p; // p is 2 byte aligned
; ((i32) p[1] << 8) | ((i32) p[0] << 16)
-define i32 @zext_load_i32_by_i8_bswap_shl_8(i32* %arg) {
+define i32 @zext_load_i32_by_i8_bswap_shl_8(ptr %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_bswap_shl_8:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrb r1, [r0]
@@ -1023,22 +1000,20 @@ define i32 @zext_load_i32_by_i8_bswap_shl_8(i32* %arg) {
; CHECK-THUMBv7-NEXT: adds r0, r0, r1
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp2 = load i8, i8* %tmp1, align 1
+ %tmp1 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp2 = load i8, ptr %tmp1, align 1
%tmp3 = zext i8 %tmp2 to i32
%tmp30 = shl nuw nsw i32 %tmp3, 8
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 0
- %tmp5 = load i8, i8* %tmp4, align 2
+ %tmp5 = load i8, ptr %arg, align 2
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 16
%tmp8 = or i32 %tmp7, %tmp30
ret i32 %tmp8
}
-; i8* p; // p is 2 byte aligned
+; ptr p; // p is 2 byte aligned
; ((i32) p[1] << 16) | ((i32) p[0] << 24)
-define i32 @zext_load_i32_by_i8_bswap_shl_16(i32* %arg) {
+define i32 @zext_load_i32_by_i8_bswap_shl_16(ptr %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_bswap_shl_16:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrb r1, [r0]
@@ -1073,26 +1048,24 @@ define i32 @zext_load_i32_by_i8_bswap_shl_16(i32* %arg) {
; CHECK-THUMBv7-NEXT: adds r0, r0, r1
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp2 = load i8, i8* %tmp1, align 1
+ %tmp1 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp2 = load i8, ptr %tmp1, align 1
%tmp3 = zext i8 %tmp2 to i32
%tmp30 = shl nuw nsw i32 %tmp3, 16
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 0
- %tmp5 = load i8, i8* %tmp4, align 2
+ %tmp5 = load i8, ptr %arg, align 2
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 24
%tmp8 = or i32 %tmp7, %tmp30
ret i32 %tmp8
}
-; i8* p;
-; i16* p1.i16 = (i16*) p;
+; ptr p;
+; ptr p1.i16 = (ptr) p;
; (p1.i16[0] << 8) | ((i16) p[2])
;
; This is essentialy a i16 load from p[1], but we don't fold the pattern now
; because in the original DAG we don't have p[1] address available
-define i16 @load_i16_from_nonzero_offset(i8* %p) {
+define i16 @load_i16_from_nonzero_offset(ptr %p) {
; CHECK-LABEL: load_i16_from_nonzero_offset:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrh r1, [r0]
@@ -1123,10 +1096,9 @@ define i16 @load_i16_from_nonzero_offset(i8* %p) {
; CHECK-THUMBv7-NEXT: adds r0, r0, r1
; CHECK-THUMBv7-NEXT: bx lr
- %p1.i16 = bitcast i8* %p to i16*
- %p2.i8 = getelementptr i8, i8* %p, i64 2
- %v1 = load i16, i16* %p1.i16
- %v2.i8 = load i8, i8* %p2.i8
+ %p2.i8 = getelementptr i8, ptr %p, i64 2
+ %v1 = load i16, ptr %p
+ %v2.i8 = load i8, ptr %p2.i8
%v2 = zext i8 %v2.i8 to i16
%v1.shl = shl i16 %v1, 8
%res = or i16 %v1.shl, %v2
diff --git a/llvm/test/CodeGen/ARM/load-combine.ll b/llvm/test/CodeGen/ARM/load-combine.ll
index 1720f41895639..0f6ec8aa47386 100644
--- a/llvm/test/CodeGen/ARM/load-combine.ll
+++ b/llvm/test/CodeGen/ARM/load-combine.ll
@@ -4,9 +4,9 @@
; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-THUMBv6
; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-THUMBv7
-; i8* p; // p is 1 byte aligned
+; ptr p; // p is 1 byte aligned
; (i32) p[0] | ((i32) p[1] << 8) | ((i32) p[2] << 16) | ((i32) p[3] << 24)
-define i32 @load_i32_by_i8_unaligned(i32* %arg) {
+define i32 @load_i32_by_i8_unaligned(ptr %arg) {
; CHECK-LABEL: load_i32_by_i8_unaligned:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrb r2, [r0, #1]
@@ -48,31 +48,29 @@ define i32 @load_i32_by_i8_unaligned(i32* %arg) {
; CHECK-THUMBv7-NEXT: ldr r0, [r0]
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
- %tmp2 = load i8, i8* %tmp1, align 1
+ %tmp2 = load i8, ptr %arg, align 1
%tmp3 = zext i8 %tmp2 to i32
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 8
%tmp8 = or i32 %tmp7, %tmp3
- %tmp9 = getelementptr inbounds i8, i8* %tmp, i32 2
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i32 2
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i32
%tmp12 = shl nuw nsw i32 %tmp11, 16
%tmp13 = or i32 %tmp8, %tmp12
- %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 3
- %tmp15 = load i8, i8* %tmp14, align 1
+ %tmp14 = getelementptr inbounds i8, ptr %arg, i32 3
+ %tmp15 = load i8, ptr %tmp14, align 1
%tmp16 = zext i8 %tmp15 to i32
%tmp17 = shl nuw nsw i32 %tmp16, 24
%tmp18 = or i32 %tmp13, %tmp17
ret i32 %tmp18
}
-; i8* p; // p is 4 byte aligned
+; ptr p; // p is 4 byte aligned
; (i32) p[0] | ((i32) p[1] << 8) | ((i32) p[2] << 16) | ((i32) p[3] << 24)
-define i32 @load_i32_by_i8_aligned(i32* %arg) {
+define i32 @load_i32_by_i8_aligned(ptr %arg) {
; CHECK-LABEL: load_i32_by_i8_aligned:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0]
@@ -93,31 +91,29 @@ define i32 @load_i32_by_i8_aligned(i32* %arg) {
; CHECK-THUMBv7-NEXT: ldr r0, [r0]
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
- %tmp2 = load i8, i8* %tmp1, align 4
+ %tmp2 = load i8, ptr %arg, align 4
%tmp3 = zext i8 %tmp2 to i32
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 8
%tmp8 = or i32 %tmp7, %tmp3
- %tmp9 = getelementptr inbounds i8, i8* %tmp, i32 2
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i32 2
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i32
%tmp12 = shl nuw nsw i32 %tmp11, 16
%tmp13 = or i32 %tmp8, %tmp12
- %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 3
- %tmp15 = load i8, i8* %tmp14, align 1
+ %tmp14 = getelementptr inbounds i8, ptr %arg, i32 3
+ %tmp15 = load i8, ptr %tmp14, align 1
%tmp16 = zext i8 %tmp15 to i32
%tmp17 = shl nuw nsw i32 %tmp16, 24
%tmp18 = or i32 %tmp13, %tmp17
ret i32 %tmp18
}
-; i8* p; // p is 4 byte aligned
+; ptr p; // p is 4 byte aligned
; ((i32) p[0] << 24) | ((i32) p[1] << 16) | ((i32) p[2] << 8) | (i32) p[3]
-define i32 @load_i32_by_i8_bswap(i32* %arg) {
+define i32 @load_i32_by_i8_bswap(ptr %arg) {
; BSWAP is not supported by 32 bit target
; CHECK-LABEL: load_i32_by_i8_bswap:
; CHECK: @ %bb.0:
@@ -149,30 +145,29 @@ define i32 @load_i32_by_i8_bswap(i32* %arg) {
; CHECK-THUMBv7-NEXT: rev r0, r0
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = load i8, i8* %tmp, align 4
+ %tmp1 = load i8, ptr %arg, align 4
%tmp2 = zext i8 %tmp1 to i32
%tmp3 = shl nuw nsw i32 %tmp2, 24
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 16
%tmp8 = or i32 %tmp7, %tmp3
- %tmp9 = getelementptr inbounds i8, i8* %tmp, i32 2
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i32 2
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i32
%tmp12 = shl nuw nsw i32 %tmp11, 8
%tmp13 = or i32 %tmp8, %tmp12
- %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 3
- %tmp15 = load i8, i8* %tmp14, align 1
+ %tmp14 = getelementptr inbounds i8, ptr %arg, i32 3
+ %tmp15 = load i8, ptr %tmp14, align 1
%tmp16 = zext i8 %tmp15 to i32
%tmp17 = or i32 %tmp13, %tmp16
ret i32 %tmp17
}
-; i8* p; // p is 8 byte aligned
+; ptr p; // p is 8 byte aligned
; (i64) p[0] | ((i64) p[1] << 8) | ((i64) p[2] << 16) | ((i64) p[3] << 24) | ((i64) p[4] << 32) | ((i64) p[5] << 40) | ((i64) p[6] << 48) | ((i64) p[7] << 56)
-define i64 @load_i64_by_i8(i64* %arg) {
+define i64 @load_i64_by_i8(ptr %arg) {
; CHECK-LABEL: load_i64_by_i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r2, [r0]
@@ -197,50 +192,49 @@ define i64 @load_i64_by_i8(i64* %arg) {
; CHECK-THUMBv7-NEXT: ldrd r0, r1, [r0]
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i64* %arg to i8*
- %tmp1 = load i8, i8* %tmp, align 8
+ %tmp1 = load i8, ptr %arg, align 8
%tmp2 = zext i8 %tmp1 to i64
- %tmp3 = getelementptr inbounds i8, i8* %tmp, i64 1
- %tmp4 = load i8, i8* %tmp3, align 1
+ %tmp3 = getelementptr inbounds i8, ptr %arg, i64 1
+ %tmp4 = load i8, ptr %tmp3, align 1
%tmp5 = zext i8 %tmp4 to i64
%tmp6 = shl nuw nsw i64 %tmp5, 8
%tmp7 = or i64 %tmp6, %tmp2
- %tmp8 = getelementptr inbounds i8, i8* %tmp, i64 2
- %tmp9 = load i8, i8* %tmp8, align 1
+ %tmp8 = getelementptr inbounds i8, ptr %arg, i64 2
+ %tmp9 = load i8, ptr %tmp8, align 1
%tmp10 = zext i8 %tmp9 to i64
%tmp11 = shl nuw nsw i64 %tmp10, 16
%tmp12 = or i64 %tmp7, %tmp11
- %tmp13 = getelementptr inbounds i8, i8* %tmp, i64 3
- %tmp14 = load i8, i8* %tmp13, align 1
+ %tmp13 = getelementptr inbounds i8, ptr %arg, i64 3
+ %tmp14 = load i8, ptr %tmp13, align 1
%tmp15 = zext i8 %tmp14 to i64
%tmp16 = shl nuw nsw i64 %tmp15, 24
%tmp17 = or i64 %tmp12, %tmp16
- %tmp18 = getelementptr inbounds i8, i8* %tmp, i64 4
- %tmp19 = load i8, i8* %tmp18, align 1
+ %tmp18 = getelementptr inbounds i8, ptr %arg, i64 4
+ %tmp19 = load i8, ptr %tmp18, align 1
%tmp20 = zext i8 %tmp19 to i64
%tmp21 = shl nuw nsw i64 %tmp20, 32
%tmp22 = or i64 %tmp17, %tmp21
- %tmp23 = getelementptr inbounds i8, i8* %tmp, i64 5
- %tmp24 = load i8, i8* %tmp23, align 1
+ %tmp23 = getelementptr inbounds i8, ptr %arg, i64 5
+ %tmp24 = load i8, ptr %tmp23, align 1
%tmp25 = zext i8 %tmp24 to i64
%tmp26 = shl nuw nsw i64 %tmp25, 40
%tmp27 = or i64 %tmp22, %tmp26
- %tmp28 = getelementptr inbounds i8, i8* %tmp, i64 6
- %tmp29 = load i8, i8* %tmp28, align 1
+ %tmp28 = getelementptr inbounds i8, ptr %arg, i64 6
+ %tmp29 = load i8, ptr %tmp28, align 1
%tmp30 = zext i8 %tmp29 to i64
%tmp31 = shl nuw nsw i64 %tmp30, 48
%tmp32 = or i64 %tmp27, %tmp31
- %tmp33 = getelementptr inbounds i8, i8* %tmp, i64 7
- %tmp34 = load i8, i8* %tmp33, align 1
+ %tmp33 = getelementptr inbounds i8, ptr %arg, i64 7
+ %tmp34 = load i8, ptr %tmp33, align 1
%tmp35 = zext i8 %tmp34 to i64
%tmp36 = shl nuw i64 %tmp35, 56
%tmp37 = or i64 %tmp32, %tmp36
ret i64 %tmp37
}
-; i8* p; // p is 8 byte aligned
+; ptr p; // p is 8 byte aligned
; ((i64) p[0] << 56) | ((i64) p[1] << 48) | ((i64) p[2] << 40) | ((i64) p[3] << 32) | ((i64) p[4] << 24) | ((i64) p[5] << 16) | ((i64) p[6] << 8) | (i64) p[7]
-define i64 @load_i64_by_i8_bswap(i64* %arg) {
+define i64 @load_i64_by_i8_bswap(ptr %arg) {
; CHECK-LABEL: load_i64_by_i8_bswap:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r1, [r0]
@@ -282,50 +276,49 @@ define i64 @load_i64_by_i8_bswap(i64* %arg) {
; CHECK-THUMBv7-NEXT: rev r1, r1
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i64* %arg to i8*
- %tmp1 = load i8, i8* %tmp, align 8
+ %tmp1 = load i8, ptr %arg, align 8
%tmp2 = zext i8 %tmp1 to i64
%tmp3 = shl nuw i64 %tmp2, 56
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i64 1
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i64 1
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i64
%tmp7 = shl nuw nsw i64 %tmp6, 48
%tmp8 = or i64 %tmp7, %tmp3
- %tmp9 = getelementptr inbounds i8, i8* %tmp, i64 2
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i64 2
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i64
%tmp12 = shl nuw nsw i64 %tmp11, 40
%tmp13 = or i64 %tmp8, %tmp12
- %tmp14 = getelementptr inbounds i8, i8* %tmp, i64 3
- %tmp15 = load i8, i8* %tmp14, align 1
+ %tmp14 = getelementptr inbounds i8, ptr %arg, i64 3
+ %tmp15 = load i8, ptr %tmp14, align 1
%tmp16 = zext i8 %tmp15 to i64
%tmp17 = shl nuw nsw i64 %tmp16, 32
%tmp18 = or i64 %tmp13, %tmp17
- %tmp19 = getelementptr inbounds i8, i8* %tmp, i64 4
- %tmp20 = load i8, i8* %tmp19, align 1
+ %tmp19 = getelementptr inbounds i8, ptr %arg, i64 4
+ %tmp20 = load i8, ptr %tmp19, align 1
%tmp21 = zext i8 %tmp20 to i64
%tmp22 = shl nuw nsw i64 %tmp21, 24
%tmp23 = or i64 %tmp18, %tmp22
- %tmp24 = getelementptr inbounds i8, i8* %tmp, i64 5
- %tmp25 = load i8, i8* %tmp24, align 1
+ %tmp24 = getelementptr inbounds i8, ptr %arg, i64 5
+ %tmp25 = load i8, ptr %tmp24, align 1
%tmp26 = zext i8 %tmp25 to i64
%tmp27 = shl nuw nsw i64 %tmp26, 16
%tmp28 = or i64 %tmp23, %tmp27
- %tmp29 = getelementptr inbounds i8, i8* %tmp, i64 6
- %tmp30 = load i8, i8* %tmp29, align 1
+ %tmp29 = getelementptr inbounds i8, ptr %arg, i64 6
+ %tmp30 = load i8, ptr %tmp29, align 1
%tmp31 = zext i8 %tmp30 to i64
%tmp32 = shl nuw nsw i64 %tmp31, 8
%tmp33 = or i64 %tmp28, %tmp32
- %tmp34 = getelementptr inbounds i8, i8* %tmp, i64 7
- %tmp35 = load i8, i8* %tmp34, align 1
+ %tmp34 = getelementptr inbounds i8, ptr %arg, i64 7
+ %tmp35 = load i8, ptr %tmp34, align 1
%tmp36 = zext i8 %tmp35 to i64
%tmp37 = or i64 %tmp33, %tmp36
ret i64 %tmp37
}
-; i8* p; // p[1] is 4 byte aligned
+; ptr p; // p[1] is 4 byte aligned
; (i32) p[1] | ((i32) p[2] << 8) | ((i32) p[3] << 16) | ((i32) p[4] << 24)
-define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
+define i32 @load_i32_by_i8_nonzero_offset(ptr %arg) {
; CHECK-LABEL: load_i32_by_i8_nonzero_offset:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0, #1]
@@ -348,31 +341,30 @@ define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp2 = load i8, i8* %tmp1, align 4
+ %tmp1 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp2 = load i8, ptr %tmp1, align 4
%tmp3 = zext i8 %tmp2 to i32
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 2
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 2
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 8
%tmp8 = or i32 %tmp7, %tmp3
- %tmp9 = getelementptr inbounds i8, i8* %tmp, i32 3
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i32 3
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i32
%tmp12 = shl nuw nsw i32 %tmp11, 16
%tmp13 = or i32 %tmp8, %tmp12
- %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 4
- %tmp15 = load i8, i8* %tmp14, align 1
+ %tmp14 = getelementptr inbounds i8, ptr %arg, i32 4
+ %tmp15 = load i8, ptr %tmp14, align 1
%tmp16 = zext i8 %tmp15 to i32
%tmp17 = shl nuw nsw i32 %tmp16, 24
%tmp18 = or i32 %tmp13, %tmp17
ret i32 %tmp18
}
-; i8* p; // p[-4] is 4 byte aligned
+; ptr p; // p[-4] is 4 byte aligned
; (i32) p[-4] | ((i32) p[-3] << 8) | ((i32) p[-2] << 16) | ((i32) p[-1] << 24)
-define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
+define i32 @load_i32_by_i8_neg_offset(ptr %arg) {
; CHECK-LABEL: load_i32_by_i8_neg_offset:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0, #-4]
@@ -395,31 +387,30 @@ define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 -4
- %tmp2 = load i8, i8* %tmp1, align 4
+ %tmp1 = getelementptr inbounds i8, ptr %arg, i32 -4
+ %tmp2 = load i8, ptr %tmp1, align 4
%tmp3 = zext i8 %tmp2 to i32
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 -3
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 -3
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 8
%tmp8 = or i32 %tmp7, %tmp3
- %tmp9 = getelementptr inbounds i8, i8* %tmp, i32 -2
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i32 -2
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i32
%tmp12 = shl nuw nsw i32 %tmp11, 16
%tmp13 = or i32 %tmp8, %tmp12
- %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 -1
- %tmp15 = load i8, i8* %tmp14, align 1
+ %tmp14 = getelementptr inbounds i8, ptr %arg, i32 -1
+ %tmp15 = load i8, ptr %tmp14, align 1
%tmp16 = zext i8 %tmp15 to i32
%tmp17 = shl nuw nsw i32 %tmp16, 24
%tmp18 = or i32 %tmp13, %tmp17
ret i32 %tmp18
}
-; i8* p; // p[1] is 4 byte aligned
+; ptr p; // p[1] is 4 byte aligned
; (i32) p[4] | ((i32) p[3] << 8) | ((i32) p[2] << 16) | ((i32) p[1] << 24)
-define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
+define i32 @load_i32_by_i8_nonzero_offset_bswap(ptr %arg) {
; CHECK-LABEL: load_i32_by_i8_nonzero_offset_bswap:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0, #1]
@@ -452,31 +443,30 @@ define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 4
- %tmp2 = load i8, i8* %tmp1, align 1
+ %tmp1 = getelementptr inbounds i8, ptr %arg, i32 4
+ %tmp2 = load i8, ptr %tmp1, align 1
%tmp3 = zext i8 %tmp2 to i32
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 3
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 3
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 8
%tmp8 = or i32 %tmp7, %tmp3
- %tmp9 = getelementptr inbounds i8, i8* %tmp, i32 2
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i32 2
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i32
%tmp12 = shl nuw nsw i32 %tmp11, 16
%tmp13 = or i32 %tmp8, %tmp12
- %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp15 = load i8, i8* %tmp14, align 4
+ %tmp14 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp15 = load i8, ptr %tmp14, align 4
%tmp16 = zext i8 %tmp15 to i32
%tmp17 = shl nuw nsw i32 %tmp16, 24
%tmp18 = or i32 %tmp13, %tmp17
ret i32 %tmp18
}
-; i8* p; // p[-4] is 4 byte aligned
+; ptr p; // p[-4] is 4 byte aligned
; (i32) p[-1] | ((i32) p[-2] << 8) | ((i32) p[-3] << 16) | ((i32) p[-4] << 24)
-define i32 @load_i32_by_i8_neg_offset_bswap(i32* %arg) {
+define i32 @load_i32_by_i8_neg_offset_bswap(ptr %arg) {
; CHECK-LABEL: load_i32_by_i8_neg_offset_bswap:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0, #-4]
@@ -509,22 +499,21 @@ define i32 @load_i32_by_i8_neg_offset_bswap(i32* %arg) {
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 -1
- %tmp2 = load i8, i8* %tmp1, align 1
+ %tmp1 = getelementptr inbounds i8, ptr %arg, i32 -1
+ %tmp2 = load i8, ptr %tmp1, align 1
%tmp3 = zext i8 %tmp2 to i32
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 -2
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 -2
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 8
%tmp8 = or i32 %tmp7, %tmp3
- %tmp9 = getelementptr inbounds i8, i8* %tmp, i32 -3
- %tmp10 = load i8, i8* %tmp9, align 1
+ %tmp9 = getelementptr inbounds i8, ptr %arg, i32 -3
+ %tmp10 = load i8, ptr %tmp9, align 1
%tmp11 = zext i8 %tmp10 to i32
%tmp12 = shl nuw nsw i32 %tmp11, 16
%tmp13 = or i32 %tmp8, %tmp12
- %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 -4
- %tmp15 = load i8, i8* %tmp14, align 4
+ %tmp14 = getelementptr inbounds i8, ptr %arg, i32 -4
+ %tmp15 = load i8, ptr %tmp14, align 4
%tmp16 = zext i8 %tmp15 to i32
%tmp17 = shl nuw nsw i32 %tmp16, 24
%tmp18 = or i32 %tmp13, %tmp17
@@ -533,9 +522,9 @@ define i32 @load_i32_by_i8_neg_offset_bswap(i32* %arg) {
declare i16 @llvm.bswap.i16(i16)
-; i16* p; // p is 4 byte aligned
+; ptr p; // p is 4 byte aligned
; (i32) bswap(p[1]) | (i32) bswap(p[0] << 16)
-define i32 @load_i32_by_bswap_i16(i32* %arg) {
+define i32 @load_i32_by_bswap_i16(ptr %arg) {
; CHECK-LABEL: load_i32_by_bswap_i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0]
@@ -567,12 +556,11 @@ define i32 @load_i32_by_bswap_i16(i32* %arg) {
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i16*
- %tmp1 = load i16, i16* %tmp, align 4
+ %tmp1 = load i16, ptr %arg, align 4
%tmp11 = call i16 @llvm.bswap.i16(i16 %tmp1)
%tmp2 = zext i16 %tmp11 to i32
- %tmp3 = getelementptr inbounds i16, i16* %tmp, i32 1
- %tmp4 = load i16, i16* %tmp3, align 1
+ %tmp3 = getelementptr inbounds i16, ptr %arg, i32 1
+ %tmp4 = load i16, ptr %tmp3, align 1
%tmp41 = call i16 @llvm.bswap.i16(i16 %tmp4)
%tmp5 = zext i16 %tmp41 to i32
%tmp6 = shl nuw nsw i32 %tmp2, 16
@@ -580,9 +568,9 @@ define i32 @load_i32_by_bswap_i16(i32* %arg) {
ret i32 %tmp7
}
-; i16* p;
+; ptr p;
; (i32) p[0] | (sext(p[1] << 16) to i32)
-define i32 @load_i32_by_sext_i16(i32* %arg) {
+define i32 @load_i32_by_sext_i16(ptr %arg) {
; CHECK-LABEL: load_i32_by_sext_i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0]
@@ -602,21 +590,20 @@ define i32 @load_i32_by_sext_i16(i32* %arg) {
; CHECK-THUMBv7: @ %bb.0:
; CHECK-THUMBv7-NEXT: ldr r0, [r0]
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i16*
- %tmp1 = load i16, i16* %tmp, align 4
+ %tmp1 = load i16, ptr %arg, align 4
%tmp2 = zext i16 %tmp1 to i32
- %tmp3 = getelementptr inbounds i16, i16* %tmp, i32 1
- %tmp4 = load i16, i16* %tmp3, align 1
+ %tmp3 = getelementptr inbounds i16, ptr %arg, i32 1
+ %tmp4 = load i16, ptr %tmp3, align 1
%tmp5 = sext i16 %tmp4 to i32
%tmp6 = shl nuw nsw i32 %tmp5, 16
%tmp7 = or i32 %tmp6, %tmp2
ret i32 %tmp7
}
-; i8* arg; i32 i;
+; ptr arg; i32 i;
; p = arg + 12;
; (i32) p[i] | ((i32) p[i + 1] << 8) | ((i32) p[i + 2] << 16) | ((i32) p[i + 3] << 24)
-define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
+define i32 @load_i32_by_i8_base_offset_index(ptr %arg, i32 %i) {
; CHECK-LABEL: load_i32_by_i8_base_offset_index:
; CHECK: @ %bb.0:
; CHECK-NEXT: add r0, r0, r1
@@ -644,36 +631,36 @@ define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
%tmp = add nuw nsw i32 %i, 3
%tmp2 = add nuw nsw i32 %i, 2
%tmp3 = add nuw nsw i32 %i, 1
- %tmp4 = getelementptr inbounds i8, i8* %arg, i64 12
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i64 12
%tmp5 = zext i32 %i to i64
- %tmp6 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp5
- %tmp7 = load i8, i8* %tmp6, align 4
+ %tmp6 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp5
+ %tmp7 = load i8, ptr %tmp6, align 4
%tmp8 = zext i8 %tmp7 to i32
%tmp9 = zext i32 %tmp3 to i64
- %tmp10 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp9
- %tmp11 = load i8, i8* %tmp10, align 1
+ %tmp10 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp9
+ %tmp11 = load i8, ptr %tmp10, align 1
%tmp12 = zext i8 %tmp11 to i32
%tmp13 = shl nuw nsw i32 %tmp12, 8
%tmp14 = or i32 %tmp13, %tmp8
%tmp15 = zext i32 %tmp2 to i64
- %tmp16 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp15
- %tmp17 = load i8, i8* %tmp16, align 1
+ %tmp16 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp15
+ %tmp17 = load i8, ptr %tmp16, align 1
%tmp18 = zext i8 %tmp17 to i32
%tmp19 = shl nuw nsw i32 %tmp18, 16
%tmp20 = or i32 %tmp14, %tmp19
%tmp21 = zext i32 %tmp to i64
- %tmp22 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp21
- %tmp23 = load i8, i8* %tmp22, align 1
+ %tmp22 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp21
+ %tmp23 = load i8, ptr %tmp22, align 1
%tmp24 = zext i8 %tmp23 to i32
%tmp25 = shl nuw i32 %tmp24, 24
%tmp26 = or i32 %tmp20, %tmp25
ret i32 %tmp26
}
-; i8* arg; i32 i;
+; ptr arg; i32 i;
; p = arg + 12;
; (i32) p[i + 1] | ((i32) p[i + 2] << 8) | ((i32) p[i + 3] << 16) | ((i32) p[i + 4] << 24)
-define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
+define i32 @load_i32_by_i8_base_offset_index_2(ptr %arg, i32 %i) {
; CHECK-LABEL: load_i32_by_i8_base_offset_index_2:
; CHECK: @ %bb.0:
; CHECK-NEXT: add r0, r1, r0
@@ -701,36 +688,36 @@ define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
%tmp = add nuw nsw i32 %i, 4
%tmp2 = add nuw nsw i32 %i, 3
%tmp3 = add nuw nsw i32 %i, 2
- %tmp4 = getelementptr inbounds i8, i8* %arg, i64 12
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i64 12
%tmp5 = add nuw nsw i32 %i, 1
%tmp27 = zext i32 %tmp5 to i64
- %tmp28 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp27
- %tmp29 = load i8, i8* %tmp28, align 4
+ %tmp28 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp27
+ %tmp29 = load i8, ptr %tmp28, align 4
%tmp30 = zext i8 %tmp29 to i32
%tmp31 = zext i32 %tmp3 to i64
- %tmp32 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp31
- %tmp33 = load i8, i8* %tmp32, align 1
+ %tmp32 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp31
+ %tmp33 = load i8, ptr %tmp32, align 1
%tmp34 = zext i8 %tmp33 to i32
%tmp35 = shl nuw nsw i32 %tmp34, 8
%tmp36 = or i32 %tmp35, %tmp30
%tmp37 = zext i32 %tmp2 to i64
- %tmp38 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp37
- %tmp39 = load i8, i8* %tmp38, align 1
+ %tmp38 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp37
+ %tmp39 = load i8, ptr %tmp38, align 1
%tmp40 = zext i8 %tmp39 to i32
%tmp41 = shl nuw nsw i32 %tmp40, 16
%tmp42 = or i32 %tmp36, %tmp41
%tmp43 = zext i32 %tmp to i64
- %tmp44 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp43
- %tmp45 = load i8, i8* %tmp44, align 1
+ %tmp44 = getelementptr inbounds i8, ptr %tmp4, i64 %tmp43
+ %tmp45 = load i8, ptr %tmp44, align 1
%tmp46 = zext i8 %tmp45 to i32
%tmp47 = shl nuw i32 %tmp46, 24
%tmp48 = or i32 %tmp42, %tmp47
ret i32 %tmp48
}
-; i8* p; // p is 2 byte aligned
+; ptr p; // p is 2 byte aligned
; (i32) p[0] | ((i32) p[1] << 8)
-define i32 @zext_load_i32_by_i8(i32* %arg) {
+define i32 @zext_load_i32_by_i8(ptr %arg) {
; CHECK-LABEL: zext_load_i32_by_i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrh r0, [r0]
@@ -751,21 +738,19 @@ define i32 @zext_load_i32_by_i8(i32* %arg) {
; CHECK-THUMBv7-NEXT: ldrh r0, [r0]
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
- %tmp2 = load i8, i8* %tmp1, align 2
+ %tmp2 = load i8, ptr %arg, align 2
%tmp3 = zext i8 %tmp2 to i32
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 8
%tmp8 = or i32 %tmp7, %tmp3
ret i32 %tmp8
}
-; i8* p; // p is 2 byte aligned
+; ptr p; // p is 2 byte aligned
; ((i32) p[0] << 8) | ((i32) p[1] << 16)
-define i32 @zext_load_i32_by_i8_shl_8(i32* %arg) {
+define i32 @zext_load_i32_by_i8_shl_8(ptr %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_shl_8:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrb r1, [r0]
@@ -799,22 +784,20 @@ define i32 @zext_load_i32_by_i8_shl_8(i32* %arg) {
; CHECK-THUMBv7-NEXT: orr.w r0, r0, r1, lsl #8
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
- %tmp2 = load i8, i8* %tmp1, align 2
+ %tmp2 = load i8, ptr %arg, align 2
%tmp3 = zext i8 %tmp2 to i32
%tmp30 = shl nuw nsw i32 %tmp3, 8
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 16
%tmp8 = or i32 %tmp7, %tmp30
ret i32 %tmp8
}
-; i8* p; // p is 2 byte aligned
+; ptr p; // p is 2 byte aligned
; ((i32) p[0] << 16) | ((i32) p[1] << 24)
-define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
+define i32 @zext_load_i32_by_i8_shl_16(ptr %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_shl_16:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrb r1, [r0]
@@ -848,22 +831,20 @@ define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
; CHECK-THUMBv7-NEXT: orr.w r0, r0, r1, lsl #16
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
- %tmp2 = load i8, i8* %tmp1, align 2
+ %tmp2 = load i8, ptr %arg, align 2
%tmp3 = zext i8 %tmp2 to i32
%tmp30 = shl nuw nsw i32 %tmp3, 16
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp5 = load i8, i8* %tmp4, align 1
+ %tmp4 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp5 = load i8, ptr %tmp4, align 1
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 24
%tmp8 = or i32 %tmp7, %tmp30
ret i32 %tmp8
}
-; i8* p; // p is 2 byte aligned
+; ptr p; // p is 2 byte aligned
; (i32) p[1] | ((i32) p[0] << 8)
-define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
+define i32 @zext_load_i32_by_i8_bswap(ptr %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_bswap:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrb r1, [r0]
@@ -889,21 +870,19 @@ define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
; CHECK-THUMBv7-NEXT: rev16 r0, r0
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp2 = load i8, i8* %tmp1, align 1
+ %tmp1 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp2 = load i8, ptr %tmp1, align 1
%tmp3 = zext i8 %tmp2 to i32
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 0
- %tmp5 = load i8, i8* %tmp4, align 2
+ %tmp5 = load i8, ptr %arg, align 2
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 8
%tmp8 = or i32 %tmp7, %tmp3
ret i32 %tmp8
}
-; i8* p; // p is 2 byte aligned
+; ptr p; // p is 2 byte aligned
; ((i32) p[1] << 8) | ((i32) p[0] << 16)
-define i32 @zext_load_i32_by_i8_bswap_shl_8(i32* %arg) {
+define i32 @zext_load_i32_by_i8_bswap_shl_8(ptr %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_bswap_shl_8:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrb r1, [r0]
@@ -937,22 +916,20 @@ define i32 @zext_load_i32_by_i8_bswap_shl_8(i32* %arg) {
; CHECK-THUMBv7-NEXT: orr.w r0, r1, r0, lsl #8
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp2 = load i8, i8* %tmp1, align 1
+ %tmp1 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp2 = load i8, ptr %tmp1, align 1
%tmp3 = zext i8 %tmp2 to i32
%tmp30 = shl nuw nsw i32 %tmp3, 8
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 0
- %tmp5 = load i8, i8* %tmp4, align 2
+ %tmp5 = load i8, ptr %arg, align 2
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 16
%tmp8 = or i32 %tmp7, %tmp30
ret i32 %tmp8
}
-; i8* p; // p is 2 byte aligned
+; ptr p; // p is 2 byte aligned
; ((i32) p[1] << 16) | ((i32) p[0] << 24)
-define i32 @zext_load_i32_by_i8_bswap_shl_16(i32* %arg) {
+define i32 @zext_load_i32_by_i8_bswap_shl_16(ptr %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_bswap_shl_16:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldrb r1, [r0]
@@ -986,13 +963,11 @@ define i32 @zext_load_i32_by_i8_bswap_shl_16(i32* %arg) {
; CHECK-THUMBv7-NEXT: orr.w r0, r1, r0, lsl #16
; CHECK-THUMBv7-NEXT: bx lr
- %tmp = bitcast i32* %arg to i8*
- %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
- %tmp2 = load i8, i8* %tmp1, align 1
+ %tmp1 = getelementptr inbounds i8, ptr %arg, i32 1
+ %tmp2 = load i8, ptr %tmp1, align 1
%tmp3 = zext i8 %tmp2 to i32
%tmp30 = shl nuw nsw i32 %tmp3, 16
- %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 0
- %tmp5 = load i8, i8* %tmp4, align 2
+ %tmp5 = load i8, ptr %arg, align 2
%tmp6 = zext i8 %tmp5 to i32
%tmp7 = shl nuw nsw i32 %tmp6, 24
%tmp8 = or i32 %tmp7, %tmp30
diff --git a/llvm/test/CodeGen/ARM/load-global.ll b/llvm/test/CodeGen/ARM/load-global.ll
index eade2fda37054..0d370a495d2f5 100644
--- a/llvm/test/CodeGen/ARM/load-global.ll
+++ b/llvm/test/CodeGen/ARM/load-global.ll
@@ -49,6 +49,6 @@ define i32 @test1() {
; LINUX_T: add r0, pc
; LINUX_T: ldr r0, [r0]
; LINUX_T: ldr r0, [r0]
- %tmp = load i32, i32* @G
+ %tmp = load i32, ptr @G
ret i32 %tmp
}
diff --git a/llvm/test/CodeGen/ARM/load-global2.ll b/llvm/test/CodeGen/ARM/load-global2.ll
index 2b1a66ea03035..08a8f4280d3b8 100644
--- a/llvm/test/CodeGen/ARM/load-global2.ll
+++ b/llvm/test/CodeGen/ARM/load-global2.ll
@@ -30,14 +30,14 @@ define signext i8 @foo() {
; LINUX-PIC-NEXT: .Ltmp0:
; LINUX-PIC-NEXT: .long x(GOT_PREL)-((.LPC0_0+8)-.Ltmp0)
entry:
- %0 = load i8, i8* @x
+ %0 = load i8, ptr @x
%tobool = icmp eq i8 %0, 0
br i1 %tobool, label %bb1, label %bb2
bb1:
call void @bar()
; No more pc-relative loads! Reuse r[[B]].
- %1 = load i8, i8* @x
+ %1 = load i8, ptr @x
ret i8 %1
bb2:
diff --git a/llvm/test/CodeGen/ARM/load-store-flags.ll b/llvm/test/CodeGen/ARM/load-store-flags.ll
index 95d9b484a0a76..bf82b80fa6dfe 100644
--- a/llvm/test/CodeGen/ARM/load-store-flags.ll
+++ b/llvm/test/CodeGen/ARM/load-store-flags.ll
@@ -3,20 +3,20 @@
; The base register for the store is killed by the last instruction, but is
; actually also used during as part of the store itself. If an extra ADD is
; inserted, it should not kill the base.
-define void @test_base_kill(i32 %v0, i32 %v1, i32* %addr) {
+define void @test_base_kill(i32 %v0, i32 %v1, ptr %addr) {
; CHECK-LABEL: test_base_kill:
; CHECK: adds [[NEWBASE:r[0-9]+]], r2, #4
; CHECK: stm [[NEWBASE]]!, {r0, r1, r2}
- %addr.1 = getelementptr i32, i32* %addr, i32 1
- store i32 %v0, i32* %addr.1
+ %addr.1 = getelementptr i32, ptr %addr, i32 1
+ store i32 %v0, ptr %addr.1
- %addr.2 = getelementptr i32, i32* %addr, i32 2
- store i32 %v1, i32* %addr.2
+ %addr.2 = getelementptr i32, ptr %addr, i32 2
+ store i32 %v1, ptr %addr.2
- %addr.3 = getelementptr i32, i32* %addr, i32 3
- %val = ptrtoint i32* %addr to i32
- store i32 %val, i32* %addr.3
+ %addr.3 = getelementptr i32, ptr %addr, i32 3
+ %val = ptrtoint ptr %addr to i32
+ store i32 %val, ptr %addr.3
ret void
}
@@ -24,20 +24,20 @@ define void @test_base_kill(i32 %v0, i32 %v1, i32* %addr) {
; Similar, but it's not sufficient to look at just the last instruction (where
; liveness of the base is determined). An intervening instruction might be moved
; past it to form the STM.
-define void @test_base_kill_mid(i32 %v0, i32* %addr, i32 %v1) {
+define void @test_base_kill_mid(i32 %v0, ptr %addr, i32 %v1) {
; CHECK-LABEL: test_base_kill_mid:
; CHECK: adds [[NEWBASE:r[0-9]+]], r1, #4
; CHECK: stm [[NEWBASE]]!, {r0, r1, r2}
- %addr.1 = getelementptr i32, i32* %addr, i32 1
- store i32 %v0, i32* %addr.1
+ %addr.1 = getelementptr i32, ptr %addr, i32 1
+ store i32 %v0, ptr %addr.1
- %addr.2 = getelementptr i32, i32* %addr, i32 2
- %val = ptrtoint i32* %addr to i32
- store i32 %val, i32* %addr.2
+ %addr.2 = getelementptr i32, ptr %addr, i32 2
+ %val = ptrtoint ptr %addr to i32
+ store i32 %val, ptr %addr.2
- %addr.3 = getelementptr i32, i32* %addr, i32 3
- store i32 %v1, i32* %addr.3
+ %addr.3 = getelementptr i32, ptr %addr, i32 3
+ store i32 %v1, ptr %addr.3
ret void
}
diff --git a/llvm/test/CodeGen/ARM/load.ll b/llvm/test/CodeGen/ARM/load.ll
index d23d2693ec011..d87a1e49fafe4 100644
--- a/llvm/test/CodeGen/ARM/load.ll
+++ b/llvm/test/CodeGen/ARM/load.ll
@@ -6,10 +6,10 @@
; CHECK-LABEL: ldrsb_rr
; CHECK: ldrsb r0, [r0, r1]
-define i32 @ldrsb_rr(i8* %p, i32 %n) {
+define i32 @ldrsb_rr(ptr %p, i32 %n) {
entry:
- %arrayidx = getelementptr inbounds i8, i8* %p, i32 %n
- %0 = load i8, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds i8, ptr %p, i32 %n
+ %0 = load i8, ptr %arrayidx, align 1
%conv = sext i8 %0 to i32
ret i32 %conv
}
@@ -18,20 +18,20 @@ entry:
; CHECK-T1: lsls r1, r1, #1
; CHECK-T1: ldrsh r0, [r0, r1]
; CHECK-T2: ldrsh.w r0, [r0, r1, lsl #1]
-define i32 @ldrsh_rr(i16* %p, i32 %n) {
+define i32 @ldrsh_rr(ptr %p, i32 %n) {
entry:
- %arrayidx = getelementptr inbounds i16, i16* %p, i32 %n
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %p, i32 %n
+ %0 = load i16, ptr %arrayidx, align 2
%conv = sext i16 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: ldrb_rr
; CHECK: ldrb r0, [r0, r1]
-define i32 @ldrb_rr(i8* %p, i32 %n) {
+define i32 @ldrb_rr(ptr %p, i32 %n) {
entry:
- %arrayidx = getelementptr inbounds i8, i8* %p, i32 %n
- %0 = load i8, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds i8, ptr %p, i32 %n
+ %0 = load i8, ptr %arrayidx, align 1
%conv = zext i8 %0 to i32
ret i32 %conv
}
@@ -40,10 +40,10 @@ entry:
; CHECK-T1: lsls r1, r1, #1
; CHECK-T1: ldrh r0, [r0, r1]
; CHECK-T2: ldrh.w r0, [r0, r1, lsl #1]
-define i32 @ldrh_rr(i16* %p, i32 %n) {
+define i32 @ldrh_rr(ptr %p, i32 %n) {
entry:
- %arrayidx = getelementptr inbounds i16, i16* %p, i32 %n
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %p, i32 %n
+ %0 = load i16, ptr %arrayidx, align 2
%conv = zext i16 %0 to i32
ret i32 %conv
}
@@ -52,20 +52,20 @@ entry:
; CHECK-T1: lsls r1, r1, #2
; CHECK-T1: ldr r0, [r0, r1]
; CHECK-T2: ldr.w r0, [r0, r1, lsl #2]
-define i32 @ldr_rr(i32* %p, i32 %n) {
+define i32 @ldr_rr(ptr %p, i32 %n) {
entry:
- %arrayidx = getelementptr inbounds i32, i32* %p, i32 %n
- %0 = load i32, i32* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %p, i32 %n
+ %0 = load i32, ptr %arrayidx, align 4
ret i32 %0
}
; CHECK-LABEL: strb_rr
; CHECK: strb r2, [r0, r1]
-define void @strb_rr(i8* %p, i32 %n, i32 %x) {
+define void @strb_rr(ptr %p, i32 %n, i32 %x) {
entry:
%conv = trunc i32 %x to i8
- %arrayidx = getelementptr inbounds i8, i8* %p, i32 %n
- store i8 %conv, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds i8, ptr %p, i32 %n
+ store i8 %conv, ptr %arrayidx, align 1
ret void
}
@@ -73,11 +73,11 @@ entry:
; CHECK-T1: lsls r1, r1, #1
; CHECK-T1: strh r2, [r0, r1]
; CHECK-T2: strh.w r2, [r0, r1, lsl #1]
-define void @strh_rr(i16* %p, i32 %n, i32 %x) {
+define void @strh_rr(ptr %p, i32 %n, i32 %x) {
entry:
%conv = trunc i32 %x to i16
- %arrayidx = getelementptr inbounds i16, i16* %p, i32 %n
- store i16 %conv, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %p, i32 %n
+ store i16 %conv, ptr %arrayidx, align 2
ret void
}
@@ -85,10 +85,10 @@ entry:
; CHECK-T1: lsls r1, r1, #2
; CHECK-T1: str r2, [r0, r1]
; CHECK-T2: str.w r2, [r0, r1, lsl #2]
-define void @str_rr(i32* %p, i32 %n, i32 %x) {
+define void @str_rr(ptr %p, i32 %n, i32 %x) {
entry:
- %arrayidx = getelementptr inbounds i32, i32* %p, i32 %n
- store i32 %x, i32* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %p, i32 %n
+ store i32 %x, ptr %arrayidx, align 4
ret void
}
@@ -99,9 +99,9 @@ entry:
; CHECK-T1: movs r1, #0
; CHECK-T1: ldrsb r0, [r0, r1]
; CHECK-T2: ldrsb.w r0, [r0]
-define i32 @ldrsb_ri_zero(i8* %p) {
+define i32 @ldrsb_ri_zero(ptr %p) {
entry:
- %0 = load i8, i8* %p, align 1
+ %0 = load i8, ptr %p, align 1
%conv = sext i8 %0 to i32
ret i32 %conv
}
@@ -110,62 +110,62 @@ entry:
; CHECK-T1: movs r1, #0
; CHECK-T1: ldrsh r0, [r0, r1]
; CHECK-T2: ldrsh.w r0, [r0]
-define i32 @ldrsh_ri_zero(i16* %p) {
+define i32 @ldrsh_ri_zero(ptr %p) {
entry:
- %0 = load i16, i16* %p, align 2
+ %0 = load i16, ptr %p, align 2
%conv = sext i16 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: ldrb_ri_zero
; CHECK: ldrb r0, [r0]
-define i32 @ldrb_ri_zero(i8* %p) {
+define i32 @ldrb_ri_zero(ptr %p) {
entry:
- %0 = load i8, i8* %p, align 1
+ %0 = load i8, ptr %p, align 1
%conv = zext i8 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: ldrh_ri_zero
; CHECK: ldrh r0, [r0]
-define i32 @ldrh_ri_zero(i16* %p) {
+define i32 @ldrh_ri_zero(ptr %p) {
entry:
- %0 = load i16, i16* %p, align 2
+ %0 = load i16, ptr %p, align 2
%conv = zext i16 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: ldr_ri_zero
; CHECK: ldr r0, [r0]
-define i32 @ldr_ri_zero(i32* %p) {
+define i32 @ldr_ri_zero(ptr %p) {
entry:
- %0 = load i32, i32* %p, align 4
+ %0 = load i32, ptr %p, align 4
ret i32 %0
}
; CHECK-LABEL: strb_ri_zero
; CHECK: strb r1, [r0]
-define void @strb_ri_zero(i8* %p, i32 %x) {
+define void @strb_ri_zero(ptr %p, i32 %x) {
entry:
%conv = trunc i32 %x to i8
- store i8 %conv, i8* %p, align 1
+ store i8 %conv, ptr %p, align 1
ret void
}
; CHECK-LABEL: strh_ri_zero
; CHECK: strh r1, [r0]
-define void @strh_ri_zero(i16* %p, i32 %x) {
+define void @strh_ri_zero(ptr %p, i32 %x) {
entry:
%conv = trunc i32 %x to i16
- store i16 %conv, i16* %p, align 2
+ store i16 %conv, ptr %p, align 2
ret void
}
; CHECK-LABEL: str_ri_zero
; CHECK: str r1, [r0]
-define void @str_ri_zero(i32* %p, i32 %x) {
+define void @str_ri_zero(ptr %p, i32 %x) {
entry:
- store i32 %x, i32* %p, align 4
+ store i32 %x, ptr %p, align 4
ret void
}
@@ -176,10 +176,10 @@ entry:
; CHECK-T1: movs r1, #31
; CHECK-T1: ldrsb r0, [r0, r1]
; CHECK-T2: ldrsb.w r0, [r0, #31]
-define i32 @ldrsb_ri_t1_max(i8* %p) {
+define i32 @ldrsb_ri_t1_max(ptr %p) {
entry:
- %arrayidx = getelementptr inbounds i8, i8* %p, i32 31
- %0 = load i8, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds i8, ptr %p, i32 31
+ %0 = load i8, ptr %arrayidx, align 1
%conv = sext i8 %0 to i32
ret i32 %conv
}
@@ -188,69 +188,69 @@ entry:
; CHECK-T1: movs r1, #62
; CHECK-T1: ldrsh r0, [r0, r1]
; CHECK-T2: ldrsh.w r0, [r0, #62]
-define i32 @ldrsh_ri_t1_max(i16* %p) {
+define i32 @ldrsh_ri_t1_max(ptr %p) {
entry:
- %arrayidx = getelementptr inbounds i16, i16* %p, i32 31
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %p, i32 31
+ %0 = load i16, ptr %arrayidx, align 2
%conv = sext i16 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: ldrb_ri_t1_max
; CHECK: ldrb r0, [r0, #31]
-define i32 @ldrb_ri_t1_max(i8* %p) {
+define i32 @ldrb_ri_t1_max(ptr %p) {
entry:
- %arrayidx = getelementptr inbounds i8, i8* %p, i32 31
- %0 = load i8, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds i8, ptr %p, i32 31
+ %0 = load i8, ptr %arrayidx, align 1
%conv = zext i8 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: ldrh_ri_t1_max
; CHECK: ldrh r0, [r0, #62]
-define i32 @ldrh_ri_t1_max(i16* %p) {
+define i32 @ldrh_ri_t1_max(ptr %p) {
entry:
- %arrayidx = getelementptr inbounds i16, i16* %p, i32 31
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %p, i32 31
+ %0 = load i16, ptr %arrayidx, align 2
%conv = zext i16 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: ldr_ri_t1_max
; CHECK: ldr r0, [r0, #124]
-define i32 @ldr_ri_t1_max(i32* %p) {
+define i32 @ldr_ri_t1_max(ptr %p) {
entry:
- %arrayidx = getelementptr inbounds i32, i32* %p, i32 31
- %0 = load i32, i32* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %p, i32 31
+ %0 = load i32, ptr %arrayidx, align 4
ret i32 %0
}
; CHECK-LABEL: strb_ri_t1_max
; CHECK: strb r1, [r0, #31]
-define void @strb_ri_t1_max(i8* %p, i32 %x) {
+define void @strb_ri_t1_max(ptr %p, i32 %x) {
entry:
%conv = trunc i32 %x to i8
- %arrayidx = getelementptr inbounds i8, i8* %p, i32 31
- store i8 %conv, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds i8, ptr %p, i32 31
+ store i8 %conv, ptr %arrayidx, align 1
ret void
}
; CHECK-LABEL: strh_ri_t1_max
; CHECK: strh r1, [r0, #62]
-define void @strh_ri_t1_max(i16* %p, i32 %x) {
+define void @strh_ri_t1_max(ptr %p, i32 %x) {
entry:
%conv = trunc i32 %x to i16
- %arrayidx = getelementptr inbounds i16, i16* %p, i32 31
- store i16 %conv, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %p, i32 31
+ store i16 %conv, ptr %arrayidx, align 2
ret void
}
; CHECK-LABEL: str_ri_t1_max
; CHECK: str r1, [r0, #124]
-define void @str_ri_t1_max(i32* %p, i32 %x) {
+define void @str_ri_t1_max(ptr %p, i32 %x) {
entry:
- %arrayidx = getelementptr inbounds i32, i32* %p, i32 31
- store i32 %x, i32* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %p, i32 31
+ store i32 %x, ptr %arrayidx, align 4
ret void
}
@@ -261,10 +261,10 @@ entry:
; CHECK-T1: movs r1, #32
; CHECK-T1: ldrsb r0, [r0, r1]
; CHECK-T2: ldrsb.w r0, [r0, #32]
-define i32 @ldrsb_ri_t1_too_big(i8* %p) {
+define i32 @ldrsb_ri_t1_too_big(ptr %p) {
entry:
- %arrayidx = getelementptr inbounds i8, i8* %p, i32 32
- %0 = load i8, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds i8, ptr %p, i32 32
+ %0 = load i8, ptr %arrayidx, align 1
%conv = sext i8 %0 to i32
ret i32 %conv
}
@@ -273,10 +273,10 @@ entry:
; CHECK-T1: movs r1, #64
; CHECK-T1: ldrsh r0, [r0, r1]
; CHECK-T2: ldrsh.w r0, [r0, #64]
-define i32 @ldrsh_ri_t1_too_big(i16* %p) {
+define i32 @ldrsh_ri_t1_too_big(ptr %p) {
entry:
- %arrayidx = getelementptr inbounds i16, i16* %p, i32 32
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %p, i32 32
+ %0 = load i16, ptr %arrayidx, align 2
%conv = sext i16 %0 to i32
ret i32 %conv
}
@@ -285,10 +285,10 @@ entry:
; CHECK-T1: movs r1, #32
; CHECK-T1: ldrb r0, [r0, r1]
; CHECK-T2: ldrb.w r0, [r0, #32]
-define i32 @ldrb_ri_t1_too_big(i8* %p) {
+define i32 @ldrb_ri_t1_too_big(ptr %p) {
entry:
- %arrayidx = getelementptr inbounds i8, i8* %p, i32 32
- %0 = load i8, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds i8, ptr %p, i32 32
+ %0 = load i8, ptr %arrayidx, align 1
%conv = zext i8 %0 to i32
ret i32 %conv
}
@@ -297,10 +297,10 @@ entry:
; CHECK-T1: movs r1, #64
; CHECK-T1: ldrh r0, [r0, r1]
; CHECK-T2: ldrh.w r0, [r0, #64]
-define i32 @ldrh_ri_t1_too_big(i16* %p) {
+define i32 @ldrh_ri_t1_too_big(ptr %p) {
entry:
- %arrayidx = getelementptr inbounds i16, i16* %p, i32 32
- %0 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %p, i32 32
+ %0 = load i16, ptr %arrayidx, align 2
%conv = zext i16 %0 to i32
ret i32 %conv
}
@@ -309,10 +309,10 @@ entry:
; CHECK-T1: movs r1, #128
; CHECK-T1: ldr r0, [r0, r1]
; CHECK-T2: ldr.w r0, [r0, #128]
-define i32 @ldr_ri_t1_too_big(i32* %p) {
+define i32 @ldr_ri_t1_too_big(ptr %p) {
entry:
- %arrayidx = getelementptr inbounds i32, i32* %p, i32 32
- %0 = load i32, i32* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %p, i32 32
+ %0 = load i32, ptr %arrayidx, align 4
ret i32 %0
}
@@ -320,11 +320,11 @@ entry:
; CHECK-T1: movs r2, #32
; CHECK-T1: strb r1, [r0, r2]
; CHECK-T2: strb.w r1, [r0, #32]
-define void @strb_ri_t1_too_big(i8* %p, i32 %x) {
+define void @strb_ri_t1_too_big(ptr %p, i32 %x) {
entry:
%conv = trunc i32 %x to i8
- %arrayidx = getelementptr inbounds i8, i8* %p, i32 32
- store i8 %conv, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds i8, ptr %p, i32 32
+ store i8 %conv, ptr %arrayidx, align 1
ret void
}
@@ -332,11 +332,11 @@ entry:
; CHECK-T1: movs r2, #64
; CHECK-T1: strh r1, [r0, r2]
; CHECK-T2: strh.w r1, [r0, #64]
-define void @strh_ri_t1_too_big(i16* %p, i32 %x) {
+define void @strh_ri_t1_too_big(ptr %p, i32 %x) {
entry:
%conv = trunc i32 %x to i16
- %arrayidx = getelementptr inbounds i16, i16* %p, i32 32
- store i16 %conv, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %p, i32 32
+ store i16 %conv, ptr %arrayidx, align 2
ret void
}
@@ -344,10 +344,10 @@ entry:
; CHECK-T1: movs r2, #128
; CHECK-T1: str r1, [r0, r2]
; CHECK-T2: str.w r1, [r0, #128]
-define void @str_ri_t1_too_big(i32* %p, i32 %x) {
+define void @str_ri_t1_too_big(ptr %p, i32 %x) {
entry:
- %arrayidx = getelementptr inbounds i32, i32* %p, i32 32
- store i32 %x, i32* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %p, i32 32
+ store i32 %x, ptr %arrayidx, align 4
ret void
}
@@ -358,10 +358,10 @@ entry:
; CHECK-T1: ldr r1, .LCP
; CHECK-T1: ldrsb r0, [r0, r1]
; CHECK-T2: ldrsb.w r0, [r0, #4095]
-define i32 @ldrsb_ri_t2_max(i8* %p) {
+define i32 @ldrsb_ri_t2_max(ptr %p) {
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095
- %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4095
+ %0 = load i8, ptr %add.ptr, align 1
%conv = sext i8 %0 to i32
ret i32 %conv
}
@@ -370,12 +370,11 @@ entry:
; CHECK-T1: ldr r1, .LCP
; CHECK-T1: ldrsh r0, [r0, r1]
; CHECK-T2: ldrsh.w r0, [r0, #4095]
-define i32 @ldrsh_ri_t2_max(i8* %p) {
+define i32 @ldrsh_ri_t2_max(ptr %p) {
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095
- %0 = bitcast i8* %add.ptr to i16*
- %1 = load i16, i16* %0, align 2
- %conv = sext i16 %1 to i32
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4095
+ %0 = load i16, ptr %add.ptr, align 2
+ %conv = sext i16 %0 to i32
ret i32 %conv
}
@@ -383,10 +382,10 @@ entry:
; CHECK-T1: ldr r1, .LCP
; CHECK-T1: ldrb r0, [r0, r1]
; CHECK-T2: ldrb.w r0, [r0, #4095]
-define i32 @ldrb_ri_t2_max(i8* %p) {
+define i32 @ldrb_ri_t2_max(ptr %p) {
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095
- %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4095
+ %0 = load i8, ptr %add.ptr, align 1
%conv = zext i8 %0 to i32
ret i32 %conv
}
@@ -395,12 +394,11 @@ entry:
; CHECK-T1: ldr r1, .LCP
; CHECK-T1: ldrh r0, [r0, r1]
; CHECK-T2: ldrh.w r0, [r0, #4095]
-define i32 @ldrh_ri_t2_max(i8* %p) {
+define i32 @ldrh_ri_t2_max(ptr %p) {
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095
- %0 = bitcast i8* %add.ptr to i16*
- %1 = load i16, i16* %0, align 2
- %conv = zext i16 %1 to i32
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4095
+ %0 = load i16, ptr %add.ptr, align 2
+ %conv = zext i16 %0 to i32
ret i32 %conv
}
@@ -408,23 +406,22 @@ entry:
; CHECK-T1: ldr r1, .LCP
; CHECK-T1: ldr r0, [r0, r1]
; CHECK-T2: ldr.w r0, [r0, #4095]
-define i32 @ldr_ri_t2_max(i8* %p) {
+define i32 @ldr_ri_t2_max(ptr %p) {
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095
- %0 = bitcast i8* %add.ptr to i32*
- %1 = load i32, i32* %0, align 4
- ret i32 %1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4095
+ %0 = load i32, ptr %add.ptr, align 4
+ ret i32 %0
}
; CHECK-LABEL: strb_ri_t2_max
; CHECK-T1: ldr r2, .LCP
; CHECK-T1: strb r1, [r0, r2]
; CHECK-T2: strb.w r1, [r0, #4095]
-define void @strb_ri_t2_max(i8* %p, i32 %x) {
+define void @strb_ri_t2_max(ptr %p, i32 %x) {
entry:
%conv = trunc i32 %x to i8
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095
- store i8 %conv, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4095
+ store i8 %conv, ptr %add.ptr, align 1
ret void
}
@@ -432,12 +429,11 @@ entry:
; CHECK-T1: ldr r2, .LCP
; CHECK-T1: strh r1, [r0, r2]
; CHECK-T2: strh.w r1, [r0, #4095]
-define void @strh_ri_t2_max(i8* %p, i32 %x) {
+define void @strh_ri_t2_max(ptr %p, i32 %x) {
entry:
%conv = trunc i32 %x to i16
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095
- %0 = bitcast i8* %add.ptr to i16*
- store i16 %conv, i16* %0, align 2
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4095
+ store i16 %conv, ptr %add.ptr, align 2
ret void
}
@@ -445,11 +441,10 @@ entry:
; CHECK-T1: ldr r2, .LCP
; CHECK-T1: str r1, [r0, r2]
; CHECK-T2: str.w r1, [r0, #4095]
-define void @str_ri_t2_max(i8* %p, i32 %x) {
+define void @str_ri_t2_max(ptr %p, i32 %x) {
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095
- %0 = bitcast i8* %add.ptr to i32*
- store i32 %x, i32* %0, align 4
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4095
+ store i32 %x, ptr %add.ptr, align 4
ret void
}
@@ -461,10 +456,10 @@ entry:
; CHECK-T1: lsls r1, r1, #12
; CHECK-T2: mov.w r1, #4096
; CHECK: ldrsb r0, [r0, r1]
-define i32 @ldrsb_ri_t2_too_big(i8* %p) {
+define i32 @ldrsb_ri_t2_too_big(ptr %p) {
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096
- %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4096
+ %0 = load i8, ptr %add.ptr, align 1
%conv = sext i8 %0 to i32
ret i32 %conv
}
@@ -474,12 +469,11 @@ entry:
; CHECK-T1: lsls r1, r1, #12
; CHECK-T2: mov.w r1, #4096
; CHECK: ldrsh r0, [r0, r1]
-define i32 @ldrsh_ri_t2_too_big(i8* %p) {
+define i32 @ldrsh_ri_t2_too_big(ptr %p) {
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096
- %0 = bitcast i8* %add.ptr to i16*
- %1 = load i16, i16* %0, align 2
- %conv = sext i16 %1 to i32
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4096
+ %0 = load i16, ptr %add.ptr, align 2
+ %conv = sext i16 %0 to i32
ret i32 %conv
}
@@ -488,10 +482,10 @@ entry:
; CHECK-T1: lsls r1, r1, #12
; CHECK-T2: mov.w r1, #4096
; CHECK: ldrb r0, [r0, r1]
-define i32 @ldrb_ri_t2_too_big(i8* %p) {
+define i32 @ldrb_ri_t2_too_big(ptr %p) {
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096
- %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4096
+ %0 = load i8, ptr %add.ptr, align 1
%conv = zext i8 %0 to i32
ret i32 %conv
}
@@ -501,12 +495,11 @@ entry:
; CHECK-T1: lsls r1, r1, #12
; CHECK-T2: mov.w r1, #4096
; CHECK: ldrh r0, [r0, r1]
-define i32 @ldrh_ri_t2_too_big(i8* %p) {
+define i32 @ldrh_ri_t2_too_big(ptr %p) {
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096
- %0 = bitcast i8* %add.ptr to i16*
- %1 = load i16, i16* %0, align 2
- %conv = zext i16 %1 to i32
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4096
+ %0 = load i16, ptr %add.ptr, align 2
+ %conv = zext i16 %0 to i32
ret i32 %conv
}
@@ -515,12 +508,11 @@ entry:
; CHECK-T1: lsls r1, r1, #12
; CHECK-T2: mov.w r1, #4096
; CHECK: ldr r0, [r0, r1]
-define i32 @ldr_ri_t2_too_big(i8* %p) {
+define i32 @ldr_ri_t2_too_big(ptr %p) {
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096
- %0 = bitcast i8* %add.ptr to i32*
- %1 = load i32, i32* %0, align 4
- ret i32 %1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4096
+ %0 = load i32, ptr %add.ptr, align 4
+ ret i32 %0
}
; CHECK-LABEL: strb_ri_t2_too_big
@@ -528,11 +520,11 @@ entry:
; CHECK-T1: lsls r2, r2, #12
; CHECK-T2: mov.w r2, #4096
; CHECK: strb r1, [r0, r2]
-define void @strb_ri_t2_too_big(i8* %p, i32 %x) {
+define void @strb_ri_t2_too_big(ptr %p, i32 %x) {
entry:
%conv = trunc i32 %x to i8
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096
- store i8 %conv, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4096
+ store i8 %conv, ptr %add.ptr, align 1
ret void
}
@@ -541,12 +533,11 @@ entry:
; CHECK-T1: lsls r2, r2, #12
; CHECK-T2: mov.w r2, #4096
; CHECK: strh r1, [r0, r2]
-define void @strh_ri_t2_too_big(i8* %p, i32 %x) {
+define void @strh_ri_t2_too_big(ptr %p, i32 %x) {
entry:
%conv = trunc i32 %x to i16
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096
- %0 = bitcast i8* %add.ptr to i16*
- store i16 %conv, i16* %0, align 2
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4096
+ store i16 %conv, ptr %add.ptr, align 2
ret void
}
@@ -555,18 +546,17 @@ entry:
; CHECK-T1: lsls r2, r2, #12
; CHECK-T2: mov.w r2, #4096
; CHECK: str r1, [r0, r2]
-define void @str_ri_t2_too_big(i8* %p, i32 %x) {
+define void @str_ri_t2_too_big(ptr %p, i32 %x) {
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096
- %0 = bitcast i8* %add.ptr to i32*
- store i32 %x, i32* %0, align 4
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 4096
+ store i32 %x, ptr %add.ptr, align 4
ret void
}
; Negative offset
-define i32 @ldrsb_ri_negative(i8* %p) {
+define i32 @ldrsb_ri_negative(ptr %p) {
; CHECK-T1-LABEL: ldrsb_ri_negative:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: movs r1, #0
@@ -579,13 +569,13 @@ define i32 @ldrsb_ri_negative(i8* %p) {
; CHECK-T2-NEXT: ldrsb r0, [r0, #-1]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -1
- %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -1
+ %0 = load i8, ptr %add.ptr, align 1
%conv = sext i8 %0 to i32
ret i32 %conv
}
-define i32 @ldrsh_ri_negative(i8* %p) {
+define i32 @ldrsh_ri_negative(ptr %p) {
; CHECK-T1-LABEL: ldrsh_ri_negative:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: movs r1, #0
@@ -598,14 +588,13 @@ define i32 @ldrsh_ri_negative(i8* %p) {
; CHECK-T2-NEXT: ldrsh r0, [r0, #-1]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -1
- %0 = bitcast i8* %add.ptr to i16*
- %1 = load i16, i16* %0, align 2
- %conv = sext i16 %1 to i32
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -1
+ %0 = load i16, ptr %add.ptr, align 2
+ %conv = sext i16 %0 to i32
ret i32 %conv
}
-define i32 @ldrb_ri_negative(i8* %p) {
+define i32 @ldrb_ri_negative(ptr %p) {
; CHECK-T1-LABEL: ldrb_ri_negative:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -617,13 +606,13 @@ define i32 @ldrb_ri_negative(i8* %p) {
; CHECK-T2-NEXT: ldrb r0, [r0, #-1]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -1
- %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -1
+ %0 = load i8, ptr %add.ptr, align 1
%conv = zext i8 %0 to i32
ret i32 %conv
}
-define i32 @ldrh_ri_negative(i8* %p) {
+define i32 @ldrh_ri_negative(ptr %p) {
; CHECK-T1-LABEL: ldrh_ri_negative:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -635,14 +624,13 @@ define i32 @ldrh_ri_negative(i8* %p) {
; CHECK-T2-NEXT: ldrh r0, [r0, #-1]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -1
- %0 = bitcast i8* %add.ptr to i16*
- %1 = load i16, i16* %0, align 2
- %conv = zext i16 %1 to i32
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -1
+ %0 = load i16, ptr %add.ptr, align 2
+ %conv = zext i16 %0 to i32
ret i32 %conv
}
-define i32 @ldr_ri_negative(i8* %p) {
+define i32 @ldr_ri_negative(ptr %p) {
; CHECK-T1-LABEL: ldr_ri_negative:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -654,13 +642,12 @@ define i32 @ldr_ri_negative(i8* %p) {
; CHECK-T2-NEXT: ldr r0, [r0, #-1]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -1
- %0 = bitcast i8* %add.ptr to i32*
- %1 = load i32, i32* %0, align 4
- ret i32 %1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -1
+ %0 = load i32, ptr %add.ptr, align 4
+ ret i32 %0
}
-define void @strb_ri_negative(i8* %p, i32 %x) {
+define void @strb_ri_negative(ptr %p, i32 %x) {
; CHECK-T1-LABEL: strb_ri_negative:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -673,12 +660,12 @@ define void @strb_ri_negative(i8* %p, i32 %x) {
; CHECK-T2-NEXT: bx lr
entry:
%conv = trunc i32 %x to i8
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -1
- store i8 %conv, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -1
+ store i8 %conv, ptr %add.ptr, align 1
ret void
}
-define void @strh_ri_negative(i8* %p, i32 %x) {
+define void @strh_ri_negative(ptr %p, i32 %x) {
; CHECK-T1-LABEL: strh_ri_negative:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -691,13 +678,12 @@ define void @strh_ri_negative(i8* %p, i32 %x) {
; CHECK-T2-NEXT: bx lr
entry:
%conv = trunc i32 %x to i16
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -1
- %0 = bitcast i8* %add.ptr to i16*
- store i16 %conv, i16* %0, align 2
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -1
+ store i16 %conv, ptr %add.ptr, align 2
ret void
}
-define void @str_ri_negative(i8* %p, i32 %x) {
+define void @str_ri_negative(ptr %p, i32 %x) {
; CHECK-T1-LABEL: str_ri_negative:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -709,16 +695,15 @@ define void @str_ri_negative(i8* %p, i32 %x) {
; CHECK-T2-NEXT: str r1, [r0, #-1]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -1
- %0 = bitcast i8* %add.ptr to i32*
- store i32 %x, i32* %0, align 4
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -1
+ store i32 %x, ptr %add.ptr, align 4
ret void
}
; Negative 255 offset
-define i32 @ldrsb_ri_negative255(i8* %p) {
+define i32 @ldrsb_ri_negative255(ptr %p) {
; CHECK-T1-LABEL: ldrsb_ri_negative255:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: movs r1, #254
@@ -731,13 +716,13 @@ define i32 @ldrsb_ri_negative255(i8* %p) {
; CHECK-T2-NEXT: ldrsb r0, [r0, #-255]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -255
- %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -255
+ %0 = load i8, ptr %add.ptr, align 1
%conv = sext i8 %0 to i32
ret i32 %conv
}
-define i32 @ldrsh_ri_negative255(i8* %p) {
+define i32 @ldrsh_ri_negative255(ptr %p) {
; CHECK-T1-LABEL: ldrsh_ri_negative255:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: movs r1, #254
@@ -750,14 +735,13 @@ define i32 @ldrsh_ri_negative255(i8* %p) {
; CHECK-T2-NEXT: ldrsh r0, [r0, #-255]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -255
- %0 = bitcast i8* %add.ptr to i16*
- %1 = load i16, i16* %0, align 2
- %conv = sext i16 %1 to i32
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -255
+ %0 = load i16, ptr %add.ptr, align 2
+ %conv = sext i16 %0 to i32
ret i32 %conv
}
-define i32 @ldrb_ri_negative255(i8* %p) {
+define i32 @ldrb_ri_negative255(ptr %p) {
; CHECK-T1-LABEL: ldrb_ri_negative255:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: subs r0, #255
@@ -769,13 +753,13 @@ define i32 @ldrb_ri_negative255(i8* %p) {
; CHECK-T2-NEXT: ldrb r0, [r0, #-255]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -255
- %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -255
+ %0 = load i8, ptr %add.ptr, align 1
%conv = zext i8 %0 to i32
ret i32 %conv
}
-define i32 @ldrh_ri_negative255(i8* %p) {
+define i32 @ldrh_ri_negative255(ptr %p) {
; CHECK-T1-LABEL: ldrh_ri_negative255:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: subs r0, #255
@@ -787,14 +771,13 @@ define i32 @ldrh_ri_negative255(i8* %p) {
; CHECK-T2-NEXT: ldrh r0, [r0, #-255]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -255
- %0 = bitcast i8* %add.ptr to i16*
- %1 = load i16, i16* %0, align 2
- %conv = zext i16 %1 to i32
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -255
+ %0 = load i16, ptr %add.ptr, align 2
+ %conv = zext i16 %0 to i32
ret i32 %conv
}
-define i32 @ldr_ri_negative255(i8* %p) {
+define i32 @ldr_ri_negative255(ptr %p) {
; CHECK-T1-LABEL: ldr_ri_negative255:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: subs r0, #255
@@ -806,13 +789,12 @@ define i32 @ldr_ri_negative255(i8* %p) {
; CHECK-T2-NEXT: ldr r0, [r0, #-255]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -255
- %0 = bitcast i8* %add.ptr to i32*
- %1 = load i32, i32* %0, align 4
- ret i32 %1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -255
+ %0 = load i32, ptr %add.ptr, align 4
+ ret i32 %0
}
-define void @strb_ri_negative255(i8* %p, i32 %x) {
+define void @strb_ri_negative255(ptr %p, i32 %x) {
; CHECK-T1-LABEL: strb_ri_negative255:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: subs r0, #255
@@ -825,12 +807,12 @@ define void @strb_ri_negative255(i8* %p, i32 %x) {
; CHECK-T2-NEXT: bx lr
entry:
%conv = trunc i32 %x to i8
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -255
- store i8 %conv, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -255
+ store i8 %conv, ptr %add.ptr, align 1
ret void
}
-define void @strh_ri_negative255(i8* %p, i32 %x) {
+define void @strh_ri_negative255(ptr %p, i32 %x) {
; CHECK-T1-LABEL: strh_ri_negative255:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: subs r0, #255
@@ -843,13 +825,12 @@ define void @strh_ri_negative255(i8* %p, i32 %x) {
; CHECK-T2-NEXT: bx lr
entry:
%conv = trunc i32 %x to i16
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -255
- %0 = bitcast i8* %add.ptr to i16*
- store i16 %conv, i16* %0, align 2
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -255
+ store i16 %conv, ptr %add.ptr, align 2
ret void
}
-define void @str_ri_negative255(i8* %p, i32 %x) {
+define void @str_ri_negative255(ptr %p, i32 %x) {
; CHECK-T1-LABEL: str_ri_negative255:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: subs r0, #255
@@ -861,16 +842,15 @@ define void @str_ri_negative255(i8* %p, i32 %x) {
; CHECK-T2-NEXT: str r1, [r0, #-255]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -255
- %0 = bitcast i8* %add.ptr to i32*
- store i32 %x, i32* %0, align 4
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -255
+ store i32 %x, ptr %add.ptr, align 4
ret void
}
; Negative 256 offset
-define i32 @ldrsb_ri_negative256(i8* %p) {
+define i32 @ldrsb_ri_negative256(ptr %p) {
; CHECK-T1-LABEL: ldrsb_ri_negative256:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: movs r1, #255
@@ -884,13 +864,13 @@ define i32 @ldrsb_ri_negative256(i8* %p) {
; CHECK-T2-NEXT: ldrsb r0, [r0, r1]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -256
- %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -256
+ %0 = load i8, ptr %add.ptr, align 1
%conv = sext i8 %0 to i32
ret i32 %conv
}
-define i32 @ldrsh_ri_negative256(i8* %p) {
+define i32 @ldrsh_ri_negative256(ptr %p) {
; CHECK-T1-LABEL: ldrsh_ri_negative256:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: movs r1, #255
@@ -904,14 +884,13 @@ define i32 @ldrsh_ri_negative256(i8* %p) {
; CHECK-T2-NEXT: ldrsh r0, [r0, r1]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -256
- %0 = bitcast i8* %add.ptr to i16*
- %1 = load i16, i16* %0, align 2
- %conv = sext i16 %1 to i32
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -256
+ %0 = load i16, ptr %add.ptr, align 2
+ %conv = sext i16 %0 to i32
ret i32 %conv
}
-define i32 @ldrb_ri_negative256(i8* %p) {
+define i32 @ldrb_ri_negative256(ptr %p) {
; CHECK-T1-LABEL: ldrb_ri_negative256:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: movs r1, #255
@@ -925,13 +904,13 @@ define i32 @ldrb_ri_negative256(i8* %p) {
; CHECK-T2-NEXT: ldrb r0, [r0, r1]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -256
- %0 = load i8, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -256
+ %0 = load i8, ptr %add.ptr, align 1
%conv = zext i8 %0 to i32
ret i32 %conv
}
-define i32 @ldrh_ri_negative256(i8* %p) {
+define i32 @ldrh_ri_negative256(ptr %p) {
; CHECK-T1-LABEL: ldrh_ri_negative256:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: movs r1, #255
@@ -945,14 +924,13 @@ define i32 @ldrh_ri_negative256(i8* %p) {
; CHECK-T2-NEXT: ldrh r0, [r0, r1]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -256
- %0 = bitcast i8* %add.ptr to i16*
- %1 = load i16, i16* %0, align 2
- %conv = zext i16 %1 to i32
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -256
+ %0 = load i16, ptr %add.ptr, align 2
+ %conv = zext i16 %0 to i32
ret i32 %conv
}
-define i32 @ldr_ri_negative256(i8* %p) {
+define i32 @ldr_ri_negative256(ptr %p) {
; CHECK-T1-LABEL: ldr_ri_negative256:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: movs r1, #255
@@ -966,13 +944,12 @@ define i32 @ldr_ri_negative256(i8* %p) {
; CHECK-T2-NEXT: ldr r0, [r0, r1]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -256
- %0 = bitcast i8* %add.ptr to i32*
- %1 = load i32, i32* %0, align 4
- ret i32 %1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -256
+ %0 = load i32, ptr %add.ptr, align 4
+ ret i32 %0
}
-define void @strb_ri_negative256(i8* %p, i32 %x) {
+define void @strb_ri_negative256(ptr %p, i32 %x) {
; CHECK-T1-LABEL: strb_ri_negative256:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: movs r2, #255
@@ -987,12 +964,12 @@ define void @strb_ri_negative256(i8* %p, i32 %x) {
; CHECK-T2-NEXT: bx lr
entry:
%conv = trunc i32 %x to i8
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -256
- store i8 %conv, i8* %add.ptr, align 1
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -256
+ store i8 %conv, ptr %add.ptr, align 1
ret void
}
-define void @strh_ri_negative256(i8* %p, i32 %x) {
+define void @strh_ri_negative256(ptr %p, i32 %x) {
; CHECK-T1-LABEL: strh_ri_negative256:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: movs r2, #255
@@ -1007,13 +984,12 @@ define void @strh_ri_negative256(i8* %p, i32 %x) {
; CHECK-T2-NEXT: bx lr
entry:
%conv = trunc i32 %x to i16
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -256
- %0 = bitcast i8* %add.ptr to i16*
- store i16 %conv, i16* %0, align 2
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -256
+ store i16 %conv, ptr %add.ptr, align 2
ret void
}
-define void @str_ri_negative256(i8* %p, i32 %x) {
+define void @str_ri_negative256(ptr %p, i32 %x) {
; CHECK-T1-LABEL: str_ri_negative256:
; CHECK-T1: @ %bb.0: @ %entry
; CHECK-T1-NEXT: movs r2, #255
@@ -1027,8 +1003,7 @@ define void @str_ri_negative256(i8* %p, i32 %x) {
; CHECK-T2-NEXT: str r1, [r0, r2]
; CHECK-T2-NEXT: bx lr
entry:
- %add.ptr = getelementptr inbounds i8, i8* %p, i32 -256
- %0 = bitcast i8* %add.ptr to i32*
- store i32 %x, i32* %0, align 4
+ %add.ptr = getelementptr inbounds i8, ptr %p, i32 -256
+ store i32 %x, ptr %add.ptr, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/load_i1_select.ll b/llvm/test/CodeGen/ARM/load_i1_select.ll
index 459b121ce1de1..296ff25967e50 100644
--- a/llvm/test/CodeGen/ARM/load_i1_select.ll
+++ b/llvm/test/CodeGen/ARM/load_i1_select.ll
@@ -9,11 +9,11 @@ target triple = "thumbv7-apple-ios0.0.0"
; CHECK-LABEL: foo:
; CHECK: ldrb r[[R0:[0-9]+]], [r0]
; CHECK: lsls r{{[0-9]+}}, r[[R0]], #31
-define void @foo(i8* %call, double* %p) nounwind {
+define void @foo(ptr %call, ptr %p) nounwind {
entry:
- %tmp2 = load i8, i8* %call
+ %tmp2 = load i8, ptr %call
%tmp3 = trunc i8 %tmp2 to i1
%cond = select i1 %tmp3, double 2.000000e+00, double 1.000000e+00
- store double %cond, double* %p
+ store double %cond, ptr %p
ret void
}
diff --git a/llvm/test/CodeGen/ARM/load_store_multiple.ll b/llvm/test/CodeGen/ARM/load_store_multiple.ll
index a636a8d12b223..7917c45fd53ed 100644
--- a/llvm/test/CodeGen/ARM/load_store_multiple.ll
+++ b/llvm/test/CodeGen/ARM/load_store_multiple.ll
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple=armv7-eabi -mattr=+neon %s -o - | FileCheck %s --check-prefix=CHECK-LE
; RUN: llc -verify-machineinstrs -mtriple=armv7eb-eabi -mattr=+neon %s -o - | FileCheck %s --check-prefix=CHECK-BE
-define void @ld_st_vec_i8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define void @ld_st_vec_i8(ptr %A, ptr %B) nounwind {
;CHECK-LE-LABEL: ld_st_vec_i8:
;CHECK-LE: vld1.8 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}]
;CHECK-LE-NOT: vrev
@@ -13,12 +13,12 @@ define void @ld_st_vec_i8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
;CHECK-BE: vrev64.8 [[Q1]], [[Q2]]
;CHECK-BE: vst1.8 {[[D1]], [[D2]]}, [{{r[0-9]+}}]
-%load = load <16 x i8>, <16 x i8>* %A, align 1
-store <16 x i8> %load, <16 x i8>* %B, align 1
+%load = load <16 x i8>, ptr %A, align 1
+store <16 x i8> %load, ptr %B, align 1
ret void
}
-define void @ld_st_vec_i16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define void @ld_st_vec_i16(ptr %A, ptr %B) nounwind {
;CHECK-LE-LABEL: ld_st_vec_i16:
;CHECK-LE: vld1.16 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}]
;CHECK-LE-NOT: vrev
@@ -30,12 +30,12 @@ define void @ld_st_vec_i16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
;CHECK-BE: vrev64.16 [[Q1]], [[Q2]]
;CHECK-BE: vst1.16 {[[D1]], [[D2]]}, [{{r[0-9]+}}]
-%load = load <8 x i16>, <8 x i16>* %A, align 2
-store <8 x i16> %load, <8 x i16>* %B, align 2
+%load = load <8 x i16>, ptr %A, align 2
+store <8 x i16> %load, ptr %B, align 2
ret void
}
-define void @ld_st_vec_i32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define void @ld_st_vec_i32(ptr %A, ptr %B) nounwind {
;CHECK-LE-LABEL: ld_st_vec_i32:
;CHECK-LE: vld1.32 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}]
;CHECK-LE-NOT: vrev
@@ -46,12 +46,12 @@ define void @ld_st_vec_i32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
;CHECK-BE-NOT: vrev
;CHECK-BE: vstmia {{r[0-9]+}}, {[[D1]], [[D2]]}
-%load = load <4 x i32>, <4 x i32>* %A, align 4
-store <4 x i32> %load, <4 x i32>* %B, align 4
+%load = load <4 x i32>, ptr %A, align 4
+store <4 x i32> %load, ptr %B, align 4
ret void
}
-define void @ld_st_vec_double(<2 x double>* %A, <2 x double>* %B) nounwind {
+define void @ld_st_vec_double(ptr %A, ptr %B) nounwind {
;CHECK-LE-LABEL: ld_st_vec_double:
;CHECK-LE: vld1.64 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}]
;CHECK-LE-NOT: vrev
@@ -62,7 +62,7 @@ define void @ld_st_vec_double(<2 x double>* %A, <2 x double>* %B) nounwind {
;CHECK-BE-NOT: vrev
;CHECK-BE: vst1.64 {[[D1]], [[D2]]}, [{{r[0-9]+}}]
-%load = load <2 x double>, <2 x double>* %A, align 8
-store <2 x double> %load, <2 x double>* %B, align 8
+%load = load <2 x double>, ptr %A, align 8
+store <2 x double> %load, ptr %B, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/long.ll b/llvm/test/CodeGen/ARM/long.ll
index 1807813d93052..153b76ecfee11 100644
--- a/llvm/test/CodeGen/ARM/long.ll
+++ b/llvm/test/CodeGen/ARM/long.ll
@@ -84,7 +84,7 @@ entry:
define i64 @f10() {
; CHECK-LABEL: f10:
entry:
- %a = alloca i64, align 8 ; <i64*> [#uses=1]
- %retval = load i64, i64* %a ; <i64> [#uses=1]
+ %a = alloca i64, align 8 ; <ptr> [#uses=1]
+ %retval = load i64, ptr %a ; <i64> [#uses=1]
ret i64 %retval
}
diff --git a/llvm/test/CodeGen/ARM/longMAC.ll b/llvm/test/CodeGen/ARM/longMAC.ll
index 565e26537c163..1670cf15fa6cb 100644
--- a/llvm/test/CodeGen/ARM/longMAC.ll
+++ b/llvm/test/CodeGen/ARM/longMAC.ll
@@ -357,7 +357,7 @@ define i64 @MACLongTest14(i32 %a, i32 %b, i64 %c) {
;CHECK-V7M-THUMB-NOT: smlaltb
define i64 @MACLongTest15(i32 %t, i64 %acc) {
entry:
- %0 = load i16, i16* @global_b, align 2
+ %0 = load i16, ptr @global_b, align 2
%conv = sext i16 %0 to i32
%shr = ashr i32 %t, 16
%mul = mul nsw i32 %shr, %conv
@@ -387,7 +387,7 @@ entry:
;CHECK-V7M-THUMB-NOT: smlalbt
define i64 @MACLongTest16(i32 %t, i64 %acc) {
entry:
- %0 = load i16, i16* @global_b, align 2
+ %0 = load i16, ptr @global_b, align 2
%conv = sext i16 %0 to i32
%shr = ashr i32 %t, 16
%mul = mul nsw i32 %conv, %shr
diff --git a/llvm/test/CodeGen/ARM/loop-align-cortex-m.ll b/llvm/test/CodeGen/ARM/loop-align-cortex-m.ll
index 61ba1a6ca2df3..bce0bbabfdc29 100644
--- a/llvm/test/CodeGen/ARM/loop-align-cortex-m.ll
+++ b/llvm/test/CodeGen/ARM/loop-align-cortex-m.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=thumbv7m-none-eabi %s -mcpu=cortex-m4 -o - | FileCheck %s
; RUN: llc -mtriple=thumbv8m-none-eabi %s -mcpu=cortex-m33 -o - | FileCheck %s
-define void @test_loop_alignment(i32* %in, i32* %out) optsize {
+define void @test_loop_alignment(ptr %in, ptr %out) optsize {
; CHECK-LABEL: test_loop_alignment:
; CHECK: mov{{.*}}, #0
; CHECK: .p2align 2
@@ -12,11 +12,11 @@ entry:
loop:
%i = phi i32 [ 0, %entry ], [ %i.next, %loop ]
- %in.addr = getelementptr inbounds i32, i32* %in, i32 %i
- %lhs = load i32, i32* %in.addr, align 4
+ %in.addr = getelementptr inbounds i32, ptr %in, i32 %i
+ %lhs = load i32, ptr %in.addr, align 4
%res = mul nsw i32 %lhs, 5
- %out.addr = getelementptr inbounds i32, i32* %out, i32 %i
- store i32 %res, i32* %out.addr, align 4
+ %out.addr = getelementptr inbounds i32, ptr %out, i32 %i
+ store i32 %res, ptr %out.addr, align 4
%i.next = add i32 %i, 1
%done = icmp eq i32 %i.next, 1024
br i1 %done, label %end, label %loop
@@ -25,7 +25,7 @@ end:
ret void
}
-define void @test_loop_alignment_minsize(i32* %in, i32* %out) minsize {
+define void @test_loop_alignment_minsize(ptr %in, ptr %out) minsize {
; CHECK-LABEL: test_loop_alignment_minsize:
; CHECK: movs {{r[0-9]+}}, #0
; CHECK-NOT: .p2align
@@ -35,11 +35,11 @@ entry:
loop:
%i = phi i32 [ 0, %entry ], [ %i.next, %loop ]
- %in.addr = getelementptr inbounds i32, i32* %in, i32 %i
- %lhs = load i32, i32* %in.addr, align 4
+ %in.addr = getelementptr inbounds i32, ptr %in, i32 %i
+ %lhs = load i32, ptr %in.addr, align 4
%res = mul nsw i32 %lhs, 5
- %out.addr = getelementptr inbounds i32, i32* %out, i32 %i
- store i32 %res, i32* %out.addr, align 4
+ %out.addr = getelementptr inbounds i32, ptr %out, i32 %i
+ store i32 %res, ptr %out.addr, align 4
%i.next = add i32 %i, 1
%done = icmp eq i32 %i.next, 1024
br i1 %done, label %end, label %loop
diff --git a/llvm/test/CodeGen/ARM/loop-indexing.ll b/llvm/test/CodeGen/ARM/loop-indexing.ll
index 496599f473dbc..110342c7f3ba7 100644
--- a/llvm/test/CodeGen/ARM/loop-indexing.ll
+++ b/llvm/test/CodeGen/ARM/loop-indexing.ll
@@ -37,7 +37,7 @@
; CHECK-COMPLEX: vldr s{{.*}}, #12]
; CHECK-COMPLEX: vldr s{{.*}}, #12]
-define float @test_fma(float* %a, float* %b, i32 %N) {
+define float @test_fma(ptr %a, ptr %b, i32 %N) {
entry:
br label %loop
@@ -45,17 +45,17 @@ loop:
%i = phi i32 [ 0, %entry ], [ %i.next, %loop ]
%idx.1 = phi i32 [ 0, %entry ], [ %idx.next, %loop ]
%res = phi float [ 0.0, %entry ], [ %fma.2, %loop ]
- %gep.a.1 = getelementptr inbounds float, float* %a, i32 %idx.1
- %a.1 = load float, float* %gep.a.1
- %gep.b.1 = getelementptr inbounds float, float* %b, i32 %idx.1
- %b.1 = load float, float* %gep.b.1
+ %gep.a.1 = getelementptr inbounds float, ptr %a, i32 %idx.1
+ %a.1 = load float, ptr %gep.a.1
+ %gep.b.1 = getelementptr inbounds float, ptr %b, i32 %idx.1
+ %b.1 = load float, ptr %gep.b.1
%fmul.1 = fmul float %a.1, %b.1
%fma.1 = fadd float %fmul.1, %res
%idx.2 = or i32 %idx.1, 1
- %gep.a.2 = getelementptr inbounds float, float* %a, i32 %idx.2
- %a.2 = load float, float* %gep.a.2
- %gep.b.2 = getelementptr inbounds float, float* %b, i32 %idx.2
- %b.2 = load float, float* %gep.b.2
+ %gep.a.2 = getelementptr inbounds float, ptr %a, i32 %idx.2
+ %a.2 = load float, ptr %gep.a.2
+ %gep.b.2 = getelementptr inbounds float, ptr %b, i32 %idx.2
+ %b.2 = load float, ptr %gep.b.2
%fmul.2 = fmul float %a.2, %b.2
%fma.2 = fadd float %fmul.2, %fma.1
%i.next = add nsw nuw i32 %i, -2
@@ -78,9 +78,9 @@ exit:
; DISABLED-NOT: ldr{{.*}}]!
; DISABLED-NOT: str{{.*}}]!
-define void @convolve_16bit(i16** nocapture readonly %input_image, i16** nocapture readonly %filter,
+define void @convolve_16bit(ptr nocapture readonly %input_image, ptr nocapture readonly %filter,
i32 %filter_dim, i32 %out_width, i32 %out_height,
- i32** nocapture readonly %convolved) {
+ ptr nocapture readonly %convolved) {
entry:
%cmp92 = icmp eq i32 %out_height, 0
br i1 %cmp92, label %for.cond.cleanup, label %for.cond1.preheader.lr.ph
@@ -92,8 +92,8 @@ for.cond1.preheader.lr.ph: ; preds = %entry
for.cond1.preheader: ; preds = %for.cond.cleanup3, %for.cond1.preheader.lr.ph
%res_y.093 = phi i32 [ 0, %for.cond1.preheader.lr.ph ], [ %add28, %for.cond.cleanup3 ]
- %arrayidx22 = getelementptr inbounds i32*, i32** %convolved, i32 %res_y.093
- %tmp3 = load i32*, i32** %arrayidx22, align 4
+ %arrayidx22 = getelementptr inbounds ptr, ptr %convolved, i32 %res_y.093
+ %tmp3 = load ptr, ptr %arrayidx22, align 4
br label %for.cond9.preheader.us.us.preheader
for.cond9.preheader.us.us.preheader: ; preds = %for.cond5.for.cond.cleanup7_crit_edge.us, %for.cond5.preheader.lr.ph
@@ -104,10 +104,10 @@ for.cond9.preheader.us.us: ; preds = %for.cond9.for.cond.
%filter_y.056.us.us = phi i32 [ %inc20.us.us, %for.cond9.for.cond.cleanup11_crit_edge.us.us.unr-lcssa ], [ 0, %for.cond9.preheader.us.us.preheader ]
%result_element.055.us.us = phi i32 [ %add18.us.us.3, %for.cond9.for.cond.cleanup11_crit_edge.us.us.unr-lcssa ], [ 0, %for.cond9.preheader.us.us.preheader ]
%add.us.us = add i32 %filter_y.056.us.us, %res_y.093
- %arrayidx.us.us = getelementptr inbounds i16*, i16** %filter, i32 %filter_y.056.us.us
- %tmp5 = load i16*, i16** %arrayidx.us.us, align 4
- %arrayidx15.us.us = getelementptr inbounds i16*, i16** %input_image, i32 %add.us.us
- %tmp6 = load i16*, i16** %arrayidx15.us.us, align 4
+ %arrayidx.us.us = getelementptr inbounds ptr, ptr %filter, i32 %filter_y.056.us.us
+ %tmp5 = load ptr, ptr %arrayidx.us.us, align 4
+ %arrayidx15.us.us = getelementptr inbounds ptr, ptr %input_image, i32 %add.us.us
+ %tmp6 = load ptr, ptr %arrayidx15.us.us, align 4
br label %for.body12.us.us
for.body12.us.us: ; preds = %for.body12.us.us, %for.cond9.preheader.us.us
@@ -115,41 +115,41 @@ for.body12.us.us: ; preds = %for.body12.us.us, %
%result_element.152.us.us = phi i32 [ %add18.us.us.3, %for.body12.us.us ], [ %result_element.055.us.us, %for.cond9.preheader.us.us ]
%niter = phi i32 [ %niter.nsub.3, %for.body12.us.us ], [ %unroll_iter, %for.cond9.preheader.us.us ]
%add13.us.us = add i32 %filter_x.053.us.us, %res_x.060.us
- %arrayidx14.us.us = getelementptr inbounds i16, i16* %tmp5, i32 %filter_x.053.us.us
- %tmp9 = load i16, i16* %arrayidx14.us.us, align 2
+ %arrayidx14.us.us = getelementptr inbounds i16, ptr %tmp5, i32 %filter_x.053.us.us
+ %tmp9 = load i16, ptr %arrayidx14.us.us, align 2
%conv.us.us = sext i16 %tmp9 to i32
- %arrayidx16.us.us = getelementptr inbounds i16, i16* %tmp6, i32 %add13.us.us
- %tmp10 = load i16, i16* %arrayidx16.us.us, align 2
+ %arrayidx16.us.us = getelementptr inbounds i16, ptr %tmp6, i32 %add13.us.us
+ %tmp10 = load i16, ptr %arrayidx16.us.us, align 2
%conv17.us.us = sext i16 %tmp10 to i32
%mul.us.us = mul nsw i32 %conv17.us.us, %conv.us.us
%add18.us.us = add nsw i32 %mul.us.us, %result_element.152.us.us
%inc.us.us = or i32 %filter_x.053.us.us, 1
%add13.us.us.1 = add i32 %inc.us.us, %res_x.060.us
- %arrayidx14.us.us.1 = getelementptr inbounds i16, i16* %tmp5, i32 %inc.us.us
- %tmp11 = load i16, i16* %arrayidx14.us.us.1, align 2
+ %arrayidx14.us.us.1 = getelementptr inbounds i16, ptr %tmp5, i32 %inc.us.us
+ %tmp11 = load i16, ptr %arrayidx14.us.us.1, align 2
%conv.us.us.1 = sext i16 %tmp11 to i32
- %arrayidx16.us.us.1 = getelementptr inbounds i16, i16* %tmp6, i32 %add13.us.us.1
- %tmp12 = load i16, i16* %arrayidx16.us.us.1, align 2
+ %arrayidx16.us.us.1 = getelementptr inbounds i16, ptr %tmp6, i32 %add13.us.us.1
+ %tmp12 = load i16, ptr %arrayidx16.us.us.1, align 2
%conv17.us.us.1 = sext i16 %tmp12 to i32
%mul.us.us.1 = mul nsw i32 %conv17.us.us.1, %conv.us.us.1
%add18.us.us.1 = add nsw i32 %mul.us.us.1, %add18.us.us
%inc.us.us.1 = or i32 %filter_x.053.us.us, 2
%add13.us.us.2 = add i32 %inc.us.us.1, %res_x.060.us
- %arrayidx14.us.us.2 = getelementptr inbounds i16, i16* %tmp5, i32 %inc.us.us.1
- %tmp13 = load i16, i16* %arrayidx14.us.us.2, align 2
+ %arrayidx14.us.us.2 = getelementptr inbounds i16, ptr %tmp5, i32 %inc.us.us.1
+ %tmp13 = load i16, ptr %arrayidx14.us.us.2, align 2
%conv.us.us.2 = sext i16 %tmp13 to i32
- %arrayidx16.us.us.2 = getelementptr inbounds i16, i16* %tmp6, i32 %add13.us.us.2
- %tmp14 = load i16, i16* %arrayidx16.us.us.2, align 2
+ %arrayidx16.us.us.2 = getelementptr inbounds i16, ptr %tmp6, i32 %add13.us.us.2
+ %tmp14 = load i16, ptr %arrayidx16.us.us.2, align 2
%conv17.us.us.2 = sext i16 %tmp14 to i32
%mul.us.us.2 = mul nsw i32 %conv17.us.us.2, %conv.us.us.2
%add18.us.us.2 = add nsw i32 %mul.us.us.2, %add18.us.us.1
%inc.us.us.2 = or i32 %filter_x.053.us.us, 3
%add13.us.us.3 = add i32 %inc.us.us.2, %res_x.060.us
- %arrayidx14.us.us.3 = getelementptr inbounds i16, i16* %tmp5, i32 %inc.us.us.2
- %tmp15 = load i16, i16* %arrayidx14.us.us.3, align 2
+ %arrayidx14.us.us.3 = getelementptr inbounds i16, ptr %tmp5, i32 %inc.us.us.2
+ %tmp15 = load i16, ptr %arrayidx14.us.us.3, align 2
%conv.us.us.3 = sext i16 %tmp15 to i32
- %arrayidx16.us.us.3 = getelementptr inbounds i16, i16* %tmp6, i32 %add13.us.us.3
- %tmp16 = load i16, i16* %arrayidx16.us.us.3, align 2
+ %arrayidx16.us.us.3 = getelementptr inbounds i16, ptr %tmp6, i32 %add13.us.us.3
+ %tmp16 = load i16, ptr %arrayidx16.us.us.3, align 2
%conv17.us.us.3 = sext i16 %tmp16 to i32
%mul.us.us.3 = mul nsw i32 %conv17.us.us.3, %conv.us.us.3
%add18.us.us.3 = add nsw i32 %mul.us.us.3, %add18.us.us.2
@@ -164,8 +164,8 @@ for.cond9.for.cond.cleanup11_crit_edge.us.us.unr-lcssa: ; preds = %for.body12.us
br i1 %exitcond98, label %for.cond5.for.cond.cleanup7_crit_edge.us, label %for.cond9.preheader.us.us
for.cond5.for.cond.cleanup7_crit_edge.us: ; preds = %for.cond9.for.cond.cleanup11_crit_edge.us.us
- %arrayidx23.us = getelementptr inbounds i32, i32* %tmp3, i32 %res_x.060.us
- store i32 %add18.us.us.3, i32* %arrayidx23.us, align 4
+ %arrayidx23.us = getelementptr inbounds i32, ptr %tmp3, i32 %res_x.060.us
+ store i32 %add18.us.us.3, ptr %arrayidx23.us, align 4
%add25.us = add nuw i32 %res_x.060.us, 1
%exitcond99 = icmp eq i32 %add25.us, %out_width
br i1 %exitcond99, label %for.cond.cleanup3, label %for.cond9.preheader.us.us.preheader
@@ -198,7 +198,7 @@ for.cond.cleanup: ; preds = %for.cond.cleanup3,
; CHECK-T2: ldrb{{.*}}, #1]!
; CHECK-T2: str{{.*}}, #4]!
-define void @mul_8x8(i8* nocapture readonly %A, i8* nocapture readonly %B, i32* nocapture %C, i32 %N) {
+define void @mul_8x8(ptr nocapture readonly %A, ptr nocapture readonly %B, ptr nocapture %C, i32 %N) {
entry:
%cmp9 = icmp eq i32 %N, 0
br i1 %cmp9, label %for.cond.cleanup, label %for.body.preheader
@@ -221,15 +221,15 @@ for.cond.cleanup.loopexit.unr-lcssa: ; preds = %for.body, %for.body
for.body.epil: ; preds = %for.body.epil, %for.cond.cleanup.loopexit.unr-lcssa
%i.010.epil = phi i32 [ %inc.epil, %for.body.epil ], [ %i.010.unr, %for.cond.cleanup.loopexit.unr-lcssa ]
%epil.iter = phi i32 [ %epil.iter.sub, %for.body.epil ], [ %xtraiter, %for.cond.cleanup.loopexit.unr-lcssa ]
- %arrayidx.epil = getelementptr inbounds i8, i8* %A, i32 %i.010.epil
- %tmp2 = load i8, i8* %arrayidx.epil, align 1
+ %arrayidx.epil = getelementptr inbounds i8, ptr %A, i32 %i.010.epil
+ %tmp2 = load i8, ptr %arrayidx.epil, align 1
%conv.epil = zext i8 %tmp2 to i32
- %arrayidx1.epil = getelementptr inbounds i8, i8* %B, i32 %i.010.epil
- %tmp3 = load i8, i8* %arrayidx1.epil, align 1
+ %arrayidx1.epil = getelementptr inbounds i8, ptr %B, i32 %i.010.epil
+ %tmp3 = load i8, ptr %arrayidx1.epil, align 1
%conv2.epil = zext i8 %tmp3 to i32
%mul.epil = mul nuw nsw i32 %conv2.epil, %conv.epil
- %arrayidx3.epil = getelementptr inbounds i32, i32* %C, i32 %i.010.epil
- store i32 %mul.epil, i32* %arrayidx3.epil, align 4
+ %arrayidx3.epil = getelementptr inbounds i32, ptr %C, i32 %i.010.epil
+ store i32 %mul.epil, ptr %arrayidx3.epil, align 4
%inc.epil = add nuw i32 %i.010.epil, 1
%epil.iter.sub = add i32 %epil.iter, -1
%epil.iter.cmp = icmp eq i32 %epil.iter.sub, 0
@@ -241,45 +241,45 @@ for.cond.cleanup: ; preds = %for.body.epil, %for
for.body: ; preds = %for.body, %for.body.preheader.new
%i.010 = phi i32 [ 0, %for.body.preheader.new ], [ %inc.3, %for.body ]
%niter = phi i32 [ %unroll_iter, %for.body.preheader.new ], [ %niter.nsub.3, %for.body ]
- %arrayidx = getelementptr inbounds i8, i8* %A, i32 %i.010
- %tmp4 = load i8, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds i8, ptr %A, i32 %i.010
+ %tmp4 = load i8, ptr %arrayidx, align 1
%conv = zext i8 %tmp4 to i32
- %arrayidx1 = getelementptr inbounds i8, i8* %B, i32 %i.010
- %tmp5 = load i8, i8* %arrayidx1, align 1
+ %arrayidx1 = getelementptr inbounds i8, ptr %B, i32 %i.010
+ %tmp5 = load i8, ptr %arrayidx1, align 1
%conv2 = zext i8 %tmp5 to i32
%mul = mul nuw nsw i32 %conv2, %conv
- %arrayidx3 = getelementptr inbounds i32, i32* %C, i32 %i.010
- store i32 %mul, i32* %arrayidx3, align 4
+ %arrayidx3 = getelementptr inbounds i32, ptr %C, i32 %i.010
+ store i32 %mul, ptr %arrayidx3, align 4
%inc = or i32 %i.010, 1
- %arrayidx.1 = getelementptr inbounds i8, i8* %A, i32 %inc
- %tmp6 = load i8, i8* %arrayidx.1, align 1
+ %arrayidx.1 = getelementptr inbounds i8, ptr %A, i32 %inc
+ %tmp6 = load i8, ptr %arrayidx.1, align 1
%conv.1 = zext i8 %tmp6 to i32
- %arrayidx1.1 = getelementptr inbounds i8, i8* %B, i32 %inc
- %tmp7 = load i8, i8* %arrayidx1.1, align 1
+ %arrayidx1.1 = getelementptr inbounds i8, ptr %B, i32 %inc
+ %tmp7 = load i8, ptr %arrayidx1.1, align 1
%conv2.1 = zext i8 %tmp7 to i32
%mul.1 = mul nuw nsw i32 %conv2.1, %conv.1
- %arrayidx3.1 = getelementptr inbounds i32, i32* %C, i32 %inc
- store i32 %mul.1, i32* %arrayidx3.1, align 4
+ %arrayidx3.1 = getelementptr inbounds i32, ptr %C, i32 %inc
+ store i32 %mul.1, ptr %arrayidx3.1, align 4
%inc.1 = or i32 %i.010, 2
- %arrayidx.2 = getelementptr inbounds i8, i8* %A, i32 %inc.1
- %tmp8 = load i8, i8* %arrayidx.2, align 1
+ %arrayidx.2 = getelementptr inbounds i8, ptr %A, i32 %inc.1
+ %tmp8 = load i8, ptr %arrayidx.2, align 1
%conv.2 = zext i8 %tmp8 to i32
- %arrayidx1.2 = getelementptr inbounds i8, i8* %B, i32 %inc.1
- %tmp9 = load i8, i8* %arrayidx1.2, align 1
+ %arrayidx1.2 = getelementptr inbounds i8, ptr %B, i32 %inc.1
+ %tmp9 = load i8, ptr %arrayidx1.2, align 1
%conv2.2 = zext i8 %tmp9 to i32
%mul.2 = mul nuw nsw i32 %conv2.2, %conv.2
- %arrayidx3.2 = getelementptr inbounds i32, i32* %C, i32 %inc.1
- store i32 %mul.2, i32* %arrayidx3.2, align 4
+ %arrayidx3.2 = getelementptr inbounds i32, ptr %C, i32 %inc.1
+ store i32 %mul.2, ptr %arrayidx3.2, align 4
%inc.2 = or i32 %i.010, 3
- %arrayidx.3 = getelementptr inbounds i8, i8* %A, i32 %inc.2
- %tmp10 = load i8, i8* %arrayidx.3, align 1
+ %arrayidx.3 = getelementptr inbounds i8, ptr %A, i32 %inc.2
+ %tmp10 = load i8, ptr %arrayidx.3, align 1
%conv.3 = zext i8 %tmp10 to i32
- %arrayidx1.3 = getelementptr inbounds i8, i8* %B, i32 %inc.2
- %tmp11 = load i8, i8* %arrayidx1.3, align 1
+ %arrayidx1.3 = getelementptr inbounds i8, ptr %B, i32 %inc.2
+ %tmp11 = load i8, ptr %arrayidx1.3, align 1
%conv2.3 = zext i8 %tmp11 to i32
%mul.3 = mul nuw nsw i32 %conv2.3, %conv.3
- %arrayidx3.3 = getelementptr inbounds i32, i32* %C, i32 %inc.2
- store i32 %mul.3, i32* %arrayidx3.3, align 4
+ %arrayidx3.3 = getelementptr inbounds i32, ptr %C, i32 %inc.2
+ store i32 %mul.3, ptr %arrayidx3.3, align 4
%inc.3 = add i32 %i.010, 4
%niter.nsub.3 = add i32 %niter, -4
%niter.ncmp.3 = icmp eq i32 %niter.nsub.3, 0
@@ -304,7 +304,7 @@ for.body: ; preds = %for.body, %for.body
; CHECK-T2: ldrb{{.*}}, #1]!
; CHECK-T2: str{{.*}}, #4]!
-define void @mul_16x8(i16* nocapture readonly %A, i8* nocapture readonly %B, i32* nocapture %C, i32 %N) {
+define void @mul_16x8(ptr nocapture readonly %A, ptr nocapture readonly %B, ptr nocapture %C, i32 %N) {
entry:
%cmp9 = icmp eq i32 %N, 0
br i1 %cmp9, label %for.cond.cleanup, label %for.body.preheader
@@ -327,15 +327,15 @@ for.cond.cleanup.loopexit.unr-lcssa: ; preds = %for.body, %for.body
for.body.epil: ; preds = %for.body.epil, %for.cond.cleanup.loopexit.unr-lcssa
%i.010.epil = phi i32 [ %inc.epil, %for.body.epil ], [ %i.010.unr, %for.cond.cleanup.loopexit.unr-lcssa ]
%epil.iter = phi i32 [ %epil.iter.sub, %for.body.epil ], [ %xtraiter, %for.cond.cleanup.loopexit.unr-lcssa ]
- %arrayidx.epil = getelementptr inbounds i16, i16* %A, i32 %i.010.epil
- %tmp2 = load i16, i16* %arrayidx.epil, align 2
+ %arrayidx.epil = getelementptr inbounds i16, ptr %A, i32 %i.010.epil
+ %tmp2 = load i16, ptr %arrayidx.epil, align 2
%conv.epil = sext i16 %tmp2 to i32
- %arrayidx1.epil = getelementptr inbounds i8, i8* %B, i32 %i.010.epil
- %tmp3 = load i8, i8* %arrayidx1.epil, align 1
+ %arrayidx1.epil = getelementptr inbounds i8, ptr %B, i32 %i.010.epil
+ %tmp3 = load i8, ptr %arrayidx1.epil, align 1
%conv2.epil = zext i8 %tmp3 to i32
%mul.epil = mul nsw i32 %conv2.epil, %conv.epil
- %arrayidx3.epil = getelementptr inbounds i32, i32* %C, i32 %i.010.epil
- store i32 %mul.epil, i32* %arrayidx3.epil, align 4
+ %arrayidx3.epil = getelementptr inbounds i32, ptr %C, i32 %i.010.epil
+ store i32 %mul.epil, ptr %arrayidx3.epil, align 4
%inc.epil = add nuw i32 %i.010.epil, 1
%epil.iter.sub = add i32 %epil.iter, -1
%epil.iter.cmp = icmp eq i32 %epil.iter.sub, 0
@@ -347,45 +347,45 @@ for.cond.cleanup: ; preds = %for.body.epil, %for
for.body: ; preds = %for.body, %for.body.preheader.new
%i.010 = phi i32 [ 0, %for.body.preheader.new ], [ %inc.3, %for.body ]
%niter = phi i32 [ %unroll_iter, %for.body.preheader.new ], [ %niter.nsub.3, %for.body ]
- %arrayidx = getelementptr inbounds i16, i16* %A, i32 %i.010
- %tmp4 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %A, i32 %i.010
+ %tmp4 = load i16, ptr %arrayidx, align 2
%conv = sext i16 %tmp4 to i32
- %arrayidx1 = getelementptr inbounds i8, i8* %B, i32 %i.010
- %tmp5 = load i8, i8* %arrayidx1, align 1
+ %arrayidx1 = getelementptr inbounds i8, ptr %B, i32 %i.010
+ %tmp5 = load i8, ptr %arrayidx1, align 1
%conv2 = zext i8 %tmp5 to i32
%mul = mul nsw i32 %conv2, %conv
- %arrayidx3 = getelementptr inbounds i32, i32* %C, i32 %i.010
- store i32 %mul, i32* %arrayidx3, align 4
+ %arrayidx3 = getelementptr inbounds i32, ptr %C, i32 %i.010
+ store i32 %mul, ptr %arrayidx3, align 4
%inc = or i32 %i.010, 1
- %arrayidx.1 = getelementptr inbounds i16, i16* %A, i32 %inc
- %tmp6 = load i16, i16* %arrayidx.1, align 2
+ %arrayidx.1 = getelementptr inbounds i16, ptr %A, i32 %inc
+ %tmp6 = load i16, ptr %arrayidx.1, align 2
%conv.1 = sext i16 %tmp6 to i32
- %arrayidx1.1 = getelementptr inbounds i8, i8* %B, i32 %inc
- %tmp7 = load i8, i8* %arrayidx1.1, align 1
+ %arrayidx1.1 = getelementptr inbounds i8, ptr %B, i32 %inc
+ %tmp7 = load i8, ptr %arrayidx1.1, align 1
%conv2.1 = zext i8 %tmp7 to i32
%mul.1 = mul nsw i32 %conv2.1, %conv.1
- %arrayidx3.1 = getelementptr inbounds i32, i32* %C, i32 %inc
- store i32 %mul.1, i32* %arrayidx3.1, align 4
+ %arrayidx3.1 = getelementptr inbounds i32, ptr %C, i32 %inc
+ store i32 %mul.1, ptr %arrayidx3.1, align 4
%inc.1 = or i32 %i.010, 2
- %arrayidx.2 = getelementptr inbounds i16, i16* %A, i32 %inc.1
- %tmp8 = load i16, i16* %arrayidx.2, align 2
+ %arrayidx.2 = getelementptr inbounds i16, ptr %A, i32 %inc.1
+ %tmp8 = load i16, ptr %arrayidx.2, align 2
%conv.2 = sext i16 %tmp8 to i32
- %arrayidx1.2 = getelementptr inbounds i8, i8* %B, i32 %inc.1
- %tmp9 = load i8, i8* %arrayidx1.2, align 1
+ %arrayidx1.2 = getelementptr inbounds i8, ptr %B, i32 %inc.1
+ %tmp9 = load i8, ptr %arrayidx1.2, align 1
%conv2.2 = zext i8 %tmp9 to i32
%mul.2 = mul nsw i32 %conv2.2, %conv.2
- %arrayidx3.2 = getelementptr inbounds i32, i32* %C, i32 %inc.1
- store i32 %mul.2, i32* %arrayidx3.2, align 4
+ %arrayidx3.2 = getelementptr inbounds i32, ptr %C, i32 %inc.1
+ store i32 %mul.2, ptr %arrayidx3.2, align 4
%inc.2 = or i32 %i.010, 3
- %arrayidx.3 = getelementptr inbounds i16, i16* %A, i32 %inc.2
- %tmp10 = load i16, i16* %arrayidx.3, align 2
+ %arrayidx.3 = getelementptr inbounds i16, ptr %A, i32 %inc.2
+ %tmp10 = load i16, ptr %arrayidx.3, align 2
%conv.3 = sext i16 %tmp10 to i32
- %arrayidx1.3 = getelementptr inbounds i8, i8* %B, i32 %inc.2
- %tmp11 = load i8, i8* %arrayidx1.3, align 1
+ %arrayidx1.3 = getelementptr inbounds i8, ptr %B, i32 %inc.2
+ %tmp11 = load i8, ptr %arrayidx1.3, align 1
%conv2.3 = zext i8 %tmp11 to i32
%mul.3 = mul nsw i32 %conv2.3, %conv.3
- %arrayidx3.3 = getelementptr inbounds i32, i32* %C, i32 %inc.2
- store i32 %mul.3, i32* %arrayidx3.3, align 4
+ %arrayidx3.3 = getelementptr inbounds i32, ptr %C, i32 %inc.2
+ store i32 %mul.3, ptr %arrayidx3.3, align 4
%inc.3 = add i32 %i.010, 4
%niter.nsub.3 = add i32 %niter, -4
%niter.ncmp.3 = icmp eq i32 %niter.nsub.3, 0
@@ -412,7 +412,7 @@ for.body: ; preds = %for.body, %for.body
; CHECK-T2: ldrsh{{.*}}, #2]!
; CHECK-T2: str{{.*}}, #4]!
-define void @mul_16x16(i16* nocapture readonly %A, i16* nocapture readonly %B, i32* nocapture %C, i32 %N) {
+define void @mul_16x16(ptr nocapture readonly %A, ptr nocapture readonly %B, ptr nocapture %C, i32 %N) {
entry:
%cmp9 = icmp eq i32 %N, 0
br i1 %cmp9, label %for.cond.cleanup, label %for.body.preheader
@@ -435,15 +435,15 @@ for.cond.cleanup.loopexit.unr-lcssa: ; preds = %for.body, %for.body
for.body.epil: ; preds = %for.body.epil, %for.cond.cleanup.loopexit.unr-lcssa
%i.010.epil = phi i32 [ %inc.epil, %for.body.epil ], [ %i.010.unr, %for.cond.cleanup.loopexit.unr-lcssa ]
%epil.iter = phi i32 [ %epil.iter.sub, %for.body.epil ], [ %xtraiter, %for.cond.cleanup.loopexit.unr-lcssa ]
- %arrayidx.epil = getelementptr inbounds i16, i16* %A, i32 %i.010.epil
- %tmp2 = load i16, i16* %arrayidx.epil, align 2
+ %arrayidx.epil = getelementptr inbounds i16, ptr %A, i32 %i.010.epil
+ %tmp2 = load i16, ptr %arrayidx.epil, align 2
%conv.epil = sext i16 %tmp2 to i32
- %arrayidx1.epil = getelementptr inbounds i16, i16* %B, i32 %i.010.epil
- %tmp3 = load i16, i16* %arrayidx1.epil, align 2
+ %arrayidx1.epil = getelementptr inbounds i16, ptr %B, i32 %i.010.epil
+ %tmp3 = load i16, ptr %arrayidx1.epil, align 2
%conv2.epil = sext i16 %tmp3 to i32
%mul.epil = mul nsw i32 %conv2.epil, %conv.epil
- %arrayidx3.epil = getelementptr inbounds i32, i32* %C, i32 %i.010.epil
- store i32 %mul.epil, i32* %arrayidx3.epil, align 4
+ %arrayidx3.epil = getelementptr inbounds i32, ptr %C, i32 %i.010.epil
+ store i32 %mul.epil, ptr %arrayidx3.epil, align 4
%inc.epil = add nuw i32 %i.010.epil, 1
%epil.iter.sub = add i32 %epil.iter, -1
%epil.iter.cmp = icmp eq i32 %epil.iter.sub, 0
@@ -455,45 +455,45 @@ for.cond.cleanup: ; preds = %for.body.epil, %for
for.body: ; preds = %for.body, %for.body.preheader.new
%i.010 = phi i32 [ 0, %for.body.preheader.new ], [ %inc.3, %for.body ]
%niter = phi i32 [ %unroll_iter, %for.body.preheader.new ], [ %niter.nsub.3, %for.body ]
- %arrayidx = getelementptr inbounds i16, i16* %A, i32 %i.010
- %tmp4 = load i16, i16* %arrayidx, align 2
+ %arrayidx = getelementptr inbounds i16, ptr %A, i32 %i.010
+ %tmp4 = load i16, ptr %arrayidx, align 2
%conv = sext i16 %tmp4 to i32
- %arrayidx1 = getelementptr inbounds i16, i16* %B, i32 %i.010
- %tmp5 = load i16, i16* %arrayidx1, align 2
+ %arrayidx1 = getelementptr inbounds i16, ptr %B, i32 %i.010
+ %tmp5 = load i16, ptr %arrayidx1, align 2
%conv2 = sext i16 %tmp5 to i32
%mul = mul nsw i32 %conv2, %conv
- %arrayidx3 = getelementptr inbounds i32, i32* %C, i32 %i.010
- store i32 %mul, i32* %arrayidx3, align 4
+ %arrayidx3 = getelementptr inbounds i32, ptr %C, i32 %i.010
+ store i32 %mul, ptr %arrayidx3, align 4
%inc = or i32 %i.010, 1
- %arrayidx.1 = getelementptr inbounds i16, i16* %A, i32 %inc
- %tmp6 = load i16, i16* %arrayidx.1, align 2
+ %arrayidx.1 = getelementptr inbounds i16, ptr %A, i32 %inc
+ %tmp6 = load i16, ptr %arrayidx.1, align 2
%conv.1 = sext i16 %tmp6 to i32
- %arrayidx1.1 = getelementptr inbounds i16, i16* %B, i32 %inc
- %tmp7 = load i16, i16* %arrayidx1.1, align 2
+ %arrayidx1.1 = getelementptr inbounds i16, ptr %B, i32 %inc
+ %tmp7 = load i16, ptr %arrayidx1.1, align 2
%conv2.1 = sext i16 %tmp7 to i32
%mul.1 = mul nsw i32 %conv2.1, %conv.1
- %arrayidx3.1 = getelementptr inbounds i32, i32* %C, i32 %inc
- store i32 %mul.1, i32* %arrayidx3.1, align 4
+ %arrayidx3.1 = getelementptr inbounds i32, ptr %C, i32 %inc
+ store i32 %mul.1, ptr %arrayidx3.1, align 4
%inc.1 = or i32 %i.010, 2
- %arrayidx.2 = getelementptr inbounds i16, i16* %A, i32 %inc.1
- %tmp8 = load i16, i16* %arrayidx.2, align 2
+ %arrayidx.2 = getelementptr inbounds i16, ptr %A, i32 %inc.1
+ %tmp8 = load i16, ptr %arrayidx.2, align 2
%conv.2 = sext i16 %tmp8 to i32
- %arrayidx1.2 = getelementptr inbounds i16, i16* %B, i32 %inc.1
- %tmp9 = load i16, i16* %arrayidx1.2, align 2
+ %arrayidx1.2 = getelementptr inbounds i16, ptr %B, i32 %inc.1
+ %tmp9 = load i16, ptr %arrayidx1.2, align 2
%conv2.2 = sext i16 %tmp9 to i32
%mul.2 = mul nsw i32 %conv2.2, %conv.2
- %arrayidx3.2 = getelementptr inbounds i32, i32* %C, i32 %inc.1
- store i32 %mul.2, i32* %arrayidx3.2, align 4
+ %arrayidx3.2 = getelementptr inbounds i32, ptr %C, i32 %inc.1
+ store i32 %mul.2, ptr %arrayidx3.2, align 4
%inc.2 = or i32 %i.010, 3
- %arrayidx.3 = getelementptr inbounds i16, i16* %A, i32 %inc.2
- %tmp10 = load i16, i16* %arrayidx.3, align 2
+ %arrayidx.3 = getelementptr inbounds i16, ptr %A, i32 %inc.2
+ %tmp10 = load i16, ptr %arrayidx.3, align 2
%conv.3 = sext i16 %tmp10 to i32
- %arrayidx1.3 = getelementptr inbounds i16, i16* %B, i32 %inc.2
- %tmp11 = load i16, i16* %arrayidx1.3, align 2
+ %arrayidx1.3 = getelementptr inbounds i16, ptr %B, i32 %inc.2
+ %tmp11 = load i16, ptr %arrayidx1.3, align 2
%conv2.3 = sext i16 %tmp11 to i32
%mul.3 = mul nsw i32 %conv2.3, %conv.3
- %arrayidx3.3 = getelementptr inbounds i32, i32* %C, i32 %inc.2
- store i32 %mul.3, i32* %arrayidx3.3, align 4
+ %arrayidx3.3 = getelementptr inbounds i32, ptr %C, i32 %inc.2
+ store i32 %mul.3, ptr %arrayidx3.3, align 4
%inc.3 = add i32 %i.010, 4
%niter.nsub.3 = add i32 %niter, -4
%niter.ncmp.3 = icmp eq i32 %niter.nsub.3, 0
@@ -513,7 +513,7 @@ for.body: ; preds = %for.body, %for.body
; CHECK-T2: ldrb{{.*}}, #1]!
; CHECK-T2: ldr{{.*}}, #4]!
-define void @mul_8x8_2d(i8* nocapture readonly %A, i8** nocapture readonly %B, i32** nocapture readonly %C, i32 %N, i32 %M) {
+define void @mul_8x8_2d(ptr nocapture readonly %A, ptr nocapture readonly %B, ptr nocapture readonly %C, i32 %N, i32 %M) {
entry:
%cmp24 = icmp eq i32 %N, 0
%cmp222 = icmp eq i32 %M, 0
@@ -530,59 +530,59 @@ for.cond1.preheader.us.preheader: ; preds = %entry
for.cond1.preheader.us: ; preds = %for.cond1.for.cond.cleanup3_crit_edge.us, %for.cond1.preheader.us.preheader
%i.025.us = phi i32 [ %inc11.us, %for.cond1.for.cond.cleanup3_crit_edge.us ], [ 0, %for.cond1.preheader.us.preheader ]
- %arrayidx.us = getelementptr inbounds i8, i8* %A, i32 %i.025.us
- %arrayidx5.us = getelementptr inbounds i8*, i8** %B, i32 %i.025.us
- %arrayidx8.us = getelementptr inbounds i32*, i32** %C, i32 %i.025.us
- %.pre = load i8*, i8** %arrayidx5.us, align 4
- %.pre30 = load i32*, i32** %arrayidx8.us, align 4
+ %arrayidx.us = getelementptr inbounds i8, ptr %A, i32 %i.025.us
+ %arrayidx5.us = getelementptr inbounds ptr, ptr %B, i32 %i.025.us
+ %arrayidx8.us = getelementptr inbounds ptr, ptr %C, i32 %i.025.us
+ %.pre = load ptr, ptr %arrayidx5.us, align 4
+ %.pre30 = load ptr, ptr %arrayidx8.us, align 4
br i1 %tmp1, label %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa, label %for.body4.us
for.body4.us: ; preds = %for.body4.us, %for.cond1.preheader.us
%j.023.us = phi i32 [ %inc.us.3, %for.body4.us ], [ 0, %for.cond1.preheader.us ]
%niter = phi i32 [ %niter.nsub.3, %for.body4.us ], [ %unroll_iter, %for.cond1.preheader.us ]
- %tmp2 = load i8, i8* %arrayidx.us, align 1
+ %tmp2 = load i8, ptr %arrayidx.us, align 1
%conv.us = zext i8 %tmp2 to i32
- %arrayidx6.us = getelementptr inbounds i8, i8* %.pre, i32 %j.023.us
- %tmp3 = load i8, i8* %arrayidx6.us, align 1
+ %arrayidx6.us = getelementptr inbounds i8, ptr %.pre, i32 %j.023.us
+ %tmp3 = load i8, ptr %arrayidx6.us, align 1
%conv7.us = zext i8 %tmp3 to i32
%mul.us = mul nuw nsw i32 %conv7.us, %conv.us
- %arrayidx9.us = getelementptr inbounds i32, i32* %.pre30, i32 %j.023.us
- %tmp4 = load i32, i32* %arrayidx9.us, align 4
+ %arrayidx9.us = getelementptr inbounds i32, ptr %.pre30, i32 %j.023.us
+ %tmp4 = load i32, ptr %arrayidx9.us, align 4
%add.us = add nsw i32 %tmp4, %mul.us
- store i32 %add.us, i32* %arrayidx9.us, align 4
+ store i32 %add.us, ptr %arrayidx9.us, align 4
%inc.us = or i32 %j.023.us, 1
- %tmp5 = load i8, i8* %arrayidx.us, align 1
+ %tmp5 = load i8, ptr %arrayidx.us, align 1
%conv.us.1 = zext i8 %tmp5 to i32
- %arrayidx6.us.1 = getelementptr inbounds i8, i8* %.pre, i32 %inc.us
- %tmp6 = load i8, i8* %arrayidx6.us.1, align 1
+ %arrayidx6.us.1 = getelementptr inbounds i8, ptr %.pre, i32 %inc.us
+ %tmp6 = load i8, ptr %arrayidx6.us.1, align 1
%conv7.us.1 = zext i8 %tmp6 to i32
%mul.us.1 = mul nuw nsw i32 %conv7.us.1, %conv.us.1
- %arrayidx9.us.1 = getelementptr inbounds i32, i32* %.pre30, i32 %inc.us
- %tmp7 = load i32, i32* %arrayidx9.us.1, align 4
+ %arrayidx9.us.1 = getelementptr inbounds i32, ptr %.pre30, i32 %inc.us
+ %tmp7 = load i32, ptr %arrayidx9.us.1, align 4
%add.us.1 = add nsw i32 %tmp7, %mul.us.1
- store i32 %add.us.1, i32* %arrayidx9.us.1, align 4
+ store i32 %add.us.1, ptr %arrayidx9.us.1, align 4
%inc.us.1 = or i32 %j.023.us, 2
- %tmp8 = load i8, i8* %arrayidx.us, align 1
+ %tmp8 = load i8, ptr %arrayidx.us, align 1
%conv.us.2 = zext i8 %tmp8 to i32
- %arrayidx6.us.2 = getelementptr inbounds i8, i8* %.pre, i32 %inc.us.1
- %tmp9 = load i8, i8* %arrayidx6.us.2, align 1
+ %arrayidx6.us.2 = getelementptr inbounds i8, ptr %.pre, i32 %inc.us.1
+ %tmp9 = load i8, ptr %arrayidx6.us.2, align 1
%conv7.us.2 = zext i8 %tmp9 to i32
%mul.us.2 = mul nuw nsw i32 %conv7.us.2, %conv.us.2
- %arrayidx9.us.2 = getelementptr inbounds i32, i32* %.pre30, i32 %inc.us.1
- %tmp10 = load i32, i32* %arrayidx9.us.2, align 4
+ %arrayidx9.us.2 = getelementptr inbounds i32, ptr %.pre30, i32 %inc.us.1
+ %tmp10 = load i32, ptr %arrayidx9.us.2, align 4
%add.us.2 = add nsw i32 %tmp10, %mul.us.2
- store i32 %add.us.2, i32* %arrayidx9.us.2, align 4
+ store i32 %add.us.2, ptr %arrayidx9.us.2, align 4
%inc.us.2 = or i32 %j.023.us, 3
- %tmp11 = load i8, i8* %arrayidx.us, align 1
+ %tmp11 = load i8, ptr %arrayidx.us, align 1
%conv.us.3 = zext i8 %tmp11 to i32
- %arrayidx6.us.3 = getelementptr inbounds i8, i8* %.pre, i32 %inc.us.2
- %tmp12 = load i8, i8* %arrayidx6.us.3, align 1
+ %arrayidx6.us.3 = getelementptr inbounds i8, ptr %.pre, i32 %inc.us.2
+ %tmp12 = load i8, ptr %arrayidx6.us.3, align 1
%conv7.us.3 = zext i8 %tmp12 to i32
%mul.us.3 = mul nuw nsw i32 %conv7.us.3, %conv.us.3
- %arrayidx9.us.3 = getelementptr inbounds i32, i32* %.pre30, i32 %inc.us.2
- %tmp13 = load i32, i32* %arrayidx9.us.3, align 4
+ %arrayidx9.us.3 = getelementptr inbounds i32, ptr %.pre30, i32 %inc.us.2
+ %tmp13 = load i32, ptr %arrayidx9.us.3, align 4
%add.us.3 = add nsw i32 %tmp13, %mul.us.3
- store i32 %add.us.3, i32* %arrayidx9.us.3, align 4
+ store i32 %add.us.3, ptr %arrayidx9.us.3, align 4
%inc.us.3 = add i32 %j.023.us, 4
%niter.nsub.3 = add i32 %niter, -4
%niter.ncmp.3 = icmp eq i32 %niter.nsub.3, 0
@@ -595,16 +595,16 @@ for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa: ; preds = %for.body4.us, %fo
for.body4.us.epil: ; preds = %for.body4.us.epil, %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa
%j.023.us.epil = phi i32 [ %inc.us.epil, %for.body4.us.epil ], [ %j.023.us.unr, %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa ]
%epil.iter = phi i32 [ %epil.iter.sub, %for.body4.us.epil ], [ %xtraiter, %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa ]
- %tmp14 = load i8, i8* %arrayidx.us, align 1
+ %tmp14 = load i8, ptr %arrayidx.us, align 1
%conv.us.epil = zext i8 %tmp14 to i32
- %arrayidx6.us.epil = getelementptr inbounds i8, i8* %.pre, i32 %j.023.us.epil
- %tmp15 = load i8, i8* %arrayidx6.us.epil, align 1
+ %arrayidx6.us.epil = getelementptr inbounds i8, ptr %.pre, i32 %j.023.us.epil
+ %tmp15 = load i8, ptr %arrayidx6.us.epil, align 1
%conv7.us.epil = zext i8 %tmp15 to i32
%mul.us.epil = mul nuw nsw i32 %conv7.us.epil, %conv.us.epil
- %arrayidx9.us.epil = getelementptr inbounds i32, i32* %.pre30, i32 %j.023.us.epil
- %tmp16 = load i32, i32* %arrayidx9.us.epil, align 4
+ %arrayidx9.us.epil = getelementptr inbounds i32, ptr %.pre30, i32 %j.023.us.epil
+ %tmp16 = load i32, ptr %arrayidx9.us.epil, align 4
%add.us.epil = add nsw i32 %tmp16, %mul.us.epil
- store i32 %add.us.epil, i32* %arrayidx9.us.epil, align 4
+ store i32 %add.us.epil, ptr %arrayidx9.us.epil, align 4
%inc.us.epil = add nuw i32 %j.023.us.epil, 1
%epil.iter.sub = add i32 %epil.iter, -1
%epil.iter.cmp = icmp eq i32 %epil.iter.sub, 0
@@ -632,7 +632,7 @@ for.cond.cleanup: ; preds = %for.cond1.for.cond.
; CHECK-T2: ldrsh{{.*}}, #2]!
; CHECK-T2: ldr{{.*}}, #4]!
-define void @mul_16x16_2d(i16* nocapture readonly %A, i16** nocapture readonly %B, i32** nocapture readonly %C, i32 %N, i32 %M) {
+define void @mul_16x16_2d(ptr nocapture readonly %A, ptr nocapture readonly %B, ptr nocapture readonly %C, i32 %N, i32 %M) {
entry:
%cmp24 = icmp eq i32 %N, 0
%cmp222 = icmp eq i32 %M, 0
@@ -649,53 +649,53 @@ for.cond1.preheader.us.preheader: ; preds = %entry
for.cond1.preheader.us: ; preds = %for.cond1.for.cond.cleanup3_crit_edge.us, %for.cond1.preheader.us.preheader
%i.025.us = phi i32 [ %inc11.us, %for.cond1.for.cond.cleanup3_crit_edge.us ], [ 0, %for.cond1.preheader.us.preheader ]
- %arrayidx.us = getelementptr inbounds i16, i16* %A, i32 %i.025.us
- %tmp2 = load i16, i16* %arrayidx.us, align 2
+ %arrayidx.us = getelementptr inbounds i16, ptr %A, i32 %i.025.us
+ %tmp2 = load i16, ptr %arrayidx.us, align 2
%conv.us = sext i16 %tmp2 to i32
- %arrayidx5.us = getelementptr inbounds i16*, i16** %B, i32 %i.025.us
- %tmp3 = load i16*, i16** %arrayidx5.us, align 4
- %arrayidx8.us = getelementptr inbounds i32*, i32** %C, i32 %i.025.us
- %tmp4 = load i32*, i32** %arrayidx8.us, align 4
+ %arrayidx5.us = getelementptr inbounds ptr, ptr %B, i32 %i.025.us
+ %tmp3 = load ptr, ptr %arrayidx5.us, align 4
+ %arrayidx8.us = getelementptr inbounds ptr, ptr %C, i32 %i.025.us
+ %tmp4 = load ptr, ptr %arrayidx8.us, align 4
br i1 %tmp1, label %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa, label %for.body4.us
for.body4.us: ; preds = %for.body4.us, %for.cond1.preheader.us
%j.023.us = phi i32 [ %inc.us.3, %for.body4.us ], [ 0, %for.cond1.preheader.us ]
%niter = phi i32 [ %niter.nsub.3, %for.body4.us ], [ %unroll_iter, %for.cond1.preheader.us ]
- %arrayidx6.us = getelementptr inbounds i16, i16* %tmp3, i32 %j.023.us
- %tmp5 = load i16, i16* %arrayidx6.us, align 2
+ %arrayidx6.us = getelementptr inbounds i16, ptr %tmp3, i32 %j.023.us
+ %tmp5 = load i16, ptr %arrayidx6.us, align 2
%conv7.us = sext i16 %tmp5 to i32
%mul.us = mul nsw i32 %conv7.us, %conv.us
- %arrayidx9.us = getelementptr inbounds i32, i32* %tmp4, i32 %j.023.us
- %tmp6 = load i32, i32* %arrayidx9.us, align 4
+ %arrayidx9.us = getelementptr inbounds i32, ptr %tmp4, i32 %j.023.us
+ %tmp6 = load i32, ptr %arrayidx9.us, align 4
%add.us = add nsw i32 %tmp6, %mul.us
- store i32 %add.us, i32* %arrayidx9.us, align 4
+ store i32 %add.us, ptr %arrayidx9.us, align 4
%inc.us = or i32 %j.023.us, 1
- %arrayidx6.us.1 = getelementptr inbounds i16, i16* %tmp3, i32 %inc.us
- %tmp7 = load i16, i16* %arrayidx6.us.1, align 2
+ %arrayidx6.us.1 = getelementptr inbounds i16, ptr %tmp3, i32 %inc.us
+ %tmp7 = load i16, ptr %arrayidx6.us.1, align 2
%conv7.us.1 = sext i16 %tmp7 to i32
%mul.us.1 = mul nsw i32 %conv7.us.1, %conv.us
- %arrayidx9.us.1 = getelementptr inbounds i32, i32* %tmp4, i32 %inc.us
- %tmp8 = load i32, i32* %arrayidx9.us.1, align 4
+ %arrayidx9.us.1 = getelementptr inbounds i32, ptr %tmp4, i32 %inc.us
+ %tmp8 = load i32, ptr %arrayidx9.us.1, align 4
%add.us.1 = add nsw i32 %tmp8, %mul.us.1
- store i32 %add.us.1, i32* %arrayidx9.us.1, align 4
+ store i32 %add.us.1, ptr %arrayidx9.us.1, align 4
%inc.us.1 = or i32 %j.023.us, 2
- %arrayidx6.us.2 = getelementptr inbounds i16, i16* %tmp3, i32 %inc.us.1
- %tmp9 = load i16, i16* %arrayidx6.us.2, align 2
+ %arrayidx6.us.2 = getelementptr inbounds i16, ptr %tmp3, i32 %inc.us.1
+ %tmp9 = load i16, ptr %arrayidx6.us.2, align 2
%conv7.us.2 = sext i16 %tmp9 to i32
%mul.us.2 = mul nsw i32 %conv7.us.2, %conv.us
- %arrayidx9.us.2 = getelementptr inbounds i32, i32* %tmp4, i32 %inc.us.1
- %tmp10 = load i32, i32* %arrayidx9.us.2, align 4
+ %arrayidx9.us.2 = getelementptr inbounds i32, ptr %tmp4, i32 %inc.us.1
+ %tmp10 = load i32, ptr %arrayidx9.us.2, align 4
%add.us.2 = add nsw i32 %tmp10, %mul.us.2
- store i32 %add.us.2, i32* %arrayidx9.us.2, align 4
+ store i32 %add.us.2, ptr %arrayidx9.us.2, align 4
%inc.us.2 = or i32 %j.023.us, 3
- %arrayidx6.us.3 = getelementptr inbounds i16, i16* %tmp3, i32 %inc.us.2
- %tmp11 = load i16, i16* %arrayidx6.us.3, align 2
+ %arrayidx6.us.3 = getelementptr inbounds i16, ptr %tmp3, i32 %inc.us.2
+ %tmp11 = load i16, ptr %arrayidx6.us.3, align 2
%conv7.us.3 = sext i16 %tmp11 to i32
%mul.us.3 = mul nsw i32 %conv7.us.3, %conv.us
- %arrayidx9.us.3 = getelementptr inbounds i32, i32* %tmp4, i32 %inc.us.2
- %tmp12 = load i32, i32* %arrayidx9.us.3, align 4
+ %arrayidx9.us.3 = getelementptr inbounds i32, ptr %tmp4, i32 %inc.us.2
+ %tmp12 = load i32, ptr %arrayidx9.us.3, align 4
%add.us.3 = add nsw i32 %tmp12, %mul.us.3
- store i32 %add.us.3, i32* %arrayidx9.us.3, align 4
+ store i32 %add.us.3, ptr %arrayidx9.us.3, align 4
%inc.us.3 = add i32 %j.023.us, 4
%niter.nsub.3 = add i32 %niter, -4
%niter.ncmp.3 = icmp eq i32 %niter.nsub.3, 0
@@ -708,14 +708,14 @@ for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa: ; preds = %for.body4.us, %fo
for.body4.us.epil: ; preds = %for.body4.us.epil, %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa
%j.023.us.epil = phi i32 [ %inc.us.epil, %for.body4.us.epil ], [ %j.023.us.unr, %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa ]
%epil.iter = phi i32 [ %epil.iter.sub, %for.body4.us.epil ], [ %xtraiter, %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa ]
- %arrayidx6.us.epil = getelementptr inbounds i16, i16* %tmp3, i32 %j.023.us.epil
- %tmp13 = load i16, i16* %arrayidx6.us.epil, align 2
+ %arrayidx6.us.epil = getelementptr inbounds i16, ptr %tmp3, i32 %j.023.us.epil
+ %tmp13 = load i16, ptr %arrayidx6.us.epil, align 2
%conv7.us.epil = sext i16 %tmp13 to i32
%mul.us.epil = mul nsw i32 %conv7.us.epil, %conv.us
- %arrayidx9.us.epil = getelementptr inbounds i32, i32* %tmp4, i32 %j.023.us.epil
- %tmp14 = load i32, i32* %arrayidx9.us.epil, align 4
+ %arrayidx9.us.epil = getelementptr inbounds i32, ptr %tmp4, i32 %j.023.us.epil
+ %tmp14 = load i32, ptr %arrayidx9.us.epil, align 4
%add.us.epil = add nsw i32 %tmp14, %mul.us.epil
- store i32 %add.us.epil, i32* %arrayidx9.us.epil, align 4
+ store i32 %add.us.epil, ptr %arrayidx9.us.epil, align 4
%inc.us.epil = add nuw i32 %j.023.us.epil, 1
%epil.iter.sub = add i32 %epil.iter, -1
%epil.iter.cmp = icmp eq i32 %epil.iter.sub, 0
@@ -749,7 +749,7 @@ for.cond.cleanup: ; preds = %for.cond1.for.cond.
; CHECK-T2: @ %for.body4.us.epil
; CHECK-T2: ldrb{{.*}}, #1]!
-define void @mac_8x8_2d(i8* nocapture readonly %A, i8** nocapture readonly %B, i32* nocapture %C, i32 %N, i32 %M) {
+define void @mac_8x8_2d(ptr nocapture readonly %A, ptr nocapture readonly %B, ptr nocapture %C, i32 %N, i32 %M) {
entry:
%cmp22 = icmp eq i32 %N, 0
%cmp220 = icmp eq i32 %M, 0
@@ -766,52 +766,52 @@ for.cond1.preheader.us.preheader: ; preds = %entry
for.cond1.preheader.us: ; preds = %for.cond1.for.cond.cleanup3_crit_edge.us, %for.cond1.preheader.us.preheader
%i.023.us = phi i32 [ %inc10.us, %for.cond1.for.cond.cleanup3_crit_edge.us ], [ 0, %for.cond1.preheader.us.preheader ]
- %arrayidx.us = getelementptr inbounds i8, i8* %A, i32 %i.023.us
- %arrayidx5.us = getelementptr inbounds i8*, i8** %B, i32 %i.023.us
- %arrayidx8.us = getelementptr inbounds i32, i32* %C, i32 %i.023.us
- %.pre = load i8*, i8** %arrayidx5.us, align 4
- %.pre28 = load i32, i32* %arrayidx8.us, align 4
+ %arrayidx.us = getelementptr inbounds i8, ptr %A, i32 %i.023.us
+ %arrayidx5.us = getelementptr inbounds ptr, ptr %B, i32 %i.023.us
+ %arrayidx8.us = getelementptr inbounds i32, ptr %C, i32 %i.023.us
+ %.pre = load ptr, ptr %arrayidx5.us, align 4
+ %.pre28 = load i32, ptr %arrayidx8.us, align 4
br i1 %tmp1, label %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa, label %for.body4.us
for.body4.us: ; preds = %for.body4.us, %for.cond1.preheader.us
%tmp2 = phi i32 [ %add.us.3, %for.body4.us ], [ %.pre28, %for.cond1.preheader.us ]
%j.021.us = phi i32 [ %inc.us.3, %for.body4.us ], [ 0, %for.cond1.preheader.us ]
%niter = phi i32 [ %niter.nsub.3, %for.body4.us ], [ %unroll_iter, %for.cond1.preheader.us ]
- %tmp3 = load i8, i8* %arrayidx.us, align 1
+ %tmp3 = load i8, ptr %arrayidx.us, align 1
%conv.us = zext i8 %tmp3 to i32
- %arrayidx6.us = getelementptr inbounds i8, i8* %.pre, i32 %j.021.us
- %tmp4 = load i8, i8* %arrayidx6.us, align 1
+ %arrayidx6.us = getelementptr inbounds i8, ptr %.pre, i32 %j.021.us
+ %tmp4 = load i8, ptr %arrayidx6.us, align 1
%conv7.us = zext i8 %tmp4 to i32
%mul.us = mul nuw nsw i32 %conv7.us, %conv.us
%add.us = add nsw i32 %mul.us, %tmp2
- store i32 %add.us, i32* %arrayidx8.us, align 4
+ store i32 %add.us, ptr %arrayidx8.us, align 4
%inc.us = or i32 %j.021.us, 1
- %tmp5 = load i8, i8* %arrayidx.us, align 1
+ %tmp5 = load i8, ptr %arrayidx.us, align 1
%conv.us.1 = zext i8 %tmp5 to i32
- %arrayidx6.us.1 = getelementptr inbounds i8, i8* %.pre, i32 %inc.us
- %tmp6 = load i8, i8* %arrayidx6.us.1, align 1
+ %arrayidx6.us.1 = getelementptr inbounds i8, ptr %.pre, i32 %inc.us
+ %tmp6 = load i8, ptr %arrayidx6.us.1, align 1
%conv7.us.1 = zext i8 %tmp6 to i32
%mul.us.1 = mul nuw nsw i32 %conv7.us.1, %conv.us.1
%add.us.1 = add nsw i32 %mul.us.1, %add.us
- store i32 %add.us.1, i32* %arrayidx8.us, align 4
+ store i32 %add.us.1, ptr %arrayidx8.us, align 4
%inc.us.1 = or i32 %j.021.us, 2
- %tmp7 = load i8, i8* %arrayidx.us, align 1
+ %tmp7 = load i8, ptr %arrayidx.us, align 1
%conv.us.2 = zext i8 %tmp7 to i32
- %arrayidx6.us.2 = getelementptr inbounds i8, i8* %.pre, i32 %inc.us.1
- %tmp8 = load i8, i8* %arrayidx6.us.2, align 1
+ %arrayidx6.us.2 = getelementptr inbounds i8, ptr %.pre, i32 %inc.us.1
+ %tmp8 = load i8, ptr %arrayidx6.us.2, align 1
%conv7.us.2 = zext i8 %tmp8 to i32
%mul.us.2 = mul nuw nsw i32 %conv7.us.2, %conv.us.2
%add.us.2 = add nsw i32 %mul.us.2, %add.us.1
- store i32 %add.us.2, i32* %arrayidx8.us, align 4
+ store i32 %add.us.2, ptr %arrayidx8.us, align 4
%inc.us.2 = or i32 %j.021.us, 3
- %tmp9 = load i8, i8* %arrayidx.us, align 1
+ %tmp9 = load i8, ptr %arrayidx.us, align 1
%conv.us.3 = zext i8 %tmp9 to i32
- %arrayidx6.us.3 = getelementptr inbounds i8, i8* %.pre, i32 %inc.us.2
- %tmp10 = load i8, i8* %arrayidx6.us.3, align 1
+ %arrayidx6.us.3 = getelementptr inbounds i8, ptr %.pre, i32 %inc.us.2
+ %tmp10 = load i8, ptr %arrayidx6.us.3, align 1
%conv7.us.3 = zext i8 %tmp10 to i32
%mul.us.3 = mul nuw nsw i32 %conv7.us.3, %conv.us.3
%add.us.3 = add nsw i32 %mul.us.3, %add.us.2
- store i32 %add.us.3, i32* %arrayidx8.us, align 4
+ store i32 %add.us.3, ptr %arrayidx8.us, align 4
%inc.us.3 = add i32 %j.021.us, 4
%niter.nsub.3 = add i32 %niter, -4
%niter.ncmp.3 = icmp eq i32 %niter.nsub.3, 0
@@ -826,14 +826,14 @@ for.body4.us.epil: ; preds = %for.body4.us.epil,
%tmp11 = phi i32 [ %add.us.epil, %for.body4.us.epil ], [ %.unr, %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa ]
%j.021.us.epil = phi i32 [ %inc.us.epil, %for.body4.us.epil ], [ %j.021.us.unr, %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa ]
%epil.iter = phi i32 [ %epil.iter.sub, %for.body4.us.epil ], [ %xtraiter, %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa ]
- %tmp12 = load i8, i8* %arrayidx.us, align 1
+ %tmp12 = load i8, ptr %arrayidx.us, align 1
%conv.us.epil = zext i8 %tmp12 to i32
- %arrayidx6.us.epil = getelementptr inbounds i8, i8* %.pre, i32 %j.021.us.epil
- %tmp13 = load i8, i8* %arrayidx6.us.epil, align 1
+ %arrayidx6.us.epil = getelementptr inbounds i8, ptr %.pre, i32 %j.021.us.epil
+ %tmp13 = load i8, ptr %arrayidx6.us.epil, align 1
%conv7.us.epil = zext i8 %tmp13 to i32
%mul.us.epil = mul nuw nsw i32 %conv7.us.epil, %conv.us.epil
%add.us.epil = add nsw i32 %mul.us.epil, %tmp11
- store i32 %add.us.epil, i32* %arrayidx8.us, align 4
+ store i32 %add.us.epil, ptr %arrayidx8.us, align 4
%inc.us.epil = add nuw i32 %j.021.us.epil, 1
%epil.iter.sub = add i32 %epil.iter, -1
%epil.iter.cmp = icmp eq i32 %epil.iter.sub, 0
@@ -863,7 +863,7 @@ for.cond.cleanup: ; preds = %for.cond1.for.cond.
; CHECK-T2: @ %for.body4.us.epil
; CHECK-T2: ldrsh{{.*}}, #2]!
-define void @mac_16x16_2d(i16* nocapture readonly %A, i16** nocapture readonly %B, i32* nocapture %C, i32 %N, i32 %M) {
+define void @mac_16x16_2d(ptr nocapture readonly %A, ptr nocapture readonly %B, ptr nocapture %C, i32 %N, i32 %M) {
entry:
%cmp23 = icmp eq i32 %N, 0
%cmp220 = icmp eq i32 %M, 0
@@ -880,39 +880,39 @@ for.cond1.preheader.us.preheader: ; preds = %entry
for.cond1.preheader.us: ; preds = %for.cond1.for.cond.cleanup3_crit_edge.us, %for.cond1.preheader.us.preheader
%i.024.us = phi i32 [ %inc10.us, %for.cond1.for.cond.cleanup3_crit_edge.us ], [ 0, %for.cond1.preheader.us.preheader ]
- %arrayidx.us = getelementptr inbounds i16, i16* %A, i32 %i.024.us
- %tmp2 = load i16, i16* %arrayidx.us, align 2
+ %arrayidx.us = getelementptr inbounds i16, ptr %A, i32 %i.024.us
+ %tmp2 = load i16, ptr %arrayidx.us, align 2
%conv.us = sext i16 %tmp2 to i32
- %arrayidx5.us = getelementptr inbounds i16*, i16** %B, i32 %i.024.us
- %tmp3 = load i16*, i16** %arrayidx5.us, align 4
- %arrayidx8.us = getelementptr inbounds i32, i32* %C, i32 %i.024.us
- %arrayidx8.promoted.us = load i32, i32* %arrayidx8.us, align 4
+ %arrayidx5.us = getelementptr inbounds ptr, ptr %B, i32 %i.024.us
+ %tmp3 = load ptr, ptr %arrayidx5.us, align 4
+ %arrayidx8.us = getelementptr inbounds i32, ptr %C, i32 %i.024.us
+ %arrayidx8.promoted.us = load i32, ptr %arrayidx8.us, align 4
br i1 %tmp1, label %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa, label %for.body4.us
for.body4.us: ; preds = %for.body4.us, %for.cond1.preheader.us
%add22.us = phi i32 [ %add.us.3, %for.body4.us ], [ %arrayidx8.promoted.us, %for.cond1.preheader.us ]
%j.021.us = phi i32 [ %inc.us.3, %for.body4.us ], [ 0, %for.cond1.preheader.us ]
%niter = phi i32 [ %niter.nsub.3, %for.body4.us ], [ %unroll_iter, %for.cond1.preheader.us ]
- %arrayidx6.us = getelementptr inbounds i16, i16* %tmp3, i32 %j.021.us
- %tmp4 = load i16, i16* %arrayidx6.us, align 2
+ %arrayidx6.us = getelementptr inbounds i16, ptr %tmp3, i32 %j.021.us
+ %tmp4 = load i16, ptr %arrayidx6.us, align 2
%conv7.us = sext i16 %tmp4 to i32
%mul.us = mul nsw i32 %conv7.us, %conv.us
%add.us = add nsw i32 %mul.us, %add22.us
%inc.us = or i32 %j.021.us, 1
- %arrayidx6.us.1 = getelementptr inbounds i16, i16* %tmp3, i32 %inc.us
- %tmp5 = load i16, i16* %arrayidx6.us.1, align 2
+ %arrayidx6.us.1 = getelementptr inbounds i16, ptr %tmp3, i32 %inc.us
+ %tmp5 = load i16, ptr %arrayidx6.us.1, align 2
%conv7.us.1 = sext i16 %tmp5 to i32
%mul.us.1 = mul nsw i32 %conv7.us.1, %conv.us
%add.us.1 = add nsw i32 %mul.us.1, %add.us
%inc.us.1 = or i32 %j.021.us, 2
- %arrayidx6.us.2 = getelementptr inbounds i16, i16* %tmp3, i32 %inc.us.1
- %tmp6 = load i16, i16* %arrayidx6.us.2, align 2
+ %arrayidx6.us.2 = getelementptr inbounds i16, ptr %tmp3, i32 %inc.us.1
+ %tmp6 = load i16, ptr %arrayidx6.us.2, align 2
%conv7.us.2 = sext i16 %tmp6 to i32
%mul.us.2 = mul nsw i32 %conv7.us.2, %conv.us
%add.us.2 = add nsw i32 %mul.us.2, %add.us.1
%inc.us.2 = or i32 %j.021.us, 3
- %arrayidx6.us.3 = getelementptr inbounds i16, i16* %tmp3, i32 %inc.us.2
- %tmp7 = load i16, i16* %arrayidx6.us.3, align 2
+ %arrayidx6.us.3 = getelementptr inbounds i16, ptr %tmp3, i32 %inc.us.2
+ %tmp7 = load i16, ptr %arrayidx6.us.3, align 2
%conv7.us.3 = sext i16 %tmp7 to i32
%mul.us.3 = mul nsw i32 %conv7.us.3, %conv.us
%add.us.3 = add nsw i32 %mul.us.3, %add.us.2
@@ -931,8 +931,8 @@ for.body4.us.epil: ; preds = %for.body4.us.epil,
%add22.us.epil = phi i32 [ %add.us.epil, %for.body4.us.epil ], [ %add22.us.unr, %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa ]
%j.021.us.epil = phi i32 [ %inc.us.epil, %for.body4.us.epil ], [ %j.021.us.unr, %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa ]
%epil.iter = phi i32 [ %epil.iter.sub, %for.body4.us.epil ], [ %xtraiter, %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa ]
- %arrayidx6.us.epil = getelementptr inbounds i16, i16* %tmp3, i32 %j.021.us.epil
- %tmp8 = load i16, i16* %arrayidx6.us.epil, align 2
+ %arrayidx6.us.epil = getelementptr inbounds i16, ptr %tmp3, i32 %j.021.us.epil
+ %tmp8 = load i16, ptr %arrayidx6.us.epil, align 2
%conv7.us.epil = sext i16 %tmp8 to i32
%mul.us.epil = mul nsw i32 %conv7.us.epil, %conv.us
%add.us.epil = add nsw i32 %mul.us.epil, %add22.us.epil
@@ -943,7 +943,7 @@ for.body4.us.epil: ; preds = %for.body4.us.epil,
for.cond1.for.cond.cleanup3_crit_edge.us: ; preds = %for.body4.us.epil, %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa
%add.us.lcssa = phi i32 [ %add.us.lcssa.ph, %for.cond1.for.cond.cleanup3_crit_edge.us.unr-lcssa ], [ %add.us.epil, %for.body4.us.epil ]
- store i32 %add.us.lcssa, i32* %arrayidx8.us, align 4
+ store i32 %add.us.lcssa, ptr %arrayidx8.us, align 4
%inc10.us = add nuw i32 %i.024.us, 1
%exitcond27 = icmp eq i32 %inc10.us, %N
br i1 %exitcond27, label %for.cond.cleanup, label %for.cond1.preheader.us
@@ -962,7 +962,7 @@ for.cond.cleanup: ; preds = %for.cond1.for.cond.
; CHECK-COMPLEX-NOT: ldr{{.*}}]!
; CHECK-COMPLEX-NOT: str{{.*}}]!
-define void @mul32x32_backwards(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) {
+define void @mul32x32_backwards(ptr nocapture %a, ptr nocapture readonly %b, ptr nocapture readonly %c, i32 %N) {
entry:
%i.08 = add i32 %N, -1
%cmp9 = icmp sgt i32 %i.08, -1
@@ -976,13 +976,13 @@ for.body.preheader: ; preds = %entry
for.body.prol: ; preds = %for.body.prol, %for.body.preheader
%i.010.prol = phi i32 [ %i.0.prol, %for.body.prol ], [ %i.08, %for.body.preheader ]
%prol.iter = phi i32 [ %prol.iter.sub, %for.body.prol ], [ %xtraiter, %for.body.preheader ]
- %arrayidx.prol = getelementptr inbounds i32, i32* %b, i32 %i.010.prol
- %tmp = load i32, i32* %arrayidx.prol, align 4
- %arrayidx1.prol = getelementptr inbounds i32, i32* %c, i32 %i.010.prol
- %tmp1 = load i32, i32* %arrayidx1.prol, align 4
+ %arrayidx.prol = getelementptr inbounds i32, ptr %b, i32 %i.010.prol
+ %tmp = load i32, ptr %arrayidx.prol, align 4
+ %arrayidx1.prol = getelementptr inbounds i32, ptr %c, i32 %i.010.prol
+ %tmp1 = load i32, ptr %arrayidx1.prol, align 4
%mul.prol = mul nsw i32 %tmp1, %tmp
- %arrayidx2.prol = getelementptr inbounds i32, i32* %a, i32 %i.010.prol
- store i32 %mul.prol, i32* %arrayidx2.prol, align 4
+ %arrayidx2.prol = getelementptr inbounds i32, ptr %a, i32 %i.010.prol
+ store i32 %mul.prol, ptr %arrayidx2.prol, align 4
%i.0.prol = add i32 %i.010.prol, -1
%prol.iter.sub = add i32 %prol.iter, -1
%prol.iter.cmp = icmp eq i32 %prol.iter.sub, 0
@@ -998,37 +998,37 @@ for.cond.cleanup: ; preds = %for.body, %for.body
for.body: ; preds = %for.body, %for.body.prol.loopexit
%i.010 = phi i32 [ %i.0.3, %for.body ], [ %i.010.unr, %for.body.prol.loopexit ]
- %arrayidx = getelementptr inbounds i32, i32* %b, i32 %i.010
- %tmp3 = load i32, i32* %arrayidx, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %c, i32 %i.010
- %tmp4 = load i32, i32* %arrayidx1, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %b, i32 %i.010
+ %tmp3 = load i32, ptr %arrayidx, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %c, i32 %i.010
+ %tmp4 = load i32, ptr %arrayidx1, align 4
%mul = mul nsw i32 %tmp4, %tmp3
- %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 %i.010
- store i32 %mul, i32* %arrayidx2, align 4
+ %arrayidx2 = getelementptr inbounds i32, ptr %a, i32 %i.010
+ store i32 %mul, ptr %arrayidx2, align 4
%i.0 = add i32 %i.010, -1
- %arrayidx.1 = getelementptr inbounds i32, i32* %b, i32 %i.0
- %tmp5 = load i32, i32* %arrayidx.1, align 4
- %arrayidx1.1 = getelementptr inbounds i32, i32* %c, i32 %i.0
- %tmp6 = load i32, i32* %arrayidx1.1, align 4
+ %arrayidx.1 = getelementptr inbounds i32, ptr %b, i32 %i.0
+ %tmp5 = load i32, ptr %arrayidx.1, align 4
+ %arrayidx1.1 = getelementptr inbounds i32, ptr %c, i32 %i.0
+ %tmp6 = load i32, ptr %arrayidx1.1, align 4
%mul.1 = mul nsw i32 %tmp6, %tmp5
- %arrayidx2.1 = getelementptr inbounds i32, i32* %a, i32 %i.0
- store i32 %mul.1, i32* %arrayidx2.1, align 4
+ %arrayidx2.1 = getelementptr inbounds i32, ptr %a, i32 %i.0
+ store i32 %mul.1, ptr %arrayidx2.1, align 4
%i.0.1 = add i32 %i.010, -2
- %arrayidx.2 = getelementptr inbounds i32, i32* %b, i32 %i.0.1
- %tmp7 = load i32, i32* %arrayidx.2, align 4
- %arrayidx1.2 = getelementptr inbounds i32, i32* %c, i32 %i.0.1
- %tmp8 = load i32, i32* %arrayidx1.2, align 4
+ %arrayidx.2 = getelementptr inbounds i32, ptr %b, i32 %i.0.1
+ %tmp7 = load i32, ptr %arrayidx.2, align 4
+ %arrayidx1.2 = getelementptr inbounds i32, ptr %c, i32 %i.0.1
+ %tmp8 = load i32, ptr %arrayidx1.2, align 4
%mul.2 = mul nsw i32 %tmp8, %tmp7
- %arrayidx2.2 = getelementptr inbounds i32, i32* %a, i32 %i.0.1
- store i32 %mul.2, i32* %arrayidx2.2, align 4
+ %arrayidx2.2 = getelementptr inbounds i32, ptr %a, i32 %i.0.1
+ store i32 %mul.2, ptr %arrayidx2.2, align 4
%i.0.2 = add i32 %i.010, -3
- %arrayidx.3 = getelementptr inbounds i32, i32* %b, i32 %i.0.2
- %tmp9 = load i32, i32* %arrayidx.3, align 4
- %arrayidx1.3 = getelementptr inbounds i32, i32* %c, i32 %i.0.2
- %tmp10 = load i32, i32* %arrayidx1.3, align 4
+ %arrayidx.3 = getelementptr inbounds i32, ptr %b, i32 %i.0.2
+ %tmp9 = load i32, ptr %arrayidx.3, align 4
+ %arrayidx1.3 = getelementptr inbounds i32, ptr %c, i32 %i.0.2
+ %tmp10 = load i32, ptr %arrayidx1.3, align 4
%mul.3 = mul nsw i32 %tmp10, %tmp9
- %arrayidx2.3 = getelementptr inbounds i32, i32* %a, i32 %i.0.2
- store i32 %mul.3, i32* %arrayidx2.3, align 4
+ %arrayidx2.3 = getelementptr inbounds i32, ptr %a, i32 %i.0.2
+ store i32 %mul.3, ptr %arrayidx2.3, align 4
%i.0.3 = add i32 %i.010, -4
%cmp.3 = icmp sgt i32 %i.0.3, -1
br i1 %cmp.3, label %for.body, label %for.cond.cleanup
@@ -1052,7 +1052,7 @@ for.body: ; preds = %for.body, %for.body
; CHECK-T2: ldr{{.*}}, #4]!
; CHECK-T2: str{{.*}}, #4]!
-define void @mul32x32_forwards(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) {
+define void @mul32x32_forwards(ptr nocapture %a, ptr nocapture readonly %b, ptr nocapture readonly %c, i32 %N) {
entry:
%cmp8 = icmp eq i32 %N, 0
br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
@@ -1075,13 +1075,13 @@ for.cond.cleanup.loopexit.unr-lcssa: ; preds = %for.body, %for.body
for.body.epil: ; preds = %for.body.epil, %for.cond.cleanup.loopexit.unr-lcssa
%i.09.epil = phi i32 [ %inc.epil, %for.body.epil ], [ %i.09.unr, %for.cond.cleanup.loopexit.unr-lcssa ]
%epil.iter = phi i32 [ %epil.iter.sub, %for.body.epil ], [ %xtraiter, %for.cond.cleanup.loopexit.unr-lcssa ]
- %arrayidx.epil = getelementptr inbounds i32, i32* %b, i32 %i.09.epil
- %tmp2 = load i32, i32* %arrayidx.epil, align 4
- %arrayidx1.epil = getelementptr inbounds i32, i32* %c, i32 %i.09.epil
- %tmp3 = load i32, i32* %arrayidx1.epil, align 4
+ %arrayidx.epil = getelementptr inbounds i32, ptr %b, i32 %i.09.epil
+ %tmp2 = load i32, ptr %arrayidx.epil, align 4
+ %arrayidx1.epil = getelementptr inbounds i32, ptr %c, i32 %i.09.epil
+ %tmp3 = load i32, ptr %arrayidx1.epil, align 4
%mul.epil = mul nsw i32 %tmp3, %tmp2
- %arrayidx2.epil = getelementptr inbounds i32, i32* %a, i32 %i.09.epil
- store i32 %mul.epil, i32* %arrayidx2.epil, align 4
+ %arrayidx2.epil = getelementptr inbounds i32, ptr %a, i32 %i.09.epil
+ store i32 %mul.epil, ptr %arrayidx2.epil, align 4
%inc.epil = add nuw nsw i32 %i.09.epil, 1
%epil.iter.sub = add i32 %epil.iter, -1
%epil.iter.cmp = icmp eq i32 %epil.iter.sub, 0
@@ -1093,37 +1093,37 @@ for.cond.cleanup: ; preds = %for.body.epil, %for
for.body: ; preds = %for.body, %for.body.preheader.new
%i.09 = phi i32 [ 0, %for.body.preheader.new ], [ %inc.3, %for.body ]
%niter = phi i32 [ %unroll_iter, %for.body.preheader.new ], [ %niter.nsub.3, %for.body ]
- %arrayidx = getelementptr inbounds i32, i32* %b, i32 %i.09
- %tmp4 = load i32, i32* %arrayidx, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %c, i32 %i.09
- %tmp5 = load i32, i32* %arrayidx1, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %b, i32 %i.09
+ %tmp4 = load i32, ptr %arrayidx, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %c, i32 %i.09
+ %tmp5 = load i32, ptr %arrayidx1, align 4
%mul = mul nsw i32 %tmp5, %tmp4
- %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 %i.09
- store i32 %mul, i32* %arrayidx2, align 4
+ %arrayidx2 = getelementptr inbounds i32, ptr %a, i32 %i.09
+ store i32 %mul, ptr %arrayidx2, align 4
%inc = or i32 %i.09, 1
- %arrayidx.1 = getelementptr inbounds i32, i32* %b, i32 %inc
- %tmp6 = load i32, i32* %arrayidx.1, align 4
- %arrayidx1.1 = getelementptr inbounds i32, i32* %c, i32 %inc
- %tmp7 = load i32, i32* %arrayidx1.1, align 4
+ %arrayidx.1 = getelementptr inbounds i32, ptr %b, i32 %inc
+ %tmp6 = load i32, ptr %arrayidx.1, align 4
+ %arrayidx1.1 = getelementptr inbounds i32, ptr %c, i32 %inc
+ %tmp7 = load i32, ptr %arrayidx1.1, align 4
%mul.1 = mul nsw i32 %tmp7, %tmp6
- %arrayidx2.1 = getelementptr inbounds i32, i32* %a, i32 %inc
- store i32 %mul.1, i32* %arrayidx2.1, align 4
+ %arrayidx2.1 = getelementptr inbounds i32, ptr %a, i32 %inc
+ store i32 %mul.1, ptr %arrayidx2.1, align 4
%inc.1 = or i32 %i.09, 2
- %arrayidx.2 = getelementptr inbounds i32, i32* %b, i32 %inc.1
- %tmp8 = load i32, i32* %arrayidx.2, align 4
- %arrayidx1.2 = getelementptr inbounds i32, i32* %c, i32 %inc.1
- %tmp9 = load i32, i32* %arrayidx1.2, align 4
+ %arrayidx.2 = getelementptr inbounds i32, ptr %b, i32 %inc.1
+ %tmp8 = load i32, ptr %arrayidx.2, align 4
+ %arrayidx1.2 = getelementptr inbounds i32, ptr %c, i32 %inc.1
+ %tmp9 = load i32, ptr %arrayidx1.2, align 4
%mul.2 = mul nsw i32 %tmp9, %tmp8
- %arrayidx2.2 = getelementptr inbounds i32, i32* %a, i32 %inc.1
- store i32 %mul.2, i32* %arrayidx2.2, align 4
+ %arrayidx2.2 = getelementptr inbounds i32, ptr %a, i32 %inc.1
+ store i32 %mul.2, ptr %arrayidx2.2, align 4
%inc.2 = or i32 %i.09, 3
- %arrayidx.3 = getelementptr inbounds i32, i32* %b, i32 %inc.2
- %tmp10 = load i32, i32* %arrayidx.3, align 4
- %arrayidx1.3 = getelementptr inbounds i32, i32* %c, i32 %inc.2
- %tmp11 = load i32, i32* %arrayidx1.3, align 4
+ %arrayidx.3 = getelementptr inbounds i32, ptr %b, i32 %inc.2
+ %tmp10 = load i32, ptr %arrayidx.3, align 4
+ %arrayidx1.3 = getelementptr inbounds i32, ptr %c, i32 %inc.2
+ %tmp11 = load i32, ptr %arrayidx1.3, align 4
%mul.3 = mul nsw i32 %tmp11, %tmp10
- %arrayidx2.3 = getelementptr inbounds i32, i32* %a, i32 %inc.2
- store i32 %mul.3, i32* %arrayidx2.3, align 4
+ %arrayidx2.3 = getelementptr inbounds i32, ptr %a, i32 %inc.2
+ store i32 %mul.3, ptr %arrayidx2.3, align 4
%inc.3 = add nuw nsw i32 %i.09, 4
%niter.nsub.3 = add i32 %niter, -4
%niter.ncmp.3 = icmp eq i32 %niter.nsub.3, 0
diff --git a/llvm/test/CodeGen/ARM/loopvectorize_pr33804.ll b/llvm/test/CodeGen/ARM/loopvectorize_pr33804.ll
index 4000a59b92a93..540cbbfe96e81 100644
--- a/llvm/test/CodeGen/ARM/loopvectorize_pr33804.ll
+++ b/llvm/test/CodeGen/ARM/loopvectorize_pr33804.ll
@@ -10,22 +10,21 @@ source_filename = "bugpoint-output-26dbd81.bc"
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv7-unknown-linux-gnueabihf"
-%struct.CvNode1D = type { float, %struct.CvNode1D* }
+%struct.CvNode1D = type { float, ptr }
; CHECK-LABEL: @cvCalcEMD2
; CHECK: vector.body
-; CHECK: store <{{[0-9]+}} x %struct.CvNode1D*>
-define void @cvCalcEMD2() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+; CHECK: store <{{[0-9]+}} x ptr>
+define void @cvCalcEMD2() local_unnamed_addr #0 personality ptr @__gxx_personality_v0 {
entry:
br label %for.body14.i.i
for.body14.i.i: ; preds = %for.body14.i.i, %entry
%i.1424.i.i = phi i32 [ %inc21.i.i, %for.body14.i.i ], [ 0, %entry ]
- %arrayidx15.i.i1427 = getelementptr inbounds %struct.CvNode1D, %struct.CvNode1D* undef, i32 %i.1424.i.i
- %val.i.i = getelementptr inbounds %struct.CvNode1D, %struct.CvNode1D* %arrayidx15.i.i1427, i32 0, i32 0
- store float 0xC415AF1D80000000, float* %val.i.i, align 4
- %next19.i.i = getelementptr inbounds %struct.CvNode1D, %struct.CvNode1D* undef, i32 %i.1424.i.i, i32 1
- store %struct.CvNode1D* undef, %struct.CvNode1D** %next19.i.i, align 4
+ %arrayidx15.i.i1427 = getelementptr inbounds %struct.CvNode1D, ptr undef, i32 %i.1424.i.i
+ store float 0xC415AF1D80000000, ptr %arrayidx15.i.i1427, align 4
+ %next19.i.i = getelementptr inbounds %struct.CvNode1D, ptr undef, i32 %i.1424.i.i, i32 1
+ store ptr undef, ptr %next19.i.i, align 4
%inc21.i.i = add nuw nsw i32 %i.1424.i.i, 1
%exitcond438.i.i = icmp eq i32 %inc21.i.i, 0
br i1 %exitcond438.i.i, label %for.end22.i.i, label %for.body14.i.i
@@ -36,22 +35,22 @@ for.end22.i.i: ; preds = %for.body14.i.i
; This test checks when a pointer value is stored into a float type.
-%struct.CvNode1D2 = type { %struct.CvNode1D2*, float }
+%struct.CvNode1D2 = type { ptr, float }
; CHECK-LABEL: @cvCalcEMD2_2
; CHECK: vector.body
; CHECK: store <{{[0-9]+}} x float>
-define void @cvCalcEMD2_2() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+define void @cvCalcEMD2_2() local_unnamed_addr #0 personality ptr @__gxx_personality_v0 {
entry:
br label %for.body14.i.i
for.body14.i.i: ; preds = %for.body14.i.i, %entry
%i.1424.i.i = phi i32 [ %inc21.i.i, %for.body14.i.i ], [ 0, %entry ]
- %next19.i.i = getelementptr inbounds %struct.CvNode1D2, %struct.CvNode1D2* undef, i32 %i.1424.i.i, i32 0
- store %struct.CvNode1D2* undef, %struct.CvNode1D2** %next19.i.i, align 4
- %arrayidx15.i.i1427 = getelementptr inbounds %struct.CvNode1D2, %struct.CvNode1D2* undef, i32 %i.1424.i.i
- %val.i.i = getelementptr inbounds %struct.CvNode1D2, %struct.CvNode1D2* %arrayidx15.i.i1427, i32 0, i32 1
- store float 0xC415AF1D80000000, float* %val.i.i, align 4
+ %next19.i.i = getelementptr inbounds %struct.CvNode1D2, ptr undef, i32 %i.1424.i.i, i32 0
+ store ptr undef, ptr %next19.i.i, align 4
+ %arrayidx15.i.i1427 = getelementptr inbounds %struct.CvNode1D2, ptr undef, i32 %i.1424.i.i
+ %val.i.i = getelementptr inbounds %struct.CvNode1D2, ptr %arrayidx15.i.i1427, i32 0, i32 1
+ store float 0xC415AF1D80000000, ptr %val.i.i, align 4
%inc21.i.i = add nuw nsw i32 %i.1424.i.i, 1
%exitcond438.i.i = icmp eq i32 %inc21.i.i, 0
br i1 %exitcond438.i.i, label %for.end22.i.i, label %for.body14.i.i
@@ -65,17 +64,16 @@ for.end22.i.i: ; preds = %for.body14.i.i
; CHECK-LABEL: @cvCalcEMD3
; CHECK: vector.body
; CHECK: inttoptr <{{[0-9]+}} x i32>
-define void @cvCalcEMD3() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+define void @cvCalcEMD3() local_unnamed_addr #0 personality ptr @__gxx_personality_v0 {
entry:
br label %for.body14.i.i
for.body14.i.i: ; preds = %for.body14.i.i, %entry
%i.1424.i.i = phi i32 [ %inc21.i.i, %for.body14.i.i ], [ 0, %entry ]
- %arrayidx15.i.i1427 = getelementptr inbounds %struct.CvNode1D, %struct.CvNode1D* undef, i32 %i.1424.i.i
- %val.i.i = getelementptr inbounds %struct.CvNode1D, %struct.CvNode1D* %arrayidx15.i.i1427, i32 0, i32 0
- %loadf = load float, float* %val.i.i, align 4
- %next19.i.i = getelementptr inbounds %struct.CvNode1D, %struct.CvNode1D* undef, i32 %i.1424.i.i, i32 1
- %loadp = load %struct.CvNode1D*, %struct.CvNode1D** %next19.i.i, align 4
+ %arrayidx15.i.i1427 = getelementptr inbounds %struct.CvNode1D, ptr undef, i32 %i.1424.i.i
+ %loadf = load float, ptr %arrayidx15.i.i1427, align 4
+ %next19.i.i = getelementptr inbounds %struct.CvNode1D, ptr undef, i32 %i.1424.i.i, i32 1
+ %loadp = load ptr, ptr %next19.i.i, align 4
%inc21.i.i = add nuw nsw i32 %i.1424.i.i, 1
%exitcond438.i.i = icmp eq i32 %inc21.i.i, 0
br i1 %exitcond438.i.i, label %for.end22.i.i, label %for.body14.i.i
@@ -88,18 +86,18 @@ for.end22.i.i: ; preds = %for.body14.i.i
; CHECK-LABEL: @cvCalcEMD3_2
; CHECK: vector.body
-; CHECK: ptrtoint <{{[0-9]+}} x %struct.CvNode1D2*>
-define void @cvCalcEMD3_2() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+; CHECK: ptrtoint <{{[0-9]+}} x ptr>
+define void @cvCalcEMD3_2() local_unnamed_addr #0 personality ptr @__gxx_personality_v0 {
entry:
br label %for.body14.i.i
for.body14.i.i: ; preds = %for.body14.i.i, %entry
%i.1424.i.i = phi i32 [ %inc21.i.i, %for.body14.i.i ], [ 0, %entry ]
- %next19.i.i = getelementptr inbounds %struct.CvNode1D2, %struct.CvNode1D2* undef, i32 %i.1424.i.i, i32 0
- %loadp = load %struct.CvNode1D2*, %struct.CvNode1D2** %next19.i.i, align 4
- %arrayidx15.i.i1427 = getelementptr inbounds %struct.CvNode1D2, %struct.CvNode1D2* undef, i32 %i.1424.i.i
- %val.i.i = getelementptr inbounds %struct.CvNode1D2, %struct.CvNode1D2* %arrayidx15.i.i1427, i32 0, i32 1
- %loadf = load float, float* %val.i.i, align 4
+ %next19.i.i = getelementptr inbounds %struct.CvNode1D2, ptr undef, i32 %i.1424.i.i, i32 0
+ %loadp = load ptr, ptr %next19.i.i, align 4
+ %arrayidx15.i.i1427 = getelementptr inbounds %struct.CvNode1D2, ptr undef, i32 %i.1424.i.i
+ %val.i.i = getelementptr inbounds %struct.CvNode1D2, ptr %arrayidx15.i.i1427, i32 0, i32 1
+ %loadf = load float, ptr %val.i.i, align 4
%inc21.i.i = add nuw nsw i32 %i.1424.i.i, 1
%exitcond438.i.i = icmp eq i32 %inc21.i.i, 0
br i1 %exitcond438.i.i, label %for.end22.i.i, label %for.body14.i.i
diff --git a/llvm/test/CodeGen/ARM/lowerMUL-newload.ll b/llvm/test/CodeGen/ARM/lowerMUL-newload.ll
index 92a07b234ca19..7876e64b8cfe1 100644
--- a/llvm/test/CodeGen/ARM/lowerMUL-newload.ll
+++ b/llvm/test/CodeGen/ARM/lowerMUL-newload.ll
@@ -18,7 +18,7 @@ entry:
ret <4 x i16> %v5
}
-define void @mla_loadstore(i16* %a, i16* %b, i16* %c) {
+define void @mla_loadstore(ptr %a, ptr %b, ptr %c) {
; CHECK-LABEL: mla_loadstore:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, [r0, #16]
@@ -30,24 +30,20 @@ define void @mla_loadstore(i16* %a, i16* %b, i16* %c) {
; CHECK-NEXT: vstr d16, [r0, #16]
; CHECK-NEXT: bx lr
entry:
- %scevgep0 = getelementptr i16, i16* %a, i32 8
- %vector_ptr0 = bitcast i16* %scevgep0 to <4 x i16>*
- %vec0 = load <4 x i16>, <4 x i16>* %vector_ptr0, align 8
+ %scevgep0 = getelementptr i16, ptr %a, i32 8
+ %vec0 = load <4 x i16>, ptr %scevgep0, align 8
%v0 = sext <4 x i16> %vec0 to <4 x i32>
- %scevgep1 = getelementptr i16, i16* %b, i32 8
- %vector_ptr1 = bitcast i16* %scevgep1 to <4 x i16>*
- %vec1 = load <4 x i16>, <4 x i16>* %vector_ptr1, align 8
+ %scevgep1 = getelementptr i16, ptr %b, i32 8
+ %vec1 = load <4 x i16>, ptr %scevgep1, align 8
%v1 = sext <4 x i16> %vec1 to <4 x i32>
- %scevgep2 = getelementptr i16, i16* %c, i32 8
- %vector_ptr2 = bitcast i16* %scevgep2 to <4 x i16>*
- %vec2 = load <4 x i16>, <4 x i16>* %vector_ptr2, align 8
+ %scevgep2 = getelementptr i16, ptr %c, i32 8
+ %vec2 = load <4 x i16>, ptr %scevgep2, align 8
%v2 = sext <4 x i16> %vec2 to <4 x i32>
%v3 = mul <4 x i32> %v1, %v0
%v4 = add <4 x i32> %v3, %v2
%v5 = trunc <4 x i32> %v4 to <4 x i16>
- %scevgep3 = getelementptr i16, i16* %a, i32 8
- %vector_ptr3 = bitcast i16* %scevgep3 to <4 x i16>*
- store <4 x i16> %v5, <4 x i16>* %vector_ptr3, align 8
+ %scevgep3 = getelementptr i16, ptr %a, i32 8
+ store <4 x i16> %v5, ptr %scevgep3, align 8
ret void
}
@@ -68,7 +64,7 @@ entry:
ret <4 x i16> %v5
}
-define void @addmul_loadstore(i16* %a, i16* %b, i16* %c) {
+define void @addmul_loadstore(ptr %a, ptr %b, ptr %c) {
; CHECK-LABEL: addmul_loadstore:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, [r2, #16]
@@ -80,28 +76,24 @@ define void @addmul_loadstore(i16* %a, i16* %b, i16* %c) {
; CHECK-NEXT: vstr d16, [r0, #16]
; CHECK-NEXT: bx lr
entry:
- %scevgep0 = getelementptr i16, i16* %a, i32 8
- %vector_ptr0 = bitcast i16* %scevgep0 to <4 x i16>*
- %vec0 = load <4 x i16>, <4 x i16>* %vector_ptr0, align 8
+ %scevgep0 = getelementptr i16, ptr %a, i32 8
+ %vec0 = load <4 x i16>, ptr %scevgep0, align 8
%v0 = sext <4 x i16> %vec0 to <4 x i32>
- %scevgep1 = getelementptr i16, i16* %b, i32 8
- %vector_ptr1 = bitcast i16* %scevgep1 to <4 x i16>*
- %vec1 = load <4 x i16>, <4 x i16>* %vector_ptr1, align 8
+ %scevgep1 = getelementptr i16, ptr %b, i32 8
+ %vec1 = load <4 x i16>, ptr %scevgep1, align 8
%v1 = sext <4 x i16> %vec1 to <4 x i32>
- %scevgep2 = getelementptr i16, i16* %c, i32 8
- %vector_ptr2 = bitcast i16* %scevgep2 to <4 x i16>*
- %vec2 = load <4 x i16>, <4 x i16>* %vector_ptr2, align 8
+ %scevgep2 = getelementptr i16, ptr %c, i32 8
+ %vec2 = load <4 x i16>, ptr %scevgep2, align 8
%v2 = sext <4 x i16> %vec2 to <4 x i32>
%v3 = add <4 x i32> %v1, %v0
%v4 = mul <4 x i32> %v3, %v2
%v5 = trunc <4 x i32> %v4 to <4 x i16>
- %scevgep3 = getelementptr i16, i16* %a, i32 8
- %vector_ptr3 = bitcast i16* %scevgep3 to <4 x i16>*
- store <4 x i16> %v5, <4 x i16>* %vector_ptr3, align 8
+ %scevgep3 = getelementptr i16, ptr %a, i32 8
+ store <4 x i16> %v5, ptr %scevgep3, align 8
ret void
}
-define void @func1(i16* %a, i16* %b, i16* %c) {
+define void @func1(ptr %a, ptr %b, ptr %c) {
; CHECK-LABEL: func1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: add r3, r1, #16
@@ -126,9 +118,9 @@ define void @func1(i16* %a, i16* %b, i16* %c) {
entry:
; The test case trying to vectorize the pseudo code below.
; a[i] = b[i] + c[i];
-; b[i] = a[i] * c[i];
-; a[i] = b[i] + a[i] * c[i];
-; Checking that vector load a[i] for "a[i] = b[i] + a[i] * c[i]" is
+; b[i] = aptr c[i];
+; a[i] = b[i] + aptr c[i];
+; Checking that vector load a[i] for "a[i] = b[i] + aptr c[i]" is
; scheduled before the first vector store to "a[i] = b[i] + c[i]".
; Checking that there is no vector load a[i] scheduled between the vector
; stores to a[i], otherwise the load of a[i] will be polluted by the first
@@ -137,42 +129,34 @@ entry:
; lowerMUL for the new created Load SDNode.
- %scevgep0 = getelementptr i16, i16* %a, i32 8
- %vector_ptr0 = bitcast i16* %scevgep0 to <4 x i16>*
- %vec0 = load <4 x i16>, <4 x i16>* %vector_ptr0, align 8
- %scevgep1 = getelementptr i16, i16* %b, i32 8
- %vector_ptr1 = bitcast i16* %scevgep1 to <4 x i16>*
- %vec1 = load <4 x i16>, <4 x i16>* %vector_ptr1, align 8
+ %scevgep0 = getelementptr i16, ptr %a, i32 8
+ %vec0 = load <4 x i16>, ptr %scevgep0, align 8
+ %scevgep1 = getelementptr i16, ptr %b, i32 8
+ %vec1 = load <4 x i16>, ptr %scevgep1, align 8
%0 = zext <4 x i16> %vec1 to <4 x i32>
- %scevgep2 = getelementptr i16, i16* %c, i32 8
- %vector_ptr2 = bitcast i16* %scevgep2 to <4 x i16>*
- %vec2 = load <4 x i16>, <4 x i16>* %vector_ptr2, align 8
+ %scevgep2 = getelementptr i16, ptr %c, i32 8
+ %vec2 = load <4 x i16>, ptr %scevgep2, align 8
%1 = sext <4 x i16> %vec2 to <4 x i32>
%vec3 = add <4 x i32> %1, %0
%2 = trunc <4 x i32> %vec3 to <4 x i16>
- %scevgep3 = getelementptr i16, i16* %a, i32 8
- %vector_ptr3 = bitcast i16* %scevgep3 to <4 x i16>*
- store <4 x i16> %2, <4 x i16>* %vector_ptr3, align 8
- %vector_ptr4 = bitcast i16* %scevgep2 to <4 x i16>*
- %vec4 = load <4 x i16>, <4 x i16>* %vector_ptr4, align 8
+ %scevgep3 = getelementptr i16, ptr %a, i32 8
+ store <4 x i16> %2, ptr %scevgep3, align 8
+ %vec4 = load <4 x i16>, ptr %scevgep2, align 8
%3 = sext <4 x i16> %vec4 to <4 x i32>
%vec5 = mul <4 x i32> %3, %vec3
%4 = trunc <4 x i32> %vec5 to <4 x i16>
- %vector_ptr5 = bitcast i16* %scevgep1 to <4 x i16>*
- store <4 x i16> %4, <4 x i16>* %vector_ptr5, align 8
+ store <4 x i16> %4, ptr %scevgep1, align 8
%5 = sext <4 x i16> %vec0 to <4 x i32>
- %vector_ptr6 = bitcast i16* %scevgep2 to <4 x i16>*
- %vec6 = load <4 x i16>, <4 x i16>* %vector_ptr6, align 8
+ %vec6 = load <4 x i16>, ptr %scevgep2, align 8
%6 = sext <4 x i16> %vec6 to <4 x i32>
%vec7 = mul <4 x i32> %6, %5
%vec8 = add <4 x i32> %vec7, %vec5
%7 = trunc <4 x i32> %vec8 to <4 x i16>
- %vector_ptr7 = bitcast i16* %scevgep3 to <4 x i16>*
- store <4 x i16> %7, <4 x i16>* %vector_ptr7, align 8
+ store <4 x i16> %7, ptr %scevgep3, align 8
ret void
}
-define void @func2(i16* %a, i16* %b, i16* %c) {
+define void @func2(ptr %a, ptr %b, ptr %c) {
; CHECK-LABEL: func2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, [r1, #16]
@@ -201,9 +185,9 @@ define void @func2(i16* %a, i16* %b, i16* %c) {
entry:
; The test case trying to vectorize the pseudo code below.
; a[i] = b[i] + c[i];
-; b[i] = a[i] * c[i];
-; a[i] = b[i] + a[i] * c[i] + a[i];
-; Checking that vector load a[i] for "a[i] = b[i] + a[i] * c[i] + a[i]"
+; b[i] = aptr c[i];
+; a[i] = b[i] + aptr c[i] + a[i];
+; Checking that vector load a[i] for "a[i] = b[i] + aptr c[i] + a[i]"
; is scheduled before the first vector store to "a[i] = b[i] + c[i]".
; Checking that there is no vector load a[i] scheduled between the first
; vector store to a[i] and the vector add of a[i], otherwise the load of
@@ -212,38 +196,30 @@ entry:
; Load SDNode are updated during lowerMUL.
- %scevgep0 = getelementptr i16, i16* %a, i32 8
- %vector_ptr0 = bitcast i16* %scevgep0 to <4 x i16>*
- %vec0 = load <4 x i16>, <4 x i16>* %vector_ptr0, align 8
- %scevgep1 = getelementptr i16, i16* %b, i32 8
- %vector_ptr1 = bitcast i16* %scevgep1 to <4 x i16>*
- %vec1 = load <4 x i16>, <4 x i16>* %vector_ptr1, align 8
+ %scevgep0 = getelementptr i16, ptr %a, i32 8
+ %vec0 = load <4 x i16>, ptr %scevgep0, align 8
+ %scevgep1 = getelementptr i16, ptr %b, i32 8
+ %vec1 = load <4 x i16>, ptr %scevgep1, align 8
%0 = zext <4 x i16> %vec1 to <4 x i32>
- %scevgep2 = getelementptr i16, i16* %c, i32 8
- %vector_ptr2 = bitcast i16* %scevgep2 to <4 x i16>*
- %vec2 = load <4 x i16>, <4 x i16>* %vector_ptr2, align 8
+ %scevgep2 = getelementptr i16, ptr %c, i32 8
+ %vec2 = load <4 x i16>, ptr %scevgep2, align 8
%1 = sext <4 x i16> %vec2 to <4 x i32>
%vec3 = add <4 x i32> %1, %0
%2 = trunc <4 x i32> %vec3 to <4 x i16>
- %scevgep3 = getelementptr i16, i16* %a, i32 8
- %vector_ptr3 = bitcast i16* %scevgep3 to <4 x i16>*
- store <4 x i16> %2, <4 x i16>* %vector_ptr3, align 8
- %vector_ptr4 = bitcast i16* %scevgep2 to <4 x i16>*
- %vec4 = load <4 x i16>, <4 x i16>* %vector_ptr4, align 8
+ %scevgep3 = getelementptr i16, ptr %a, i32 8
+ store <4 x i16> %2, ptr %scevgep3, align 8
+ %vec4 = load <4 x i16>, ptr %scevgep2, align 8
%3 = sext <4 x i16> %vec4 to <4 x i32>
%vec5 = mul <4 x i32> %3, %vec3
%4 = trunc <4 x i32> %vec5 to <4 x i16>
- %vector_ptr5 = bitcast i16* %scevgep1 to <4 x i16>*
- store <4 x i16> %4, <4 x i16>* %vector_ptr5, align 8
+ store <4 x i16> %4, ptr %scevgep1, align 8
%5 = sext <4 x i16> %vec0 to <4 x i32>
- %vector_ptr6 = bitcast i16* %scevgep2 to <4 x i16>*
- %vec6 = load <4 x i16>, <4 x i16>* %vector_ptr6, align 8
+ %vec6 = load <4 x i16>, ptr %scevgep2, align 8
%6 = sext <4 x i16> %vec6 to <4 x i32>
%vec7 = mul <4 x i32> %6, %5
%vec8 = add <4 x i32> %vec7, %vec5
%vec9 = add <4 x i32> %vec8, %5
%7 = trunc <4 x i32> %vec9 to <4 x i16>
- %vector_ptr7 = bitcast i16* %scevgep3 to <4 x i16>*
- store <4 x i16> %7, <4 x i16>* %vector_ptr7, align 8
+ store <4 x i16> %7, ptr %scevgep3, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/lsr-code-insertion.ll b/llvm/test/CodeGen/ARM/lsr-code-insertion.ll
index 766710fd1d64b..e9cf177a93322 100644
--- a/llvm/test/CodeGen/ARM/lsr-code-insertion.ll
+++ b/llvm/test/CodeGen/ARM/lsr-code-insertion.ll
@@ -14,7 +14,7 @@
target triple = "arm-apple-darwin8"
-define void @foo(i32* %mc, i32* %mpp, i32* %ip, i32* %dpp, i32* %tpmm, i32 %M, i32* %tpim, i32* %tpdm, i32* %bp, i32* %ms, i32 %xmb) {
+define void @foo(ptr %mc, ptr %mpp, ptr %ip, ptr %dpp, ptr %tpmm, i32 %M, ptr %tpim, ptr %tpdm, ptr %bp, ptr %ms, i32 %xmb) {
entry:
%tmp6584 = icmp slt i32 %M, 1 ; <i1> [#uses=1]
br i1 %tmp6584, label %return, label %bb
@@ -22,36 +22,36 @@ entry:
bb: ; preds = %cond_next59, %entry
%indvar = phi i32 [ 0, %entry ], [ %k.069.0, %cond_next59 ] ; <i32> [#uses=6]
%k.069.0 = add i32 %indvar, 1 ; <i32> [#uses=3]
- %tmp3 = getelementptr i32, i32* %mpp, i32 %indvar ; <i32*> [#uses=1]
- %tmp4 = load i32, i32* %tmp3 ; <i32> [#uses=1]
- %tmp8 = getelementptr i32, i32* %tpmm, i32 %indvar ; <i32*> [#uses=1]
- %tmp9 = load i32, i32* %tmp8 ; <i32> [#uses=1]
+ %tmp3 = getelementptr i32, ptr %mpp, i32 %indvar ; <ptr> [#uses=1]
+ %tmp4 = load i32, ptr %tmp3 ; <i32> [#uses=1]
+ %tmp8 = getelementptr i32, ptr %tpmm, i32 %indvar ; <ptr> [#uses=1]
+ %tmp9 = load i32, ptr %tmp8 ; <i32> [#uses=1]
%tmp10 = add i32 %tmp9, %tmp4 ; <i32> [#uses=2]
- %tmp13 = getelementptr i32, i32* %mc, i32 %k.069.0 ; <i32*> [#uses=5]
- store i32 %tmp10, i32* %tmp13
- %tmp17 = getelementptr i32, i32* %ip, i32 %indvar ; <i32*> [#uses=1]
- %tmp18 = load i32, i32* %tmp17 ; <i32> [#uses=1]
- %tmp22 = getelementptr i32, i32* %tpim, i32 %indvar ; <i32*> [#uses=1]
- %tmp23 = load i32, i32* %tmp22 ; <i32> [#uses=1]
+ %tmp13 = getelementptr i32, ptr %mc, i32 %k.069.0 ; <ptr> [#uses=5]
+ store i32 %tmp10, ptr %tmp13
+ %tmp17 = getelementptr i32, ptr %ip, i32 %indvar ; <ptr> [#uses=1]
+ %tmp18 = load i32, ptr %tmp17 ; <i32> [#uses=1]
+ %tmp22 = getelementptr i32, ptr %tpim, i32 %indvar ; <ptr> [#uses=1]
+ %tmp23 = load i32, ptr %tmp22 ; <i32> [#uses=1]
%tmp24 = add i32 %tmp23, %tmp18 ; <i32> [#uses=2]
%tmp30 = icmp sgt i32 %tmp24, %tmp10 ; <i1> [#uses=1]
br i1 %tmp30, label %cond_true, label %cond_next
cond_true: ; preds = %bb
- store i32 %tmp24, i32* %tmp13
+ store i32 %tmp24, ptr %tmp13
br label %cond_next
cond_next: ; preds = %cond_true, %bb
- %tmp39 = load i32, i32* %tmp13 ; <i32> [#uses=1]
- %tmp42 = getelementptr i32, i32* %ms, i32 %k.069.0 ; <i32*> [#uses=1]
- %tmp43 = load i32, i32* %tmp42 ; <i32> [#uses=1]
+ %tmp39 = load i32, ptr %tmp13 ; <i32> [#uses=1]
+ %tmp42 = getelementptr i32, ptr %ms, i32 %k.069.0 ; <ptr> [#uses=1]
+ %tmp43 = load i32, ptr %tmp42 ; <i32> [#uses=1]
%tmp44 = add i32 %tmp43, %tmp39 ; <i32> [#uses=2]
- store i32 %tmp44, i32* %tmp13
+ store i32 %tmp44, ptr %tmp13
%tmp52 = icmp slt i32 %tmp44, -987654321 ; <i1> [#uses=1]
br i1 %tmp52, label %cond_true55, label %cond_next59
cond_true55: ; preds = %cond_next
- store i32 -987654321, i32* %tmp13
+ store i32 -987654321, ptr %tmp13
br label %cond_next59
cond_next59: ; preds = %cond_true55, %cond_next
diff --git a/llvm/test/CodeGen/ARM/lsr-icmp-imm.ll b/llvm/test/CodeGen/ARM/lsr-icmp-imm.ll
index 3c68cc70aa8fd..837d2cd7f5cc8 100644
--- a/llvm/test/CodeGen/ARM/lsr-icmp-imm.ll
+++ b/llvm/test/CodeGen/ARM/lsr-icmp-imm.ll
@@ -10,7 +10,7 @@
; CHECK-T: adds{{.*}}[[IV]], #2
; CHECK-A: cmn{{.*}}[[IV]], #2
; CHECK: bne
-define i32 @f(i32* nocapture %a, i32 %i) nounwind readonly ssp {
+define i32 @f(ptr nocapture %a, i32 %i) nounwind readonly ssp {
entry:
%cmp3 = icmp eq i32 %i, -2
br i1 %cmp3, label %for.end, label %for.body
@@ -19,8 +19,8 @@ for.body: ; preds = %entry, %for.body
%bi.06 = phi i32 [ %i.addr.0.bi.0, %for.body ], [ 0, %entry ]
%i.addr.05 = phi i32 [ %sub, %for.body ], [ %i, %entry ]
%b.04 = phi i32 [ %.b.0, %for.body ], [ 0, %entry ]
- %arrayidx = getelementptr inbounds i32, i32* %a, i32 %i.addr.05
- %0 = load i32, i32* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %a, i32 %i.addr.05
+ %0 = load i32, ptr %arrayidx, align 4
%cmp1 = icmp sgt i32 %0, %b.04
%.b.0 = select i1 %cmp1, i32 %0, i32 %b.04
%i.addr.0.bi.0 = select i1 %cmp1, i32 %i.addr.05, i32 %bi.06
diff --git a/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll b/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll
index c50e42b515cf9..0c519f6285dc9 100644
--- a/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll
+++ b/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll
@@ -6,16 +6,16 @@
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
; Should not generate negated register offset
-define void @sintzero(i32* %a) nounwind {
+define void @sintzero(ptr %a) nounwind {
entry:
- store i32 0, i32* %a
+ store i32 0, ptr %a
br label %cond_next
cond_next: ; preds = %cond_next, %entry
%indvar = phi i32 [ 0, %entry ], [ %tmp25, %cond_next ] ; <i32> [#uses=1]
%tmp25 = add i32 %indvar, 1 ; <i32> [#uses=3]
- %tmp36 = getelementptr i32, i32* %a, i32 %tmp25 ; <i32*> [#uses=1]
- store i32 0, i32* %tmp36
+ %tmp36 = getelementptr i32, ptr %a, i32 %tmp25 ; <ptr> [#uses=1]
+ store i32 0, ptr %tmp36
icmp eq i32 %tmp25, -1 ; <i1>:0 [#uses=1]
br i1 %0, label %return, label %cond_next
diff --git a/llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll b/llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll
index a9a353cad5758..40f9f0857a753 100644
--- a/llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll
+++ b/llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll
@@ -15,7 +15,7 @@ target triple = "thumbv7-apple-ios"
%struct.partition_entry = type { i32, i32, i64, i64 }
-define i32 @partition_overlap_check(%struct.partition_entry* nocapture %part, i32 %num_entries) nounwind readonly optsize ssp "frame-pointer"="all" {
+define i32 @partition_overlap_check(ptr nocapture %part, i32 %num_entries) nounwind readonly optsize ssp "frame-pointer"="all" {
entry:
%cmp79 = icmp sgt i32 %num_entries, 0
br i1 %cmp79, label %outer.loop, label %for.end72
@@ -23,10 +23,10 @@ entry:
outer.loop: ; preds = %for.inc69, %entry
%overlap.081 = phi i32 [ %overlap.4, %for.inc69 ], [ 0, %entry ]
%0 = phi i32 [ %inc71, %for.inc69 ], [ 0, %entry ]
- %offset = getelementptr %struct.partition_entry, %struct.partition_entry* %part, i32 %0, i32 2
- %len = getelementptr %struct.partition_entry, %struct.partition_entry* %part, i32 %0, i32 3
- %tmp5 = load i64, i64* %offset, align 4
- %tmp15 = load i64, i64* %len, align 4
+ %offset = getelementptr %struct.partition_entry, ptr %part, i32 %0, i32 2
+ %len = getelementptr %struct.partition_entry, ptr %part, i32 %0, i32 3
+ %tmp5 = load i64, ptr %offset, align 4
+ %tmp15 = load i64, ptr %len, align 4
%add = add nsw i64 %tmp15, %tmp5
br label %inner.loop
@@ -37,10 +37,10 @@ inner.loop: ; preds = %for.inc, %outer.loo
br i1 %cmp23, label %for.inc, label %if.end
if.end: ; preds = %inner.loop
- %len39 = getelementptr %struct.partition_entry, %struct.partition_entry* %part, i32 %1, i32 3
- %offset28 = getelementptr %struct.partition_entry, %struct.partition_entry* %part, i32 %1, i32 2
- %tmp29 = load i64, i64* %offset28, align 4
- %tmp40 = load i64, i64* %len39, align 4
+ %len39 = getelementptr %struct.partition_entry, ptr %part, i32 %1, i32 3
+ %offset28 = getelementptr %struct.partition_entry, ptr %part, i32 %1, i32 2
+ %tmp29 = load i64, ptr %offset28, align 4
+ %tmp40 = load i64, ptr %len39, align 4
%add41 = add nsw i64 %tmp40, %tmp29
%cmp44 = icmp sge i64 %tmp29, %tmp5
%cmp47 = icmp slt i64 %tmp29, %add
diff --git a/llvm/test/CodeGen/ARM/machine-cse-cmp.ll b/llvm/test/CodeGen/ARM/machine-cse-cmp.ll
index 14565a7172827..36899d6baa7c0 100644
--- a/llvm/test/CodeGen/ARM/machine-cse-cmp.ll
+++ b/llvm/test/CodeGen/ARM/machine-cse-cmp.ll
@@ -32,14 +32,14 @@ entry:
; CHECK: bxlt
; CHECK-NOT: cmp
; CHECK: movle
- %0 = load i32, i32* @foo, align 4
+ %0 = load i32, ptr @foo, align 4
%cmp28 = icmp sgt i32 %0, 0
br i1 %cmp28, label %for.body.lr.ph, label %for.cond1.preheader
for.body.lr.ph: ; preds = %entry
%1 = icmp sgt i32 %0, 1
%smax = select i1 %1, i32 %0, i32 1
- call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([250 x i8], [250 x i8]* @bar, i32 0, i32 0), i8 0, i32 %smax, i1 false)
+ call void @llvm.memset.p0.i32(ptr @bar, i8 0, i32 %smax, i1 false)
call void @llvm.trap()
unreachable
@@ -47,16 +47,16 @@ for.cond1.preheader: ; preds = %entry
ret void
}
-declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) nounwind
+declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) nounwind
; rdar://12462006
-define i8* @f3(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
+define ptr @f3(ptr %base, ptr nocapture %offset, i32 %size) nounwind {
entry:
; CHECK-LABEL: f3:
; CHECK-NOT: sub
; CHECK: cmp
; CHECK: blt
-%0 = load i32, i32* %offset, align 4
+%0 = load i32, ptr %offset, align 4
%cmp = icmp slt i32 %0, %size
%s = sub nsw i32 %0, %size
%size2 = sub nsw i32 %size, 0
@@ -72,17 +72,17 @@ if.end:
; CHECK: add [[R4:r[0-9]+]], [[R1]], [[R3]]
; CHECK-NOT: sub
; CHECK: str
-store i32 %s3, i32* %offset, align 4
-%add.ptr = getelementptr inbounds i8, i8* %base, i32 %sub
+store i32 %s3, ptr %offset, align 4
+%add.ptr = getelementptr inbounds i8, ptr %base, i32 %sub
br label %return
return:
-%retval.0 = phi i8* [ %add.ptr, %if.end ], [ null, %entry ]
-ret i8* %retval.0
+%retval.0 = phi ptr [ %add.ptr, %if.end ], [ null, %entry ]
+ret ptr %retval.0
}
; The cmp of %val should not be hoisted above the preceding conditional branch
-define void @f4(i32** %ptr1, i64* %ptr2, i64 %val) {
+define void @f4(ptr %ptr1, ptr %ptr2, i64 %val) {
entry:
; CHECK-LABEL: f4:
; CHECK: cmp
@@ -92,11 +92,11 @@ entry:
; CHECK-NOT: subs
; CHECK-NOT: sbcs
; CHECK: beq
- %tobool.not = icmp eq i32** %ptr1, null
+ %tobool.not = icmp eq ptr %ptr1, null
br i1 %tobool.not, label %if.end, label %if.then
if.then:
- store i32* null, i32** %ptr1, align 4
+ store ptr null, ptr %ptr1, align 4
br label %if.end
if.end:
@@ -112,7 +112,7 @@ if.end3:
; CHECK: subs
; CHECK: sbc
%sub = add nsw i64 %val, -10
- store i64 %sub, i64* %ptr2, align 8
+ store i64 %sub, ptr %ptr2, align 8
br label %cleanup
cleanup:
diff --git a/llvm/test/CodeGen/ARM/machine-licm.ll b/llvm/test/CodeGen/ARM/machine-licm.ll
index 1cf291be6621d..bb64bcca97904 100644
--- a/llvm/test/CodeGen/ARM/machine-licm.ll
+++ b/llvm/test/CodeGen/ARM/machine-licm.ll
@@ -5,9 +5,9 @@
; rdar://7354376
; rdar://8887598
- at GV = external global i32 ; <i32*> [#uses=2]
+ at GV = external global i32 ; <ptr> [#uses=2]
-define void @t(i32* nocapture %vals, i32 %c) nounwind {
+define void @t(ptr nocapture %vals, i32 %c) nounwind {
entry:
; ARM-LABEL: t:
; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0
@@ -39,16 +39,16 @@ bb.nph: ; preds = %entry
; THUMB: LCPI0_0:
; THUMB-NOT: LCPI0_1:
; THUMB: .section
- %.pre = load i32, i32* @GV, align 4 ; <i32> [#uses=1]
+ %.pre = load i32, ptr @GV, align 4 ; <i32> [#uses=1]
br label %bb
bb: ; preds = %bb, %bb.nph
%1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; <i32> [#uses=1]
%i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; <i32> [#uses=2]
- %scevgep = getelementptr i32, i32* %vals, i32 %i.03 ; <i32*> [#uses=1]
- %2 = load i32, i32* %scevgep, align 4 ; <i32> [#uses=1]
+ %scevgep = getelementptr i32, ptr %vals, i32 %i.03 ; <ptr> [#uses=1]
+ %2 = load i32, ptr %scevgep, align 4 ; <i32> [#uses=1]
%3 = add nsw i32 %1, %2 ; <i32> [#uses=2]
- store i32 %3, i32* @GV, align 4
+ store i32 %3, ptr @GV, align 4
%4 = add i32 %i.03, 1 ; <i32> [#uses=2]
%exitcond = icmp eq i32 %4, %c ; <i1> [#uses=1]
br i1 %exitcond, label %return, label %bb
diff --git a/llvm/test/CodeGen/ARM/machine-outliner-cfi-1.ll b/llvm/test/CodeGen/ARM/machine-outliner-cfi-1.ll
index 67c859c4bea8d..d727a8d3c908f 100644
--- a/llvm/test/CodeGen/ARM/machine-outliner-cfi-1.ll
+++ b/llvm/test/CodeGen/ARM/machine-outliner-cfi-1.ll
@@ -27,15 +27,15 @@ target triple = "thumbv7m-unknown-unknown-eabi"
define dso_local i32 @x() local_unnamed_addr #0 {
entry:
- %0 = load volatile i32, i32* @a, align 4
- %1 = load volatile i32, i32* @b, align 4
+ %0 = load volatile i32, ptr @a, align 4
+ %1 = load volatile i32, ptr @b, align 4
%add = add nsw i32 %1, %0
- %2 = load volatile i32, i32* @c, align 4
- %3 = load volatile i32, i32* @d, align 4
+ %2 = load volatile i32, ptr @c, align 4
+ %3 = load volatile i32, ptr @d, align 4
%add1 = add nsw i32 %3, %2
%div = sdiv i32 %add, %add1
- %4 = load volatile i32, i32* @e, align 4
- %5 = load volatile i32, i32* @f, align 4
+ %4 = load volatile i32, ptr @e, align 4
+ %5 = load volatile i32, ptr @f, align 4
%add2 = add i32 %div, 1
%add3 = add i32 %add2, %4
%add4 = add i32 %add3, %5
@@ -52,15 +52,15 @@ entry:
define dso_local i32 @y() local_unnamed_addr #0 {
entry:
- %0 = load volatile i32, i32* @a, align 4
- %1 = load volatile i32, i32* @b, align 4
+ %0 = load volatile i32, ptr @a, align 4
+ %1 = load volatile i32, ptr @b, align 4
%add = add nsw i32 %1, %0
- %2 = load volatile i32, i32* @c, align 4
- %3 = load volatile i32, i32* @d, align 4
+ %2 = load volatile i32, ptr @c, align 4
+ %3 = load volatile i32, ptr @d, align 4
%add1 = add nsw i32 %3, %2
%div = sdiv i32 %add, %add1
- %4 = load volatile i32, i32* @e, align 4
- %5 = load volatile i32, i32* @f, align 4
+ %4 = load volatile i32, ptr @e, align 4
+ %5 = load volatile i32, ptr @f, align 4
%add2 = add i32 %div, 2
%add3 = add i32 %add2, %4
%add4 = add i32 %add3, %5
diff --git a/llvm/test/CodeGen/ARM/machine-outliner-cfi-2.ll b/llvm/test/CodeGen/ARM/machine-outliner-cfi-2.ll
index e5dee8fd2938c..6098080f9426e 100644
--- a/llvm/test/CodeGen/ARM/machine-outliner-cfi-2.ll
+++ b/llvm/test/CodeGen/ARM/machine-outliner-cfi-2.ll
@@ -26,12 +26,12 @@ target triple = "thumbv7m-unknown-unknown-eabi"
define dso_local i32 @x() local_unnamed_addr #0 {
entry:
- %0 = load volatile i32, i32* @a, align 4
- %1 = load volatile i32, i32* @b, align 4
- %2 = load volatile i32, i32* @c, align 4
- %3 = load volatile i32, i32* @d, align 4
- %4 = load volatile i32, i32* @e, align 4
- %5 = load volatile i32, i32* @f, align 4
+ %0 = load volatile i32, ptr @a, align 4
+ %1 = load volatile i32, ptr @b, align 4
+ %2 = load volatile i32, ptr @c, align 4
+ %3 = load volatile i32, ptr @d, align 4
+ %4 = load volatile i32, ptr @e, align 4
+ %5 = load volatile i32, ptr @f, align 4
%add = add i32 %0, 1
%add1 = add i32 %add, %1
%add2 = add i32 %add1, %2
@@ -49,12 +49,12 @@ entry:
define dso_local i32 @y() local_unnamed_addr #0 {
entry:
- %0 = load volatile i32, i32* @a, align 4
- %1 = load volatile i32, i32* @b, align 4
- %2 = load volatile i32, i32* @c, align 4
- %3 = load volatile i32, i32* @d, align 4
- %4 = load volatile i32, i32* @e, align 4
- %5 = load volatile i32, i32* @f, align 4
+ %0 = load volatile i32, ptr @a, align 4
+ %1 = load volatile i32, ptr @b, align 4
+ %2 = load volatile i32, ptr @c, align 4
+ %3 = load volatile i32, ptr @d, align 4
+ %4 = load volatile i32, ptr @e, align 4
+ %5 = load volatile i32, ptr @f, align 4
%add = add i32 %0, 2
%add1 = add i32 %add, %1
%add2 = add i32 %add1, %2
diff --git a/llvm/test/CodeGen/ARM/machine-outliner-tail.ll b/llvm/test/CodeGen/ARM/machine-outliner-tail.ll
index 30355988e8563..407681bb795d2 100644
--- a/llvm/test/CodeGen/ARM/machine-outliner-tail.ll
+++ b/llvm/test/CodeGen/ARM/machine-outliner-tail.ll
@@ -41,7 +41,7 @@ entry:
declare void @z(i32, i32, i32, i32)
-define dso_local void @b(i32* nocapture readnone %p) #0 {
+define dso_local void @b(ptr nocapture readnone %p) #0 {
entry:
tail call void @z(i32 1, i32 2, i32 3, i32 4)
ret void
diff --git a/llvm/test/CodeGen/ARM/machine-sink-multidef.ll b/llvm/test/CodeGen/ARM/machine-sink-multidef.ll
index a287373c695db..6e3a5731c69b4 100644
--- a/llvm/test/CodeGen/ARM/machine-sink-multidef.ll
+++ b/llvm/test/CodeGen/ARM/machine-sink-multidef.ll
@@ -31,11 +31,11 @@ define arm_aapcscc void @g() {
; CHECK-NEXT: .LCPI0_1:
; CHECK-NEXT: .long e
entry:
- %0 = load i32, i32* @f, align 4
- %c = getelementptr inbounds [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95], [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95]* @e, i32 0, i32 %0, i32 0
- %1 = load i32, i32* %c, align 4
- %d = getelementptr inbounds [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95], [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95]* @e, i32 0, i32 %0, i32 1
- %2 = load i32, i32* %d, align 4
+ %0 = load i32, ptr @f, align 4
+ %c = getelementptr inbounds [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95], ptr @e, i32 0, i32 %0, i32 0
+ %1 = load i32, ptr %c, align 4
+ %d = getelementptr inbounds [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95], ptr @e, i32 0, i32 %0, i32 1
+ %2 = load i32, ptr %d, align 4
br i1 undef, label %land.lhs.true, label %if.end
land.lhs.true: ; preds = %entry
@@ -46,7 +46,7 @@ if.end: ; preds = %land.lhs.true, %ent
br i1 undef, label %if.end7, label %if.then5
if.then5: ; preds = %if.end
- %call6 = call arm_aapcscc i32 bitcast (i32 (...)* @k to i32 (i32, i32)*)(i32 %h.0, i32 %2)
+ %call6 = call arm_aapcscc i32 @k(i32 %h.0, i32 %2)
unreachable
if.end7: ; preds = %if.end
diff --git a/llvm/test/CodeGen/ARM/macho-extern-hidden.ll b/llvm/test/CodeGen/ARM/macho-extern-hidden.ll
index 6a45f008bf362..f0369e70fd183 100644
--- a/llvm/test/CodeGen/ARM/macho-extern-hidden.ll
+++ b/llvm/test/CodeGen/ARM/macho-extern-hidden.ll
@@ -5,6 +5,6 @@
@bar = external hidden global i32
define i32 @foo() {
- %tmp = load i32, i32* @bar, align 4
+ %tmp = load i32, ptr @bar, align 4
ret i32 %tmp
}
diff --git a/llvm/test/CodeGen/ARM/mbp.ll b/llvm/test/CodeGen/ARM/mbp.ll
index 3741b4b4c500f..e7ab3860b52ac 100644
--- a/llvm/test/CodeGen/ARM/mbp.ll
+++ b/llvm/test/CodeGen/ARM/mbp.ll
@@ -2,8 +2,8 @@
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv7-unknown-linux-gnueabihf"
-%Target = type { %Target*, %List* }
-%List = type { i32, i32* }
+%Target = type { ptr, ptr }
+%List = type { i32, ptr }
; The entry block should be the first block of the function.
; CHECK-LABEL: foo
@@ -15,24 +15,23 @@ target triple = "thumbv7-unknown-linux-gnueabihf"
; CHECK: %for.body.i
; CHECK: %return
-define i1 @foo(%Target** %ha, i32 %he) !prof !39 {
+define i1 @foo(ptr %ha, i32 %he) !prof !39 {
entry:
- %TargetPtr = load %Target*, %Target** %ha, align 4
- %cmp1 = icmp eq %Target* %TargetPtr, null
+ %TargetPtr = load ptr, ptr %ha, align 4
+ %cmp1 = icmp eq ptr %TargetPtr, null
br i1 %cmp1, label %return, label %for.body, !prof !50
for.body:
- %TargetPhi = phi %Target* [ %NextPtr, %for.inc ], [ %TargetPtr, %entry ]
- %ListAddr = getelementptr inbounds %Target, %Target* %TargetPhi, i32 0, i32 1
- %ListPtr = load %List*, %List** %ListAddr, align 4
- %cmp2 = icmp eq %List* %ListPtr, null
+ %TargetPhi = phi ptr [ %NextPtr, %for.inc ], [ %TargetPtr, %entry ]
+ %ListAddr = getelementptr inbounds %Target, ptr %TargetPhi, i32 0, i32 1
+ %ListPtr = load ptr, ptr %ListAddr, align 4
+ %cmp2 = icmp eq ptr %ListPtr, null
br i1 %cmp2, label %for.inc, label %if.then, !prof !59
if.then:
- %lenAddr = getelementptr inbounds %List, %List* %ListPtr, i32 0, i32 0
- %len = load i32, i32* %lenAddr, align 4
- %ptr = getelementptr inbounds %List, %List* %ListPtr, i32 0, i32 1
- %ptr2 = load i32*, i32** %ptr, align 4
+ %len = load i32, ptr %ListPtr, align 4
+ %ptr = getelementptr inbounds %List, ptr %ListPtr, i32 0, i32 1
+ %ptr2 = load ptr, ptr %ptr, align 4
br label %for.cond.i
for.cond.i:
@@ -42,15 +41,14 @@ for.cond.i:
br i1 %cmp3, label %for.body.i, label %for.inc, !prof !75
for.body.i:
- %ptr3 = getelementptr inbounds i32, i32* %ptr2, i32 %index
- %data = load i32, i32* %ptr3, align 4
+ %ptr3 = getelementptr inbounds i32, ptr %ptr2, i32 %index
+ %data = load i32, ptr %ptr3, align 4
%cmp4 = icmp eq i32 %data, %he
br i1 %cmp4, label %return, label %for.cond.i, !prof !79
for.inc:
- %NextAddr = getelementptr inbounds %Target, %Target* %TargetPhi, i32 0, i32 0
- %NextPtr = load %Target*, %Target** %NextAddr, align 4
- %cmp5 = icmp eq %Target* %NextPtr, null
+ %NextPtr = load ptr, ptr %TargetPhi, align 4
+ %cmp5 = icmp eq ptr %NextPtr, null
br i1 %cmp5, label %return, label %for.body, !prof !50
return:
diff --git a/llvm/test/CodeGen/ARM/mem.ll b/llvm/test/CodeGen/ARM/mem.ll
index 3c9cd913add65..7d50da8db7ae9 100644
--- a/llvm/test/CodeGen/ARM/mem.ll
+++ b/llvm/test/CodeGen/ARM/mem.ll
@@ -2,7 +2,7 @@
define void @f1() {
entry:
- store i8 0, i8* null
+ store i8 0, ptr null
ret void
}
@@ -10,7 +10,7 @@ entry:
define void @f2() {
entry:
- store i16 0, i16* null
+ store i16 0, ptr null
ret void
}
diff --git a/llvm/test/CodeGen/ARM/memcpy-const-vol-struct.ll b/llvm/test/CodeGen/ARM/memcpy-const-vol-struct.ll
index 74f675876834a..51cb148206b12 100644
--- a/llvm/test/CodeGen/ARM/memcpy-const-vol-struct.ll
+++ b/llvm/test/CodeGen/ARM/memcpy-const-vol-struct.ll
@@ -7,7 +7,7 @@
define hidden void @InitVal() local_unnamed_addr {
entry:
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 bitcast (%struct.sMyType* @v to i8*), i8* align 4 bitcast (%struct.sMyType* @val to i8*), i32 4, i1 true)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 4 @v, ptr align 4 @val, i32 4, i1 true)
; The last argument is the isvolatile argument. This is a volatile memcpy.
; Test that the memcpy expansion does not optimize away the load.
; CHECK: ldr
@@ -15,4 +15,4 @@ entry:
ret void
}
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i32, i1 immarg)
+declare void @llvm.memcpy.p0.p0.i32(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i32, i1 immarg)
diff --git a/llvm/test/CodeGen/ARM/memcpy-inline.ll b/llvm/test/CodeGen/ARM/memcpy-inline.ll
index f4ed4fe0b7bfb..596a58afe46e5 100644
--- a/llvm/test/CodeGen/ARM/memcpy-inline.ll
+++ b/llvm/test/CodeGen/ARM/memcpy-inline.ll
@@ -55,11 +55,11 @@ define i32 @t0() {
; CHECK-T1-NEXT: .LCPI0_1:
; CHECK-T1-NEXT: .long dst
entry:
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 getelementptr inbounds (%struct.x, %struct.x* @dst, i32 0, i32 0), i8* align 8 getelementptr inbounds (%struct.x, %struct.x* @src, i32 0, i32 0), i32 11, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 8 @dst, ptr align 8 @src, i32 11, i1 false)
ret i32 0
}
-define void @t1(i8* nocapture %C) nounwind {
+define void @t1(ptr nocapture %C) nounwind {
; CHECK-LABEL: t1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movw r1, :lower16:(L_.str1-(LPC1_0+4))
@@ -86,11 +86,11 @@ define void @t1(i8* nocapture %C) nounwind {
; CHECK-T1-NEXT: .LCPI1_0:
; CHECK-T1-NEXT: .long .L.str1
entry:
- tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str1, i64 0, i64 0), i64 31, i1 false)
+ tail call void @llvm.memcpy.p0.p0.i64(ptr %C, ptr @.str1, i64 31, i1 false)
ret void
}
-define void @t2(i8* nocapture %C) nounwind {
+define void @t2(ptr nocapture %C) nounwind {
; CHECK-LABEL: t2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movw r1, :lower16:(L_.str2-(LPC2_0+4))
@@ -119,11 +119,11 @@ define void @t2(i8* nocapture %C) nounwind {
; CHECK-T1-NEXT: .LCPI2_0:
; CHECK-T1-NEXT: .long .L.str2
entry:
- tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8], [36 x i8]* @.str2, i64 0, i64 0), i64 36, i1 false)
+ tail call void @llvm.memcpy.p0.p0.i64(ptr %C, ptr @.str2, i64 36, i1 false)
ret void
}
-define void @t3(i8* nocapture %C) nounwind {
+define void @t3(ptr nocapture %C) nounwind {
; CHECK-LABEL: t3:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movw r1, :lower16:(L_.str3-(LPC3_0+4))
@@ -149,11 +149,11 @@ define void @t3(i8* nocapture %C) nounwind {
; CHECK-T1-NEXT: .LCPI3_0:
; CHECK-T1-NEXT: .long .L.str3
entry:
- tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str3, i64 0, i64 0), i64 24, i1 false)
+ tail call void @llvm.memcpy.p0.p0.i64(ptr %C, ptr @.str3, i64 24, i1 false)
ret void
}
-define void @t4(i8* nocapture %C) nounwind {
+define void @t4(ptr nocapture %C) nounwind {
; CHECK-LABEL: t4:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movw r1, :lower16:(L_.str4-(LPC4_0+4))
@@ -179,11 +179,11 @@ define void @t4(i8* nocapture %C) nounwind {
; CHECK-T1-NEXT: .LCPI4_0:
; CHECK-T1-NEXT: .long .L.str4
entry:
- tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str4, i64 0, i64 0), i64 18, i1 false)
+ tail call void @llvm.memcpy.p0.p0.i64(ptr %C, ptr @.str4, i64 18, i1 false)
ret void
}
-define void @t5(i8* nocapture %C) nounwind {
+define void @t5(ptr nocapture %C) nounwind {
; CHECK-LABEL: t5:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movw r1, #21337
@@ -207,7 +207,7 @@ define void @t5(i8* nocapture %C) nounwind {
; CHECK-T1-NEXT: .LCPI5_0:
; CHECK-T1-NEXT: .long .L.str5
entry:
- tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str5, i64 0, i64 0), i64 7, i1 false)
+ tail call void @llvm.memcpy.p0.p0.i64(ptr %C, ptr @.str5, i64 7, i1 false)
ret void
}
@@ -253,13 +253,13 @@ define void @t6() nounwind {
; CHECK-T1-NEXT: .LCPI6_3:
; CHECK-T1-NEXT: .long 1886221359 @ 0x706d742f
entry:
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([512 x i8], [512 x i8]* @spool.splbuf, i64 0, i64 0), i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str6, i64 0, i64 0), i64 14, i1 false)
+ call void @llvm.memcpy.p0.p0.i64(ptr @spool.splbuf, ptr @.str6, i64 14, i1 false)
ret void
}
%struct.Foo = type { i32, i32, i32, i32 }
-define void @t7(%struct.Foo* nocapture %a, %struct.Foo* nocapture %b) nounwind {
+define void @t7(ptr nocapture %a, ptr nocapture %b) nounwind {
; CHECK-LABEL: t7:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.32 {d16, d17}, [r1]
@@ -278,11 +278,9 @@ define void @t7(%struct.Foo* nocapture %a, %struct.Foo* nocapture %b) nounwind {
; CHECK-T1-NEXT: str r1, [r0]
; CHECK-T1-NEXT: bx lr
entry:
- %0 = bitcast %struct.Foo* %a to i8*
- %1 = bitcast %struct.Foo* %b to i8*
- tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 %1, i32 16, i1 false)
+ tail call void @llvm.memcpy.p0.p0.i32(ptr align 4 %a, ptr align 4 %b, i32 16, i1 false)
ret void
}
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
-declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
+declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind
diff --git a/llvm/test/CodeGen/ARM/memcpy-ldm-stm.ll b/llvm/test/CodeGen/ARM/memcpy-ldm-stm.ll
index 77d2efb50a92b..3f0b0611e2f48 100644
--- a/llvm/test/CodeGen/ARM/memcpy-ldm-stm.ll
+++ b/llvm/test/CodeGen/ARM/memcpy-ldm-stm.ll
@@ -24,7 +24,7 @@ entry:
; Think of the monstrosity '[[[LB]]]' as '[ [[LB]] ]' without the spaces.
; CHECK-NEXT: ldrb{{(\.w)?}} {{.*}}, [[[LB]]]
; CHECK-NEXT: strb{{(\.w)?}} {{.*}}, [[[SB]]]
- tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 bitcast ([64 x i32]* @s to i8*), i8* align 4 bitcast ([64 x i32]* @d to i8*), i32 17, i1 false)
+ tail call void @llvm.memcpy.p0.p0.i32(ptr align 4 @s, ptr align 4 @d, i32 17, i1 false)
ret void
}
@@ -44,7 +44,7 @@ entry:
; CHECKV7-NEXT: movt [[SB:[rl0-9]+]], :upper16:s
; CHECKV7: ldr{{(\.w)?}} {{.*}}, [[[LB]], #11]
; CHECKV7-NEXT: str{{(\.w)?}} {{.*}}, [[[SB]], #11]
- tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 bitcast ([64 x i32]* @s to i8*), i8* align 4 bitcast ([64 x i32]* @d to i8*), i32 15, i1 false)
+ tail call void @llvm.memcpy.p0.p0.i32(ptr align 4 @s, ptr align 4 @d, i32 15, i1 false)
ret void
}
@@ -55,13 +55,13 @@ entry:
@etest = external global %struct.T, align 8
define void @t3() {
- call void @llvm.memcpy.p0i8.p0i8.i32(
- i8* align 8 getelementptr inbounds (%struct.T, %struct.T* @copy, i32 0, i32 0),
- i8* align 8 getelementptr inbounds (%struct.T, %struct.T* @etest, i32 0, i32 0),
+ call void @llvm.memcpy.p0.p0.i32(
+ ptr align 8 @copy,
+ ptr align 8 @etest,
i32 24, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i32(
- i8* align 8 getelementptr inbounds (%struct.T, %struct.T* @copy, i32 0, i32 0),
- i8* align 8 getelementptr inbounds (%struct.T, %struct.T* @etest, i32 0, i32 0),
+ call void @llvm.memcpy.p0.p0.i32(
+ ptr align 8 @copy,
+ ptr align 8 @etest,
i32 24, i1 false)
ret void
}
@@ -69,10 +69,8 @@ define void @t3() {
%struct.S = type { [12 x i32] }
; CHECK-LABEL: test3
-define void @test3(%struct.S* %d, %struct.S* %s) #0 {
- %1 = bitcast %struct.S* %d to i8*
- %2 = bitcast %struct.S* %s to i8*
- tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %1, i8* align 4 %2, i32 48, i1 false)
+define void @test3(ptr %d, ptr %s) #0 {
+ tail call void @llvm.memcpy.p0.p0.i32(ptr align 4 %d, ptr align 4 %s, i32 48, i1 false)
; 3 ldm/stm pairs in v6; 2 in v7
; CHECK: ldm{{(\.w)?}} {{[rl0-9]+!?}}, [[REGLIST1:{.*}]]
; CHECK: stm{{(\.w)?}} {{[rl0-9]+!?}}, [[REGLIST1]]
@@ -82,15 +80,15 @@ define void @test3(%struct.S* %d, %struct.S* %s) #0 {
; CHECKV6: stm {{r[0-7]!?}}, [[REGLIST3]]
; CHECKV7-NOT: ldm
; CHECKV7-NOT: stm
- %arrayidx = getelementptr inbounds %struct.S, %struct.S* %s, i32 0, i32 0, i32 1
- tail call void @g(i32* %arrayidx) #3
+ %arrayidx = getelementptr inbounds %struct.S, ptr %s, i32 0, i32 0, i32 1
+ tail call void @g(ptr %arrayidx) #3
ret void
}
-declare void @g(i32*)
+declare void @g(ptr)
; Set "frame-pointer"="all" to increase register pressure
attributes #0 = { "frame-pointer"="all" }
; Function Attrs: nounwind
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1) #1
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture readonly, i32, i1) #1
diff --git a/llvm/test/CodeGen/ARM/memcpy-no-inline.ll b/llvm/test/CodeGen/ARM/memcpy-no-inline.ll
index 7aaac19eee3f1..43d640a4058a7 100644
--- a/llvm/test/CodeGen/ARM/memcpy-no-inline.ll
+++ b/llvm/test/CodeGen/ARM/memcpy-no-inline.ll
@@ -13,8 +13,7 @@ entry:
; CHECK: __aeabi_memcpy
; CHECK-NOT: ldm
%mystring = alloca [31 x i8], align 1
- %0 = getelementptr inbounds [31 x i8], [31 x i8]* %mystring, i32 0, i32 0
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %0, i8* align 1 getelementptr inbounds ([31 x i8], [31 x i8]* @.str, i32 0, i32 0), i32 31, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 %mystring, ptr align 1 @.str, i32 31, i1 false)
ret void
}
@@ -23,11 +22,10 @@ entry:
; CHECK-LABEL: bar:
; CHECK-NOT: __aeabi_memcpy
%mystring = alloca [31 x i8], align 1
- %0 = getelementptr inbounds [31 x i8], [31 x i8]* %mystring, i32 0, i32 0
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %0, i8* align 1 getelementptr inbounds ([21 x i8], [21 x i8]* @.str.1, i32 0, i32 0), i32 21, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 %mystring, ptr align 1 @.str.1, i32 21, i1 false)
ret void
}
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1) #1
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture readonly, i32, i1) #1
attributes #0 = { minsize noinline nounwind optsize }
diff --git a/llvm/test/CodeGen/ARM/memfunc.ll b/llvm/test/CodeGen/ARM/memfunc.ll
index 217b88a32de06..dfd86a2691cd5 100644
--- a/llvm/test/CodeGen/ARM/memfunc.ll
+++ b/llvm/test/CodeGen/ARM/memfunc.ll
@@ -8,7 +8,7 @@
; RUN: llc < %s -mtriple=arm-none-musleabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI --check-prefix=CHECK
; RUN: llc < %s -mtriple=arm-none-musleabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI --check-prefix=CHECK
-define void @f1(i8* %dest, i8* %src) "frame-pointer"="all" {
+define void @f1(ptr %dest, ptr %src) "frame-pointer"="all" {
entry:
; CHECK-LABEL: f1
@@ -16,13 +16,13 @@ entry:
; CHECK-DARWIN: bl _memmove
; CHECK-EABI: bl __aeabi_memmove
; CHECK-GNUEABI: bl memmove
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i1 false)
+ call void @llvm.memmove.p0.p0.i32(ptr %dest, ptr %src, i32 500, i1 false)
; CHECK-IOS: bl _memcpy
; CHECK-DARWIN: bl _memcpy
; CHECK-EABI: bl __aeabi_memcpy
; CHECK-GNUEABI: bl memcpy
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr %src, i32 500, i1 false)
; EABI memset swaps arguments
; CHECK-IOS: mov r1, #1
@@ -33,7 +33,7 @@ entry:
; CHECK-EABI: bl __aeabi_memset
; CHECK-GNUEABI: mov r1, #1
; CHECK-GNUEABI: bl memset
- call void @llvm.memset.p0i8.i32(i8* %dest, i8 1, i32 500, i1 false)
+ call void @llvm.memset.p0.i32(ptr %dest, i8 1, i32 500, i1 false)
; EABI uses memclr if value set to 0
; CHECK-IOS: mov r1, #0
@@ -42,7 +42,7 @@ entry:
; CHECK-DARWIN: bl _memset
; CHECK-EABI: bl __aeabi_memclr
; CHECK-GNUEABI: bl memset
- call void @llvm.memset.p0i8.i32(i8* %dest, i8 0, i32 500, i1 false)
+ call void @llvm.memset.p0.i32(ptr %dest, i8 0, i32 500, i1 false)
; EABI uses aligned function variants if possible
@@ -50,55 +50,55 @@ entry:
; CHECK-DARWIN: bl _memmove
; CHECK-EABI: bl __aeabi_memmove4
; CHECK-GNUEABI: bl memmove
- call void @llvm.memmove.p0i8.p0i8.i32(i8* align 4 %dest, i8* align 4 %src, i32 500, i1 false)
+ call void @llvm.memmove.p0.p0.i32(ptr align 4 %dest, ptr align 4 %src, i32 500, i1 false)
; CHECK-IOS: bl _memcpy
; CHECK-DARWIN: bl _memcpy
; CHECK-EABI: bl __aeabi_memcpy4
; CHECK-GNUEABI: bl memcpy
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %dest, i8* align 4 %src, i32 500, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 4 %dest, ptr align 4 %src, i32 500, i1 false)
; CHECK-IOS: bl _memset
; CHECK-DARWIN: bl _memset
; CHECK-EABI: bl __aeabi_memset4
; CHECK-GNUEABI: bl memset
- call void @llvm.memset.p0i8.i32(i8* align 4 %dest, i8 1, i32 500, i1 false)
+ call void @llvm.memset.p0.i32(ptr align 4 %dest, i8 1, i32 500, i1 false)
; CHECK-IOS: bl _memset
; CHECK-DARWIN: bl _memset
; CHECK-EABI: bl __aeabi_memclr4
; CHECK-GNUEABI: bl memset
- call void @llvm.memset.p0i8.i32(i8* align 4 %dest, i8 0, i32 500, i1 false)
+ call void @llvm.memset.p0.i32(ptr align 4 %dest, i8 0, i32 500, i1 false)
; CHECK-IOS: bl _memmove
; CHECK-DARWIN: bl _memmove
; CHECK-EABI: bl __aeabi_memmove8
; CHECK-GNUEABI: bl memmove
- call void @llvm.memmove.p0i8.p0i8.i32(i8* align 8 %dest, i8* align 8 %src, i32 500, i1 false)
+ call void @llvm.memmove.p0.p0.i32(ptr align 8 %dest, ptr align 8 %src, i32 500, i1 false)
; CHECK-IOS: bl _memcpy
; CHECK-DARWIN: bl _memcpy
; CHECK-EABI: bl __aeabi_memcpy8
; CHECK-GNUEABI: bl memcpy
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %dest, i8* align 8 %src, i32 500, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 8 %dest, ptr align 8 %src, i32 500, i1 false)
; CHECK-IOS: bl _memset
; CHECK-DARWIN: bl _memset
; CHECK-EABI: bl __aeabi_memset8
; CHECK-GNUEABI: bl memset
- call void @llvm.memset.p0i8.i32(i8* align 8 %dest, i8 1, i32 500, i1 false)
+ call void @llvm.memset.p0.i32(ptr align 8 %dest, i8 1, i32 500, i1 false)
; CHECK-IOS: bl _memset
; CHECK-DARWIN: bl _memset
; CHECK-EABI: bl __aeabi_memclr8
; CHECK-GNUEABI: bl memset
- call void @llvm.memset.p0i8.i32(i8* align 8 %dest, i8 0, i32 500, i1 false)
+ call void @llvm.memset.p0.i32(ptr align 8 %dest, i8 0, i32 500, i1 false)
ret void
}
; Check that alloca arguments to memory intrinsics are automatically aligned if at least 8 bytes in size
-define void @f2(i8* %dest, i32 %n) "frame-pointer"="all" {
+define void @f2(ptr %dest, i32 %n) "frame-pointer"="all" {
entry:
; CHECK-LABEL: f2
@@ -112,8 +112,7 @@ entry:
; CHECK-GNUEABI: {{add r1, sp, #28|sub r1, r(7|11), #20}}
; CHECK-GNUEABI: bl memmove
%arr0 = alloca [9 x i8], align 1
- %0 = bitcast [9 x i8]* %arr0 to i8*
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i1 false)
+ call void @llvm.memmove.p0.p0.i32(ptr %dest, ptr %arr0, i32 %n, i1 false)
; CHECK: add r1, sp, #16
; CHECK-IOS: bl _memcpy
@@ -121,8 +120,7 @@ entry:
; CHECK-EABI: bl __aeabi_memcpy
; CHECK-GNUEABI: bl memcpy
%arr1 = alloca [9 x i8], align 1
- %1 = bitcast [9 x i8]* %arr1 to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr %arr1, i32 %n, i1 false)
; CHECK-IOS: mov r0, sp
; CHECK-IOS: mov r1, #1
@@ -137,14 +135,13 @@ entry:
; CHECK-GNUEABI: mov r1, #1
; CHECK-GNUEABI: bl memset
%arr2 = alloca [9 x i8], align 1
- %2 = bitcast [9 x i8]* %arr2 to i8*
- call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i1 false)
+ call void @llvm.memset.p0.i32(ptr %arr2, i8 1, i32 %n, i1 false)
ret void
}
; Check that alloca arguments are not aligned if less than 8 bytes in size
-define void @f3(i8* %dest, i32 %n) "frame-pointer"="all" {
+define void @f3(ptr %dest, i32 %n) "frame-pointer"="all" {
entry:
; CHECK-LABEL: f3
@@ -154,8 +151,7 @@ entry:
; CHECK-EABI: bl __aeabi_memmove
; CHECK-GNUEABI: bl memmove
%arr0 = alloca [7 x i8], align 1
- %0 = bitcast [7 x i8]* %arr0 to i8*
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i1 false)
+ call void @llvm.memmove.p0.p0.i32(ptr %dest, ptr %arr0, i32 %n, i1 false)
; CHECK: {{add(.w)? r1, sp, #10|sub(.w)? r1, r(7|11), #22}}
; CHECK-IOS: bl _memcpy
@@ -163,8 +159,7 @@ entry:
; CHECK-EABI: bl __aeabi_memcpy
; CHECK-GNUEABI: bl memcpy
%arr1 = alloca [7 x i8], align 1
- %1 = bitcast [7 x i8]* %arr1 to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr %arr1, i32 %n, i1 false)
; CHECK: {{add(.w)? r0, sp, #3|sub(.w)? r0, r(7|11), #29}}
; CHECK-IOS: mov r1, #1
@@ -176,14 +171,13 @@ entry:
; CHECK-GNUEABI: mov r1, #1
; CHECK-GNUEABI: bl memset
%arr2 = alloca [7 x i8], align 1
- %2 = bitcast [7 x i8]* %arr2 to i8*
- call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i1 false)
+ call void @llvm.memset.p0.i32(ptr %arr2, i8 1, i32 %n, i1 false)
ret void
}
; Check that alloca arguments are not aligned if size+offset is less than 8 bytes
-define void @f4(i8* %dest, i32 %n) "frame-pointer"="all" {
+define void @f4(ptr %dest, i32 %n) "frame-pointer"="all" {
entry:
; CHECK-LABEL: f4
@@ -193,8 +187,8 @@ entry:
; CHECK-EABI: bl __aeabi_memmove
; CHECK-GNUEABI: bl memmove
%arr0 = alloca [9 x i8], align 1
- %0 = getelementptr inbounds [9 x i8], [9 x i8]* %arr0, i32 0, i32 4
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i1 false)
+ %0 = getelementptr inbounds [9 x i8], ptr %arr0, i32 0, i32 4
+ call void @llvm.memmove.p0.p0.i32(ptr %dest, ptr %0, i32 %n, i1 false)
; CHECK: {{add(.w)? r., sp, #(10|14)|sub(.w) r., r(7|11), #26}}
; CHECK-IOS: bl _memcpy
@@ -202,8 +196,8 @@ entry:
; CHECK-EABI: bl __aeabi_memcpy
; CHECK-GNUEABI: bl memcpy
%arr1 = alloca [9 x i8], align 1
- %1 = getelementptr inbounds [9 x i8], [9 x i8]* %arr1, i32 0, i32 4
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i1 false)
+ %1 = getelementptr inbounds [9 x i8], ptr %arr1, i32 0, i32 4
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr %1, i32 %n, i1 false)
; CHECK: {{add(.w)? r., sp, #(1|5)|sub(.w) r., r(7|11), #35}}
; CHECK-IOS: mov r1, #1
@@ -215,14 +209,14 @@ entry:
; CHECK-GNUEABI: mov r1, #1
; CHECK-GNUEABI: bl memset
%arr2 = alloca [9 x i8], align 1
- %2 = getelementptr inbounds [9 x i8], [9 x i8]* %arr2, i32 0, i32 4
- call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i1 false)
+ %2 = getelementptr inbounds [9 x i8], ptr %arr2, i32 0, i32 4
+ call void @llvm.memset.p0.i32(ptr %2, i8 1, i32 %n, i1 false)
ret void
}
; Check that alloca arguments are not aligned if the offset is not a multiple of 4
-define void @f5(i8* %dest, i32 %n) "frame-pointer"="all" {
+define void @f5(ptr %dest, i32 %n) "frame-pointer"="all" {
entry:
; CHECK-LABEL: f5
@@ -232,8 +226,8 @@ entry:
; CHECK-EABI: bl __aeabi_memmove
; CHECK-GNUEABI: bl memmove
%arr0 = alloca [13 x i8], align 1
- %0 = getelementptr inbounds [13 x i8], [13 x i8]* %arr0, i32 0, i32 1
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i1 false)
+ %0 = getelementptr inbounds [13 x i8], ptr %arr0, i32 0, i32 1
+ call void @llvm.memmove.p0.p0.i32(ptr %dest, ptr %0, i32 %n, i1 false)
; CHECK: {{add(.w)? r., sp, #(10|14)|sub(.w)? r., r(7|11), #34}}
; CHECK-IOS: bl _memcpy
@@ -241,8 +235,8 @@ entry:
; CHECK-EABI: bl __aeabi_memcpy
; CHECK-GNUEABI: bl memcpy
%arr1 = alloca [13 x i8], align 1
- %1 = getelementptr inbounds [13 x i8], [13 x i8]* %arr1, i32 0, i32 1
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i1 false)
+ %1 = getelementptr inbounds [13 x i8], ptr %arr1, i32 0, i32 1
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr %1, i32 %n, i1 false)
; CHECK: {{add(.w)? r., sp, #(1|5)|sub(.w)? r., r(7|11), #47}}
; CHECK-IOS: mov r1, #1
@@ -254,14 +248,14 @@ entry:
; CHECK-GNUEABI: mov r1, #1
; CHECK-GNUEABI: bl memset
%arr2 = alloca [13 x i8], align 1
- %2 = getelementptr inbounds [13 x i8], [13 x i8]* %arr2, i32 0, i32 1
- call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i1 false)
+ %2 = getelementptr inbounds [13 x i8], ptr %arr2, i32 0, i32 1
+ call void @llvm.memset.p0.i32(ptr %2, i8 1, i32 %n, i1 false)
ret void
}
; Check that alloca arguments are not aligned if the offset is unknown
-define void @f6(i8* %dest, i32 %n, i32 %i) "frame-pointer"="all" {
+define void @f6(ptr %dest, i32 %n, i32 %i) "frame-pointer"="all" {
entry:
; CHECK-LABEL: f6
@@ -271,8 +265,8 @@ entry:
; CHECK-EABI: bl __aeabi_memmove
; CHECK-GNUEABI: bl memmove
%arr0 = alloca [13 x i8], align 1
- %0 = getelementptr inbounds [13 x i8], [13 x i8]* %arr0, i32 0, i32 %i
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i1 false)
+ %0 = getelementptr inbounds [13 x i8], ptr %arr0, i32 0, i32 %i
+ call void @llvm.memmove.p0.p0.i32(ptr %dest, ptr %0, i32 %n, i1 false)
; CHECK: {{add(.w)? r., sp, #(10|14)|sub(.w)? r., r(7|11), #42}}
; CHECK-IOS: bl _memcpy
@@ -280,8 +274,8 @@ entry:
; CHECK-EABI: bl __aeabi_memcpy
; CHECK-GNUEABI: bl memcpy
%arr1 = alloca [13 x i8], align 1
- %1 = getelementptr inbounds [13 x i8], [13 x i8]* %arr1, i32 0, i32 %i
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i1 false)
+ %1 = getelementptr inbounds [13 x i8], ptr %arr1, i32 0, i32 %i
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr %1, i32 %n, i1 false)
; CHECK: {{add(.w)? r., sp, #(1|5)|sub(.w)? r., r(7|11), #55}}
; CHECK-IOS: mov r1, #1
@@ -293,14 +287,14 @@ entry:
; CHECK-GNUEABI: mov r1, #1
; CHECK-GNUEABI: bl memset
%arr2 = alloca [13 x i8], align 1
- %2 = getelementptr inbounds [13 x i8], [13 x i8]* %arr2, i32 0, i32 %i
- call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i1 false)
+ %2 = getelementptr inbounds [13 x i8], ptr %arr2, i32 0, i32 %i
+ call void @llvm.memset.p0.i32(ptr %2, i8 1, i32 %n, i1 false)
ret void
}
; Check that alloca arguments are not aligned if the GEP is not inbounds
-define void @f7(i8* %dest, i32 %n) "frame-pointer"="all" {
+define void @f7(ptr %dest, i32 %n) "frame-pointer"="all" {
entry:
; CHECK-LABEL: f7
@@ -310,8 +304,8 @@ entry:
; CHECK-EABI: bl __aeabi_memmove
; CHECK-GNUEABI: bl memmove
%arr0 = alloca [13 x i8], align 1
- %0 = getelementptr [13 x i8], [13 x i8]* %arr0, i32 0, i32 4
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i1 false)
+ %0 = getelementptr [13 x i8], ptr %arr0, i32 0, i32 4
+ call void @llvm.memmove.p0.p0.i32(ptr %dest, ptr %0, i32 %n, i1 false)
; CHECK: {{add(.w)? r., sp, #(10|14)|sub(.w)? r., r(7|11), #34}}
; CHECK-IOS: bl _memcpy
@@ -319,8 +313,8 @@ entry:
; CHECK-EABI: bl __aeabi_memcpy
; CHECK-GNUEABI: bl memcpy
%arr1 = alloca [13 x i8], align 1
- %1 = getelementptr [13 x i8], [13 x i8]* %arr1, i32 0, i32 4
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i1 false)
+ %1 = getelementptr [13 x i8], ptr %arr1, i32 0, i32 4
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr %1, i32 %n, i1 false)
; CHECK: {{add(.w)? r., sp, #(1|5)|sub(.w)? r., r(7|11), #47}}
; CHECK-IOS: mov r1, #1
@@ -332,14 +326,14 @@ entry:
; CHECK-GNUEABI: mov r1, #1
; CHECK-GNUEABI: bl memset
%arr2 = alloca [13 x i8], align 1
- %2 = getelementptr [13 x i8], [13 x i8]* %arr2, i32 0, i32 4
- call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i1 false)
+ %2 = getelementptr [13 x i8], ptr %arr2, i32 0, i32 4
+ call void @llvm.memset.p0.i32(ptr %2, i8 1, i32 %n, i1 false)
ret void
}
; Check that alloca arguments are not aligned when the offset is past the end of the allocation
-define void @f8(i8* %dest, i32 %n) "frame-pointer"="all" {
+define void @f8(ptr %dest, i32 %n) "frame-pointer"="all" {
entry:
; CHECK-LABEL: f8
@@ -349,8 +343,8 @@ entry:
; CHECK-EABI: bl __aeabi_memmove
; CHECK-GNUEABI: bl memmove
%arr0 = alloca [13 x i8], align 1
- %0 = getelementptr inbounds [13 x i8], [13 x i8]* %arr0, i32 0, i32 16
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i1 false)
+ %0 = getelementptr inbounds [13 x i8], ptr %arr0, i32 0, i32 16
+ call void @llvm.memmove.p0.p0.i32(ptr %dest, ptr %0, i32 %n, i1 false)
; CHECK: {{add(.w)? r., sp, #(10|14)|sub(.w)? r., r(7|11), #34}}
; CHECK-IOS: bl _memcpy
@@ -358,8 +352,8 @@ entry:
; CHECK-EABI: bl __aeabi_memcpy
; CHECK-GNUEABI: bl memcpy
%arr1 = alloca [13 x i8], align 1
- %1 = getelementptr inbounds [13 x i8], [13 x i8]* %arr1, i32 0, i32 16
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i1 false)
+ %1 = getelementptr inbounds [13 x i8], ptr %arr1, i32 0, i32 16
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr %1, i32 %n, i1 false)
; CHECK: {{add(.w)? r., sp, #(1|5)|sub(.w)? r., r(7|11), #47}}
; CHECK-IOS: mov r1, #1
@@ -371,8 +365,8 @@ entry:
; CHECK-GNUEABI: mov r1, #1
; CHECK-GNUEABI: bl memset
%arr2 = alloca [13 x i8], align 1
- %2 = getelementptr inbounds [13 x i8], [13 x i8]* %arr2, i32 0, i32 16
- call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i1 false)
+ %2 = getelementptr inbounds [13 x i8], ptr %arr2, i32 0, i32 16
+ call void @llvm.memset.p0.i32(ptr %2, i8 1, i32 %n, i1 false)
ret void
}
@@ -389,18 +383,18 @@ entry:
@arr8 = internal global [128 x i8] undef
@arr9 = weak_odr global [128 x i8] undef
@arr10 = dso_local global [8 x i8] c"\01\02\03\04\05\06\07\08", align 1
-define void @f9(i8* %dest, i32 %n) "frame-pointer"="all" {
+define void @f9(ptr %dest, i32 %n) "frame-pointer"="all" {
entry:
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr1, i32 0, i32 0), i32 %n, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @arr2, i32 0, i32 0), i32 %n, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr3, i32 0, i32 0), i32 %n, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @arr4, i32 0, i32 0), i32 %n, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr5, i32 0, i32 0), i32 %n, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr6, i32 0, i32 0), i32 %n, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr7, i32 0, i32 0), i32 %n, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([128 x i8], [128 x i8]* @arr8, i32 0, i32 0), i32 %n, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([128 x i8], [128 x i8]* @arr9, i32 0, i32 0), i32 %n, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @arr10, i32 0, i32 0), i32 %n, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr @arr1, i32 %n, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr @arr2, i32 %n, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr @arr3, i32 %n, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr @arr4, i32 %n, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr @arr5, i32 %n, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr @arr6, i32 %n, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr @arr7, i32 %n, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr @arr8, i32 %n, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr @arr9, i32 %n, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr @arr10, i32 %n, i1 false)
ret void
}
@@ -436,6 +430,6 @@ entry:
; CHECK-NOT: arr7:
-declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
-declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) nounwind
+declare void @llvm.memmove.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
+declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) nounwind
diff --git a/llvm/test/CodeGen/ARM/memset-align.ll b/llvm/test/CodeGen/ARM/memset-align.ll
index cdd01477c0d1f..3b468fb495c7e 100644
--- a/llvm/test/CodeGen/ARM/memset-align.ll
+++ b/llvm/test/CodeGen/ARM/memset-align.ll
@@ -26,13 +26,11 @@ define void @test() {
; CHECK-NEXT: pop {r7, pc}
entry:
%a = alloca %struct.af, align 8
- %0 = bitcast %struct.af* %a to i8*
- %1 = bitcast %struct.af* %a to i8*
- call void @llvm.memset.p0i8.i64(i8* align 8 %1, i8 -1, i64 24, i1 false)
- call void @llvm.memset.p0i8.i64(i8* align 8 %0, i8 0, i64 19, i1 false)
- call void @callee(%struct.af* %a)
+ call void @llvm.memset.p0.i64(ptr align 8 %a, i8 -1, i64 24, i1 false)
+ call void @llvm.memset.p0.i64(ptr align 8 %a, i8 0, i64 19, i1 false)
+ call void @callee(ptr %a)
ret void
}
-declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1 immarg)
-declare void @callee(%struct.af*) local_unnamed_addr #1
+declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg)
+declare void @callee(ptr) local_unnamed_addr #1
diff --git a/llvm/test/CodeGen/ARM/memset-inline.ll b/llvm/test/CodeGen/ARM/memset-inline.ll
index 1b88539211cc0..09469b4128f47 100644
--- a/llvm/test/CodeGen/ARM/memset-inline.ll
+++ b/llvm/test/CodeGen/ARM/memset-inline.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -pre-RA-sched=source -disable-post-ra | FileCheck %s -check-prefix=CHECK-7A
; RUN: llc < %s -mtriple=thumbv6m -pre-RA-sched=source -disable-post-ra -mattr=+strict-align | FileCheck %s -check-prefix=CHECK-6M
-define void @t1(i8* nocapture %c) nounwind optsize {
+define void @t1(ptr nocapture %c) nounwind optsize {
entry:
; CHECK-7A-LABEL: t1:
; CHECK-7A: movs r1, #0
@@ -12,7 +12,7 @@ entry:
; CHECK-6M: str r1, [r0]
; CHECK-6M: str r1, [r0, #4]
; CHECK-6M: str r1, [r0, #8]
- call void @llvm.memset.p0i8.i64(i8* align 8 %c, i8 0, i64 12, i1 false)
+ call void @llvm.memset.p0.i64(ptr align 8 %c, i8 0, i64 12, i1 false)
ret void
}
@@ -32,13 +32,12 @@ entry:
; CHECK-6M-DAG: str [[REG]], [sp, #4]
; CHECK-6M-DAG: str [[REG]], [sp]
%buf = alloca [26 x i8], align 1
- %0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0
- call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i1 false)
- call void @something(i8* %0) nounwind
+ call void @llvm.memset.p0.i32(ptr %buf, i8 0, i32 26, i1 false)
+ call void @something(ptr %buf) nounwind
ret void
}
-define void @t3(i8* %p) {
+define void @t3(ptr %p) {
entry:
; CHECK-7A-LABEL: t3:
; CHECK-7A: muls [[REG:r[0-9]+]],
@@ -54,8 +53,8 @@ entry:
for.body:
%i = phi i32 [ 0, %entry ], [ %inc, %for.body ]
%0 = trunc i32 %i to i8
- call void @llvm.memset.p0i8.i32(i8* %p, i8 %0, i32 4, i1 false)
- call void @something(i8* %p)
+ call void @llvm.memset.p0.i32(ptr %p, i8 %0, i32 4, i1 false)
+ call void @something(ptr %p)
%inc = add nuw nsw i32 %i, 1
%exitcond = icmp eq i32 %inc, 255
br i1 %exitcond, label %for.end, label %for.body
@@ -64,7 +63,7 @@ for.end:
ret void
}
-define void @t4(i8* %p) {
+define void @t4(ptr %p) {
entry:
; CHECK-7A-LABEL: t4:
; CHECK-7A: muls [[REG:r[0-9]+]],
@@ -78,8 +77,8 @@ entry:
for.body:
%i = phi i32 [ 0, %entry ], [ %inc, %for.body ]
%0 = trunc i32 %i to i8
- call void @llvm.memset.p0i8.i32(i8* align 2 %p, i8 %0, i32 4, i1 false)
- call void @something(i8* %p)
+ call void @llvm.memset.p0.i32(ptr align 2 %p, i8 %0, i32 4, i1 false)
+ call void @something(ptr %p)
%inc = add nuw nsw i32 %i, 1
%exitcond = icmp eq i32 %inc, 255
br i1 %exitcond, label %for.end, label %for.body
@@ -88,6 +87,6 @@ for.end:
ret void
}
-declare void @something(i8*) nounwind
-declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) nounwind
-declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind
+declare void @something(ptr) nounwind
+declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) nounwind
+declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind
diff --git a/llvm/test/CodeGen/ARM/minsize-litpools.ll b/llvm/test/CodeGen/ARM/minsize-litpools.ll
index d5452ed0f9095..d43050fa7b3c5 100644
--- a/llvm/test/CodeGen/ARM/minsize-litpools.ll
+++ b/llvm/test/CodeGen/ARM/minsize-litpools.ll
@@ -12,7 +12,7 @@ define i32 @small_global() minsize {
; CHECK: ldr r[[GLOBDEST:[0-9]+]], {{.?LCPI0_0}}
; CHECK: ldr r0, [r[[GLOBDEST]]]
- %val = load i32, i32* @var
+ %val = load i32, ptr @var
ret i32 %val
}
@@ -21,6 +21,6 @@ define i32 @big_global() {
; CHECK: movw [[GLOBDEST:r[0-9]+]], :lower16:var
; CHECK: movt [[GLOBDEST]], :upper16:var
- %val = load i32, i32* @var
+ %val = load i32, ptr @var
ret i32 %val
}
diff --git a/llvm/test/CodeGen/ARM/misched-fusion-aes.ll b/llvm/test/CodeGen/ARM/misched-fusion-aes.ll
index addd698d786ed..2d73a31fd27fe 100644
--- a/llvm/test/CodeGen/ARM/misched-fusion-aes.ll
+++ b/llvm/test/CodeGen/ARM/misched-fusion-aes.ll
@@ -5,15 +5,15 @@ declare <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %d)
declare <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %d, <16 x i8> %k)
declare <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %d)
-define void @aesea(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d, <16 x i8> %e) {
- %d0 = load <16 x i8>, <16 x i8>* %a0
- %a1 = getelementptr inbounds <16 x i8>, <16 x i8>* %a0, i64 1
- %d1 = load <16 x i8>, <16 x i8>* %a1
- %a2 = getelementptr inbounds <16 x i8>, <16 x i8>* %a0, i64 2
- %d2 = load <16 x i8>, <16 x i8>* %a2
- %a3 = getelementptr inbounds <16 x i8>, <16 x i8>* %a0, i64 3
- %d3 = load <16 x i8>, <16 x i8>* %a3
- %k0 = load <16 x i8>, <16 x i8>* %b0
+define void @aesea(ptr %a0, ptr %b0, ptr %c0, <16 x i8> %d, <16 x i8> %e) {
+ %d0 = load <16 x i8>, ptr %a0
+ %a1 = getelementptr inbounds <16 x i8>, ptr %a0, i64 1
+ %d1 = load <16 x i8>, ptr %a1
+ %a2 = getelementptr inbounds <16 x i8>, ptr %a0, i64 2
+ %d2 = load <16 x i8>, ptr %a2
+ %a3 = getelementptr inbounds <16 x i8>, ptr %a0, i64 3
+ %d3 = load <16 x i8>, ptr %a3
+ %k0 = load <16 x i8>, ptr %b0
%e00 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d0, <16 x i8> %k0)
%f00 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e00)
%e01 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d1, <16 x i8> %k0)
@@ -22,8 +22,8 @@ define void @aesea(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d,
%f02 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e02)
%e03 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d3, <16 x i8> %k0)
%f03 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e03)
- %b1 = getelementptr inbounds <16 x i8>, <16 x i8>* %b0, i64 1
- %k1 = load <16 x i8>, <16 x i8>* %b1
+ %b1 = getelementptr inbounds <16 x i8>, ptr %b0, i64 1
+ %k1 = load <16 x i8>, ptr %b1
%e10 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f00, <16 x i8> %k1)
%f10 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e00)
%e11 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f01, <16 x i8> %k1)
@@ -32,8 +32,8 @@ define void @aesea(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d,
%f12 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e02)
%e13 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f03, <16 x i8> %k1)
%f13 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e03)
- %b2 = getelementptr inbounds <16 x i8>, <16 x i8>* %b0, i64 2
- %k2 = load <16 x i8>, <16 x i8>* %b2
+ %b2 = getelementptr inbounds <16 x i8>, ptr %b0, i64 2
+ %k2 = load <16 x i8>, ptr %b2
%e20 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f10, <16 x i8> %k2)
%f20 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e10)
%e21 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f11, <16 x i8> %k2)
@@ -42,8 +42,8 @@ define void @aesea(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d,
%f22 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e12)
%e23 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f13, <16 x i8> %k2)
%f23 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e13)
- %b3 = getelementptr inbounds <16 x i8>, <16 x i8>* %b0, i64 3
- %k3 = load <16 x i8>, <16 x i8>* %b3
+ %b3 = getelementptr inbounds <16 x i8>, ptr %b0, i64 3
+ %k3 = load <16 x i8>, ptr %b3
%e30 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f20, <16 x i8> %k3)
%f30 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e20)
%e31 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f21, <16 x i8> %k3)
@@ -60,13 +60,13 @@ define void @aesea(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d,
%h2 = xor <16 x i8> %g2, %e
%g3 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %f33, <16 x i8> %d)
%h3 = xor <16 x i8> %g3, %e
- store <16 x i8> %h0, <16 x i8>* %c0
- %c1 = getelementptr inbounds <16 x i8>, <16 x i8>* %c0, i64 1
- store <16 x i8> %h1, <16 x i8>* %c1
- %c2 = getelementptr inbounds <16 x i8>, <16 x i8>* %c0, i64 2
- store <16 x i8> %h2, <16 x i8>* %c2
- %c3 = getelementptr inbounds <16 x i8>, <16 x i8>* %c0, i64 3
- store <16 x i8> %h3, <16 x i8>* %c3
+ store <16 x i8> %h0, ptr %c0
+ %c1 = getelementptr inbounds <16 x i8>, ptr %c0, i64 1
+ store <16 x i8> %h1, ptr %c1
+ %c2 = getelementptr inbounds <16 x i8>, ptr %c0, i64 2
+ store <16 x i8> %h2, ptr %c2
+ %c3 = getelementptr inbounds <16 x i8>, ptr %c0, i64 3
+ store <16 x i8> %h3, ptr %c3
ret void
; CHECK-LABEL: aesea:
@@ -98,15 +98,15 @@ define void @aesea(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d,
; CHECK-NEXT: aesmc.8 {{q[0-9][0-9]?}}, [[QH]]
}
-define void @aesda(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d, <16 x i8> %e) {
- %d0 = load <16 x i8>, <16 x i8>* %a0
- %a1 = getelementptr inbounds <16 x i8>, <16 x i8>* %a0, i64 1
- %d1 = load <16 x i8>, <16 x i8>* %a1
- %a2 = getelementptr inbounds <16 x i8>, <16 x i8>* %a0, i64 2
- %d2 = load <16 x i8>, <16 x i8>* %a2
- %a3 = getelementptr inbounds <16 x i8>, <16 x i8>* %a0, i64 3
- %d3 = load <16 x i8>, <16 x i8>* %a3
- %k0 = load <16 x i8>, <16 x i8>* %b0
+define void @aesda(ptr %a0, ptr %b0, ptr %c0, <16 x i8> %d, <16 x i8> %e) {
+ %d0 = load <16 x i8>, ptr %a0
+ %a1 = getelementptr inbounds <16 x i8>, ptr %a0, i64 1
+ %d1 = load <16 x i8>, ptr %a1
+ %a2 = getelementptr inbounds <16 x i8>, ptr %a0, i64 2
+ %d2 = load <16 x i8>, ptr %a2
+ %a3 = getelementptr inbounds <16 x i8>, ptr %a0, i64 3
+ %d3 = load <16 x i8>, ptr %a3
+ %k0 = load <16 x i8>, ptr %b0
%e00 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %d0, <16 x i8> %k0)
%f00 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e00)
%e01 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %d1, <16 x i8> %k0)
@@ -115,8 +115,8 @@ define void @aesda(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d,
%f02 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e02)
%e03 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %d3, <16 x i8> %k0)
%f03 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e03)
- %b1 = getelementptr inbounds <16 x i8>, <16 x i8>* %b0, i64 1
- %k1 = load <16 x i8>, <16 x i8>* %b1
+ %b1 = getelementptr inbounds <16 x i8>, ptr %b0, i64 1
+ %k1 = load <16 x i8>, ptr %b1
%e10 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f00, <16 x i8> %k1)
%f10 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e00)
%e11 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f01, <16 x i8> %k1)
@@ -125,8 +125,8 @@ define void @aesda(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d,
%f12 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e02)
%e13 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f03, <16 x i8> %k1)
%f13 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e03)
- %b2 = getelementptr inbounds <16 x i8>, <16 x i8>* %b0, i64 2
- %k2 = load <16 x i8>, <16 x i8>* %b2
+ %b2 = getelementptr inbounds <16 x i8>, ptr %b0, i64 2
+ %k2 = load <16 x i8>, ptr %b2
%e20 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f10, <16 x i8> %k2)
%f20 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e10)
%e21 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f11, <16 x i8> %k2)
@@ -135,8 +135,8 @@ define void @aesda(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d,
%f22 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e12)
%e23 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f13, <16 x i8> %k2)
%f23 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e13)
- %b3 = getelementptr inbounds <16 x i8>, <16 x i8>* %b0, i64 3
- %k3 = load <16 x i8>, <16 x i8>* %b3
+ %b3 = getelementptr inbounds <16 x i8>, ptr %b0, i64 3
+ %k3 = load <16 x i8>, ptr %b3
%e30 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f20, <16 x i8> %k3)
%f30 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %e20)
%e31 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f21, <16 x i8> %k3)
@@ -153,13 +153,13 @@ define void @aesda(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d,
%h2 = xor <16 x i8> %g2, %e
%g3 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %f33, <16 x i8> %d)
%h3 = xor <16 x i8> %g3, %e
- store <16 x i8> %h0, <16 x i8>* %c0
- %c1 = getelementptr inbounds <16 x i8>, <16 x i8>* %c0, i64 1
- store <16 x i8> %h1, <16 x i8>* %c1
- %c2 = getelementptr inbounds <16 x i8>, <16 x i8>* %c0, i64 2
- store <16 x i8> %h2, <16 x i8>* %c2
- %c3 = getelementptr inbounds <16 x i8>, <16 x i8>* %c0, i64 3
- store <16 x i8> %h3, <16 x i8>* %c3
+ store <16 x i8> %h0, ptr %c0
+ %c1 = getelementptr inbounds <16 x i8>, ptr %c0, i64 1
+ store <16 x i8> %h1, ptr %c1
+ %c2 = getelementptr inbounds <16 x i8>, ptr %c0, i64 2
+ store <16 x i8> %h2, ptr %c2
+ %c3 = getelementptr inbounds <16 x i8>, ptr %c0, i64 3
+ store <16 x i8> %h3, ptr %c3
ret void
; CHECK-LABEL: aesda:
@@ -191,24 +191,24 @@ define void @aesda(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d,
; CHECK-NEXT: aesimc.8 {{q[0-9][0-9]?}}, [[QH]]
}
-define void @aes_load_store(<16 x i8> *%p1, <16 x i8> *%p2 , <16 x i8> *%p3) {
+define void @aes_load_store(ptr %p1, ptr %p2 , ptr %p3) {
entry:
%x1 = alloca <16 x i8>, align 16
%x2 = alloca <16 x i8>, align 16
%x3 = alloca <16 x i8>, align 16
%x4 = alloca <16 x i8>, align 16
%x5 = alloca <16 x i8>, align 16
- %in1 = load <16 x i8>, <16 x i8>* %p1, align 16
- store <16 x i8> %in1, <16 x i8>* %x1, align 16
+ %in1 = load <16 x i8>, ptr %p1, align 16
+ store <16 x i8> %in1, ptr %x1, align 16
%aese1 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %in1, <16 x i8> %in1) #2
- store <16 x i8> %aese1, <16 x i8>* %x2, align 16
- %in2 = load <16 x i8>, <16 x i8>* %p2, align 16
+ store <16 x i8> %aese1, ptr %x2, align 16
+ %in2 = load <16 x i8>, ptr %p2, align 16
%aesmc1= call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %aese1) #2
- store <16 x i8> %aesmc1, <16 x i8>* %x3, align 16
+ store <16 x i8> %aesmc1, ptr %x3, align 16
%aese2 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %in1, <16 x i8> %in2) #2
- store <16 x i8> %aese2, <16 x i8>* %x4, align 16
+ store <16 x i8> %aese2, ptr %x4, align 16
%aesmc2= call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %aese2) #2
- store <16 x i8> %aesmc2, <16 x i8>* %x5, align 16
+ store <16 x i8> %aesmc2, ptr %x5, align 16
ret void
; CHECK-LABEL: aes_load_store:
diff --git a/llvm/test/CodeGen/ARM/misched-fusion-lit.ll b/llvm/test/CodeGen/ARM/misched-fusion-lit.ll
index cfc4356e01ae9..6d89f8e402019 100644
--- a/llvm/test/CodeGen/ARM/misched-fusion-lit.ll
+++ b/llvm/test/CodeGen/ARM/misched-fusion-lit.ll
@@ -1,15 +1,15 @@
; RUN: llc %s -o - -mtriple=armv8-unknown -mattr=-fuse-literals,+use-misched | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKDONT
; RUN: llc %s -o - -mtriple=armv8-unknown -mattr=+fuse-literals,+use-misched | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
- at g = common global i32* zeroinitializer
+ at g = common global ptr zeroinitializer
-define i32* @litp(i32 %a, i32 %b) {
+define ptr @litp(i32 %a, i32 %b) {
entry:
%add = add nsw i32 %b, %a
- %ptr = getelementptr i32, i32* bitcast (i32* (i32, i32)* @litp to i32*), i32 %add
- %res = getelementptr i32, i32* bitcast (i32** @g to i32*), i32 %add
- store i32* %ptr, i32** @g, align 4
- ret i32* %res
+ %ptr = getelementptr i32, ptr @litp, i32 %add
+ %res = getelementptr i32, ptr @g, i32 %add
+ store ptr %ptr, ptr @g, align 4
+ ret ptr %res
; CHECK-LABEL: litp:
; CHECK: movw [[R:r[0-9]+]], :lower16:litp
@@ -25,7 +25,7 @@ entry:
%add1 = add i32 %adda, %b
%addb = add i32 %b, 121110837
%add2 = add i32 %addb, %a
- store i32 %add1, i32* bitcast (i32** @g to i32*), align 4
+ store i32 %add1, ptr @g, align 4
ret i32 %add2
; CHECK-LABEL: liti:
diff --git a/llvm/test/CodeGen/ARM/movcc-double.ll b/llvm/test/CodeGen/ARM/movcc-double.ll
index 9ce708d9bd36f..c04e779b28a4e 100644
--- a/llvm/test/CodeGen/ARM/movcc-double.ll
+++ b/llvm/test/CodeGen/ARM/movcc-double.ll
@@ -44,7 +44,7 @@ define i32 @select_noopt(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
%cmp1 = icmp ult i32 %a1, %a2
%or = or i1 %cmp0, %cmp1
%zero_one = zext i1 %or to i32
- store volatile i32 %zero_one, i32* @var32
+ store volatile i32 %zero_one, ptr @var32
%res = select i1 %or, i32 %a3, i32 %a4
ret i32 %res
}
diff --git a/llvm/test/CodeGen/ARM/movt-movw-global.ll b/llvm/test/CodeGen/ARM/movt-movw-global.ll
index 1e10af181f309..d84fe31ad0e28 100644
--- a/llvm/test/CodeGen/ARM/movt-movw-global.ll
+++ b/llvm/test/CodeGen/ARM/movt-movw-global.ll
@@ -5,7 +5,7 @@
@foo = common global i32 0
-define i32* @bar1() nounwind readnone {
+define ptr @bar1() nounwind readnone {
entry:
; EABI: movw r0, :lower16:foo
; EABI-NEXT: movt r0, :upper16:foo
@@ -18,7 +18,7 @@ entry:
; IOS-STATIC: movw r0, :lower16:_foo
; IOS-STATIC-NEXT: movt r0, :upper16:_foo
- ret i32* @foo
+ ret ptr @foo
}
define void @bar2(i32 %baz) nounwind {
@@ -34,6 +34,6 @@ entry:
; IOS-STATIC: movw r1, :lower16:_foo
; IOS-STATIC-NEXT: movt r1, :upper16:_foo
- store i32 %baz, i32* @foo, align 4
+ store i32 %baz, ptr @foo, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/mult-alt-generic-arm.ll b/llvm/test/CodeGen/ARM/mult-alt-generic-arm.ll
index 2ac2b8eefff98..56dc6399d2295 100644
--- a/llvm/test/CodeGen/ARM/mult-alt-generic-arm.ll
+++ b/llvm/test/CodeGen/ARM/mult-alt-generic-arm.ll
@@ -9,7 +9,7 @@ target triple = "arm--"
define arm_aapcscc void @single_m() nounwind {
entry:
- call void asm "foo $1,$0", "=*m,*m"(i32* elementtype(i32) @mout0, i32* elementtype(i32) @min1) nounwind
+ call void asm "foo $1,$0", "=*m,*m"(ptr elementtype(i32) @mout0, ptr elementtype(i32) @min1) nounwind
ret void
}
@@ -17,8 +17,8 @@ define arm_aapcscc void @single_o() nounwind {
entry:
%out0 = alloca i32, align 4
%index = alloca i32, align 4
- store i32 0, i32* %out0, align 4
- store i32 1, i32* %index, align 4
+ store i32 0, ptr %out0, align 4
+ store i32 1, ptr %index, align 4
ret void
}
@@ -31,14 +31,14 @@ define arm_aapcscc void @single_lt() nounwind {
entry:
%out0 = alloca i32, align 4
%in1 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
- store i32 1, i32* %in1, align 4
- %tmp = load i32, i32* %in1, align 4
+ store i32 0, ptr %out0, align 4
+ store i32 1, ptr %in1, align 4
+ %tmp = load i32, ptr %in1, align 4
%0 = call i32 asm "foo $1,$0", "=r,<r"(i32 %tmp) nounwind
- store i32 %0, i32* %out0, align 4
- %tmp1 = load i32, i32* %in1, align 4
+ store i32 %0, ptr %out0, align 4
+ %tmp1 = load i32, ptr %in1, align 4
%1 = call i32 asm "foo $1,$0", "=r,r<"(i32 %tmp1) nounwind
- store i32 %1, i32* %out0, align 4
+ store i32 %1, ptr %out0, align 4
ret void
}
@@ -46,14 +46,14 @@ define arm_aapcscc void @single_gt() nounwind {
entry:
%out0 = alloca i32, align 4
%in1 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
- store i32 1, i32* %in1, align 4
- %tmp = load i32, i32* %in1, align 4
+ store i32 0, ptr %out0, align 4
+ store i32 1, ptr %in1, align 4
+ %tmp = load i32, ptr %in1, align 4
%0 = call i32 asm "foo $1,$0", "=r,>r"(i32 %tmp) nounwind
- store i32 %0, i32* %out0, align 4
- %tmp1 = load i32, i32* %in1, align 4
+ store i32 %0, ptr %out0, align 4
+ %tmp1 = load i32, ptr %in1, align 4
%1 = call i32 asm "foo $1,$0", "=r,r>"(i32 %tmp1) nounwind
- store i32 %1, i32* %out0, align 4
+ store i32 %1, ptr %out0, align 4
ret void
}
@@ -61,56 +61,56 @@ define arm_aapcscc void @single_r() nounwind {
entry:
%out0 = alloca i32, align 4
%in1 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
- store i32 1, i32* %in1, align 4
- %tmp = load i32, i32* %in1, align 4
+ store i32 0, ptr %out0, align 4
+ store i32 1, ptr %in1, align 4
+ %tmp = load i32, ptr %in1, align 4
%0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind
- store i32 %0, i32* %out0, align 4
+ store i32 %0, ptr %out0, align 4
ret void
}
define arm_aapcscc void @single_i() nounwind {
entry:
%out0 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
+ store i32 0, ptr %out0, align 4
%0 = call i32 asm "foo $1,$0", "=r,i"(i32 1) nounwind
- store i32 %0, i32* %out0, align 4
+ store i32 %0, ptr %out0, align 4
ret void
}
define arm_aapcscc void @single_n() nounwind {
entry:
%out0 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
+ store i32 0, ptr %out0, align 4
%0 = call i32 asm "foo $1,$0", "=r,n"(i32 1) nounwind
- store i32 %0, i32* %out0, align 4
+ store i32 %0, ptr %out0, align 4
ret void
}
define arm_aapcscc void @single_E() nounwind {
entry:
%out0 = alloca double, align 8
- store double 0.000000e+000, double* %out0, align 8
+ store double 0.000000e+000, ptr %out0, align 8
; No lowering support.
; %0 = call double asm "foo $1,$0", "=r,E"(double 1.000000e+001) nounwind
-; store double %0, double* %out0, align 8
+; store double %0, ptr %out0, align 8
ret void
}
define arm_aapcscc void @single_F() nounwind {
entry:
%out0 = alloca double, align 8
- store double 0.000000e+000, double* %out0, align 8
+ store double 0.000000e+000, ptr %out0, align 8
; No lowering support.
; %0 = call double asm "foo $1,$0", "=r,F"(double 1.000000e+000) nounwind
-; store double %0, double* %out0, align 8
+; store double %0, ptr %out0, align 8
ret void
}
define arm_aapcscc void @single_s() nounwind {
entry:
%out0 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
+ store i32 0, ptr %out0, align 4
ret void
}
@@ -118,16 +118,16 @@ define arm_aapcscc void @single_g() nounwind {
entry:
%out0 = alloca i32, align 4
%in1 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
- store i32 1, i32* %in1, align 4
- %tmp = load i32, i32* %in1, align 4
+ store i32 0, ptr %out0, align 4
+ store i32 1, ptr %in1, align 4
+ %tmp = load i32, ptr %in1, align 4
%0 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp) nounwind
- store i32 %0, i32* %out0, align 4
- %tmp1 = load i32, i32* @min1, align 4
+ store i32 %0, ptr %out0, align 4
+ %tmp1 = load i32, ptr @min1, align 4
%1 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp1) nounwind
- store i32 %1, i32* %out0, align 4
+ store i32 %1, ptr %out0, align 4
%2 = call i32 asm "foo $1,$0", "=r,imr"(i32 1) nounwind
- store i32 %2, i32* %out0, align 4
+ store i32 %2, ptr %out0, align 4
ret void
}
@@ -135,39 +135,39 @@ define arm_aapcscc void @single_X() nounwind {
entry:
%out0 = alloca i32, align 4
%in1 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
- store i32 1, i32* %in1, align 4
- %tmp = load i32, i32* %in1, align 4
+ store i32 0, ptr %out0, align 4
+ store i32 1, ptr %in1, align 4
+ %tmp = load i32, ptr %in1, align 4
%0 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp) nounwind
- store i32 %0, i32* %out0, align 4
- %tmp1 = load i32, i32* @min1, align 4
+ store i32 %0, ptr %out0, align 4
+ %tmp1 = load i32, ptr @min1, align 4
%1 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp1) nounwind
- store i32 %1, i32* %out0, align 4
+ store i32 %1, ptr %out0, align 4
%2 = call i32 asm "foo $1,$0", "=r,X"(i32 1) nounwind
- store i32 %2, i32* %out0, align 4
- %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
- store i32 %3, i32* %out0, align 4
+ store i32 %2, ptr %out0, align 4
+ %3 = call i32 asm "foo $1,$0", "=r,X"(ptr @marray) nounwind
+ store i32 %3, ptr %out0, align 4
; No lowering support.
; %4 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind
-; store i32 %4, i32* %out0, align 4
+; store i32 %4, ptr %out0, align 4
; %5 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+000) nounwind
-; store i32 %5, i32* %out0, align 4
+; store i32 %5, ptr %out0, align 4
ret void
}
define arm_aapcscc void @single_p() nounwind {
entry:
%out0 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
- %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
- store i32 %0, i32* %out0, align 4
+ store i32 0, ptr %out0, align 4
+ %0 = call i32 asm "foo $1,$0", "=r,r"(ptr @marray) nounwind
+ store i32 %0, ptr %out0, align 4
ret void
}
define arm_aapcscc void @multi_m() nounwind {
entry:
- %tmp = load i32, i32* @min1, align 4
- call void asm "foo $1,$0", "=*m|r,m|r"(i32* elementtype(i32) @mout0, i32 %tmp) nounwind
+ %tmp = load i32, ptr @min1, align 4
+ call void asm "foo $1,$0", "=*m|r,m|r"(ptr elementtype(i32) @mout0, i32 %tmp) nounwind
ret void
}
@@ -175,8 +175,8 @@ define arm_aapcscc void @multi_o() nounwind {
entry:
%out0 = alloca i32, align 4
%index = alloca i32, align 4
- store i32 0, i32* %out0, align 4
- store i32 1, i32* %index, align 4
+ store i32 0, ptr %out0, align 4
+ store i32 1, ptr %index, align 4
ret void
}
@@ -189,14 +189,14 @@ define arm_aapcscc void @multi_lt() nounwind {
entry:
%out0 = alloca i32, align 4
%in1 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
- store i32 1, i32* %in1, align 4
- %tmp = load i32, i32* %in1, align 4
+ store i32 0, ptr %out0, align 4
+ store i32 1, ptr %in1, align 4
+ %tmp = load i32, ptr %in1, align 4
%0 = call i32 asm "foo $1,$0", "=r|r,r|<r"(i32 %tmp) nounwind
- store i32 %0, i32* %out0, align 4
- %tmp1 = load i32, i32* %in1, align 4
+ store i32 %0, ptr %out0, align 4
+ %tmp1 = load i32, ptr %in1, align 4
%1 = call i32 asm "foo $1,$0", "=r|r,r|r<"(i32 %tmp1) nounwind
- store i32 %1, i32* %out0, align 4
+ store i32 %1, ptr %out0, align 4
ret void
}
@@ -204,14 +204,14 @@ define arm_aapcscc void @multi_gt() nounwind {
entry:
%out0 = alloca i32, align 4
%in1 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
- store i32 1, i32* %in1, align 4
- %tmp = load i32, i32* %in1, align 4
+ store i32 0, ptr %out0, align 4
+ store i32 1, ptr %in1, align 4
+ %tmp = load i32, ptr %in1, align 4
%0 = call i32 asm "foo $1,$0", "=r|r,r|>r"(i32 %tmp) nounwind
- store i32 %0, i32* %out0, align 4
- %tmp1 = load i32, i32* %in1, align 4
+ store i32 %0, ptr %out0, align 4
+ %tmp1 = load i32, ptr %in1, align 4
%1 = call i32 asm "foo $1,$0", "=r|r,r|r>"(i32 %tmp1) nounwind
- store i32 %1, i32* %out0, align 4
+ store i32 %1, ptr %out0, align 4
ret void
}
@@ -219,56 +219,56 @@ define arm_aapcscc void @multi_r() nounwind {
entry:
%out0 = alloca i32, align 4
%in1 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
- store i32 1, i32* %in1, align 4
- %tmp = load i32, i32* %in1, align 4
+ store i32 0, ptr %out0, align 4
+ store i32 1, ptr %in1, align 4
+ %tmp = load i32, ptr %in1, align 4
%0 = call i32 asm "foo $1,$0", "=r|r,r|m"(i32 %tmp) nounwind
- store i32 %0, i32* %out0, align 4
+ store i32 %0, ptr %out0, align 4
ret void
}
define arm_aapcscc void @multi_i() nounwind {
entry:
%out0 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
+ store i32 0, ptr %out0, align 4
%0 = call i32 asm "foo $1,$0", "=r|r,r|i"(i32 1) nounwind
- store i32 %0, i32* %out0, align 4
+ store i32 %0, ptr %out0, align 4
ret void
}
define arm_aapcscc void @multi_n() nounwind {
entry:
%out0 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
+ store i32 0, ptr %out0, align 4
%0 = call i32 asm "foo $1,$0", "=r|r,r|n"(i32 1) nounwind
- store i32 %0, i32* %out0, align 4
+ store i32 %0, ptr %out0, align 4
ret void
}
define arm_aapcscc void @multi_E() nounwind {
entry:
%out0 = alloca double, align 8
- store double 0.000000e+000, double* %out0, align 8
+ store double 0.000000e+000, ptr %out0, align 8
; No lowering support.
; %0 = call double asm "foo $1,$0", "=r|r,r|E"(double 1.000000e+001) nounwind
-; store double %0, double* %out0, align 8
+; store double %0, ptr %out0, align 8
ret void
}
define arm_aapcscc void @multi_F() nounwind {
entry:
%out0 = alloca double, align 8
- store double 0.000000e+000, double* %out0, align 8
+ store double 0.000000e+000, ptr %out0, align 8
; No lowering support.
; %0 = call double asm "foo $1,$0", "=r|r,r|F"(double 1.000000e+000) nounwind
-; store double %0, double* %out0, align 8
+; store double %0, ptr %out0, align 8
ret void
}
define arm_aapcscc void @multi_s() nounwind {
entry:
%out0 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
+ store i32 0, ptr %out0, align 4
ret void
}
@@ -276,16 +276,16 @@ define arm_aapcscc void @multi_g() nounwind {
entry:
%out0 = alloca i32, align 4
%in1 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
- store i32 1, i32* %in1, align 4
- %tmp = load i32, i32* %in1, align 4
+ store i32 0, ptr %out0, align 4
+ store i32 1, ptr %in1, align 4
+ %tmp = load i32, ptr %in1, align 4
%0 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp) nounwind
- store i32 %0, i32* %out0, align 4
- %tmp1 = load i32, i32* @min1, align 4
+ store i32 %0, ptr %out0, align 4
+ %tmp1 = load i32, ptr @min1, align 4
%1 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp1) nounwind
- store i32 %1, i32* %out0, align 4
+ store i32 %1, ptr %out0, align 4
%2 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 1) nounwind
- store i32 %2, i32* %out0, align 4
+ store i32 %2, ptr %out0, align 4
ret void
}
@@ -293,31 +293,31 @@ define arm_aapcscc void @multi_X() nounwind {
entry:
%out0 = alloca i32, align 4
%in1 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
- store i32 1, i32* %in1, align 4
- %tmp = load i32, i32* %in1, align 4
+ store i32 0, ptr %out0, align 4
+ store i32 1, ptr %in1, align 4
+ %tmp = load i32, ptr %in1, align 4
%0 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp) nounwind
- store i32 %0, i32* %out0, align 4
- %tmp1 = load i32, i32* @min1, align 4
+ store i32 %0, ptr %out0, align 4
+ %tmp1 = load i32, ptr @min1, align 4
%1 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp1) nounwind
- store i32 %1, i32* %out0, align 4
+ store i32 %1, ptr %out0, align 4
%2 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 1) nounwind
- store i32 %2, i32* %out0, align 4
- %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
- store i32 %3, i32* %out0, align 4
+ store i32 %2, ptr %out0, align 4
+ %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(ptr @marray) nounwind
+ store i32 %3, ptr %out0, align 4
; No lowering support.
; %4 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind
-; store i32 %4, i32* %out0, align 4
+; store i32 %4, ptr %out0, align 4
; %5 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+000) nounwind
-; store i32 %5, i32* %out0, align 4
+; store i32 %5, ptr %out0, align 4
ret void
}
define arm_aapcscc void @multi_p() nounwind {
entry:
%out0 = alloca i32, align 4
- store i32 0, i32* %out0, align 4
- %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind
- store i32 %0, i32* %out0, align 4
+ store i32 0, ptr %out0, align 4
+ %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(ptr @marray) nounwind
+ store i32 %0, ptr %out0, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/naked-no-prolog.ll b/llvm/test/CodeGen/ARM/naked-no-prolog.ll
index 2e9226d2527a9..f6b6cf2993276 100644
--- a/llvm/test/CodeGen/ARM/naked-no-prolog.ll
+++ b/llvm/test/CodeGen/ARM/naked-no-prolog.ll
@@ -2,7 +2,7 @@
%struct.S = type { [65 x i8] }
-define void @naked_no_prologue(%struct.S* byval(%struct.S) align 4 %0) naked noinline nounwind optnone {
+define void @naked_no_prologue(ptr byval(%struct.S) align 4 %0) naked noinline nounwind optnone {
; CHECK-NOT: stm
; CHECK-NOT: str
diff --git a/llvm/test/CodeGen/ARM/negative-offset.ll b/llvm/test/CodeGen/ARM/negative-offset.ll
index bafc9645471cf..721705c1b9eac 100644
--- a/llvm/test/CodeGen/ARM/negative-offset.ll
+++ b/llvm/test/CodeGen/ARM/negative-offset.ll
@@ -1,16 +1,16 @@
; RUN: llc -mtriple=arm-eabi -O3 %s -o - | FileCheck %s
; Function Attrs: nounwind readonly
-define arm_aapcscc i32 @sum(i32* nocapture readonly %p) #0 {
+define arm_aapcscc i32 @sum(ptr nocapture readonly %p) #0 {
entry:
;CHECK-LABEL: sum:
;CHECK-NOT: sub
;CHECK: ldr r{{.*}}, [r0, #-16]
;CHECK: ldr r{{.*}}, [r0, #-8]
- %arrayidx = getelementptr inbounds i32, i32* %p, i32 -4
- %0 = load i32, i32* %arrayidx, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %p, i32 -2
- %1 = load i32, i32* %arrayidx1, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %p, i32 -4
+ %0 = load i32, ptr %arrayidx, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %p, i32 -2
+ %1 = load i32, ptr %arrayidx1, align 4
%add = add nsw i32 %1, %0
ret i32 %add
}
diff --git a/llvm/test/CodeGen/ARM/neon-spfp.ll b/llvm/test/CodeGen/ARM/neon-spfp.ll
index 4eeaa8abfab23..cbf25965a2fac 100644
--- a/llvm/test/CodeGen/ARM/neon-spfp.ll
+++ b/llvm/test/CodeGen/ARM/neon-spfp.ll
@@ -64,7 +64,7 @@ for.body: ; preds = %for.body, %entry
; CHECK-DARWINA15: vmul.f32 s{{[0-9]*}}
; CHECK-DARWINSWIFT: vmul.f32 d{{[0-9]*}}
%conv = fpext float %mul to double
- %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), double %conv) #1
+ %call = tail call i32 (ptr, ...) @printf(ptr @.str, double %conv) #1
%inc = add nsw i32 %i.04, 1
%exitcond = icmp eq i32 %inc, 16000
br i1 %exitcond, label %for.end, label %for.body
@@ -73,4 +73,4 @@ for.end: ; preds = %for.body
ret i32 0
}
-declare i32 @printf(i8* nocapture, ...)
+declare i32 @printf(ptr nocapture, ...)
diff --git a/llvm/test/CodeGen/ARM/neon-vqaddsub-upgrade.ll b/llvm/test/CodeGen/ARM/neon-vqaddsub-upgrade.ll
index a1323810151a5..a8be4cf216639 100644
--- a/llvm/test/CodeGen/ARM/neon-vqaddsub-upgrade.ll
+++ b/llvm/test/CodeGen/ARM/neon-vqaddsub-upgrade.ll
@@ -1,290 +1,290 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vqadds8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqadds8:
;CHECK: vqadd.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vqadds16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqadds16:
;CHECK: vqadd.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vqadds32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqadds32:
;CHECK: vqadd.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vqadds64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqadds64:
;CHECK: vqadd.s64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vqaddu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddu8:
;CHECK: vqadd.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vqaddu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddu16:
;CHECK: vqadd.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vqaddu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddu32:
;CHECK: vqadd.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vqaddu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddu64:
;CHECK: vqadd.u64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vqaddQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQs8:
;CHECK: vqadd.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vqaddQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQs16:
;CHECK: vqadd.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vqaddQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQs32:
;CHECK: vqadd.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vqaddQs64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQs64:
;CHECK: vqadd.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
-define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vqaddQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQu8:
;CHECK: vqadd.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vqaddQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQu16:
;CHECK: vqadd.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vqaddQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQu32:
;CHECK: vqadd.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vqaddQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vqaddQu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQu64:
;CHECK: vqadd.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
-define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vqsubs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubs8:
;CHECK: vqsub.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vqsubs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubs16:
;CHECK: vqsub.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vqsubs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubs32:
;CHECK: vqsub.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vqsubs64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubs64:
;CHECK: vqsub.s64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vqsubu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubu8:
;CHECK: vqsub.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vqsubu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubu16:
;CHECK: vqsub.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vqsubu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubu32:
;CHECK: vqsub.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vqsubu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubu64:
;CHECK: vqsub.u64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vqsubQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQs8:
;CHECK: vqsub.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vqsubQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQs16:
;CHECK: vqsub.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vqsubQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQs32:
;CHECK: vqsub.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vqsubQs64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQs64:
;CHECK: vqsub.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
-define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vqsubQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQu8:
;CHECK: vqsub.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vqsubQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQu16:
;CHECK: vqsub.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vqsubQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQu32:
;CHECK: vqsub.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vqsubQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vqsubQu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQu64:
;CHECK: vqsub.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
diff --git a/llvm/test/CodeGen/ARM/neon_cmp.ll b/llvm/test/CodeGen/ARM/neon_cmp.ll
index fcf4486fa46de..a99ea4d24c5ff 100644
--- a/llvm/test/CodeGen/ARM/neon_cmp.ll
+++ b/llvm/test/CodeGen/ARM/neon_cmp.ll
@@ -3,14 +3,14 @@
; bug 15283
; radar://13191881
; CHECK: vfcmp
-define void @vfcmp(<2 x double>* %a, <2 x double>* %b) {
- %wide.load = load <2 x double>, <2 x double>* %a, align 4
- %wide.load2 = load <2 x double>, <2 x double>* %b, align 4
+define void @vfcmp(ptr %a, ptr %b) {
+ %wide.load = load <2 x double>, ptr %a, align 4
+ %wide.load2 = load <2 x double>, ptr %b, align 4
; CHECK-NOT: vdup.32
; CHECK-NOT: vmovn.i64
%v1 = fcmp olt <2 x double> %wide.load, %wide.load2
%v2 = zext <2 x i1> %v1 to <2 x i32>
%v3 = sitofp <2 x i32> %v2 to <2 x double>
- store <2 x double> %v3, <2 x double>* %b, align 4
+ store <2 x double> %v3, ptr %b, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/neon_div.ll b/llvm/test/CodeGen/ARM/neon_div.ll
index 23b626e0ce516..f09a81cdca40c 100644
--- a/llvm/test/CodeGen/ARM/neon_div.ll
+++ b/llvm/test/CodeGen/ARM/neon_div.ll
@@ -1,9 +1,9 @@
; RUN: llc -mtriple arm-eabi -mattr=+neon -disable-post-ra -pre-RA-sched source %s -o - | FileCheck %s
; RUN: llc -mtriple thumbv7-windows-itanium -mattr=+neon -disable-post-ra -pre-RA-sched source %s -o - | FileCheck %s
-define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+define <8 x i8> @sdivi8(ptr %A, ptr %B) nounwind {
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = sdiv <8 x i8> %tmp1, %tmp2
ret <8 x i8> %tmp3
}
@@ -15,9 +15,9 @@ define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK: vmovn.i32
; CHECK: vmovn.i16
-define <8 x i8> @udivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+define <8 x i8> @udivi8(ptr %A, ptr %B) nounwind {
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = udiv <8 x i8> %tmp1, %tmp2
ret <8 x i8> %tmp3
}
@@ -31,9 +31,9 @@ define <8 x i8> @udivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK: vmovn.i32
; CHECK: vqmovun.s16
-define <4 x i16> @sdivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+define <4 x i16> @sdivi16(ptr %A, ptr %B) nounwind {
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = sdiv <4 x i16> %tmp1, %tmp2
ret <4 x i16> %tmp3
}
@@ -43,9 +43,9 @@ define <4 x i16> @sdivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK: vrecps.f32
; CHECK: vmovn.i32
-define <4 x i16> @udivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+define <4 x i16> @udivi16(ptr %A, ptr %B) nounwind {
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = udiv <4 x i16> %tmp1, %tmp2
ret <4 x i16> %tmp3
}
diff --git a/llvm/test/CodeGen/ARM/neon_fpconv.ll b/llvm/test/CodeGen/ARM/neon_fpconv.ll
index 61ac4098a6dd6..1365af95d8e9a 100644
--- a/llvm/test/CodeGen/ARM/neon_fpconv.ll
+++ b/llvm/test/CodeGen/ARM/neon_fpconv.ll
@@ -17,26 +17,26 @@ define <2 x double> @vextend(<2 x float> %a) {
; We used to generate vmovs between scalar and vfp/neon registers.
; CHECK: vsitofp_double
-define void @vsitofp_double(<2 x i32>* %loadaddr,
- <2 x double>* %storeaddr) {
- %v0 = load <2 x i32>, <2 x i32>* %loadaddr
+define void @vsitofp_double(ptr %loadaddr,
+ ptr %storeaddr) {
+ %v0 = load <2 x i32>, ptr %loadaddr
; CHECK: vldr
; CHECK-NEXT: vcvt.f64.s32
; CHECK-NEXT: vcvt.f64.s32
; CHECK-NEXT: vst
%r = sitofp <2 x i32> %v0 to <2 x double>
- store <2 x double> %r, <2 x double>* %storeaddr
+ store <2 x double> %r, ptr %storeaddr
ret void
}
; CHECK: vuitofp_double
-define void @vuitofp_double(<2 x i32>* %loadaddr,
- <2 x double>* %storeaddr) {
- %v0 = load <2 x i32>, <2 x i32>* %loadaddr
+define void @vuitofp_double(ptr %loadaddr,
+ ptr %storeaddr) {
+ %v0 = load <2 x i32>, ptr %loadaddr
; CHECK: vldr
; CHECK-NEXT: vcvt.f64.u32
; CHECK-NEXT: vcvt.f64.u32
; CHECK-NEXT: vst
%r = uitofp <2 x i32> %v0 to <2 x double>
- store <2 x double> %r, <2 x double>* %storeaddr
+ store <2 x double> %r, ptr %storeaddr
ret void
}
diff --git a/llvm/test/CodeGen/ARM/neon_ld1.ll b/llvm/test/CodeGen/ARM/neon_ld1.ll
index f4d6019055373..d21066098fca8 100644
--- a/llvm/test/CodeGen/ARM/neon_ld1.ll
+++ b/llvm/test/CodeGen/ARM/neon_ld1.ll
@@ -5,13 +5,13 @@
; CHECK: vldr d
; CHECK: vadd.i16 d
; CHECK: vstr d
-define void @t1(<2 x i32>* %r, <4 x i16>* %a, <4 x i16>* %b) nounwind {
+define void @t1(ptr %r, ptr %a, ptr %b) nounwind {
entry:
- %0 = load <4 x i16>, <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1]
- %1 = load <4 x i16>, <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1]
+ %0 = load <4 x i16>, ptr %a, align 8 ; <<4 x i16>> [#uses=1]
+ %1 = load <4 x i16>, ptr %b, align 8 ; <<4 x i16>> [#uses=1]
%2 = add <4 x i16> %0, %1 ; <<4 x i16>> [#uses=1]
%3 = bitcast <4 x i16> %2 to <2 x i32> ; <<2 x i32>> [#uses=1]
- store <2 x i32> %3, <2 x i32>* %r, align 8
+ store <2 x i32> %3, ptr %r, align 8
ret void
}
@@ -20,10 +20,10 @@ entry:
; CHECK: vldr d
; CHECK: vsub.i16 d
; CHECK: vmov r0, r1, d
-define <2 x i32> @t2(<4 x i16>* %a, <4 x i16>* %b) nounwind readonly {
+define <2 x i32> @t2(ptr %a, ptr %b) nounwind readonly {
entry:
- %0 = load <4 x i16>, <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1]
- %1 = load <4 x i16>, <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1]
+ %0 = load <4 x i16>, ptr %a, align 8 ; <<4 x i16>> [#uses=1]
+ %1 = load <4 x i16>, ptr %b, align 8 ; <<4 x i16>> [#uses=1]
%2 = sub <4 x i16> %0, %1 ; <<4 x i16>> [#uses=1]
%3 = bitcast <4 x i16> %2 to <2 x i32> ; <<2 x i32>> [#uses=1]
ret <2 x i32> %3
diff --git a/llvm/test/CodeGen/ARM/neon_ld2.ll b/llvm/test/CodeGen/ARM/neon_ld2.ll
index 5bd6ae6d2a986..37294598c59f8 100644
--- a/llvm/test/CodeGen/ARM/neon_ld2.ll
+++ b/llvm/test/CodeGen/ARM/neon_ld2.ll
@@ -11,13 +11,13 @@
; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
; SWIFT: vadd.i64 q
; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
-define void @t1(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+define void @t1(ptr %r, ptr %a, ptr %b) nounwind {
entry:
- %0 = load <2 x i64>, <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1]
- %1 = load <2 x i64>, <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1]
+ %0 = load <2 x i64>, ptr %a, align 16 ; <<2 x i64>> [#uses=1]
+ %1 = load <2 x i64>, ptr %b, align 16 ; <<2 x i64>> [#uses=1]
%2 = add <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1]
%3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
- store <4 x i32> %3, <4 x i32>* %r, align 16
+ store <4 x i32> %3, ptr %r, align 16
ret void
}
@@ -33,10 +33,10 @@ entry:
; SWIFT: vsub.i64 q
; SWIFT: vmov r0, r1, d
; SWIFT: vmov r2, r3, d
-define <4 x i32> @t2(<2 x i64>* %a, <2 x i64>* %b) nounwind readonly {
+define <4 x i32> @t2(ptr %a, ptr %b) nounwind readonly {
entry:
- %0 = load <2 x i64>, <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1]
- %1 = load <2 x i64>, <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1]
+ %0 = load <2 x i64>, ptr %a, align 16 ; <<2 x i64>> [#uses=1]
+ %1 = load <2 x i64>, ptr %b, align 16 ; <<2 x i64>> [#uses=1]
%2 = sub <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1]
%3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
ret <4 x i32> %3
@@ -48,12 +48,12 @@ entry:
; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}}
; SWIFT: vadd.i64 q
; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}}
-define void @t3(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+define void @t3(ptr %r, ptr %a, ptr %b) nounwind {
entry:
- %0 = load <2 x i64>, <2 x i64>* %a, align 8
- %1 = load <2 x i64>, <2 x i64>* %b, align 8
+ %0 = load <2 x i64>, ptr %a, align 8
+ %1 = load <2 x i64>, ptr %b, align 8
%2 = add <2 x i64> %0, %1
%3 = bitcast <2 x i64> %2 to <4 x i32>
- store <4 x i32> %3, <4 x i32>* %r, align 8
+ store <4 x i32> %3, ptr %r, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/neon_spill.ll b/llvm/test/CodeGen/ARM/neon_spill.ll
index f9282f93f4d27..f3e5f1f936afc 100644
--- a/llvm/test/CodeGen/ARM/neon_spill.ll
+++ b/llvm/test/CodeGen/ARM/neon_spill.ll
@@ -7,43 +7,43 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7-none-linux-gnueabi"
-%0 = type { %1*, i32, i32, i32, i8 }
-%1 = type { i32 (...)** }
-%2 = type { i8*, i8*, i8*, i32 }
+%0 = type { ptr, i32, i32, i32, i8 }
+%1 = type { ptr }
+%2 = type { ptr, ptr, ptr, i32 }
%3 = type { %4 }
-%4 = type { i32 (...)**, %2, %4*, i8, i8 }
+%4 = type { ptr, %2, ptr, i8, i8 }
-declare arm_aapcs_vfpcc void @func1(%0*, float* nocapture, float* nocapture, %2*) nounwind
+declare arm_aapcs_vfpcc void @func1(ptr, ptr nocapture, ptr nocapture, ptr) nounwind
-declare arm_aapcs_vfpcc %0** @func2()
+declare arm_aapcs_vfpcc ptr @func2()
-declare arm_aapcs_vfpcc %2* @func3(%2*, %2*, i32)
+declare arm_aapcs_vfpcc ptr @func3(ptr, ptr, i32)
-declare arm_aapcs_vfpcc %2** @func4()
+declare arm_aapcs_vfpcc ptr @func4()
-define arm_aapcs_vfpcc void @foo(%3* nocapture) nounwind align 2 {
- call void @llvm.arm.neon.vst4.p0i8.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind
- %2 = call arm_aapcs_vfpcc %0** @func2() nounwind
- %3 = load %0*, %0** %2, align 4
- store float 0.000000e+00, float* undef, align 4
- %4 = call arm_aapcs_vfpcc %2* @func3(%2* undef, %2* undef, i32 2956) nounwind
- call arm_aapcs_vfpcc void @func1(%0* %3, float* undef, float* undef, %2* undef)
- %5 = call arm_aapcs_vfpcc %0** @func2() nounwind
- store float 1.000000e+00, float* undef, align 4
- call arm_aapcs_vfpcc void @func1(%0* undef, float* undef, float* undef, %2* undef)
- store float 1.500000e+01, float* undef, align 4
- %6 = call arm_aapcs_vfpcc %2** @func4() nounwind
- %7 = call arm_aapcs_vfpcc %2* @func3(%2* undef, %2* undef, i32 2971) nounwind
+define arm_aapcs_vfpcc void @foo(ptr nocapture) nounwind align 2 {
+ call void @llvm.arm.neon.vst4.p0.v4i32(ptr undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind
+ %2 = call arm_aapcs_vfpcc ptr @func2() nounwind
+ %3 = load ptr, ptr %2, align 4
+ store float 0.000000e+00, ptr undef, align 4
+ %4 = call arm_aapcs_vfpcc ptr @func3(ptr undef, ptr undef, i32 2956) nounwind
+ call arm_aapcs_vfpcc void @func1(ptr %3, ptr undef, ptr undef, ptr undef)
+ %5 = call arm_aapcs_vfpcc ptr @func2() nounwind
+ store float 1.000000e+00, ptr undef, align 4
+ call arm_aapcs_vfpcc void @func1(ptr undef, ptr undef, ptr undef, ptr undef)
+ store float 1.500000e+01, ptr undef, align 4
+ %6 = call arm_aapcs_vfpcc ptr @func4() nounwind
+ %7 = call arm_aapcs_vfpcc ptr @func3(ptr undef, ptr undef, i32 2971) nounwind
%8 = fadd float undef, -1.000000e+05
- store float %8, float* undef, align 16
+ store float %8, ptr undef, align 16
%9 = call arm_aapcs_vfpcc i32 @rand() nounwind
%10 = fmul float undef, 2.000000e+05
%11 = fadd float %10, -1.000000e+05
- store float %11, float* undef, align 4
- call void @llvm.arm.neon.vst4.p0i8.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind
+ store float %11, ptr undef, align 4
+ call void @llvm.arm.neon.vst4.p0.v4i32(ptr undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind
ret void
}
-declare void @llvm.arm.neon.vst4.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst4.p0.v4i32(ptr, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind
declare arm_aapcs_vfpcc i32 @rand()
diff --git a/llvm/test/CodeGen/ARM/nest-register.ll b/llvm/test/CodeGen/ARM/nest-register.ll
index ac7afe0007cd5..51568762a708c 100644
--- a/llvm/test/CodeGen/ARM/nest-register.ll
+++ b/llvm/test/CodeGen/ARM/nest-register.ll
@@ -3,19 +3,19 @@
; Tests that the 'nest' parameter attribute causes the relevant parameter to be
; passed in the right register.
-define i8* @nest_receiver(i8* nest %arg) nounwind {
+define ptr @nest_receiver(ptr nest %arg) nounwind {
; CHECK-LABEL: nest_receiver:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: mov pc, lr
- ret i8* %arg
+ ret ptr %arg
}
-define i8* @nest_caller(i8* %arg) nounwind {
+define ptr @nest_caller(ptr %arg) nounwind {
; CHECK-LABEL: nest_caller:
; CHECK: mov r12, r0
; CHECK-NEXT: bl nest_receiver
; CHECK: mov pc, lr
- %result = call i8* @nest_receiver(i8* nest %arg)
- ret i8* %result
+ %result = call ptr @nest_receiver(ptr nest %arg)
+ ret ptr %result
}
diff --git a/llvm/test/CodeGen/ARM/no-fpscr-liveness.ll b/llvm/test/CodeGen/ARM/no-fpscr-liveness.ll
index ee1285587b657..63628cc877241 100644
--- a/llvm/test/CodeGen/ARM/no-fpscr-liveness.ll
+++ b/llvm/test/CodeGen/ARM/no-fpscr-liveness.ll
@@ -18,12 +18,11 @@ target triple = "thumbv7s-apple-ios"
; ...
; CHECK: add sp, #8
; CHECK: bx lr
-define i32 @eggs(double* nocapture readnone %arg) {
+define i32 @eggs(ptr nocapture readnone %arg) {
bb:
%tmp = alloca %struct.wibble, align 4
- %tmp1 = bitcast %struct.wibble* %tmp to i8*
%tmp2 = tail call i32 @llvm.get.rounding()
- %tmp3 = ptrtoint %struct.wibble* %tmp to i32
+ %tmp3 = ptrtoint ptr %tmp to i32
%tmp4 = sitofp i32 %tmp3 to double
%tmp5 = fmul double %tmp4, 0x0123456789ABCDEF
%tmp6 = fptosi double %tmp5 to i32
@@ -33,14 +32,14 @@ bb:
%tmp10 = and i1 %tmp7, %tmp9
%tmp11 = sext i1 %tmp10 to i32
%tmp12 = add nsw i32 %tmp11, %tmp6
- store i32 %tmp12, i32* @global, align 4
+ store i32 %tmp12, ptr @global, align 4
%tmp13 = icmp ne i32 %tmp12, 0
%tmp14 = icmp ne i32 %tmp2, 0
%tmp15 = and i1 %tmp14, %tmp13
br i1 %tmp15, label %bb16, label %bb18
bb16: ; preds = %bb
- %tmp17 = load i32, i32* @global.1, align 4
+ %tmp17 = load i32, ptr @global.1, align 4
br label %bb18
bb18: ; preds = %bb16, %bb
diff --git a/llvm/test/CodeGen/ARM/no-fpu.ll b/llvm/test/CodeGen/ARM/no-fpu.ll
index 468a8237f8fae..6a6856d17658d 100644
--- a/llvm/test/CodeGen/ARM/no-fpu.ll
+++ b/llvm/test/CodeGen/ARM/no-fpu.ll
@@ -4,16 +4,14 @@
; RUN: llc < %s -mtriple=armv7-none-gnueabi -mattr=-neon,+vfp2 | FileCheck --check-prefix=NONEON-VFP %s
; Check no NEON instructions are selected when feature is disabled.
-define void @neonop(i64* nocapture readonly %a, i64* nocapture %b) #0 {
- %1 = bitcast i64* %a to <2 x i64>*
- %wide.load = load <2 x i64>, <2 x i64>* %1, align 8
+define void @neonop(ptr nocapture readonly %a, ptr nocapture %b) #0 {
+ %wide.load = load <2 x i64>, ptr %a, align 8
; NONEON-NOVFP-NOT: vld1.64
; NONEON-NOT: vld1.64
%add = add <2 x i64> %wide.load, %wide.load
; NONEON-NOVFP-NOT: vadd.i64
; NONEON-NOT: vadd.i64
- %2 = bitcast i64* %b to <2 x i64>*
- store <2 x i64> %add, <2 x i64>* %2, align 8
+ store <2 x i64> %add, ptr %b, align 8
; NONEON-NOVFP-NOT: vst1.64
; NONEON-NOT: vst1.64
ret void
diff --git a/llvm/test/CodeGen/ARM/no-tail-call.ll b/llvm/test/CodeGen/ARM/no-tail-call.ll
index 5a5d43c28714e..b27aa632a7ac9 100644
--- a/llvm/test/CodeGen/ARM/no-tail-call.ll
+++ b/llvm/test/CodeGen/ARM/no-tail-call.ll
@@ -17,28 +17,18 @@ entry:
%0 = alloca %foo, align 4
%1 = alloca %foo, align 4
%2 = alloca %foo, align 4
- %.native = getelementptr inbounds %foo, %foo* %0, i32 0, i32 0
- %.native.value = getelementptr inbounds %Sf, %Sf* %.native, i32 0, i32 0
- store float 0.000000e+00, float* %.native.value, align 4
- %.native1 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0
- %.native1.value = getelementptr inbounds %Sf, %Sf* %.native1, i32 0, i32 0
- store float 1.000000e+00, float* %.native1.value, align 4
- %.native2 = getelementptr inbounds %foo, %foo* %2, i32 0, i32 0
- %.native2.value = getelementptr inbounds %Sf, %Sf* %.native2, i32 0, i32 0
- store float 5.000000e+00, float* %.native2.value, align 4
+ store float 0.000000e+00, ptr %0, align 4
+ store float 1.000000e+00, ptr %1, align 4
+ store float 5.000000e+00, ptr %2, align 4
br i1 true, label %3, label %4
; <label>:3 ; preds = %entry
- %.native4 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0
- %.native4.value = getelementptr inbounds %Sf, %Sf* %.native4, i32 0, i32 0
- store float 2.000000e+00, float* %.native4.value, align 4
+ store float 2.000000e+00, ptr %1, align 4
br label %4
; <label>:4 ; preds = %3, %entry
%5 = call float @llvm.ceil.f32(float 5.000000e+00)
- %.native3 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0
- %.native3.value = getelementptr inbounds %Sf, %Sf* %.native3, i32 0, i32 0
- %6 = load float, float* %.native3.value, align 4
+ %6 = load float, ptr %1, align 4
%7 = call float @llvm.ceil.f32(float %6)
%8 = insertvalue { float, float, float } { float 0.000000e+00, float undef, float undef }, float %5, 1
%9 = insertvalue { float, float, float } %8, float %7, 2
@@ -55,28 +45,18 @@ entry:
%0 = alloca %foo, align 4
%1 = alloca %foo, align 4
%2 = alloca %foo, align 4
- %.native = getelementptr inbounds %foo, %foo* %0, i32 0, i32 0
- %.native.value = getelementptr inbounds %Sf, %Sf* %.native, i32 0, i32 0
- store float 0.000000e+00, float* %.native.value, align 4
- %.native1 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0
- %.native1.value = getelementptr inbounds %Sf, %Sf* %.native1, i32 0, i32 0
- store float 1.000000e+00, float* %.native1.value, align 4
- %.native2 = getelementptr inbounds %foo, %foo* %2, i32 0, i32 0
- %.native2.value = getelementptr inbounds %Sf, %Sf* %.native2, i32 0, i32 0
- store float 5.000000e+00, float* %.native2.value, align 4
+ store float 0.000000e+00, ptr %0, align 4
+ store float 1.000000e+00, ptr %1, align 4
+ store float 5.000000e+00, ptr %2, align 4
br i1 true, label %3, label %4
; <label>:3 ; preds = %entry
- %.native4 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0
- %.native4.value = getelementptr inbounds %Sf, %Sf* %.native4, i32 0, i32 0
- store float 2.000000e+00, float* %.native4.value, align 4
+ store float 2.000000e+00, ptr %1, align 4
br label %4
; <label>:4 ; preds = %3, %entry
%5 = call float @llvm.ceil.f32(float 5.000000e+00)
- %.native3 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0
- %.native3.value = getelementptr inbounds %Sf, %Sf* %.native3, i32 0, i32 0
- %6 = load float, float* %.native3.value, align 4
+ %6 = load float, ptr %1, align 4
%7 = call float @llvm.ceil.f32(float %6)
%8 = insertvalue { float, float } { float 0.000000e+00, float undef }, float %7, 1
ret { float, float } %8
diff --git a/llvm/test/CodeGen/ARM/no_redundant_trunc_for_cmp.ll b/llvm/test/CodeGen/ARM/no_redundant_trunc_for_cmp.ll
index 64fd4f959169e..ad0a3d2e0dd87 100644
--- a/llvm/test/CodeGen/ARM/no_redundant_trunc_for_cmp.ll
+++ b/llvm/test/CodeGen/ARM/no_redundant_trunc_for_cmp.ll
@@ -14,11 +14,11 @@ entry:
%tobool = icmp eq i16 %x, 0
br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry
- tail call void bitcast (void (...)* @foo1 to void ()*)()
+ tail call void @foo1()
br label %if.end
if.else: ; preds = %entry
- tail call void bitcast (void (...)* @foo2 to void ()*)()
+ tail call void @foo2()
br label %if.end
if.end: ; preds = %if.else, %if.then
@@ -37,11 +37,11 @@ entry:
%tobool = icmp eq i18 %x, 150
br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry
- tail call void bitcast (void (...)* @foo1 to void ()*)()
+ tail call void @foo1()
br label %if.end
if.else: ; preds = %entry
- tail call void bitcast (void (...)* @foo2 to void ()*)()
+ tail call void @foo2()
br label %if.end
if.end: ; preds = %if.else, %if.then
@@ -61,11 +61,11 @@ entry:
%tobool = icmp eq i16 %x16, 300
br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry
- tail call void bitcast (void (...)* @foo1 to void ()*)()
+ tail call void @foo1()
br label %if.end
if.else: ; preds = %entry
- tail call void bitcast (void (...)* @foo2 to void ()*)()
+ tail call void @foo2()
br label %if.end
if.end: ; preds = %if.else, %if.then
@@ -86,11 +86,11 @@ entry:
%tobool = icmp eq i8 %x8, 128
br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry
- tail call void bitcast (void (...)* @foo1 to void ()*)()
+ tail call void @foo1()
br label %if.end
if.else: ; preds = %entry
- tail call void bitcast (void (...)* @foo2 to void ()*)()
+ tail call void @foo2()
br label %if.end
if.end: ; preds = %if.else, %if.then
@@ -109,11 +109,11 @@ entry:
%tobool = icmp eq i16 %x, 0
br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry
- tail call void bitcast (void (...)* @foo1 to void ()*)()
+ tail call void @foo1()
br label %if.end
if.else: ; preds = %entry
- tail call void bitcast (void (...)* @foo2 to void ()*)()
+ tail call void @foo2()
br label %if.end
if.end: ; preds = %if.else, %if.then
diff --git a/llvm/test/CodeGen/ARM/none-macho.ll b/llvm/test/CodeGen/ARM/none-macho.ll
index 057da94961452..e4f19960d94d7 100644
--- a/llvm/test/CodeGen/ARM/none-macho.ll
+++ b/llvm/test/CodeGen/ARM/none-macho.ll
@@ -6,7 +6,7 @@
define i32 @test_litpool() minsize {
; CHECK-LABEL: test_litpool:
- %val = load i32, i32* @var
+ %val = load i32, ptr @var
ret i32 %val
; Lit-pool entries need to produce a "$non_lazy_ptr" version of the symbol.
@@ -16,7 +16,7 @@ define i32 @test_litpool() minsize {
define i32 @test_movw_movt() {
; CHECK-LABEL: test_movw_movt:
- %val = load i32, i32* @var
+ %val = load i32, ptr @var
ret i32 %val
; movw/movt should also address their symbols MachO-style
@@ -49,11 +49,11 @@ define i32 @test_frame_ptr() {
}
%big_arr = type [8 x i32]
-define void @test_two_areas(%big_arr* %addr) {
+define void @test_two_areas(ptr %addr) {
; CHECK-LABEL: test_two_areas:
- %val = load %big_arr, %big_arr* %addr
+ %val = load %big_arr, ptr %addr
call void @test_trap()
- store %big_arr %val, %big_arr* %addr
+ store %big_arr %val, ptr %addr
; This goes with the choice of r7 as FP (largely). FP and LR have to be stored
; consecutively on the stack for the frame record to be valid, which means we
diff --git a/llvm/test/CodeGen/ARM/nop_concat_vectors.ll b/llvm/test/CodeGen/ARM/nop_concat_vectors.ll
index fa0e892f9e243..cda1e8390e0d6 100644
--- a/llvm/test/CodeGen/ARM/nop_concat_vectors.ll
+++ b/llvm/test/CodeGen/ARM/nop_concat_vectors.ll
@@ -4,10 +4,10 @@
;CHECK-NOT: vld1.32
;CHECK-NOT: vst1.32
;CHECK: bx
-define void @foo(<16 x i8>* %J) {
- %A = load <16 x i8>, <16 x i8>* %J
+define void @foo(ptr %J) {
+ %A = load <16 x i8>, ptr %J
%T1 = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%T2 = shufflevector <8 x i8> %T1, <8 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- store <16 x i8> %T2, <16 x i8>* %J
+ store <16 x i8> %T2, ptr %J
ret void
}
diff --git a/llvm/test/CodeGen/ARM/opt-shuff-tstore.ll b/llvm/test/CodeGen/ARM/opt-shuff-tstore.ll
index 74c9a21355d71..f6f397625a585 100644
--- a/llvm/test/CodeGen/ARM/opt-shuff-tstore.ll
+++ b/llvm/test/CodeGen/ARM/opt-shuff-tstore.ll
@@ -3,17 +3,17 @@
; CHECK: func_4_8
; CHECK: vst1.32
; CHECK: bx lr
-define void @func_4_8(<4 x i8> %param, <4 x i8>* %p) {
+define void @func_4_8(<4 x i8> %param, ptr %p) {
%r = add <4 x i8> %param, <i8 1, i8 2, i8 3, i8 4>
- store <4 x i8> %r, <4 x i8>* %p
+ store <4 x i8> %r, ptr %p
ret void
}
; CHECK: func_2_16
; CHECK: vst1.32
; CHECK: bx lr
-define void @func_2_16(<2 x i16> %param, <2 x i16>* %p) {
+define void @func_2_16(<2 x i16> %param, ptr %p) {
%r = add <2 x i16> %param, <i16 1, i16 2>
- store <2 x i16> %r, <2 x i16>* %p
+ store <2 x i16> %r, ptr %p
ret void
}
diff --git a/llvm/test/CodeGen/ARM/optimize-dmbs-v7.ll b/llvm/test/CodeGen/ARM/optimize-dmbs-v7.ll
index 34a55aa718a3c..ad79d9a80e5b7 100644
--- a/llvm/test/CodeGen/ARM/optimize-dmbs-v7.ll
+++ b/llvm/test/CodeGen/ARM/optimize-dmbs-v7.ll
@@ -9,9 +9,9 @@ entry:
for.body: ; preds = %for.body, %entry
%i.013 = phi i32 [ 1, %entry ], [ %inc6, %for.body ]
- store atomic i32 %i.013, i32* @x1 seq_cst, align 4
- store atomic i32 %i.013, i32* @x1 seq_cst, align 4
- store atomic i32 %i.013, i32* @x2 seq_cst, align 4
+ store atomic i32 %i.013, ptr @x1 seq_cst, align 4
+ store atomic i32 %i.013, ptr @x1 seq_cst, align 4
+ store atomic i32 %i.013, ptr @x2 seq_cst, align 4
%inc6 = add nsw i32 %i.013, 1
%exitcond = icmp eq i32 %inc6, 2
br i1 %exitcond, label %for.end, label %for.body
diff --git a/llvm/test/CodeGen/ARM/optselect-regclass.ll b/llvm/test/CodeGen/ARM/optselect-regclass.ll
index 4c5d44c352b28..95bb6ad920e44 100644
--- a/llvm/test/CodeGen/ARM/optselect-regclass.ll
+++ b/llvm/test/CodeGen/ARM/optselect-regclass.ll
@@ -9,7 +9,7 @@
; Function Attrs: nounwind ssp
define void @xfr() {
entry:
- %bf.load4 = load i32, i32* getelementptr inbounds (%union.opcode.0.2.5.8.15.28, %union.opcode.0.2.5.8.15.28* @opcode, i32 0, i32 0), align 4
+ %bf.load4 = load i32, ptr @opcode, align 4
%bf.clear10 = and i32 %bf.load4, 65535
%and11 = and i32 %bf.load4, 32768
%tobool12 = icmp ne i32 %and11, 0
@@ -17,8 +17,8 @@ entry:
%or = or i32 %cond13, %bf.clear10
%shl = shl nuw i32 %or, 2
%add = add i32 0, %shl
- tail call void (i8*, i32, i32, i8*, ...) @__sprintf_chk(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @operands, i32 0, i32 0), i32 0, i32 50, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str86, i32 0, i32 0), i32 undef, i32 undef, i32 %add)
+ tail call void (ptr, i32, i32, ptr, ...) @__sprintf_chk(ptr @operands, i32 0, i32 50, ptr @.str86, i32 undef, i32 undef, i32 %add)
ret void
}
-declare void @__sprintf_chk(i8*, i32, i32, i8*, ...)
+declare void @__sprintf_chk(ptr, i32, i32, ptr, ...)
diff --git a/llvm/test/CodeGen/ARM/out-of-registers.ll b/llvm/test/CodeGen/ARM/out-of-registers.ll
index a6d9fe0981adc..c6488f1789c1f 100644
--- a/llvm/test/CodeGen/ARM/out-of-registers.ll
+++ b/llvm/test/CodeGen/ARM/out-of-registers.ll
@@ -6,9 +6,9 @@ target triple = "thumbv7-none-linux-gnueabi"
; CHECK: vpush
; CHECK: vpop
-define void @foo(float* nocapture %A) #0 {
- %1= bitcast float* %A to i8*
- %2 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32.p0i8(i8* %1, i32 4)
+define void @foo(ptr nocapture %A) #0 {
+ %1= bitcast ptr %A to ptr
+ %2 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32.p0(ptr %1, i32 4)
%3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 0
%divp_vec = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %3
%4 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 1
@@ -17,18 +17,18 @@ define void @foo(float* nocapture %A) #0 {
%div8p_vec = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %5
%6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 3
%div13p_vec = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %6
- tail call void @llvm.arm.neon.vst4.p0i8.v4f32(i8* %1, <4 x float> %divp_vec, <4 x float> %div3p_vec, <4 x float> %div8p_vec, <4 x float> %div13p_vec, i32 4)
+ tail call void @llvm.arm.neon.vst4.p0.v4f32(ptr %1, <4 x float> %divp_vec, <4 x float> %div3p_vec, <4 x float> %div8p_vec, <4 x float> %div13p_vec, i32 4)
ret void
}
; Function Attrs: nounwind
-declare i32 @llvm.annotation.i32(i32, i8*, i8*, i32) #1
+declare i32 @llvm.annotation.i32(i32, ptr, ptr, i32) #1
; Function Attrs: nounwind readonly
; Function Attrs: nounwind
-declare void @llvm.arm.neon.vst4.p0i8.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) #1
-declare { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32.p0i8(i8*, i32) #2
+declare void @llvm.arm.neon.vst4.p0.v4f32(ptr, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) #1
+declare { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32.p0(ptr, i32) #2
; Function Attrs: nounwind
diff --git a/llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll b/llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll
index 1a7809e369ea1..198927d1da3a4 100644
--- a/llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll
+++ b/llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll
@@ -119,7 +119,7 @@ cont:
ret i32 %2
}
-define void @sum(i32* %a, i32* %b, i32 %n) local_unnamed_addr #0 {
+define void @sum(ptr %a, ptr %b, i32 %n) local_unnamed_addr #0 {
; CHECK-LABEL: sum:
; CHECK: ldr [[R0:r[0-9]+]],
; CHECK-NEXT: ldr [[R1:r[0-9]+|lr]],
@@ -136,10 +136,10 @@ for.cond.cleanup:
for.body:
%i.08 = phi i32 [ %7, %cont2 ], [ 0, %entry ]
- %arrayidx = getelementptr inbounds i32, i32* %b, i32 %i.08
- %0 = load i32, i32* %arrayidx, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %a, i32 %i.08
- %1 = load i32, i32* %arrayidx1, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %b, i32 %i.08
+ %0 = load i32, ptr %arrayidx, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %a, i32 %i.08
+ %1 = load i32, ptr %arrayidx1, align 4
%2 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %1, i32 %0)
%3 = extractvalue { i32, i1 } %2, 1
br i1 %3, label %trap, label %cont
@@ -150,7 +150,7 @@ trap:
cont:
%4 = extractvalue { i32, i1 } %2, 0
- store i32 %4, i32* %arrayidx1, align 4
+ store i32 %4, ptr %arrayidx1, align 4
%5 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %i.08, i32 1)
%6 = extractvalue { i32, i1 } %5, 1
br i1 %6, label %trap, label %cont2
@@ -189,7 +189,7 @@ for.cond.cleanup:
for.body:
%i.046 = phi i32 [ %5, %cont1 ], [ 0, %for.body.preheader ]
- tail call void bitcast (void (...)* @external_fn to void ()*)() #4
+ tail call void @external_fn() #4
%3 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %i.046, i32 1)
%4 = extractvalue { i32, i1 } %3, 1
br i1 %4, label %trap, label %cont1
@@ -202,7 +202,7 @@ cont1:
declare void @external_fn(...) local_unnamed_addr #0
-define i32 @are_equal(i32* nocapture readonly %a1, i32* nocapture readonly %a2, i32 %n) local_unnamed_addr #0 {
+define i32 @are_equal(ptr nocapture readonly %a1, ptr nocapture readonly %a2, i32 %n) local_unnamed_addr #0 {
; CHECK-LABEL: are_equal
; CHECK: subs r{{[0-9]+}}, r{{[0-9]+}}, #1
; CHECK-NEXT: bne
@@ -220,10 +220,10 @@ while.cond:
land.rhs:
%dec9.in = phi i32 [ %dec9, %while.cond ], [ %n, %land.rhs.preheader ]
%dec9 = add nsw i32 %dec9.in, -1
- %arrayidx = getelementptr inbounds i32, i32* %a1, i32 %dec9
- %0 = load i32, i32* %arrayidx, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %a2, i32 %dec9
- %1 = load i32, i32* %arrayidx1, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %a1, i32 %dec9
+ %0 = load i32, ptr %arrayidx, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %a2, i32 %dec9
+ %1 = load i32, ptr %arrayidx1, align 4
%cmp = icmp eq i32 %0, %1
br i1 %cmp, label %while.cond, label %while.end
@@ -234,7 +234,7 @@ while.end:
ret i32 %conv
}
-define i1 @no__mulodi4(i32 %a, i64 %b, i32* %c) {
+define i1 @no__mulodi4(i32 %a, i64 %b, ptr %c) {
; CHECK-LABEL: no__mulodi4
; CHECK-NOT: bl __mulodi4
entry:
@@ -246,7 +246,7 @@ entry:
%5 = sext i32 %4 to i64
%6 = icmp ne i64 %3, %5
%7 = or i1 %2, %6
- store i32 %4, i32* %c, align 4
+ store i32 %4, ptr %c, align 4
ret i1 %7
}
diff --git a/llvm/test/CodeGen/ARM/phi.ll b/llvm/test/CodeGen/ARM/phi.ll
index 568f7572b32e9..18a2207b1921d 100644
--- a/llvm/test/CodeGen/ARM/phi.ll
+++ b/llvm/test/CodeGen/ARM/phi.ll
@@ -2,23 +2,23 @@
; <rdar://problem/8686347>
-define i32 @test1(i1 %a, i32* %b) {
+define i32 @test1(i1 %a, ptr %b) {
; CHECK: test1
entry:
br i1 %a, label %lblock, label %rblock
lblock:
- %lbranch = getelementptr i32, i32* %b, i32 1
+ %lbranch = getelementptr i32, ptr %b, i32 1
br label %end
rblock:
- %rbranch = getelementptr i32, i32* %b, i32 1
+ %rbranch = getelementptr i32, ptr %b, i32 1
br label %end
end:
; CHECK: ldr r0, [r1, #4]
- %gep = phi i32* [%lbranch, %lblock], [%rbranch, %rblock]
- %r = load i32, i32* %gep
+ %gep = phi ptr [%lbranch, %lblock], [%rbranch, %rblock]
+ %r = load i32, ptr %gep
; CHECK-NEXT: bx lr
ret i32 %r
}
diff --git a/llvm/test/CodeGen/ARM/pie.ll b/llvm/test/CodeGen/ARM/pie.ll
index ced5bb362f33e..38d6d4ccc2564 100644
--- a/llvm/test/CodeGen/ARM/pie.ll
+++ b/llvm/test/CodeGen/ARM/pie.ll
@@ -2,8 +2,8 @@
@foo = dso_local global i32 42
-define dso_local i32* @get_foo() {
- ret i32* @foo
+define dso_local ptr @get_foo() {
+ ret ptr @foo
}
; Test that we only use one load. Even that is only needed because there
diff --git a/llvm/test/CodeGen/ARM/plt-relative-reloc.ll b/llvm/test/CodeGen/ARM/plt-relative-reloc.ll
index 08dcfdf1298f9..414a48e5aaaed 100644
--- a/llvm/test/CodeGen/ARM/plt-relative-reloc.ll
+++ b/llvm/test/CodeGen/ARM/plt-relative-reloc.ll
@@ -1,9 +1,9 @@
; RUN: llc -mtriple=armv7-unknown-linux -o - %s | FileCheck %s
@vtable = constant [4 x i32] [i32 0,
- i32 sub (i32 ptrtoint (void ()* @fn1 to i32), i32 ptrtoint (i32* getelementptr ([4 x i32], [4 x i32]* @vtable, i32 0, i32 1) to i32)),
- i32 sub (i32 ptrtoint (void ()* @fn2 to i32), i32 ptrtoint (i32* getelementptr ([4 x i32], [4 x i32]* @vtable, i32 0, i32 1) to i32)),
- i32 sub (i32 ptrtoint (void ()* @fn3 to i32), i32 ptrtoint (i32* getelementptr ([4 x i32], [4 x i32]* @vtable, i32 0, i32 1) to i32))
+ i32 sub (i32 ptrtoint (ptr @fn1 to i32), i32 ptrtoint (ptr getelementptr ([4 x i32], ptr @vtable, i32 0, i32 1) to i32)),
+ i32 sub (i32 ptrtoint (ptr @fn2 to i32), i32 ptrtoint (ptr getelementptr ([4 x i32], ptr @vtable, i32 0, i32 1) to i32)),
+ i32 sub (i32 ptrtoint (ptr @fn3 to i32), i32 ptrtoint (ptr getelementptr ([4 x i32], ptr @vtable, i32 0, i32 1) to i32))
]
declare void @fn1() unnamed_addr
diff --git a/llvm/test/CodeGen/ARM/popcnt.ll b/llvm/test/CodeGen/ARM/popcnt.ll
index b1e41da497e18..62374e5073c4e 100644
--- a/llvm/test/CodeGen/ARM/popcnt.ll
+++ b/llvm/test/CodeGen/ARM/popcnt.ll
@@ -2,19 +2,19 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
; Implement ctpop with vcnt
-define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vcnt8(ptr %A) nounwind {
; CHECK-LABEL: vcnt8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vcnt.8 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)
ret <8 x i8> %tmp2
}
-define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vcntQ8(ptr %A) nounwind {
; CHECK-LABEL: vcntQ8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -22,12 +22,12 @@ define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)
ret <16 x i8> %tmp2
}
-define <4 x i16> @vcnt16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vcnt16(ptr %A) nounwind {
; CHECK-LABEL: vcnt16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -35,12 +35,12 @@ define <4 x i16> @vcnt16(<4 x i16>* %A) nounwind {
; CHECK-NEXT: vpaddl.u8 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.ctpop.v4i16(<4 x i16> %tmp1)
ret <4 x i16> %tmp2
}
-define <8 x i16> @vcntQ16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vcntQ16(ptr %A) nounwind {
; CHECK-LABEL: vcntQ16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -49,12 +49,12 @@ define <8 x i16> @vcntQ16(<8 x i16>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %tmp1)
ret <8 x i16> %tmp2
}
-define <2 x i32> @vcnt32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vcnt32(ptr %A) nounwind {
; CHECK-LABEL: vcnt32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -63,12 +63,12 @@ define <2 x i32> @vcnt32(<2 x i32>* %A) nounwind {
; CHECK-NEXT: vpaddl.u16 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %tmp1)
ret <2 x i32> %tmp2
}
-define <4 x i32> @vcntQ32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vcntQ32(ptr %A) nounwind {
; CHECK-LABEL: vcntQ32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -78,12 +78,12 @@ define <4 x i32> @vcntQ32(<4 x i32>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %tmp1)
ret <4 x i32> %tmp2
}
-define <1 x i64> @vcnt64(<1 x i64>* %A) nounwind {
+define <1 x i64> @vcnt64(ptr %A) nounwind {
; CHECK-LABEL: vcnt64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -93,12 +93,12 @@ define <1 x i64> @vcnt64(<1 x i64>* %A) nounwind {
; CHECK-NEXT: vpaddl.u32 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <1 x i64>, <1 x i64>* %A
+ %tmp1 = load <1 x i64>, ptr %A
%tmp2 = call <1 x i64> @llvm.ctpop.v1i64(<1 x i64> %tmp1)
ret <1 x i64> %tmp2
}
-define <2 x i64> @vcntQ64(<2 x i64>* %A) nounwind {
+define <2 x i64> @vcntQ64(ptr %A) nounwind {
; CHECK-LABEL: vcntQ64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -109,7 +109,7 @@ define <2 x i64> @vcntQ64(<2 x i64>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %tmp1)
ret <2 x i64> %tmp2
}
@@ -123,43 +123,43 @@ declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
declare <1 x i64> @llvm.ctpop.v1i64(<1 x i64>) nounwind readnone
declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone
-define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vclz8(ptr %A) nounwind {
; CHECK-LABEL: vclz8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vclz.i8 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vclz16(ptr %A) nounwind {
; CHECK-LABEL: vclz16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vclz.i16 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vclz32(ptr %A) nounwind {
; CHECK-LABEL: vclz32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vclz.i32 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
ret <2 x i32> %tmp2
}
-define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vclzQ8(ptr %A) nounwind {
; CHECK-LABEL: vclzQ8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -167,12 +167,12 @@ define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vclzQ16(ptr %A) nounwind {
; CHECK-LABEL: vclzQ16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -180,12 +180,12 @@ define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vclzQ32(ptr %A) nounwind {
; CHECK-LABEL: vclzQ32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -193,7 +193,7 @@ define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
ret <4 x i32> %tmp2
}
@@ -206,43 +206,43 @@ declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) nounwind readnone
declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
-define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vclss8(ptr %A) nounwind {
; CHECK-LABEL: vclss8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vcls.s8 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vclss16(ptr %A) nounwind {
; CHECK-LABEL: vclss16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vcls.s16 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vclss32(ptr %A) nounwind {
; CHECK-LABEL: vclss32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vcls.s32 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
ret <2 x i32> %tmp2
}
-define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vclsQs8(ptr %A) nounwind {
; CHECK-LABEL: vclsQs8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -250,12 +250,12 @@ define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vclsQs16(ptr %A) nounwind {
; CHECK-LABEL: vclsQs16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -263,12 +263,12 @@ define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vclsQs32(ptr %A) nounwind {
; CHECK-LABEL: vclsQs32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -276,7 +276,7 @@ define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
ret <4 x i32> %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/postrasched.ll b/llvm/test/CodeGen/ARM/postrasched.ll
index 85593d55105ce..0666bb9746606 100644
--- a/llvm/test/CodeGen/ARM/postrasched.ll
+++ b/llvm/test/CodeGen/ARM/postrasched.ll
@@ -10,10 +10,10 @@
; CHECK: t2LDRi12
; CHECK: Latency : 2
-define i32 @test_misched(i32* %ptr) "target-cpu"="cortex-m33" {
+define i32 @test_misched(ptr %ptr) "target-cpu"="cortex-m33" {
entry:
- %l = load i32, i32* %ptr
- store i32 0, i32* %ptr
+ %l = load i32, ptr %ptr
+ store i32 0, ptr %ptr
ret i32 %l
}
@@ -21,10 +21,10 @@ entry:
; CHECK: Subtarget disables post-MI-sched.
; CHECK: ********** List Scheduling **********
-define i32 @test_rasched(i32* %ptr) {
+define i32 @test_rasched(ptr %ptr) {
entry:
- %l = load i32, i32* %ptr
- store i32 0, i32* %ptr
+ %l = load i32, ptr %ptr
+ store i32 0, ptr %ptr
ret i32 %l
}
diff --git a/llvm/test/CodeGen/ARM/pr13249.ll b/llvm/test/CodeGen/ARM/pr13249.ll
index cede6007ba166..eda6ef7247353 100644
--- a/llvm/test/CodeGen/ARM/pr13249.ll
+++ b/llvm/test/CodeGen/ARM/pr13249.ll
@@ -1,27 +1,27 @@
; RUN: llc < %s -mtriple armv7--linux-gnueabi
-define arm_aapcscc i8* @__strtok_r_1c(i8* %arg, i8 signext %arg1, i8** nocapture %arg2) nounwind {
+define arm_aapcscc ptr @__strtok_r_1c(ptr %arg, i8 signext %arg1, ptr nocapture %arg2) nounwind {
bb:
br label %bb3
bb3: ; preds = %bb3, %bb
- %tmp = phi i8* [ %tmp5, %bb3 ], [ %arg, %bb ]
- %tmp4 = load i8, i8* %tmp, align 1
- %tmp5 = getelementptr inbounds i8, i8* %tmp, i32 1
+ %tmp = phi ptr [ %tmp5, %bb3 ], [ %arg, %bb ]
+ %tmp4 = load i8, ptr %tmp, align 1
+ %tmp5 = getelementptr inbounds i8, ptr %tmp, i32 1
br i1 undef, label %bb3, label %bb7
bb7: ; preds = %bb13, %bb3
%tmp8 = phi i8 [ %tmp14, %bb13 ], [ %tmp4, %bb3 ]
- %tmp9 = phi i8* [ %tmp12, %bb13 ], [ %tmp, %bb3 ]
+ %tmp9 = phi ptr [ %tmp12, %bb13 ], [ %tmp, %bb3 ]
%tmp10 = icmp ne i8 %tmp8, %arg1
- %tmp12 = getelementptr inbounds i8, i8* %tmp9, i32 1
+ %tmp12 = getelementptr inbounds i8, ptr %tmp9, i32 1
br i1 %tmp10, label %bb13, label %bb15
bb13: ; preds = %bb7
- %tmp14 = load i8, i8* %tmp12, align 1
+ %tmp14 = load i8, ptr %tmp12, align 1
br label %bb7
bb15: ; preds = %bb7
- store i8* %tmp9, i8** %arg2, align 4
- ret i8* %tmp
+ store ptr %tmp9, ptr %arg2, align 4
+ ret ptr %tmp
}
diff --git a/llvm/test/CodeGen/ARM/pr18364-movw.ll b/llvm/test/CodeGen/ARM/pr18364-movw.ll
index b783522c42b87..828f172b7e697 100644
--- a/llvm/test/CodeGen/ARM/pr18364-movw.ll
+++ b/llvm/test/CodeGen/ARM/pr18364-movw.ll
@@ -12,10 +12,10 @@ entry:
; V7: movw
%y = alloca i64, align 8
%z = alloca i64, align 8
- store i64 1, i64* %y, align 8
- store i64 11579764786944, i64* %z, align 8
- %0 = load i64, i64* %y, align 8
- %1 = load i64, i64* %z, align 8
+ store i64 1, ptr %y, align 8
+ store i64 11579764786944, ptr %z, align 8
+ %0 = load i64, ptr %y, align 8
+ %1 = load i64, ptr %z, align 8
%sub = sub i64 %0, %1
ret i64 %sub
}
diff --git a/llvm/test/CodeGen/ARM/pr25317.ll b/llvm/test/CodeGen/ARM/pr25317.ll
index ca29185672bf0..171e5a0fe4621 100644
--- a/llvm/test/CodeGen/ARM/pr25317.ll
+++ b/llvm/test/CodeGen/ARM/pr25317.ll
@@ -5,7 +5,7 @@ target triple = "armv7--linux-gnueabihf"
; CHECK-LABEL: f:
; CHECK: str lr, [r0]
-define void @f(i32* %p) {
- call void asm sideeffect "str lr, $0", "=*o"(i32* elementtype(i32) %p)
+define void @f(ptr %p) {
+ call void asm sideeffect "str lr, $0", "=*o"(ptr elementtype(i32) %p)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/pr25838.ll b/llvm/test/CodeGen/ARM/pr25838.ll
index f3bb98f4260c2..bfb65773df25d 100644
--- a/llvm/test/CodeGen/ARM/pr25838.ll
+++ b/llvm/test/CodeGen/ARM/pr25838.ll
@@ -5,7 +5,7 @@ target triple = "armv7--linux-android"
%0 = type { i32, i32 }
-define i32 @foo(%0* readonly) {
+define i32 @foo(ptr readonly) {
br i1 undef, label %12, label %2
; <label>:2
diff --git a/llvm/test/CodeGen/ARM/pr26669.ll b/llvm/test/CodeGen/ARM/pr26669.ll
index 6c28ddd2d848d..b3de1843da382 100644
--- a/llvm/test/CodeGen/ARM/pr26669.ll
+++ b/llvm/test/CodeGen/ARM/pr26669.ll
@@ -2,15 +2,15 @@
target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
target triple = "thumbv7--ios5.0.0"
-define void @g() personality i32 (...)* @__gxx_personality_sj0 {
+define void @g() personality ptr @__gxx_personality_sj0 {
entry:
- %exn.slot = alloca i8*
+ %exn.slot = alloca ptr
%ehselector.slot = alloca i32
invoke void @f()
to label %try.cont unwind label %lpad
lpad: ; preds = %entry
- %0 = landingpad { i8*, i32 }
+ %0 = landingpad { ptr, i32 }
cleanup
br label %try.cont
diff --git a/llvm/test/CodeGen/ARM/pr32545.ll b/llvm/test/CodeGen/ARM/pr32545.ll
index 5bfb01b45983b..80b0a79fd3f81 100644
--- a/llvm/test/CodeGen/ARM/pr32545.ll
+++ b/llvm/test/CodeGen/ARM/pr32545.ll
@@ -7,12 +7,12 @@ target triple = "armv7--linux-gnueabi"
; CHECK: vmovl.u8 [[QREG:q[0-9]+]], [[DREG]]
; CHECK: vmovl.u16 [[QREG]], [[DREG]]
-define void @f(i32 %dstStride, i8* %indvars.iv, <2 x i8>* %zz) {
+define void @f(i32 %dstStride, ptr %indvars.iv, ptr %zz) {
entry:
br label %for.body
for.body:
- %tmp = load <2 x i8>, <2 x i8>* %zz, align 1
+ %tmp = load <2 x i8>, ptr %zz, align 1
%tmp1 = extractelement <2 x i8> %tmp, i32 0
%.lhs.rhs = zext i8 %tmp1 to i32
call void @g(i32 %.lhs.rhs)
diff --git a/llvm/test/CodeGen/ARM/pr32578.ll b/llvm/test/CodeGen/ARM/pr32578.ll
index b46bb5e8cbf96..b7025473191b9 100644
--- a/llvm/test/CodeGen/ARM/pr32578.ll
+++ b/llvm/test/CodeGen/ARM/pr32578.ll
@@ -9,12 +9,12 @@ define arm_aapcscc double @func() {
br label %tailrecurse
tailrecurse:
- %v0 = load i16, i16* undef, align 8
+ %v0 = load i16, ptr undef, align 8
%cond36.i = icmp eq i16 %v0, 3
br i1 %cond36.i, label %sw.bb.i, label %sw.epilog.i
sw.bb.i:
- %v1 = load double, double* undef, align 8
+ %v1 = load double, ptr undef, align 8
%call21.i = tail call arm_aapcscc double @func()
%mul.i = fmul double %v1, %call21.i
ret double %mul.i
diff --git a/llvm/test/CodeGen/ARM/pr34045-2.ll b/llvm/test/CodeGen/ARM/pr34045-2.ll
index 94bc3ea3e4fc0..11b4373d3de03 100644
--- a/llvm/test/CodeGen/ARM/pr34045-2.ll
+++ b/llvm/test/CodeGen/ARM/pr34045-2.ll
@@ -1,14 +1,14 @@
; RUN: llc < %s -mtriple thumbv7 | FileCheck %s
-define hidden void @foo(i32* %ptr, i1 zeroext %long_blocks) {
+define hidden void @foo(ptr %ptr, i1 zeroext %long_blocks) {
entry:
; This test is actually checking that no cycle is introduced but at least we
; want to see one umull.
; CHECK: umull
- %0 = load i32, i32* %ptr, align 4
+ %0 = load i32, ptr %ptr, align 4
%conv.i.i13.i = zext i32 %0 to i64
%mul.i.i14.i = mul nuw nsw i64 %conv.i.i13.i, 18782
- %1 = load i32, i32* undef, align 4
+ %1 = load i32, ptr undef, align 4
%conv4.i.i16.i = zext i32 %1 to i64
%add5.i.i17.i = add nuw nsw i64 %mul.i.i14.i, %conv4.i.i16.i
%shr.i.i18.i = lshr i64 %add5.i.i17.i, 32
@@ -16,7 +16,7 @@ entry:
%conv11.i.i21.i = trunc i64 %add10.i.i20.i to i32
%x.0.neg.i.i26.i = sub i32 -2, %conv11.i.i21.i
%sub.i.i27.i = add i32 %x.0.neg.i.i26.i, 0
- store i32 %sub.i.i27.i, i32* %ptr, align 4
+ store i32 %sub.i.i27.i, ptr %ptr, align 4
br label %while.body.i
while.body.i: ; preds = %while.body.i, %entry
diff --git a/llvm/test/CodeGen/ARM/pr34045.ll b/llvm/test/CodeGen/ARM/pr34045.ll
index 5d52bfe591b71..0ecfcb104eec7 100644
--- a/llvm/test/CodeGen/ARM/pr34045.ll
+++ b/llvm/test/CodeGen/ARM/pr34045.ll
@@ -1,30 +1,30 @@
; RUN: llc < %s -mtriple thumbv7 | FileCheck %s
; ModuleID = 'bugpoint-reduced-simplified.bc'
-define hidden void @bn_mul_comba8(i32* nocapture %r, i32* nocapture readonly %a, i32* nocapture readonly %b) local_unnamed_addr {
+define hidden void @bn_mul_comba8(ptr nocapture %r, ptr nocapture readonly %a, ptr nocapture readonly %b) local_unnamed_addr {
entry:
; This test is actually checking that no cycle is introduced but at least we
; want to see a couple of umull and one umlal in the output
; CHECK: umull
; CHECK: umull
; CHECK: umlal
- %0 = load i32, i32* %a, align 4
+ %0 = load i32, ptr %a, align 4
%conv = zext i32 %0 to i64
- %1 = load i32, i32* %b, align 4
+ %1 = load i32, ptr %b, align 4
%conv2 = zext i32 %1 to i64
%mul = mul nuw i64 %conv2, %conv
%shr = lshr i64 %mul, 32
- %2 = load i32, i32* %a, align 4
+ %2 = load i32, ptr %a, align 4
%conv13 = zext i32 %2 to i64
- %3 = load i32, i32* undef, align 4
+ %3 = load i32, ptr undef, align 4
%conv15 = zext i32 %3 to i64
%mul16 = mul nuw i64 %conv15, %conv13
%add18 = add i64 %mul16, %shr
%shr20 = lshr i64 %add18, 32
%conv21 = trunc i64 %shr20 to i32
- %4 = load i32, i32* undef, align 4
+ %4 = load i32, ptr undef, align 4
%conv34 = zext i32 %4 to i64
- %5 = load i32, i32* %b, align 4
+ %5 = load i32, ptr %b, align 4
%conv36 = zext i32 %5 to i64
%mul37 = mul nuw i64 %conv36, %conv34
%conv38 = and i64 %add18, 4294967295
@@ -46,8 +46,8 @@ entry:
%conv187 = and i64 %add167, 4294967295
%add188 = add i64 %conv187, 0
%conv189 = trunc i64 %add188 to i32
- %arrayidx200 = getelementptr inbounds i32, i32* %r, i32 3
- store i32 %conv189, i32* %arrayidx200, align 4
+ %arrayidx200 = getelementptr inbounds i32, ptr %r, i32 3
+ store i32 %conv189, ptr %arrayidx200, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/pr3502.ll b/llvm/test/CodeGen/ARM/pr3502.ll
index 4ec982ebea2b7..2448a08613b64 100644
--- a/llvm/test/CodeGen/ARM/pr3502.ll
+++ b/llvm/test/CodeGen/ARM/pr3502.ll
@@ -4,15 +4,15 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
%struct.ArmPTD = type { i32 }
%struct.RegisterSave = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
- %struct.SHARED_AREA = type { i32, %struct.SHARED_AREA*, %struct.SHARED_AREA*, %struct.SHARED_AREA*, %struct.ArmPTD, void (%struct.RegisterSave*)*, void (%struct.RegisterSave*)*, i32, [1024 x i8], i32, i32, i32, i32, i32, i8, i8, i16, i32, i32, i32, i32, [16 x i8], i32, i32, i32, i8, i8, i8, i32, i16, i32, i64, i32, i32, i32, i32, i32, i32, i8*, i32, [256 x i8], i32, i32, i32, [20 x i8], %struct.RegisterSave, { %struct.WorldSwitchV5 }, [4 x i32] }
+ %struct.SHARED_AREA = type { i32, ptr, ptr, ptr, %struct.ArmPTD, ptr, ptr, i32, [1024 x i8], i32, i32, i32, i32, i32, i8, i8, i16, i32, i32, i32, i32, [16 x i8], i32, i32, i32, i8, i8, i8, i32, i16, i32, i64, i32, i32, i32, i32, i32, i32, ptr, i32, [256 x i8], i32, i32, i32, [20 x i8], %struct.RegisterSave, { %struct.WorldSwitchV5 }, [4 x i32] }
%struct.WorldSwitchV5 = type { i32, i32, i32, i32, i32, i32, i32 }
define void @SomeCall(i32 %num) nounwind {
entry:
tail call void asm sideeffect "mcr p15, 0, $0, c7, c10, 4 \0A\09", "r,~{memory}"(i32 0) nounwind
tail call void asm sideeffect "mcr p15,0,$0,c7,c14,0", "r,~{memory}"(i32 0) nounwind
- %0 = load %struct.SHARED_AREA*, %struct.SHARED_AREA** null, align 4 ; <%struct.SHARED_AREA*> [#uses=1]
- %1 = ptrtoint %struct.SHARED_AREA* %0 to i32 ; <i32> [#uses=1]
+ %0 = load ptr, ptr null, align 4 ; <ptr> [#uses=1]
+ %1 = ptrtoint ptr %0 to i32 ; <i32> [#uses=1]
%2 = lshr i32 %1, 20 ; <i32> [#uses=1]
%3 = tail call i32 @SetCurrEntry(i32 %2, i32 0) nounwind ; <i32> [#uses=0]
tail call void @ClearStuff(i32 0) nounwind
diff --git a/llvm/test/CodeGen/ARM/pr36577.ll b/llvm/test/CodeGen/ARM/pr36577.ll
index c910ba9efc441..83cde09b603bd 100644
--- a/llvm/test/CodeGen/ARM/pr36577.ll
+++ b/llvm/test/CodeGen/ARM/pr36577.ll
@@ -8,7 +8,7 @@
@a = common dso_local local_unnamed_addr global i16 0, align 2
-define dso_local arm_aapcscc i32** @pr36577() {
+define dso_local arm_aapcscc ptr @pr36577() {
; CHECK-LABEL: pr36577:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movw r0, :lower16:a
@@ -29,12 +29,12 @@ define dso_local arm_aapcscc i32** @pr36577() {
; CHECK-T2-NEXT: orr.w r0, r1, r0, lsl #2
; CHECK-T2-NEXT: bx lr
entry:
- %0 = load i16, i16* @a, align 2
+ %0 = load i16, ptr @a, align 2
%1 = lshr i16 %0, 7
%2 = and i16 %1, 1
%3 = zext i16 %2 to i32
%4 = xor i32 %3, -1
- %add.ptr = getelementptr inbounds i32*, i32** null, i32 %4
- ret i32** %add.ptr
+ %add.ptr = getelementptr inbounds ptr, ptr null, i32 %4
+ ret ptr %add.ptr
}
diff --git a/llvm/test/CodeGen/ARM/pr39060.ll b/llvm/test/CodeGen/ARM/pr39060.ll
index dfaabfa374a54..a86baf7287872 100644
--- a/llvm/test/CodeGen/ARM/pr39060.ll
+++ b/llvm/test/CodeGen/ARM/pr39060.ll
@@ -10,18 +10,18 @@
; CHECK: uxth
define void @pr39060() local_unnamed_addr #0 {
entry:
- %0 = load i16, i16* @a, align 2
- %1 = load i16, i16* @b, align 2
+ %0 = load i16, ptr @a, align 2
+ %1 = load i16, ptr @b, align 2
%sub = add i16 %1, -1
%cmp = icmp eq i16 %0, %sub
br i1 %cmp, label %if.else, label %if.then
if.then:
- tail call void bitcast (void (...)* @f to void ()*)() #2
+ tail call void @f() #2
br label %if.end
if.else:
- tail call void bitcast (void (...)* @g to void ()*)() #2
+ tail call void @g() #2
br label %if.end
if.end:
diff --git a/llvm/test/CodeGen/ARM/pr39571.ll b/llvm/test/CodeGen/ARM/pr39571.ll
index fbc910a557af6..1d0b8203f1197 100644
--- a/llvm/test/CodeGen/ARM/pr39571.ll
+++ b/llvm/test/CodeGen/ARM/pr39571.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple armv4t-unknown-linux-gnueabi -mattr=+strict-align
; Avoid crash from forwarding indexed-loads back to store.
-%struct.anon = type { %struct.ma*, %struct.mb }
+%struct.anon = type { ptr, %struct.mb }
%struct.ma = type { i8 }
%struct.mb = type { i8, i8 }
%struct.anon.0 = type { %struct.anon.1 }
@@ -10,24 +10,21 @@
%union.ie = type { %struct.ib }
%struct.ib = type { i8, i8, i16 }
- at a = common dso_local local_unnamed_addr global %struct.anon* null, align 4
+ at a = common dso_local local_unnamed_addr global ptr null, align 4
@b = common dso_local local_unnamed_addr global %struct.anon.0 zeroinitializer, align 1
; Function Attrs: norecurse nounwind
define dso_local void @func() local_unnamed_addr {
entry:
- %0 = load %struct.anon*, %struct.anon** @a, align 4
- %ad = getelementptr inbounds %struct.anon, %struct.anon* %0, i32 0, i32 0
- %1 = load %struct.ma*, %struct.ma** %ad, align 4
- %c.sroa.0.0..sroa_idx = getelementptr inbounds %struct.ma, %struct.ma* %1, i32 0, i32 0
- %c.sroa.0.0.copyload = load i8, i8* %c.sroa.0.0..sroa_idx, align 1
- %cb = getelementptr inbounds %struct.anon, %struct.anon* %0, i32 0, i32 1
- %band = getelementptr inbounds %struct.anon, %struct.anon* %0, i32 0, i32 1, i32 1
- store i8 %c.sroa.0.0.copyload, i8* %band, align 4
- store i8 6, i8* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @b, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0), align 1
- store i8 2, i8* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @b, i32 0, i32 0, i32 0, i32 1, i32 0, i32 1), align 1
- %2 = bitcast %struct.mb* %cb to i32*
- %3 = load i32, i32* bitcast (i8* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @b, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0) to i32*), align 1
- store i32 %3, i32* %2, align 1
+ %0 = load ptr, ptr @a, align 4
+ %1 = load ptr, ptr %0, align 4
+ %c.sroa.0.0.copyload = load i8, ptr %1, align 1
+ %cb = getelementptr inbounds %struct.anon, ptr %0, i32 0, i32 1
+ %band = getelementptr inbounds %struct.anon, ptr %0, i32 0, i32 1, i32 1
+ store i8 %c.sroa.0.0.copyload, ptr %band, align 4
+ store i8 6, ptr getelementptr inbounds (%struct.anon.0, ptr @b, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0), align 1
+ store i8 2, ptr getelementptr inbounds (%struct.anon.0, ptr @b, i32 0, i32 0, i32 0, i32 1, i32 0, i32 1), align 1
+ %2 = load i32, ptr getelementptr inbounds (%struct.anon.0, ptr @b, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0), align 1
+ store i32 %2, ptr %cb, align 1
ret void
}
diff --git a/llvm/test/CodeGen/ARM/pr42062.ll b/llvm/test/CodeGen/ARM/pr42062.ll
index 612c9d67f40d1..8396f93a62414 100644
--- a/llvm/test/CodeGen/ARM/pr42062.ll
+++ b/llvm/test/CodeGen/ARM/pr42062.ll
@@ -2,9 +2,9 @@
; RUN: llc -o - %s 2>&1 | FileCheck %s --implicit-check-not=error
target triple = "thumbv8m.base-arm-none-eabi"
@foo = external global i8
-declare i32 @bar(i8* nocapture, i32, i32, i8* nocapture)
+declare i32 @bar(ptr nocapture, i32, i32, ptr nocapture)
-define void @food(i8* %a) #0 {
+define void @food(ptr %a) #0 {
; CHECK-LABEL: food:
; CHECK: mov [[ARG0:r[4-7]]], r0
; CHECK-NEXT: movs r1, #8
@@ -29,9 +29,9 @@ define void @food(i8* %a) #0 {
; CHECK: [[BAR_ADDR]]:
; CHECK-NEXT: .long bar
entry:
- %0 = tail call i32 @bar(i8* %a, i32 8, i32 1, i8* nonnull @foo)
- %1 = tail call i32 @bar(i8* %a, i32 9, i32 0, i8* nonnull @foo)
- %2 = tail call i32 @bar(i8* %a, i32 7, i32 2, i8* nonnull @foo)
+ %0 = tail call i32 @bar(ptr %a, i32 8, i32 1, ptr nonnull @foo)
+ %1 = tail call i32 @bar(ptr %a, i32 9, i32 0, ptr nonnull @foo)
+ %2 = tail call i32 @bar(ptr %a, i32 7, i32 2, ptr nonnull @foo)
ret void
}
attributes #0 = { minsize "target-cpu"="cortex-m23" }
diff --git a/llvm/test/CodeGen/ARM/pr42638-VMOVRRDCombine.ll b/llvm/test/CodeGen/ARM/pr42638-VMOVRRDCombine.ll
index 22c73c7775d55..8ee88fd18f3c8 100644
--- a/llvm/test/CodeGen/ARM/pr42638-VMOVRRDCombine.ll
+++ b/llvm/test/CodeGen/ARM/pr42638-VMOVRRDCombine.ll
@@ -2,22 +2,19 @@
; REQUIRES: asserts
; pr42638
target triple = "armv8r-arm-none-eabi"
-%struct.__va_list = type { i8* }
+%struct.__va_list = type { ptr }
define double @foo(i32 %P0, ...) #0 {
entry:
%V1 = alloca [8 x i8], align 8
%vl = alloca %struct.__va_list, align 4
- %0 = getelementptr inbounds [8 x i8], [8 x i8]* %V1, i32 0, i32 0
- call void asm sideeffect "", "r"(i8* nonnull %0)
- %1 = bitcast %struct.__va_list* %vl to i8*
- call void @llvm.va_start(i8* nonnull %1)
- %2 = bitcast %struct.__va_list* %vl to double**
- %argp.cur3 = load double*, double** %2, align 4
- %v.sroa.0.0.copyload = load double, double* %argp.cur3, align 4
+ call void asm sideeffect "", "r"(ptr nonnull %V1)
+ call void @llvm.va_start(ptr nonnull %vl)
+ %argp.cur3 = load ptr, ptr %vl, align 4
+ %v.sroa.0.0.copyload = load double, ptr %argp.cur3, align 4
ret double %v.sroa.0.0.copyload
}
-declare void @llvm.va_start(i8*)
+declare void @llvm.va_start(ptr)
attributes #0 = { "target-cpu"="cortex-r52" "target-features"="-fp64" }
diff --git a/llvm/test/CodeGen/ARM/pr47454.ll b/llvm/test/CodeGen/ARM/pr47454.ll
index 399de44ec731a..6624c94d2e9c5 100644
--- a/llvm/test/CodeGen/ARM/pr47454.ll
+++ b/llvm/test/CodeGen/ARM/pr47454.ll
@@ -39,8 +39,8 @@ define internal fastcc void @main() {
Entry:
; First arg directly from constant
%const = alloca half, align 2
- store half 0xH7C00, half* %const, align 2
- %arg1 = load half, half* %const, align 2
+ store half 0xH7C00, ptr %const, align 2
+ %arg1 = load half, ptr %const, align 2
; Second arg from fucntion return
%arg2 = call fastcc half @getConstant()
; Arguments should have equivalent mangling
diff --git a/llvm/test/CodeGen/ARM/prefetch.ll b/llvm/test/CodeGen/ARM/prefetch.ll
index f594be346aa7a..ffdb1bf13dc31 100644
--- a/llvm/test/CodeGen/ARM/prefetch.ll
+++ b/llvm/test/CodeGen/ARM/prefetch.ll
@@ -7,7 +7,7 @@
; CHECK-T1-NOT: pld
-define void @t1(i8* %ptr) nounwind {
+define void @t1(ptr %ptr) nounwind {
entry:
; ARM-LABEL: t1:
; ARM-NOT: pldw [r0]
@@ -20,20 +20,20 @@ entry:
; THUMB2-LABEL: t1:
; THUMB2-NOT: pldw [r0]
; THUMB2: pld [r0]
- tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 )
- tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
+ tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 3, i32 1 )
+ tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 3, i32 1 )
ret void
}
-define void @t2(i8* %ptr) nounwind {
+define void @t2(ptr %ptr) nounwind {
entry:
; ARM-LABEL: t2:
; ARM: pld [r0, #1023]
; THUMB2-LABEL: t2:
; THUMB2: pld [r0, #1023]
- %tmp = getelementptr i8, i8* %ptr, i32 1023
- tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3, i32 1 )
+ %tmp = getelementptr i8, ptr %ptr, i32 1023
+ tail call void @llvm.prefetch( ptr %tmp, i32 0, i32 3, i32 1 )
ret void
}
@@ -47,8 +47,8 @@ entry:
; THUMB2: pld [r0, r1]
%tmp1 = lshr i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
- %tmp3 = inttoptr i32 %tmp2 to i8*
- tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3, i32 1 )
+ %tmp3 = inttoptr i32 %tmp2 to ptr
+ tail call void @llvm.prefetch( ptr %tmp3, i32 0, i32 3, i32 1 )
ret void
}
@@ -61,21 +61,21 @@ entry:
; THUMB2: pld [r0, r1, lsl #2]
%tmp1 = shl i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
- %tmp3 = inttoptr i32 %tmp2 to i8*
- tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3, i32 1 )
+ %tmp3 = inttoptr i32 %tmp2 to ptr
+ tail call void @llvm.prefetch( ptr %tmp3, i32 0, i32 3, i32 1 )
ret void
}
-declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
+declare void @llvm.prefetch(ptr, i32, i32, i32) nounwind
-define void @t5(i8* %ptr) nounwind {
+define void @t5(ptr %ptr) nounwind {
entry:
; ARM-LABEL: t5:
; ARM: pli [r0]
; THUMB2-LABEL: t5:
; THUMB2: pli [r0]
- tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 0 )
+ tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 3, i32 0 )
ret void
}
@@ -92,12 +92,11 @@ entry:
;THUMB2: pld [sp, #-50]
%red = alloca [100 x i8], align 1
-%0 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 0
-%1 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 50
-%2 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 -50
-call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1)
-call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1)
-call void @llvm.prefetch(i8* %2, i32 0, i32 3, i32 1)
+%0 = getelementptr inbounds [100 x i8], ptr %red, i32 0, i32 50
+%1 = getelementptr inbounds [100 x i8], ptr %red, i32 0, i32 -50
+call void @llvm.prefetch(ptr %red, i32 0, i32 3, i32 1)
+call void @llvm.prefetch(ptr %0, i32 0, i32 3, i32 1)
+call void @llvm.prefetch(ptr %1, i32 0, i32 3, i32 1)
ret void
}
@@ -114,12 +113,11 @@ entry:
;THUMB2-MP: pldw [sp, #-50]
%red = alloca [100 x i8], align 1
-%0 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 0
-%1 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 50
-%2 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 -50
-call void @llvm.prefetch(i8* %0, i32 1, i32 3, i32 1)
-call void @llvm.prefetch(i8* %1, i32 1, i32 3, i32 1)
-call void @llvm.prefetch(i8* %2, i32 1, i32 3, i32 1)
+%0 = getelementptr inbounds [100 x i8], ptr %red, i32 0, i32 50
+%1 = getelementptr inbounds [100 x i8], ptr %red, i32 0, i32 -50
+call void @llvm.prefetch(ptr %red, i32 1, i32 3, i32 1)
+call void @llvm.prefetch(ptr %0, i32 1, i32 3, i32 1)
+call void @llvm.prefetch(ptr %1, i32 1, i32 3, i32 1)
ret void
}
@@ -136,11 +134,10 @@ entry:
;THUMB2: pli [sp, #-50]
%red = alloca [100 x i8], align 1
-%0 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 0
-%1 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 50
-%2 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 -50
-call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 0)
-call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 0)
-call void @llvm.prefetch(i8* %2, i32 0, i32 3, i32 0)
+%0 = getelementptr inbounds [100 x i8], ptr %red, i32 0, i32 50
+%1 = getelementptr inbounds [100 x i8], ptr %red, i32 0, i32 -50
+call void @llvm.prefetch(ptr %red, i32 0, i32 3, i32 0)
+call void @llvm.prefetch(ptr %0, i32 0, i32 3, i32 0)
+call void @llvm.prefetch(ptr %1, i32 0, i32 3, i32 0)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/private.ll b/llvm/test/CodeGen/ARM/private.ll
index fab8f37f989aa..2326889a09dbb 100644
--- a/llvm/test/CodeGen/ARM/private.ll
+++ b/llvm/test/CodeGen/ARM/private.ll
@@ -15,7 +15,7 @@ define private void @foo() {
define i32 @bar() {
call void @foo()
- %1 = load i32, i32* @baz, align 4
+ %1 = load i32, ptr @baz, align 4
ret i32 %1
}
diff --git a/llvm/test/CodeGen/ARM/readonly-aliases.ll b/llvm/test/CodeGen/ARM/readonly-aliases.ll
index c90650d3a81de..b12c5ead73cb5 100644
--- a/llvm/test/CodeGen/ARM/readonly-aliases.ll
+++ b/llvm/test/CodeGen/ARM/readonly-aliases.ll
@@ -1,13 +1,13 @@
; RUN: llc -mtriple thumbv7-unknown-linux-android -filetype asm -o - %s | FileCheck %s
@a = protected constant <{ i32, i32 }> <{ i32 0, i32 0 }>
- at b = protected alias i32, getelementptr(i32, i32* getelementptr inbounds (<{ i32, i32 }>, <{ i32, i32 }>* @a, i32 0, i32 1), i32 -1)
+ at b = protected alias i32, getelementptr(i32, ptr getelementptr inbounds (<{ i32, i32 }>, <{ i32, i32 }>* @a, i32 0, i32 1), i32 -1)
-declare void @f(i32*)
+declare void @f(ptr)
define void @g() {
entry:
- call void @f(i32* @b)
+ call void @f(ptr @b)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/readtp.ll b/llvm/test/CodeGen/ARM/readtp.ll
index 0a97bfcd3b4bd..c8675d8c2ffe4 100644
--- a/llvm/test/CodeGen/ARM/readtp.ll
+++ b/llvm/test/CodeGen/ARM/readtp.ll
@@ -14,7 +14,7 @@
define void @foo() local_unnamed_addr #0 {
entry:
- store i32 5, i32* @counter, align 4
+ store i32 5, ptr @counter, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/reg_sequence.ll b/llvm/test/CodeGen/ARM/reg_sequence.ll
index db620f65855cf..2f49862f7fff6 100644
--- a/llvm/test/CodeGen/ARM/reg_sequence.ll
+++ b/llvm/test/CodeGen/ARM/reg_sequence.ll
@@ -9,7 +9,7 @@
%struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> }
%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }
-define void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind {
+define void @t1(ptr %i_ptr, ptr %o_ptr, ptr nocapture %vT0ptr, ptr nocapture %vT1ptr) nounwind {
entry:
; CHECK-LABEL: t1:
; CHECK: vld1.16
@@ -19,32 +19,30 @@ entry:
; CHECK: vshrn.i32
; CHECK-NOT: vmov d
; CHECK-NEXT: vst1.16
- %0 = getelementptr inbounds %struct.int32x4_t, %struct.int32x4_t* %vT0ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1]
- %1 = load <4 x i32>, <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1]
- %2 = getelementptr inbounds %struct.int32x4_t, %struct.int32x4_t* %vT1ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1]
- %3 = load <4 x i32>, <4 x i32>* %2, align 16 ; <<4 x i32>> [#uses=1]
- %4 = bitcast i16* %i_ptr to i8* ; <i8*> [#uses=1]
- %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %4, i32 1) ; <<8 x i16>> [#uses=1]
- %6 = bitcast <8 x i16> %5 to <2 x double> ; <<2 x double>> [#uses=2]
- %7 = extractelement <2 x double> %6, i32 0 ; <double> [#uses=1]
- %8 = bitcast double %7 to <4 x i16> ; <<4 x i16>> [#uses=1]
- %9 = sext <4 x i16> %8 to <4 x i32> ; <<4 x i32>> [#uses=1]
- %10 = extractelement <2 x double> %6, i32 1 ; <double> [#uses=1]
- %11 = bitcast double %10 to <4 x i16> ; <<4 x i16>> [#uses=1]
- %12 = sext <4 x i16> %11 to <4 x i32> ; <<4 x i32>> [#uses=1]
- %13 = mul <4 x i32> %1, %9 ; <<4 x i32>> [#uses=1]
- %14 = mul <4 x i32> %3, %12 ; <<4 x i32>> [#uses=1]
+ %0 = getelementptr inbounds %struct.int32x4_t, ptr %vT0ptr, i32 0, i32 0 ; <ptr> [#uses=1]
+ %1 = load <4 x i32>, ptr %0, align 16 ; <<4 x i32>> [#uses=1]
+ %2 = getelementptr inbounds %struct.int32x4_t, ptr %vT1ptr, i32 0, i32 0 ; <ptr> [#uses=1]
+ %3 = load <4 x i32>, ptr %2, align 16 ; <<4 x i32>> [#uses=1]
+ %4 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0(ptr %i_ptr, i32 1) ; <<8 x i16>> [#uses=1]
+ %5 = bitcast <8 x i16> %4 to <2 x double> ; <<2 x double>> [#uses=2]
+ %6 = extractelement <2 x double> %5, i32 0 ; <double> [#uses=1]
+ %7 = bitcast double %6 to <4 x i16> ; <<4 x i16>> [#uses=1]
+ %8 = sext <4 x i16> %7 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %9 = extractelement <2 x double> %5, i32 1 ; <double> [#uses=1]
+ %10 = bitcast double %9 to <4 x i16> ; <<4 x i16>> [#uses=1]
+ %11 = sext <4 x i16> %10 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %12 = mul <4 x i32> %1, %8 ; <<4 x i32>> [#uses=1]
+ %13 = mul <4 x i32> %3, %11 ; <<4 x i32>> [#uses=1]
+ %14 = lshr <4 x i32> %12, <i32 12, i32 12, i32 12, i32 12>
+ %trunc_15 = trunc <4 x i32> %14 to <4 x i16>
%15 = lshr <4 x i32> %13, <i32 12, i32 12, i32 12, i32 12>
- %trunc_15 = trunc <4 x i32> %15 to <4 x i16>
- %16 = lshr <4 x i32> %14, <i32 12, i32 12, i32 12, i32 12>
- %trunc_16 = trunc <4 x i32> %16 to <4 x i16>
- %17 = shufflevector <4 x i16> %trunc_15, <4 x i16> %trunc_16, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; <<8 x i16>> [#uses=1]
- %18 = bitcast i16* %o_ptr to i8* ; <i8*> [#uses=1]
- tail call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %18, <8 x i16> %17, i32 1)
+ %trunc_16 = trunc <4 x i32> %15 to <4 x i16>
+ %16 = shufflevector <4 x i16> %trunc_15, <4 x i16> %trunc_16, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; <<8 x i16>> [#uses=1]
+ tail call void @llvm.arm.neon.vst1.p0.v8i16(ptr %o_ptr, <8 x i16> %16, i32 1)
ret void
}
-define void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind {
+define void @t2(ptr %i_ptr, ptr %o_ptr, ptr nocapture %vT0ptr, ptr nocapture %vT1ptr) nounwind {
entry:
; CHECK-LABEL: t2:
; CHECK: vld1.16
@@ -55,44 +53,40 @@ entry:
; CHECK-NOT: vmov
; CHECK: vst1.16
; CHECK: vst1.16
- %0 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %vT0ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1]
- %1 = load <8 x i16>, <8 x i16>* %0, align 16 ; <<8 x i16>> [#uses=1]
- %2 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %vT1ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1]
- %3 = load <8 x i16>, <8 x i16>* %2, align 16 ; <<8 x i16>> [#uses=1]
- %4 = bitcast i16* %i_ptr to i8* ; <i8*> [#uses=1]
- %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %4, i32 1) ; <<8 x i16>> [#uses=1]
- %6 = getelementptr inbounds i16, i16* %i_ptr, i32 8 ; <i16*> [#uses=1]
- %7 = bitcast i16* %6 to i8* ; <i8*> [#uses=1]
- %8 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %7, i32 1) ; <<8 x i16>> [#uses=1]
- %9 = mul <8 x i16> %1, %5 ; <<8 x i16>> [#uses=1]
- %10 = mul <8 x i16> %3, %8 ; <<8 x i16>> [#uses=1]
- %11 = bitcast i16* %o_ptr to i8* ; <i8*> [#uses=1]
- tail call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %11, <8 x i16> %9, i32 1)
- %12 = getelementptr inbounds i16, i16* %o_ptr, i32 8 ; <i16*> [#uses=1]
- %13 = bitcast i16* %12 to i8* ; <i8*> [#uses=1]
- tail call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %13, <8 x i16> %10, i32 1)
+ %0 = getelementptr inbounds %struct.int16x8_t, ptr %vT0ptr, i32 0, i32 0 ; <ptr> [#uses=1]
+ %1 = load <8 x i16>, ptr %0, align 16 ; <<8 x i16>> [#uses=1]
+ %2 = getelementptr inbounds %struct.int16x8_t, ptr %vT1ptr, i32 0, i32 0 ; <ptr> [#uses=1]
+ %3 = load <8 x i16>, ptr %2, align 16 ; <<8 x i16>> [#uses=1]
+ %4 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0(ptr %i_ptr, i32 1) ; <<8 x i16>> [#uses=1]
+ %5 = getelementptr inbounds i16, ptr %i_ptr, i32 8 ; <ptr> [#uses=1]
+ %6 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0(ptr %5, i32 1) ; <<8 x i16>> [#uses=1]
+ %7 = mul <8 x i16> %1, %4 ; <<8 x i16>> [#uses=1]
+ %8 = mul <8 x i16> %3, %6 ; <<8 x i16>> [#uses=1]
+ tail call void @llvm.arm.neon.vst1.p0.v8i16(ptr %o_ptr, <8 x i16> %7, i32 1)
+ %9 = getelementptr inbounds i16, ptr %o_ptr, i32 8 ; <ptr> [#uses=1]
+ tail call void @llvm.arm.neon.vst1.p0.v8i16(ptr %9, <8 x i16> %8, i32 1)
ret void
}
-define <8 x i8> @t3(i8* %A, i8* %B) nounwind {
+define <8 x i8> @t3(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: t3:
; CHECK: vld3.8
; CHECK: vmul.i8
; CHECK: vmov r
; CHECK-NOT: vmov d
; CHECK: vst3.8
- %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
+ %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
%tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1]
%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2 ; <<8 x i8>> [#uses=1]
%tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 1 ; <<8 x i8>> [#uses=1]
%tmp5 = sub <8 x i8> %tmp3, %tmp4
%tmp6 = add <8 x i8> %tmp2, %tmp3 ; <<8 x i8>> [#uses=1]
%tmp7 = mul <8 x i8> %tmp4, %tmp2
- tail call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %B, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7, i32 1)
+ tail call void @llvm.arm.neon.vst3.p0.v8i8(ptr %B, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7, i32 1)
ret <8 x i8> %tmp4
}
-define void @t4(i32* %in, i32* %out) nounwind {
+define void @t4(ptr %in, ptr %out) nounwind {
entry:
; CHECK-LABEL: t4:
; CHECK: vld2.32
@@ -100,12 +94,9 @@ entry:
; CHECK: vld2.32
; CHECK-NOT: vmov
; CHECK: bne
- %tmp1 = bitcast i32* %in to i8* ; <i8*> [#uses=1]
- %tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8* %tmp1, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
- %tmp3 = getelementptr inbounds i32, i32* %in, i32 8 ; <i32*> [#uses=1]
- %tmp4 = bitcast i32* %tmp3 to i8* ; <i8*> [#uses=1]
- %tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8* %tmp4, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
- %tmp8 = bitcast i32* %out to i8* ; <i8*> [#uses=1]
+ %tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %in, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
+ %tmp3 = getelementptr inbounds i32, ptr %in, i32 8 ; <ptr> [#uses=1]
+ %tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %tmp3, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
br i1 undef, label %return1, label %return2
return1:
@@ -120,7 +111,7 @@ return1:
%tmp39 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1]
%tmp6 = add <4 x i32> %tmp52, %tmp ; <<4 x i32>> [#uses=1]
%tmp7 = add <4 x i32> %tmp57, %tmp39 ; <<4 x i32>> [#uses=1]
- tail call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* %tmp8, <4 x i32> %tmp6, <4 x i32> %tmp7, i32 1)
+ tail call void @llvm.arm.neon.vst2.p0.v4i32(ptr %out, <4 x i32> %tmp6, <4 x i32> %tmp7, i32 1)
ret void
return2:
@@ -131,12 +122,12 @@ return2:
%tmp100 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1]
%tmp101 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1]
%tmp102 = add <4 x i32> %tmp100, %tmp101 ; <<4 x i32>> [#uses=1]
- tail call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* %tmp8, <4 x i32> %tmp102, <4 x i32> %tmp101, i32 1)
+ tail call void @llvm.arm.neon.vst2.p0.v4i32(ptr %out, <4 x i32> %tmp102, <4 x i32> %tmp101, i32 1)
call void @llvm.trap()
unreachable
}
-define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @t5(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: t5:
; CHECK: vld1.32
; How can FileCheck match Q and D registers? We need a lisp interpreter.
@@ -145,29 +136,28 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind {
; CHECK: vld2.16 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0]
; CHECK-NOT: vmov
; CHECK: vadd.i16
- %tmp0 = bitcast i16* %A to i8* ; <i8*> [#uses=1]
- %tmp1 = load <8 x i16>, <8 x i16>* %B ; <<8 x i16>> [#uses=2]
- %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0i8(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 1) ; <%struct.__neon_int16x8x2_t> [#uses=2]
+ %tmp1 = load <8 x i16>, ptr %B ; <<8 x i16>> [#uses=2]
+ %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0(ptr %A, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 1) ; <%struct.__neon_int16x8x2_t> [#uses=2]
%tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 ; <<8 x i16>> [#uses=1]
%tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 ; <<8 x i16>> [#uses=1]
%tmp5 = add <8 x i16> %tmp3, %tmp4 ; <<8 x i16>> [#uses=1]
ret <8 x i16> %tmp5
}
-define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @t6(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: t6:
; CHECK: vldr
; CHECK: vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]]
; CHECK-NEXT: vld2.8 {d[[D1]][1], d[[D0]][1]}
- %tmp1 = load <8 x i8>, <8 x i8>* %B ; <<8 x i8>> [#uses=2]
- %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2]
+ %tmp1 = load <8 x i8>, ptr %B ; <<8 x i8>> [#uses=2]
+ %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2]
%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 ; <<8 x i8>> [#uses=1]
%tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 ; <<8 x i8>> [#uses=1]
%tmp5 = add <8 x i8> %tmp3, %tmp4 ; <<8 x i8>> [#uses=1]
ret <8 x i8> %tmp5
}
-define void @t7(i32* %iptr, i32* %optr) nounwind {
+define void @t7(ptr %iptr, ptr %optr) nounwind {
entry:
; CHECK-LABEL: t7:
; CHECK: vld2.32
@@ -177,15 +167,13 @@ entry:
; CHECK-NOT: vmov
; CHECK: vuzp.32 q[[Q1]], q[[Q0]]
; CHECK: vst1.32
- %0 = bitcast i32* %iptr to i8* ; <i8*> [#uses=2]
- %1 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8* %0, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
- %tmp57 = extractvalue %struct.__neon_int32x4x2_t %1, 0 ; <<4 x i32>> [#uses=1]
- %tmp60 = extractvalue %struct.__neon_int32x4x2_t %1, 1 ; <<4 x i32>> [#uses=1]
- %2 = bitcast i32* %optr to i8* ; <i8*> [#uses=2]
- tail call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* %2, <4 x i32> %tmp57, <4 x i32> %tmp60, i32 1)
- %3 = tail call <4 x i32> @llvm.arm.neon.vld1.v4i32.p0i8(i8* %0, i32 1) ; <<4 x i32>> [#uses=1]
- %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2> ; <<4 x i32>> [#uses=1]
- tail call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %2, <4 x i32> %4, i32 1)
+ %0 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %iptr, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2]
+ %tmp57 = extractvalue %struct.__neon_int32x4x2_t %0, 0 ; <<4 x i32>> [#uses=1]
+ %tmp60 = extractvalue %struct.__neon_int32x4x2_t %0, 1 ; <<4 x i32>> [#uses=1]
+ tail call void @llvm.arm.neon.vst2.p0.v4i32(ptr %optr, <4 x i32> %tmp57, <4 x i32> %tmp60, i32 1)
+ %1 = tail call <4 x i32> @llvm.arm.neon.vld1.v4i32.p0(ptr %iptr, i32 1) ; <<4 x i32>> [#uses=1]
+ %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2> ; <<4 x i32>> [#uses=1]
+ tail call void @llvm.arm.neon.vst1.p0.v4i32(ptr %optr, <4 x i32> %2, i32 1)
ret void
}
@@ -211,7 +199,7 @@ bb.i25: ; preds = %bb.i25, %bb5
%4 = extractelement <2 x double> %tmp26.i, i32 0 ; <double> [#uses=1]
%5 = bitcast double %4 to <2 x float> ; <<2 x float>> [#uses=1]
%6 = extractelement <2 x float> %5, i32 1 ; <float> [#uses=1]
- store float %6, float* undef, align 4
+ store float %6, ptr undef, align 4
br i1 undef, label %bb6, label %bb.i25
bb6: ; preds = %bb.i25
@@ -239,7 +227,7 @@ bb14: ; preds = %bb6
%3 = type { %0, %1 }
; PR7157
-define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind {
+define arm_aapcs_vfpcc float @t9(ptr nocapture, ptr nocapture) nounwind {
; CHECK-LABEL: t9:
; CHECK: vmov.i32 d16, #0x0
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
@@ -247,9 +235,9 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind {
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
%3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2]
%4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
- store <4 x float> %4, <4 x float>* undef, align 16
+ store <4 x float> %4, ptr undef, align 16
%5 = shufflevector <2 x float> %3, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
- store <4 x float> %5, <4 x float>* undef, align 16
+ store <4 x float> %5, ptr undef, align 16
br label %8
; <label>:6 ; preds = %8
@@ -307,7 +295,7 @@ entry:
%16 = shufflevector <4 x float> undef, <4 x float> %15, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1]
%17 = fmul <4 x float> %16, %16
%18 = extractelement <4 x float> %17, i32 2 ; <float> [#uses=1]
- store float %18, float* undef, align 4
+ store float %18, ptr undef, align 4
br i1 undef, label %exit, label %bb14
exit: ; preds = %bb.i19
@@ -318,44 +306,44 @@ bb14: ; preds = %bb6
}
; This test crashes the coalescer because live variables were not updated properly.
-define <8 x i8> @t11(i8* %A1, i8* %A2, i8* %A3, i8* %A4, i8* %A5, i8* %A6, i8* %A7, i8* %A8, i8* %B) nounwind {
- %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
+define <8 x i8> @t11(ptr %A1, ptr %A2, ptr %A3, ptr %A4, ptr %A5, ptr %A6, ptr %A7, ptr %A8, ptr %B) nounwind {
+ %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
%tmp2d = extractvalue %struct.__neon_int8x8x3_t %tmp1d, 0 ; <<8 x i8>> [#uses=1]
- %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
+ %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1]
%tmp2f = extractvalue %struct.__neon_int8x8x3_t %tmp1f, 0 ; <<8 x i8>> [#uses=1]
%tmp2bd = add <8 x i8> zeroinitializer, %tmp2d ; <<8 x i8>> [#uses=1]
%tmp2abcd = mul <8 x i8> zeroinitializer, %tmp2bd ; <<8 x i8>> [#uses=1]
%tmp2ef = sub <8 x i8> zeroinitializer, %tmp2f ; <<8 x i8>> [#uses=1]
%tmp2efgh = mul <8 x i8> %tmp2ef, undef ; <<8 x i8>> [#uses=2]
- call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %A2, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp2efgh, i32 1)
+ call void @llvm.arm.neon.vst3.p0.v8i8(ptr %A2, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp2efgh, i32 1)
%tmp2 = sub <8 x i8> %tmp2efgh, %tmp2abcd ; <<8 x i8>> [#uses=1]
%tmp7 = mul <8 x i8> undef, %tmp2 ; <<8 x i8>> [#uses=1]
- tail call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %B, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp7, i32 1)
+ tail call void @llvm.arm.neon.vst3.p0.v8i8(ptr %B, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp7, i32 1)
ret <8 x i8> undef
}
-declare <4 x i32> @llvm.arm.neon.vld1.v4i32.p0i8(i8*, i32) nounwind readonly
+declare <4 x i32> @llvm.arm.neon.vld1.v4i32.p0(ptr, i32) nounwind readonly
-declare <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8*, i32) nounwind readonly
+declare <8 x i16> @llvm.arm.neon.vld1.v8i16.p0(ptr, i32) nounwind readonly
declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
-declare void @llvm.arm.neon.vst1.p0i8.v4i32(i8*, <4 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v4i32(ptr, <4 x i32>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v8i16(i8*, <8 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v8i16(ptr, <8 x i16>, i32) nounwind
-declare void @llvm.arm.neon.vst3.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32)
+declare void @llvm.arm.neon.vst3.p0.v8i8(ptr, <8 x i8>, <8 x i8>, <8 x i8>, i32)
nounwind
-declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8*, i32) nounwind readonly
+declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8*, i32) nounwind readonly
+declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
+declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
-declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0i8(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
+declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0(ptr, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
-declare void @llvm.arm.neon.vst2.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst2.p0.v4i32(ptr, <4 x i32>, <4 x i32>, i32) nounwind
declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
diff --git a/llvm/test/CodeGen/ARM/regpair_hint_phys.ll b/llvm/test/CodeGen/ARM/regpair_hint_phys.ll
index 8585a4c207c1c..882756743f26a 100644
--- a/llvm/test/CodeGen/ARM/regpair_hint_phys.ll
+++ b/llvm/test/CodeGen/ARM/regpair_hint_phys.ll
@@ -4,19 +4,19 @@
target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
target triple = "thumbv7-apple-tvos8.3.0"
-declare i8* @llvm.frameaddress(i32) #1
-declare i8* @llvm.returnaddress(i32) #1
+declare ptr @llvm.frameaddress(i32) #1
+declare ptr @llvm.returnaddress(i32) #1
@somevar = global [2 x i32] [i32 0, i32 0]
define void @__ubsan_handle_shift_out_of_bounds() #0 {
entry:
- %0 = tail call i8* @llvm.frameaddress(i32 0)
- %1 = ptrtoint i8* %0 to i32
- %2 = tail call i8* @llvm.returnaddress(i32 0)
- %3 = ptrtoint i8* %2 to i32
+ %0 = tail call ptr @llvm.frameaddress(i32 0)
+ %1 = ptrtoint ptr %0 to i32
+ %2 = tail call ptr @llvm.returnaddress(i32 0)
+ %3 = ptrtoint ptr %2 to i32
%val0 = insertvalue [2 x i32] [i32 undef, i32 undef], i32 %3, 0
%val1 = insertvalue [2 x i32] %val0, i32 %1, 1
- store [2 x i32] %val1, [2 x i32]* @somevar, align 8
+ store [2 x i32] %val1, ptr @somevar, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/relax-per-target-feature.ll b/llvm/test/CodeGen/ARM/relax-per-target-feature.ll
index 769c82b51d63c..71db2944c3884 100644
--- a/llvm/test/CodeGen/ARM/relax-per-target-feature.ll
+++ b/llvm/test/CodeGen/ARM/relax-per-target-feature.ll
@@ -11,7 +11,7 @@ declare dso_local void @g(...) local_unnamed_addr #2
define dso_local void @f() local_unnamed_addr #0 {
entry:
- tail call void bitcast (void (...)* @g to void ()*)() #3
+ tail call void @g() #3
ret void
}
; Function has thumb2 target-feature, tail call is allowed and must be widened.
@@ -20,7 +20,7 @@ entry:
define dso_local void @h() local_unnamed_addr #2 {
entry:
- tail call void bitcast (void (...)* @g to void ()*)() #3
+ tail call void @g() #3
ret void
}
; Function does not have thumb2 target-feature, tail call should not be
diff --git a/llvm/test/CodeGen/ARM/rotate.ll b/llvm/test/CodeGen/ARM/rotate.ll
index 1f5ecba613f33..e475b135cdbc1 100644
--- a/llvm/test/CodeGen/ARM/rotate.ll
+++ b/llvm/test/CodeGen/ARM/rotate.ll
@@ -3,7 +3,7 @@
;; This used to cause a backend crash about not being able to
;; select ROTL. Make sure if generates the basic VSHL/VSHR.
-define <2 x i64> @testcase(<2 x i64>* %in) {
+define <2 x i64> @testcase(ptr %in) {
; CHECK-LABEL: testcase:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -11,7 +11,7 @@ define <2 x i64> @testcase(<2 x i64>* %in) {
; CHECK-NEXT: vshl.i64 q8, q8, #56
; CHECK-NEXT: vorr q0, q8, q9
; CHECK-NEXT: bx lr
- %1 = load <2 x i64>, <2 x i64>* %in
+ %1 = load <2 x i64>, ptr %in
%2 = lshr <2 x i64> %1, <i64 8, i64 8>
%3 = shl <2 x i64> %1, <i64 56, i64 56>
%4 = or <2 x i64> %2, %3
diff --git a/llvm/test/CodeGen/ARM/saxpy10-a9.ll b/llvm/test/CodeGen/ARM/saxpy10-a9.ll
index 8245c47cbf84f..1920256e37296 100644
--- a/llvm/test/CodeGen/ARM/saxpy10-a9.ll
+++ b/llvm/test/CodeGen/ARM/saxpy10-a9.ll
@@ -61,74 +61,74 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-
; CHECK-NEXT: bx
;
; This accumulates a sum rather than storing each result.
-define float @saxpy10(float* nocapture readonly %data1, float* nocapture readonly %data2, float %a) {
+define float @saxpy10(ptr nocapture readonly %data1, ptr nocapture readonly %data2, float %a) {
entry:
- %0 = load float, float* %data1, align 4
+ %0 = load float, ptr %data1, align 4
%mul = fmul float %0, %a
- %1 = load float, float* %data2, align 4
+ %1 = load float, ptr %data2, align 4
%add = fadd float %mul, %1
%add2 = fadd float %add, 0.000000e+00
- %arrayidx.1 = getelementptr inbounds float, float* %data1, i32 1
- %2 = load float, float* %arrayidx.1, align 4
+ %arrayidx.1 = getelementptr inbounds float, ptr %data1, i32 1
+ %2 = load float, ptr %arrayidx.1, align 4
%mul.1 = fmul float %2, %a
- %arrayidx1.1 = getelementptr inbounds float, float* %data2, i32 1
- %3 = load float, float* %arrayidx1.1, align 4
+ %arrayidx1.1 = getelementptr inbounds float, ptr %data2, i32 1
+ %3 = load float, ptr %arrayidx1.1, align 4
%add.1 = fadd float %mul.1, %3
%add2.1 = fadd float %add2, %add.1
- %arrayidx.2 = getelementptr inbounds float, float* %data1, i32 2
- %4 = load float, float* %arrayidx.2, align 4
+ %arrayidx.2 = getelementptr inbounds float, ptr %data1, i32 2
+ %4 = load float, ptr %arrayidx.2, align 4
%mul.2 = fmul float %4, %a
- %arrayidx1.2 = getelementptr inbounds float, float* %data2, i32 2
- %5 = load float, float* %arrayidx1.2, align 4
+ %arrayidx1.2 = getelementptr inbounds float, ptr %data2, i32 2
+ %5 = load float, ptr %arrayidx1.2, align 4
%add.2 = fadd float %mul.2, %5
%add2.2 = fadd float %add2.1, %add.2
- %arrayidx.3 = getelementptr inbounds float, float* %data1, i32 3
- %6 = load float, float* %arrayidx.3, align 4
+ %arrayidx.3 = getelementptr inbounds float, ptr %data1, i32 3
+ %6 = load float, ptr %arrayidx.3, align 4
%mul.3 = fmul float %6, %a
- %arrayidx1.3 = getelementptr inbounds float, float* %data2, i32 3
- %7 = load float, float* %arrayidx1.3, align 4
+ %arrayidx1.3 = getelementptr inbounds float, ptr %data2, i32 3
+ %7 = load float, ptr %arrayidx1.3, align 4
%add.3 = fadd float %mul.3, %7
%add2.3 = fadd float %add2.2, %add.3
- %arrayidx.4 = getelementptr inbounds float, float* %data1, i32 4
- %8 = load float, float* %arrayidx.4, align 4
+ %arrayidx.4 = getelementptr inbounds float, ptr %data1, i32 4
+ %8 = load float, ptr %arrayidx.4, align 4
%mul.4 = fmul float %8, %a
- %arrayidx1.4 = getelementptr inbounds float, float* %data2, i32 4
- %9 = load float, float* %arrayidx1.4, align 4
+ %arrayidx1.4 = getelementptr inbounds float, ptr %data2, i32 4
+ %9 = load float, ptr %arrayidx1.4, align 4
%add.4 = fadd float %mul.4, %9
%add2.4 = fadd float %add2.3, %add.4
- %arrayidx.5 = getelementptr inbounds float, float* %data1, i32 5
- %10 = load float, float* %arrayidx.5, align 4
+ %arrayidx.5 = getelementptr inbounds float, ptr %data1, i32 5
+ %10 = load float, ptr %arrayidx.5, align 4
%mul.5 = fmul float %10, %a
- %arrayidx1.5 = getelementptr inbounds float, float* %data2, i32 5
- %11 = load float, float* %arrayidx1.5, align 4
+ %arrayidx1.5 = getelementptr inbounds float, ptr %data2, i32 5
+ %11 = load float, ptr %arrayidx1.5, align 4
%add.5 = fadd float %mul.5, %11
%add2.5 = fadd float %add2.4, %add.5
- %arrayidx.6 = getelementptr inbounds float, float* %data1, i32 6
- %12 = load float, float* %arrayidx.6, align 4
+ %arrayidx.6 = getelementptr inbounds float, ptr %data1, i32 6
+ %12 = load float, ptr %arrayidx.6, align 4
%mul.6 = fmul float %12, %a
- %arrayidx1.6 = getelementptr inbounds float, float* %data2, i32 6
- %13 = load float, float* %arrayidx1.6, align 4
+ %arrayidx1.6 = getelementptr inbounds float, ptr %data2, i32 6
+ %13 = load float, ptr %arrayidx1.6, align 4
%add.6 = fadd float %mul.6, %13
%add2.6 = fadd float %add2.5, %add.6
- %arrayidx.7 = getelementptr inbounds float, float* %data1, i32 7
- %14 = load float, float* %arrayidx.7, align 4
+ %arrayidx.7 = getelementptr inbounds float, ptr %data1, i32 7
+ %14 = load float, ptr %arrayidx.7, align 4
%mul.7 = fmul float %14, %a
- %arrayidx1.7 = getelementptr inbounds float, float* %data2, i32 7
- %15 = load float, float* %arrayidx1.7, align 4
+ %arrayidx1.7 = getelementptr inbounds float, ptr %data2, i32 7
+ %15 = load float, ptr %arrayidx1.7, align 4
%add.7 = fadd float %mul.7, %15
%add2.7 = fadd float %add2.6, %add.7
- %arrayidx.8 = getelementptr inbounds float, float* %data1, i32 8
- %16 = load float, float* %arrayidx.8, align 4
+ %arrayidx.8 = getelementptr inbounds float, ptr %data1, i32 8
+ %16 = load float, ptr %arrayidx.8, align 4
%mul.8 = fmul float %16, %a
- %arrayidx1.8 = getelementptr inbounds float, float* %data2, i32 8
- %17 = load float, float* %arrayidx1.8, align 4
+ %arrayidx1.8 = getelementptr inbounds float, ptr %data2, i32 8
+ %17 = load float, ptr %arrayidx1.8, align 4
%add.8 = fadd float %mul.8, %17
%add2.8 = fadd float %add2.7, %add.8
- %arrayidx.9 = getelementptr inbounds float, float* %data1, i32 9
- %18 = load float, float* %arrayidx.9, align 4
+ %arrayidx.9 = getelementptr inbounds float, ptr %data1, i32 9
+ %18 = load float, ptr %arrayidx.9, align 4
%mul.9 = fmul float %18, %a
- %arrayidx1.9 = getelementptr inbounds float, float* %data2, i32 9
- %19 = load float, float* %arrayidx1.9, align 4
+ %arrayidx1.9 = getelementptr inbounds float, ptr %data2, i32 9
+ %19 = load float, ptr %arrayidx1.9, align 4
%add.9 = fadd float %mul.9, %19
%add2.9 = fadd float %add2.8, %add.9
ret float %add2.9
diff --git a/llvm/test/CodeGen/ARM/section.ll b/llvm/test/CodeGen/ARM/section.ll
index 27620562c1631..686376392448a 100644
--- a/llvm/test/CodeGen/ARM/section.ll
+++ b/llvm/test/CodeGen/ARM/section.ll
@@ -2,5 +2,5 @@
; CHECK: .section .dtors,"aw",%progbits
; CHECK: __DTOR_END__:
- at __DTOR_END__ = internal global [1 x i32] zeroinitializer, section ".dtors" ; <[1 x i32]*> [#uses=0]
+ at __DTOR_END__ = internal global [1 x i32] zeroinitializer, section ".dtors" ; <ptr> [#uses=0]
diff --git a/llvm/test/CodeGen/ARM/segmented-stacks-dynamic.ll b/llvm/test/CodeGen/ARM/segmented-stacks-dynamic.ll
index 65d25cad386e0..6bfa7a3508b20 100644
--- a/llvm/test/CodeGen/ARM/segmented-stacks-dynamic.ll
+++ b/llvm/test/CodeGen/ARM/segmented-stacks-dynamic.ll
@@ -4,11 +4,11 @@
; RUN: llc < %s -mtriple=arm-linux-unknown-gnueabi -mattr=+v4t -filetype=obj
; Just to prevent the alloca from being optimized away
-declare void @dummy_use(i32*, i32)
+declare void @dummy_use(ptr, i32)
define i32 @test_basic(i32 %l) #0 {
%mem = alloca i32, i32 %l
- call void @dummy_use (i32* %mem, i32 %l)
+ call void @dummy_use (ptr %mem, i32 %l)
%terminate = icmp eq i32 %l, 0
br i1 %terminate, label %true, label %false
diff --git a/llvm/test/CodeGen/ARM/segmented-stacks.ll b/llvm/test/CodeGen/ARM/segmented-stacks.ll
index 38617122cbd31..3acae3ccf3236 100644
--- a/llvm/test/CodeGen/ARM/segmented-stacks.ll
+++ b/llvm/test/CodeGen/ARM/segmented-stacks.ll
@@ -7,11 +7,11 @@
; Just to prevent the alloca from being optimized away
-declare void @dummy_use(i32*, i32)
+declare void @dummy_use(ptr, i32)
define void @test_basic() #0 {
%mem = alloca i32, i32 10
- call void @dummy_use (i32* %mem, i32 10)
+ call void @dummy_use (ptr %mem, i32 10)
ret void
; ARM-linux-LABEL: test_basic:
@@ -54,11 +54,11 @@ define void @test_basic() #0 {
}
-define i32 @test_nested(i32 * nest %closure, i32 %other) #0 {
- %addend = load i32 , i32 * %closure
+define i32 @test_nested(ptr nest %closure, i32 %other) #0 {
+ %addend = load i32 , ptr %closure
%result = add i32 %other, %addend
%mem = alloca i32, i32 10
- call void @dummy_use (i32* %mem, i32 10)
+ call void @dummy_use (ptr %mem, i32 10)
ret i32 %result
; ARM-linux-LABEL: test_nested:
@@ -103,7 +103,7 @@ define i32 @test_nested(i32 * nest %closure, i32 %other) #0 {
define void @test_large() #0 {
%mem = alloca i32, i32 10000
- call void @dummy_use (i32* %mem, i32 0)
+ call void @dummy_use (ptr %mem, i32 0)
ret void
; ARM-linux-LABEL: test_large:
@@ -156,7 +156,7 @@ define void @test_large() #0 {
define fastcc void @test_fastcc() #0 {
%mem = alloca i32, i32 10
- call void @dummy_use (i32* %mem, i32 10)
+ call void @dummy_use (ptr %mem, i32 10)
ret void
; ARM-linux-LABEL: test_fastcc:
@@ -201,7 +201,7 @@ define fastcc void @test_fastcc() #0 {
define fastcc void @test_fastcc_large() #0 {
%mem = alloca i32, i32 10000
- call void @dummy_use (i32* %mem, i32 0)
+ call void @dummy_use (ptr %mem, i32 0)
ret void
; ARM-linux-LABEL: test_fastcc_large:
diff --git a/llvm/test/CodeGen/ARM/select-imm.ll b/llvm/test/CodeGen/ARM/select-imm.ll
index 646ec1d2e0a1d..1b88cbeeeb6ad 100644
--- a/llvm/test/CodeGen/ARM/select-imm.ll
+++ b/llvm/test/CodeGen/ARM/select-imm.ll
@@ -422,7 +422,7 @@ entry:
}
; ARM scheduler emits icmp/zext before both calls, so isn't relevant
-define void @t9(i8* %a, i8 %b) {
+define void @t9(ptr %a, i8 %b) {
; ARM-LABEL: t9:
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: .save {r4, lr}
@@ -542,7 +542,7 @@ define void @t9(i8* %a, i8 %b) {
; V8MBASE-NEXT: .LBB8_3: @ %while.end
; V8MBASE-NEXT: pop {r4, pc}
entry:
- %0 = load i8, i8* %a
+ %0 = load i8, ptr %a
%conv = sext i8 %0 to i32
%conv119 = zext i8 %0 to i32
%conv522 = and i32 %conv, 255
@@ -667,10 +667,10 @@ define i1 @t10() {
entry:
%q = alloca i32
%p = alloca i32
- store i32 -3, i32* %q
- store i32 -8, i32* %p
- %0 = load i32, i32* %q
- %1 = load i32, i32* %p
+ store i32 -3, ptr %q
+ store i32 -8, ptr %p
+ %0 = load i32, ptr %q
+ %1 = load i32, ptr %p
%div = sdiv i32 %0, %1
%mul = mul nsw i32 %div, %1
%rem = srem i32 %0, %1
@@ -805,18 +805,18 @@ define i1 @t11() {
; V8MBASE-NEXT: bx lr
entry:
%bit = alloca i32
- %load = load i32, i32* %bit
+ %load = load i32, ptr %bit
%clear = and i32 %load, -4096
%set = or i32 %clear, 33
- store i32 %set, i32* %bit
- %load1 = load i32, i32* %bit
+ store i32 %set, ptr %bit
+ %load1 = load i32, ptr %bit
%clear2 = and i32 %load1, -33550337
%set3 = or i32 %clear2, 40960
%clear5 = and i32 %set3, 4095
%rem = srem i32 %clear5, 10
%clear9 = and i32 %set3, -4096
%set10 = or i32 %clear9, %rem
- store i32 %set10, i32* %bit
+ store i32 %set10, ptr %bit
%clear12 = and i32 %set10, 4095
%cmp = icmp eq i32 %clear12, 3
ret i1 %cmp
diff --git a/llvm/test/CodeGen/ARM/select.ll b/llvm/test/CodeGen/ARM/select.ll
index dbec6dd57090c..4bb79651f0402 100644
--- a/llvm/test/CodeGen/ARM/select.ll
+++ b/llvm/test/CodeGen/ARM/select.ll
@@ -100,10 +100,10 @@ define arm_apcscc float @f8(i32 %a) nounwind {
; scheduler to assert.
; CHECK-VFP-LABEL: f9:
-declare i8* @objc_msgSend(i8*, i8*, ...)
+declare ptr @objc_msgSend(ptr, ptr, ...)
define void @f9() optsize {
entry:
- %cmp = icmp eq i8* undef, inttoptr (i32 4 to i8*)
+ %cmp = icmp eq ptr undef, inttoptr (i32 4 to ptr)
%conv191 = select i1 %cmp, float -3.000000e+00, float 0.000000e+00
%conv195 = select i1 %cmp, double -1.000000e+00, double 0.000000e+00
%add = fadd double %conv195, 1.100000e+01
@@ -113,7 +113,7 @@ entry:
%tmp478 = bitcast float %add201 to i32
%tmp490 = insertvalue [2 x i32] undef, i32 %tmp484, 0
%tmp493 = insertvalue [2 x i32] %tmp490, i32 %tmp478, 1
- call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, [2 x i32], i32, float)*)(i8* undef, i8* undef, [2 x i32] %tmp493, i32 0, float 1.000000e+00) optsize
+ call void @objc_msgSend(ptr undef, ptr undef, [2 x i32] %tmp493, i32 0, float 1.000000e+00) optsize
ret void
}
diff --git a/llvm/test/CodeGen/ARM/select_xform.ll b/llvm/test/CodeGen/ARM/select_xform.ll
index 159ff50fcf2fa..382536fc91d6d 100644
--- a/llvm/test/CodeGen/ARM/select_xform.ll
+++ b/llvm/test/CodeGen/ARM/select_xform.ll
@@ -283,13 +283,13 @@ define void @pr13628() nounwind uwtable align 2 {
; T2-NEXT: add sp, #256
; T2-NEXT: pop {r7, pc}
%x3 = alloca i8, i32 256, align 8
- %x4 = load i8, i8* undef, align 1
+ %x4 = load i8, ptr undef, align 1
%x5 = icmp ne i8 %x4, 0
- %x6 = select i1 %x5, i8* %x3, i8* null
- call void @bar(i8* %x6) nounwind
+ %x6 = select i1 %x5, ptr %x3, ptr null
+ call void @bar(ptr %x6) nounwind
ret void
}
-declare void @bar(i8*)
+declare void @bar(ptr)
; Fold zext i1 into predicated add
define i32 @t13(i32 %c, i32 %a) nounwind readnone ssp {
diff --git a/llvm/test/CodeGen/ARM/setcc-type-mismatch.ll b/llvm/test/CodeGen/ARM/setcc-type-mismatch.ll
index 2cfdba12db54a..e4ac43daa6c92 100644
--- a/llvm/test/CodeGen/ARM/setcc-type-mismatch.ll
+++ b/llvm/test/CodeGen/ARM/setcc-type-mismatch.ll
@@ -1,11 +1,11 @@
; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s
-define void @test_mismatched_setcc(<4 x i22> %l, <4 x i22> %r, <4 x i1>* %addr) {
+define void @test_mismatched_setcc(<4 x i22> %l, <4 x i22> %r, ptr %addr) {
; CHECK-LABEL: test_mismatched_setcc:
; CHECK: vceq.i32 [[CMP128:q[0-9]+]], {{q[0-9]+}}, {{q[0-9]+}}
; CHECK: vmovn.i32 {{d[0-9]+}}, [[CMP128]]
%tst = icmp eq <4 x i22> %l, %r
- store <4 x i1> %tst, <4 x i1>* %addr
+ store <4 x i1> %tst, ptr %addr
ret void
}
diff --git a/llvm/test/CodeGen/ARM/setjmp-bti-basic.ll b/llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
index 4c10cd6ebcbe6..41ba125ae5c15 100644
--- a/llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
+++ b/llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
@@ -27,7 +27,7 @@ define i32 @foo(i32 %x) {
; NOBTI-NOT: bti
entry:
- %call = call i32 @setjmp(i64* getelementptr inbounds ([20 x i64], [20 x i64]* @buf, i32 0, i32 0)) #0
+ %call = call i32 @setjmp(ptr @buf) #0
%tobool.not = icmp eq i32 %call, 0
br i1 %tobool.not, label %if.else, label %if.end
@@ -41,7 +41,7 @@ if.end: ; preds = %entry, %if.else
}
declare void @bar(i32)
-declare i32 @setjmp(i64*) #0
+declare i32 @setjmp(ptr) #0
attributes #0 = { returns_twice }
diff --git a/llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll b/llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll
index c168eb2cdd2da..2ff1a6df1f1ac 100644
--- a/llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll
+++ b/llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll
@@ -33,14 +33,14 @@ define i32 @f(i32 %a, i32 %b, i32 %c, i32 %d) {
; NOBTI-NEXT: cbz r0, .LBB0_2
entry:
%a.addr = alloca i32, align 4
- store i32 %a, i32* %a.addr, align 4
- %call = call i32 @setjmp(i64* getelementptr inbounds ([20 x i64], [20 x i64]* @buf, i32 0, i32 0)) #0
+ store i32 %a, ptr %a.addr, align 4
+ %call = call i32 @setjmp(ptr @buf) #0
%cmp.not = icmp eq i32 %call, 0
br i1 %cmp.not, label %if.end, label %return
if.end: ; preds = %entry
- call void @h(i32 %a, i32 %b, i32* nonnull %a.addr)
- %0 = load i32, i32* %a.addr, align 4
+ call void @h(i32 %a, i32 %b, ptr nonnull %a.addr)
+ %0 = load i32, ptr %a.addr, align 4
%add = add nsw i32 %0, %b
%mul = mul nsw i32 %add, %0
%add1 = add nsw i32 %d, %c
@@ -62,14 +62,14 @@ define i32 @g(i32 %a, i32 %b, i32 %c, i32 %d) {
; NOBTI-NEXT: cbz r0, .LBB1_2
entry:
%a.addr = alloca i32, align 4
- store i32 %a, i32* %a.addr, align 4
- %call = call i32 @setjmp(i64* getelementptr inbounds ([20 x i64], [20 x i64]* @buf, i32 0, i32 0)) #0
+ store i32 %a, ptr %a.addr, align 4
+ %call = call i32 @setjmp(ptr @buf) #0
%cmp.not = icmp eq i32 %call, 0
br i1 %cmp.not, label %if.end, label %return
if.end: ; preds = %entry
- call void @h(i32 %a, i32 %b, i32* nonnull %a.addr)
- %0 = load i32, i32* %a.addr, align 4
+ call void @h(i32 %a, i32 %b, ptr nonnull %a.addr)
+ %0 = load i32, ptr %a.addr, align 4
%add = add nsw i32 %0, %b
%mul = mul nsw i32 %add, %0
%add1 = add nsw i32 %d, %c
@@ -82,8 +82,8 @@ return: ; preds = %entry, %if.end
ret i32 %retval.0
}
-declare void @h(i32, i32, i32*)
-declare i32 @setjmp(i64*) #0
+declare void @h(i32, i32, ptr)
+declare i32 @setjmp(ptr) #0
attributes #0 = { returns_twice }
diff --git a/llvm/test/CodeGen/ARM/setjmp_longjmp.ll b/llvm/test/CodeGen/ARM/setjmp_longjmp.ll
index 21eac987f5e82..ddc1de3e31d38 100644
--- a/llvm/test/CodeGen/ARM/setjmp_longjmp.ll
+++ b/llvm/test/CodeGen/ARM/setjmp_longjmp.ll
@@ -3,18 +3,18 @@
; RUN: llc -mtriple=thumbv7-win32 -exception-model sjlj -simplifycfg-require-and-preserve-domtree=1 %s -o - | FileCheck %s -check-prefix CHECK-WIN32
target triple = "armv7-apple-ios"
-declare i32 @llvm.eh.sjlj.setjmp(i8*)
-declare void @llvm.eh.sjlj.longjmp(i8*)
+declare i32 @llvm.eh.sjlj.setjmp(ptr)
+declare void @llvm.eh.sjlj.longjmp(ptr)
@g = external global i32
declare void @may_throw()
declare i32 @__gxx_personality_sj0(...)
-declare i8* @__cxa_begin_catch(i8*)
+declare ptr @__cxa_begin_catch(ptr)
declare void @__cxa_end_catch()
-declare i32 @llvm.eh.typeid.for(i8*)
-declare i8* @llvm.frameaddress(i32)
-declare i8* @llvm.stacksave()
- at _ZTIPKc = external constant i8*
+declare i32 @llvm.eh.typeid.for(ptr)
+declare ptr @llvm.frameaddress(i32)
+declare ptr @llvm.stacksave()
+ at _ZTIPKc = external constant ptr
; CHECK-LABEL: foobar
;
@@ -42,22 +42,20 @@ declare i8* @llvm.stacksave()
; CHECK-WIN32-NEXT: ldr.w pc, [[[BUFREG]], #4]
define void @foobar() {
entry:
- %buf = alloca [5 x i8*], align 4
- %arraydecay = getelementptr inbounds [5 x i8*], [5 x i8*]* %buf, i32 0, i32 0
- %bufptr = bitcast i8** %arraydecay to i8*
+ %buf = alloca [5 x ptr], align 4
; Note: This is simplified, in reality you have to store the framepointer +
; stackpointer in the buffer as well for this to be legal!
- %setjmpres = call i32 @llvm.eh.sjlj.setjmp(i8* %bufptr)
+ %setjmpres = call i32 @llvm.eh.sjlj.setjmp(ptr %buf)
%tobool = icmp ne i32 %setjmpres, 0
br i1 %tobool, label %if.then, label %if.else
if.then:
- store volatile i32 1, i32* @g, align 4
+ store volatile i32 1, ptr @g, align 4
br label %if.end
if.else:
- store volatile i32 0, i32* @g, align 4
- call void @llvm.eh.sjlj.longjmp(i8* %bufptr)
+ store volatile i32 0, ptr @g, align 4
+ call void @llvm.eh.sjlj.longjmp(ptr %buf)
unreachable
if.end:
@@ -80,45 +78,43 @@ if.end:
; CHECK-NEXT: ldr [[DESTREG:r[0-9]+]], [[[BUFREG]], #4]
; CHECK-NEXT: ldr r7, [[[BUFREG]]]
; CHECK-NEXT: bx [[DESTREG]]
-define void @combine_sjlj_eh_and_setjmp_longjmp() personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
+define void @combine_sjlj_eh_and_setjmp_longjmp() personality ptr @__gxx_personality_sj0 {
entry:
- %buf = alloca [5 x i8*], align 4
+ %buf = alloca [5 x ptr], align 4
invoke void @may_throw() to label %try.cont unwind label %lpad
lpad:
- %0 = landingpad { i8*, i32 } catch i8* bitcast (i8** @_ZTIPKc to i8*)
- %1 = extractvalue { i8*, i32 } %0, 1
- %2 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIPKc to i8*)) #3
+ %0 = landingpad { ptr, i32 } catch ptr @_ZTIPKc
+ %1 = extractvalue { ptr, i32 } %0, 1
+ %2 = tail call i32 @llvm.eh.typeid.for(ptr @_ZTIPKc) #3
%matches = icmp eq i32 %1, %2
br i1 %matches, label %catch, label %eh.resume
catch:
- %3 = extractvalue { i8*, i32 } %0, 0
- %4 = tail call i8* @__cxa_begin_catch(i8* %3) #3
- store volatile i32 0, i32* @g, align 4
- %5 = bitcast [5 x i8*]* %buf to i8*
- %arraydecay = getelementptr inbounds [5 x i8*], [5 x i8*]* %buf, i64 0, i64 0
- %6 = tail call i8* @llvm.frameaddress(i32 0)
- store i8* %6, i8** %arraydecay, align 16
- %7 = tail call i8* @llvm.stacksave()
- %8 = getelementptr [5 x i8*], [5 x i8*]* %buf, i64 0, i64 2
- store i8* %7, i8** %8, align 16
- %9 = call i32 @llvm.eh.sjlj.setjmp(i8* %5)
- %tobool = icmp eq i32 %9, 0
+ %3 = extractvalue { ptr, i32 } %0, 0
+ %4 = tail call ptr @__cxa_begin_catch(ptr %3) #3
+ store volatile i32 0, ptr @g, align 4
+ %5 = tail call ptr @llvm.frameaddress(i32 0)
+ store ptr %5, ptr %buf, align 16
+ %6 = tail call ptr @llvm.stacksave()
+ %7 = getelementptr [5 x ptr], ptr %buf, i64 0, i64 2
+ store ptr %6, ptr %7, align 16
+ %8 = call i32 @llvm.eh.sjlj.setjmp(ptr %buf)
+ %tobool = icmp eq i32 %8, 0
br i1 %tobool, label %if.else, label %if.then
if.then:
- store volatile i32 2, i32* @g, align 4
+ store volatile i32 2, ptr @g, align 4
call void @__cxa_end_catch() #3
br label %try.cont
if.else:
- store volatile i32 1, i32* @g, align 4
- call void @llvm.eh.sjlj.longjmp(i8* %5)
+ store volatile i32 1, ptr @g, align 4
+ call void @llvm.eh.sjlj.longjmp(ptr %buf)
unreachable
eh.resume:
- resume { i8*, i32 } %0
+ resume { ptr, i32 } %0
try.cont:
ret void
diff --git a/llvm/test/CodeGen/ARM/shift-combine.ll b/llvm/test/CodeGen/ARM/shift-combine.ll
index ea2b9dcac9059..0dd5007b4a413 100644
--- a/llvm/test/CodeGen/ARM/shift-combine.ll
+++ b/llvm/test/CodeGen/ARM/shift-combine.ll
@@ -39,8 +39,8 @@ define i32 @test_lshr_and1(i32 %x) {
entry:
%tmp2 = lshr i32 %x, 2
%tmp3 = and i32 %tmp2, 3
- %tmp4 = getelementptr [4 x i32], [4 x i32]* @array, i32 0, i32 %tmp3
- %tmp5 = load i32, i32* %tmp4, align 4
+ %tmp4 = getelementptr [4 x i32], ptr @array, i32 0, i32 %tmp3
+ %tmp5 = load i32, ptr %tmp4, align 4
ret i32 %tmp5
}
define i32 @test_lshr_and2(i32 %x) {
@@ -83,7 +83,7 @@ entry:
ret i32 %e
}
-define arm_aapcscc i32 @test_lshr_load1(i16* %a) {
+define arm_aapcscc i32 @test_lshr_load1(ptr %a) {
; CHECK-COMMON-LABEL: test_lshr_load1:
; CHECK-COMMON: @ %bb.0: @ %entry
; CHECK-COMMON-NEXT: ldrb r0, [r0, #1]
@@ -99,13 +99,13 @@ define arm_aapcscc i32 @test_lshr_load1(i16* %a) {
; CHECK-V6M-NEXT: ldrb r0, [r0, #1]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i16, i16* %a, align 2
+ %0 = load i16, ptr %a, align 2
%conv1 = zext i16 %0 to i32
%1 = lshr i32 %conv1, 8
ret i32 %1
}
-define arm_aapcscc i32 @test_lshr_load1_sext(i16* %a) {
+define arm_aapcscc i32 @test_lshr_load1_sext(ptr %a) {
; CHECK-ARM-LABEL: test_lshr_load1_sext:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: ldrsh r0, [r0]
@@ -137,13 +137,13 @@ define arm_aapcscc i32 @test_lshr_load1_sext(i16* %a) {
; CHECK-V6M-NEXT: lsrs r0, r0, #8
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i16, i16* %a, align 2
+ %0 = load i16, ptr %a, align 2
%conv1 = sext i16 %0 to i32
%1 = lshr i32 %conv1, 8
ret i32 %1
}
-define arm_aapcscc i32 @test_lshr_load1_fail(i16* %a) {
+define arm_aapcscc i32 @test_lshr_load1_fail(ptr %a) {
; CHECK-ARM-LABEL: test_lshr_load1_fail:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: ldrh r0, [r0]
@@ -174,13 +174,13 @@ define arm_aapcscc i32 @test_lshr_load1_fail(i16* %a) {
; CHECK-V6M-NEXT: lsrs r0, r0, #9
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i16, i16* %a, align 2
+ %0 = load i16, ptr %a, align 2
%conv1 = zext i16 %0 to i32
%1 = lshr i32 %conv1, 9
ret i32 %1
}
-define arm_aapcscc i32 @test_lshr_load32(i32* %a) {
+define arm_aapcscc i32 @test_lshr_load32(ptr %a) {
; CHECK-ARM-LABEL: test_lshr_load32:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: ldr r0, [r0]
@@ -211,12 +211,12 @@ define arm_aapcscc i32 @test_lshr_load32(i32* %a) {
; CHECK-V6M-NEXT: lsrs r0, r0, #8
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i32, i32* %a, align 4
+ %0 = load i32, ptr %a, align 4
%1 = lshr i32 %0, 8
ret i32 %1
}
-define arm_aapcscc i32 @test_lshr_load32_2(i32* %a) {
+define arm_aapcscc i32 @test_lshr_load32_2(ptr %a) {
; CHECK-COMMON-LABEL: test_lshr_load32_2:
; CHECK-COMMON: @ %bb.0: @ %entry
; CHECK-COMMON-NEXT: ldrh r0, [r0, #2]
@@ -232,12 +232,12 @@ define arm_aapcscc i32 @test_lshr_load32_2(i32* %a) {
; CHECK-V6M-NEXT: ldrh r0, [r0, #2]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i32, i32* %a, align 4
+ %0 = load i32, ptr %a, align 4
%1 = lshr i32 %0, 16
ret i32 %1
}
-define arm_aapcscc i32 @test_lshr_load32_1(i32* %a) {
+define arm_aapcscc i32 @test_lshr_load32_1(ptr %a) {
; CHECK-COMMON-LABEL: test_lshr_load32_1:
; CHECK-COMMON: @ %bb.0: @ %entry
; CHECK-COMMON-NEXT: ldrb r0, [r0, #3]
@@ -253,12 +253,12 @@ define arm_aapcscc i32 @test_lshr_load32_1(i32* %a) {
; CHECK-V6M-NEXT: ldrb r0, [r0, #3]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i32, i32* %a, align 4
+ %0 = load i32, ptr %a, align 4
%1 = lshr i32 %0, 24
ret i32 %1
}
-define arm_aapcscc i32 @test_lshr_load32_fail(i32* %a) {
+define arm_aapcscc i32 @test_lshr_load32_fail(ptr %a) {
; CHECK-ARM-LABEL: test_lshr_load32_fail:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: ldr r0, [r0]
@@ -289,12 +289,12 @@ define arm_aapcscc i32 @test_lshr_load32_fail(i32* %a) {
; CHECK-V6M-NEXT: lsrs r0, r0, #15
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i32, i32* %a, align 4
+ %0 = load i32, ptr %a, align 4
%1 = lshr i32 %0, 15
ret i32 %1
}
-define arm_aapcscc i32 @test_lshr_load64_4_unaligned(i64* %a) {
+define arm_aapcscc i32 @test_lshr_load64_4_unaligned(ptr %a) {
; CHECK-ARM-LABEL: test_lshr_load64_4_unaligned:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: ldr r0, [r0, #2]
@@ -325,13 +325,13 @@ define arm_aapcscc i32 @test_lshr_load64_4_unaligned(i64* %a) {
; CHECK-V6M-NEXT: adds r0, r1, r0
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i64, i64* %a, align 8
+ %0 = load i64, ptr %a, align 8
%1 = lshr i64 %0, 16
%conv = trunc i64 %1 to i32
ret i32 %conv
}
-define arm_aapcscc i32 @test_lshr_load64_1_lsb(i64* %a) {
+define arm_aapcscc i32 @test_lshr_load64_1_lsb(ptr %a) {
; CHECK-ARM-LABEL: test_lshr_load64_1_lsb:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: ldr r0, [r0, #3]
@@ -362,13 +362,13 @@ define arm_aapcscc i32 @test_lshr_load64_1_lsb(i64* %a) {
; CHECK-V6M-NEXT: adds r0, r1, r0
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i64, i64* %a, align 8
+ %0 = load i64, ptr %a, align 8
%1 = lshr i64 %0, 24
%conv = trunc i64 %1 to i32
ret i32 %conv
}
-define arm_aapcscc i32 @test_lshr_load64_1_msb(i64* %a) {
+define arm_aapcscc i32 @test_lshr_load64_1_msb(ptr %a) {
; CHECK-COMMON-LABEL: test_lshr_load64_1_msb:
; CHECK-COMMON: @ %bb.0: @ %entry
; CHECK-COMMON-NEXT: ldrb r0, [r0, #7]
@@ -384,13 +384,13 @@ define arm_aapcscc i32 @test_lshr_load64_1_msb(i64* %a) {
; CHECK-V6M-NEXT: ldrb r0, [r0, #7]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i64, i64* %a, align 8
+ %0 = load i64, ptr %a, align 8
%1 = lshr i64 %0, 56
%conv = trunc i64 %1 to i32
ret i32 %conv
}
-define arm_aapcscc i32 @test_lshr_load64_4(i64* %a) {
+define arm_aapcscc i32 @test_lshr_load64_4(ptr %a) {
; CHECK-COMMON-LABEL: test_lshr_load64_4:
; CHECK-COMMON: @ %bb.0: @ %entry
; CHECK-COMMON-NEXT: ldr r0, [r0, #4]
@@ -406,13 +406,13 @@ define arm_aapcscc i32 @test_lshr_load64_4(i64* %a) {
; CHECK-V6M-NEXT: ldr r0, [r0, #4]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i64, i64* %a, align 8
+ %0 = load i64, ptr %a, align 8
%1 = lshr i64 %0, 32
%conv = trunc i64 %1 to i32
ret i32 %conv
}
-define arm_aapcscc i32 @test_lshr_load64_2(i64* %a) {
+define arm_aapcscc i32 @test_lshr_load64_2(ptr %a) {
; CHECK-COMMON-LABEL: test_lshr_load64_2:
; CHECK-COMMON: @ %bb.0: @ %entry
; CHECK-COMMON-NEXT: ldrh r0, [r0, #6]
@@ -428,13 +428,13 @@ define arm_aapcscc i32 @test_lshr_load64_2(i64* %a) {
; CHECK-V6M-NEXT: ldrh r0, [r0, #6]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i64, i64* %a, align 8
+ %0 = load i64, ptr %a, align 8
%1 = lshr i64 %0, 48
%conv = trunc i64 %1 to i32
ret i32 %conv
}
-define arm_aapcscc i32 @test_lshr_load4_fail(i64* %a) {
+define arm_aapcscc i32 @test_lshr_load4_fail(ptr %a) {
; CHECK-ARM-LABEL: test_lshr_load4_fail:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: ldr r0, [r0, #1]
@@ -466,13 +466,13 @@ define arm_aapcscc i32 @test_lshr_load4_fail(i64* %a) {
; CHECK-V6M-NEXT: adds r0, r1, r0
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i64, i64* %a, align 8
+ %0 = load i64, ptr %a, align 8
%1 = lshr i64 %0, 8
%conv = trunc i64 %1 to i32
ret i32 %conv
}
-define arm_aapcscc void @test_shift7_mask8(i32* nocapture %p) {
+define arm_aapcscc void @test_shift7_mask8(ptr nocapture %p) {
; CHECK-COMMON-LABEL: test_shift7_mask8:
; CHECK-COMMON: @ %bb.0: @ %entry
; CHECK-COMMON-NEXT: ldr r1, [r0]
@@ -495,14 +495,14 @@ define arm_aapcscc void @test_shift7_mask8(i32* nocapture %p) {
; CHECK-V6M-NEXT: str r1, [r0]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i32, i32* %p, align 4
+ %0 = load i32, ptr %p, align 4
%shl = lshr i32 %0, 7
%and = and i32 %shl, 255
- store i32 %and, i32* %p, align 4
+ store i32 %and, ptr %p, align 4
ret void
}
-define arm_aapcscc void @test_shift8_mask8(i32* nocapture %p) {
+define arm_aapcscc void @test_shift8_mask8(ptr nocapture %p) {
; CHECK-COMMON-LABEL: test_shift8_mask8:
; CHECK-COMMON: @ %bb.0: @ %entry
; CHECK-COMMON-NEXT: ldrb r1, [r0, #1]
@@ -521,14 +521,14 @@ define arm_aapcscc void @test_shift8_mask8(i32* nocapture %p) {
; CHECK-V6M-NEXT: str r1, [r0]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i32, i32* %p, align 4
+ %0 = load i32, ptr %p, align 4
%shl = lshr i32 %0, 8
%and = and i32 %shl, 255
- store i32 %and, i32* %p, align 4
+ store i32 %and, ptr %p, align 4
ret void
}
-define arm_aapcscc void @test_shift8_mask7(i32* nocapture %p) {
+define arm_aapcscc void @test_shift8_mask7(ptr nocapture %p) {
; CHECK-COMMON-LABEL: test_shift8_mask7:
; CHECK-COMMON: @ %bb.0: @ %entry
; CHECK-COMMON-NEXT: ldr r1, [r0]
@@ -551,14 +551,14 @@ define arm_aapcscc void @test_shift8_mask7(i32* nocapture %p) {
; CHECK-V6M-NEXT: str r1, [r0]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i32, i32* %p, align 4
+ %0 = load i32, ptr %p, align 4
%shl = lshr i32 %0, 8
%and = and i32 %shl, 127
- store i32 %and, i32* %p, align 4
+ store i32 %and, ptr %p, align 4
ret void
}
-define arm_aapcscc void @test_shift9_mask8(i32* nocapture %p) {
+define arm_aapcscc void @test_shift9_mask8(ptr nocapture %p) {
; CHECK-COMMON-LABEL: test_shift9_mask8:
; CHECK-COMMON: @ %bb.0: @ %entry
; CHECK-COMMON-NEXT: ldr r1, [r0]
@@ -581,14 +581,14 @@ define arm_aapcscc void @test_shift9_mask8(i32* nocapture %p) {
; CHECK-V6M-NEXT: str r1, [r0]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i32, i32* %p, align 4
+ %0 = load i32, ptr %p, align 4
%shl = lshr i32 %0, 9
%and = and i32 %shl, 255
- store i32 %and, i32* %p, align 4
+ store i32 %and, ptr %p, align 4
ret void
}
-define arm_aapcscc void @test_shift8_mask16(i32* nocapture %p) {
+define arm_aapcscc void @test_shift8_mask16(ptr nocapture %p) {
; CHECK-ARM-LABEL: test_shift8_mask16:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: ldrh r1, [r0, #1]
@@ -622,14 +622,14 @@ define arm_aapcscc void @test_shift8_mask16(i32* nocapture %p) {
; CHECK-V6M-NEXT: str r1, [r0]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i32, i32* %p, align 4
+ %0 = load i32, ptr %p, align 4
%shl = lshr i32 %0, 8
%and = and i32 %shl, 65535
- store i32 %and, i32* %p, align 4
+ store i32 %and, ptr %p, align 4
ret void
}
-define arm_aapcscc void @test_shift15_mask16(i32* nocapture %p) {
+define arm_aapcscc void @test_shift15_mask16(ptr nocapture %p) {
; CHECK-COMMON-LABEL: test_shift15_mask16:
; CHECK-COMMON: @ %bb.0: @ %entry
; CHECK-COMMON-NEXT: ldr r1, [r0]
@@ -652,14 +652,14 @@ define arm_aapcscc void @test_shift15_mask16(i32* nocapture %p) {
; CHECK-V6M-NEXT: str r1, [r0]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i32, i32* %p, align 4
+ %0 = load i32, ptr %p, align 4
%shl = lshr i32 %0, 15
%and = and i32 %shl, 65535
- store i32 %and, i32* %p, align 4
+ store i32 %and, ptr %p, align 4
ret void
}
-define arm_aapcscc void @test_shift16_mask15(i32* nocapture %p) {
+define arm_aapcscc void @test_shift16_mask15(ptr nocapture %p) {
; CHECK-COMMON-LABEL: test_shift16_mask15:
; CHECK-COMMON: @ %bb.0: @ %entry
; CHECK-COMMON-NEXT: ldrh r1, [r0, #2]
@@ -686,14 +686,14 @@ define arm_aapcscc void @test_shift16_mask15(i32* nocapture %p) {
; CHECK-V6M-NEXT: .LCPI21_0:
; CHECK-V6M-NEXT: .long 32767 @ 0x7fff
entry:
- %0 = load i32, i32* %p, align 4
+ %0 = load i32, ptr %p, align 4
%shl = lshr i32 %0, 16
%and = and i32 %shl, 32767
- store i32 %and, i32* %p, align 4
+ store i32 %and, ptr %p, align 4
ret void
}
-define arm_aapcscc void @test_shift8_mask24(i32* nocapture %p) {
+define arm_aapcscc void @test_shift8_mask24(ptr nocapture %p) {
; CHECK-ARM-LABEL: test_shift8_mask24:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: ldr r1, [r0]
@@ -729,14 +729,14 @@ define arm_aapcscc void @test_shift8_mask24(i32* nocapture %p) {
; CHECK-V6M-NEXT: str r1, [r0]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i32, i32* %p, align 4
+ %0 = load i32, ptr %p, align 4
%shl = lshr i32 %0, 8
%and = and i32 %shl, 16777215
- store i32 %and, i32* %p, align 4
+ store i32 %and, ptr %p, align 4
ret void
}
-define arm_aapcscc void @test_shift24_mask16(i32* nocapture %p) {
+define arm_aapcscc void @test_shift24_mask16(ptr nocapture %p) {
; CHECK-COMMON-LABEL: test_shift24_mask16:
; CHECK-COMMON: @ %bb.0: @ %entry
; CHECK-COMMON-NEXT: ldrb r1, [r0, #3]
@@ -755,14 +755,14 @@ define arm_aapcscc void @test_shift24_mask16(i32* nocapture %p) {
; CHECK-V6M-NEXT: str r1, [r0]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i32, i32* %p, align 4
+ %0 = load i32, ptr %p, align 4
%shl = lshr i32 %0, 24
%and = and i32 %shl, 65535
- store i32 %and, i32* %p, align 4
+ store i32 %and, ptr %p, align 4
ret void
}
-define arm_aapcscc void @test_sext_shift8_mask8(i16* %p, i32* %q) {
+define arm_aapcscc void @test_sext_shift8_mask8(ptr %p, ptr %q) {
; CHECK-COMMON-LABEL: test_sext_shift8_mask8:
; CHECK-COMMON: @ %bb.0: @ %entry
; CHECK-COMMON-NEXT: ldrb r0, [r0, #1]
@@ -781,15 +781,15 @@ define arm_aapcscc void @test_sext_shift8_mask8(i16* %p, i32* %q) {
; CHECK-V6M-NEXT: str r0, [r1]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i16, i16* %p, align 4
+ %0 = load i16, ptr %p, align 4
%1 = sext i16 %0 to i32
%shl = lshr i32 %1, 8
%and = and i32 %shl, 255
- store i32 %and, i32* %q, align 4
+ store i32 %and, ptr %q, align 4
ret void
}
-define arm_aapcscc void @test_sext_shift8_mask16(i16* %p, i32* %q) {
+define arm_aapcscc void @test_sext_shift8_mask16(ptr %p, ptr %q) {
; CHECK-ARM-LABEL: test_sext_shift8_mask16:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: ldrsh r0, [r0]
@@ -827,15 +827,15 @@ define arm_aapcscc void @test_sext_shift8_mask16(i16* %p, i32* %q) {
; CHECK-V6M-NEXT: str r0, [r1]
; CHECK-V6M-NEXT: bx lr
entry:
- %0 = load i16, i16* %p, align 4
+ %0 = load i16, ptr %p, align 4
%1 = sext i16 %0 to i32
%shl = lshr i32 %1, 8
%and = and i32 %shl, 65535
- store i32 %and, i32* %q, align 4
+ store i32 %and, ptr %q, align 4
ret void
}
-define i1 @trunc_i64_mask_srl(i32 zeroext %AttrArgNo, i64* %ptr) {
+define i1 @trunc_i64_mask_srl(i32 zeroext %AttrArgNo, ptr %ptr) {
; CHECK-ARM-LABEL: trunc_i64_mask_srl:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: ldrh r2, [r1, #4]
@@ -886,7 +886,7 @@ define i1 @trunc_i64_mask_srl(i32 zeroext %AttrArgNo, i64* %ptr) {
; CHECK-V6M-NEXT: movs r0, #1
; CHECK-V6M-NEXT: bx lr
entry:
- %bf.load.i = load i64, i64* %ptr, align 8
+ %bf.load.i = load i64, ptr %ptr, align 8
%bf.lshr.i = lshr i64 %bf.load.i, 32
%0 = trunc i64 %bf.lshr.i to i32
%bf.cast.i = and i32 %0, 65535
diff --git a/llvm/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll b/llvm/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll
index 17393e44b12e4..4161845a98a6e 100644
--- a/llvm/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll
+++ b/llvm/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll
@@ -4,65 +4,64 @@
%struct.__CFString = type opaque
-declare void @bar(%struct.__CFString*, %struct.__CFString*)
+declare void @bar(ptr, ptr)
-define noalias i8* @foo(i8* nocapture %inRefURL) noreturn ssp personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
+define noalias ptr @foo(ptr nocapture %inRefURL) noreturn ssp personality ptr @__gxx_personality_sj0 {
entry:
- %call = tail call %struct.__CFString* @bar3()
- %call2 = invoke i8* @bar2()
+ %call = tail call ptr @bar3()
+ %call2 = invoke ptr @bar2()
to label %for.cond unwind label %lpad
for.cond: ; preds = %entry, %for.cond
- invoke void @bar(%struct.__CFString* undef, %struct.__CFString* null)
+ invoke void @bar(ptr undef, ptr null)
to label %for.cond unwind label %lpad5
lpad: ; preds = %entry
- %0 = landingpad { i8*, i32 }
+ %0 = landingpad { ptr, i32 }
cleanup
- %1 = extractvalue { i8*, i32 } %0, 0
- %2 = extractvalue { i8*, i32 } %0, 1
+ %1 = extractvalue { ptr, i32 } %0, 0
+ %2 = extractvalue { ptr, i32 } %0, 1
br label %ehcleanup
lpad5: ; preds = %for.cond
- %3 = landingpad { i8*, i32 }
+ %3 = landingpad { ptr, i32 }
cleanup
- %4 = extractvalue { i8*, i32 } %3, 0
- %5 = extractvalue { i8*, i32 } %3, 1
- invoke void @release(i8* %call2)
+ %4 = extractvalue { ptr, i32 } %3, 0
+ %5 = extractvalue { ptr, i32 } %3, 1
+ invoke void @release(ptr %call2)
to label %ehcleanup unwind label %terminate.lpad.i.i16
terminate.lpad.i.i16: ; preds = %lpad5
- %6 = landingpad { i8*, i32 }
- catch i8* null
+ %6 = landingpad { ptr, i32 }
+ catch ptr null
tail call void @terminatev() noreturn nounwind
unreachable
ehcleanup: ; preds = %lpad5, %lpad
- %exn.slot.0 = phi i8* [ %1, %lpad ], [ %4, %lpad5 ]
+ %exn.slot.0 = phi ptr [ %1, %lpad ], [ %4, %lpad5 ]
%ehselector.slot.0 = phi i32 [ %2, %lpad ], [ %5, %lpad5 ]
- %7 = bitcast %struct.__CFString* %call to i8*
- invoke void @release(i8* %7)
+ invoke void @release(ptr %call)
to label %_ZN5SmartIPK10__CFStringED1Ev.exit unwind label %terminate.lpad.i.i
terminate.lpad.i.i: ; preds = %ehcleanup
- %8 = landingpad { i8*, i32 }
- catch i8* null
+ %7 = landingpad { ptr, i32 }
+ catch ptr null
tail call void @terminatev() noreturn nounwind
unreachable
_ZN5SmartIPK10__CFStringED1Ev.exit: ; preds = %ehcleanup
- %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn.slot.0, 0
- %lpad.val12 = insertvalue { i8*, i32 } %lpad.val, i32 %ehselector.slot.0, 1
- resume { i8*, i32 } %lpad.val12
+ %lpad.val = insertvalue { ptr, i32 } undef, ptr %exn.slot.0, 0
+ %lpad.val12 = insertvalue { ptr, i32 } %lpad.val, i32 %ehselector.slot.0, 1
+ resume { ptr, i32 } %lpad.val12
}
-declare %struct.__CFString* @bar3()
+declare ptr @bar3()
-declare i8* @bar2()
+declare ptr @bar2()
declare i32 @__gxx_personality_sj0(...)
-declare void @release(i8*)
+declare void @release(ptr)
declare void @terminatev()
@@ -86,108 +85,108 @@ declare void @terminatev()
%"class.std::__1::__libcpp_compressed_pair_imp" = type { %"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__rep" }
%"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__rep" = type { %union.anon }
%union.anon = type { %"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__long" }
-%"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__long" = type { i32, i32, i8* }
+%"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__long" = type { i32, i32, ptr }
@.str = private unnamed_addr constant [12 x i8] c"some_string\00", align 1
-define void @_Z4foo1c(i8 signext %a) personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
+define void @_Z4foo1c(i8 signext %a) personality ptr @__gxx_personality_sj0 {
entry:
%s1 = alloca %"class.std::__1::basic_string", align 4
- call void @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEPKcm(%"class.std::__1::basic_string"* %s1, i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), i32 11)
- %call.i.i.i14.i.i = invoke noalias i8* @_Znwm(i32 1024)
+ call void @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEPKcm(ptr %s1, ptr @.str, i32 11)
+ %call.i.i.i14.i.i = invoke noalias ptr @_Znwm(i32 1024)
to label %do.body.i.i.i unwind label %lpad.body
do.body.i.i.i: ; preds = %entry, %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i
%lsr.iv = phi i32 [ %lsr.iv.next, %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i ], [ -1024, %entry ]
- %0 = phi i8* [ %incdec.ptr.i.i.i, %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i ], [ %call.i.i.i14.i.i, %entry ]
- %new.isnull.i.i.i.i = icmp eq i8* %0, null
+ %0 = phi ptr [ %incdec.ptr.i.i.i, %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i ], [ %call.i.i.i14.i.i, %entry ]
+ %new.isnull.i.i.i.i = icmp eq ptr %0, null
br i1 %new.isnull.i.i.i.i, label %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i, label %new.notnull.i.i.i.i
new.notnull.i.i.i.i: ; preds = %do.body.i.i.i
- store i8 %a, i8* %0, align 1
+ store i8 %a, ptr %0, align 1
br label %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i
_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i: ; preds = %new.notnull.i.i.i.i, %do.body.i.i.i
- %1 = phi i8* [ null, %do.body.i.i.i ], [ %0, %new.notnull.i.i.i.i ]
- %incdec.ptr.i.i.i = getelementptr inbounds i8, i8* %1, i32 1
+ %1 = phi ptr [ null, %do.body.i.i.i ], [ %0, %new.notnull.i.i.i.i ]
+ %incdec.ptr.i.i.i = getelementptr inbounds i8, ptr %1, i32 1
%lsr.iv.next = add i32 %lsr.iv, 1
%cmp.i16.i.i = icmp eq i32 %lsr.iv.next, 0
br i1 %cmp.i16.i.i, label %invoke.cont, label %do.body.i.i.i
invoke.cont: ; preds = %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i
- invoke void @_Z4foo2Pci(i8* %call.i.i.i14.i.i, i32 1024)
+ invoke void @_Z4foo2Pci(ptr %call.i.i.i14.i.i, i32 1024)
to label %invoke.cont5 unwind label %lpad2
invoke.cont5: ; preds = %invoke.cont
- %cmp.i.i.i15 = icmp eq i8* %call.i.i.i14.i.i, null
+ %cmp.i.i.i15 = icmp eq ptr %call.i.i.i14.i.i, null
br i1 %cmp.i.i.i15, label %invoke.cont6, label %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i19
_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i19: ; preds = %invoke.cont5
- call void @_ZdlPv(i8* %call.i.i.i14.i.i)
+ call void @_ZdlPv(ptr %call.i.i.i14.i.i)
br label %invoke.cont6
invoke.cont6: ; preds = %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i19, %invoke.cont5
- %call10 = call %"class.std::__1::basic_string"* @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(%"class.std::__1::basic_string"* %s1)
+ %call10 = call ptr @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(ptr %s1)
ret void
lpad.body: ; preds = %entry
- %2 = landingpad { i8*, i32 }
+ %2 = landingpad { ptr, i32 }
cleanup
- %3 = extractvalue { i8*, i32 } %2, 0
- %4 = extractvalue { i8*, i32 } %2, 1
+ %3 = extractvalue { ptr, i32 } %2, 0
+ %4 = extractvalue { ptr, i32 } %2, 1
br label %ehcleanup
lpad2: ; preds = %invoke.cont
- %5 = landingpad { i8*, i32 }
+ %5 = landingpad { ptr, i32 }
cleanup
- %6 = extractvalue { i8*, i32 } %5, 0
- %7 = extractvalue { i8*, i32 } %5, 1
- %cmp.i.i.i21 = icmp eq i8* %call.i.i.i14.i.i, null
+ %6 = extractvalue { ptr, i32 } %5, 0
+ %7 = extractvalue { ptr, i32 } %5, 1
+ %cmp.i.i.i21 = icmp eq ptr %call.i.i.i14.i.i, null
br i1 %cmp.i.i.i21, label %ehcleanup, label %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26
_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26: ; preds = %lpad2
- call void @_ZdlPv(i8* %call.i.i.i14.i.i)
+ call void @_ZdlPv(ptr %call.i.i.i14.i.i)
br label %ehcleanup
ehcleanup: ; preds = %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26, %lpad2, %lpad.body
- %exn.slot.0 = phi i8* [ %3, %lpad.body ], [ %6, %lpad2 ], [ %6, %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26 ]
+ %exn.slot.0 = phi ptr [ %3, %lpad.body ], [ %6, %lpad2 ], [ %6, %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26 ]
%ehselector.slot.0 = phi i32 [ %4, %lpad.body ], [ %7, %lpad2 ], [ %7, %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26 ]
- %call12 = invoke %"class.std::__1::basic_string"* @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(%"class.std::__1::basic_string"* %s1)
+ %call12 = invoke ptr @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(ptr %s1)
to label %eh.resume unwind label %terminate.lpad
eh.resume: ; preds = %ehcleanup
- %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn.slot.0, 0
- %lpad.val13 = insertvalue { i8*, i32 } %lpad.val, i32 %ehselector.slot.0, 1
- resume { i8*, i32 } %lpad.val13
+ %lpad.val = insertvalue { ptr, i32 } undef, ptr %exn.slot.0, 0
+ %lpad.val13 = insertvalue { ptr, i32 } %lpad.val, i32 %ehselector.slot.0, 1
+ resume { ptr, i32 } %lpad.val13
terminate.lpad: ; preds = %ehcleanup
- %8 = landingpad { i8*, i32 }
- catch i8* null
- %9 = extractvalue { i8*, i32 } %8, 0
- call void @__clang_call_terminate(i8* %9)
+ %8 = landingpad { ptr, i32 }
+ catch ptr null
+ %9 = extractvalue { ptr, i32 } %8, 0
+ call void @__clang_call_terminate(ptr %9)
unreachable
}
-declare void @_Z4foo2Pci(i8*, i32)
+declare void @_Z4foo2Pci(ptr, i32)
-define linkonce_odr hidden void @__clang_call_terminate(i8*) {
- %2 = tail call i8* @__cxa_begin_catch(i8* %0)
+define linkonce_odr hidden void @__clang_call_terminate(ptr) {
+ %2 = tail call ptr @__cxa_begin_catch(ptr %0)
tail call void @_ZSt9terminatev()
unreachable
}
-declare i8* @__cxa_begin_catch(i8*)
+declare ptr @__cxa_begin_catch(ptr)
declare void @_ZSt9terminatev()
-declare %"class.std::__1::basic_string"* @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(%"class.std::__1::basic_string"* returned)
-declare void @_ZdlPv(i8*) #3
-declare noalias i8* @_Znwm(i32)
-declare void @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEPKcm(%"class.std::__1::basic_string"*, i8*, i32)
-declare void @_Unwind_SjLj_Register({ i8*, i32, [4 x i32], i8*, i8*, [5 x i8*] }*)
-declare void @_Unwind_SjLj_Unregister({ i8*, i32, [4 x i32], i8*, i8*, [5 x i8*] }*)
-declare i8* @llvm.frameaddress(i32)
-declare i8* @llvm.stacksave()
-declare void @llvm.stackrestore(i8*)
-declare i32 @llvm.eh.sjlj.setjmp(i8*)
-declare i8* @llvm.eh.sjlj.lsda()
+declare ptr @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(ptr returned)
+declare void @_ZdlPv(ptr) #3
+declare noalias ptr @_Znwm(i32)
+declare void @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEPKcm(ptr, ptr, i32)
+declare void @_Unwind_SjLj_Register(ptr)
+declare void @_Unwind_SjLj_Unregister(ptr)
+declare ptr @llvm.frameaddress(i32)
+declare ptr @llvm.stacksave()
+declare void @llvm.stackrestore(ptr)
+declare i32 @llvm.eh.sjlj.setjmp(ptr)
+declare ptr @llvm.eh.sjlj.lsda()
declare void @llvm.eh.sjlj.callsite(i32)
-declare void @llvm.eh.sjlj.functioncontext(i8*)
+declare void @llvm.eh.sjlj.functioncontext(ptr)
diff --git a/llvm/test/CodeGen/ARM/sjljeh-swifterror.ll b/llvm/test/CodeGen/ARM/sjljeh-swifterror.ll
index 2018e08a44f3e..1436a73c7c262 100644
--- a/llvm/test/CodeGen/ARM/sjljeh-swifterror.ll
+++ b/llvm/test/CodeGen/ARM/sjljeh-swifterror.ll
@@ -11,42 +11,42 @@ declare i32 @__objc_personality_v0(...)
; Make sure we don't leave a select on a swifterror argument.
; CHECK-LABEL: @test
; CHECK-NOT: select true, %0
-define swiftcc void @test(%swift.error** swifterror) local_unnamed_addr personality i32 (...)* @__objc_personality_v0 {
+define swiftcc void @test(ptr swifterror) local_unnamed_addr personality ptr @__objc_personality_v0 {
entry:
- %call28.i = invoke i32 bitcast (void ()* @objc_msgSend to i32 (i8*, i8*)*)(i8* undef, i8* undef)
+ %call28.i = invoke i32 @objc_msgSend(ptr undef, ptr undef)
to label %invoke.cont.i unwind label %lpad.i
invoke.cont.i:
unreachable
lpad.i:
- %1 = landingpad { i8*, i32 }
+ %1 = landingpad { ptr, i32 }
cleanup
- resume { i8*, i32 } undef
+ resume { ptr, i32 } undef
}
-%struct._objc_typeinfo = type { i8**, i8*, i64* }
+%struct._objc_typeinfo = type { ptr, ptr, ptr }
@"OBJC_EHTYPE_$_NSException" = external global %struct._objc_typeinfo
; Make sure this does not crash.
; CHECK-LABEL: @swift_error_bug
-; CHECK: store %swift.error* null, %swift.error** %0
+; CHECK: store ptr null, ptr %0
-define hidden swiftcc void @swift_error_bug(%swift.error** swifterror, void (i8*)** %fun, i1 %b) local_unnamed_addr #0 personality i32 (...)* @__objc_personality_v0 {
- %2 = load void (i8*)*, void (i8*)** %fun, align 4
- invoke void %2(i8* null) #1
+define hidden swiftcc void @swift_error_bug(ptr swifterror, ptr %fun, i1 %b) local_unnamed_addr #0 personality ptr @__objc_personality_v0 {
+ %2 = load ptr, ptr %fun, align 4
+ invoke void %2(ptr null) #1
to label %tryBlock.exit unwind label %3, !clang.arc.no_objc_arc_exceptions !1
; <label>:3:
- %4 = landingpad { i8*, i32 }
- catch %struct._objc_typeinfo* @"OBJC_EHTYPE_$_NSException"
+ %4 = landingpad { ptr, i32 }
+ catch ptr @"OBJC_EHTYPE_$_NSException"
br label %tryBlock.exit
tryBlock.exit:
br i1 %b, label %5, label %_T0ypMa.exit.i.i
_T0ypMa.exit.i.i:
- store %swift.error* null, %swift.error** %0, align 4
+ store ptr null, ptr %0, align 4
ret void
; <label>:5:
diff --git a/llvm/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll b/llvm/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll
index a2b986effba98..d691a7891e97c 100644
--- a/llvm/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll
+++ b/llvm/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll
@@ -13,7 +13,7 @@
; __Unwind_SjLj_Register and actual @bar invocation
-define i8* @foo(i8 %a, {} %c) personality i8* bitcast (i32 (...)* @baz to i8*) {
+define ptr @foo(i8 %a, {} %c) personality ptr @baz {
entry:
; CHECK: bl __Unwind_SjLj_Register
; CHECK-NEXT: {{[A-Z][a-zA-Z0-9]*}}:
@@ -34,9 +34,9 @@ unreachable:
unreachable
handler:
- %tmp = landingpad { i8*, i32 }
+ %tmp = landingpad { ptr, i32 }
cleanup
- resume { i8*, i32 } undef
+ resume { ptr, i32 } undef
}
declare void @bar()
diff --git a/llvm/test/CodeGen/ARM/smul.ll b/llvm/test/CodeGen/ARM/smul.ll
index 7091f8d191483..ef59bd09373f5 100644
--- a/llvm/test/CodeGen/ARM/smul.ll
+++ b/llvm/test/CodeGen/ARM/smul.ll
@@ -286,7 +286,7 @@ define i32 @f22(i32 %a) {
; CHECK-NOT: sxth
; CHECK: smulwb r0, r0, r1
; DISABLED-NOT: smulwb
- %b = load i16, i16* @global_b, align 2
+ %b = load i16, ptr @global_b, align 2
%sext = sext i16 %b to i64
%conv = sext i32 %a to i64
%mul = mul nsw i64 %sext, %conv
@@ -300,7 +300,7 @@ define i32 @f23(i32 %a, i32 %c) {
; CHECK-NOT: sxth
; CHECK: smlawb r0, r0, r2, r1
; DISABLED-NOT: smlawb
- %b = load i16, i16* @global_b, align 2
+ %b = load i16, ptr @global_b, align 2
%sext = sext i16 %b to i64
%conv = sext i32 %a to i64
%mul = mul nsw i64 %sext, %conv
@@ -313,64 +313,64 @@ define i32 @f23(i32 %a, i32 %c) {
; CHECK-LABEL: f24
; CHECK-NOT: sxth
; CHECK: smulbb
-define i32 @f24(i16* %a, i32* %b, i32* %c) {
- %ld.0 = load i16, i16* %a, align 2
- %ld.1 = load i32, i32* %b, align 4
+define i32 @f24(ptr %a, ptr %b, ptr %c) {
+ %ld.0 = load i16, ptr %a, align 2
+ %ld.1 = load i32, ptr %b, align 4
%conv.0 = sext i16 %ld.0 to i32
%shift = shl i32 %ld.1, 16
%conv.1 = ashr i32 %shift, 16
%mul.0 = mul i32 %conv.0, %conv.1
- store i32 %ld.1, i32* %c
+ store i32 %ld.1, ptr %c
ret i32 %mul.0
}
; CHECK-LABEL: f25
; CHECK-NOT: sxth
; CHECK: smulbb
-define i32 @f25(i16* %a, i32 %b, i32* %c) {
- %ld.0 = load i16, i16* %a, align 2
+define i32 @f25(ptr %a, i32 %b, ptr %c) {
+ %ld.0 = load i16, ptr %a, align 2
%conv.0 = sext i16 %ld.0 to i32
%shift = shl i32 %b, 16
%conv.1 = ashr i32 %shift, 16
%mul.0 = mul i32 %conv.0, %conv.1
- store i32 %b, i32* %c
+ store i32 %b, ptr %c
ret i32 %mul.0
}
; CHECK-LABEL: f25_b
; CHECK-NOT: sxth
; CHECK: smulbb
-define i32 @f25_b(i16* %a, i32 %b, i32* %c) {
- %ld.0 = load i16, i16* %a, align 2
+define i32 @f25_b(ptr %a, i32 %b, ptr %c) {
+ %ld.0 = load i16, ptr %a, align 2
%conv.0 = sext i16 %ld.0 to i32
%shift = shl i32 %b, 16
%conv.1 = ashr i32 %shift, 16
%mul.0 = mul i32 %conv.1, %conv.0
- store i32 %b, i32* %c
+ store i32 %b, ptr %c
ret i32 %mul.0
}
; CHECK-LABEL: f26
; CHECK-NOT: sxth
; CHECK: {{smulbt | smultb}}
-define i32 @f26(i16* %a, i32 %b, i32* %c) {
- %ld.0 = load i16, i16* %a, align 2
+define i32 @f26(ptr %a, i32 %b, ptr %c) {
+ %ld.0 = load i16, ptr %a, align 2
%conv.0 = sext i16 %ld.0 to i32
%conv.1 = ashr i32 %b, 16
%mul.0 = mul i32 %conv.0, %conv.1
- store i32 %b, i32* %c
+ store i32 %b, ptr %c
ret i32 %mul.0
}
; CHECK-LABEL: f26_b
; CHECK-NOT: sxth
; CHECK: {{smulbt | smultb}}
-define i32 @f26_b(i16* %a, i32 %b, i32* %c) {
- %ld.0 = load i16, i16* %a, align 2
+define i32 @f26_b(ptr %a, i32 %b, ptr %c) {
+ %ld.0 = load i16, ptr %a, align 2
%conv.0 = sext i16 %ld.0 to i32
%conv.1 = ashr i32 %b, 16
%mul.0 = mul i32 %conv.1, %conv.0
- store i32 %b, i32* %c
+ store i32 %b, ptr %c
ret i32 %mul.0
}
@@ -378,9 +378,9 @@ define i32 @f26_b(i16* %a, i32 %b, i32* %c) {
; CHECK-NOT: sxth
; CHECK: smulbb
; CHECK: {{smlabt | smlatb}}
-define i32 @f27(i16* %a, i32* %b) {
- %ld.0 = load i16, i16* %a, align 2
- %ld.1 = load i32, i32* %b, align 4
+define i32 @f27(ptr %a, ptr %b) {
+ %ld.0 = load i16, ptr %a, align 2
+ %ld.1 = load i32, ptr %b, align 4
%conv.0 = sext i16 %ld.0 to i32
%shift = shl i32 %ld.1, 16
%conv.1 = ashr i32 %shift, 16
@@ -395,9 +395,9 @@ define i32 @f27(i16* %a, i32* %b) {
; CHECK-NOT: sxth
; CHECK: smulbb
; CHECK: {{smlabt | smlatb}}
-define i32 @f27_b(i16* %a, i32* %b) {
- %ld.0 = load i16, i16* %a, align 2
- %ld.1 = load i32, i32* %b, align 4
+define i32 @f27_b(ptr %a, ptr %b) {
+ %ld.0 = load i16, ptr %a, align 2
+ %ld.1 = load i32, ptr %b, align 4
%conv.0 = sext i16 %ld.0 to i32
%shift = shl i32 %ld.1, 16
%conv.1 = ashr i32 %shift, 16
diff --git a/llvm/test/CodeGen/ARM/softfp-constant-comparison.ll b/llvm/test/CodeGen/ARM/softfp-constant-comparison.ll
index e076e75e8066d..76df93b286c33 100644
--- a/llvm/test/CodeGen/ARM/softfp-constant-comparison.ll
+++ b/llvm/test/CodeGen/ARM/softfp-constant-comparison.ll
@@ -17,7 +17,7 @@ define hidden void @fn1() nounwind #0 {
; CHECK-NEXT: .LBB0_2: @ %land.end
; CHECK-NEXT: bx lr
entry:
- %0 = load i32, i32* @a, align 4
+ %0 = load i32, ptr @a, align 4
%conv = sitofp i32 %0 to double
%mul = fmul nnan ninf nsz double 0.000000e+00, %conv
%tobool = fcmp nnan ninf nsz une double %mul, 0.000000e+00
diff --git a/llvm/test/CodeGen/ARM/space-directive.ll b/llvm/test/CodeGen/ARM/space-directive.ll
index 24f0d0aadf602..e2d174c4cd7bf 100644
--- a/llvm/test/CodeGen/ARM/space-directive.ll
+++ b/llvm/test/CodeGen/ARM/space-directive.ll
@@ -10,8 +10,8 @@ define i32 @test_space() minsize {
; CHECK: [[PAST_CP]]:
; CHECK: .zero 10000
- %addr = inttoptr i32 12345678 to i32*
- %val = load i32, i32* %addr
+ %addr = inttoptr i32 12345678 to ptr
+ %val = load i32, ptr %addr
call i32 @llvm.arm.space(i32 10000, i32 undef)
ret i32 %val
}
diff --git a/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll b/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
index dfae40effe96c..282ffb2c41cd3 100644
--- a/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
+++ b/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
@@ -53,16 +53,16 @@ if.else: ; preds = %entry
; CHECK-NEXT: .Lfunc_end
}
- at __const.indirect_branch.ptr = private unnamed_addr constant [2 x i8*] [i8* blockaddress(@indirect_branch, %return), i8* blockaddress(@indirect_branch, %l2)], align 8
+ at __const.indirect_branch.ptr = private unnamed_addr constant [2 x ptr] [ptr blockaddress(@indirect_branch, %return), ptr blockaddress(@indirect_branch, %l2)], align 8
; Function Attrs: norecurse nounwind readnone
define dso_local i32 @indirect_branch(i32 %a, i32 %b, i32 %i) {
; CHECK-LABEL: indirect_branch:
entry:
%idxprom = sext i32 %i to i64
- %arrayidx = getelementptr inbounds [2 x i8*], [2 x i8*]* @__const.indirect_branch.ptr, i64 0, i64 %idxprom
- %0 = load i8*, i8** %arrayidx, align 8
- indirectbr i8* %0, [label %return, label %l2]
+ %arrayidx = getelementptr inbounds [2 x ptr], ptr @__const.indirect_branch.ptr, i64 0, i64 %idxprom
+ %0 = load ptr, ptr %arrayidx, align 8
+ indirectbr ptr %0, [label %return, label %l2]
; ARM: bx r0
; THUMB: mov pc, r0
; ISBDSB-NEXT: dsb sy
@@ -163,15 +163,13 @@ sw.epilog: ; preds = %sw.bb5, %entry
}
define dso_local i32 @indirect_call(
-i32 (...)* nocapture %f1, i32 (...)* nocapture %f2) {
+ptr nocapture %f1, ptr nocapture %f2) {
entry:
; CHECK-LABEL: indirect_call:
- %callee.knr.cast = bitcast i32 (...)* %f1 to i32 ()*
- %call = tail call i32 %callee.knr.cast()
+ %call = tail call i32 %f1()
; HARDENARM: bl {{__llvm_slsblr_thunk_arm_r[0-9]+$}}
; HARDENTHUMB: bl {{__llvm_slsblr_thunk_thumb_r[0-9]+$}}
- %callee.knr.cast1 = bitcast i32 (...)* %f2 to i32 ()*
- %call2 = tail call i32 %callee.knr.cast1()
+ %call2 = tail call i32 %f2()
; HARDENARM: bl {{__llvm_slsblr_thunk_arm_r[0-9]+$}}
; HARDENTHUMB: bl {{__llvm_slsblr_thunk_thumb_r[0-9]+$}}
%add = add nsw i32 %call2, %call
@@ -180,16 +178,16 @@ entry:
}
; verify calling through a function pointer.
- at a = dso_local local_unnamed_addr global i32 (...)* null, align 8
+ at a = dso_local local_unnamed_addr global ptr null, align 8
@b = dso_local local_unnamed_addr global i32 0, align 4
define dso_local void @indirect_call_global() local_unnamed_addr {
; CHECK-LABEL: indirect_call_global:
entry:
- %0 = load i32 ()*, i32 ()** bitcast (i32 (...)** @a to i32 ()**), align 8
+ %0 = load ptr, ptr @a, align 8
%call = tail call i32 %0() nounwind
; HARDENARM: bl {{__llvm_slsblr_thunk_arm_r[0-9]+$}}
; HARDENTHUMB: bl {{__llvm_slsblr_thunk_thumb_r[0-9]+$}}
- store i32 %call, i32* @b, align 4
+ store i32 %call, ptr @b, align 4
ret void
; CHECK: .Lfunc_end
}
@@ -199,12 +197,12 @@ entry:
; (a) a linker is allowed to clobber r12 on calls, and
; (b) the hardening transformation isn't correct if lr is the register holding
; the address of the function called.
-define i32 @check_r12(i32 ()** %fp) {
+define i32 @check_r12(ptr %fp) {
entry:
; CHECK-LABEL: check_r12:
- %f = load i32 ()*, i32 ()** %fp, align 4
+ %f = load ptr, ptr %fp, align 4
; Force f to be moved into r12
- %r12_f = tail call i32 ()* asm "add $0, $1, #0", "={r12},{r12}"(i32 ()* %f) nounwind
+ %r12_f = tail call ptr asm "add $0, $1, #0", "={r12},{r12}"(ptr %f) nounwind
%call = call i32 %r12_f()
; NOHARDENARM: blx r12
; NOHARDENTHUMB: blx r12
@@ -213,12 +211,12 @@ entry:
; CHECK: .Lfunc_end
}
-define i32 @check_lr(i32 ()** %fp) {
+define i32 @check_lr(ptr %fp) {
entry:
; CHECK-LABEL: check_lr:
- %f = load i32 ()*, i32 ()** %fp, align 4
+ %f = load ptr, ptr %fp, align 4
; Force f to be moved into lr
- %lr_f = tail call i32 ()* asm "add $0, $1, #0", "={lr},{lr}"(i32 ()* %f) nounwind
+ %lr_f = tail call ptr asm "add $0, $1, #0", "={lr},{lr}"(ptr %f) nounwind
%call = call i32 %lr_f()
; NOHARDENARM: blx lr
; NOHARDENTHUMB: blx lr
@@ -229,11 +227,10 @@ entry:
; Verify that even when sls-harden-blr is enabled, "blx r12" is still an
; instruction that is accepted by the inline assembler
-define void @verify_inline_asm_blx_r12(void ()* %g) {
+define void @verify_inline_asm_blx_r12(ptr %g) {
entry:
; CHECK-LABEL: verify_inline_asm_blx_r12:
- %0 = bitcast void ()* %g to i8*
- tail call void asm sideeffect "blx $0", "{r12}"(i8* %0) nounwind
+ tail call void asm sideeffect "blx $0", "{r12}"(ptr %g) nounwind
; CHECK: blx r12
ret void
; CHECK: {{bx lr$}}
diff --git a/llvm/test/CodeGen/ARM/spill-q.ll b/llvm/test/CodeGen/ARM/spill-q.ll
index bec145dd80b4d..b4f36cd3d99e6 100644
--- a/llvm/test/CodeGen/ARM/spill-q.ll
+++ b/llvm/test/CodeGen/ARM/spill-q.ll
@@ -4,12 +4,12 @@
%bar = type { float, float, float }
%baz = type { i32, [16 x %bar], [16 x float], [16 x i32], i8 }
%foo = type { <4 x float> }
-%quux = type { i32 (...)**, %baz*, i32 }
+%quux = type { ptr, ptr, i32 }
%quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo }
-declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8*, i32) nounwind readonly
+declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr, i32) nounwind readonly
-define void @aaa(%quuz* %this, i8* %block) {
+define void @aaa(ptr %this, ptr %block) {
; CHECK-LABEL: aaa:
; CHECK: bfc {{.*}}, #0, #4
; CHECK: vst1.64 {{.*}}sp:128
@@ -17,33 +17,32 @@ define void @aaa(%quuz* %this, i8* %block) {
entry:
%aligned_vec = alloca <4 x float>, align 16
%"alloca point" = bitcast i32 0 to i32
- %vecptr = bitcast <4 x float>* %aligned_vec to i8*
- %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* %vecptr, i32 1) nounwind ; <<4 x float>> [#uses=1]
- store float 6.300000e+01, float* undef, align 4
- %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
- store float 0.000000e+00, float* undef, align 4
- %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
- %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
- store float 0.000000e+00, float* undef, align 4
- %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
- store float 0.000000e+00, float* undef, align 4
- %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
- store float 0.000000e+00, float* undef, align 4
- %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
- store float 0.000000e+00, float* undef, align 4
- %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
- store float 0.000000e+00, float* undef, align 4
- %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
- store float 0.000000e+00, float* undef, align 4
- %ld9 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
- store float 0.000000e+00, float* undef, align 4
- %ld10 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
- store float 0.000000e+00, float* undef, align 4
- %ld11 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
- store float 0.000000e+00, float* undef, align 4
- %ld12 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
- store float 0.000000e+00, float* undef, align 4
- %val173 = load <4 x float>, <4 x float>* undef ; <<4 x float>> [#uses=1]
+ %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr %aligned_vec, i32 1) nounwind ; <<4 x float>> [#uses=1]
+ store float 6.300000e+01, ptr undef, align 4
+ %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
+ store float 0.000000e+00, ptr undef, align 4
+ %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
+ %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
+ store float 0.000000e+00, ptr undef, align 4
+ %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
+ store float 0.000000e+00, ptr undef, align 4
+ %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
+ store float 0.000000e+00, ptr undef, align 4
+ %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
+ store float 0.000000e+00, ptr undef, align 4
+ %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
+ store float 0.000000e+00, ptr undef, align 4
+ %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
+ store float 0.000000e+00, ptr undef, align 4
+ %ld9 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
+ store float 0.000000e+00, ptr undef, align 4
+ %ld10 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
+ store float 0.000000e+00, ptr undef, align 4
+ %ld11 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
+ store float 0.000000e+00, ptr undef, align 4
+ %ld12 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1) nounwind
+ store float 0.000000e+00, ptr undef, align 4
+ %val173 = load <4 x float>, ptr undef ; <<4 x float>> [#uses=1]
br label %bb4
bb4: ; preds = %bb193, %entry
diff --git a/llvm/test/CodeGen/ARM/splitkit.ll b/llvm/test/CodeGen/ARM/splitkit.ll
index 870c6952311c3..d9db9f7cf4151 100644
--- a/llvm/test/CodeGen/ARM/splitkit.ll
+++ b/llvm/test/CodeGen/ARM/splitkit.ll
@@ -10,17 +10,17 @@ target triple = "thumbv7-apple-ios"
%struct.barney = type { %struct.snork.1 }
%struct.snork.1 = type { %struct.wobble.2 }
%struct.wobble.2 = type { %struct.blam }
-%struct.blam = type { i32, i32, i8* }
+%struct.blam = type { i32, i32, ptr }
%struct.ham.3 = type { %struct.pluto }
-%struct.pluto = type { %struct.zot*, %struct.snork.5, %struct.wibble }
-%struct.zot = type { %struct.blam.4* }
-%struct.blam.4 = type <{ %struct.zot, %struct.blam.4*, %struct.zot*, i8, [3 x i8] }>
+%struct.pluto = type { ptr, %struct.snork.5, %struct.wibble }
+%struct.zot = type { ptr }
+%struct.blam.4 = type <{ %struct.zot, ptr, ptr, i8, [3 x i8] }>
%struct.snork.5 = type { %struct.quux }
%struct.quux = type { %struct.zot }
%struct.wibble = type { %struct.widget }
%struct.widget = type { i32 }
%struct.bar = type { %struct.spam }
-%struct.spam = type { %struct.zot*, %struct.wobble, %struct.zot.7 }
+%struct.spam = type { ptr, %struct.wobble, %struct.zot.7 }
%struct.wobble = type { %struct.wibble.6 }
%struct.wibble.6 = type { %struct.zot }
%struct.zot.7 = type { %struct.ham.8 }
@@ -90,31 +90,31 @@ target triple = "thumbv7-apple-ios"
@global.56 = external global %struct.bar
@global.57 = external global i8
-declare %struct.ham* @bar(%struct.ham* returned)
+declare ptr @bar(ptr returned)
-declare i32 @__cxa_atexit(void (i8*)*, i8*, i8*)
+declare i32 @__cxa_atexit(ptr, ptr, ptr)
-declare %struct.ham* @wobble(%struct.ham* returned, %struct.ham* )
+declare ptr @wobble(ptr returned, ptr )
declare i32 @quux(...)
-declare i8* @_Znwm(i32)
+declare ptr @_Znwm(i32)
-declare i32 @wobble.58(%struct.pluto*, [1 x i32], %struct.ham* , %struct.hoge* )
+declare i32 @wobble.58(ptr, [1 x i32], ptr , ptr )
-declare i32 @widget(%struct.spam*, [1 x i32], %struct.ham* , %struct.wombat* )
+declare i32 @widget(ptr, [1 x i32], ptr , ptr )
; Just check we didn't crash and did output something...
; CHECK-LABEL: func:
; CHECK: trap
-define internal void @func() section "__TEXT,__StaticInit,regular,pure_instructions" personality i32 (...)* @quux {
- %tmp = tail call i32 @__cxa_atexit(void (i8*)* bitcast (%struct.ham* (%struct.ham*)* @bar to void (i8*)*), i8* bitcast (%struct.ham* @global.3 to i8*), i8* @global) #0
- %tmp2 = invoke %struct.ham* @wobble(%struct.ham* undef, %struct.ham* @global.9)
+define internal void @func() section "__TEXT,__StaticInit,regular,pure_instructions" personality ptr @quux {
+ %tmp = tail call i32 @__cxa_atexit(ptr @bar, ptr @global.3, ptr @global) #0
+ %tmp2 = invoke ptr @wobble(ptr undef, ptr @global.9)
to label %bb14 unwind label %bbunwind
bb14:
- %tmp15 = getelementptr i8, i8* undef, i32 12
- store i8 0, i8* %tmp15
+ %tmp15 = getelementptr i8, ptr undef, i32 12
+ store i8 0, ptr %tmp15
%tmp16 = icmp eq i8 undef, 0
br i1 %tmp16, label %bb28, label %bb18
@@ -122,23 +122,23 @@ bb18:
br i1 undef, label %bb21, label %bb29
bb21:
- %tmp22 = call i8* @_Znwm(i32 16)
- store i32 17, i32* getelementptr (%struct.ham, %struct.ham* @global.10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
- %tmp23 = call i8* @_Znwm(i32 32)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 undef, i8* align 1 getelementptr ([27 x i8], [27 x i8]* @global.2, i32 0, i32 0), i32 26, i1 false)
- store i32 33, i32* getelementptr (%struct.ham, %struct.ham* @global.11, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
- store i32 23, i32* getelementptr (%struct.ham, %struct.ham* @global.11, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 undef, i8* align 1 getelementptr ([24 x i8], [24 x i8]* @global.7, i32 0, i32 0), i32 23, i1 false)
- %tmp24 = call i32 @__cxa_atexit(void (i8*)* bitcast (%struct.ham* (%struct.ham*)* @bar to void (i8*)*), i8* bitcast (%struct.ham* @global.11 to i8*), i8* @global) #0
- store i32 49, i32* getelementptr (%struct.ham, %struct.ham* @global.12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
- store i32 37, i32* getelementptr (%struct.ham, %struct.ham* @global.13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
- call void @llvm.memset.p0i8.i32(i8* align 4 bitcast (%struct.ham* @global.14 to i8*), i8 0, i32 12, i1 false)
- %tmp25 = call i8* @_Znwm(i32 48)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %tmp25, i8* align 1 getelementptr ([40 x i8], [40 x i8]* @global.6, i32 0, i32 0), i32 39, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 undef, i8* align 1 getelementptr ([47 x i8], [47 x i8]* @global.4, i32 0, i32 0), i32 46, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 undef, i8* align 1 getelementptr ([61 x i8], [61 x i8]* @global.5, i32 0, i32 0), i32 60, i1 false)
- %tmp26 = call i8* @_Znwm(i32 48)
- store i32 65, i32* getelementptr (%struct.ham, %struct.ham* @global.15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+ %tmp22 = call ptr @_Znwm(i32 16)
+ store i32 17, ptr @global.10
+ %tmp23 = call ptr @_Znwm(i32 32)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 undef, ptr align 1 @global.2, i32 26, i1 false)
+ store i32 33, ptr @global.11
+ store i32 23, ptr getelementptr (%struct.ham, ptr @global.11, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 undef, ptr align 1 @global.7, i32 23, i1 false)
+ %tmp24 = call i32 @__cxa_atexit(ptr @bar, ptr @global.11, ptr @global) #0
+ store i32 49, ptr @global.12
+ store i32 37, ptr getelementptr (%struct.ham, ptr @global.13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
+ call void @llvm.memset.p0.i32(ptr align 4 @global.14, i8 0, i32 12, i1 false)
+ %tmp25 = call ptr @_Znwm(i32 48)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 %tmp25, ptr align 1 @global.6, i32 39, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 undef, ptr align 1 @global.4, i32 46, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 undef, ptr align 1 @global.5, i32 60, i1 false)
+ %tmp26 = call ptr @_Znwm(i32 48)
+ store i32 65, ptr @global.15
%tmp27 = icmp eq i8 undef, 0
br i1 %tmp27, label %bb30, label %bb33
@@ -155,91 +155,91 @@ bb30:
br i1 %tmp31, label %bb32, label %bb30
bb32:
- store i8 1, i8* @global.57
+ store i8 1, ptr @global.57
br label %bb33
bb33:
- %tmp34 = call i8* @_Znwm(i32 32)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 undef, i8* align 1 getelementptr ([20 x i8], [20 x i8]* @global.1, i32 0, i32 0), i32 19, i1 false)
- store i32 17, i32* getelementptr (%struct.ham, %struct.ham* @global.16, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
- store i32 65, i32* getelementptr (%struct.ham, %struct.ham* @global.17, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 undef, i8* align 1 getelementptr ([35 x i8], [35 x i8]* @global.18, i32 0, i32 0), i32 34, i1 false)
- store i32 65, i32* getelementptr (%struct.ham, %struct.ham* @global.19, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 undef, i8* align 1 getelementptr ([53 x i8], [53 x i8]* @global.20, i32 0, i32 0), i32 52, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 undef, i8* align 1 getelementptr ([20 x i8], [20 x i8]* @global.8, i32 0, i32 0), i32 19, i1 false)
- store i32 37, i32* getelementptr (%struct.ham, %struct.ham* @global.21, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
- %tmp35 = call i8* @_Znwm(i32 32)
- store i8 16, i8* bitcast (%struct.ham* @global.22 to i8*)
- %tmp36 = call i8* @_Znwm(i32 32)
- store i32 31, i32* getelementptr (%struct.ham, %struct.ham* @global.23, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %tmp36, i8* align 1 getelementptr ([32 x i8], [32 x i8]* @global.24, i32 0, i32 0), i32 31, i1 false)
- %tmp37 = getelementptr i8, i8* %tmp36, i32 31
- store i8 0, i8* %tmp37
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 undef, i8* align 1 getelementptr ([47 x i8], [47 x i8]* @global.26, i32 0, i32 0), i32 46, i1 false)
- %tmp38 = call i32 @__cxa_atexit(void (i8*)* bitcast (%struct.ham* (%struct.ham*)* @bar to void (i8*)*), i8* bitcast (%struct.ham* @global.25 to i8*), i8* @global) #0
- %tmp39 = call i8* @_Znwm(i32 48)
- store i32 44, i32* getelementptr (%struct.ham, %struct.ham* @global.27, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %tmp39, i8* align 1 getelementptr ([45 x i8], [45 x i8]* @global.28, i32 0, i32 0), i32 44, i1 false)
- %tmp40 = getelementptr i8, i8* %tmp39, i32 44
- store i8 0, i8* %tmp40
- call void @llvm.memset.p0i8.i32(i8* align 4 bitcast (%struct.ham* @global.29 to i8*), i8 0, i32 12, i1 false)
- %tmp41 = call i8* @_Znwm(i32 32)
- store i32 23, i32* getelementptr (%struct.ham, %struct.ham* @global.30, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %tmp41, i8* align 1 getelementptr ([24 x i8], [24 x i8]* @global.31, i32 0, i32 0), i32 23, i1 false)
- %tmp42 = getelementptr i8, i8* %tmp41, i32 23
- store i8 0, i8* %tmp42
- call void @llvm.memset.p0i8.i32(i8* align 4 bitcast (%struct.ham* @global.32 to i8*), i8 0, i32 12, i1 false)
- store i8 16, i8* bitcast (%struct.ham* @global.32 to i8*)
- %tmp43 = call i32 @__cxa_atexit(void (i8*)* bitcast (%struct.ham* (%struct.ham*)* @bar to void (i8*)*), i8* bitcast (%struct.ham* @global.33 to i8*), i8* @global) #0
- %tmp44 = call i8* @_Znwm(i32 16)
- call void @llvm.memset.p0i8.i32(i8* align 4 bitcast (%struct.ham* @global.34 to i8*), i8 0, i32 12, i1 false)
- call void @llvm.memset.p0i8.i32(i8* align 4 bitcast (%struct.ham* @global.9 to i8*), i8 0, i32 12, i1 false)
- %tmp45 = call i8* @_Znwm(i32 32)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %tmp45, i8* align 1 getelementptr ([27 x i8], [27 x i8]* @global.36, i32 0, i32 0), i32 26, i1 false)
- call void @llvm.memset.p0i8.i32(i8* align 4 bitcast (%struct.ham* @global.37 to i8*), i8 0, i32 12, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 getelementptr (%struct.snork, %struct.snork* bitcast (%struct.ham* @global.37 to %struct.snork*), i32 0, i32 1, i32 0), i8* align 1 getelementptr ([10 x i8], [10 x i8]* @global.38, i32 0, i32 0), i32 9, i1 false)
- store i32 17, i32* getelementptr (%struct.ham, %struct.ham* @global.39, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
- %tmp46 = call i32 @__cxa_atexit(void (i8*)* bitcast (%struct.ham* (%struct.ham*)* @bar to void (i8*)*), i8* bitcast (%struct.ham* @global.40 to i8*), i8* @global) #0
- %tmp47 = call i8* @_Znwm(i32 32)
- %tmp48 = getelementptr i8, i8* %tmp47, i32 21
- store i8 0, i8* %tmp48
- store i32 33, i32* getelementptr (%struct.ham, %struct.ham* @global.41, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
- store i32 15, i32* getelementptr (%struct.ham, %struct.ham* @global.42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
- %tmp49 = call i32 @__cxa_atexit(void (i8*)* bitcast (%struct.ham* (%struct.ham*)* @bar to void (i8*)*), i8* bitcast (%struct.ham* @global.43 to i8*), i8* @global) #0
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 undef, i8* align 1 getelementptr ([41 x i8], [41 x i8]* @global.44, i32 0, i32 0), i32 40, i1 false)
- %tmp50 = call i32 @__cxa_atexit(void (i8*)* bitcast (%struct.ham* (%struct.ham*)* @bar to void (i8*)*), i8* bitcast (%struct.ham* @global.45 to i8*), i8* @global) #0
- %tmp51 = call i32 @__cxa_atexit(void (i8*)* bitcast (%struct.ham* (%struct.ham*)* @bar to void (i8*)*), i8* bitcast (%struct.ham* @global.46 to i8*), i8* @global) #0
- %tmp52 = call i8* @_Znwm(i32 32)
- store i8* %tmp52, i8** getelementptr (%struct.ham, %struct.ham* @global.47, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 2)
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 undef, i8* align 1 getelementptr ([52 x i8], [52 x i8]* @global.49, i32 0, i32 0), i32 51, i1 false)
- %tmp53 = call i32 @__cxa_atexit(void (i8*)* bitcast (%struct.ham* (%struct.ham*)* @bar to void (i8*)*), i8* bitcast (%struct.ham* @global.48 to i8*), i8* @global) #0
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 undef, i8* align 1 getelementptr ([47 x i8], [47 x i8]* @global.50, i32 0, i32 0), i32 46, i1 false)
- store i32 33, i32* getelementptr (%struct.ham, %struct.ham* @global.51, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
- store i32 37, i32* getelementptr (%struct.ham, %struct.ham* @global.52, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
- %tmp54 = invoke %struct.ham* @wobble(%struct.ham* undef, %struct.ham* @global.54)
+ %tmp34 = call ptr @_Znwm(i32 32)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 undef, ptr align 1 @global.1, i32 19, i1 false)
+ store i32 17, ptr @global.16
+ store i32 65, ptr @global.17
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 undef, ptr align 1 @global.18, i32 34, i1 false)
+ store i32 65, ptr @global.19
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 undef, ptr align 1 @global.20, i32 52, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 undef, ptr align 1 @global.8, i32 19, i1 false)
+ store i32 37, ptr getelementptr (%struct.ham, ptr @global.21, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
+ %tmp35 = call ptr @_Znwm(i32 32)
+ store i8 16, ptr @global.22
+ %tmp36 = call ptr @_Znwm(i32 32)
+ store i32 31, ptr getelementptr (%struct.ham, ptr @global.23, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 %tmp36, ptr align 1 @global.24, i32 31, i1 false)
+ %tmp37 = getelementptr i8, ptr %tmp36, i32 31
+ store i8 0, ptr %tmp37
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 undef, ptr align 1 @global.26, i32 46, i1 false)
+ %tmp38 = call i32 @__cxa_atexit(ptr @bar, ptr @global.25, ptr @global) #0
+ %tmp39 = call ptr @_Znwm(i32 48)
+ store i32 44, ptr getelementptr (%struct.ham, ptr @global.27, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 %tmp39, ptr align 1 @global.28, i32 44, i1 false)
+ %tmp40 = getelementptr i8, ptr %tmp39, i32 44
+ store i8 0, ptr %tmp40
+ call void @llvm.memset.p0.i32(ptr align 4 @global.29, i8 0, i32 12, i1 false)
+ %tmp41 = call ptr @_Znwm(i32 32)
+ store i32 23, ptr getelementptr (%struct.ham, ptr @global.30, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 %tmp41, ptr align 1 @global.31, i32 23, i1 false)
+ %tmp42 = getelementptr i8, ptr %tmp41, i32 23
+ store i8 0, ptr %tmp42
+ call void @llvm.memset.p0.i32(ptr align 4 @global.32, i8 0, i32 12, i1 false)
+ store i8 16, ptr @global.32
+ %tmp43 = call i32 @__cxa_atexit(ptr @bar, ptr @global.33, ptr @global) #0
+ %tmp44 = call ptr @_Znwm(i32 16)
+ call void @llvm.memset.p0.i32(ptr align 4 @global.34, i8 0, i32 12, i1 false)
+ call void @llvm.memset.p0.i32(ptr align 4 @global.9, i8 0, i32 12, i1 false)
+ %tmp45 = call ptr @_Znwm(i32 32)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 %tmp45, ptr align 1 @global.36, i32 26, i1 false)
+ call void @llvm.memset.p0.i32(ptr align 4 @global.37, i8 0, i32 12, i1 false)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 getelementptr (%struct.snork, ptr @global.37, i32 0, i32 1, i32 0), ptr align 1 @global.38, i32 9, i1 false)
+ store i32 17, ptr @global.39
+ %tmp46 = call i32 @__cxa_atexit(ptr @bar, ptr @global.40, ptr @global) #0
+ %tmp47 = call ptr @_Znwm(i32 32)
+ %tmp48 = getelementptr i8, ptr %tmp47, i32 21
+ store i8 0, ptr %tmp48
+ store i32 33, ptr @global.41
+ store i32 15, ptr getelementptr (%struct.ham, ptr @global.42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
+ %tmp49 = call i32 @__cxa_atexit(ptr @bar, ptr @global.43, ptr @global) #0
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 undef, ptr align 1 @global.44, i32 40, i1 false)
+ %tmp50 = call i32 @__cxa_atexit(ptr @bar, ptr @global.45, ptr @global) #0
+ %tmp51 = call i32 @__cxa_atexit(ptr @bar, ptr @global.46, ptr @global) #0
+ %tmp52 = call ptr @_Znwm(i32 32)
+ store ptr %tmp52, ptr getelementptr (%struct.ham, ptr @global.47, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 2)
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 undef, ptr align 1 @global.49, i32 51, i1 false)
+ %tmp53 = call i32 @__cxa_atexit(ptr @bar, ptr @global.48, ptr @global) #0
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 undef, ptr align 1 @global.50, i32 46, i1 false)
+ store i32 33, ptr @global.51
+ store i32 37, ptr getelementptr (%struct.ham, ptr @global.52, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1)
+ %tmp54 = invoke ptr @wobble(ptr undef, ptr @global.54)
to label %bb58 unwind label %bbunwind
bb58:
- %tmp59 = invoke i32 @wobble.58(%struct.pluto* getelementptr (%struct.ham.3, %struct.ham.3* @global.55, i32 0, i32 0), [1 x i32] [i32 ptrtoint (%struct.zot* getelementptr (%struct.ham.3, %struct.ham.3* @global.55, i32 0, i32 0, i32 1, i32 0, i32 0) to i32)], %struct.ham* undef, %struct.hoge* undef)
+ %tmp59 = invoke i32 @wobble.58(ptr @global.55, [1 x i32] [i32 ptrtoint (ptr getelementptr (%struct.ham.3, ptr @global.55, i32 0, i32 0, i32 1, i32 0, i32 0) to i32)], ptr undef, ptr undef)
to label %bb71 unwind label %bbunwind
bb71:
- %tmp72 = invoke i32 @widget(%struct.spam* getelementptr (%struct.bar, %struct.bar* @global.56, i32 0, i32 0), [1 x i32] [i32 ptrtoint (%struct.zot* getelementptr (%struct.bar, %struct.bar* @global.56, i32 0, i32 0, i32 1, i32 0, i32 0) to i32)], %struct.ham* undef, %struct.wombat* undef)
+ %tmp72 = invoke i32 @widget(ptr @global.56, [1 x i32] [i32 ptrtoint (ptr getelementptr (%struct.bar, ptr @global.56, i32 0, i32 0, i32 1, i32 0, i32 0) to i32)], ptr undef, ptr undef)
to label %bb73 unwind label %bbunwind
bb73:
ret void
bbunwind:
- %tmp75 = landingpad { i8*, i32 }
+ %tmp75 = landingpad { ptr, i32 }
cleanup
- resume { i8*, i32 } undef
+ resume { ptr, i32 } undef
}
declare void @llvm.trap()
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* , i8* , i32, i1)
+declare void @llvm.memcpy.p0.p0.i32(ptr , ptr , i32, i1)
-declare void @llvm.memset.p0i8.i32(i8* , i8, i32, i1)
+declare void @llvm.memset.p0.i32(ptr , i8, i32, i1)
attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/ARM/sponentry.ll b/llvm/test/CodeGen/ARM/sponentry.ll
index b98a14591b010..fc3f1e5a1f57d 100644
--- a/llvm/test/CodeGen/ARM/sponentry.ll
+++ b/llvm/test/CodeGen/ARM/sponentry.ll
@@ -3,14 +3,12 @@
; RUN: llc -mtriple=thumbv7-windows-msvc %s -o - | FileCheck %s --check-prefix=NOFP
; RUN: llc -mtriple=thumbv7-windows-msvc -fast-isel %s -o - | FileCheck %s --check-prefix=NOFP
- at env2 = common dso_local global [24 x i64]* null, align 8
+ at env2 = common dso_local global ptr null, align 8
define dso_local void @bar() {
- %1 = call i8* @llvm.sponentry()
- %2 = load [24 x i64]*, [24 x i64]** @env2, align 8
- %3 = getelementptr inbounds [24 x i64], [24 x i64]* %2, i32 0, i32 0
- %4 = bitcast i64* %3 to i8*
- %5 = call i32 @_setjmpex(i8* %4, i8* %1) #2
+ %1 = call ptr @llvm.sponentry()
+ %2 = load ptr, ptr @env2, align 8
+ %3 = call i32 @_setjmpex(ptr %2, ptr %1) #2
ret void
}
@@ -25,17 +23,15 @@ define dso_local void @bar() {
; NOFP: add r1, sp, #8
; NOFP: bl _setjmpex
-define dso_local void @foo([24 x i64]*) {
- %2 = alloca [24 x i64]*, align 8
+define dso_local void @foo(ptr) {
+ %2 = alloca ptr, align 8
%3 = alloca i32, align 4
%4 = alloca [100 x i32], align 4
- store [24 x i64]* %0, [24 x i64]** %2, align 8
- %5 = call i8* @llvm.sponentry()
- %6 = load [24 x i64]*, [24 x i64]** %2, align 8
- %7 = getelementptr inbounds [24 x i64], [24 x i64]* %6, i32 0, i32 0
- %8 = bitcast i64* %7 to i8*
- %9 = call i32 @_setjmpex(i8* %8, i8* %5)
- store i32 %9, i32* %3, align 4
+ store ptr %0, ptr %2, align 8
+ %5 = call ptr @llvm.sponentry()
+ %6 = load ptr, ptr %2, align 8
+ %7 = call i32 @_setjmpex(ptr %6, ptr %5)
+ store i32 %7, ptr %3, align 4
ret void
}
@@ -52,24 +48,19 @@ define dso_local void @foo([24 x i64]*) {
; NOFP: add r1, sp, #424
; NOFP: bl _setjmpex
-define dso_local void @var_args(i8*, ...) {
- %2 = alloca i8*, align 8
- %3 = alloca i8*, align 8
- store i8* %0, i8** %2, align 8
- %4 = bitcast i8** %3 to i8*
- call void @llvm.va_start(i8* %4)
- %5 = load i8*, i8** %3, align 8
- %6 = getelementptr inbounds i8, i8* %5, i64 8
- store i8* %6, i8** %3, align 8
- %7 = bitcast i8* %5 to i32*
- %8 = load i32, i32* %7, align 8
- %9 = bitcast i8** %3 to i8*
- call void @llvm.va_end(i8* %9)
- %10 = call i8* @llvm.sponentry()
- %11 = load [24 x i64]*, [24 x i64]** @env2, align 8
- %12 = getelementptr inbounds [24 x i64], [24 x i64]* %11, i32 0, i32 0
- %13 = bitcast i64* %12 to i8*
- %14 = call i32 @_setjmpex(i8* %13, i8* %10) #3
+define dso_local void @var_args(ptr, ...) {
+ %2 = alloca ptr, align 8
+ %3 = alloca ptr, align 8
+ store ptr %0, ptr %2, align 8
+ call void @llvm.va_start(ptr %3)
+ %4 = load ptr, ptr %3, align 8
+ %5 = getelementptr inbounds i8, ptr %4, i64 8
+ store ptr %5, ptr %3, align 8
+ %6 = load i32, ptr %4, align 8
+ call void @llvm.va_end(ptr %3)
+ %7 = call ptr @llvm.sponentry()
+ %8 = load ptr, ptr @env2, align 8
+ %9 = call i32 @_setjmpex(ptr %8, ptr %7) #3
ret void
}
@@ -88,11 +79,9 @@ define dso_local void @var_args(i8*, ...) {
; NOFP: bl _setjmpex
define dso_local void @manyargs(i64 %x1, i64 %x2, i64 %x3, i64 %x4, i64 %x5, i64 %x6, i64 %x7, i64 %x8, i64 %x9, i64 %x10) {
- %1 = call i8* @llvm.sponentry()
- %2 = load [24 x i64]*, [24 x i64]** @env2, align 8
- %3 = getelementptr inbounds [24 x i64], [24 x i64]* %2, i32 0, i32 0
- %4 = bitcast i64* %3 to i8*
- %5 = call i32 @_setjmpex(i8* %4, i8* %1) #2
+ %1 = call ptr @llvm.sponentry()
+ %2 = load ptr, ptr @env2, align 8
+ %3 = call i32 @_setjmpex(ptr %2, ptr %1) #2
ret void
}
@@ -108,13 +97,13 @@ define dso_local void @manyargs(i64 %x1, i64 %x2, i64 %x3, i64 %x4, i64 %x5, i64
; NOFP: bl _setjmpex
; Function Attrs: nounwind readnone
-declare i8* @llvm.sponentry()
+declare ptr @llvm.sponentry()
; Function Attrs: returns_twice
-declare dso_local i32 @_setjmpex(i8*, i8*)
+declare dso_local i32 @_setjmpex(ptr, ptr)
; Function Attrs: nounwind
-declare void @llvm.va_start(i8*) #1
+declare void @llvm.va_start(ptr) #1
; Function Attrs: nounwind
-declare void @llvm.va_end(i8*) #1
+declare void @llvm.va_end(ptr) #1
diff --git a/llvm/test/CodeGen/ARM/ssat-unroll-loops.ll b/llvm/test/CodeGen/ARM/ssat-unroll-loops.ll
index def54a046bfc0..2755d354a6244 100644
--- a/llvm/test/CodeGen/ARM/ssat-unroll-loops.ll
+++ b/llvm/test/CodeGen/ARM/ssat-unroll-loops.ll
@@ -3,7 +3,7 @@
; Checks SSAT is still generated when loop unrolling is on
-define void @ssat_unroll(i16* %pSrcA, i16* %pSrcB, i16* %pDst, i32 %blockSize) {
+define void @ssat_unroll(ptr %pSrcA, ptr %pSrcB, ptr %pDst, i32 %blockSize) {
; CHECK-LABEL: ssat_unroll:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r11, lr}
@@ -54,11 +54,11 @@ while.body.preheader: ; preds = %entry
br i1 %lcmp.mod.not, label %while.body.prol.loopexit, label %while.body.prol.preheader
while.body.prol.preheader: ; preds = %while.body.preheader
- %incdec.ptr.prol = getelementptr inbounds i16, i16* %pSrcA, i32 1
- %1 = load i16, i16* %pSrcA
+ %incdec.ptr.prol = getelementptr inbounds i16, ptr %pSrcA, i32 1
+ %1 = load i16, ptr %pSrcA
%conv.prol = sext i16 %1 to i32
- %incdec.ptr1.prol = getelementptr inbounds i16, i16* %pSrcB, i32 1
- %2 = load i16, i16* %pSrcB
+ %incdec.ptr1.prol = getelementptr inbounds i16, ptr %pSrcB, i32 1
+ %2 = load i16, ptr %pSrcB
%conv2.prol = sext i16 %2 to i32
%mul.prol = mul nsw i32 %conv2.prol, %conv.prol
%shr.prol = ashr i32 %mul.prol, 14
@@ -67,28 +67,28 @@ while.body.prol.preheader: ; preds = %while.body.preheade
%5 = icmp slt i32 %4, 32767
%spec.select.i.prol = select i1 %5, i32 %4, i32 32767
%conv3.prol = trunc i32 %spec.select.i.prol to i16
- %incdec.ptr4.prol = getelementptr inbounds i16, i16* %pDst, i32 1
- store i16 %conv3.prol, i16* %pDst
+ %incdec.ptr4.prol = getelementptr inbounds i16, ptr %pDst, i32 1
+ store i16 %conv3.prol, ptr %pDst
br label %while.body.prol.loopexit
while.body.prol.loopexit: ; preds = %while.body.prol.preheader, %while.body.preheader
%blkCnt.011.unr = phi i32 [ %blockSize, %while.body.preheader ], [ %0, %while.body.prol.preheader ]
- %pSrcA.addr.010.unr = phi i16* [ %pSrcA, %while.body.preheader ], [ %incdec.ptr.prol, %while.body.prol.preheader ]
- %pDst.addr.09.unr = phi i16* [ %pDst, %while.body.preheader ], [ %incdec.ptr4.prol, %while.body.prol.preheader ]
- %pSrcB.addr.08.unr = phi i16* [ %pSrcB, %while.body.preheader ], [ %incdec.ptr1.prol, %while.body.prol.preheader ]
+ %pSrcA.addr.010.unr = phi ptr [ %pSrcA, %while.body.preheader ], [ %incdec.ptr.prol, %while.body.prol.preheader ]
+ %pDst.addr.09.unr = phi ptr [ %pDst, %while.body.preheader ], [ %incdec.ptr4.prol, %while.body.prol.preheader ]
+ %pSrcB.addr.08.unr = phi ptr [ %pSrcB, %while.body.preheader ], [ %incdec.ptr1.prol, %while.body.prol.preheader ]
%6 = icmp eq i32 %0, 0
br i1 %6, label %while.end, label %while.body
while.body: ; preds = %while.body.prol.loopexit, %while.body
%blkCnt.011 = phi i32 [ %dec.1, %while.body ], [ %blkCnt.011.unr, %while.body.prol.loopexit ]
- %pSrcA.addr.010 = phi i16* [ %incdec.ptr.1, %while.body ], [ %pSrcA.addr.010.unr, %while.body.prol.loopexit ]
- %pDst.addr.09 = phi i16* [ %incdec.ptr4.1, %while.body ], [ %pDst.addr.09.unr, %while.body.prol.loopexit ]
- %pSrcB.addr.08 = phi i16* [ %incdec.ptr1.1, %while.body ], [ %pSrcB.addr.08.unr, %while.body.prol.loopexit ]
- %incdec.ptr = getelementptr inbounds i16, i16* %pSrcA.addr.010, i32 1
- %7 = load i16, i16* %pSrcA.addr.010
+ %pSrcA.addr.010 = phi ptr [ %incdec.ptr.1, %while.body ], [ %pSrcA.addr.010.unr, %while.body.prol.loopexit ]
+ %pDst.addr.09 = phi ptr [ %incdec.ptr4.1, %while.body ], [ %pDst.addr.09.unr, %while.body.prol.loopexit ]
+ %pSrcB.addr.08 = phi ptr [ %incdec.ptr1.1, %while.body ], [ %pSrcB.addr.08.unr, %while.body.prol.loopexit ]
+ %incdec.ptr = getelementptr inbounds i16, ptr %pSrcA.addr.010, i32 1
+ %7 = load i16, ptr %pSrcA.addr.010
%conv = sext i16 %7 to i32
- %incdec.ptr1 = getelementptr inbounds i16, i16* %pSrcB.addr.08, i32 1
- %8 = load i16, i16* %pSrcB.addr.08
+ %incdec.ptr1 = getelementptr inbounds i16, ptr %pSrcB.addr.08, i32 1
+ %8 = load i16, ptr %pSrcB.addr.08
%conv2 = sext i16 %8 to i32
%mul = mul nsw i32 %conv2, %conv
%shr = ashr i32 %mul, 14
@@ -97,13 +97,13 @@ while.body: ; preds = %while.body.prol.loo
%11 = icmp slt i32 %10, 32767
%spec.select.i = select i1 %11, i32 %10, i32 32767
%conv3 = trunc i32 %spec.select.i to i16
- %incdec.ptr4 = getelementptr inbounds i16, i16* %pDst.addr.09, i32 1
- store i16 %conv3, i16* %pDst.addr.09
- %incdec.ptr.1 = getelementptr inbounds i16, i16* %pSrcA.addr.010, i32 2
- %12 = load i16, i16* %incdec.ptr
+ %incdec.ptr4 = getelementptr inbounds i16, ptr %pDst.addr.09, i32 1
+ store i16 %conv3, ptr %pDst.addr.09
+ %incdec.ptr.1 = getelementptr inbounds i16, ptr %pSrcA.addr.010, i32 2
+ %12 = load i16, ptr %incdec.ptr
%conv.1 = sext i16 %12 to i32
- %incdec.ptr1.1 = getelementptr inbounds i16, i16* %pSrcB.addr.08, i32 2
- %13 = load i16, i16* %incdec.ptr1
+ %incdec.ptr1.1 = getelementptr inbounds i16, ptr %pSrcB.addr.08, i32 2
+ %13 = load i16, ptr %incdec.ptr1
%conv2.1 = sext i16 %13 to i32
%mul.1 = mul nsw i32 %conv2.1, %conv.1
%shr.1 = ashr i32 %mul.1, 14
@@ -112,8 +112,8 @@ while.body: ; preds = %while.body.prol.loo
%16 = icmp slt i32 %15, 32767
%spec.select.i.1 = select i1 %16, i32 %15, i32 32767
%conv3.1 = trunc i32 %spec.select.i.1 to i16
- %incdec.ptr4.1 = getelementptr inbounds i16, i16* %pDst.addr.09, i32 2
- store i16 %conv3.1, i16* %incdec.ptr4
+ %incdec.ptr4.1 = getelementptr inbounds i16, ptr %pDst.addr.09, i32 2
+ store i16 %conv3.1, ptr %incdec.ptr4
%dec.1 = add i32 %blkCnt.011, -2
%cmp.not.1 = icmp eq i32 %dec.1, 0
br i1 %cmp.not.1, label %while.end, label %while.body
@@ -122,7 +122,7 @@ while.end: ; preds = %while.body, %while.
ret void
}
-define void @ssat_unroll_minmax(i16* nocapture readonly %pSrcA, i16* nocapture readonly %pSrcB, i16* nocapture writeonly %pDst, i32 %blockSize) {
+define void @ssat_unroll_minmax(ptr nocapture readonly %pSrcA, ptr nocapture readonly %pSrcB, ptr nocapture writeonly %pDst, i32 %blockSize) {
; CHECK-LABEL: ssat_unroll_minmax:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r11, lr}
@@ -173,60 +173,60 @@ while.body.preheader: ; preds = %entry
br i1 %lcmp.mod.not, label %while.body.prol.loopexit, label %while.body.prol.preheader
while.body.prol.preheader: ; preds = %while.body.preheader
- %incdec.ptr.prol = getelementptr inbounds i16, i16* %pSrcA, i64 1
- %1 = load i16, i16* %pSrcA, align 2
+ %incdec.ptr.prol = getelementptr inbounds i16, ptr %pSrcA, i64 1
+ %1 = load i16, ptr %pSrcA, align 2
%conv.prol = sext i16 %1 to i32
- %incdec.ptr1.prol = getelementptr inbounds i16, i16* %pSrcB, i64 1
- %2 = load i16, i16* %pSrcB, align 2
+ %incdec.ptr1.prol = getelementptr inbounds i16, ptr %pSrcB, i64 1
+ %2 = load i16, ptr %pSrcB, align 2
%conv2.prol = sext i16 %2 to i32
%mul.prol = mul nsw i32 %conv2.prol, %conv.prol
%shr.prol = ashr i32 %mul.prol, 14
%3 = call i32 @llvm.smax.i32(i32 %shr.prol, i32 -32768)
%4 = call i32 @llvm.smin.i32(i32 %3, i32 32767)
%conv3.prol = trunc i32 %4 to i16
- %incdec.ptr4.prol = getelementptr inbounds i16, i16* %pDst, i64 1
- store i16 %conv3.prol, i16* %pDst, align 2
+ %incdec.ptr4.prol = getelementptr inbounds i16, ptr %pDst, i64 1
+ store i16 %conv3.prol, ptr %pDst, align 2
br label %while.body.prol.loopexit
while.body.prol.loopexit: ; preds = %while.body.prol.preheader, %while.body.preheader
%blkCnt.011.unr = phi i32 [ %blockSize, %while.body.preheader ], [ %0, %while.body.prol.preheader ]
- %pSrcA.addr.010.unr = phi i16* [ %pSrcA, %while.body.preheader ], [ %incdec.ptr.prol, %while.body.prol.preheader ]
- %pDst.addr.09.unr = phi i16* [ %pDst, %while.body.preheader ], [ %incdec.ptr4.prol, %while.body.prol.preheader ]
- %pSrcB.addr.08.unr = phi i16* [ %pSrcB, %while.body.preheader ], [ %incdec.ptr1.prol, %while.body.prol.preheader ]
+ %pSrcA.addr.010.unr = phi ptr [ %pSrcA, %while.body.preheader ], [ %incdec.ptr.prol, %while.body.prol.preheader ]
+ %pDst.addr.09.unr = phi ptr [ %pDst, %while.body.preheader ], [ %incdec.ptr4.prol, %while.body.prol.preheader ]
+ %pSrcB.addr.08.unr = phi ptr [ %pSrcB, %while.body.preheader ], [ %incdec.ptr1.prol, %while.body.prol.preheader ]
%5 = icmp eq i32 %0, 0
br i1 %5, label %while.end, label %while.body
while.body: ; preds = %while.body.prol.loopexit, %while.body
%blkCnt.011 = phi i32 [ %dec.1, %while.body ], [ %blkCnt.011.unr, %while.body.prol.loopexit ]
- %pSrcA.addr.010 = phi i16* [ %incdec.ptr.1, %while.body ], [ %pSrcA.addr.010.unr, %while.body.prol.loopexit ]
- %pDst.addr.09 = phi i16* [ %incdec.ptr4.1, %while.body ], [ %pDst.addr.09.unr, %while.body.prol.loopexit ]
- %pSrcB.addr.08 = phi i16* [ %incdec.ptr1.1, %while.body ], [ %pSrcB.addr.08.unr, %while.body.prol.loopexit ]
- %incdec.ptr = getelementptr inbounds i16, i16* %pSrcA.addr.010, i64 1
- %6 = load i16, i16* %pSrcA.addr.010, align 2
+ %pSrcA.addr.010 = phi ptr [ %incdec.ptr.1, %while.body ], [ %pSrcA.addr.010.unr, %while.body.prol.loopexit ]
+ %pDst.addr.09 = phi ptr [ %incdec.ptr4.1, %while.body ], [ %pDst.addr.09.unr, %while.body.prol.loopexit ]
+ %pSrcB.addr.08 = phi ptr [ %incdec.ptr1.1, %while.body ], [ %pSrcB.addr.08.unr, %while.body.prol.loopexit ]
+ %incdec.ptr = getelementptr inbounds i16, ptr %pSrcA.addr.010, i64 1
+ %6 = load i16, ptr %pSrcA.addr.010, align 2
%conv = sext i16 %6 to i32
- %incdec.ptr1 = getelementptr inbounds i16, i16* %pSrcB.addr.08, i64 1
- %7 = load i16, i16* %pSrcB.addr.08, align 2
+ %incdec.ptr1 = getelementptr inbounds i16, ptr %pSrcB.addr.08, i64 1
+ %7 = load i16, ptr %pSrcB.addr.08, align 2
%conv2 = sext i16 %7 to i32
%mul = mul nsw i32 %conv2, %conv
%shr = ashr i32 %mul, 14
%8 = call i32 @llvm.smax.i32(i32 %shr, i32 -32768)
%9 = call i32 @llvm.smin.i32(i32 %8, i32 32767)
%conv3 = trunc i32 %9 to i16
- %incdec.ptr4 = getelementptr inbounds i16, i16* %pDst.addr.09, i64 1
- store i16 %conv3, i16* %pDst.addr.09, align 2
- %incdec.ptr.1 = getelementptr inbounds i16, i16* %pSrcA.addr.010, i64 2
- %10 = load i16, i16* %incdec.ptr, align 2
+ %incdec.ptr4 = getelementptr inbounds i16, ptr %pDst.addr.09, i64 1
+ store i16 %conv3, ptr %pDst.addr.09, align 2
+ %incdec.ptr.1 = getelementptr inbounds i16, ptr %pSrcA.addr.010, i64 2
+ %10 = load i16, ptr %incdec.ptr, align 2
%conv.1 = sext i16 %10 to i32
- %incdec.ptr1.1 = getelementptr inbounds i16, i16* %pSrcB.addr.08, i64 2
- %11 = load i16, i16* %incdec.ptr1, align 2
+ %incdec.ptr1.1 = getelementptr inbounds i16, ptr %pSrcB.addr.08, i64 2
+ %11 = load i16, ptr %incdec.ptr1, align 2
%conv2.1 = sext i16 %11 to i32
%mul.1 = mul nsw i32 %conv2.1, %conv.1
%shr.1 = ashr i32 %mul.1, 14
%12 = call i32 @llvm.smax.i32(i32 %shr.1, i32 -32768)
%13 = call i32 @llvm.smin.i32(i32 %12, i32 32767)
%conv3.1 = trunc i32 %13 to i16
- %incdec.ptr4.1 = getelementptr inbounds i16, i16* %pDst.addr.09, i64 2
- store i16 %conv3.1, i16* %incdec.ptr4, align 2
+ %incdec.ptr4.1 = getelementptr inbounds i16, ptr %pDst.addr.09, i64 2
+ store i16 %conv3.1, ptr %incdec.ptr4, align 2
%dec.1 = add i32 %blkCnt.011, -2
%cmp.not.1 = icmp eq i32 %dec.1, 0
br i1 %cmp.not.1, label %while.end, label %while.body
diff --git a/llvm/test/CodeGen/ARM/ssat.ll b/llvm/test/CodeGen/ARM/ssat.ll
index f792a38987af5..ed777f2b1882b 100644
--- a/llvm/test/CodeGen/ARM/ssat.ll
+++ b/llvm/test/CodeGen/ARM/ssat.ll
@@ -536,7 +536,7 @@ entry:
ret i32 %saturateUp
}
-define void @extended(i32 %xx, i16 signext %y, i8* nocapture %z) {
+define void @extended(i32 %xx, i16 signext %y, ptr nocapture %z) {
; V4T-LABEL: extended:
; V4T: @ %bb.0: @ %entry
; V4T-NEXT: add r0, r1, r0, lsr #16
@@ -571,7 +571,7 @@ entry:
%cmp.i11 = icmp sgt i16 %cond.i, -128
%cond.i12 = select i1 %cmp.i11, i16 %cond.i, i16 -128
%conv5 = trunc i16 %cond.i12 to i8
- store i8 %conv5, i8* %z, align 1
+ store i8 %conv5, ptr %z, align 1
ret void
}
diff --git a/llvm/test/CodeGen/ARM/ssp-data-layout.ll b/llvm/test/CodeGen/ARM/ssp-data-layout.ll
index ccae951d5c6cf..9dd62a936c4c8 100644
--- a/llvm/test/CodeGen/ARM/ssp-data-layout.ll
+++ b/llvm/test/CodeGen/ARM/ssp-data-layout.ll
@@ -96,70 +96,48 @@ entry:
%c = alloca %struct.struct_large_nonchar, align 8
%d = alloca %struct.struct_small_nonchar, align 2
%call = call i32 @get_scalar1()
- store i32 %call, i32* %x, align 4
+ store i32 %call, ptr %x, align 4
call void @end_scalar1()
%call1 = call i32 @get_scalar2()
- store i32 %call1, i32* %y, align 4
+ store i32 %call1, ptr %y, align 4
call void @end_scalar2()
%call2 = call i32 @get_scalar3()
- store i32 %call2, i32* %z, align 4
+ store i32 %call2, ptr %z, align 4
call void @end_scalar3()
%call3 = call i32 @get_addrof()
- store i32 %call3, i32* %ptr, align 4
+ store i32 %call3, ptr %ptr, align 4
call void @end_addrof()
%call4 = call signext i16 @get_small_nonchar()
- %arrayidx = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i64 0
- store i16 %call4, i16* %arrayidx, align 2
+ store i16 %call4, ptr %small2, align 2
call void @end_small_nonchar()
%call5 = call i32 @get_large_nonchar()
- %arrayidx6 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i64 0
- store i32 %call5, i32* %arrayidx6, align 4
+ store i32 %call5, ptr %large2, align 4
call void @end_large_nonchar()
%call7 = call signext i8 @get_small_char()
- %arrayidx8 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i64 0
- store i8 %call7, i8* %arrayidx8, align 1
+ store i8 %call7, ptr %small, align 1
call void @end_small_char()
%call9 = call signext i8 @get_large_char()
- %arrayidx10 = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i64 0
- store i8 %call9, i8* %arrayidx10, align 1
+ store i8 %call9, ptr %large, align 1
call void @end_large_char()
%call11 = call signext i8 @get_struct_large_char()
- %foo = getelementptr inbounds %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
- %arrayidx12 = getelementptr inbounds [8 x i8], [8 x i8]* %foo, i32 0, i64 0
- store i8 %call11, i8* %arrayidx12, align 1
+ store i8 %call11, ptr %a, align 1
call void @end_struct_large_char()
%call13 = call signext i8 @get_struct_small_char()
- %foo14 = getelementptr inbounds %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
- %arrayidx15 = getelementptr inbounds [2 x i8], [2 x i8]* %foo14, i32 0, i64 0
- store i8 %call13, i8* %arrayidx15, align 1
+ store i8 %call13, ptr %b, align 1
call void @end_struct_small_char()
%call16 = call i32 @get_struct_large_nonchar()
- %foo17 = getelementptr inbounds %struct.struct_large_nonchar, %struct.struct_large_nonchar* %c, i32 0, i32 0
- %arrayidx18 = getelementptr inbounds [8 x i32], [8 x i32]* %foo17, i32 0, i64 0
- store i32 %call16, i32* %arrayidx18, align 4
+ store i32 %call16, ptr %c, align 4
call void @end_struct_large_nonchar()
%call19 = call signext i16 @get_struct_small_nonchar()
- %foo20 = getelementptr inbounds %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
- %arrayidx21 = getelementptr inbounds [2 x i16], [2 x i16]* %foo20, i32 0, i64 0
- store i16 %call19, i16* %arrayidx21, align 2
+ store i16 %call19, ptr %d, align 2
call void @end_struct_small_nonchar()
- %arraydecay = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i32 0
- %arraydecay22 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i32 0
- %arraydecay23 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i32 0
- %arraydecay24 = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i32 0
- %0 = load i32, i32* %x, align 4
- %1 = load i32, i32* %y, align 4
- %2 = load i32, i32* %z, align 4
- %coerce.dive = getelementptr %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
- %3 = bitcast [8 x i8]* %coerce.dive to i64*
- %4 = load i64, i64* %3, align 1
- %coerce.dive25 = getelementptr %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
- %5 = bitcast [2 x i8]* %coerce.dive25 to i16*
- %6 = load i16, i16* %5, align 1
- %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
- %7 = bitcast [2 x i16]* %coerce.dive26 to i32*
- %8 = load i32, i32* %7, align 1
- call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
+ %0 = load i32, ptr %x, align 4
+ %1 = load i32, ptr %y, align 4
+ %2 = load i32, ptr %z, align 4
+ %3 = load i64, ptr %a, align 1
+ %4 = load i16, ptr %b, align 1
+ %5 = load i32, ptr %d, align 1
+ call void @takes_all(i64 %3, i16 %4, ptr byval(%struct.struct_large_nonchar) align 4 %c, i32 %5, ptr %large, ptr %small, ptr %large2, ptr %small2, ptr %ptr, i32 %0, i32 %1, i32 %2)
ret void
}
@@ -241,70 +219,48 @@ entry:
%c = alloca %struct.struct_large_nonchar, align 8
%d = alloca %struct.struct_small_nonchar, align 2
%call = call i32 @get_scalar1()
- store i32 %call, i32* %x, align 4
+ store i32 %call, ptr %x, align 4
call void @end_scalar1()
%call1 = call i32 @get_scalar2()
- store i32 %call1, i32* %y, align 4
+ store i32 %call1, ptr %y, align 4
call void @end_scalar2()
%call2 = call i32 @get_scalar3()
- store i32 %call2, i32* %z, align 4
+ store i32 %call2, ptr %z, align 4
call void @end_scalar3()
%call3 = call i32 @get_addrof()
- store i32 %call3, i32* %ptr, align 4
+ store i32 %call3, ptr %ptr, align 4
call void @end_addrof()
%call4 = call signext i16 @get_small_nonchar()
- %arrayidx = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i64 0
- store i16 %call4, i16* %arrayidx, align 2
+ store i16 %call4, ptr %small2, align 2
call void @end_small_nonchar()
%call5 = call i32 @get_large_nonchar()
- %arrayidx6 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i64 0
- store i32 %call5, i32* %arrayidx6, align 4
+ store i32 %call5, ptr %large2, align 4
call void @end_large_nonchar()
%call7 = call signext i8 @get_small_char()
- %arrayidx8 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i64 0
- store i8 %call7, i8* %arrayidx8, align 1
+ store i8 %call7, ptr %small, align 1
call void @end_small_char()
%call9 = call signext i8 @get_large_char()
- %arrayidx10 = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i64 0
- store i8 %call9, i8* %arrayidx10, align 1
+ store i8 %call9, ptr %large, align 1
call void @end_large_char()
%call11 = call signext i8 @get_struct_large_char()
- %foo = getelementptr inbounds %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
- %arrayidx12 = getelementptr inbounds [8 x i8], [8 x i8]* %foo, i32 0, i64 0
- store i8 %call11, i8* %arrayidx12, align 1
+ store i8 %call11, ptr %a, align 1
call void @end_struct_large_char()
%call13 = call signext i8 @get_struct_small_char()
- %foo14 = getelementptr inbounds %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
- %arrayidx15 = getelementptr inbounds [2 x i8], [2 x i8]* %foo14, i32 0, i64 0
- store i8 %call13, i8* %arrayidx15, align 1
+ store i8 %call13, ptr %b, align 1
call void @end_struct_small_char()
%call16 = call i32 @get_struct_large_nonchar()
- %foo17 = getelementptr inbounds %struct.struct_large_nonchar, %struct.struct_large_nonchar* %c, i32 0, i32 0
- %arrayidx18 = getelementptr inbounds [8 x i32], [8 x i32]* %foo17, i32 0, i64 0
- store i32 %call16, i32* %arrayidx18, align 4
+ store i32 %call16, ptr %c, align 4
call void @end_struct_large_nonchar()
%call19 = call signext i16 @get_struct_small_nonchar()
- %foo20 = getelementptr inbounds %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
- %arrayidx21 = getelementptr inbounds [2 x i16], [2 x i16]* %foo20, i32 0, i64 0
- store i16 %call19, i16* %arrayidx21, align 2
+ store i16 %call19, ptr %d, align 2
call void @end_struct_small_nonchar()
- %arraydecay = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i32 0
- %arraydecay22 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i32 0
- %arraydecay23 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i32 0
- %arraydecay24 = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i32 0
- %0 = load i32, i32* %x, align 4
- %1 = load i32, i32* %y, align 4
- %2 = load i32, i32* %z, align 4
- %coerce.dive = getelementptr %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
- %3 = bitcast [8 x i8]* %coerce.dive to i64*
- %4 = load i64, i64* %3, align 1
- %coerce.dive25 = getelementptr %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
- %5 = bitcast [2 x i8]* %coerce.dive25 to i16*
- %6 = load i16, i16* %5, align 1
- %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
- %7 = bitcast [2 x i16]* %coerce.dive26 to i32*
- %8 = load i32, i32* %7, align 1
- call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
+ %0 = load i32, ptr %x, align 4
+ %1 = load i32, ptr %y, align 4
+ %2 = load i32, ptr %z, align 4
+ %3 = load i64, ptr %a, align 1
+ %4 = load i16, ptr %b, align 1
+ %5 = load i32, ptr %d, align 1
+ call void @takes_all(i64 %3, i16 %4, ptr byval(%struct.struct_large_nonchar) align 4 %c, i32 %5, ptr %large, ptr %small, ptr %large2, ptr %small2, ptr %ptr, i32 %0, i32 %1, i32 %2)
ret void
}
@@ -374,70 +330,48 @@ entry:
%c = alloca %struct.struct_large_nonchar, align 8
%d = alloca %struct.struct_small_nonchar, align 2
%call = call i32 @get_scalar1()
- store i32 %call, i32* %x, align 4
+ store i32 %call, ptr %x, align 4
call void @end_scalar1()
%call1 = call i32 @get_scalar2()
- store i32 %call1, i32* %y, align 4
+ store i32 %call1, ptr %y, align 4
call void @end_scalar2()
%call2 = call i32 @get_scalar3()
- store i32 %call2, i32* %z, align 4
+ store i32 %call2, ptr %z, align 4
call void @end_scalar3()
%call3 = call i32 @get_addrof()
- store i32 %call3, i32* %ptr, align 4
+ store i32 %call3, ptr %ptr, align 4
call void @end_addrof()
%call4 = call signext i16 @get_small_nonchar()
- %arrayidx = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i64 0
- store i16 %call4, i16* %arrayidx, align 2
+ store i16 %call4, ptr %small2, align 2
call void @end_small_nonchar()
%call5 = call i32 @get_large_nonchar()
- %arrayidx6 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i64 0
- store i32 %call5, i32* %arrayidx6, align 4
+ store i32 %call5, ptr %large2, align 4
call void @end_large_nonchar()
%call7 = call signext i8 @get_small_char()
- %arrayidx8 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i64 0
- store i8 %call7, i8* %arrayidx8, align 1
+ store i8 %call7, ptr %small, align 1
call void @end_small_char()
%call9 = call signext i8 @get_large_char()
- %arrayidx10 = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i64 0
- store i8 %call9, i8* %arrayidx10, align 1
+ store i8 %call9, ptr %large, align 1
call void @end_large_char()
%call11 = call signext i8 @get_struct_large_char()
- %foo = getelementptr inbounds %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
- %arrayidx12 = getelementptr inbounds [8 x i8], [8 x i8]* %foo, i32 0, i64 0
- store i8 %call11, i8* %arrayidx12, align 1
+ store i8 %call11, ptr %a, align 1
call void @end_struct_large_char()
%call13 = call signext i8 @get_struct_small_char()
- %foo14 = getelementptr inbounds %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
- %arrayidx15 = getelementptr inbounds [2 x i8], [2 x i8]* %foo14, i32 0, i64 0
- store i8 %call13, i8* %arrayidx15, align 1
+ store i8 %call13, ptr %b, align 1
call void @end_struct_small_char()
%call16 = call i32 @get_struct_large_nonchar()
- %foo17 = getelementptr inbounds %struct.struct_large_nonchar, %struct.struct_large_nonchar* %c, i32 0, i32 0
- %arrayidx18 = getelementptr inbounds [8 x i32], [8 x i32]* %foo17, i32 0, i64 0
- store i32 %call16, i32* %arrayidx18, align 4
+ store i32 %call16, ptr %c, align 4
call void @end_struct_large_nonchar()
%call19 = call signext i16 @get_struct_small_nonchar()
- %foo20 = getelementptr inbounds %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
- %arrayidx21 = getelementptr inbounds [2 x i16], [2 x i16]* %foo20, i32 0, i64 0
- store i16 %call19, i16* %arrayidx21, align 2
+ store i16 %call19, ptr %d, align 2
call void @end_struct_small_nonchar()
- %arraydecay = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i32 0
- %arraydecay22 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i32 0
- %arraydecay23 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i32 0
- %arraydecay24 = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i32 0
- %0 = load i32, i32* %x, align 4
- %1 = load i32, i32* %y, align 4
- %2 = load i32, i32* %z, align 4
- %coerce.dive = getelementptr %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0
- %3 = bitcast [8 x i8]* %coerce.dive to i64*
- %4 = load i64, i64* %3, align 1
- %coerce.dive25 = getelementptr %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0
- %5 = bitcast [2 x i8]* %coerce.dive25 to i16*
- %6 = load i16, i16* %5, align 1
- %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0
- %7 = bitcast [2 x i16]* %coerce.dive26 to i32*
- %8 = load i32, i32* %7, align 1
- call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2)
+ %0 = load i32, ptr %x, align 4
+ %1 = load i32, ptr %y, align 4
+ %2 = load i32, ptr %z, align 4
+ %3 = load i64, ptr %a, align 1
+ %4 = load i16, ptr %b, align 1
+ %5 = load i32, ptr %d, align 1
+ call void @takes_all(i64 %3, i16 %4, ptr byval(%struct.struct_large_nonchar) align 4 %c, i32 %5, ptr %large, ptr %small, ptr %large2, ptr %small2, ptr %ptr, i32 %0, i32 %1, i32 %2)
ret void
}
@@ -457,26 +391,16 @@ entry:
%d1 = alloca %struct.struct_large_nonchar, align 8
%d2 = alloca %struct.struct_small_nonchar, align 2
%call = call signext i8 @get_struct_small_char()
- %foo = getelementptr inbounds %struct.struct_small_char, %struct.struct_small_char* %a, i32 0, i32 0
- %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* %foo, i32 0, i64 0
- store i8 %call, i8* %arrayidx, align 1
+ store i8 %call, ptr %a, align 1
call void @end_struct_small_char()
%call1 = call signext i8 @get_struct_large_char2()
- %foo2 = getelementptr inbounds %struct.struct_large_char2, %struct.struct_large_char2* %b, i32 0, i32 1
- %arrayidx3 = getelementptr inbounds [8 x i8], [8 x i8]* %foo2, i32 0, i64 0
- store i8 %call1, i8* %arrayidx3, align 1
+ %foo2 = getelementptr inbounds %struct.struct_large_char2, ptr %b, i32 0, i32 1
+ store i8 %call1, ptr %foo2, align 1
call void @end_struct_large_char2()
- %0 = bitcast %struct.struct_large_char2* %b to %struct.struct_large_char*
- %coerce.dive = getelementptr %struct.struct_large_char, %struct.struct_large_char* %0, i32 0, i32 0
- %1 = bitcast [8 x i8]* %coerce.dive to i64*
- %2 = load i64, i64* %1, align 1
- %coerce.dive4 = getelementptr %struct.struct_small_char, %struct.struct_small_char* %a, i32 0, i32 0
- %3 = bitcast [2 x i8]* %coerce.dive4 to i16*
- %4 = load i16, i16* %3, align 1
- %coerce.dive5 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d2, i32 0, i32 0
- %5 = bitcast [2 x i16]* %coerce.dive5 to i32*
- %6 = load i32, i32* %5, align 1
- call void @takes_all(i64 %2, i16 %4, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %d1, i32 %6, i8* null, i8* null, i32* null, i16* null, i32* null, i32 0, i32 0, i32 0)
+ %0 = load i64, ptr %b, align 1
+ %1 = load i16, ptr %a, align 1
+ %2 = load i32, ptr %d2, align 1
+ call void @takes_all(i64 %0, i16 %1, ptr byval(%struct.struct_large_nonchar) align 4 %d1, i32 %2, ptr null, ptr null, ptr null, ptr null, ptr null, i32 0, i32 0, i32 0)
ret void
}
@@ -519,4 +443,4 @@ declare void @end_struct_large_nonchar()
declare signext i16 @get_struct_small_nonchar()
declare void @end_struct_small_nonchar()
-declare void @takes_all(i64, i16, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 8, i32, i8*, i8*, i32*, i16*, i32*, i32, i32, i32)
+declare void @takes_all(i64, i16, ptr byval(%struct.struct_large_nonchar) align 8, i32, ptr, ptr, ptr, ptr, ptr, i32, i32, i32)
diff --git a/llvm/test/CodeGen/ARM/stack-alignment.ll b/llvm/test/CodeGen/ARM/stack-alignment.ll
index ac14a5959d1f1..6b14ebf87766b 100644
--- a/llvm/test/CodeGen/ARM/stack-alignment.ll
+++ b/llvm/test/CodeGen/ARM/stack-alignment.ll
@@ -13,7 +13,7 @@ entry:
; CHECK-THUMB2-NEXT: bfc r4, #0, #8
; CHECK-THUMB2-NEXT: mov sp, r4
%x = alloca i32, align 256
- store volatile i32 0, i32* %x, align 256
+ store volatile i32 0, ptr %x, align 256
ret i32 0
}
@@ -27,11 +27,11 @@ entry:
; CHECK-THUMB2-NEXT: bfc r4, #0, #9
; CHECK-THUMB2-NEXT: mov sp, r4
%x = alloca i32, align 512
- store volatile i32 0, i32* %x, align 512
+ store volatile i32 0, ptr %x, align 512
ret i32 0
}
-define i8* @f_alignedDPRCS2Spills(double* %d) #0 {
+define ptr @f_alignedDPRCS2Spills(ptr %d) #0 {
entry:
; CHECK-LABEL: f_too_large_for_bic_align:
; CHECK-v7A32: bfc sp, #0, #12
@@ -40,65 +40,65 @@ entry:
; CHECK-THUMB2: bfc r4, #0, #12
; CHECK-THUMB2-NEXT: mov sp, r4
%a = alloca i8, align 4096
- %0 = load double, double* %d, align 4
- %arrayidx1 = getelementptr inbounds double, double* %d, i32 1
- %1 = load double, double* %arrayidx1, align 4
- %arrayidx2 = getelementptr inbounds double, double* %d, i32 2
- %2 = load double, double* %arrayidx2, align 4
- %arrayidx3 = getelementptr inbounds double, double* %d, i32 3
- %3 = load double, double* %arrayidx3, align 4
- %arrayidx4 = getelementptr inbounds double, double* %d, i32 4
- %4 = load double, double* %arrayidx4, align 4
- %arrayidx5 = getelementptr inbounds double, double* %d, i32 5
- %5 = load double, double* %arrayidx5, align 4
- %arrayidx6 = getelementptr inbounds double, double* %d, i32 6
- %6 = load double, double* %arrayidx6, align 4
- %arrayidx7 = getelementptr inbounds double, double* %d, i32 7
- %7 = load double, double* %arrayidx7, align 4
- %arrayidx8 = getelementptr inbounds double, double* %d, i32 8
- %8 = load double, double* %arrayidx8, align 4
- %arrayidx9 = getelementptr inbounds double, double* %d, i32 9
- %9 = load double, double* %arrayidx9, align 4
- %arrayidx10 = getelementptr inbounds double, double* %d, i32 10
- %10 = load double, double* %arrayidx10, align 4
- %arrayidx11 = getelementptr inbounds double, double* %d, i32 11
- %11 = load double, double* %arrayidx11, align 4
- %arrayidx12 = getelementptr inbounds double, double* %d, i32 12
- %12 = load double, double* %arrayidx12, align 4
- %arrayidx13 = getelementptr inbounds double, double* %d, i32 13
- %13 = load double, double* %arrayidx13, align 4
- %arrayidx14 = getelementptr inbounds double, double* %d, i32 14
- %14 = load double, double* %arrayidx14, align 4
- %arrayidx15 = getelementptr inbounds double, double* %d, i32 15
- %15 = load double, double* %arrayidx15, align 4
- %arrayidx16 = getelementptr inbounds double, double* %d, i32 16
- %16 = load double, double* %arrayidx16, align 4
- %arrayidx17 = getelementptr inbounds double, double* %d, i32 17
- %17 = load double, double* %arrayidx17, align 4
- %arrayidx18 = getelementptr inbounds double, double* %d, i32 18
- %18 = load double, double* %arrayidx18, align 4
- %arrayidx19 = getelementptr inbounds double, double* %d, i32 19
- %19 = load double, double* %arrayidx19, align 4
- %arrayidx20 = getelementptr inbounds double, double* %d, i32 20
- %20 = load double, double* %arrayidx20, align 4
- %arrayidx21 = getelementptr inbounds double, double* %d, i32 21
- %21 = load double, double* %arrayidx21, align 4
- %arrayidx22 = getelementptr inbounds double, double* %d, i32 22
- %22 = load double, double* %arrayidx22, align 4
- %arrayidx23 = getelementptr inbounds double, double* %d, i32 23
- %23 = load double, double* %arrayidx23, align 4
- %arrayidx24 = getelementptr inbounds double, double* %d, i32 24
- %24 = load double, double* %arrayidx24, align 4
- %arrayidx25 = getelementptr inbounds double, double* %d, i32 25
- %25 = load double, double* %arrayidx25, align 4
- %arrayidx26 = getelementptr inbounds double, double* %d, i32 26
- %26 = load double, double* %arrayidx26, align 4
- %arrayidx27 = getelementptr inbounds double, double* %d, i32 27
- %27 = load double, double* %arrayidx27, align 4
- %arrayidx28 = getelementptr inbounds double, double* %d, i32 28
- %28 = load double, double* %arrayidx28, align 4
- %arrayidx29 = getelementptr inbounds double, double* %d, i32 29
- %29 = load double, double* %arrayidx29, align 4
+ %0 = load double, ptr %d, align 4
+ %arrayidx1 = getelementptr inbounds double, ptr %d, i32 1
+ %1 = load double, ptr %arrayidx1, align 4
+ %arrayidx2 = getelementptr inbounds double, ptr %d, i32 2
+ %2 = load double, ptr %arrayidx2, align 4
+ %arrayidx3 = getelementptr inbounds double, ptr %d, i32 3
+ %3 = load double, ptr %arrayidx3, align 4
+ %arrayidx4 = getelementptr inbounds double, ptr %d, i32 4
+ %4 = load double, ptr %arrayidx4, align 4
+ %arrayidx5 = getelementptr inbounds double, ptr %d, i32 5
+ %5 = load double, ptr %arrayidx5, align 4
+ %arrayidx6 = getelementptr inbounds double, ptr %d, i32 6
+ %6 = load double, ptr %arrayidx6, align 4
+ %arrayidx7 = getelementptr inbounds double, ptr %d, i32 7
+ %7 = load double, ptr %arrayidx7, align 4
+ %arrayidx8 = getelementptr inbounds double, ptr %d, i32 8
+ %8 = load double, ptr %arrayidx8, align 4
+ %arrayidx9 = getelementptr inbounds double, ptr %d, i32 9
+ %9 = load double, ptr %arrayidx9, align 4
+ %arrayidx10 = getelementptr inbounds double, ptr %d, i32 10
+ %10 = load double, ptr %arrayidx10, align 4
+ %arrayidx11 = getelementptr inbounds double, ptr %d, i32 11
+ %11 = load double, ptr %arrayidx11, align 4
+ %arrayidx12 = getelementptr inbounds double, ptr %d, i32 12
+ %12 = load double, ptr %arrayidx12, align 4
+ %arrayidx13 = getelementptr inbounds double, ptr %d, i32 13
+ %13 = load double, ptr %arrayidx13, align 4
+ %arrayidx14 = getelementptr inbounds double, ptr %d, i32 14
+ %14 = load double, ptr %arrayidx14, align 4
+ %arrayidx15 = getelementptr inbounds double, ptr %d, i32 15
+ %15 = load double, ptr %arrayidx15, align 4
+ %arrayidx16 = getelementptr inbounds double, ptr %d, i32 16
+ %16 = load double, ptr %arrayidx16, align 4
+ %arrayidx17 = getelementptr inbounds double, ptr %d, i32 17
+ %17 = load double, ptr %arrayidx17, align 4
+ %arrayidx18 = getelementptr inbounds double, ptr %d, i32 18
+ %18 = load double, ptr %arrayidx18, align 4
+ %arrayidx19 = getelementptr inbounds double, ptr %d, i32 19
+ %19 = load double, ptr %arrayidx19, align 4
+ %arrayidx20 = getelementptr inbounds double, ptr %d, i32 20
+ %20 = load double, ptr %arrayidx20, align 4
+ %arrayidx21 = getelementptr inbounds double, ptr %d, i32 21
+ %21 = load double, ptr %arrayidx21, align 4
+ %arrayidx22 = getelementptr inbounds double, ptr %d, i32 22
+ %22 = load double, ptr %arrayidx22, align 4
+ %arrayidx23 = getelementptr inbounds double, ptr %d, i32 23
+ %23 = load double, ptr %arrayidx23, align 4
+ %arrayidx24 = getelementptr inbounds double, ptr %d, i32 24
+ %24 = load double, ptr %arrayidx24, align 4
+ %arrayidx25 = getelementptr inbounds double, ptr %d, i32 25
+ %25 = load double, ptr %arrayidx25, align 4
+ %arrayidx26 = getelementptr inbounds double, ptr %d, i32 26
+ %26 = load double, ptr %arrayidx26, align 4
+ %arrayidx27 = getelementptr inbounds double, ptr %d, i32 27
+ %27 = load double, ptr %arrayidx27, align 4
+ %arrayidx28 = getelementptr inbounds double, ptr %d, i32 28
+ %28 = load double, ptr %arrayidx28, align 4
+ %arrayidx29 = getelementptr inbounds double, ptr %d, i32 29
+ %29 = load double, ptr %arrayidx29, align 4
%div = fdiv double %29, %28
%div30 = fdiv double %div, %27
%div31 = fdiv double %div30, %26
@@ -159,6 +159,6 @@ entry:
%div86 = fdiv double %div85, %29
%mul = fmul double %div57, %div86
%conv = fptosi double %mul to i32
- %add.ptr = getelementptr inbounds i8, i8* %a, i32 %conv
- ret i8* %add.ptr
+ %add.ptr = getelementptr inbounds i8, ptr %a, i32 %conv
+ ret ptr %add.ptr
}
diff --git a/llvm/test/CodeGen/ARM/stack-guard-rwpi.ll b/llvm/test/CodeGen/ARM/stack-guard-rwpi.ll
index c7eeee39dca56..25fcc738ef014 100644
--- a/llvm/test/CodeGen/ARM/stack-guard-rwpi.ll
+++ b/llvm/test/CodeGen/ARM/stack-guard-rwpi.ll
@@ -21,8 +21,8 @@
define dso_local i32 @foo(i32 %t) nounwind sspstrong {
entry:
%vla = alloca i32, i32 %t
- %call = call i32 @baz(i32* %vla)
+ %call = call i32 @baz(ptr %vla)
ret i32 %call
}
-declare dso_local i32 @baz(i32*)
+declare dso_local i32 @baz(ptr)
diff --git a/llvm/test/CodeGen/ARM/stack-guard-tls.ll b/llvm/test/CodeGen/ARM/stack-guard-tls.ll
index 5d405e276d8ec..6c3fe43ab31ce 100644
--- a/llvm/test/CodeGen/ARM/stack-guard-tls.ll
+++ b/llvm/test/CodeGen/ARM/stack-guard-tls.ll
@@ -11,11 +11,11 @@
; RUN: FileCheck --check-prefixes=CHECK,CHECK-LARGE %s
;--- main.ll
-declare void @baz(i32*)
+declare void @baz(ptr)
define void @foo(i64 %t) sspstrong {
%vla = alloca i32, i64 %t, align 4
- call void @baz(i32* nonnull %vla)
+ call void @baz(ptr nonnull %vla)
ret void
}
!llvm.module.flags = !{!1, !2}
diff --git a/llvm/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll b/llvm/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll
index 9f37203d8533a..6f2cb4251b456 100644
--- a/llvm/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll
+++ b/llvm/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll
@@ -14,17 +14,16 @@ target triple = "armv7s-apple-ios6.0.0"
define i32 @main() #0 {
entry:
%title = alloca [15 x i8], align 1
- %0 = getelementptr inbounds [15 x i8], [15 x i8]* %title, i32 0, i32 0
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %0, i8* align 1 getelementptr inbounds ([15 x i8], [15 x i8]* @main.title, i32 0, i32 0), i32 15, i1 false)
- %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i8* %0) #3
+ call void @llvm.memcpy.p0.p0.i32(ptr align 1 %title, ptr align 1 @main.title, i32 15, i1 false)
+ %call = call i32 (ptr, ...) @printf(ptr @.str, ptr %title) #3
ret i32 0
}
; Function Attrs: nounwind
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1) #1
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture readonly, i32, i1) #1
; Function Attrs: nounwind optsize
-declare i32 @printf(i8* nocapture readonly, ...) #2
+declare i32 @printf(ptr nocapture readonly, ...) #2
attributes #0 = { nounwind optsize ssp "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind }
diff --git a/llvm/test/CodeGen/ARM/stack_guard_remat.ll b/llvm/test/CodeGen/ARM/stack_guard_remat.ll
index 12c9b85ab8d0a..f1677a204f9d1 100644
--- a/llvm/test/CodeGen/ARM/stack_guard_remat.ll
+++ b/llvm/test/CodeGen/ARM/stack_guard_remat.ll
@@ -50,21 +50,19 @@
; Function Attrs: nounwind ssp
define i32 @test_stack_guard_remat() #0 {
%a1 = alloca [256 x i32], align 4
- %1 = bitcast [256 x i32]* %a1 to i8*
- call void @llvm.lifetime.start.p0i8(i64 1024, i8* %1)
- %2 = getelementptr inbounds [256 x i32], [256 x i32]* %a1, i32 0, i32 0
- call void @foo3(i32* %2) #3
+ call void @llvm.lifetime.start.p0(i64 1024, ptr %a1)
+ call void @foo3(ptr %a1) #3
call void asm sideeffect "foo2", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{sp},~{lr}"()
- call void @llvm.lifetime.end.p0i8(i64 1024, i8* %1)
+ call void @llvm.lifetime.end.p0(i64 1024, ptr %a1)
ret i32 0
}
; Function Attrs: nounwind
-declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
+declare void @llvm.lifetime.start.p0(i64, ptr nocapture)
-declare void @foo3(i32*)
+declare void @foo3(ptr)
; Function Attrs: nounwind
-declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)
+declare void @llvm.lifetime.end.p0(i64, ptr nocapture)
attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/CodeGen/ARM/static-addr-hoisting.ll b/llvm/test/CodeGen/ARM/static-addr-hoisting.ll
index 01b6437143eab..20d28c8dea9a1 100644
--- a/llvm/test/CodeGen/ARM/static-addr-hoisting.ll
+++ b/llvm/test/CodeGen/ARM/static-addr-hoisting.ll
@@ -14,9 +14,9 @@ define void @multiple_store() {
; CHECK-NEXT: movt r0, #18
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- store i32 42, i32* inttoptr(i32 1000000 to i32*)
- store i32 42, i32* inttoptr(i32 1000024 to i32*)
- store i32 42, i32* inttoptr(i32 1000042 to i32*)
- store i32 42, i32* inttoptr(i32 1200042 to i32*)
+ store i32 42, ptr inttoptr(i32 1000000 to ptr)
+ store i32 42, ptr inttoptr(i32 1000024 to ptr)
+ store i32 42, ptr inttoptr(i32 1000042 to ptr)
+ store i32 42, ptr inttoptr(i32 1200042 to ptr)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/stc2.ll b/llvm/test/CodeGen/ARM/stc2.ll
index c4d7ff007f513..b65b0097c43ce 100644
--- a/llvm/test/CodeGen/ARM/stc2.ll
+++ b/llvm/test/CodeGen/ARM/stc2.ll
@@ -2,10 +2,10 @@
; RUN: not --crash llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.stc2
-define void @stc2(i8* %i) nounwind {
+define void @stc2(ptr %i) nounwind {
entry:
- call void @llvm.arm.stc2(i32 1, i32 2, i8* %i) nounwind
+ call void @llvm.arm.stc2(i32 1, i32 2, ptr %i) nounwind
ret void
}
-declare void @llvm.arm.stc2(i32, i32, i8*) nounwind
+declare void @llvm.arm.stc2(i32, i32, ptr) nounwind
diff --git a/llvm/test/CodeGen/ARM/stm.ll b/llvm/test/CodeGen/ARM/stm.ll
index 88207e6be105d..a0e4e966fd1d2 100644
--- a/llvm/test/CodeGen/ARM/stm.ll
+++ b/llvm/test/CodeGen/ARM/stm.ll
@@ -1,16 +1,16 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | FileCheck %s
-@"\01LC" = internal constant [32 x i8] c"Boolean Not: %d %d %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[32 x i8]*> [#uses=1]
-@"\01LC1" = internal constant [26 x i8] c"Bitwise Not: %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[26 x i8]*> [#uses=1]
+@"\01LC" = internal constant [32 x i8] c"Boolean Not: %d %d %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <ptr> [#uses=1]
+@"\01LC1" = internal constant [26 x i8] c"Bitwise Not: %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <ptr> [#uses=1]
-declare i32 @printf(i8* nocapture, ...) nounwind
+declare i32 @printf(ptr nocapture, ...) nounwind
define i32 @main() nounwind {
entry:
; CHECK: main
; CHECK: push
; CHECK: stm
- %0 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([26 x i8], [26 x i8]* @"\01LC1", i32 0, i32 0), i32 -2, i32 -3, i32 2, i32 -6) nounwind ; <i32> [#uses=0]
- %1 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([32 x i8], [32 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 1, i32 0, i32 1, i32 0, i32 1) nounwind ; <i32> [#uses=0]
+ %0 = tail call i32 (ptr, ...) @printf(ptr @"\01LC1", i32 -2, i32 -3, i32 2, i32 -6) nounwind ; <i32> [#uses=0]
+ %1 = tail call i32 (ptr, ...) @printf(ptr @"\01LC", i32 0, i32 1, i32 0, i32 1, i32 0, i32 1) nounwind ; <i32> [#uses=0]
ret i32 0
}
diff --git a/llvm/test/CodeGen/ARM/store-postinc.ll b/llvm/test/CodeGen/ARM/store-postinc.ll
index 29d2550e05d2d..2735819b2a71f 100644
--- a/llvm/test/CodeGen/ARM/store-postinc.ll
+++ b/llvm/test/CodeGen/ARM/store-postinc.ll
@@ -3,18 +3,16 @@
; RUN: llc -mtriple=thumbv7m-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-T2
; RUN: llc -mtriple=armv7a-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-ARM
-define i8* @i32_0(i8* %p, i32 %v) {
+define ptr @i32_0(ptr %p, i32 %v) {
; CHECK-LABEL: i32_0:
; CHECK: @ %bb.0:
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 0
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ store i32 %v, ptr %p, align 4
+ ret ptr %p
}
-define i8* @i32_3(i8* %p, i32 %v) {
+define ptr @i32_3(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_3:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #3
@@ -31,13 +29,12 @@ define i8* @i32_3(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #3]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 3
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 3
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_4(i8* %p, i32 %v) {
+define ptr @i32_4(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: str r1, [r0, #4]
@@ -53,13 +50,12 @@ define i8* @i32_4(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_8(i8* %p, i32 %v) {
+define ptr @i32_8(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_8:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: str r1, [r0, #8]
@@ -75,13 +71,12 @@ define i8* @i32_8(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #8]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 8
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 8
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_m1(i8* %p, i32 %v) {
+define ptr @i32_m1(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_m1:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -97,13 +92,12 @@ define i8* @i32_m1(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #-1]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -1
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -1
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_m4(i8* %p, i32 %v) {
+define ptr @i32_m4(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_m4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #4
@@ -119,13 +113,12 @@ define i8* @i32_m4(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #-4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_252(i8* %p, i32 %v) {
+define ptr @i32_252(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #252
@@ -142,13 +135,12 @@ define i8* @i32_252(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #252]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 252
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 252
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_255(i8* %p, i32 %v) {
+define ptr @i32_255(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #255
@@ -165,13 +157,12 @@ define i8* @i32_255(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #255]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 255
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 255
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_256(i8* %p, i32 %v) {
+define ptr @i32_256(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #1
@@ -190,13 +181,12 @@ define i8* @i32_256(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #256]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 256
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 256
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_m252(i8* %p, i32 %v) {
+define ptr @i32_m252(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_m252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #252
@@ -212,13 +202,12 @@ define i8* @i32_m252(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #-252]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -252
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -252
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_m255(i8* %p, i32 %v) {
+define ptr @i32_m255(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_m255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #255
@@ -234,13 +223,12 @@ define i8* @i32_m255(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #-255]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -255
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -255
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_m256(i8* %p, i32 %v) {
+define ptr @i32_m256(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_m256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #255
@@ -260,13 +248,12 @@ define i8* @i32_m256(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #-256]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -256
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -256
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_4095(i8* %p, i32 %v) {
+define ptr @i32_4095(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI12_0
@@ -288,13 +275,12 @@ define i8* @i32_4095(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #4095]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4095
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4095
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_4096(i8* %p, i32 %v) {
+define ptr @i32_4096(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #1
@@ -315,13 +301,12 @@ define i8* @i32_4096(i8* %p, i32 %v) {
; CHECK-ARM-NEXT: mov r2, #4096
; CHECK-ARM-NEXT: str r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4096
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4096
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_m4095(i8* %p, i32 %v) {
+define ptr @i32_m4095(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_m4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI14_0
@@ -345,13 +330,12 @@ define i8* @i32_m4095(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #-4095]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4095
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4095
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_m4096(i8* %p, i32 %v) {
+define ptr @i32_m4096(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_m4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI15_0
@@ -377,13 +361,12 @@ define i8* @i32_m4096(i8* %p, i32 %v) {
; CHECK-ARM-NEXT: movt r2, #65535
; CHECK-ARM-NEXT: str r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4096
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4096
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i64_0(i8* %p, i64 %v) {
+define ptr @i64_0(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_0:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: stm r0!, {r2, r3}
@@ -401,13 +384,11 @@ define i8* @i64_0(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0]
; CHECK-ARM-NEXT: str r1, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 0
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ store i64 %v, ptr %p, align 8
+ ret ptr %p
}
-define i8* @i64_3(i8* %p, i64 %v) {
+define ptr @i64_3(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_3:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r1, #3
@@ -427,13 +408,12 @@ define i8* @i64_3(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #3]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 3
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 3
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_4(i8* %p, i64 %v) {
+define ptr @i64_4(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: str r2, [r0, #4]
@@ -452,13 +432,12 @@ define i8* @i64_4(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #4]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_8(i8* %p, i64 %v) {
+define ptr @i64_8(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_8:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: str r2, [r0, #8]
@@ -477,13 +456,12 @@ define i8* @i64_8(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #8]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 8
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 8
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_m1(i8* %p, i64 %v) {
+define ptr @i64_m1(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_m1:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -502,13 +480,12 @@ define i8* @i64_m1(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #-1]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -1
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -1
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_m4(i8* %p, i64 %v) {
+define ptr @i64_m4(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_m4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: str r3, [r0]
@@ -527,13 +504,12 @@ define i8* @i64_m4(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r3, [r0]
; CHECK-ARM-NEXT: str r2, [r0, #-4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_252(i8* %p, i64 %v) {
+define ptr @i64_252(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r1, #252
@@ -553,13 +529,12 @@ define i8* @i64_252(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #252]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 252
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 252
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_255(i8* %p, i64 %v) {
+define ptr @i64_255(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r1, #255
@@ -579,13 +554,12 @@ define i8* @i64_255(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #255]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 255
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 255
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_256(i8* %p, i64 %v) {
+define ptr @i64_256(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r1, #1
@@ -606,13 +580,12 @@ define i8* @i64_256(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #256]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 256
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 256
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_m252(i8* %p, i64 %v) {
+define ptr @i64_m252(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_m252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #252
@@ -631,13 +604,12 @@ define i8* @i64_m252(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #-252]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -252
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -252
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_m255(i8* %p, i64 %v) {
+define ptr @i64_m255(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_m255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #255
@@ -656,13 +628,12 @@ define i8* @i64_m255(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #-255]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -255
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -255
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_m256(i8* %p, i64 %v) {
+define ptr @i64_m256(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_m256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r1, #255
@@ -685,13 +656,12 @@ define i8* @i64_m256(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #-256]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -256
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -256
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_4095(i8* %p, i64 %v) {
+define ptr @i64_4095(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, .LCPI28_0
@@ -716,13 +686,12 @@ define i8* @i64_4095(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #4095]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4095
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4095
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_4096(i8* %p, i64 %v) {
+define ptr @i64_4096(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r1, #1
@@ -746,13 +715,12 @@ define i8* @i64_4096(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, r1]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4096
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4096
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_m4095(i8* %p, i64 %v) {
+define ptr @i64_m4095(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_m4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, .LCPI30_0
@@ -779,13 +747,12 @@ define i8* @i64_m4095(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #-4095]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4095
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4095
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_m4096(i8* %p, i64 %v) {
+define ptr @i64_m4096(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_m4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, .LCPI31_0
@@ -814,13 +781,12 @@ define i8* @i64_m4096(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, r1]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4096
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4096
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i128_0(i8* %p, i128 %v) {
+define ptr @i128_0(ptr %p, i128 %v) {
; CHECK-T1-LABEL: i128_0:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, [sp, #4]
@@ -847,13 +813,11 @@ define i8* @i128_0(i8* %p, i128 %v) {
; CHECK-ARM-NEXT: str r1, [r0, #8]
; CHECK-ARM-NEXT: str r12, [r0, #12]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 0
- %q = bitcast i8* %o to i128*
- store i128 %v, i128* %q, align 16
- ret i8* %o
+ store i128 %v, ptr %p, align 16
+ ret ptr %p
}
-define i8* @i128_3(i8* %p, i128 %v) {
+define ptr @i128_3(ptr %p, i128 %v) {
; CHECK-T1-LABEL: i128_3:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r1, #3
@@ -883,13 +847,12 @@ define i8* @i128_3(i8* %p, i128 %v) {
; CHECK-ARM-NEXT: str r1, [r0, #8]
; CHECK-ARM-NEXT: str r12, [r0, #12]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 3
- %q = bitcast i8* %o to i128*
- store i128 %v, i128* %q, align 16
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 3
+ store i128 %v, ptr %o, align 16
+ ret ptr %o
}
-define i8* @i128_4(i8* %p, i128 %v) {
+define ptr @i128_4(ptr %p, i128 %v) {
; CHECK-T1-LABEL: i128_4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, [sp, #4]
@@ -918,13 +881,12 @@ define i8* @i128_4(i8* %p, i128 %v) {
; CHECK-ARM-NEXT: str r1, [r0, #8]
; CHECK-ARM-NEXT: str r12, [r0, #12]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4
- %q = bitcast i8* %o to i128*
- store i128 %v, i128* %q, align 16
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4
+ store i128 %v, ptr %o, align 16
+ ret ptr %o
}
-define i8* @i128_8(i8* %p, i128 %v) {
+define ptr @i128_8(ptr %p, i128 %v) {
; CHECK-T1-LABEL: i128_8:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, [sp, #4]
@@ -953,13 +915,12 @@ define i8* @i128_8(i8* %p, i128 %v) {
; CHECK-ARM-NEXT: str r1, [r0, #8]
; CHECK-ARM-NEXT: str r12, [r0, #12]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 8
- %q = bitcast i8* %o to i128*
- store i128 %v, i128* %q, align 16
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 8
+ store i128 %v, ptr %o, align 16
+ ret ptr %o
}
-define i8* @i128_16(i8* %p, i128 %v) {
+define ptr @i128_16(ptr %p, i128 %v) {
; CHECK-T1-LABEL: i128_16:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, [sp, #4]
@@ -988,13 +949,12 @@ define i8* @i128_16(i8* %p, i128 %v) {
; CHECK-ARM-NEXT: str r1, [r0, #8]
; CHECK-ARM-NEXT: str r12, [r0, #12]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 16
- %q = bitcast i8* %o to i128*
- store i128 %v, i128* %q, align 16
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 16
+ store i128 %v, ptr %o, align 16
+ ret ptr %o
}
-define i8* @i128_m1(i8* %p, i128 %v) {
+define ptr @i128_m1(ptr %p, i128 %v) {
; CHECK-T1-LABEL: i128_m1:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -1023,13 +983,12 @@ define i8* @i128_m1(i8* %p, i128 %v) {
; CHECK-ARM-NEXT: str r1, [r0, #8]
; CHECK-ARM-NEXT: str r12, [r0, #12]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -1
- %q = bitcast i8* %o to i128*
- store i128 %v, i128* %q, align 16
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -1
+ store i128 %v, ptr %o, align 16
+ ret ptr %o
}
-define i8* @i128_m4(i8* %p, i128 %v) {
+define ptr @i128_m4(ptr %p, i128 %v) {
; CHECK-T1-LABEL: i128_m4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, [sp, #4]
@@ -1057,24 +1016,21 @@ define i8* @i128_m4(i8* %p, i128 %v) {
; CHECK-ARM-NEXT: stmib r0, {r1, r12}
; CHECK-ARM-NEXT: str r2, [r0, #-4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4
- %q = bitcast i8* %o to i128*
- store i128 %v, i128* %q, align 16
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4
+ store i128 %v, ptr %o, align 16
+ ret ptr %o
}
-define i8* @i16_0(i8* %p, i16 %v) {
+define ptr @i16_0(ptr %p, i16 %v) {
; CHECK-LABEL: i16_0:
; CHECK: @ %bb.0:
; CHECK-NEXT: strh r1, [r0]
; CHECK-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 0
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ store i16 %v, ptr %p, align 2
+ ret ptr %p
}
-define i8* @i16_3(i8* %p, i16 %v) {
+define ptr @i16_3(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_3:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #3
@@ -1091,13 +1047,12 @@ define i8* @i16_3(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #3]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 3
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 3
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_4(i8* %p, i16 %v) {
+define ptr @i16_4(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: strh r1, [r0, #4]
@@ -1113,13 +1068,12 @@ define i8* @i16_4(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_8(i8* %p, i16 %v) {
+define ptr @i16_8(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_8:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: strh r1, [r0, #8]
@@ -1135,13 +1089,12 @@ define i8* @i16_8(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #8]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 8
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 8
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_m1(i8* %p, i16 %v) {
+define ptr @i16_m1(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_m1:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -1157,13 +1110,12 @@ define i8* @i16_m1(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #-1]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -1
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -1
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_m4(i8* %p, i16 %v) {
+define ptr @i16_m4(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_m4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #4
@@ -1179,13 +1131,12 @@ define i8* @i16_m4(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #-4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_252(i8* %p, i16 %v) {
+define ptr @i16_252(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #252
@@ -1202,13 +1153,12 @@ define i8* @i16_252(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #252]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 252
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 252
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_255(i8* %p, i16 %v) {
+define ptr @i16_255(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #255
@@ -1225,13 +1175,12 @@ define i8* @i16_255(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #255]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 255
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 255
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_256(i8* %p, i16 %v) {
+define ptr @i16_256(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #1
@@ -1251,13 +1200,12 @@ define i8* @i16_256(i8* %p, i16 %v) {
; CHECK-ARM-NEXT: mov r2, #256
; CHECK-ARM-NEXT: strh r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 256
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 256
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_m252(i8* %p, i16 %v) {
+define ptr @i16_m252(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_m252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #252
@@ -1273,13 +1221,12 @@ define i8* @i16_m252(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #-252]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -252
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -252
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_m255(i8* %p, i16 %v) {
+define ptr @i16_m255(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_m255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #255
@@ -1295,13 +1242,12 @@ define i8* @i16_m255(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #-255]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -255
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -255
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_m256(i8* %p, i16 %v) {
+define ptr @i16_m256(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_m256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #255
@@ -1322,13 +1268,12 @@ define i8* @i16_m256(i8* %p, i16 %v) {
; CHECK-ARM-NEXT: mvn r2, #255
; CHECK-ARM-NEXT: strh r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -256
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -256
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_4095(i8* %p, i16 %v) {
+define ptr @i16_4095(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI51_0
@@ -1351,13 +1296,12 @@ define i8* @i16_4095(i8* %p, i16 %v) {
; CHECK-ARM-NEXT: movw r2, #4095
; CHECK-ARM-NEXT: strh r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4095
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4095
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_4096(i8* %p, i16 %v) {
+define ptr @i16_4096(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #1
@@ -1378,13 +1322,12 @@ define i8* @i16_4096(i8* %p, i16 %v) {
; CHECK-ARM-NEXT: mov r2, #4096
; CHECK-ARM-NEXT: strh r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4096
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4096
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_m4095(i8* %p, i16 %v) {
+define ptr @i16_m4095(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_m4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI53_0
@@ -1410,13 +1353,12 @@ define i8* @i16_m4095(i8* %p, i16 %v) {
; CHECK-ARM-NEXT: movt r2, #65535
; CHECK-ARM-NEXT: strh r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4095
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4095
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_m4096(i8* %p, i16 %v) {
+define ptr @i16_m4096(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_m4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI54_0
@@ -1442,24 +1384,21 @@ define i8* @i16_m4096(i8* %p, i16 %v) {
; CHECK-ARM-NEXT: movt r2, #65535
; CHECK-ARM-NEXT: strh r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4096
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4096
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i8_0(i8* %p, i8 %v) {
+define ptr @i8_0(ptr %p, i8 %v) {
; CHECK-LABEL: i8_0:
; CHECK: @ %bb.0:
; CHECK-NEXT: strb r1, [r0]
; CHECK-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 0
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ store i8 %v, ptr %p, align 1
+ ret ptr %p
}
-define i8* @i8_3(i8* %p, i8 %v) {
+define ptr @i8_3(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_3:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: strb r1, [r0, #3]
@@ -1475,13 +1414,12 @@ define i8* @i8_3(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #3]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 3
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 3
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_4(i8* %p, i8 %v) {
+define ptr @i8_4(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: strb r1, [r0, #4]
@@ -1497,13 +1435,12 @@ define i8* @i8_4(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_8(i8* %p, i8 %v) {
+define ptr @i8_8(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_8:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: strb r1, [r0, #8]
@@ -1519,13 +1456,12 @@ define i8* @i8_8(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #8]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 8
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 8
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_m1(i8* %p, i8 %v) {
+define ptr @i8_m1(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_m1:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -1541,13 +1477,12 @@ define i8* @i8_m1(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #-1]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -1
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -1
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_m4(i8* %p, i8 %v) {
+define ptr @i8_m4(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_m4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #4
@@ -1563,13 +1498,12 @@ define i8* @i8_m4(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #-4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_252(i8* %p, i8 %v) {
+define ptr @i8_252(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #252
@@ -1586,13 +1520,12 @@ define i8* @i8_252(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #252]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 252
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 252
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_255(i8* %p, i8 %v) {
+define ptr @i8_255(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #255
@@ -1609,13 +1542,12 @@ define i8* @i8_255(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #255]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 255
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 255
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_256(i8* %p, i8 %v) {
+define ptr @i8_256(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #1
@@ -1634,13 +1566,12 @@ define i8* @i8_256(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #256]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 256
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 256
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_m252(i8* %p, i8 %v) {
+define ptr @i8_m252(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_m252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #252
@@ -1656,13 +1587,12 @@ define i8* @i8_m252(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #-252]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -252
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -252
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_m255(i8* %p, i8 %v) {
+define ptr @i8_m255(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_m255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #255
@@ -1678,13 +1608,12 @@ define i8* @i8_m255(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #-255]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -255
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -255
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_m256(i8* %p, i8 %v) {
+define ptr @i8_m256(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_m256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #255
@@ -1704,13 +1633,12 @@ define i8* @i8_m256(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #-256]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -256
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -256
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_4095(i8* %p, i8 %v) {
+define ptr @i8_4095(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI67_0
@@ -1732,13 +1660,12 @@ define i8* @i8_4095(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #4095]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4095
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4095
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_4096(i8* %p, i8 %v) {
+define ptr @i8_4096(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #1
@@ -1759,13 +1686,12 @@ define i8* @i8_4096(i8* %p, i8 %v) {
; CHECK-ARM-NEXT: mov r2, #4096
; CHECK-ARM-NEXT: strb r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4096
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4096
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_m4095(i8* %p, i8 %v) {
+define ptr @i8_m4095(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_m4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI69_0
@@ -1789,13 +1715,12 @@ define i8* @i8_m4095(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #-4095]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4095
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4095
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_m4096(i8* %p, i8 %v) {
+define ptr @i8_m4096(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_m4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI70_0
@@ -1821,8 +1746,7 @@ define i8* @i8_m4096(i8* %p, i8 %v) {
; CHECK-ARM-NEXT: movt r2, #65535
; CHECK-ARM-NEXT: strb r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4096
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4096
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
diff --git a/llvm/test/CodeGen/ARM/store-preinc.ll b/llvm/test/CodeGen/ARM/store-preinc.ll
index 47aa73a86e76c..d3bf001ca307b 100644
--- a/llvm/test/CodeGen/ARM/store-preinc.ll
+++ b/llvm/test/CodeGen/ARM/store-preinc.ll
@@ -3,18 +3,16 @@
; RUN: llc -mtriple=thumbv7m-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-T2
; RUN: llc -mtriple=armv7a-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-ARM
-define i8* @i32_0(i8* %p, i32 %v) {
+define ptr @i32_0(ptr %p, i32 %v) {
; CHECK-LABEL: i32_0:
; CHECK: @ %bb.0:
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 0
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ store i32 %v, ptr %p, align 4
+ ret ptr %p
}
-define i8* @i32_3(i8* %p, i32 %v) {
+define ptr @i32_3(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_3:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #3
@@ -31,13 +29,12 @@ define i8* @i32_3(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #3]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 3
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 3
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_4(i8* %p, i32 %v) {
+define ptr @i32_4(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: str r1, [r0, #4]
@@ -53,13 +50,12 @@ define i8* @i32_4(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_8(i8* %p, i32 %v) {
+define ptr @i32_8(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_8:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: str r1, [r0, #8]
@@ -75,13 +71,12 @@ define i8* @i32_8(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #8]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 8
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 8
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_m1(i8* %p, i32 %v) {
+define ptr @i32_m1(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_m1:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -97,13 +92,12 @@ define i8* @i32_m1(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #-1]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -1
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -1
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_m4(i8* %p, i32 %v) {
+define ptr @i32_m4(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_m4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #4
@@ -119,13 +113,12 @@ define i8* @i32_m4(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #-4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_252(i8* %p, i32 %v) {
+define ptr @i32_252(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #252
@@ -142,13 +135,12 @@ define i8* @i32_252(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #252]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 252
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 252
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_255(i8* %p, i32 %v) {
+define ptr @i32_255(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #255
@@ -165,13 +157,12 @@ define i8* @i32_255(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #255]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 255
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 255
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_256(i8* %p, i32 %v) {
+define ptr @i32_256(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #1
@@ -190,13 +181,12 @@ define i8* @i32_256(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #256]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 256
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 256
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_m252(i8* %p, i32 %v) {
+define ptr @i32_m252(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_m252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #252
@@ -212,13 +202,12 @@ define i8* @i32_m252(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #-252]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -252
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -252
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_m255(i8* %p, i32 %v) {
+define ptr @i32_m255(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_m255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #255
@@ -234,13 +223,12 @@ define i8* @i32_m255(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #-255]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -255
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -255
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_m256(i8* %p, i32 %v) {
+define ptr @i32_m256(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_m256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #255
@@ -260,13 +248,12 @@ define i8* @i32_m256(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #-256]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -256
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -256
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_4095(i8* %p, i32 %v) {
+define ptr @i32_4095(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI12_0
@@ -288,13 +275,12 @@ define i8* @i32_4095(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #4095]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4095
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4095
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_4096(i8* %p, i32 %v) {
+define ptr @i32_4096(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #1
@@ -315,13 +301,12 @@ define i8* @i32_4096(i8* %p, i32 %v) {
; CHECK-ARM-NEXT: mov r2, #4096
; CHECK-ARM-NEXT: str r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4096
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4096
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_m4095(i8* %p, i32 %v) {
+define ptr @i32_m4095(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_m4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI14_0
@@ -345,13 +330,12 @@ define i8* @i32_m4095(i8* %p, i32 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: str r1, [r0, #-4095]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4095
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4095
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i32_m4096(i8* %p, i32 %v) {
+define ptr @i32_m4096(ptr %p, i32 %v) {
; CHECK-T1-LABEL: i32_m4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI15_0
@@ -377,13 +361,12 @@ define i8* @i32_m4096(i8* %p, i32 %v) {
; CHECK-ARM-NEXT: movt r2, #65535
; CHECK-ARM-NEXT: str r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4096
- %q = bitcast i8* %o to i32*
- store i32 %v, i32* %q, align 4
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4096
+ store i32 %v, ptr %o, align 4
+ ret ptr %o
}
-define i8* @i64_0(i8* %p, i64 %v) {
+define ptr @i64_0(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_0:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: stm r0!, {r2, r3}
@@ -401,13 +384,11 @@ define i8* @i64_0(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0]
; CHECK-ARM-NEXT: str r1, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 0
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ store i64 %v, ptr %p, align 8
+ ret ptr %p
}
-define i8* @i64_3(i8* %p, i64 %v) {
+define ptr @i64_3(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_3:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r1, #3
@@ -427,13 +408,12 @@ define i8* @i64_3(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #3]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 3
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 3
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_4(i8* %p, i64 %v) {
+define ptr @i64_4(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: str r2, [r0, #4]
@@ -452,13 +432,12 @@ define i8* @i64_4(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #4]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_8(i8* %p, i64 %v) {
+define ptr @i64_8(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_8:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: str r2, [r0, #8]
@@ -477,13 +456,12 @@ define i8* @i64_8(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #8]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 8
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 8
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_m1(i8* %p, i64 %v) {
+define ptr @i64_m1(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_m1:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -502,13 +480,12 @@ define i8* @i64_m1(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #-1]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -1
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -1
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_m4(i8* %p, i64 %v) {
+define ptr @i64_m4(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_m4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: str r3, [r0]
@@ -527,13 +504,12 @@ define i8* @i64_m4(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r3, [r0]
; CHECK-ARM-NEXT: str r2, [r0, #-4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_252(i8* %p, i64 %v) {
+define ptr @i64_252(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r1, #252
@@ -553,13 +529,12 @@ define i8* @i64_252(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #252]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 252
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 252
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_255(i8* %p, i64 %v) {
+define ptr @i64_255(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r1, #255
@@ -579,13 +554,12 @@ define i8* @i64_255(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #255]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 255
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 255
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_256(i8* %p, i64 %v) {
+define ptr @i64_256(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r1, #1
@@ -606,13 +580,12 @@ define i8* @i64_256(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #256]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 256
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 256
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_m252(i8* %p, i64 %v) {
+define ptr @i64_m252(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_m252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #252
@@ -631,13 +604,12 @@ define i8* @i64_m252(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #-252]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -252
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -252
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_m255(i8* %p, i64 %v) {
+define ptr @i64_m255(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_m255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #255
@@ -656,13 +628,12 @@ define i8* @i64_m255(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #-255]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -255
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -255
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_m256(i8* %p, i64 %v) {
+define ptr @i64_m256(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_m256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r1, #255
@@ -685,13 +656,12 @@ define i8* @i64_m256(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #-256]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -256
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -256
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_4095(i8* %p, i64 %v) {
+define ptr @i64_4095(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, .LCPI28_0
@@ -716,13 +686,12 @@ define i8* @i64_4095(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #4095]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4095
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4095
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_4096(i8* %p, i64 %v) {
+define ptr @i64_4096(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r1, #1
@@ -746,13 +715,12 @@ define i8* @i64_4096(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, r1]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4096
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4096
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_m4095(i8* %p, i64 %v) {
+define ptr @i64_m4095(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_m4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, .LCPI30_0
@@ -779,13 +747,12 @@ define i8* @i64_m4095(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, #-4095]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4095
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4095
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i64_m4096(i8* %p, i64 %v) {
+define ptr @i64_m4096(ptr %p, i64 %v) {
; CHECK-T1-LABEL: i64_m4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, .LCPI31_0
@@ -814,13 +781,12 @@ define i8* @i64_m4096(i8* %p, i64 %v) {
; CHECK-ARM-NEXT: str r2, [r0, r1]!
; CHECK-ARM-NEXT: str r3, [r0, #4]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4096
- %q = bitcast i8* %o to i64*
- store i64 %v, i64* %q, align 8
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4096
+ store i64 %v, ptr %o, align 8
+ ret ptr %o
}
-define i8* @i128_0(i8* %p, i128 %v) {
+define ptr @i128_0(ptr %p, i128 %v) {
; CHECK-T1-LABEL: i128_0:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, [sp, #4]
@@ -847,13 +813,11 @@ define i8* @i128_0(i8* %p, i128 %v) {
; CHECK-ARM-NEXT: str r1, [r0, #8]
; CHECK-ARM-NEXT: str r12, [r0, #12]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 0
- %q = bitcast i8* %o to i128*
- store i128 %v, i128* %q, align 16
- ret i8* %o
+ store i128 %v, ptr %p, align 16
+ ret ptr %p
}
-define i8* @i128_3(i8* %p, i128 %v) {
+define ptr @i128_3(ptr %p, i128 %v) {
; CHECK-T1-LABEL: i128_3:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r1, #3
@@ -883,13 +847,12 @@ define i8* @i128_3(i8* %p, i128 %v) {
; CHECK-ARM-NEXT: str r1, [r0, #8]
; CHECK-ARM-NEXT: str r12, [r0, #12]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 3
- %q = bitcast i8* %o to i128*
- store i128 %v, i128* %q, align 16
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 3
+ store i128 %v, ptr %o, align 16
+ ret ptr %o
}
-define i8* @i128_4(i8* %p, i128 %v) {
+define ptr @i128_4(ptr %p, i128 %v) {
; CHECK-T1-LABEL: i128_4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, [sp, #4]
@@ -918,13 +881,12 @@ define i8* @i128_4(i8* %p, i128 %v) {
; CHECK-ARM-NEXT: str r1, [r0, #8]
; CHECK-ARM-NEXT: str r12, [r0, #12]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4
- %q = bitcast i8* %o to i128*
- store i128 %v, i128* %q, align 16
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4
+ store i128 %v, ptr %o, align 16
+ ret ptr %o
}
-define i8* @i128_8(i8* %p, i128 %v) {
+define ptr @i128_8(ptr %p, i128 %v) {
; CHECK-T1-LABEL: i128_8:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, [sp, #4]
@@ -953,13 +915,12 @@ define i8* @i128_8(i8* %p, i128 %v) {
; CHECK-ARM-NEXT: str r1, [r0, #8]
; CHECK-ARM-NEXT: str r12, [r0, #12]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 8
- %q = bitcast i8* %o to i128*
- store i128 %v, i128* %q, align 16
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 8
+ store i128 %v, ptr %o, align 16
+ ret ptr %o
}
-define i8* @i128_16(i8* %p, i128 %v) {
+define ptr @i128_16(ptr %p, i128 %v) {
; CHECK-T1-LABEL: i128_16:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, [sp, #4]
@@ -988,13 +949,12 @@ define i8* @i128_16(i8* %p, i128 %v) {
; CHECK-ARM-NEXT: str r1, [r0, #8]
; CHECK-ARM-NEXT: str r12, [r0, #12]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 16
- %q = bitcast i8* %o to i128*
- store i128 %v, i128* %q, align 16
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 16
+ store i128 %v, ptr %o, align 16
+ ret ptr %o
}
-define i8* @i128_m1(i8* %p, i128 %v) {
+define ptr @i128_m1(ptr %p, i128 %v) {
; CHECK-T1-LABEL: i128_m1:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -1023,13 +983,12 @@ define i8* @i128_m1(i8* %p, i128 %v) {
; CHECK-ARM-NEXT: str r1, [r0, #8]
; CHECK-ARM-NEXT: str r12, [r0, #12]
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -1
- %q = bitcast i8* %o to i128*
- store i128 %v, i128* %q, align 16
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -1
+ store i128 %v, ptr %o, align 16
+ ret ptr %o
}
-define i8* @i128_m4(i8* %p, i128 %v) {
+define ptr @i128_m4(ptr %p, i128 %v) {
; CHECK-T1-LABEL: i128_m4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r1, [sp, #4]
@@ -1057,26 +1016,23 @@ define i8* @i128_m4(i8* %p, i128 %v) {
; CHECK-ARM-NEXT: stmib r0, {r1, r12}
; CHECK-ARM-NEXT: str r2, [r0, #-4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4
- %q = bitcast i8* %o to i128*
- store i128 %v, i128* %q, align 16
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4
+ store i128 %v, ptr %o, align 16
+ ret ptr %o
}
; i16
-define i8* @i16_0(i8* %p, i16 %v) {
+define ptr @i16_0(ptr %p, i16 %v) {
; CHECK-LABEL: i16_0:
; CHECK: @ %bb.0:
; CHECK-NEXT: strh r1, [r0]
; CHECK-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 0
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ store i16 %v, ptr %p, align 2
+ ret ptr %p
}
-define i8* @i16_3(i8* %p, i16 %v) {
+define ptr @i16_3(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_3:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #3
@@ -1093,13 +1049,12 @@ define i8* @i16_3(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #3]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 3
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 3
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_4(i8* %p, i16 %v) {
+define ptr @i16_4(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: strh r1, [r0, #4]
@@ -1115,13 +1070,12 @@ define i8* @i16_4(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_8(i8* %p, i16 %v) {
+define ptr @i16_8(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_8:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: strh r1, [r0, #8]
@@ -1137,13 +1091,12 @@ define i8* @i16_8(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #8]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 8
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 8
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_m1(i8* %p, i16 %v) {
+define ptr @i16_m1(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_m1:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -1159,13 +1112,12 @@ define i8* @i16_m1(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #-1]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -1
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -1
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_m4(i8* %p, i16 %v) {
+define ptr @i16_m4(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_m4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #4
@@ -1181,13 +1133,12 @@ define i8* @i16_m4(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #-4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_252(i8* %p, i16 %v) {
+define ptr @i16_252(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #252
@@ -1204,13 +1155,12 @@ define i8* @i16_252(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #252]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 252
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 252
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_255(i8* %p, i16 %v) {
+define ptr @i16_255(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #255
@@ -1227,13 +1177,12 @@ define i8* @i16_255(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #255]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 255
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 255
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_256(i8* %p, i16 %v) {
+define ptr @i16_256(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #1
@@ -1253,13 +1202,12 @@ define i8* @i16_256(i8* %p, i16 %v) {
; CHECK-ARM-NEXT: mov r2, #256
; CHECK-ARM-NEXT: strh r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 256
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 256
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_m252(i8* %p, i16 %v) {
+define ptr @i16_m252(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_m252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #252
@@ -1275,13 +1223,12 @@ define i8* @i16_m252(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #-252]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -252
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -252
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_m255(i8* %p, i16 %v) {
+define ptr @i16_m255(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_m255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #255
@@ -1297,13 +1244,12 @@ define i8* @i16_m255(i8* %p, i16 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strh r1, [r0, #-255]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -255
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -255
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_m256(i8* %p, i16 %v) {
+define ptr @i16_m256(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_m256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #255
@@ -1324,13 +1270,12 @@ define i8* @i16_m256(i8* %p, i16 %v) {
; CHECK-ARM-NEXT: mvn r2, #255
; CHECK-ARM-NEXT: strh r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -256
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -256
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_4095(i8* %p, i16 %v) {
+define ptr @i16_4095(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI51_0
@@ -1353,13 +1298,12 @@ define i8* @i16_4095(i8* %p, i16 %v) {
; CHECK-ARM-NEXT: movw r2, #4095
; CHECK-ARM-NEXT: strh r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4095
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4095
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_4096(i8* %p, i16 %v) {
+define ptr @i16_4096(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #1
@@ -1380,13 +1324,12 @@ define i8* @i16_4096(i8* %p, i16 %v) {
; CHECK-ARM-NEXT: mov r2, #4096
; CHECK-ARM-NEXT: strh r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4096
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4096
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_m4095(i8* %p, i16 %v) {
+define ptr @i16_m4095(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_m4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI53_0
@@ -1412,13 +1355,12 @@ define i8* @i16_m4095(i8* %p, i16 %v) {
; CHECK-ARM-NEXT: movt r2, #65535
; CHECK-ARM-NEXT: strh r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4095
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4095
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
-define i8* @i16_m4096(i8* %p, i16 %v) {
+define ptr @i16_m4096(ptr %p, i16 %v) {
; CHECK-T1-LABEL: i16_m4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI54_0
@@ -1444,26 +1386,23 @@ define i8* @i16_m4096(i8* %p, i16 %v) {
; CHECK-ARM-NEXT: movt r2, #65535
; CHECK-ARM-NEXT: strh r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4096
- %q = bitcast i8* %o to i16*
- store i16 %v, i16* %q, align 2
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4096
+ store i16 %v, ptr %o, align 2
+ ret ptr %o
}
; i8
-define i8* @i8_0(i8* %p, i8 %v) {
+define ptr @i8_0(ptr %p, i8 %v) {
; CHECK-LABEL: i8_0:
; CHECK: @ %bb.0:
; CHECK-NEXT: strb r1, [r0]
; CHECK-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 0
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ store i8 %v, ptr %p, align 1
+ ret ptr %p
}
-define i8* @i8_3(i8* %p, i8 %v) {
+define ptr @i8_3(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_3:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: strb r1, [r0, #3]
@@ -1479,13 +1418,12 @@ define i8* @i8_3(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #3]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 3
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 3
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_4(i8* %p, i8 %v) {
+define ptr @i8_4(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: strb r1, [r0, #4]
@@ -1501,13 +1439,12 @@ define i8* @i8_4(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_8(i8* %p, i8 %v) {
+define ptr @i8_8(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_8:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: strb r1, [r0, #8]
@@ -1523,13 +1460,12 @@ define i8* @i8_8(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #8]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 8
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 8
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_m1(i8* %p, i8 %v) {
+define ptr @i8_m1(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_m1:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #1
@@ -1545,13 +1481,12 @@ define i8* @i8_m1(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #-1]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -1
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -1
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_m4(i8* %p, i8 %v) {
+define ptr @i8_m4(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_m4:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, #4
@@ -1567,13 +1502,12 @@ define i8* @i8_m4(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #-4]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_252(i8* %p, i8 %v) {
+define ptr @i8_252(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #252
@@ -1590,13 +1524,12 @@ define i8* @i8_252(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #252]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 252
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 252
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_255(i8* %p, i8 %v) {
+define ptr @i8_255(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #255
@@ -1613,13 +1546,12 @@ define i8* @i8_255(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #255]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 255
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 255
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_256(i8* %p, i8 %v) {
+define ptr @i8_256(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #1
@@ -1638,13 +1570,12 @@ define i8* @i8_256(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #256]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 256
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 256
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_m252(i8* %p, i8 %v) {
+define ptr @i8_m252(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_m252:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #252
@@ -1660,13 +1591,12 @@ define i8* @i8_m252(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #-252]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -252
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -252
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_m255(i8* %p, i8 %v) {
+define ptr @i8_m255(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_m255:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, #255
@@ -1682,13 +1612,12 @@ define i8* @i8_m255(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #-255]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -255
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -255
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_m256(i8* %p, i8 %v) {
+define ptr @i8_m256(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_m256:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #255
@@ -1708,13 +1637,12 @@ define i8* @i8_m256(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #-256]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -256
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -256
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_4095(i8* %p, i8 %v) {
+define ptr @i8_4095(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI67_0
@@ -1736,13 +1664,12 @@ define i8* @i8_4095(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #4095]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4095
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4095
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_4096(i8* %p, i8 %v) {
+define ptr @i8_4096(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: movs r2, #1
@@ -1763,13 +1690,12 @@ define i8* @i8_4096(i8* %p, i8 %v) {
; CHECK-ARM-NEXT: mov r2, #4096
; CHECK-ARM-NEXT: strb r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 4096
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 4096
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_m4095(i8* %p, i8 %v) {
+define ptr @i8_m4095(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_m4095:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI69_0
@@ -1793,13 +1719,12 @@ define i8* @i8_m4095(i8* %p, i8 %v) {
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: strb r1, [r0, #-4095]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4095
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4095
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
-define i8* @i8_m4096(i8* %p, i8 %v) {
+define ptr @i8_m4096(ptr %p, i8 %v) {
; CHECK-T1-LABEL: i8_m4096:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: ldr r2, .LCPI70_0
@@ -1825,8 +1750,7 @@ define i8* @i8_m4096(i8* %p, i8 %v) {
; CHECK-ARM-NEXT: movt r2, #65535
; CHECK-ARM-NEXT: strb r1, [r0, r2]!
; CHECK-ARM-NEXT: bx lr
- %o = getelementptr inbounds i8, i8* %p, i32 -4096
- %q = bitcast i8* %o to i8*
- store i8 %v, i8* %q, align 1
- ret i8* %o
+ %o = getelementptr inbounds i8, ptr %p, i32 -4096
+ store i8 %v, ptr %o, align 1
+ ret ptr %o
}
diff --git a/llvm/test/CodeGen/ARM/store_half.ll b/llvm/test/CodeGen/ARM/store_half.ll
index c182f9c3f7664..70efbb5d7e060 100644
--- a/llvm/test/CodeGen/ARM/store_half.ll
+++ b/llvm/test/CodeGen/ARM/store_half.ll
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=armebv8.2a-arm-none-eabi -mattr=+fullfp16 -filetype=obj -o /dev/null
; RUN: llc < %s -mtriple=armv8.2a-arm-none-eabi -mattr=+fullfp16 -filetype=obj -o /dev/null
-define void @woah(half* %waythere) {
- store half 0xHE110, half* %waythere
+define void @woah(ptr %waythere) {
+ store half 0xHE110, ptr %waythere
ret void
}
diff --git a/llvm/test/CodeGen/ARM/str_post.ll b/llvm/test/CodeGen/ARM/str_post.ll
index 0933e15dab4e5..892fe24b87613 100644
--- a/llvm/test/CodeGen/ARM/str_post.ll
+++ b/llvm/test/CodeGen/ARM/str_post.ll
@@ -1,22 +1,22 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
-define i16 @test1(i32* %X, i16* %A) {
+define i16 @test1(ptr %X, ptr %A) {
; CHECK-LABEL: test1:
; CHECK: strh {{.*}}[{{.*}}], #-4
- %Y = load i32, i32* %X ; <i32> [#uses=1]
+ %Y = load i32, ptr %X ; <i32> [#uses=1]
%tmp1 = trunc i32 %Y to i16 ; <i16> [#uses=1]
- store i16 %tmp1, i16* %A
- %tmp2 = ptrtoint i16* %A to i16 ; <i16> [#uses=1]
+ store i16 %tmp1, ptr %A
+ %tmp2 = ptrtoint ptr %A to i16 ; <i16> [#uses=1]
%tmp3 = sub i16 %tmp2, 4 ; <i16> [#uses=1]
ret i16 %tmp3
}
-define i32 @test2(i32* %X, i32* %A) {
+define i32 @test2(ptr %X, ptr %A) {
; CHECK-LABEL: test2:
; CHECK: str {{.*}}[{{.*}}],
- %Y = load i32, i32* %X ; <i32> [#uses=1]
- store i32 %Y, i32* %A
- %tmp1 = ptrtoint i32* %A to i32 ; <i32> [#uses=1]
+ %Y = load i32, ptr %X ; <i32> [#uses=1]
+ store i32 %Y, ptr %A
+ %tmp1 = ptrtoint ptr %A to i32 ; <i32> [#uses=1]
%tmp2 = sub i32 %tmp1, 4 ; <i32> [#uses=1]
ret i32 %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/str_pre-2.ll b/llvm/test/CodeGen/ARM/str_pre-2.ll
index 1c6c05de2579d..52f227d1153a5 100644
--- a/llvm/test/CodeGen/ARM/str_pre-2.ll
+++ b/llvm/test/CodeGen/ARM/str_pre-2.ll
@@ -1,14 +1,14 @@
; RUN: llc < %s -mtriple=armv6-linux-gnu -target-abi=apcs | FileCheck %s
- at b = external global i64*
+ at b = external global ptr
define i64 @t(i64 %a) nounwind readonly {
entry:
; CHECK: push {r4, r5, lr}
; CHECK: pop {r4, r5, pc}
call void asm sideeffect "", "~{r4},~{r5}"() nounwind
- %0 = load i64*, i64** @b, align 4
- %1 = load i64, i64* %0, align 4
+ %0 = load ptr, ptr @b, align 4
+ %1 = load i64, ptr %0, align 4
%2 = mul i64 %1, %a
ret i64 %2
}
diff --git a/llvm/test/CodeGen/ARM/str_pre.ll b/llvm/test/CodeGen/ARM/str_pre.ll
index 848261f83e31b..fede891aad2b5 100644
--- a/llvm/test/CodeGen/ARM/str_pre.ll
+++ b/llvm/test/CodeGen/ARM/str_pre.ll
@@ -1,19 +1,19 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
-define void @test1(i32* %X, i32* %A, i32** %dest) {
- %B = load i32, i32* %A ; <i32> [#uses=1]
- %Y = getelementptr i32, i32* %X, i32 4 ; <i32*> [#uses=2]
- store i32 %B, i32* %Y
- store i32* %Y, i32** %dest
+define void @test1(ptr %X, ptr %A, ptr %dest) {
+ %B = load i32, ptr %A ; <i32> [#uses=1]
+ %Y = getelementptr i32, ptr %X, i32 4 ; <ptr> [#uses=2]
+ store i32 %B, ptr %Y
+ store ptr %Y, ptr %dest
ret void
}
-define i16* @test2(i16* %X, i32* %A) {
- %B = load i32, i32* %A ; <i32> [#uses=1]
- %Y = getelementptr i16, i16* %X, i32 4 ; <i16*> [#uses=2]
+define ptr @test2(ptr %X, ptr %A) {
+ %B = load i32, ptr %A ; <i32> [#uses=1]
+ %Y = getelementptr i16, ptr %X, i32 4 ; <ptr> [#uses=2]
%tmp = trunc i32 %B to i16 ; <i16> [#uses=1]
- store i16 %tmp, i16* %Y
- ret i16* %Y
+ store i16 %tmp, ptr %Y
+ ret ptr %Y
}
; CHECK: str{{.*}}!
diff --git a/llvm/test/CodeGen/ARM/str_trunc.ll b/llvm/test/CodeGen/ARM/str_trunc.ll
index 6739684d53bf5..97e3b00f5cda3 100644
--- a/llvm/test/CodeGen/ARM/str_trunc.ll
+++ b/llvm/test/CodeGen/ARM/str_trunc.ll
@@ -1,14 +1,14 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
-define void @test1(i32 %v, i16* %ptr) {
+define void @test1(i32 %v, ptr %ptr) {
%tmp = trunc i32 %v to i16 ; <i16> [#uses=1]
- store i16 %tmp, i16* %ptr
+ store i16 %tmp, ptr %ptr
ret void
}
-define void @test2(i32 %v, i8* %ptr) {
+define void @test2(i32 %v, ptr %ptr) {
%tmp = trunc i32 %v to i8 ; <i8> [#uses=1]
- store i8 %tmp, i8* %ptr
+ store i8 %tmp, ptr %ptr
ret void
}
diff --git a/llvm/test/CodeGen/ARM/struct-byval-frame-index.ll b/llvm/test/CodeGen/ARM/struct-byval-frame-index.ll
index c398e362b1c31..24df0d3e56d1c 100644
--- a/llvm/test/CodeGen/ARM/struct-byval-frame-index.ll
+++ b/llvm/test/CodeGen/ARM/struct-byval-frame-index.ll
@@ -22,17 +22,16 @@ target triple = "armv7l-unknown-linux-gnueabihf"
; Function Attrs: nounwind
define void @set_stored_macroblock_parameters(i16 %a0, i32 %a1) #1 {
entry:
- %0 = load i32, i32* @luma_transform_size_8x8_flag, align 4
+ %0 = load i32, ptr @luma_transform_size_8x8_flag, align 4
tail call void asm sideeffect "", "~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11}"()
- tail call void @RestoreMVBlock8x8(i32 1, i32 2, %structN* byval(%structN) @tr8x8, i32 0)
- %arrayidx313 = getelementptr inbounds i8*, i8** null, i32 %0
- %1 = load i8*, i8** %arrayidx313, align 4
- %arrayidx314 = getelementptr inbounds i8, i8* %1, i32 0
- store i8 -1, i8* %arrayidx314, align 1
+ tail call void @RestoreMVBlock8x8(i32 1, i32 2, ptr byval(%structN) @tr8x8, i32 0)
+ %arrayidx313 = getelementptr inbounds ptr, ptr null, i32 %0
+ %1 = load ptr, ptr %arrayidx313, align 4
+ store i8 -1, ptr %1, align 1
ret void
}
; Function Attrs: nounwind
-declare void @RestoreMVBlock8x8(i32, i32, %structN* byval(%structN) nocapture, i32) #1
+declare void @RestoreMVBlock8x8(i32, i32, ptr byval(%structN) nocapture, i32) #1
attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/CodeGen/ARM/struct_byval.ll b/llvm/test/CodeGen/ARM/struct_byval.ll
index 6d3c7121fac77..73a1b5ee33bca 100644
--- a/llvm/test/CodeGen/ARM/struct_byval.ll
+++ b/llvm/test/CodeGen/ARM/struct_byval.ll
@@ -16,7 +16,7 @@ entry:
; CHECK: str
; CHECK-NOT:bne
%st = alloca %struct.SmallStruct, align 4
- %call = call i32 @e1(%struct.SmallStruct* byval(%struct.SmallStruct) %st)
+ %call = call i32 @e1(ptr byval(%struct.SmallStruct) %st)
ret i32 0
}
@@ -37,7 +37,7 @@ entry:
; NACL: str
; NACL: bne
%st = alloca %struct.LargeStruct, align 4
- %call = call i32 @e2(%struct.LargeStruct* byval(%struct.LargeStruct) %st)
+ %call = call i32 @e2(ptr byval(%struct.LargeStruct) %st)
ret i32 0
}
@@ -55,67 +55,61 @@ entry:
; NACL: vst1
; NACL: bne
%st = alloca %struct.LargeStruct, align 16
- %call = call i32 @e3(%struct.LargeStruct* byval(%struct.LargeStruct) align 16 %st)
+ %call = call i32 @e3(ptr byval(%struct.LargeStruct) align 16 %st)
ret i32 0
}
-declare i32 @e1(%struct.SmallStruct* nocapture byval(%struct.SmallStruct) %in) nounwind
-declare i32 @e2(%struct.LargeStruct* nocapture byval(%struct.LargeStruct) %in) nounwind
-declare i32 @e3(%struct.LargeStruct* nocapture byval(%struct.LargeStruct) align 16 %in) nounwind
+declare i32 @e1(ptr nocapture byval(%struct.SmallStruct) %in) nounwind
+declare i32 @e2(ptr nocapture byval(%struct.LargeStruct) %in) nounwind
+declare i32 @e3(ptr nocapture byval(%struct.LargeStruct) align 16 %in) nounwind
; rdar://12442472
; We can't do tail call since address of s is passed to the callee and part of
; s is in caller's local frame.
-define void @f3(%struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize {
+define void @f3(ptr nocapture byval(%struct.SmallStruct) %s) nounwind optsize {
; CHECK-LABEL: f3
; CHECK: bl _consumestruct
entry:
- %0 = bitcast %struct.SmallStruct* %s to i8*
- tail call void @consumestruct(i8* %0, i32 80) optsize
+ tail call void @consumestruct(ptr %s, i32 80) optsize
ret void
}
-define void @f4(%struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize {
+define void @f4(ptr nocapture byval(%struct.SmallStruct) %s) nounwind optsize {
; CHECK-LABEL: f4
; CHECK: bl _consumestruct
entry:
- %addr = getelementptr inbounds %struct.SmallStruct, %struct.SmallStruct* %s, i32 0, i32 0
- %0 = bitcast i32* %addr to i8*
- tail call void @consumestruct(i8* %0, i32 80) optsize
+ tail call void @consumestruct(ptr %s, i32 80) optsize
ret void
}
; We can do tail call here since s is in the incoming argument area.
-define void @f5(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize {
+define void @f5(i32 %a, i32 %b, i32 %c, i32 %d, ptr nocapture byval(%struct.SmallStruct) %s) nounwind optsize {
; CHECK-LABEL: f5
; CHECK: b{{(\.w)?}} _consumestruct
entry:
- %0 = bitcast %struct.SmallStruct* %s to i8*
- tail call void @consumestruct(i8* %0, i32 80) optsize
+ tail call void @consumestruct(ptr %s, i32 80) optsize
ret void
}
-define void @f6(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize {
+define void @f6(i32 %a, i32 %b, i32 %c, i32 %d, ptr nocapture byval(%struct.SmallStruct) %s) nounwind optsize {
; CHECK-LABEL: f6
; CHECK: b{{(\.w)?}} _consumestruct
entry:
- %addr = getelementptr inbounds %struct.SmallStruct, %struct.SmallStruct* %s, i32 0, i32 0
- %0 = bitcast i32* %addr to i8*
- tail call void @consumestruct(i8* %0, i32 80) optsize
+ tail call void @consumestruct(ptr %s, i32 80) optsize
ret void
}
-declare void @consumestruct(i8* nocapture %structp, i32 %structsize) nounwind
+declare void @consumestruct(ptr nocapture %structp, i32 %structsize) nounwind
; PR17309
%struct.I.8 = type { [10 x i32], [3 x i8] }
-declare void @use_I(%struct.I.8* byval(%struct.I.8))
+declare void @use_I(ptr byval(%struct.I.8))
define void @test_I_16() {
; CHECK-LABEL: test_I_16
; CHECK: ldrb
; CHECK: strb
entry:
- call void @use_I(%struct.I.8* byval(%struct.I.8) align 16 undef)
+ call void @use_I(ptr byval(%struct.I.8) align 16 undef)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll b/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
index e3d64547ca5e4..34cc2da16a809 100644
--- a/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
+++ b/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
@@ -25,33 +25,33 @@
;cleanup if the number of bytes does not divide evenly by the store size
%struct.A = type <{ [ 10 x i32 ] }> ; 40 bytes
-declare void @use_A(%struct.A* byval(%struct.A))
+declare void @use_A(ptr byval(%struct.A))
%struct.B = type <{ [ 10 x i32 ], i8 }> ; 41 bytes
-declare void @use_B(%struct.B* byval(%struct.B))
+declare void @use_B(ptr byval(%struct.B))
%struct.C = type <{ [ 10 x i32 ], [ 3 x i8 ] }> ; 43 bytes
-declare void @use_C(%struct.C* byval(%struct.C))
+declare void @use_C(ptr byval(%struct.C))
%struct.D = type <{ [ 100 x i32 ] }> ; 400 bytes
-declare void @use_D(%struct.D* byval(%struct.D))
+declare void @use_D(ptr byval(%struct.D))
%struct.E = type <{ [ 100 x i32 ], i8 }> ; 401 bytes
-declare void @use_E(%struct.E* byval(%struct.E))
+declare void @use_E(ptr byval(%struct.E))
%struct.F = type <{ [ 100 x i32 ], [ 3 x i8 ] }> ; 403 bytes
-declare void @use_F(%struct.F* byval(%struct.F))
+declare void @use_F(ptr byval(%struct.F))
%struct.G = type { [ 10 x i32 ] } ; 40 bytes
-declare void @use_G(%struct.G* byval(%struct.G))
+declare void @use_G(ptr byval(%struct.G))
%struct.H = type { [ 10 x i32 ], i8 } ; 41 bytes
-declare void @use_H(%struct.H* byval(%struct.H))
+declare void @use_H(ptr byval(%struct.H))
%struct.I = type { [ 10 x i32 ], [ 3 x i8 ] } ; 43 bytes
-declare void @use_I(%struct.I* byval(%struct.I))
+declare void @use_I(ptr byval(%struct.I))
%struct.J = type { [ 100 x i32 ] } ; 400 bytes
-declare void @use_J(%struct.J* byval(%struct.J))
+declare void @use_J(ptr byval(%struct.J))
%struct.K = type { [ 100 x i32 ], i8 } ; 401 bytes
-declare void @use_K(%struct.K* byval(%struct.K))
+declare void @use_K(ptr byval(%struct.K))
%struct.L = type { [ 100 x i32 ], [ 3 x i8 ] } ; 403 bytes
-declare void @use_L(%struct.L* byval(%struct.L))
+declare void @use_L(ptr byval(%struct.L))
%struct.M = type { [ 64 x i8 ] } ; 64 bytes
-declare void @use_M(%struct.M* byval(%struct.M))
+declare void @use_M(ptr byval(%struct.M))
%struct.N = type { [ 128 x i8 ] } ; 128 bytes
-declare void @use_N(%struct.N* byval(%struct.N))
+declare void @use_N(ptr byval(%struct.N))
;ARM-LABEL: <test_A_1>:
;THUMB2-LABEL: <test_A_1>:
@@ -71,7 +71,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.A, align 1
- call void @use_A(%struct.A* byval(%struct.A) align 1 %a)
+ call void @use_A(ptr byval(%struct.A) align 1 %a)
ret void
}
;ARM-LABEL: <test_A_2>:
@@ -92,7 +92,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.A, align 2
- call void @use_A(%struct.A* byval(%struct.A) align 2 %a)
+ call void @use_A(ptr byval(%struct.A) align 2 %a)
ret void
}
;ARM-LABEL: <test_A_4>:
@@ -113,7 +113,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.A, align 4
- call void @use_A(%struct.A* byval(%struct.A) align 4 %a)
+ call void @use_A(ptr byval(%struct.A) align 4 %a)
ret void
}
;ARM-LABEL: <test_A_8>:
@@ -135,7 +135,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.A, align 8
- call void @use_A(%struct.A* byval(%struct.A) align 8 %a)
+ call void @use_A(ptr byval(%struct.A) align 8 %a)
ret void
}
;ARM-LABEL: <test_A_16>:
@@ -159,7 +159,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.A, align 16
- call void @use_A(%struct.A* byval(%struct.A) align 16 %a)
+ call void @use_A(ptr byval(%struct.A) align 16 %a)
ret void
}
;ARM-LABEL: <test_B_1>:
@@ -180,7 +180,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.B, align 1
- call void @use_B(%struct.B* byval(%struct.B) align 1 %a)
+ call void @use_B(ptr byval(%struct.B) align 1 %a)
ret void
}
;ARM-LABEL: <test_B_2>:
@@ -205,7 +205,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.B, align 2
- call void @use_B(%struct.B* byval(%struct.B) align 2 %a)
+ call void @use_B(ptr byval(%struct.B) align 2 %a)
ret void
}
;ARM-LABEL: <test_B_4>:
@@ -230,7 +230,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.B, align 4
- call void @use_B(%struct.B* byval(%struct.B) align 4 %a)
+ call void @use_B(ptr byval(%struct.B) align 4 %a)
ret void
}
;ARM-LABEL: <test_B_8>:
@@ -256,7 +256,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.B, align 8
- call void @use_B(%struct.B* byval(%struct.B) align 8 %a)
+ call void @use_B(ptr byval(%struct.B) align 8 %a)
ret void
}
;ARM-LABEL: <test_B_16>:
@@ -282,7 +282,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.B, align 16
- call void @use_B(%struct.B* byval(%struct.B) align 16 %a)
+ call void @use_B(ptr byval(%struct.B) align 16 %a)
ret void
}
;ARM-LABEL: <test_C_1>:
@@ -303,7 +303,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.C, align 1
- call void @use_C(%struct.C* byval(%struct.C) align 1 %a)
+ call void @use_C(ptr byval(%struct.C) align 1 %a)
ret void
}
;ARM-LABEL: <test_C_2>:
@@ -328,7 +328,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.C, align 2
- call void @use_C(%struct.C* byval(%struct.C) align 2 %a)
+ call void @use_C(ptr byval(%struct.C) align 2 %a)
ret void
}
;ARM-LABEL: <test_C_4>:
@@ -354,7 +354,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.C, align 4
- call void @use_C(%struct.C* byval(%struct.C) align 4 %a)
+ call void @use_C(ptr byval(%struct.C) align 4 %a)
ret void
}
;ARM-LABEL: <test_C_8>:
@@ -381,7 +381,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.C, align 8
- call void @use_C(%struct.C* byval(%struct.C) align 8 %a)
+ call void @use_C(ptr byval(%struct.C) align 8 %a)
ret void
}
;ARM-LABEL: <test_C_16>:
@@ -408,7 +408,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.C, align 16
- call void @use_C(%struct.C* byval(%struct.C) align 16 %a)
+ call void @use_C(ptr byval(%struct.C) align 16 %a)
ret void
}
;ARM-LABEL: <test_D_1>:
@@ -433,7 +433,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.D, align 1
- call void @use_D(%struct.D* byval(%struct.D) align 1 %a)
+ call void @use_D(ptr byval(%struct.D) align 1 %a)
ret void
}
;ARM-LABEL: <test_D_2>:
@@ -458,7 +458,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.D, align 2
- call void @use_D(%struct.D* byval(%struct.D) align 2 %a)
+ call void @use_D(ptr byval(%struct.D) align 2 %a)
ret void
}
;ARM-LABEL: <test_D_4>:
@@ -483,7 +483,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.D, align 4
- call void @use_D(%struct.D* byval(%struct.D) align 4 %a)
+ call void @use_D(ptr byval(%struct.D) align 4 %a)
ret void
}
;ARM-LABEL: <test_D_8>:
@@ -509,7 +509,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.D, align 8
- call void @use_D(%struct.D* byval(%struct.D) align 8 %a)
+ call void @use_D(ptr byval(%struct.D) align 8 %a)
ret void
}
;ARM-LABEL: <test_D_16>:
@@ -535,7 +535,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.D, align 16
- call void @use_D(%struct.D* byval(%struct.D) align 16 %a)
+ call void @use_D(ptr byval(%struct.D) align 16 %a)
ret void
}
;ARM-LABEL: <test_E_1>:
@@ -560,7 +560,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.E, align 1
- call void @use_E(%struct.E* byval(%struct.E) align 1 %a)
+ call void @use_E(ptr byval(%struct.E) align 1 %a)
ret void
}
;ARM-LABEL: <test_E_2>:
@@ -589,7 +589,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.E, align 2
- call void @use_E(%struct.E* byval(%struct.E) align 2 %a)
+ call void @use_E(ptr byval(%struct.E) align 2 %a)
ret void
}
;ARM-LABEL: <test_E_4>:
@@ -618,7 +618,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.E, align 4
- call void @use_E(%struct.E* byval(%struct.E) align 4 %a)
+ call void @use_E(ptr byval(%struct.E) align 4 %a)
ret void
}
;ARM-LABEL: <test_E_8>:
@@ -648,7 +648,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.E, align 8
- call void @use_E(%struct.E* byval(%struct.E) align 8 %a)
+ call void @use_E(ptr byval(%struct.E) align 8 %a)
ret void
}
;ARM-LABEL: <test_E_16>:
@@ -678,7 +678,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.E, align 16
- call void @use_E(%struct.E* byval(%struct.E) align 16 %a)
+ call void @use_E(ptr byval(%struct.E) align 16 %a)
ret void
}
;ARM-LABEL: <test_F_1>:
@@ -703,7 +703,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.F, align 1
- call void @use_F(%struct.F* byval(%struct.F) align 1 %a)
+ call void @use_F(ptr byval(%struct.F) align 1 %a)
ret void
}
;ARM-LABEL: <test_F_2>:
@@ -732,7 +732,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.F, align 2
- call void @use_F(%struct.F* byval(%struct.F) align 2 %a)
+ call void @use_F(ptr byval(%struct.F) align 2 %a)
ret void
}
;ARM-LABEL: <test_F_4>:
@@ -762,7 +762,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.F, align 4
- call void @use_F(%struct.F* byval(%struct.F) align 4 %a)
+ call void @use_F(ptr byval(%struct.F) align 4 %a)
ret void
}
;ARM-LABEL: <test_F_8>:
@@ -793,7 +793,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.F, align 8
- call void @use_F(%struct.F* byval(%struct.F) align 8 %a)
+ call void @use_F(ptr byval(%struct.F) align 8 %a)
ret void
}
;ARM-LABEL: <test_F_16>:
@@ -824,7 +824,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.F, align 16
- call void @use_F(%struct.F* byval(%struct.F) align 16 %a)
+ call void @use_F(ptr byval(%struct.F) align 16 %a)
ret void
}
;ARM-LABEL: <test_G_1>:
@@ -845,7 +845,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.G, align 1
- call void @use_G(%struct.G* byval(%struct.G) align 1 %a)
+ call void @use_G(ptr byval(%struct.G) align 1 %a)
ret void
}
;ARM-LABEL: <test_G_2>:
@@ -866,7 +866,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.G, align 2
- call void @use_G(%struct.G* byval(%struct.G) align 2 %a)
+ call void @use_G(ptr byval(%struct.G) align 2 %a)
ret void
}
;ARM-LABEL: <test_G_4>:
@@ -887,7 +887,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.G, align 4
- call void @use_G(%struct.G* byval(%struct.G) align 4 %a)
+ call void @use_G(ptr byval(%struct.G) align 4 %a)
ret void
}
;ARM-LABEL: <test_G_8>:
@@ -909,7 +909,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.G, align 8
- call void @use_G(%struct.G* byval(%struct.G) align 8 %a)
+ call void @use_G(ptr byval(%struct.G) align 8 %a)
ret void
}
;ARM-LABEL: <test_G_16>:
@@ -931,7 +931,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.G, align 16
- call void @use_G(%struct.G* byval(%struct.G) align 16 %a)
+ call void @use_G(ptr byval(%struct.G) align 16 %a)
ret void
}
;ARM-LABEL: <test_H_1>:
@@ -952,7 +952,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.H, align 1
- call void @use_H(%struct.H* byval(%struct.H) align 1 %a)
+ call void @use_H(ptr byval(%struct.H) align 1 %a)
ret void
}
;ARM-LABEL: <test_H_2>:
@@ -973,7 +973,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.H, align 2
- call void @use_H(%struct.H* byval(%struct.H) align 2 %a)
+ call void @use_H(ptr byval(%struct.H) align 2 %a)
ret void
}
;ARM-LABEL: <test_H_4>:
@@ -994,7 +994,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.H, align 4
- call void @use_H(%struct.H* byval(%struct.H) align 4 %a)
+ call void @use_H(ptr byval(%struct.H) align 4 %a)
ret void
}
;ARM-LABEL: <test_H_8>:
@@ -1016,7 +1016,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.H, align 8
- call void @use_H(%struct.H* byval(%struct.H) align 8 %a)
+ call void @use_H(ptr byval(%struct.H) align 8 %a)
ret void
}
;ARM-LABEL: <test_H_16>:
@@ -1038,7 +1038,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.H, align 16
- call void @use_H(%struct.H* byval(%struct.H) align 16 %a)
+ call void @use_H(ptr byval(%struct.H) align 16 %a)
ret void
}
;ARM-LABEL: <test_I_1>:
@@ -1059,7 +1059,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.I, align 1
- call void @use_I(%struct.I* byval(%struct.I) align 1 %a)
+ call void @use_I(ptr byval(%struct.I) align 1 %a)
ret void
}
;ARM-LABEL: <test_I_2>:
@@ -1080,7 +1080,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.I, align 2
- call void @use_I(%struct.I* byval(%struct.I) align 2 %a)
+ call void @use_I(ptr byval(%struct.I) align 2 %a)
ret void
}
;ARM-LABEL: <test_I_4>:
@@ -1101,7 +1101,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.I, align 4
- call void @use_I(%struct.I* byval(%struct.I) align 4 %a)
+ call void @use_I(ptr byval(%struct.I) align 4 %a)
ret void
}
;ARM-LABEL: <test_I_8>:
@@ -1123,7 +1123,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.I, align 8
- call void @use_I(%struct.I* byval(%struct.I) align 8 %a)
+ call void @use_I(ptr byval(%struct.I) align 8 %a)
ret void
}
;ARM-LABEL: <test_I_16>:
@@ -1145,7 +1145,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.I, align 16
- call void @use_I(%struct.I* byval(%struct.I) align 16 %a)
+ call void @use_I(ptr byval(%struct.I) align 16 %a)
ret void
}
;ARM-LABEL: <test_J_1>:
@@ -1170,7 +1170,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.J, align 1
- call void @use_J(%struct.J* byval(%struct.J) align 1 %a)
+ call void @use_J(ptr byval(%struct.J) align 1 %a)
ret void
}
;ARM-LABEL: <test_J_2>:
@@ -1195,7 +1195,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.J, align 2
- call void @use_J(%struct.J* byval(%struct.J) align 2 %a)
+ call void @use_J(ptr byval(%struct.J) align 2 %a)
ret void
}
;ARM-LABEL: <test_J_4>:
@@ -1220,7 +1220,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.J, align 4
- call void @use_J(%struct.J* byval(%struct.J) align 4 %a)
+ call void @use_J(ptr byval(%struct.J) align 4 %a)
ret void
}
;ARM-LABEL: <test_J_8>:
@@ -1246,7 +1246,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.J, align 8
- call void @use_J(%struct.J* byval(%struct.J) align 8 %a)
+ call void @use_J(ptr byval(%struct.J) align 8 %a)
ret void
}
;ARM-LABEL: <test_J_16>:
@@ -1272,7 +1272,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.J, align 16
- call void @use_J(%struct.J* byval(%struct.J) align 16 %a)
+ call void @use_J(ptr byval(%struct.J) align 16 %a)
ret void
}
;ARM-LABEL: <test_K_1>:
@@ -1297,7 +1297,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.K, align 1
- call void @use_K(%struct.K* byval(%struct.K) align 1 %a)
+ call void @use_K(ptr byval(%struct.K) align 1 %a)
ret void
}
;ARM-LABEL: <test_K_2>:
@@ -1322,7 +1322,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.K, align 2
- call void @use_K(%struct.K* byval(%struct.K) align 2 %a)
+ call void @use_K(ptr byval(%struct.K) align 2 %a)
ret void
}
;ARM-LABEL: <test_K_4>:
@@ -1347,7 +1347,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.K, align 4
- call void @use_K(%struct.K* byval(%struct.K) align 4 %a)
+ call void @use_K(ptr byval(%struct.K) align 4 %a)
ret void
}
;ARM-LABEL: <test_K_8>:
@@ -1373,7 +1373,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.K, align 8
- call void @use_K(%struct.K* byval(%struct.K) align 8 %a)
+ call void @use_K(ptr byval(%struct.K) align 8 %a)
ret void
}
;ARM-LABEL: <test_K_16>:
@@ -1399,7 +1399,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.K, align 16
- call void @use_K(%struct.K* byval(%struct.K) align 16 %a)
+ call void @use_K(ptr byval(%struct.K) align 16 %a)
ret void
}
;ARM-LABEL: <test_L_1>:
@@ -1424,7 +1424,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
entry:
%a = alloca %struct.L, align 1
- call void @use_L(%struct.L* byval(%struct.L) align 1 %a)
+ call void @use_L(ptr byval(%struct.L) align 1 %a)
ret void
}
;ARM-LABEL: <test_L_2>:
@@ -1449,7 +1449,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
entry:
%a = alloca %struct.L, align 2
- call void @use_L(%struct.L* byval(%struct.L) align 2 %a)
+ call void @use_L(ptr byval(%struct.L) align 2 %a)
ret void
}
;ARM-LABEL: <test_L_4>:
@@ -1474,7 +1474,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4
entry:
%a = alloca %struct.L, align 4
- call void @use_L(%struct.L* byval(%struct.L) align 4 %a)
+ call void @use_L(ptr byval(%struct.L) align 4 %a)
ret void
}
;ARM-LABEL: <test_L_8>:
@@ -1500,7 +1500,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.L, align 8
- call void @use_L(%struct.L* byval(%struct.L) align 8 %a)
+ call void @use_L(ptr byval(%struct.L) align 8 %a)
ret void
}
;ARM-LABEL: <test_L_16>:
@@ -1526,7 +1526,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]!
entry:
%a = alloca %struct.L, align 16
- call void @use_L(%struct.L* byval(%struct.L) align 16 %a)
+ call void @use_L(ptr byval(%struct.L) align 16 %a)
ret void
}
;V8MBASE-LABEL: <test_M>:
@@ -1537,7 +1537,7 @@ declare void @use_N(%struct.N* byval(%struct.N))
;V8MBASE-NOT: movw
entry:
%a = alloca %struct.M, align 1
- call void @use_M(%struct.M* byval(%struct.M) align 1 %a)
+ call void @use_M(ptr byval(%struct.M) align 1 %a)
ret void
}
;V8MBASE-LABEL: <test_N>:
@@ -1547,6 +1547,6 @@ declare void @use_N(%struct.N* byval(%struct.N))
;V8MBASE-NOT: b #{{[0-9]+}}
entry:
%a = alloca %struct.N, align 1
- call void @use_N(%struct.N* byval(%struct.N) align 1 %a)
+ call void @use_N(ptr byval(%struct.N) align 1 %a)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll b/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
index ef907ee3ff499..7e3b8b24424ad 100644
--- a/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
+++ b/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
@@ -137,7 +137,7 @@ entry:
; V8: vsel
%cmp = icmp sgt i32 %a, %b
%sub = sub i32 %a, %b
- store i32 %sub, i32* @t
+ store i32 %sub, ptr @t
%ret = select i1 %cmp, double %x, double %y
ret double %ret
}
@@ -154,7 +154,7 @@ entry:
%cmp = icmp sgt i32 %a, %b
%sub = sub i32 %b, %a
%ret = select i1 %cmp, double %x, double %y
- store i32 %sub, i32* @t
+ store i32 %sub, ptr @t
ret double %ret
}
@@ -169,7 +169,7 @@ entry:
; CHECK: sub
; CHECK: cmn
; CHECK: ble
- %load = load i32, i32* @t, align 4
+ %load = load i32, ptr @t, align 4
%sub = sub i32 %load, 17
%cmp = icmp slt i32 %sub, 0
br i1 %cmp, label %if.then, label %if.else
@@ -191,7 +191,7 @@ entry:
; CHECK: sub
; CHECK: cmp
; CHECK: bhs
- %load = load i32, i32* @t, align 4
+ %load = load i32, ptr @t, align 4
%sub = sub i32 %load, 17
%cmp = icmp ult i32 %sub, 0
br i1 %cmp, label %if.then, label %if.else
diff --git a/llvm/test/CodeGen/ARM/sub-from-const-hoisting.ll b/llvm/test/CodeGen/ARM/sub-from-const-hoisting.ll
index bcdc507eae6b5..8c602d735cdd3 100644
--- a/llvm/test/CodeGen/ARM/sub-from-const-hoisting.ll
+++ b/llvm/test/CodeGen/ARM/sub-from-const-hoisting.ll
@@ -41,15 +41,15 @@ define dso_local i32 @c() local_unnamed_addr #0 {
; CHECK-NEXT: .LCPI0_2:
; CHECK-NEXT: .long b
entry:
- %0 = load i32, i32* @a, align 4
+ %0 = load i32, ptr @a, align 4
%sub = sub nsw i32 2000, %0
- %call = tail call i32 bitcast (i32 (...)* @d to i32 (i32)*)(i32 %sub) #2
- %1 = load i32, i32* @b, align 4
+ %call = tail call i32 @d(i32 %sub) #2
+ %1 = load i32, ptr @b, align 4
%cmp = icmp sgt i32 %1, 1999
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
- %call1 = tail call i32 bitcast (i32 (...)* @e to i32 ()*)() #2
+ %call1 = tail call i32 @e() #2
br label %if.end
if.end: ; preds = %if.then, %entry
diff --git a/llvm/test/CodeGen/ARM/subreg-remat.ll b/llvm/test/CodeGen/ARM/subreg-remat.ll
index 6166a947fad8f..a5e84a022806f 100644
--- a/llvm/test/CodeGen/ARM/subreg-remat.ll
+++ b/llvm/test/CodeGen/ARM/subreg-remat.ll
@@ -19,11 +19,11 @@ target triple = "thumbv7-apple-ios"
; And reloaded after the asm:
; CHECK: vldr [[D16:d[0-9]+]],
; CHECK: vstr [[D16]], [r1]
-define void @f1(float %x, <2 x float>* %p) {
+define void @f1(float %x, ptr %p) {
%v1 = insertelement <2 x float> undef, float %x, i32 0
%v2 = insertelement <2 x float> %v1, float 0x400921FB60000000, i32 1
%y = call double asm sideeffect "asm clobber $0", "=w,0,~{d1},~{d2},~{d3},~{d4},~{d5},~{d6},~{d7},~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15},~{d16},~{d17},~{d18},~{d19},~{d20},~{d21},~{d22},~{d23},~{d24},~{d25},~{d26},~{d27},~{d28},~{d29},~{d30},~{d31}"(<2 x float> %v2) nounwind
- store <2 x float> %v2, <2 x float>* %p, align 8
+ store <2 x float> %v2, ptr %p, align 8
ret void
}
@@ -44,9 +44,9 @@ define void @f1(float %x, <2 x float>* %p) {
; But instead rematerialize after the asm:
; CHECK: vldr [[S0:s[0-9]+]], LCPI
; CHECK: vstr [[D0:d[0-9]+]], [r0]
-define void @f2(<2 x float>* %p) {
+define void @f2(ptr %p) {
%v2 = insertelement <2 x float> undef, float 0x400921FB60000000, i32 0
%y = call double asm sideeffect "asm clobber $0", "=w,0,~{d1},~{d2},~{d3},~{d4},~{d5},~{d6},~{d7},~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15},~{d16},~{d17},~{d18},~{d19},~{d20},~{d21},~{d22},~{d23},~{d24},~{d25},~{d26},~{d27},~{d28},~{d29},~{d30},~{d31}"(<2 x float> %v2) nounwind
- store <2 x float> %v2, <2 x float>* %p, align 8
+ store <2 x float> %v2, ptr %p, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/subtarget-no-movt.ll b/llvm/test/CodeGen/ARM/subtarget-no-movt.ll
index 3fb84f00524f5..1ddab47ece5b0 100644
--- a/llvm/test/CodeGen/ARM/subtarget-no-movt.ll
+++ b/llvm/test/CodeGen/ARM/subtarget-no-movt.ll
@@ -67,7 +67,7 @@ define i32 @foo1(i32 %a) {
; NO-USE-MOVT-O0: .long 3758153728 @ 0xe000e000
define i32 @foo2() {
- %1 = load i32, i32* inttoptr (i32 -536813568 to i32*) ; load from 0xe000e000
+ %1 = load i32, ptr inttoptr (i32 -536813568 to ptr) ; load from 0xe000e000
ret i32 %1
}
attributes #0 = { "target-features"="+no-movt" }
diff --git a/llvm/test/CodeGen/ARM/swift-atomics.ll b/llvm/test/CodeGen/ARM/swift-atomics.ll
index ca7e7fb299bf2..44403790affa5 100644
--- a/llvm/test/CodeGen/ARM/swift-atomics.ll
+++ b/llvm/test/CodeGen/ARM/swift-atomics.ll
@@ -3,21 +3,21 @@
; Release operations only need the store barrier provided by a "dmb ishst",
-define void @test_store_release(i32* %p, i32 %v) {
+define void @test_store_release(ptr %p, i32 %v) {
; CHECK-LABEL: test_store_release:
; CHECK: dmb ishst
; CHECK: str
; CHECK-STRICT-ATOMIC-LABEL: test_store_release:
; CHECK-STRICT-ATOMIC: dmb {{ish$}}
- store atomic i32 %v, i32* %p release, align 4
+ store atomic i32 %v, ptr %p release, align 4
ret void
}
; However, if sequential consistency is needed *something* must ensure a release
; followed by an acquire does not get reordered. In that case a "dmb ishst" is
; not adequate.
-define i32 @test_seq_cst(i32* %p, i32 %v) {
+define i32 @test_seq_cst(ptr %p, i32 %v) {
; CHECK-LABEL: test_seq_cst:
; CHECK: dmb ishst
; CHECK: str
@@ -32,20 +32,20 @@ define i32 @test_seq_cst(i32* %p, i32 %v) {
; CHECK-STRICT-ATOMIC: ldr
; CHECK-STRICT-ATOMIC: dmb {{ish$}}
- store atomic i32 %v, i32* %p seq_cst, align 4
- %val = load atomic i32, i32* %p seq_cst, align 4
+ store atomic i32 %v, ptr %p seq_cst, align 4
+ %val = load atomic i32, ptr %p seq_cst, align 4
ret i32 %val
}
; Also, pure acquire operations should definitely not have an ishst barrier.
-define i32 @test_acq(i32* %addr) {
+define i32 @test_acq(ptr %addr) {
; CHECK-LABEL: test_acq:
; CHECK: ldr
; CHECK: dmb {{ish$}}
; CHECK-STRICT-ATOMIC-LABEL: test_acq:
; CHECK-STRICT-ATOMIC: dmb {{ish$}}
- %val = load atomic i32, i32* %addr acquire, align 4
+ %val = load atomic i32, ptr %addr acquire, align 4
ret i32 %val
}
diff --git a/llvm/test/CodeGen/ARM/swift-return.ll b/llvm/test/CodeGen/ARM/swift-return.ll
index f8cc7fc84d643..3695cfa5b029d 100644
--- a/llvm/test/CodeGen/ARM/swift-return.ll
+++ b/llvm/test/CodeGen/ARM/swift-return.ll
@@ -18,8 +18,8 @@
define i16 @test(i32 %key) {
entry:
%key.addr = alloca i32, align 4
- store i32 %key, i32* %key.addr, align 4
- %0 = load i32, i32* %key.addr, align 4
+ store i32 %key, ptr %key.addr, align 4
+ %0 = load i32, ptr %key.addr, align 4
%call = call swiftcc { i16, i8 } @gen(i32 %0)
%v3 = extractvalue { i16, i8 } %call, 0
%v1 = sext i16 %v3 to i32
@@ -61,8 +61,8 @@ declare swiftcc { i16, i8 } @gen(i32)
define i32 @test2(i32 %key) #0 {
entry:
%key.addr = alloca i32, align 4
- store i32 %key, i32* %key.addr, align 4
- %0 = load i32, i32* %key.addr, align 4
+ store i32 %key, ptr %key.addr, align 4
+ %0 = load i32, ptr %key.addr, align 4
%call = call swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %0)
%v3 = extractvalue { i32, i32, i32, i32, i32 } %call, 0
@@ -115,8 +115,8 @@ define swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %key) {
define i32 @test3(i32 %key) #0 {
entry:
%key.addr = alloca i32, align 4
- store i32 %key, i32* %key.addr, align 4
- %0 = load i32, i32* %key.addr, align 4
+ store i32 %key, ptr %key.addr, align 4
+ %0 = load i32, ptr %key.addr, align 4
%call = call swiftcc { i32, i32, i32, i32 } @gen3(i32 %0)
%v3 = extractvalue { i32, i32, i32, i32 } %call, 0
@@ -147,8 +147,8 @@ declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key)
define float @test4(float %key) #0 {
entry:
%key.addr = alloca float, align 4
- store float %key, float* %key.addr, align 4
- %0 = load float, float* %key.addr, align 4
+ store float %key, ptr %key.addr, align 4
+ %0 = load float, ptr %key.addr, align 4
%call = call swiftcc { float, float, float, float } @gen4(float %0)
%v3 = extractvalue { float, float, float, float } %call, 0
diff --git a/llvm/test/CodeGen/ARM/swift-vldm.ll b/llvm/test/CodeGen/ARM/swift-vldm.ll
index a53b2413bde16..83958719bac09 100644
--- a/llvm/test/CodeGen/ARM/swift-vldm.ll
+++ b/llvm/test/CodeGen/ARM/swift-vldm.ll
@@ -11,16 +11,16 @@
declare fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
-define void @test_vldm(double* %x, double * %y) {
+define void @test_vldm(ptr %x, ptr %y) {
entry:
- %addr1 = getelementptr double, double * %x, i32 1
- %addr2 = getelementptr double, double * %x, i32 2
- %addr3 = getelementptr double, double * %x, i32 3
- %d0 = load double , double * %y
- %d1 = load double , double * %x
- %d2 = load double , double * %addr1
- %d3 = load double , double * %addr2
- %d4 = load double , double * %addr3
+ %addr1 = getelementptr double, ptr %x, i32 1
+ %addr2 = getelementptr double, ptr %x, i32 2
+ %addr3 = getelementptr double, ptr %x, i32 3
+ %d0 = load double , ptr %y
+ %d1 = load double , ptr %x
+ %d2 = load double , ptr %addr1
+ %d3 = load double , ptr %addr2
+ %d4 = load double , ptr %addr3
; We are trying to force x[0-3] in registers d1 to d4 so that we can test we
; don't form a "vldmia rX, {d1, d2, d3, d4}".
; We are relying on the calling convention and that register allocation
diff --git a/llvm/test/CodeGen/ARM/swifterror.ll b/llvm/test/CodeGen/ARM/swifterror.ll
index 1a330e7e5c77f..c0bc3d4e20992 100644
--- a/llvm/test/CodeGen/ARM/swifterror.ll
+++ b/llvm/test/CodeGen/ARM/swifterror.ll
@@ -3,14 +3,14 @@
; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=armv7-apple-ios | FileCheck --check-prefix=CHECK-O0 %s
; RUN: llc -verify-machineinstrs < %s -mtriple=armv7-linux-androideabi | FileCheck --check-prefix=CHECK-ANDROID %s
-declare i8* @malloc(i64)
-declare void @free(i8*)
+declare ptr @malloc(i64)
+declare void @free(ptr)
%swift_error = type { i64, i8 }
%struct.S = type { i32, i32, i32, i32, i32, i32 }
; This tests the basic usage of a swifterror parameter. "foo" is the function
; that takes a swifterror parameter and "caller" is the caller of "foo".
-define float @foo(%swift_error** swifterror %error_ptr_ref) {
+define float @foo(ptr swifterror %error_ptr_ref) {
; CHECK-APPLE-LABEL: foo:
; CHECK-APPLE: @ %bb.0: @ %entry
; CHECK-APPLE-NEXT: push {lr}
@@ -52,16 +52,15 @@ define float @foo(%swift_error** swifterror %error_ptr_ref) {
; CHECK-ANDROID-NEXT: pop {r11, pc}
entry:
- %call = call i8* @malloc(i64 16)
- %call.0 = bitcast i8* %call to %swift_error*
- store %swift_error* %call.0, %swift_error** %error_ptr_ref
- %tmp = getelementptr inbounds i8, i8* %call, i64 8
- store i8 1, i8* %tmp
+ %call = call ptr @malloc(i64 16)
+ store ptr %call, ptr %error_ptr_ref
+ %tmp = getelementptr inbounds i8, ptr %call, i64 8
+ store i8 1, ptr %tmp
ret float 1.0
}
; "caller" calls "foo" that takes a swifterror parameter.
-define float @caller(i8* %error_ref) {
+define float @caller(ptr %error_ref) {
; CHECK-APPLE-LABEL: caller:
; CHECK-APPLE: @ %bb.0: @ %entry
; CHECK-APPLE-NEXT: push {r4, r8, lr}
@@ -127,25 +126,24 @@ define float @caller(i8* %error_ref) {
; spill r0
; reload r0
entry:
- %error_ptr_ref = alloca swifterror %swift_error*
- store %swift_error* null, %swift_error** %error_ptr_ref
- %call = call float @foo(%swift_error** swifterror %error_ptr_ref)
- %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref
- %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null
- %tmp = bitcast %swift_error* %error_from_foo to i8*
+ %error_ptr_ref = alloca swifterror ptr
+ store ptr null, ptr %error_ptr_ref
+ %call = call float @foo(ptr swifterror %error_ptr_ref)
+ %error_from_foo = load ptr, ptr %error_ptr_ref
+ %had_error_from_foo = icmp ne ptr %error_from_foo, null
br i1 %had_error_from_foo, label %handler, label %cont
cont:
- %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1
- %t = load i8, i8* %v1
- store i8 %t, i8* %error_ref
+ %v1 = getelementptr inbounds %swift_error, ptr %error_from_foo, i64 0, i32 1
+ %t = load i8, ptr %v1
+ store i8 %t, ptr %error_ref
br label %handler
handler:
- call void @free(i8* %tmp)
+ call void @free(ptr %error_from_foo)
ret float 1.0
}
; "caller2" is the caller of "foo", it calls "foo" inside a loop.
-define float @caller2(i8* %error_ref) {
+define float @caller2(ptr %error_ref) {
; CHECK-APPLE-LABEL: caller2:
; CHECK-APPLE: @ %bb.0: @ %entry
; CHECK-APPLE-NEXT: push {r4, r8, lr}
@@ -251,31 +249,30 @@ define float @caller2(i8* %error_ref) {
; spill r0
; reload r0
entry:
- %error_ptr_ref = alloca swifterror %swift_error*
+ %error_ptr_ref = alloca swifterror ptr
br label %bb_loop
bb_loop:
- store %swift_error* null, %swift_error** %error_ptr_ref
- %call = call float @foo(%swift_error** swifterror %error_ptr_ref)
- %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref
- %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null
- %tmp = bitcast %swift_error* %error_from_foo to i8*
+ store ptr null, ptr %error_ptr_ref
+ %call = call float @foo(ptr swifterror %error_ptr_ref)
+ %error_from_foo = load ptr, ptr %error_ptr_ref
+ %had_error_from_foo = icmp ne ptr %error_from_foo, null
br i1 %had_error_from_foo, label %handler, label %cont
cont:
%cmp = fcmp ogt float %call, 1.000000e+00
br i1 %cmp, label %bb_end, label %bb_loop
bb_end:
- %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1
- %t = load i8, i8* %v1
- store i8 %t, i8* %error_ref
+ %v1 = getelementptr inbounds %swift_error, ptr %error_from_foo, i64 0, i32 1
+ %t = load i8, ptr %v1
+ store i8 %t, ptr %error_ref
br label %handler
handler:
- call void @free(i8* %tmp)
+ call void @free(ptr %error_from_foo)
ret float 1.0
}
; "foo_if" is a function that takes a swifterror parameter, it sets swifterror
; under a certain condition.
-define float @foo_if(%swift_error** swifterror %error_ptr_ref, i32 %cc) {
+define float @foo_if(ptr swifterror %error_ptr_ref, i32 %cc) {
; CHECK-APPLE-LABEL: foo_if:
; CHECK-APPLE: @ %bb.0: @ %entry
; CHECK-APPLE-NEXT: push {lr}
@@ -360,11 +357,10 @@ entry:
br i1 %cond, label %gen_error, label %normal
gen_error:
- %call = call i8* @malloc(i64 16)
- %call.0 = bitcast i8* %call to %swift_error*
- store %swift_error* %call.0, %swift_error** %error_ptr_ref
- %tmp = getelementptr inbounds i8, i8* %call, i64 8
- store i8 1, i8* %tmp
+ %call = call ptr @malloc(i64 16)
+ store ptr %call, ptr %error_ptr_ref
+ %tmp = getelementptr inbounds i8, ptr %call, i64 8
+ store i8 1, ptr %tmp
ret float 1.0
normal:
@@ -373,7 +369,7 @@ normal:
; "foo_loop" is a function that takes a swifterror parameter, it sets swifterror
; under a certain condition inside a loop.
-define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float %cc2) {
+define float @foo_loop(ptr swifterror %error_ptr_ref, i32 %cc, float %cc2) {
; CHECK-APPLE-LABEL: foo_loop:
; CHECK-APPLE: @ %bb.0: @ %entry
; CHECK-APPLE-NEXT: push {r4, r5, lr}
@@ -491,11 +487,10 @@ bb_loop:
br i1 %cond, label %gen_error, label %bb_cont
gen_error:
- %call = call i8* @malloc(i64 16)
- %call.0 = bitcast i8* %call to %swift_error*
- store %swift_error* %call.0, %swift_error** %error_ptr_ref
- %tmp = getelementptr inbounds i8, i8* %call, i64 8
- store i8 1, i8* %tmp
+ %call = call ptr @malloc(i64 16)
+ store ptr %call, ptr %error_ptr_ref
+ %tmp = getelementptr inbounds i8, ptr %call, i64 8
+ store i8 1, ptr %tmp
br label %bb_cont
bb_cont:
@@ -507,7 +502,7 @@ bb_end:
; "foo_sret" is a function that takes a swifterror parameter, it also has a sret
; parameter.
-define void @foo_sret(%struct.S* sret(%struct.S) %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) {
+define void @foo_sret(ptr sret(%struct.S) %agg.result, i32 %val1, ptr swifterror %error_ptr_ref) {
; CHECK-APPLE-LABEL: foo_sret:
; CHECK-APPLE: @ %bb.0: @ %entry
; CHECK-APPLE-NEXT: push {r4, r5, lr}
@@ -560,18 +555,17 @@ define void @foo_sret(%struct.S* sret(%struct.S) %agg.result, i32 %val1, %swift_
; spill to stack: sret and val1
; reload from stack: sret and val1
entry:
- %call = call i8* @malloc(i64 16)
- %call.0 = bitcast i8* %call to %swift_error*
- store %swift_error* %call.0, %swift_error** %error_ptr_ref
- %tmp = getelementptr inbounds i8, i8* %call, i64 8
- store i8 1, i8* %tmp
- %v2 = getelementptr inbounds %struct.S, %struct.S* %agg.result, i32 0, i32 1
- store i32 %val1, i32* %v2
+ %call = call ptr @malloc(i64 16)
+ store ptr %call, ptr %error_ptr_ref
+ %tmp = getelementptr inbounds i8, ptr %call, i64 8
+ store i8 1, ptr %tmp
+ %v2 = getelementptr inbounds %struct.S, ptr %agg.result, i32 0, i32 1
+ store i32 %val1, ptr %v2
ret void
}
; "caller3" calls "foo_sret" that takes a swifterror parameter.
-define float @caller3(i8* %error_ref) {
+define float @caller3(ptr %error_ref) {
; CHECK-APPLE-LABEL: caller3:
; CHECK-APPLE: @ %bb.0: @ %entry
; CHECK-APPLE-NEXT: push {r4, r7, r8, lr}
@@ -646,27 +640,26 @@ define float @caller3(i8* %error_ref) {
; Access part of the error object and save it to error_ref
entry:
%s = alloca %struct.S, align 8
- %error_ptr_ref = alloca swifterror %swift_error*
- store %swift_error* null, %swift_error** %error_ptr_ref
- call void @foo_sret(%struct.S* sret(%struct.S) %s, i32 1, %swift_error** swifterror %error_ptr_ref)
- %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref
- %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null
- %tmp = bitcast %swift_error* %error_from_foo to i8*
+ %error_ptr_ref = alloca swifterror ptr
+ store ptr null, ptr %error_ptr_ref
+ call void @foo_sret(ptr sret(%struct.S) %s, i32 1, ptr swifterror %error_ptr_ref)
+ %error_from_foo = load ptr, ptr %error_ptr_ref
+ %had_error_from_foo = icmp ne ptr %error_from_foo, null
br i1 %had_error_from_foo, label %handler, label %cont
cont:
- %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1
- %t = load i8, i8* %v1
- store i8 %t, i8* %error_ref
+ %v1 = getelementptr inbounds %swift_error, ptr %error_from_foo, i64 0, i32 1
+ %t = load i8, ptr %v1
+ store i8 %t, ptr %error_ref
br label %handler
handler:
- call void @free(i8* %tmp)
+ call void @free(ptr %error_from_foo)
ret float 1.0
}
; "foo_vararg" is a function that takes a swifterror parameter, it also has
; variable number of arguments.
-declare void @llvm.va_start(i8*) nounwind
-define float @foo_vararg(%swift_error** swifterror %error_ptr_ref, ...) {
+declare void @llvm.va_start(ptr) nounwind
+define float @foo_vararg(ptr swifterror %error_ptr_ref, ...) {
; CHECK-APPLE-LABEL: foo_vararg:
; CHECK-APPLE: @ %bb.0: @ %entry
; CHECK-APPLE-NEXT: sub sp, sp, #16
@@ -770,30 +763,28 @@ define float @foo_vararg(%swift_error** swifterror %error_ptr_ref, ...) {
; CHECK-ANDROID-NEXT: bx lr
entry:
- %call = call i8* @malloc(i64 16)
- %call.0 = bitcast i8* %call to %swift_error*
- store %swift_error* %call.0, %swift_error** %error_ptr_ref
- %tmp = getelementptr inbounds i8, i8* %call, i64 8
- store i8 1, i8* %tmp
+ %call = call ptr @malloc(i64 16)
+ store ptr %call, ptr %error_ptr_ref
+ %tmp = getelementptr inbounds i8, ptr %call, i64 8
+ store i8 1, ptr %tmp
- %args = alloca i8*, align 8
+ %args = alloca ptr, align 8
%a10 = alloca i32, align 4
%a11 = alloca i32, align 4
%a12 = alloca i32, align 4
- %v10 = bitcast i8** %args to i8*
- call void @llvm.va_start(i8* %v10)
- %v11 = va_arg i8** %args, i32
- store i32 %v11, i32* %a10, align 4
- %v12 = va_arg i8** %args, i32
- store i32 %v12, i32* %a11, align 4
- %v13 = va_arg i8** %args, i32
- store i32 %v13, i32* %a12, align 4
+ call void @llvm.va_start(ptr %args)
+ %v11 = va_arg ptr %args, i32
+ store i32 %v11, ptr %a10, align 4
+ %v12 = va_arg ptr %args, i32
+ store i32 %v12, ptr %a11, align 4
+ %v13 = va_arg ptr %args, i32
+ store i32 %v13, ptr %a12, align 4
ret float 1.0
}
; "caller4" calls "foo_vararg" that takes a swifterror parameter.
-define float @caller4(i8* %error_ref) {
+define float @caller4(ptr %error_ref) {
; CHECK-APPLE-LABEL: caller4:
; CHECK-APPLE: @ %bb.0: @ %entry
; CHECK-APPLE-NEXT: push {r4, r8, lr}
@@ -883,37 +874,36 @@ define float @caller4(i8* %error_ref) {
; CHECK-ANDROID-NEXT: pop {r4, r8, r11, pc}
; Access part of the error object and save it to error_ref
entry:
- %error_ptr_ref = alloca swifterror %swift_error*
- store %swift_error* null, %swift_error** %error_ptr_ref
+ %error_ptr_ref = alloca swifterror ptr
+ store ptr null, ptr %error_ptr_ref
%a10 = alloca i32, align 4
%a11 = alloca i32, align 4
%a12 = alloca i32, align 4
- store i32 10, i32* %a10, align 4
- store i32 11, i32* %a11, align 4
- store i32 12, i32* %a12, align 4
- %v10 = load i32, i32* %a10, align 4
- %v11 = load i32, i32* %a11, align 4
- %v12 = load i32, i32* %a12, align 4
+ store i32 10, ptr %a10, align 4
+ store i32 11, ptr %a11, align 4
+ store i32 12, ptr %a12, align 4
+ %v10 = load i32, ptr %a10, align 4
+ %v11 = load i32, ptr %a11, align 4
+ %v12 = load i32, ptr %a12, align 4
- %call = call float (%swift_error**, ...) @foo_vararg(%swift_error** swifterror %error_ptr_ref, i32 %v10, i32 %v11, i32 %v12)
- %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref
- %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null
- %tmp = bitcast %swift_error* %error_from_foo to i8*
+ %call = call float (ptr, ...) @foo_vararg(ptr swifterror %error_ptr_ref, i32 %v10, i32 %v11, i32 %v12)
+ %error_from_foo = load ptr, ptr %error_ptr_ref
+ %had_error_from_foo = icmp ne ptr %error_from_foo, null
br i1 %had_error_from_foo, label %handler, label %cont
cont:
- %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1
- %t = load i8, i8* %v1
- store i8 %t, i8* %error_ref
+ %v1 = getelementptr inbounds %swift_error, ptr %error_from_foo, i64 0, i32 1
+ %t = load i8, ptr %v1
+ store i8 %t, ptr %error_ref
br label %handler
handler:
- call void @free(i8* %tmp)
+ call void @free(ptr %error_from_foo)
ret float 1.0
}
; Check that we don't blow up on tail calling swifterror argument functions.
-define float @tailcallswifterror(%swift_error** swifterror %error_ptr_ref) {
+define float @tailcallswifterror(ptr swifterror %error_ptr_ref) {
; CHECK-APPLE-LABEL: tailcallswifterror:
; CHECK-APPLE: @ %bb.0: @ %entry
; CHECK-APPLE-NEXT: push {lr}
@@ -935,10 +925,10 @@ define float @tailcallswifterror(%swift_error** swifterror %error_ptr_ref) {
; CHECK-ANDROID-NEXT: bl tailcallswifterror
; CHECK-ANDROID-NEXT: pop {r11, pc}
entry:
- %0 = tail call float @tailcallswifterror(%swift_error** swifterror %error_ptr_ref)
+ %0 = tail call float @tailcallswifterror(ptr swifterror %error_ptr_ref)
ret float %0
}
-define swiftcc float @tailcallswifterror_swiftcc(%swift_error** swifterror %error_ptr_ref) {
+define swiftcc float @tailcallswifterror_swiftcc(ptr swifterror %error_ptr_ref) {
; CHECK-APPLE-LABEL: tailcallswifterror_swiftcc:
; CHECK-APPLE: @ %bb.0: @ %entry
; CHECK-APPLE-NEXT: push {lr}
@@ -960,11 +950,11 @@ define swiftcc float @tailcallswifterror_swiftcc(%swift_error** swifterror %erro
; CHECK-ANDROID-NEXT: bl tailcallswifterror_swiftcc
; CHECK-ANDROID-NEXT: pop {r11, pc}
entry:
- %0 = tail call swiftcc float @tailcallswifterror_swiftcc(%swift_error** swifterror %error_ptr_ref)
+ %0 = tail call swiftcc float @tailcallswifterror_swiftcc(ptr swifterror %error_ptr_ref)
ret float %0
}
-define swiftcc void @swifterror_clobber(%swift_error** nocapture swifterror %err) {
+define swiftcc void @swifterror_clobber(ptr nocapture swifterror %err) {
; CHECK-APPLE-LABEL: swifterror_clobber:
; CHECK-APPLE: @ %bb.0:
; CHECK-APPLE-NEXT: mov r0, r8
@@ -997,7 +987,7 @@ define swiftcc void @swifterror_clobber(%swift_error** nocapture swifterror %err
ret void
}
-define swiftcc void @swifterror_reg_clobber(%swift_error** nocapture %err) {
+define swiftcc void @swifterror_reg_clobber(ptr nocapture %err) {
; CHECK-APPLE-LABEL: swifterror_reg_clobber:
; CHECK-APPLE: @ %bb.0:
; CHECK-APPLE-NEXT: push {r8, lr}
@@ -1029,7 +1019,7 @@ define swiftcc void @swifterror_reg_clobber(%swift_error** nocapture %err) {
ret void
}
-define swiftcc void @params_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
+define swiftcc void @params_in_reg(i32, i32, i32, i32, ptr swiftself, ptr nocapture swifterror %err) {
; CHECK-APPLE-LABEL: params_in_reg:
; CHECK-APPLE: @ %bb.0:
; CHECK-APPLE-NEXT: push {r4, r5, r6, r7, r10, r11, lr}
@@ -1120,15 +1110,15 @@ define swiftcc void @params_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_err
; CHECK-ANDROID-NEXT: bl params_in_reg2
; CHECK-ANDROID-NEXT: add sp, sp, #8
; CHECK-ANDROID-NEXT: pop {r4, r5, r6, r7, r9, r10, r11, pc}
- %error_ptr_ref = alloca swifterror %swift_error*, align 8
- store %swift_error* null, %swift_error** %error_ptr_ref
- call swiftcc void @params_in_reg2(i32 1, i32 2, i32 3, i32 4, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
- call swiftcc void @params_in_reg2(i32 %0, i32 %1, i32 %2, i32 %3, i8* swiftself %4, %swift_error** nocapture swifterror %err)
+ %error_ptr_ref = alloca swifterror ptr, align 8
+ store ptr null, ptr %error_ptr_ref
+ call swiftcc void @params_in_reg2(i32 1, i32 2, i32 3, i32 4, ptr swiftself null, ptr nocapture swifterror %error_ptr_ref)
+ call swiftcc void @params_in_reg2(i32 %0, i32 %1, i32 %2, i32 %3, ptr swiftself %4, ptr nocapture swifterror %err)
ret void
}
-declare swiftcc void @params_in_reg2(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err)
+declare swiftcc void @params_in_reg2(i32, i32, i32, i32, ptr swiftself, ptr nocapture swifterror %err)
-define swiftcc { i32, i32, i32, i32} @params_and_return_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
+define swiftcc { i32, i32, i32, i32} @params_and_return_in_reg(i32, i32, i32, i32, ptr swiftself, ptr nocapture swifterror %err) {
; CHECK-APPLE-LABEL: params_and_return_in_reg:
; CHECK-APPLE: @ %bb.0:
; CHECK-APPLE-NEXT: push {r4, r5, r6, r7, r10, r11, lr}
@@ -1284,22 +1274,22 @@ define swiftcc { i32, i32, i32, i32} @params_and_return_in_reg(i32, i32, i32, i3
; CHECK-ANDROID-NEXT: mov r8, r11
; CHECK-ANDROID-NEXT: add sp, sp, #16
; CHECK-ANDROID-NEXT: pop {r4, r5, r6, r7, r9, r10, r11, pc}
- %error_ptr_ref = alloca swifterror %swift_error*, align 8
- store %swift_error* null, %swift_error** %error_ptr_ref
- call swiftcc void @params_in_reg2(i32 1, i32 2, i32 3, i32 4, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
- %val = call swiftcc { i32, i32, i32, i32 } @params_and_return_in_reg2(i32 %0, i32 %1, i32 %2, i32 %3, i8* swiftself %4, %swift_error** nocapture swifterror %err)
- call swiftcc void @params_in_reg2(i32 1, i32 2, i32 3, i32 4, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
+ %error_ptr_ref = alloca swifterror ptr, align 8
+ store ptr null, ptr %error_ptr_ref
+ call swiftcc void @params_in_reg2(i32 1, i32 2, i32 3, i32 4, ptr swiftself null, ptr nocapture swifterror %error_ptr_ref)
+ %val = call swiftcc { i32, i32, i32, i32 } @params_and_return_in_reg2(i32 %0, i32 %1, i32 %2, i32 %3, ptr swiftself %4, ptr nocapture swifterror %err)
+ call swiftcc void @params_in_reg2(i32 1, i32 2, i32 3, i32 4, ptr swiftself null, ptr nocapture swifterror %error_ptr_ref)
ret { i32, i32, i32, i32 }%val
}
-declare swiftcc { i32, i32, i32, i32 } @params_and_return_in_reg2(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err)
+declare swiftcc { i32, i32, i32, i32 } @params_and_return_in_reg2(i32, i32, i32, i32, ptr swiftself, ptr nocapture swifterror %err)
-declare void @acallee(i8*)
+declare void @acallee(ptr)
; Make sure we don't tail call if the caller returns a swifterror value. We
; would have to move into the swifterror register before the tail call.
-define swiftcc void @tailcall_from_swifterror(%swift_error** swifterror %error_ptr_ref) {
+define swiftcc void @tailcall_from_swifterror(ptr swifterror %error_ptr_ref) {
; CHECK-APPLE-LABEL: tailcall_from_swifterror:
; CHECK-APPLE: @ %bb.0: @ %entry
; CHECK-APPLE-NEXT: push {r4, lr}
@@ -1331,15 +1321,15 @@ define swiftcc void @tailcall_from_swifterror(%swift_error** swifterror %error_p
; CHECK-ANDROID-NEXT: mov r8, r4
; CHECK-ANDROID-NEXT: pop {r4, pc}
entry:
- tail call void @acallee(i8* null)
+ tail call void @acallee(ptr null)
ret void
}
-declare swiftcc void @foo2(%swift_error** swifterror)
+declare swiftcc void @foo2(ptr swifterror)
; Make sure we properly assign registers during fast-isel.
-define swiftcc %swift_error* @testAssign(i8* %error_ref) {
+define swiftcc ptr @testAssign(ptr %error_ref) {
; CHECK-APPLE-LABEL: testAssign:
; CHECK-APPLE: @ %bb.0: @ %entry
; CHECK-APPLE-NEXT: push {r8, lr}
@@ -1378,12 +1368,12 @@ define swiftcc %swift_error* @testAssign(i8* %error_ref) {
; CHECK-ANDROID-NEXT: add sp, sp, #8
; CHECK-ANDROID-NEXT: pop {r8, pc}
entry:
- %error_ptr = alloca swifterror %swift_error*
- store %swift_error* null, %swift_error** %error_ptr
- call swiftcc void @foo2(%swift_error** swifterror %error_ptr)
+ %error_ptr = alloca swifterror ptr
+ store ptr null, ptr %error_ptr
+ call swiftcc void @foo2(ptr swifterror %error_ptr)
br label %a
a:
- %error = load %swift_error*, %swift_error** %error_ptr
- ret %swift_error* %error
+ %error = load ptr, ptr %error_ptr
+ ret ptr %error
}
diff --git a/llvm/test/CodeGen/ARM/swiftself.ll b/llvm/test/CodeGen/ARM/swiftself.ll
index 337cb5851f34d..221809f5a8ed4 100644
--- a/llvm/test/CodeGen/ARM/swiftself.ll
+++ b/llvm/test/CodeGen/ARM/swiftself.ll
@@ -7,17 +7,17 @@
; Parameter with swiftself should be allocated to r10.
; CHECK-LABEL: swiftself_param:
; CHECK: mov r0, r10
-define i8 *@swiftself_param(i8* swiftself %addr0) "frame-pointer"="all" {
- ret i8 *%addr0
+define ptr @swiftself_param(ptr swiftself %addr0) "frame-pointer"="all" {
+ ret ptr %addr0
}
; Check that r10 is used to pass a swiftself argument.
; CHECK-LABEL: call_swiftself:
; CHECK: mov r10, r0
; CHECK: bl {{_?}}swiftself_param
-define i8 *@call_swiftself(i8* %arg) "frame-pointer"="all" {
- %res = call i8 *@swiftself_param(i8* swiftself %arg)
- ret i8 *%res
+define ptr @call_swiftself(ptr %arg) "frame-pointer"="all" {
+ %res = call ptr @swiftself_param(ptr swiftself %arg)
+ ret ptr %res
}
; r10 should be saved by the callee even if used for swiftself
@@ -25,9 +25,9 @@ define i8 *@call_swiftself(i8* %arg) "frame-pointer"="all" {
; CHECK: push {r10}
; ...
; CHECK: pop {r10}
-define i8 *@swiftself_clobber(i8* swiftself %addr0) "frame-pointer"="all" {
+define ptr @swiftself_clobber(ptr swiftself %addr0) "frame-pointer"="all" {
call void asm sideeffect "", "~{r10}"()
- ret i8 *%addr0
+ ret ptr %addr0
}
; Demonstrate that we do not need any movs when calling multiple functions
@@ -37,9 +37,9 @@ define i8 *@swiftself_clobber(i8* swiftself %addr0) "frame-pointer"="all" {
; OPT: bl {{_?}}swiftself_param
; OPT-NOT: mov{{.*}}r10
; OPT-NEXT: bl {{_?}}swiftself_param
-define void @swiftself_passthrough(i8* swiftself %addr0) "frame-pointer"="all" {
- call i8 *@swiftself_param(i8* swiftself %addr0)
- call i8 *@swiftself_param(i8* swiftself %addr0)
+define void @swiftself_passthrough(ptr swiftself %addr0) "frame-pointer"="all" {
+ call ptr @swiftself_param(ptr swiftself %addr0)
+ call ptr @swiftself_param(ptr swiftself %addr0)
ret void
}
@@ -47,10 +47,10 @@ define void @swiftself_passthrough(i8* swiftself %addr0) "frame-pointer"="all" {
; CHECK-LABEL: swiftself_tail:
; TAILCALL: b {{_?}}swiftself_param
; TAILCALL-NOT: pop
-define i8* @swiftself_tail(i8* swiftself %addr0) "frame-pointer"="all" {
+define ptr @swiftself_tail(ptr swiftself %addr0) "frame-pointer"="all" {
call void asm sideeffect "", "~{r10}"()
- %res = tail call i8* @swiftself_param(i8* swiftself %addr0)
- ret i8* %res
+ %res = tail call ptr @swiftself_param(ptr swiftself %addr0)
+ ret ptr %res
}
; We can not use a tail call if the callee swiftself is not the same as the
@@ -59,24 +59,24 @@ define i8* @swiftself_tail(i8* swiftself %addr0) "frame-pointer"="all" {
; CHECK: mov r10, r0
; CHECK: bl {{_?}}swiftself_param
; CHECK: pop
-define i8* @swiftself_notail(i8* swiftself %addr0, i8* %addr1) nounwind "frame-pointer"="all" {
- %res = tail call i8* @swiftself_param(i8* swiftself %addr1)
- ret i8* %res
+define ptr @swiftself_notail(ptr swiftself %addr0, ptr %addr1) nounwind "frame-pointer"="all" {
+ %res = tail call ptr @swiftself_param(ptr swiftself %addr1)
+ ret ptr %res
}
; We cannot pretend that 'r0' is alive across the thisreturn_attribute call as
; we normally would. We marked the first parameter with swiftself which means it
; will no longer be passed in r0.
-declare swiftcc i8* @thisreturn_attribute(i8* returned swiftself)
+declare swiftcc ptr @thisreturn_attribute(ptr returned swiftself)
; OPT-LABEL: swiftself_nothisreturn:
; OPT-DAG: mov [[CSREG:r[1-9].*]], r0
; OPT-DAG: ldr r10, [r10]
; OPT: bl {{_?}}thisreturn_attribute
; OPT: str r0, [[[CSREG]]
-define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture sret(i8**), i8** noalias nocapture readonly swiftself) {
+define hidden swiftcc void @swiftself_nothisreturn(ptr noalias nocapture sret(ptr), ptr noalias nocapture readonly swiftself) {
entry:
- %2 = load i8*, i8** %1, align 8
- %3 = tail call swiftcc i8* @thisreturn_attribute(i8* swiftself %2)
- store i8* %3, i8** %0, align 8
+ %2 = load ptr, ptr %1, align 8
+ %3 = tail call swiftcc ptr @thisreturn_attribute(ptr swiftself %2)
+ store ptr %3, ptr %0, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/swifttailcc-call.ll b/llvm/test/CodeGen/ARM/swifttailcc-call.ll
index 2514e26900ee3..784ac5d9f05f2 100644
--- a/llvm/test/CodeGen/ARM/swifttailcc-call.ll
+++ b/llvm/test/CodeGen/ARM/swifttailcc-call.ll
@@ -192,10 +192,10 @@ define swifttailcc void @fromtail_toC() {
ret void
}
-declare swifttailcc i8* @SwiftSelf(i8 * swiftasync %context, i8* swiftself %closure)
-define swiftcc i8* @CallSwiftSelf(i8* swiftself %closure, i8* %context) {
+declare swifttailcc ptr @SwiftSelf(ptr swiftasync %context, ptr swiftself %closure)
+define swiftcc ptr @CallSwiftSelf(ptr swiftself %closure, ptr %context) {
; CHECK-LABEL: CallSwiftSelf:
; CHECK: push{{.*}}r10
- %res = call swifttailcc i8* @SwiftSelf(i8 * swiftasync %context, i8* swiftself %closure)
- ret i8* %res
+ %res = call swifttailcc ptr @SwiftSelf(ptr swiftasync %context, ptr swiftself %closure)
+ ret ptr %res
}
diff --git a/llvm/test/CodeGen/ARM/swifttailcc-fastisel.ll b/llvm/test/CodeGen/ARM/swifttailcc-fastisel.ll
index 7d6af2d801aa1..607dd45b07b55 100644
--- a/llvm/test/CodeGen/ARM/swifttailcc-fastisel.ll
+++ b/llvm/test/CodeGen/ARM/swifttailcc-fastisel.ll
@@ -1,11 +1,11 @@
; RUN: llc -mtriple=thumbv7-apple-ios -O0 -fast-isel %s -o - | FileCheck %s
-declare swifttailcc i8* @SwiftSelf(i8 * swiftasync %context, i8* swiftself %closure)
+declare swifttailcc ptr @SwiftSelf(ptr swiftasync %context, ptr swiftself %closure)
-define swifttailcc i8* @CallSwiftSelf(i8* swiftself %closure, i8* %context) {
+define swifttailcc ptr @CallSwiftSelf(ptr swiftself %closure, ptr %context) {
; CHECK-LABEL: CallSwiftSelf:
; CHECK: bl _SwiftSelf
; CHECK: pop {r7, pc}
- %res = call swifttailcc i8* @SwiftSelf(i8 * swiftasync %context, i8* swiftself null)
- ret i8* %res
+ %res = call swifttailcc ptr @SwiftSelf(ptr swiftasync %context, ptr swiftself null)
+ ret ptr %res
}
diff --git a/llvm/test/CodeGen/ARM/t2-shrink-ldrpost.ll b/llvm/test/CodeGen/ARM/t2-shrink-ldrpost.ll
index e7b1780c5998a..fabb6f14a35a9 100644
--- a/llvm/test/CodeGen/ARM/t2-shrink-ldrpost.ll
+++ b/llvm/test/CodeGen/ARM/t2-shrink-ldrpost.ll
@@ -5,7 +5,7 @@ target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64
target triple = "thumbv7m--linux-gnu"
; NOTE: When optimising for minimum size, an LDM is expected to be generated
-define void @f(i32 %n, i32* nocapture %a, i32* nocapture readonly %b) optsize minsize {
+define void @f(i32 %n, ptr nocapture %a, ptr nocapture readonly %b) optsize minsize {
; CHECK-LABEL: f:
; CHECK: @ %bb.0:
; CHECK-NEXT: cmp r0, #1
@@ -24,13 +24,13 @@ define void @f(i32 %n, i32* nocapture %a, i32* nocapture readonly %b) optsize mi
.lr.ph: ; preds = %.lr.ph, %0
%i.04 = phi i32 [ %6, %.lr.ph ], [ 0, %0 ]
- %.03 = phi i32* [ %2, %.lr.ph ], [ %b, %0 ]
- %.012 = phi i32* [ %5, %.lr.ph ], [ %a, %0 ]
- %2 = getelementptr inbounds i32, i32* %.03, i32 1
- %3 = load i32, i32* %.03, align 4
+ %.03 = phi ptr [ %2, %.lr.ph ], [ %b, %0 ]
+ %.012 = phi ptr [ %5, %.lr.ph ], [ %a, %0 ]
+ %2 = getelementptr inbounds i32, ptr %.03, i32 1
+ %3 = load i32, ptr %.03, align 4
%4 = add nsw i32 %3, 3
- %5 = getelementptr inbounds i32, i32* %.012, i32 1
- store i32 %4, i32* %.012, align 4
+ %5 = getelementptr inbounds i32, ptr %.012, i32 1
+ store i32 %4, ptr %.012, align 4
%6 = add nsw i32 %i.04, 1
%exitcond = icmp eq i32 %6, %n
br i1 %exitcond, label %._crit_edge, label %.lr.ph
@@ -40,7 +40,7 @@ define void @f(i32 %n, i32* nocapture %a, i32* nocapture readonly %b) optsize mi
}
; NOTE: When not optimising for minimum size, an LDM is expected not to be generated
-define void @f_nominsize(i32 %n, i32* nocapture %a, i32* nocapture readonly %b) optsize {
+define void @f_nominsize(i32 %n, ptr nocapture %a, ptr nocapture readonly %b) optsize {
; CHECK-LABEL: f_nominsize:
; CHECK: @ %bb.0:
; CHECK-NEXT: cmp r0, #1
@@ -60,13 +60,13 @@ define void @f_nominsize(i32 %n, i32* nocapture %a, i32* nocapture readonly %b)
.lr.ph: ; preds = %.lr.ph, %0
%i.04 = phi i32 [ %6, %.lr.ph ], [ 0, %0 ]
- %.03 = phi i32* [ %2, %.lr.ph ], [ %b, %0 ]
- %.012 = phi i32* [ %5, %.lr.ph ], [ %a, %0 ]
- %2 = getelementptr inbounds i32, i32* %.03, i32 1
- %3 = load i32, i32* %.03, align 4
+ %.03 = phi ptr [ %2, %.lr.ph ], [ %b, %0 ]
+ %.012 = phi ptr [ %5, %.lr.ph ], [ %a, %0 ]
+ %2 = getelementptr inbounds i32, ptr %.03, i32 1
+ %3 = load i32, ptr %.03, align 4
%4 = add nsw i32 %3, 3
- %5 = getelementptr inbounds i32, i32* %.012, i32 1
- store i32 %4, i32* %.012, align 4
+ %5 = getelementptr inbounds i32, ptr %.012, i32 1
+ store i32 %4, ptr %.012, align 4
%6 = add nsw i32 %i.04, 1
%exitcond = icmp eq i32 %6, %n
br i1 %exitcond, label %._crit_edge, label %.lr.ph
diff --git a/llvm/test/CodeGen/ARM/tail-call-scheduling.ll b/llvm/test/CodeGen/ARM/tail-call-scheduling.ll
index cd50ced0fa769..c5912e1190f01 100644
--- a/llvm/test/CodeGen/ARM/tail-call-scheduling.ll
+++ b/llvm/test/CodeGen/ARM/tail-call-scheduling.ll
@@ -7,7 +7,7 @@ target triple = "armv6kz-unknown-unknown-gnueabihf"
; it anyway just to demonstrate the issue.
; CHECK: pop {r{{[0-9]+}}, lr}
- at e = external local_unnamed_addr constant [0 x i32 (i32, i32)*], align 4
+ at e = external local_unnamed_addr constant [0 x ptr], align 4
; Function Attrs: nounwind sspstrong
define i32 @AVI_ChunkRead_p_chk(i32 %g) nounwind sspstrong "target-cpu"="arm1176jzf-s" {
@@ -18,13 +18,13 @@ entry:
if.then: ; preds = %entry
%add = add nsw i32 %g, 1
- %arrayidx = getelementptr inbounds [0 x i32 (i32, i32)*], [0 x i32 (i32, i32)*]* @e, i32 0, i32 %add
- %0 = load i32 (i32, i32)*, i32 (i32, i32)** %arrayidx, align 4
+ %arrayidx = getelementptr inbounds [0 x ptr], ptr @e, i32 0, i32 %add
+ %0 = load ptr, ptr %arrayidx, align 4
%call = tail call i32 %0(i32 0, i32 0) #3
br label %return
if.end: ; preds = %entry
- call void @c(i8* nonnull %b)
+ call void @c(ptr nonnull %b)
br label %return
return: ; preds = %if.end, %if.then
@@ -32,4 +32,4 @@ return: ; preds = %if.end, %if.then
ret i32 %retval.0
}
-declare void @c(i8*)
+declare void @c(ptr)
diff --git a/llvm/test/CodeGen/ARM/tail-call-weak.ll b/llvm/test/CodeGen/ARM/tail-call-weak.ll
index 04ba51042906f..cc6ffcf9f61c5 100644
--- a/llvm/test/CodeGen/ARM/tail-call-weak.ll
+++ b/llvm/test/CodeGen/ARM/tail-call-weak.ll
@@ -2,12 +2,12 @@
; RUN: llc -mtriple thumbv7-elf -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-OTHER
; RUN: llc -mtriple thumbv7-macho -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-OTHER
-declare i8* @f()
-declare extern_weak i8* @g(i8*)
+declare ptr @f()
+declare extern_weak ptr @g(ptr)
define void @test() {
- %call = tail call i8* @f()
- %call1 = tail call i8* @g(i8* %call)
+ %call = tail call ptr @f()
+ %call1 = tail call ptr @g(ptr %call)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/tail-call.ll b/llvm/test/CodeGen/ARM/tail-call.ll
index e320a6870789d..8bffab19cc439 100644
--- a/llvm/test/CodeGen/ARM/tail-call.ll
+++ b/llvm/test/CodeGen/ARM/tail-call.ll
@@ -101,37 +101,37 @@ entry:
; Check that nonnull attributes don't inhibit tailcalls.
-declare nonnull i8* @nonnull_callee(i8* %p, i32 %val)
-define i8* @nonnull_caller(i8* %p, i32 %val) {
+declare nonnull ptr @nonnull_callee(ptr %p, i32 %val)
+define ptr @nonnull_caller(ptr %p, i32 %val) {
; CHECK-LABEL: nonnull_caller:
; CHECK-TAIL: b nonnull_callee
; CHECK-NO-TAIL: bl nonnull_callee
entry:
- %call = tail call i8* @nonnull_callee(i8* %p, i32 %val)
- ret i8* %call
+ %call = tail call ptr @nonnull_callee(ptr %p, i32 %val)
+ ret ptr %call
}
; Check that noalias attributes don't inhibit tailcalls.
-declare noalias i8* @noalias_callee(i8* %p, i32 %val)
-define i8* @noalias_caller(i8* %p, i32 %val) {
+declare noalias ptr @noalias_callee(ptr %p, i32 %val)
+define ptr @noalias_caller(ptr %p, i32 %val) {
; CHECK-LABEL: noalias_caller:
; CHECK-TAIL: b noalias_callee
; CHECK-NO-TAIL: bl noalias_callee
entry:
- %call = tail call i8* @noalias_callee(i8* %p, i32 %val)
- ret i8* %call
+ %call = tail call ptr @noalias_callee(ptr %p, i32 %val)
+ ret ptr %call
}
; Check that alignment attributes don't inhibit tailcalls.
-declare align 8 i8* @align8_callee(i8* %p, i32 %val)
-define i8* @align8_caller(i8* %p, i32 %val) {
+declare align 8 ptr @align8_callee(ptr %p, i32 %val)
+define ptr @align8_caller(ptr %p, i32 %val) {
; CHECK-LABEL: align8_caller:
; CHECK-TAIL: b align8_callee
; CHECK-NO-TAIL: bl align8_callee
entry:
- %call = tail call i8* @align8_callee(i8* %p, i32 %val)
- ret i8* %call
+ %call = tail call ptr @align8_callee(ptr %p, i32 %val)
+ ret ptr %call
}
diff --git a/llvm/test/CodeGen/ARM/tail-dup.ll b/llvm/test/CodeGen/ARM/tail-dup.ll
index 407bdf7524b11..1aa3bb124d515 100644
--- a/llvm/test/CodeGen/ARM/tail-dup.ll
+++ b/llvm/test/CodeGen/ARM/tail-dup.ll
@@ -7,33 +7,33 @@
; CHECK: mov pc
; CHECK: mov pc
- at fn.codetable = internal unnamed_addr constant [3 x i8*] [i8* blockaddress(@fn, %RETURN), i8* blockaddress(@fn, %INCREMENT), i8* blockaddress(@fn, %DECREMENT)], align 4
+ at fn.codetable = internal unnamed_addr constant [3 x ptr] [ptr blockaddress(@fn, %RETURN), ptr blockaddress(@fn, %INCREMENT), ptr blockaddress(@fn, %DECREMENT)], align 4
-define i32 @fn(i32* nocapture %opcodes) nounwind readonly ssp {
+define i32 @fn(ptr nocapture %opcodes) nounwind readonly ssp {
entry:
- %0 = load i32, i32* %opcodes, align 4
- %arrayidx = getelementptr inbounds [3 x i8*], [3 x i8*]* @fn.codetable, i32 0, i32 %0
+ %0 = load i32, ptr %opcodes, align 4
+ %arrayidx = getelementptr inbounds [3 x ptr], ptr @fn.codetable, i32 0, i32 %0
br label %indirectgoto
INCREMENT: ; preds = %indirectgoto
%inc = add nsw i32 %result.0, 1
- %1 = load i32, i32* %opcodes.addr.0, align 4
- %arrayidx2 = getelementptr inbounds [3 x i8*], [3 x i8*]* @fn.codetable, i32 0, i32 %1
+ %1 = load i32, ptr %opcodes.addr.0, align 4
+ %arrayidx2 = getelementptr inbounds [3 x ptr], ptr @fn.codetable, i32 0, i32 %1
br label %indirectgoto
DECREMENT: ; preds = %indirectgoto
%dec = add nsw i32 %result.0, -1
- %2 = load i32, i32* %opcodes.addr.0, align 4
- %arrayidx4 = getelementptr inbounds [3 x i8*], [3 x i8*]* @fn.codetable, i32 0, i32 %2
+ %2 = load i32, ptr %opcodes.addr.0, align 4
+ %arrayidx4 = getelementptr inbounds [3 x ptr], ptr @fn.codetable, i32 0, i32 %2
br label %indirectgoto
indirectgoto: ; preds = %DECREMENT, %INCREMENT, %entry
%result.0 = phi i32 [ 0, %entry ], [ %dec, %DECREMENT ], [ %inc, %INCREMENT ]
- %opcodes.pn = phi i32* [ %opcodes, %entry ], [ %opcodes.addr.0, %DECREMENT ], [ %opcodes.addr.0, %INCREMENT ]
- %indirect.goto.dest.in = phi i8** [ %arrayidx, %entry ], [ %arrayidx4, %DECREMENT ], [ %arrayidx2, %INCREMENT ]
- %opcodes.addr.0 = getelementptr inbounds i32, i32* %opcodes.pn, i32 1
- %indirect.goto.dest = load i8*, i8** %indirect.goto.dest.in, align 4
- indirectbr i8* %indirect.goto.dest, [label %RETURN, label %INCREMENT, label %DECREMENT]
+ %opcodes.pn = phi ptr [ %opcodes, %entry ], [ %opcodes.addr.0, %DECREMENT ], [ %opcodes.addr.0, %INCREMENT ]
+ %indirect.goto.dest.in = phi ptr [ %arrayidx, %entry ], [ %arrayidx4, %DECREMENT ], [ %arrayidx2, %INCREMENT ]
+ %opcodes.addr.0 = getelementptr inbounds i32, ptr %opcodes.pn, i32 1
+ %indirect.goto.dest = load ptr, ptr %indirect.goto.dest.in, align 4
+ indirectbr ptr %indirect.goto.dest, [label %RETURN, label %INCREMENT, label %DECREMENT]
RETURN: ; preds = %indirectgoto
ret i32 %result.0
diff --git a/llvm/test/CodeGen/ARM/tail-merge-branch-weight.ll b/llvm/test/CodeGen/ARM/tail-merge-branch-weight.ll
index 33444078c616f..baecb6b16a007 100644
--- a/llvm/test/CodeGen/ARM/tail-merge-branch-weight.ll
+++ b/llvm/test/CodeGen/ARM/tail-merge-branch-weight.ll
@@ -11,20 +11,20 @@
; CHECK: bb.{{[0-9]+}}{{[0-9a-zA-Z.]*}}:
; CHECK: bb.{{[0-9]+}}{{[0-9a-zA-Z.]*}}:
-define i32 @test0(i32 %n, i32 %m, i32* nocapture %a, i32* nocapture %b) {
+define i32 @test0(i32 %n, i32 %m, ptr nocapture %a, ptr nocapture %b) {
entry:
%cmp = icmp sgt i32 %n, 0
br i1 %cmp, label %L0, label %L1, !prof !0
L0: ; preds = %entry
- store i32 12, i32* %a, align 4
- store i32 18, i32* %b, align 4
+ store i32 12, ptr %a, align 4
+ store i32 18, ptr %b, align 4
%cmp1 = icmp eq i32 %m, 8
br i1 %cmp1, label %L2, label %L3, !prof !1
L1: ; preds = %entry
- store i32 14, i32* %a, align 4
- store i32 18, i32* %b, align 4
+ store i32 14, ptr %a, align 4
+ store i32 18, ptr %b, align 4
%cmp3 = icmp eq i32 %m, 8
br i1 %cmp3, label %L2, label %L3, !prof !2
diff --git a/llvm/test/CodeGen/ARM/tail-opts.ll b/llvm/test/CodeGen/ARM/tail-opts.ll
index 475b80b3bb070..d2107b293d87d 100644
--- a/llvm/test/CodeGen/ARM/tail-opts.ll
+++ b/llvm/test/CodeGen/ARM/tail-opts.ll
@@ -9,7 +9,7 @@ declare i1 @qux()
@GHJK = global i32 0
-declare i8* @choose(i8*, i8*)
+declare ptr @choose(ptr, ptr)
; BranchFolding should tail-duplicate the indirect jump to avoid
; redundant branching.
@@ -33,8 +33,8 @@ declare i8* @choose(i8*, i8*)
define void @tail_duplicate_me() nounwind {
entry:
%a = call i1 @qux()
- %c = call i8* @choose(i8* blockaddress(@tail_duplicate_me, %return),
- i8* blockaddress(@tail_duplicate_me, %altret))
+ %c = call ptr @choose(ptr blockaddress(@tail_duplicate_me, %return),
+ ptr blockaddress(@tail_duplicate_me, %altret))
br i1 %a, label %A, label %next
next:
%b = call i1 @qux()
@@ -42,21 +42,21 @@ next:
A:
call void @bar(i32 0)
- store i32 0, i32* @GHJK
+ store i32 0, ptr @GHJK
br label %M
B:
call void @car(i32 1)
- store i32 0, i32* @GHJK
+ store i32 0, ptr @GHJK
br label %M
C:
call void @dar(i32 2)
- store i32 0, i32* @GHJK
+ store i32 0, ptr @GHJK
br label %M
M:
- indirectbr i8* %c, [label %return, label %altret]
+ indirectbr ptr %c, [label %return, label %altret]
return:
call void @ear(i32 1000)
diff --git a/llvm/test/CodeGen/ARM/tailcall-mem-intrinsics.ll b/llvm/test/CodeGen/ARM/tailcall-mem-intrinsics.ll
index 08370f2bf12ae..39bfba2ad6f70 100644
--- a/llvm/test/CodeGen/ARM/tailcall-mem-intrinsics.ll
+++ b/llvm/test/CodeGen/ARM/tailcall-mem-intrinsics.ll
@@ -2,30 +2,30 @@
; CHECK-LABEL: tail_memcpy_ret
; CHECK: bl __aeabi_memcpy
-define i8* @tail_memcpy_ret(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 {
+define ptr @tail_memcpy_ret(ptr nocapture %p, ptr nocapture readonly %q, i32 %n) #0 {
entry:
- tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i1 false)
- ret i8* %p
+ tail call void @llvm.memcpy.p0.p0.i32(ptr %p, ptr %q, i32 %n, i1 false)
+ ret ptr %p
}
; CHECK-LABEL: tail_memmove_ret
; CHECK: bl __aeabi_memmove
-define i8* @tail_memmove_ret(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 {
+define ptr @tail_memmove_ret(ptr nocapture %p, ptr nocapture readonly %q, i32 %n) #0 {
entry:
- tail call void @llvm.memmove.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i1 false)
- ret i8* %p
+ tail call void @llvm.memmove.p0.p0.i32(ptr %p, ptr %q, i32 %n, i1 false)
+ ret ptr %p
}
; CHECK-LABEL: tail_memset_ret
; CHECK: bl __aeabi_memset
-define i8* @tail_memset_ret(i8* nocapture %p, i8 %c, i32 %n) #0 {
+define ptr @tail_memset_ret(ptr nocapture %p, i8 %c, i32 %n) #0 {
entry:
- tail call void @llvm.memset.p0i8.i32(i8* %p, i8 %c, i32 %n, i1 false)
- ret i8* %p
+ tail call void @llvm.memset.p0.i32(ptr %p, i8 %c, i32 %n, i1 false)
+ ret ptr %p
}
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1) #0
-declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1) #0
-declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) #0
+declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture readonly, i32, i1) #0
+declare void @llvm.memmove.p0.p0.i32(ptr nocapture, ptr nocapture readonly, i32, i1) #0
+declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) #0
attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/ARM/taildup-branch-weight.ll b/llvm/test/CodeGen/ARM/taildup-branch-weight.ll
index bfc4d837ea856..c63c691171d25 100644
--- a/llvm/test/CodeGen/ARM/taildup-branch-weight.ll
+++ b/llvm/test/CodeGen/ARM/taildup-branch-weight.ll
@@ -4,21 +4,21 @@
; CHECK: name: test0
; CHECK: successors: %bb.1(0x04000000), %bb.2(0x7c000000)
-define void @test0(i32 %a, i32 %b, i32* %c, i32* %d) {
+define void @test0(i32 %a, i32 %b, ptr %c, ptr %d) {
entry:
- store i32 3, i32* %d
+ store i32 3, ptr %d
br label %B1
B2:
- store i32 2, i32* %c
+ store i32 2, ptr %c
br label %B4
B3:
- store i32 2, i32* %c
+ store i32 2, ptr %c
br label %B4
B1:
- store i32 1, i32* %d
+ store i32 1, ptr %d
%test0 = icmp slt i32 %a, %b
br i1 %test0, label %B2, label %B3, !prof !0
@@ -33,7 +33,7 @@ B4:
@g0 = common global i32 0, align 4
-define void @test1(i32 %a, i32 %b, i32* %c, i32* %d, i32* %e) {
+define void @test1(i32 %a, i32 %b, ptr %c, ptr %d, ptr %e) {
%test0 = icmp slt i32 %a, %b
br i1 %test0, label %B1, label %B2, !prof !1
@@ -42,11 +42,11 @@ B1:
br label %B3
B2:
- store i32 2, i32* %c
+ store i32 2, ptr %c
br label %B3
B3:
- store i32 3, i32* %e
+ store i32 3, ptr %e
ret void
}
diff --git a/llvm/test/CodeGen/ARM/test-sharedidx.ll b/llvm/test/CodeGen/ARM/test-sharedidx.ll
index 64f35399df300..09cea58070750 100644
--- a/llvm/test/CodeGen/ARM/test-sharedidx.ll
+++ b/llvm/test/CodeGen/ARM/test-sharedidx.ll
@@ -12,7 +12,7 @@
; variable.
; rdar://10674430
-define void @sharedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c, i32 %s, i32 %len) nounwind ssp {
+define void @sharedidx(ptr nocapture %a, ptr nocapture %b, ptr nocapture %c, i32 %s, i32 %len) nounwind ssp {
entry:
; CHECK-LABEL: sharedidx:
%cmp8 = icmp eq i32 %len, 0
@@ -23,16 +23,16 @@ for.body: ; preds = %entry, %for.body.3
; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
%i.09 = phi i32 [ %add5.3, %for.body.3 ], [ 0, %entry ]
- %arrayidx = getelementptr inbounds i8, i8* %a, i32 %i.09
- %0 = load i8, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds i8, ptr %a, i32 %i.09
+ %0 = load i8, ptr %arrayidx, align 1
%conv6 = zext i8 %0 to i32
- %arrayidx1 = getelementptr inbounds i8, i8* %b, i32 %i.09
- %1 = load i8, i8* %arrayidx1, align 1
+ %arrayidx1 = getelementptr inbounds i8, ptr %b, i32 %i.09
+ %1 = load i8, ptr %arrayidx1, align 1
%conv27 = zext i8 %1 to i32
%add = add nsw i32 %conv27, %conv6
%conv3 = trunc i32 %add to i8
- %arrayidx4 = getelementptr inbounds i8, i8* %c, i32 %i.09
- store i8 %conv3, i8* %arrayidx4, align 1
+ %arrayidx4 = getelementptr inbounds i8, ptr %c, i32 %i.09
+ store i8 %conv3, ptr %arrayidx4, align 1
%add5 = add i32 %i.09, %s
%cmp = icmp ult i32 %add5, %len
br i1 %cmp, label %for.body.1, label %for.end
@@ -44,31 +44,31 @@ for.body.1: ; preds = %for.body
; CHECK: %for.body.1
; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
- %arrayidx.1 = getelementptr inbounds i8, i8* %a, i32 %add5
- %2 = load i8, i8* %arrayidx.1, align 1
+ %arrayidx.1 = getelementptr inbounds i8, ptr %a, i32 %add5
+ %2 = load i8, ptr %arrayidx.1, align 1
%conv6.1 = zext i8 %2 to i32
- %arrayidx1.1 = getelementptr inbounds i8, i8* %b, i32 %add5
- %3 = load i8, i8* %arrayidx1.1, align 1
+ %arrayidx1.1 = getelementptr inbounds i8, ptr %b, i32 %add5
+ %3 = load i8, ptr %arrayidx1.1, align 1
%conv27.1 = zext i8 %3 to i32
%add.1 = add nsw i32 %conv27.1, %conv6.1
%conv3.1 = trunc i32 %add.1 to i8
- %arrayidx4.1 = getelementptr inbounds i8, i8* %c, i32 %add5
- store i8 %conv3.1, i8* %arrayidx4.1, align 1
+ %arrayidx4.1 = getelementptr inbounds i8, ptr %c, i32 %add5
+ store i8 %conv3.1, ptr %arrayidx4.1, align 1
%add5.1 = add i32 %add5, %s
%cmp.1 = icmp ult i32 %add5.1, %len
br i1 %cmp.1, label %for.body.2, label %for.end
for.body.2: ; preds = %for.body.1
- %arrayidx.2 = getelementptr inbounds i8, i8* %a, i32 %add5.1
- %4 = load i8, i8* %arrayidx.2, align 1
+ %arrayidx.2 = getelementptr inbounds i8, ptr %a, i32 %add5.1
+ %4 = load i8, ptr %arrayidx.2, align 1
%conv6.2 = zext i8 %4 to i32
- %arrayidx1.2 = getelementptr inbounds i8, i8* %b, i32 %add5.1
- %5 = load i8, i8* %arrayidx1.2, align 1
+ %arrayidx1.2 = getelementptr inbounds i8, ptr %b, i32 %add5.1
+ %5 = load i8, ptr %arrayidx1.2, align 1
%conv27.2 = zext i8 %5 to i32
%add.2 = add nsw i32 %conv27.2, %conv6.2
%conv3.2 = trunc i32 %add.2 to i8
- %arrayidx4.2 = getelementptr inbounds i8, i8* %c, i32 %add5.1
- store i8 %conv3.2, i8* %arrayidx4.2, align 1
+ %arrayidx4.2 = getelementptr inbounds i8, ptr %c, i32 %add5.1
+ store i8 %conv3.2, ptr %arrayidx4.2, align 1
%add5.2 = add i32 %add5.1, %s
%cmp.2 = icmp ult i32 %add5.2, %len
br i1 %cmp.2, label %for.body.3, label %for.end
@@ -77,16 +77,16 @@ for.body.3: ; preds = %for.body.2
; CHECK: %for.body.3
; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]
; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]
- %arrayidx.3 = getelementptr inbounds i8, i8* %a, i32 %add5.2
- %6 = load i8, i8* %arrayidx.3, align 1
+ %arrayidx.3 = getelementptr inbounds i8, ptr %a, i32 %add5.2
+ %6 = load i8, ptr %arrayidx.3, align 1
%conv6.3 = zext i8 %6 to i32
- %arrayidx1.3 = getelementptr inbounds i8, i8* %b, i32 %add5.2
- %7 = load i8, i8* %arrayidx1.3, align 1
+ %arrayidx1.3 = getelementptr inbounds i8, ptr %b, i32 %add5.2
+ %7 = load i8, ptr %arrayidx1.3, align 1
%conv27.3 = zext i8 %7 to i32
%add.3 = add nsw i32 %conv27.3, %conv6.3
%conv3.3 = trunc i32 %add.3 to i8
- %arrayidx4.3 = getelementptr inbounds i8, i8* %c, i32 %add5.2
- store i8 %conv3.3, i8* %arrayidx4.3, align 1
+ %arrayidx4.3 = getelementptr inbounds i8, ptr %c, i32 %add5.2
+ store i8 %conv3.3, ptr %arrayidx4.3, align 1
%add5.3 = add i32 %add5.2, %s
%cmp.3 = icmp ult i32 %add5.3, %len
br i1 %cmp.3, label %for.body, label %for.end
diff --git a/llvm/test/CodeGen/ARM/this-return.ll b/llvm/test/CodeGen/ARM/this-return.ll
index 4c9c94e932617..806cc9c7ca19f 100644
--- a/llvm/test/CodeGen/ARM/this-return.ll
+++ b/llvm/test/CodeGen/ARM/this-return.ll
@@ -7,15 +7,15 @@
%struct.D = type { %struct.B }
%struct.E = type { %struct.B, %struct.B }
-declare %struct.A* @A_ctor_base(%struct.A* returned)
-declare %struct.B* @B_ctor_base(%struct.B* returned, i32)
-declare %struct.B* @B_ctor_complete(%struct.B* returned, i32)
+declare ptr @A_ctor_base(ptr returned)
+declare ptr @B_ctor_base(ptr returned, i32)
+declare ptr @B_ctor_complete(ptr returned, i32)
-declare %struct.A* @A_ctor_base_nothisret(%struct.A*)
-declare %struct.B* @B_ctor_base_nothisret(%struct.B*, i32)
-declare %struct.B* @B_ctor_complete_nothisret(%struct.B*, i32)
+declare ptr @A_ctor_base_nothisret(ptr)
+declare ptr @B_ctor_base_nothisret(ptr, i32)
+declare ptr @B_ctor_complete_nothisret(ptr, i32)
-define %struct.C* @C_ctor_base(%struct.C* returned %this, i32 %x) {
+define ptr @C_ctor_base(ptr returned %this, i32 %x) {
entry:
; CHECKELF-LABEL: C_ctor_base:
; CHECKELF-NOT: mov {{r[0-9]+}}, r0
@@ -27,14 +27,12 @@ entry:
; CHECKT2D: bl _A_ctor_base
; CHECKT2D-NOT: mov r0, {{r[0-9]+}}
; CHECKT2D: b.w _B_ctor_base
- %0 = bitcast %struct.C* %this to %struct.A*
- %call = tail call %struct.A* @A_ctor_base(%struct.A* returned %0)
- %1 = getelementptr inbounds %struct.C, %struct.C* %this, i32 0, i32 0
- %call2 = tail call %struct.B* @B_ctor_base(%struct.B* returned %1, i32 %x)
- ret %struct.C* %this
+ %call = tail call ptr @A_ctor_base(ptr returned %this)
+ %call2 = tail call ptr @B_ctor_base(ptr returned %this, i32 %x)
+ ret ptr %this
}
-define %struct.C* @C_ctor_base_nothisret(%struct.C* %this, i32 %x) {
+define ptr @C_ctor_base_nothisret(ptr %this, i32 %x) {
entry:
; CHECKELF-LABEL: C_ctor_base_nothisret:
; CHECKELF: mov [[SAVETHIS:r[0-9]+]], r0
@@ -46,34 +44,32 @@ entry:
; CHECKT2D: bl _A_ctor_base_nothisret
; CHECKT2D: mov r0, [[SAVETHIS]]
; CHECKT2D-NOT: b.w _B_ctor_base_nothisret
- %0 = bitcast %struct.C* %this to %struct.A*
- %call = tail call %struct.A* @A_ctor_base_nothisret(%struct.A* %0)
- %1 = getelementptr inbounds %struct.C, %struct.C* %this, i32 0, i32 0
- %call2 = tail call %struct.B* @B_ctor_base_nothisret(%struct.B* %1, i32 %x)
- ret %struct.C* %this
+ %call = tail call ptr @A_ctor_base_nothisret(ptr %this)
+ %call2 = tail call ptr @B_ctor_base_nothisret(ptr %this, i32 %x)
+ ret ptr %this
}
-define %struct.C* @C_ctor_complete(%struct.C* %this, i32 %x) {
+define ptr @C_ctor_complete(ptr %this, i32 %x) {
entry:
; CHECKELF-LABEL: C_ctor_complete:
; CHECKELF: b C_ctor_base
; CHECKT2D-LABEL: C_ctor_complete:
; CHECKT2D: b.w _C_ctor_base
- %call = tail call %struct.C* @C_ctor_base(%struct.C* returned %this, i32 %x)
- ret %struct.C* %this
+ %call = tail call ptr @C_ctor_base(ptr returned %this, i32 %x)
+ ret ptr %this
}
-define %struct.C* @C_ctor_complete_nothisret(%struct.C* %this, i32 %x) {
+define ptr @C_ctor_complete_nothisret(ptr %this, i32 %x) {
entry:
; CHECKELF-LABEL: C_ctor_complete_nothisret:
; CHECKELF-NOT: b C_ctor_base_nothisret
; CHECKT2D-LABEL: C_ctor_complete_nothisret:
; CHECKT2D-NOT: b.w _C_ctor_base_nothisret
- %call = tail call %struct.C* @C_ctor_base_nothisret(%struct.C* %this, i32 %x)
- ret %struct.C* %this
+ %call = tail call ptr @C_ctor_base_nothisret(ptr %this, i32 %x)
+ ret ptr %this
}
-define %struct.D* @D_ctor_base(%struct.D* %this, i32 %x) {
+define ptr @D_ctor_base(ptr %this, i32 %x) {
entry:
; CHECKELF-LABEL: D_ctor_base:
; CHECKELF-NOT: mov {{r[0-9]+}}, r0
@@ -85,21 +81,19 @@ entry:
; CHECKT2D: bl _B_ctor_complete
; CHECKT2D-NOT: mov r0, {{r[0-9]+}}
; CHECKT2D: b.w _B_ctor_complete
- %b = getelementptr inbounds %struct.D, %struct.D* %this, i32 0, i32 0
- %call = tail call %struct.B* @B_ctor_complete(%struct.B* returned %b, i32 %x)
- %call2 = tail call %struct.B* @B_ctor_complete(%struct.B* returned %b, i32 %x)
- ret %struct.D* %this
+ %call = tail call ptr @B_ctor_complete(ptr returned %this, i32 %x)
+ %call2 = tail call ptr @B_ctor_complete(ptr returned %this, i32 %x)
+ ret ptr %this
}
-define %struct.E* @E_ctor_base(%struct.E* %this, i32 %x) {
+define ptr @E_ctor_base(ptr %this, i32 %x) {
entry:
; CHECKELF-LABEL: E_ctor_base:
; CHECKELF-NOT: b B_ctor_complete
; CHECKT2D-LABEL: E_ctor_base:
; CHECKT2D-NOT: b.w _B_ctor_complete
- %b = getelementptr inbounds %struct.E, %struct.E* %this, i32 0, i32 0
- %call = tail call %struct.B* @B_ctor_complete(%struct.B* returned %b, i32 %x)
- %b2 = getelementptr inbounds %struct.E, %struct.E* %this, i32 0, i32 1
- %call2 = tail call %struct.B* @B_ctor_complete(%struct.B* returned %b2, i32 %x)
- ret %struct.E* %this
+ %call = tail call ptr @B_ctor_complete(ptr returned %this, i32 %x)
+ %b2 = getelementptr inbounds %struct.E, ptr %this, i32 0, i32 1
+ %call2 = tail call ptr @B_ctor_complete(ptr returned %b2, i32 %x)
+ ret ptr %this
}
diff --git a/llvm/test/CodeGen/ARM/thread_pointer.ll b/llvm/test/CodeGen/ARM/thread_pointer.ll
index f1ef2ddac2d06..95d4467dc1e29 100644
--- a/llvm/test/CodeGen/ARM/thread_pointer.ll
+++ b/llvm/test/CodeGen/ARM/thread_pointer.ll
@@ -3,12 +3,12 @@
; RUN: llc -mtriple thumbv7-linux-gnueabi -o - %s | FileCheck %s -check-prefix=CHECK-SOFT
; RUN: llc -mtriple thumbv7-linux-gnueabi -mattr=+read-tp-hard -o - %s | FileCheck %s -check-prefix=CHECK-HARD
-declare i8* @llvm.thread.pointer()
+declare ptr @llvm.thread.pointer()
-define i8* @test() {
+define ptr @test() {
entry:
- %tmp1 = call i8* @llvm.thread.pointer()
- ret i8* %tmp1
+ %tmp1 = call ptr @llvm.thread.pointer()
+ ret ptr %tmp1
}
; CHECK-SOFT: bl __aeabi_read_tp
diff --git a/llvm/test/CodeGen/ARM/thumb-alignment.ll b/llvm/test/CodeGen/ARM/thumb-alignment.ll
index 8e894d28b6c6e..6bd110ac7c648 100644
--- a/llvm/test/CodeGen/ARM/thumb-alignment.ll
+++ b/llvm/test/CodeGen/ARM/thumb-alignment.ll
@@ -4,14 +4,14 @@
; CHECK: .globl foo
; CHECK-NEXT: .p2align 2
-define i32* @foo() {
- ret i32* @x
+define ptr @foo() {
+ ret ptr @x
}
; CHECK: .globl bar
; CHECK-NEXT: .p2align 1
-define i32* @bar() {
- ret i32* zeroinitializer
+define ptr @bar() {
+ ret ptr zeroinitializer
}
@a = external global i32
@@ -25,7 +25,7 @@ define i32* @bar() {
; CHECK-NEXT: .p2align 2
; CHECK: tbb
define i32 @baz() {
- %1 = load i32, i32* @c, align 4
+ %1 = load i32, ptr @c, align 4
switch i32 %1, label %7 [
i32 1, label %2
i32 4, label %5
@@ -34,13 +34,13 @@ define i32 @baz() {
]
; <label>:2
- %3 = load i32, i32* @a, align 4
- %4 = tail call i32 bitcast (i32 (...)* @fn2 to i32 (i32 (...)*, i32, i32)*)(i32 (...)* bitcast (i32 ()* @baz to i32 (...)*), i32 0, i32 %3) #2
+ %3 = load i32, ptr @a, align 4
+ %4 = tail call i32 @fn2(ptr @baz, i32 0, i32 %3) #2
br label %8
; <label>:5
- %6 = load i32, i32* @d, align 4
- store i32 %6, i32* @b, align 4
+ %6 = load i32, ptr @d, align 4
+ store i32 %6, ptr @b, align 4
br label %8
; <label>:7
diff --git a/llvm/test/CodeGen/ARM/thumb-big-stack.ll b/llvm/test/CodeGen/ARM/thumb-big-stack.ll
index cfb10ff2eccbf..eb7654a40929e 100644
--- a/llvm/test/CodeGen/ARM/thumb-big-stack.ll
+++ b/llvm/test/CodeGen/ARM/thumb-big-stack.ll
@@ -143,117 +143,117 @@ entry:
%.compoundliteral13969 = alloca <4 x float>, align 16
%.compoundliteral13983 = alloca <4 x float>, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40746999A0000000, float 0xC0719B3340000000, float 0xC070B66660000000, float 0xC07404CCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0x40746999A0000000, float 0xC0719B3340000000, float 0xC070B66660000000, float 0xC07404CCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40701B3340000000, float 0x405B866660000000, float 0xC0763999A0000000, float 4.895000e+02>, <4 x float>* undef
+ store <4 x float> <float 0x40701B3340000000, float 0x405B866660000000, float 0xC0763999A0000000, float 4.895000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp = load <4 x float>, <4 x float>* undef
+ %tmp = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp1 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add68 = fadd <4 x float> %tmp1, %tmp
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add68, <4 x float>* undef, align 16
+ store <4 x float> %add68, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp2 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp2 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add76 = fadd float undef, 0x4074C999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp3 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp3 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins77 = insertelement <4 x float> %tmp3, float %add76, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins77, <4 x float>* undef, align 16
+ store <4 x float> %vecins77, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp4 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp4 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext78 = extractelement <4 x float> %tmp4, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add79 = fadd float %vecext78, 0x40776E6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp5 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp5 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins80 = insertelement <4 x float> %tmp5, float %add79, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins80, <4 x float>* undef, align 16
+ store <4 x float> %vecins80, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40678CCCC0000000, float 0xC03E4CCCC0000000, float -4.170000e+02, float -1.220000e+02>, <4 x float>* undef
+ store <4 x float> <float 0x40678CCCC0000000, float 0xC03E4CCCC0000000, float -4.170000e+02, float -1.220000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp6 = load <4 x float>, <4 x float>* undef
+ %tmp6 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add82 = fadd <4 x float> undef, %tmp6
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add82, <4 x float>* undef, align 16
+ store <4 x float> %add82, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp7 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp7 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext83 = extractelement <4 x float> %tmp7, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add84 = fadd float %vecext83, 1.300000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp8 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp8 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins85 = insertelement <4 x float> %tmp8, float %add84, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins85, <4 x float>* undef, align 16
+ store <4 x float> %vecins85, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp9 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp9 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext86 = extractelement <4 x float> %tmp9, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add93 = fadd float undef, 0xC076C66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp10 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp10 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins94 = insertelement <4 x float> %tmp10, float %add93, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x406C2999A0000000, float 8.050000e+01, float 0xC0794999A0000000, float 0xC073E4CCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0x406C2999A0000000, float 8.050000e+01, float 0xC0794999A0000000, float 0xC073E4CCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp11 = load <4 x float>, <4 x float>* undef
+ %tmp11 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp12 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp12 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add96 = fadd <4 x float> %tmp12, %tmp11
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp13 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp13 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext97 = extractelement <4 x float> %tmp13, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add98 = fadd float %vecext97, 0x4079E66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp14 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp14 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins102 = insertelement <4 x float> undef, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins102, <4 x float>* undef, align 16
+ store <4 x float> %vecins102, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp15 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp15 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add104 = fadd float undef, 0x406AB999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp16 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp16 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC0531999A0000000, float 0xC0737999A0000000, float 0x407CB33340000000, float 0xC06DCCCCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0xC0531999A0000000, float 0xC0737999A0000000, float 0x407CB33340000000, float 0xC06DCCCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext579 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add580 = fadd float %vecext579, 0xC07424CCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp17 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp17 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins581 = insertelement <4 x float> %tmp17, float %add580, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins581, <4 x float>* undef, align 16
+ store <4 x float> %vecins581, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp18 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp18 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext582 = extractelement <4 x float> %tmp18, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add583 = fadd float %vecext582, 0x40444CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp19 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp19 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext590 = extractelement <4 x float> %tmp19, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -261,25 +261,25 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins592 = insertelement <4 x float> undef, float %add591, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins592, <4 x float>* undef, align 16
+ store <4 x float> %vecins592, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp20 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp20 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add594 = fadd float undef, 0xC05B466660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add605 = fadd float undef, 0x407164CCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp21 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp21 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add616 = fadd float undef, 1.885000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp22 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp22 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp23 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp23 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins620 = insertelement <4 x float> undef, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins620, <4 x float>* undef, align 16
+ store <4 x float> %vecins620, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext621 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -287,71 +287,71 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins623 = insertelement <4 x float> undef, float %add622, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins623, <4 x float>* undef, align 16
+ store <4 x float> %vecins623, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp24 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp24 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext624 = extractelement <4 x float> %tmp24, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add625 = fadd float %vecext624, 0xC064033340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp25 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp25 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins626 = insertelement <4 x float> %tmp25, float %add625, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins626, <4 x float>* undef, align 16
+ store <4 x float> %vecins626, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x404D0CCCC0000000, float 3.955000e+02, float 0xC0334CCCC0000000, float 0x40754E6660000000>, <4 x float>* undef
+ store <4 x float> <float 0x404D0CCCC0000000, float 3.955000e+02, float 0xC0334CCCC0000000, float 0x40754E6660000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp26 = load <4 x float>, <4 x float>* undef
+ %tmp26 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp27 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp27 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add628 = fadd <4 x float> %tmp27, %tmp26
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add628, <4 x float>* undef, align 16
+ store <4 x float> %add628, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp28 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp28 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext629 = extractelement <4 x float> %tmp28, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add630 = fadd float %vecext629, 0x40730CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp29 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp29 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins631 = insertelement <4 x float> %tmp29, float %add630, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins631, <4 x float>* undef, align 16
+ store <4 x float> %vecins631, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp30 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp30 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext632 = extractelement <4 x float> %tmp30, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add633 = fadd float %vecext632, 0xC0630999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp31 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp31 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins634 = insertelement <4 x float> %tmp31, float %add633, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins634, <4 x float>* undef, align 16
+ store <4 x float> %vecins634, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp32 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp32 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext635 = extractelement <4 x float> %tmp32, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add636 = fadd float %vecext635, 0xC078833340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp33 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp33 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp34 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp34 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp35 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp35 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add658 = fadd float undef, 0xC04A4CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext663 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp36 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp36 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins665 = insertelement <4 x float> %tmp36, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -359,17 +359,17 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add695 = fadd float %vecext694, 0xC03CCCCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp37 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp37 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins696 = insertelement <4 x float> %tmp37, float %add695, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins696, <4 x float>* undef, align 16
+ store <4 x float> %vecins696, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC069FCCCC0000000, float 0xC07C6E6660000000, float 0x4067E33340000000, float 0x4078DB3340000000>, <4 x float>* undef
+ store <4 x float> <float 0xC069FCCCC0000000, float 0xC07C6E6660000000, float 0x4067E33340000000, float 0x4078DB3340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp38 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp38 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext699 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -377,47 +377,47 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins704 = insertelement <4 x float> undef, float %add703, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins704, <4 x float>* undef, align 16
+ store <4 x float> %vecins704, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp39 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp39 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp40 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp40 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins710 = insertelement <4 x float> %tmp40, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins710, <4 x float>* undef, align 16
+ store <4 x float> %vecins710, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC05D9999A0000000, float 0x405D6CCCC0000000, float 0x40765CCCC0000000, float 0xC07C64CCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0xC05D9999A0000000, float 0x405D6CCCC0000000, float 0x40765CCCC0000000, float 0xC07C64CCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp41 = load <4 x float>, <4 x float>* undef
+ %tmp41 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp42 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp42 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add712 = fadd <4 x float> %tmp42, %tmp41
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add712, <4 x float>* undef, align 16
+ store <4 x float> %add712, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp43 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp43 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext713 = extractelement <4 x float> %tmp43, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp44 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp44 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins715 = insertelement <4 x float> %tmp44, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp45 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp45 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext716 = extractelement <4 x float> %tmp45, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add717 = fadd float %vecext716, -4.315000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp46 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp46 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins718 = insertelement <4 x float> %tmp46, float %add717, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins718, <4 x float>* undef, align 16
+ store <4 x float> %vecins718, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp47 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp47 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext719 = extractelement <4 x float> %tmp47, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -427,135 +427,135 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add726 = fadd <4 x float> undef, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext730 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add731 = fadd float %vecext730, 0xC0759CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp48 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp48 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins732 = insertelement <4 x float> %tmp48, float %add731, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins732, <4 x float>* undef, align 16
+ store <4 x float> %vecins732, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp49 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp49 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext733 = extractelement <4 x float> %tmp49, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp50 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp50 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins738 = insertelement <4 x float> %tmp50, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x406E6CCCC0000000, float 0xC07A766660000000, float 0xC0608CCCC0000000, float 0xC063333340000000>, <4 x float>* undef
+ store <4 x float> <float 0x406E6CCCC0000000, float 0xC07A766660000000, float 0xC0608CCCC0000000, float 0xC063333340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp51 = load <4 x float>, <4 x float>* undef
+ %tmp51 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add740 = fadd <4 x float> undef, %tmp51
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp52 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp52 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext741 = extractelement <4 x float> %tmp52, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add742 = fadd float %vecext741, 0xC07984CCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp53 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp53 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins743 = insertelement <4 x float> %tmp53, float %add742, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins743, <4 x float>* undef, align 16
+ store <4 x float> %vecins743, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp54 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp54 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp55 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp55 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add754 = fadd <4 x float> %tmp55, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add754, <4 x float>* undef, align 16
+ store <4 x float> %add754, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp56 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp56 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext755 = extractelement <4 x float> %tmp56, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add756 = fadd float %vecext755, 0xC070ACCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp57 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp57 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins757 = insertelement <4 x float> %tmp57, float %add756, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add765 = fadd float undef, 0x405BA66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp58 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp58 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins766 = insertelement <4 x float> %tmp58, float %add765, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp59 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp59 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext769 = extractelement <4 x float> %tmp59, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add770 = fadd float %vecext769, 0x40797199A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp60 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp60 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins771 = insertelement <4 x float> %tmp60, float %add770, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins771, <4 x float>* undef, align 16
+ store <4 x float> %vecins771, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp61 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp61 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add776 = fadd float undef, 0xC055F33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins777 = insertelement <4 x float> undef, float %add776, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp62 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp62 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp63 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp63 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add782 = fadd <4 x float> %tmp63, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add782, <4 x float>* undef, align 16
+ store <4 x float> %add782, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp64 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp64 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext783 = extractelement <4 x float> %tmp64, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add784 = fadd float %vecext783, -3.455000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC07A866660000000, float 0xC05CF999A0000000, float 0xC0757199A0000000, float -3.845000e+02>, <4 x float>* undef
+ store <4 x float> <float 0xC07A866660000000, float 0xC05CF999A0000000, float 0xC0757199A0000000, float -3.845000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add796 = fadd <4 x float> undef, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add796, <4 x float>* undef, align 16
+ store <4 x float> %add796, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp65 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp65 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add801 = fadd float undef, 3.045000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp66 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp66 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins802 = insertelement <4 x float> %tmp66, float %add801, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins802, <4 x float>* undef, align 16
+ store <4 x float> %vecins802, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext803 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp67 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp67 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp68 = load <4 x float>, <4 x float>* undef
+ %tmp68 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add810 = fadd <4 x float> undef, %tmp68
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add810, <4 x float>* undef, align 16
+ store <4 x float> %add810, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp69 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp69 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext811 = extractelement <4 x float> %tmp69, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp70 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp70 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins813 = insertelement <4 x float> %tmp70, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -565,31 +565,31 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins822 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins822, <4 x float>* undef, align 16
+ store <4 x float> %vecins822, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 2.700000e+01, float 0xC05F666660000000, float 0xC07D0199A0000000, float 0x407A6CCCC0000000>, <4 x float>* undef
+ store <4 x float> <float 2.700000e+01, float 0xC05F666660000000, float 0xC07D0199A0000000, float 0x407A6CCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp71 = load <4 x float>, <4 x float>* undef
+ %tmp71 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp72 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp72 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add824 = fadd <4 x float> %tmp72, %tmp71
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add838 = fadd <4 x float> undef, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add838, <4 x float>* undef, align 16
+ store <4 x float> %add838, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp73 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp73 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext839 = extractelement <4 x float> %tmp73, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add849 = fadd float undef, 0xC07C266660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC07D566660000000, float 0xC06D233340000000, float 0x4068B33340000000, float 0xC07ADCCCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0xC07D566660000000, float 0xC06D233340000000, float 0x4068B33340000000, float 0xC07ADCCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp74 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp74 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add852 = fadd <4 x float> %tmp74, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -597,43 +597,43 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add857 = fadd float %vecext856, 0xC070666660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp75 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp75 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp76 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp76 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext859 = extractelement <4 x float> %tmp76, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add860 = fadd float %vecext859, 4.705000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp77 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp77 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins861 = insertelement <4 x float> %tmp77, float %add860, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins889 = insertelement <4 x float> undef, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins889, <4 x float>* undef, align 16
+ store <4 x float> %vecins889, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp78 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp78 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext890 = extractelement <4 x float> %tmp78, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add891 = fadd float %vecext890, 0xC070633340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp79 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp79 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins892 = insertelement <4 x float> %tmp79, float %add891, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins892, <4 x float>* undef, align 16
+ store <4 x float> %vecins892, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x4063D33340000000, float 0xC076433340000000, float 0x407C966660000000, float 0xC07B5199A0000000>, <4 x float>* undef
+ store <4 x float> <float 0x4063D33340000000, float 0xC076433340000000, float 0x407C966660000000, float 0xC07B5199A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp80 = load <4 x float>, <4 x float>* undef
+ %tmp80 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp81 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp81 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add894 = fadd <4 x float> %tmp81, %tmp80
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add894, <4 x float>* undef, align 16
+ store <4 x float> %add894, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext895 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -641,7 +641,7 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins897 = insertelement <4 x float> undef, float %add896, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp82 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp82 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext898 = extractelement <4 x float> %tmp82, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -649,43 +649,43 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins900 = insertelement <4 x float> undef, float %add899, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp83 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp83 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext901 = extractelement <4 x float> %tmp83, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add902 = fadd float %vecext901, 0xC054ECCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp84 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp84 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins903 = insertelement <4 x float> %tmp84, float %add902, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins903, <4 x float>* undef, align 16
+ store <4 x float> %vecins903, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext904 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add905 = fadd float %vecext904, 0x4056A66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp85 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp85 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins906 = insertelement <4 x float> %tmp85, float %add905, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC07EFCCCC0000000, float 1.795000e+02, float 0x407E3E6660000000, float 0x4070633340000000>, <4 x float>* undef
+ store <4 x float> <float 0xC07EFCCCC0000000, float 1.795000e+02, float 0x407E3E6660000000, float 0x4070633340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp86 = load <4 x float>, <4 x float>* undef
+ %tmp86 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp87 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp87 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add908 = fadd <4 x float> %tmp87, %tmp86
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add908, <4 x float>* undef, align 16
+ store <4 x float> %add908, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp88 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp88 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp89 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp89 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp90 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp90 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext912 = extractelement <4 x float> %tmp90, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -693,41 +693,41 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins914 = insertelement <4 x float> undef, float %add913, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp91 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp91 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext915 = extractelement <4 x float> %tmp91, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add916 = fadd float %vecext915, -3.115000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp92 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp92 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins917 = insertelement <4 x float> %tmp92, float %add916, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins917, <4 x float>* undef, align 16
+ store <4 x float> %vecins917, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp93 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp93 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext918 = extractelement <4 x float> %tmp93, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add919 = fadd float %vecext918, 2.950000e+01
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp94 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp94 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins920 = insertelement <4 x float> %tmp94, float %add919, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins920, <4 x float>* undef, align 16
+ store <4 x float> %vecins920, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp95 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp95 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins925 = insertelement <4 x float> %tmp95, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins925, <4 x float>* undef, align 16
+ store <4 x float> %vecins925, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp96 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp96 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add927 = fadd float undef, 0xC0501999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp97 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp97 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins928 = insertelement <4 x float> %tmp97, float %add927, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -735,15 +735,15 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add930 = fadd float %vecext929, 0xC07C8B3340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp98 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp98 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins931 = insertelement <4 x float> %tmp98, float %add930, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC047B33340000000, float 0x404ACCCCC0000000, float 0x40708E6660000000, float 0x4060F999A0000000>, <4 x float>* undef
+ store <4 x float> <float 0xC047B33340000000, float 0x404ACCCCC0000000, float 0x40708E6660000000, float 0x4060F999A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp99 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp99 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp100 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp100 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext937 = extractelement <4 x float> %tmp100, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -751,73 +751,73 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins942 = insertelement <4 x float> undef, float %add941, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins942, <4 x float>* undef, align 16
+ store <4 x float> %vecins942, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp101 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp101 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext943 = extractelement <4 x float> %tmp101, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add944 = fadd float %vecext943, 4.580000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp102 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp102 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins945 = insertelement <4 x float> %tmp102, float %add944, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins945, <4 x float>* undef, align 16
+ store <4 x float> %vecins945, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp103 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp103 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add947 = fadd float undef, 0xC051933340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp104 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp104 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins948 = insertelement <4 x float> %tmp104, float %add947, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins948, <4 x float>* undef, align 16
+ store <4 x float> %vecins948, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x4060CCCCC0000000, float 0xC07BAB3340000000, float 0xC061233340000000, float 0xC076C199A0000000>, <4 x float>* undef
+ store <4 x float> <float 0x4060CCCCC0000000, float 0xC07BAB3340000000, float 0xC061233340000000, float 0xC076C199A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp105 = load <4 x float>, <4 x float>* undef
+ %tmp105 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add955 = fadd float undef, 0x4077F4CCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp106 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp106 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins956 = insertelement <4 x float> %tmp106, float %add955, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins956, <4 x float>* undef, align 16
+ store <4 x float> %vecins956, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext971 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add972 = fadd float %vecext971, 0x4024333340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp107 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp107 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins973 = insertelement <4 x float> %tmp107, float %add972, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins973, <4 x float>* undef, align 16
+ store <4 x float> %vecins973, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp108 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp108 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext974 = extractelement <4 x float> %tmp108, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins976 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins976, <4 x float>* undef, align 16
+ store <4 x float> %vecins976, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x407E266660000000, float -1.225000e+02, float 0x407EB199A0000000, float 0x407BA199A0000000>, <4 x float>* undef
+ store <4 x float> <float 0x407E266660000000, float -1.225000e+02, float 0x407EB199A0000000, float 0x407BA199A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp109 = load <4 x float>, <4 x float>* undef
+ %tmp109 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp110 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp110 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add978 = fadd <4 x float> %tmp110, %tmp109
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp111 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp111 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp112 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp112 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext982 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -825,173 +825,173 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins984 = insertelement <4 x float> undef, float %add983, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins984, <4 x float>* undef, align 16
+ store <4 x float> %vecins984, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp113 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp113 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext985 = extractelement <4 x float> %tmp113, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add986 = fadd float %vecext985, 0x406C8CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp114 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp114 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins987 = insertelement <4 x float> %tmp114, float %add986, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins987, <4 x float>* undef, align 16
+ store <4 x float> %vecins987, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp115 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp115 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp116 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp116 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins995 = insertelement <4 x float> %tmp116, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins995, <4 x float>* undef, align 16
+ store <4 x float> %vecins995, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp117 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp117 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add997 = fadd float undef, 0xC0798999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp118 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp118 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins998 = insertelement <4 x float> %tmp118, float %add997, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins998, <4 x float>* undef, align 16
+ store <4 x float> %vecins998, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp119 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp119 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1013 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1014 = fadd float %vecext1013, 3.105000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp120 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp120 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp121 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp121 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1016 = extractelement <4 x float> %tmp121, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1017 = fadd float %vecext1016, 0x406A1999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp122 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp122 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1030 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1031 = fadd float %vecext1030, 2.010000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp123 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp123 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp124 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp124 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1085 = insertelement <4 x float> %tmp124, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp125 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp125 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1086 = extractelement <4 x float> %tmp125, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1087 = fadd float %vecext1086, -1.575000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp126 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp126 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1088 = insertelement <4 x float> %tmp126, float %add1087, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1088, <4 x float>* undef, align 16
+ store <4 x float> %vecins1088, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp127 = load <4 x float>, <4 x float>* undef
+ %tmp127 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1090 = fadd <4 x float> undef, %tmp127
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp128 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp128 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1094 = extractelement <4 x float> %tmp128, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1095 = fadd float %vecext1094, 0x4072C999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp129 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp129 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1096 = insertelement <4 x float> %tmp129, float %add1095, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1096, <4 x float>* undef, align 16
+ store <4 x float> %vecins1096, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp130 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp130 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1097 = extractelement <4 x float> %tmp130, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1098 = fadd float %vecext1097, 0xC073E999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp131 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp131 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1099 = insertelement <4 x float> %tmp131, float %add1098, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1099, <4 x float>* undef, align 16
+ store <4 x float> %vecins1099, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp132 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp132 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1100 = extractelement <4 x float> %tmp132, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1101 = fadd float %vecext1100, 2.885000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp133 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp133 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1102 = insertelement <4 x float> %tmp133, float %add1101, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1102, <4 x float>* undef, align 16
+ store <4 x float> %vecins1102, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x4059866660000000, float 0x4072466660000000, float 0xC078FE6660000000, float 0xC058ACCCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0x4059866660000000, float 0x4072466660000000, float 0xC078FE6660000000, float 0xC058ACCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp134 = load <4 x float>, <4 x float>* undef
+ %tmp134 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1104 = fadd <4 x float> undef, %tmp134
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp135 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp135 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1105 = extractelement <4 x float> %tmp135, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1106 = fadd float %vecext1105, 0xC078A999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp136 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp136 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1107 = insertelement <4 x float> %tmp136, float %add1106, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1108 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp137 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp137 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1110 = insertelement <4 x float> %tmp137, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1110, <4 x float>* undef, align 16
+ store <4 x float> %vecins1110, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp138 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp138 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1111 = extractelement <4 x float> %tmp138, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1112 = fadd float %vecext1111, 0x407D566660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp139 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp139 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1113 = insertelement <4 x float> %tmp139, float %add1112, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1113, <4 x float>* undef, align 16
+ store <4 x float> %vecins1113, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1115 = fadd float undef, 0x4072B33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1116 = insertelement <4 x float> undef, float %add1115, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1116, <4 x float>* undef, align 16
+ store <4 x float> %vecins1116, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC0721999A0000000, float 0x4075633340000000, float 0x40794199A0000000, float 0x4061066660000000>, <4 x float>* undef
+ store <4 x float> <float 0xC0721999A0000000, float 0x4075633340000000, float 0x40794199A0000000, float 0x4061066660000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp140 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp140 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1118 = fadd <4 x float> %tmp140, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add1118, <4 x float>* undef, align 16
+ store <4 x float> %add1118, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp141 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp141 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1119 = extractelement <4 x float> %tmp141, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -999,15 +999,15 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1121 = insertelement <4 x float> undef, float %add1120, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1121, <4 x float>* undef, align 16
+ store <4 x float> %vecins1121, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp142 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp142 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1122 = extractelement <4 x float> %tmp142, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1123 = fadd float %vecext1122, 0x4072533340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp143 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp143 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1124 = insertelement <4 x float> %tmp143, float %add1123, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -1015,53 +1015,53 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1127 = insertelement <4 x float> undef, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1127, <4 x float>* undef, align 16
+ store <4 x float> %vecins1127, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp144 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp144 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1128 = extractelement <4 x float> %tmp144, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1129 = fadd float %vecext1128, 0x405C866660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp145 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp145 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1130 = insertelement <4 x float> %tmp145, float %add1129, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC06D6CCCC0000000, float 0xC032E66660000000, float -1.005000e+02, float 0x40765B3340000000>, <4 x float>* undef
+ store <4 x float> <float 0xC06D6CCCC0000000, float 0xC032E66660000000, float -1.005000e+02, float 0x40765B3340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp146 = load <4 x float>, <4 x float>* undef
+ %tmp146 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp147 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp147 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1132 = fadd <4 x float> %tmp147, %tmp146
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp148 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp148 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1133 = extractelement <4 x float> %tmp148, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1134 = fadd float %vecext1133, 0xC07EB999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp149 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp149 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1135 = insertelement <4 x float> %tmp149, float %add1134, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1135, <4 x float>* undef, align 16
+ store <4 x float> %vecins1135, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp150 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp150 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1136 = extractelement <4 x float> %tmp150, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp151 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp151 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1138 = insertelement <4 x float> %tmp151, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1138, <4 x float>* undef, align 16
+ store <4 x float> %vecins1138, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp152 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp152 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1140 = fadd float undef, 0x407AE999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp153 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp153 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1141 = insertelement <4 x float> %tmp153, float %add1140, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -1069,307 +1069,307 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1143 = fadd float %vecext1142, 0x407A24CCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp154 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp154 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1144 = insertelement <4 x float> %tmp154, float %add1143, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1144, <4 x float>* undef, align 16
+ store <4 x float> %vecins1144, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp155 = load <4 x float>, <4 x float>* undef
+ %tmp155 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp156 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp156 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1146 = fadd <4 x float> %tmp156, %tmp155
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add1146, <4 x float>* undef, align 16
+ store <4 x float> %add1146, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp157 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp157 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1148 = fadd float undef, 4.145000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp158 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp158 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1158 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1158, <4 x float>* undef, align 16
+ store <4 x float> %vecins1158, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40603999A0000000, float -9.150000e+01, float 0xC051E66660000000, float -4.825000e+02>, <4 x float>* undef
+ store <4 x float> <float 0x40603999A0000000, float -9.150000e+01, float 0xC051E66660000000, float -4.825000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1218 = fadd float undef, 0xC078733340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1219 = insertelement <4 x float> undef, float %add1218, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC0655CCCC0000000, float -4.900000e+01, float -4.525000e+02, float 4.205000e+02>, <4 x float>* undef
+ store <4 x float> <float 0xC0655CCCC0000000, float -4.900000e+01, float -4.525000e+02, float 4.205000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp159 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp159 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1279 = extractelement <4 x float> %tmp159, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1280 = fadd float %vecext1279, 0xC062D999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp160 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp160 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1281 = insertelement <4 x float> %tmp160, float %add1280, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1281, <4 x float>* undef, align 16
+ store <4 x float> %vecins1281, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp161 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp161 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1282 = extractelement <4 x float> %tmp161, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1283 = fadd float %vecext1282, 4.365000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp162 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp162 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1284 = insertelement <4 x float> %tmp162, float %add1283, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1284, <4 x float>* undef, align 16
+ store <4 x float> %vecins1284, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp163 = load <4 x float>, <4 x float>* undef
+ %tmp163 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp164 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp164 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1286 = fadd <4 x float> %tmp164, %tmp163
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add1286, <4 x float>* undef, align 16
+ store <4 x float> %add1286, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp165 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp165 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1288 = fadd float undef, 0xC0731199A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp166 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp166 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp167 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp167 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1444 = extractelement <4 x float> %tmp167, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1460 = insertelement <4 x float> undef, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1460, <4 x float>* undef, align 16
+ store <4 x float> %vecins1460, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp168 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp168 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1462 = fadd float undef, -1.670000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1463 = insertelement <4 x float> undef, float %add1462, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp169 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp169 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1464 = extractelement <4 x float> %tmp169, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1465 = fadd float %vecext1464, 0xC066333340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp170 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp170 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1466 = insertelement <4 x float> %tmp170, float %add1465, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1466, <4 x float>* undef, align 16
+ store <4 x float> %vecins1466, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 3.885000e+02, float 0x4054266660000000, float -9.500000e+01, float 8.500000e+01>, <4 x float>* undef
+ store <4 x float> <float 3.885000e+02, float 0x4054266660000000, float -9.500000e+01, float 8.500000e+01>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp171 = load <4 x float>, <4 x float>* undef
+ %tmp171 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp172 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp172 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1468 = fadd <4 x float> %tmp172, %tmp171
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add1468, <4 x float>* undef, align 16
+ store <4 x float> %add1468, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp173 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp173 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1470 = fadd float undef, 0x4033B33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp174 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp174 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1471 = insertelement <4 x float> %tmp174, float %add1470, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1471, <4 x float>* undef, align 16
+ store <4 x float> %vecins1471, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp175 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp175 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1472 = extractelement <4 x float> %tmp175, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1473 = fadd float %vecext1472, 0xC05F666660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp176 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp176 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1474 = insertelement <4 x float> %tmp176, float %add1473, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp177 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp177 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1475 = extractelement <4 x float> %tmp177, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp178 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp178 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1477 = insertelement <4 x float> %tmp178, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1477, <4 x float>* undef, align 16
+ store <4 x float> %vecins1477, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp179 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp179 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1478 = extractelement <4 x float> %tmp179, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1479 = fadd float %vecext1478, 0x407E2E6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp180 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp180 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1480 = insertelement <4 x float> %tmp180, float %add1479, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1480, <4 x float>* undef, align 16
+ store <4 x float> %vecins1480, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC061B33340000000, float 3.290000e+02, float 0xC067766660000000, float 0x407DB33340000000>, <4 x float>* undef
+ store <4 x float> <float 0xC061B33340000000, float 3.290000e+02, float 0xC067766660000000, float 0x407DB33340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp181 = load <4 x float>, <4 x float>* undef
+ %tmp181 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp182 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp182 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp183 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp183 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1483 = extractelement <4 x float> %tmp183, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1484 = fadd float %vecext1483, 0xC053D999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp184 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp184 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp185 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp185 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1486 = extractelement <4 x float> %tmp185, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1502 = insertelement <4 x float> undef, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1502, <4 x float>* undef, align 16
+ store <4 x float> %vecins1502, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1503 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1504 = fadd float %vecext1503, -2.475000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp186 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp186 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1505 = insertelement <4 x float> %tmp186, float %add1504, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1505, <4 x float>* undef, align 16
+ store <4 x float> %vecins1505, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp187 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp187 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1506 = extractelement <4 x float> %tmp187, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1507 = fadd float %vecext1506, 0x40715199A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp188 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp188 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1508 = insertelement <4 x float> %tmp188, float %add1507, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1508, <4 x float>* undef, align 16
+ store <4 x float> %vecins1508, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40762B3340000000, float 0xC074566660000000, float 0xC07C74CCC0000000, float 0xC053F999A0000000>, <4 x float>* undef
+ store <4 x float> <float 0x40762B3340000000, float 0xC074566660000000, float 0xC07C74CCC0000000, float 0xC053F999A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp189 = load <4 x float>, <4 x float>* undef
+ %tmp189 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp190 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp190 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1510 = fadd <4 x float> %tmp190, %tmp189
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add1510, <4 x float>* undef, align 16
+ store <4 x float> %add1510, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp191 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp191 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp192 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp192 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1654 = extractelement <4 x float> %tmp192, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1655 = fadd float %vecext1654, 0xC07D8CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp193 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp193 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1656 = insertelement <4 x float> %tmp193, float %add1655, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1656, <4 x float>* undef, align 16
+ store <4 x float> %vecins1656, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1658 = fadd float undef, 0x40709999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp194 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp194 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1660 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1661 = fadd float %vecext1660, 0xC06F166660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp195 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp195 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1662 = insertelement <4 x float> %tmp195, float %add1661, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1662, <4 x float>* undef, align 16
+ store <4 x float> %vecins1662, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC075266660000000, float 0xC072C4CCC0000000, float 0x407C4E6660000000, float -4.485000e+02>, <4 x float>* undef
+ store <4 x float> <float 0xC075266660000000, float 0xC072C4CCC0000000, float 0x407C4E6660000000, float -4.485000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1676 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp196 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp196 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1692 = fadd <4 x float> %tmp196, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add1692, <4 x float>* undef, align 16
+ store <4 x float> %add1692, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp197 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp197 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1693 = extractelement <4 x float> %tmp197, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1694 = fadd float %vecext1693, 0x407A1999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp198 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp198 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1695 = insertelement <4 x float> %tmp198, float %add1694, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1695, <4 x float>* undef, align 16
+ store <4 x float> %vecins1695, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp199 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp199 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1696 = extractelement <4 x float> %tmp199, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1697 = fadd float %vecext1696, 2.850000e+01
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp200 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp200 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1698 = insertelement <4 x float> %tmp200, float %add1697, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1698, <4 x float>* undef, align 16
+ store <4 x float> %vecins1698, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp201 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp201 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1699 = extractelement <4 x float> %tmp201, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp202 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp202 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1701 = insertelement <4 x float> %tmp202, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1701, <4 x float>* undef, align 16
+ store <4 x float> %vecins1701, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp203 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp203 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1704 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC075933340000000, float 0xC0489999A0000000, float 0xC078AB3340000000, float 0x406DFCCCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0xC075933340000000, float 0xC0489999A0000000, float 0xC078AB3340000000, float 0x406DFCCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp204 = load <4 x float>, <4 x float>* undef
+ %tmp204 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp205 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp205 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp206 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp206 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1709 = insertelement <4 x float> %tmp206, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1709, <4 x float>* undef, align 16
+ store <4 x float> %vecins1709, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp207 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp207 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1713 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -1377,163 +1377,163 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1723 = insertelement <4 x float> undef, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp208 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp208 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1730 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1731 = fadd float %vecext1730, 4.130000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp209 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp209 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1732 = insertelement <4 x float> %tmp209, float %add1731, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1732, <4 x float>* undef, align 16
+ store <4 x float> %vecins1732, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40551999A0000000, float 0xC0708999A0000000, float 0xC054F33340000000, float 0xC07C5999A0000000>, <4 x float>* undef
+ store <4 x float> <float 0x40551999A0000000, float 0xC0708999A0000000, float 0xC054F33340000000, float 0xC07C5999A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp210 = load <4 x float>, <4 x float>* undef
+ %tmp210 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1734 = fadd <4 x float> undef, %tmp210
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp211 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp211 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1736 = fadd float undef, 0x407C3999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp212 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp212 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1737 = insertelement <4 x float> %tmp212, float %add1736, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp213 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp213 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1738 = extractelement <4 x float> %tmp213, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1739 = fadd float %vecext1738, 0xC0711E6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp214 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp214 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1740 = insertelement <4 x float> %tmp214, float %add1739, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1740, <4 x float>* undef, align 16
+ store <4 x float> %vecins1740, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp215 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp215 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1741 = extractelement <4 x float> %tmp215, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1742 = fadd float %vecext1741, -2.545000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp216 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp216 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1743 = insertelement <4 x float> %tmp216, float %add1742, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1743, <4 x float>* undef, align 16
+ store <4 x float> %vecins1743, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1744 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp217 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp217 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1746 = insertelement <4 x float> %tmp217, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC076466660000000, float 0x4060BCCCC0000000, float 0x405EF999A0000000, float 0x4074766660000000>, <4 x float>* undef
+ store <4 x float> <float 0xC076466660000000, float 0x4060BCCCC0000000, float 0x405EF999A0000000, float 0x4074766660000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp218 = load <4 x float>, <4 x float>* undef
+ %tmp218 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1748 = fadd <4 x float> undef, %tmp218
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add1748, <4 x float>* undef, align 16
+ store <4 x float> %add1748, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp219 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp219 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1750 = fadd float undef, 0x407C6B3340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1751 = insertelement <4 x float> undef, float %add1750, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp220 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp220 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1752 = extractelement <4 x float> %tmp220, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1753 = fadd float %vecext1752, 0x40730CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp221 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp221 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1754 = insertelement <4 x float> %tmp221, float %add1753, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp222 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp222 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1755 = extractelement <4 x float> %tmp222, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1756 = fadd float %vecext1755, 0xC059F33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp223 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp223 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1759 = fadd float undef, 0x40678999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp224 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp224 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1760 = insertelement <4 x float> %tmp224, float %add1759, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1760, <4 x float>* undef, align 16
+ store <4 x float> %vecins1760, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x405E333340000000, float 0x40571999A0000000, float 0xC02E333340000000, float 0x4053A66660000000>, <4 x float>* undef
+ store <4 x float> <float 0x405E333340000000, float 0x40571999A0000000, float 0xC02E333340000000, float 0x4053A66660000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp225 = load <4 x float>, <4 x float>* undef
+ %tmp225 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1762 = fadd <4 x float> undef, %tmp225
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add1762, <4 x float>* undef, align 16
+ store <4 x float> %add1762, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp226 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp226 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1763 = extractelement <4 x float> %tmp226, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1764 = fadd float %vecext1763, 0xC0299999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp227 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp227 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1765 = insertelement <4 x float> %tmp227, float %add1764, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1765, <4 x float>* undef, align 16
+ store <4 x float> %vecins1765, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp228 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp228 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1766 = extractelement <4 x float> %tmp228, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1767 = fadd float %vecext1766, 0x407DDE6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp229 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp229 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1768 = insertelement <4 x float> %tmp229, float %add1767, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1768, <4 x float>* undef, align 16
+ store <4 x float> %vecins1768, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1769 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1770 = fadd float %vecext1769, 0x407A1B3340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp230 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp230 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1771 = insertelement <4 x float> %tmp230, float %add1770, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1771, <4 x float>* undef, align 16
+ store <4 x float> %vecins1771, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp231 = load <4 x float>, <4 x float>* undef
+ %tmp231 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp232 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp232 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp233 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp233 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp234 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp234 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1779 = insertelement <4 x float> %tmp234, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1779, <4 x float>* undef, align 16
+ store <4 x float> %vecins1779, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp235 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp235 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp236 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp236 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1783 = extractelement <4 x float> %tmp236, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -1541,31 +1541,31 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1785 = insertelement <4 x float> undef, float %add1784, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1785, <4 x float>* undef, align 16
+ store <4 x float> %vecins1785, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC07074CCC0000000, float 0xC04D666660000000, float 3.235000e+02, float 0xC0724199A0000000>, <4 x float>* undef
+ store <4 x float> <float 0xC07074CCC0000000, float 0xC04D666660000000, float 3.235000e+02, float 0xC0724199A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp237 = load <4 x float>, <4 x float>* undef
+ %tmp237 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1790 = fadd <4 x float> undef, %tmp237
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp238 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp238 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1791 = extractelement <4 x float> %tmp238, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1792 = fadd float %vecext1791, 0x4077DE6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp239 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp239 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1793 = insertelement <4 x float> %tmp239, float %add1792, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1793, <4 x float>* undef, align 16
+ store <4 x float> %vecins1793, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp240 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp240 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1795 = fadd float undef, 0x4055266660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp241 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp241 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1796 = insertelement <4 x float> %tmp241, float %add1795, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -1573,59 +1573,59 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1800 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp242 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp242 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float -6.600000e+01, float 0xC07B2199A0000000, float 0x4011333340000000, float 0xC0635CCCC0000000>, <4 x float>* undef
+ store <4 x float> <float -6.600000e+01, float 0xC07B2199A0000000, float 0x4011333340000000, float 0xC0635CCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp243 = load <4 x float>, <4 x float>* undef
+ %tmp243 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp244 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp244 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp245 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp245 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp246 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp246 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1865 = fadd float undef, -2.235000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp247 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp247 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1866 = insertelement <4 x float> %tmp247, float %add1865, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp248 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp248 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp249 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp249 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1872 = insertelement <4 x float> %tmp249, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x406B8999A0000000, float 0xC0696CCCC0000000, float 0xC07A34CCC0000000, float 0x407654CCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0x406B8999A0000000, float 0xC0696CCCC0000000, float 0xC07A34CCC0000000, float 0x407654CCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp250 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp250 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1874 = fadd <4 x float> %tmp250, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add1874, <4 x float>* undef, align 16
+ store <4 x float> %add1874, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1875 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp251 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp251 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1894 = insertelement <4 x float> %tmp251, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp252 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp252 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1895 = extractelement <4 x float> %tmp252, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1900 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1900, <4 x float>* undef, align 16
+ store <4 x float> %vecins1900, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1905 = insertelement <4 x float> undef, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1905, <4 x float>* undef, align 16
+ store <4 x float> %vecins1905, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp253 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp253 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1906 = extractelement <4 x float> %tmp253, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -1633,61 +1633,61 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1908 = insertelement <4 x float> undef, float %add1907, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1908, <4 x float>* undef, align 16
+ store <4 x float> %vecins1908, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1909 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp254 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp254 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1912 = extractelement <4 x float> %tmp254, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1913 = fadd float %vecext1912, 0xC063ECCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp255 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp255 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp256 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp256 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1916 = fadd <4 x float> %tmp256, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add1916, <4 x float>* undef, align 16
+ store <4 x float> %add1916, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1923 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp257 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp257 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1927 = fadd float undef, 0x40761999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp258 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp258 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1928 = insertelement <4 x float> %tmp258, float %add1927, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1928, <4 x float>* undef, align 16
+ store <4 x float> %vecins1928, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 7.100000e+01, float 0xC0634999A0000000, float 0x407B0B3340000000, float 0xC07DE999A0000000>, <4 x float>* undef
+ store <4 x float> <float 7.100000e+01, float 0xC0634999A0000000, float 0x407B0B3340000000, float 0xC07DE999A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp259 = load <4 x float>, <4 x float>* undef
+ %tmp259 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp260 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp260 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1930 = fadd <4 x float> %tmp260, %tmp259
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp261 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp261 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp262 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp262 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1933 = insertelement <4 x float> %tmp262, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1933, <4 x float>* undef, align 16
+ store <4 x float> %vecins1933, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp263 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp263 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1934 = extractelement <4 x float> %tmp263, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1935 = fadd float %vecext1934, 0xC07D3199A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp264 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp264 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1936 = insertelement <4 x float> %tmp264, float %add1935, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -1695,15 +1695,15 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1942 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float -8.200000e+01, float 0xC04C733340000000, float 0xC077ACCCC0000000, float 0x4074566660000000>, <4 x float>* undef
+ store <4 x float> <float -8.200000e+01, float 0xC04C733340000000, float 0xC077ACCCC0000000, float 0x4074566660000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp265 = load <4 x float>, <4 x float>* undef
+ %tmp265 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp266 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp266 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp267 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp267 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1945 = extractelement <4 x float> %tmp267, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -1711,19 +1711,19 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1953 = insertelement <4 x float> undef, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1953, <4 x float>* undef, align 16
+ store <4 x float> %vecins1953, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp268 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp268 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp269 = load <4 x float>, <4 x float>* undef
+ %tmp269 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp270 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp270 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1958 = fadd <4 x float> %tmp270, %tmp269
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp271 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp271 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1959 = extractelement <4 x float> %tmp271, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -1733,65 +1733,65 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1963 = fadd float %vecext1962, 0xC07134CCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp272 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp272 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1964 = insertelement <4 x float> %tmp272, float %add1963, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1964, <4 x float>* undef, align 16
+ store <4 x float> %vecins1964, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1965 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp273 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp273 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1967 = insertelement <4 x float> %tmp273, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1967, <4 x float>* undef, align 16
+ store <4 x float> %vecins1967, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp274 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp274 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1968 = extractelement <4 x float> %tmp274, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1969 = fadd float %vecext1968, 7.100000e+01
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp275 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp275 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1970 = insertelement <4 x float> %tmp275, float %add1969, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1970, <4 x float>* undef, align 16
+ store <4 x float> %vecins1970, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x402E9999A0000000, float 0x407344CCC0000000, float -4.165000e+02, float 0x4078FCCCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0x402E9999A0000000, float 0x407344CCC0000000, float -4.165000e+02, float 0x4078FCCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp276 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp276 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp277 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp277 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp278 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp278 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1975 = insertelement <4 x float> %tmp278, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1975, <4 x float>* undef, align 16
+ store <4 x float> %vecins1975, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp279 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp279 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1976 = extractelement <4 x float> %tmp279, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1978 = insertelement <4 x float> undef, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1978, <4 x float>* undef, align 16
+ store <4 x float> %vecins1978, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1979 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1981 = insertelement <4 x float> undef, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1981, <4 x float>* undef, align 16
+ store <4 x float> %vecins1981, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1984 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1984, <4 x float>* undef, align 16
+ store <4 x float> %vecins1984, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC06A766660000000, float 0xC07CE4CCC0000000, float -1.055000e+02, float 0x40786E6660000000>, <4 x float>* undef
+ store <4 x float> <float 0xC06A766660000000, float 0xC07CE4CCC0000000, float -1.055000e+02, float 0x40786E6660000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext1990 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -1799,143 +1799,143 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add1997 = fadd float %vecext1996, -1.400000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp280 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp280 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins1998 = insertelement <4 x float> %tmp280, float %add1997, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins1998, <4 x float>* undef, align 16
+ store <4 x float> %vecins1998, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC0794E6660000000, float 0xC073CCCCC0000000, float 0x407994CCC0000000, float 6.500000e+01>, <4 x float>* undef
+ store <4 x float> <float 0xC0794E6660000000, float 0xC073CCCCC0000000, float 0x407994CCC0000000, float 6.500000e+01>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2004 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2005 = fadd float %vecext2004, -1.970000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp281 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp281 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2006 = insertelement <4 x float> %tmp281, float %add2005, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2006, <4 x float>* undef, align 16
+ store <4 x float> %vecins2006, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp282 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp282 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2007 = extractelement <4 x float> %tmp282, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp283 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp283 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2009 = insertelement <4 x float> %tmp283, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp284 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp284 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2010 = extractelement <4 x float> %tmp284, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2011 = fadd float %vecext2010, 0xC074533340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp285 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp285 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2012 = insertelement <4 x float> %tmp285, float %add2011, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2012, <4 x float>* undef, align 16
+ store <4 x float> %vecins2012, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC04E733340000000, float 0xC074566660000000, float 0x4079F66660000000, float 0xC0705B3340000000>, <4 x float>* undef
+ store <4 x float> <float 0xC04E733340000000, float 0xC074566660000000, float 0x4079F66660000000, float 0xC0705B3340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp286 = load <4 x float>, <4 x float>* undef
+ %tmp286 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp287 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp287 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp288 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp288 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2015 = extractelement <4 x float> %tmp288, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2016 = fadd float %vecext2015, 0xC060633340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp289 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp289 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2017 = insertelement <4 x float> %tmp289, float %add2016, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2022 = fadd float undef, 8.350000e+01
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp290 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp290 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2023 = insertelement <4 x float> %tmp290, float %add2022, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp291 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp291 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2024 = extractelement <4 x float> %tmp291, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp292 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp292 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2028 = fadd <4 x float> %tmp292, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add2028, <4 x float>* undef, align 16
+ store <4 x float> %add2028, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2029 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2030 = fadd float %vecext2029, -9.450000e+01
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp293 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp293 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp294 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp294 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2036 = fadd float undef, 0x407DE66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp295 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp295 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp296 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp296 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp297 = load <4 x float>, <4 x float>* undef
+ %tmp297 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp298 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp298 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp299 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp299 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2045 = insertelement <4 x float> %tmp299, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2045, <4 x float>* undef, align 16
+ store <4 x float> %vecins2045, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp300 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp300 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2046 = extractelement <4 x float> %tmp300, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2047 = fadd float %vecext2046, 0xC065433340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2052 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp301 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp301 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2054 = insertelement <4 x float> %tmp301, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2054, <4 x float>* undef, align 16
+ store <4 x float> %vecins2054, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x4024666660000000, float 0x4079366660000000, float 0x40721B3340000000, float 0x406E533340000000>, <4 x float>* undef
+ store <4 x float> <float 0x4024666660000000, float 0x4079366660000000, float 0x40721B3340000000, float 0x406E533340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp302 = load <4 x float>, <4 x float>* undef
+ %tmp302 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2056 = fadd <4 x float> undef, %tmp302
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add2056, <4 x float>* undef, align 16
+ store <4 x float> %add2056, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp303 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp303 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp304 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp304 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2062 = insertelement <4 x float> %tmp304, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2062, <4 x float>* undef, align 16
+ store <4 x float> %vecins2062, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp305 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp305 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp306 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp306 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2066 = extractelement <4 x float> %tmp306, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -1943,71 +1943,71 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2068 = insertelement <4 x float> undef, float %add2067, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2068, <4 x float>* undef, align 16
+ store <4 x float> %vecins2068, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC07EFCCCC0000000, float -3.420000e+02, float 0xC07BC999A0000000, float 0x40751999A0000000>, <4 x float>* undef
+ store <4 x float> <float 0xC07EFCCCC0000000, float -3.420000e+02, float 0xC07BC999A0000000, float 0x40751999A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp307 = load <4 x float>, <4 x float>* undef
+ %tmp307 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp308 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp308 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2070 = fadd <4 x float> %tmp308, %tmp307
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add2070, <4 x float>* undef, align 16
+ store <4 x float> %add2070, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp309 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp309 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2071 = extractelement <4 x float> %tmp309, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2072 = fadd float %vecext2071, 0x4057733340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp310 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp310 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2073 = insertelement <4 x float> %tmp310, float %add2072, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2073, <4 x float>* undef, align 16
+ store <4 x float> %vecins2073, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp311 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp311 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2074 = extractelement <4 x float> %tmp311, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp312 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp312 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2076 = insertelement <4 x float> %tmp312, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp313 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp313 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2077 = extractelement <4 x float> %tmp313, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2078 = fadd float %vecext2077, 0x4061F999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp314 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp314 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2079 = insertelement <4 x float> %tmp314, float %add2078, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2079, <4 x float>* undef, align 16
+ store <4 x float> %vecins2079, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp315 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp315 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2080 = extractelement <4 x float> %tmp315, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2081 = fadd float %vecext2080, 0x407A1B3340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp316 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp316 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2082 = insertelement <4 x float> %tmp316, float %add2081, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2082, <4 x float>* undef, align 16
+ store <4 x float> %vecins2082, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40764E6660000000, float 0x40501999A0000000, float 0xC079A4CCC0000000, float 0x4050533340000000>, <4 x float>* undef
+ store <4 x float> <float 0x40764E6660000000, float 0x40501999A0000000, float 0xC079A4CCC0000000, float 0x4050533340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp317 = load <4 x float>, <4 x float>* undef
+ %tmp317 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp318 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp318 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp319 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp319 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2085 = extractelement <4 x float> %tmp319, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -2015,7 +2015,7 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2087 = insertelement <4 x float> undef, float %add2086, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2087, <4 x float>* undef, align 16
+ store <4 x float> %vecins2087, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2480 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -2025,59 +2025,59 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2484 = fadd float %vecext2483, 0xC06A3999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp320 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp320 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2485 = insertelement <4 x float> %tmp320, float %add2484, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2485, <4 x float>* undef, align 16
+ store <4 x float> %vecins2485, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp321 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp321 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2487 = fadd float undef, 2.030000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp322 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp322 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x4073DE6660000000, float 0x4067CCCCC0000000, float 0xC03F1999A0000000, float 4.350000e+01>, <4 x float>* undef
+ store <4 x float> <float 0x4073DE6660000000, float 0x4067CCCCC0000000, float 0xC03F1999A0000000, float 4.350000e+01>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2491 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp323 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp323 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp324 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp324 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2494 = extractelement <4 x float> %tmp324, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2495 = fadd float %vecext2494, 0xC0743CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp325 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp325 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2499 = insertelement <4 x float> undef, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2499, <4 x float>* undef, align 16
+ store <4 x float> %vecins2499, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2500 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2501 = fadd float %vecext2500, 0x40796E6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp326 = load <4 x float>, <4 x float>* undef
+ %tmp326 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp327 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp327 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2508 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2518 = fadd <4 x float> undef, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp328 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp328 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2519 = extractelement <4 x float> %tmp328, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2520 = fadd float %vecext2519, 0xC0399999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp329 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp329 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2534 = fadd float undef, 0x4072C66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -2085,11 +2085,11 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2537 = fadd float %vecext2536, 0x407D066660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp330 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp330 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2538 = insertelement <4 x float> %tmp330, float %add2537, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2538, <4 x float>* undef, align 16
+ store <4 x float> %vecins2538, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2539 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -2097,9 +2097,9 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2580 = insertelement <4 x float> undef, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2580, <4 x float>* undef, align 16
+ store <4 x float> %vecins2580, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp331 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp331 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2581 = extractelement <4 x float> %tmp331, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -2107,107 +2107,107 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2583 = insertelement <4 x float> undef, float %add2582, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2583, <4 x float>* undef, align 16
+ store <4 x float> %vecins2583, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2584 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2585 = fadd float %vecext2584, 3.585000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp332 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp332 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40773199A0000000, float 0x407D7999A0000000, float 0xC0717199A0000000, float 0xC07E9CCCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0x40773199A0000000, float 0x407D7999A0000000, float 0xC0717199A0000000, float 0xC07E9CCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2590 = fadd float undef, 0x407B1999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp333 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp333 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp334 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp334 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2672 = fadd <4 x float> undef, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add2672, <4 x float>* undef, align 16
+ store <4 x float> %add2672, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp335 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp335 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2676 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2677 = fadd float %vecext2676, 0x406D6999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp336 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp336 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2678 = insertelement <4 x float> %tmp336, float %add2677, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2678, <4 x float>* undef, align 16
+ store <4 x float> %vecins2678, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp337 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp337 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2679 = extractelement <4 x float> %tmp337, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2681 = insertelement <4 x float> undef, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2681, <4 x float>* undef, align 16
+ store <4 x float> %vecins2681, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp338 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp338 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2682 = extractelement <4 x float> %tmp338, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2684 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp339 = load <4 x float>, <4 x float>* undef
+ %tmp339 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp340 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp340 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp341 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp341 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2688 = fadd float undef, 0x4063266660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2692 = insertelement <4 x float> undef, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2692, <4 x float>* undef, align 16
+ store <4 x float> %vecins2692, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp342 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp342 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2696 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2697 = fadd float %vecext2696, 4.140000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp343 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp343 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins2698 = insertelement <4 x float> %tmp343, float %add2697, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins2698, <4 x float>* undef, align 16
+ store <4 x float> %vecins2698, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40547999A0000000, float 0xC060633340000000, float 0x4075766660000000, float 0x4072D33340000000>, <4 x float>* undef
+ store <4 x float> <float 0x40547999A0000000, float 0xC060633340000000, float 0x4075766660000000, float 0x4072D33340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp344 = load <4 x float>, <4 x float>* undef
+ %tmp344 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp345 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp345 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2700 = fadd <4 x float> %tmp345, %tmp344
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add2700, <4 x float>* undef, align 16
+ store <4 x float> %add2700, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp346 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp346 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp347 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp347 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp348 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp348 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext2704 = extractelement <4 x float> %tmp348, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add2705 = fadd float %vecext2704, 4.700000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp349 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp349 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3121 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -2215,93 +2215,93 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3126 = insertelement <4 x float> undef, float %add3125, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3126, <4 x float>* undef, align 16
+ store <4 x float> %vecins3126, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp350 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp350 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3127 = extractelement <4 x float> %tmp350, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3128 = fadd float %vecext3127, 0x40638999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp351 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp351 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3129 = insertelement <4 x float> %tmp351, float %add3128, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3129, <4 x float>* undef, align 16
+ store <4 x float> %vecins3129, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp352 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp352 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3131 = fadd float undef, 3.215000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp353 = load <4 x float>, <4 x float>* undef
+ %tmp353 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp354 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp354 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3134 = fadd <4 x float> %tmp354, %tmp353
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add3134, <4 x float>* undef, align 16
+ store <4 x float> %add3134, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp355 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp355 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3136 = fadd float undef, 0x4074333340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3140 = insertelement <4 x float> undef, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3140, <4 x float>* undef, align 16
+ store <4 x float> %vecins3140, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp356 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp356 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3141 = extractelement <4 x float> %tmp356, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3142 = fadd float %vecext3141, 2.425000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp357 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp357 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3143 = insertelement <4 x float> %tmp357, float %add3142, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3143, <4 x float>* undef, align 16
+ store <4 x float> %vecins3143, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp358 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp358 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3144 = extractelement <4 x float> %tmp358, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3145 = fadd float %vecext3144, -3.760000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp359 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp359 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3146 = insertelement <4 x float> %tmp359, float %add3145, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3146, <4 x float>* undef, align 16
+ store <4 x float> %vecins3146, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp360 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp360 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3272 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3272, <4 x float>* undef, align 16
+ store <4 x float> %vecins3272, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x407B4999A0000000, float 0x40695CCCC0000000, float 0xC05C0CCCC0000000, float 0x407EB33340000000>, <4 x float>* undef
+ store <4 x float> <float 0x407B4999A0000000, float 0x40695CCCC0000000, float 0xC05C0CCCC0000000, float 0x407EB33340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp361 = load <4 x float>, <4 x float>* undef
+ %tmp361 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp362 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp362 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3274 = fadd <4 x float> %tmp362, %tmp361
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add3274, <4 x float>* undef, align 16
+ store <4 x float> %add3274, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp363 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp363 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3275 = extractelement <4 x float> %tmp363, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3276 = fadd float %vecext3275, 0x4058066660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp364 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp364 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3277 = insertelement <4 x float> %tmp364, float %add3276, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3277, <4 x float>* undef, align 16
+ store <4 x float> %vecins3277, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp365 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp365 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3278 = extractelement <4 x float> %tmp365, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -2309,21 +2309,21 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3280 = insertelement <4 x float> undef, float %add3279, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3280, <4 x float>* undef, align 16
+ store <4 x float> %vecins3280, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp366 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp366 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3281 = extractelement <4 x float> %tmp366, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3282 = fadd float %vecext3281, 0xC0650CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp367 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp367 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3283 = insertelement <4 x float> %tmp367, float %add3282, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3283, <4 x float>* undef, align 16
+ store <4 x float> %vecins3283, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp368 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp368 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3284 = extractelement <4 x float> %tmp368, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -2331,43 +2331,43 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3286 = insertelement <4 x float> undef, float %add3285, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp369 = load <4 x float>, <4 x float>* undef
+ %tmp369 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp370 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp370 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3289 = extractelement <4 x float> %tmp370, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3290 = fadd float %vecext3289, 0xC07E133340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp371 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp371 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3291 = insertelement <4 x float> %tmp371, float %add3290, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3291, <4 x float>* undef, align 16
+ store <4 x float> %vecins3291, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3292 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp372 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp372 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp373 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp373 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3328 = insertelement <4 x float> %tmp373, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3330 = fadd <4 x float> undef, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add3330, <4 x float>* undef, align 16
+ store <4 x float> %add3330, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3331 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3332 = fadd float %vecext3331, 0x4061633340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp374 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp374 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3333 = insertelement <4 x float> %tmp374, float %add3332, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3333, <4 x float>* undef, align 16
+ store <4 x float> %vecins3333, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3334 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -2375,39 +2375,39 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3336 = insertelement <4 x float> undef, float %add3335, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp375 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp375 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3337 = extractelement <4 x float> %tmp375, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3338 = fadd float %vecext3337, 0x403C4CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp376 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp376 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3339 = insertelement <4 x float> %tmp376, float %add3338, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3339, <4 x float>* undef, align 16
+ store <4 x float> %vecins3339, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp377 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp377 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3340 = extractelement <4 x float> %tmp377, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp378 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp378 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3342 = insertelement <4 x float> %tmp378, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp379 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp379 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3344 = fadd <4 x float> %tmp379, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add3344, <4 x float>* undef, align 16
+ store <4 x float> %add3344, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp380 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp380 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3345 = extractelement <4 x float> %tmp380, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3346 = fadd float %vecext3345, 0x407E7E6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp381 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp381 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3347 = insertelement <4 x float> %tmp381, float %add3346, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -2415,123 +2415,123 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3349 = fadd float %vecext3348, 0xC05F666660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp382 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp382 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3350 = insertelement <4 x float> %tmp382, float %add3349, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3350, <4 x float>* undef, align 16
+ store <4 x float> %vecins3350, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3352 = fadd float undef, 0xC06ACCCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp383 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp383 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3423 = insertelement <4 x float> undef, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3423, <4 x float>* undef, align 16
+ store <4 x float> %vecins3423, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3424 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3425 = fadd float %vecext3424, 0xC05DB33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp384 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp384 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3426 = insertelement <4 x float> %tmp384, float %add3425, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3426, <4 x float>* undef, align 16
+ store <4 x float> %vecins3426, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 2.795000e+02, float -4.065000e+02, float 0xC05CD999A0000000, float 1.825000e+02>, <4 x float>* undef
+ store <4 x float> <float 2.795000e+02, float -4.065000e+02, float 0xC05CD999A0000000, float 1.825000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp385 = load <4 x float>, <4 x float>* undef
+ %tmp385 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp386 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp386 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3428 = fadd <4 x float> %tmp386, %tmp385
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp387 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp387 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3429 = extractelement <4 x float> %tmp387, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3430 = fadd float %vecext3429, 0x40695CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp388 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp388 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3431 = insertelement <4 x float> %tmp388, float %add3430, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3431, <4 x float>* undef, align 16
+ store <4 x float> %vecins3431, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp389 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp389 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3432 = extractelement <4 x float> %tmp389, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3433 = fadd float %vecext3432, 0x4052A66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp390 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp390 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3434 = insertelement <4 x float> %tmp390, float %add3433, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3434, <4 x float>* undef, align 16
+ store <4 x float> %vecins3434, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3435 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp391 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp391 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3437 = insertelement <4 x float> %tmp391, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3437, <4 x float>* undef, align 16
+ store <4 x float> %vecins3437, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp392 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp392 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3438 = extractelement <4 x float> %tmp392, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3439 = fadd float %vecext3438, 0xC071D999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC0798199A0000000, float -3.385000e+02, float 0xC050066660000000, float 0xC075E999A0000000>, <4 x float>* undef
+ store <4 x float> <float 0xC0798199A0000000, float -3.385000e+02, float 0xC050066660000000, float 0xC075E999A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp393 = load <4 x float>, <4 x float>* undef
+ %tmp393 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp394 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp394 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3442 = fadd <4 x float> %tmp394, %tmp393
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add3442, <4 x float>* undef, align 16
+ store <4 x float> %add3442, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3443 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3444 = fadd float %vecext3443, 0xC07CF999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp395 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp395 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3446 = extractelement <4 x float> %tmp395, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3447 = fadd float %vecext3446, 0xC06E4999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp396 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp396 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3448 = insertelement <4 x float> %tmp396, float %add3447, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3448, <4 x float>* undef, align 16
+ store <4 x float> %vecins3448, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp397 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp397 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3449 = extractelement <4 x float> %tmp397, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3450 = fadd float %vecext3449, 0x40779B3340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp398 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp398 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3451 = insertelement <4 x float> %tmp398, float %add3450, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3451, <4 x float>* undef, align 16
+ store <4 x float> %vecins3451, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3453 = fadd float undef, 0xC07ADCCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp399 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp399 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3454 = insertelement <4 x float> %tmp399, float %add3453, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3454, <4 x float>* undef, align 16
+ store <4 x float> %vecins3454, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp400 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp400 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3457 = extractelement <4 x float> %tmp400, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -2539,115 +2539,115 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3459 = insertelement <4 x float> undef, float %add3458, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3459, <4 x float>* undef, align 16
+ store <4 x float> %vecins3459, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp401 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp401 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3460 = extractelement <4 x float> %tmp401, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp402 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp402 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3462 = insertelement <4 x float> %tmp402, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3462, <4 x float>* undef, align 16
+ store <4 x float> %vecins3462, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp403 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp403 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3464 = fadd float undef, 0xC057B999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp404 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp404 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3465 = insertelement <4 x float> %tmp404, float %add3464, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3465, <4 x float>* undef, align 16
+ store <4 x float> %vecins3465, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp405 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp405 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3466 = extractelement <4 x float> %tmp405, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3467 = fadd float %vecext3466, 0xC07A9CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp406 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp406 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x405C3999A0000000, float 0xC07C6B3340000000, float 0x407ACB3340000000, float 0xC06E0999A0000000>, <4 x float>* undef
+ store <4 x float> <float 0x405C3999A0000000, float 0xC07C6B3340000000, float 0x407ACB3340000000, float 0xC06E0999A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp407 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp407 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp408 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp408 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3477 = extractelement <4 x float> %tmp408, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3479 = insertelement <4 x float> undef, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3479, <4 x float>* undef, align 16
+ store <4 x float> %vecins3479, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3480 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3481 = fadd float %vecext3480, 0xC053F33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp409 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp409 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3482 = insertelement <4 x float> %tmp409, float %add3481, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3482, <4 x float>* undef, align 16
+ store <4 x float> %vecins3482, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 3.565000e+02, float 0xC0464CCCC0000000, float 0x4037666660000000, float 0xC0788CCCC0000000>, <4 x float>* undef
+ store <4 x float> <float 3.565000e+02, float 0xC0464CCCC0000000, float 0x4037666660000000, float 0xC0788CCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp410 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp410 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3484 = fadd <4 x float> %tmp410, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add3484, <4 x float>* undef, align 16
+ store <4 x float> %add3484, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp411 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp411 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3486 = fadd float undef, -1.415000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3487 = insertelement <4 x float> undef, float %add3486, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3487, <4 x float>* undef, align 16
+ store <4 x float> %vecins3487, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp412 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp412 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3488 = extractelement <4 x float> %tmp412, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3489 = fadd float %vecext3488, 0x405A1999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp413 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp413 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3490 = insertelement <4 x float> %tmp413, float %add3489, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3490, <4 x float>* undef, align 16
+ store <4 x float> %vecins3490, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3492 = fadd float undef, 0x4078066660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp414 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp414 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3493 = insertelement <4 x float> %tmp414, float %add3492, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3493, <4 x float>* undef, align 16
+ store <4 x float> %vecins3493, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp415 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp415 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3495 = fadd float undef, 0xC0798999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp416 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp416 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3496 = insertelement <4 x float> %tmp416, float %add3495, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3496, <4 x float>* undef, align 16
+ store <4 x float> %vecins3496, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp417 = load <4 x float>, <4 x float>* undef
+ %tmp417 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp418 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp418 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3498 = fadd <4 x float> %tmp418, %tmp417
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add3498, <4 x float>* undef, align 16
+ store <4 x float> %add3498, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3499 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -2655,83 +2655,83 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3501 = insertelement <4 x float> undef, float %add3500, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp419 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp419 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3502 = extractelement <4 x float> %tmp419, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3503 = fadd float %vecext3502, 0x4058C66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp420 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp420 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3506 = fadd float undef, 0xC074DB3340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp421 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp421 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins3507 = insertelement <4 x float> %tmp421, float %add3506, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins3507, <4 x float>* undef, align 16
+ store <4 x float> %vecins3507, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3509 = fadd float undef, 0xC066033340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp422 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp422 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x404B333340000000, float 4.680000e+02, float 0x40577999A0000000, float 0xC07D9999A0000000>, <4 x float>* undef
+ store <4 x float> <float 0x404B333340000000, float 4.680000e+02, float 0x40577999A0000000, float 0xC07D9999A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp423 = load <4 x float>, <4 x float>* undef
+ %tmp423 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3513 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add3514 = fadd float %vecext3513, 2.300000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp424 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp424 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp425 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp425 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext3516 = extractelement <4 x float> %tmp425, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5414 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5414, <4 x float>* undef, align 16
+ store <4 x float> %vecins5414, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp426 = load <4 x float>, <4 x float>* undef
+ %tmp426 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp427 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp427 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5416 = fadd <4 x float> %tmp427, %tmp426
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add5416, <4 x float>* undef, align 16
+ store <4 x float> %add5416, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp428 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp428 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5418 = fadd float undef, 0xC07ED999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp429 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp429 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5419 = insertelement <4 x float> %tmp429, float %add5418, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5624 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5624, <4 x float>* undef, align 16
+ store <4 x float> %vecins5624, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC07B4999A0000000, float 0x4078B33340000000, float 0xC07674CCC0000000, float 0xC07C533340000000>, <4 x float>* undef
+ store <4 x float> <float 0xC07B4999A0000000, float 0x4078B33340000000, float 0xC07674CCC0000000, float 0xC07C533340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5626 = fadd <4 x float> undef, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add5626, <4 x float>* undef, align 16
+ store <4 x float> %add5626, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5627 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp430 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp430 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5629 = insertelement <4 x float> %tmp430, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5629, <4 x float>* undef, align 16
+ store <4 x float> %vecins5629, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp431 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp431 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5630 = extractelement <4 x float> %tmp431, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -2739,379 +2739,379 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5632 = insertelement <4 x float> undef, float %add5631, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5632, <4 x float>* undef, align 16
+ store <4 x float> %vecins5632, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp432 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp432 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5688 = insertelement <4 x float> %tmp432, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5688, <4 x float>* undef, align 16
+ store <4 x float> %vecins5688, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp433 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp433 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5689 = extractelement <4 x float> %tmp433, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp434 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp434 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5691 = insertelement <4 x float> %tmp434, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5691, <4 x float>* undef, align 16
+ store <4 x float> %vecins5691, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5692 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float -4.350000e+02, float 0xC0775CCCC0000000, float 0xC0714999A0000000, float 0xC0661999A0000000>, <4 x float>* undef
+ store <4 x float> <float -4.350000e+02, float 0xC0775CCCC0000000, float 0xC0714999A0000000, float 0xC0661999A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp435 = load <4 x float>, <4 x float>* undef
+ %tmp435 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5696 = fadd <4 x float> undef, %tmp435
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add5696, <4 x float>* undef, align 16
+ store <4 x float> %add5696, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5701 = fadd float undef, 0x4077D4CCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp436 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp436 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5702 = insertelement <4 x float> %tmp436, float %add5701, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5702, <4 x float>* undef, align 16
+ store <4 x float> %vecins5702, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp437 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp437 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp438 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp438 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5705 = insertelement <4 x float> %tmp438, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5705, <4 x float>* undef, align 16
+ store <4 x float> %vecins5705, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp439 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp439 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5706 = extractelement <4 x float> %tmp439, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5707 = fadd float %vecext5706, 0xC0780B3340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp440 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp440 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5708 = insertelement <4 x float> %tmp440, float %add5707, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5708, <4 x float>* undef, align 16
+ store <4 x float> %vecins5708, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x405D666660000000, float 0xC069333340000000, float 0x407B6B3340000000, float 0xC06EB33340000000>, <4 x float>* undef
+ store <4 x float> <float 0x405D666660000000, float 0xC069333340000000, float 0x407B6B3340000000, float 0xC06EB33340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp441 = load <4 x float>, <4 x float>* undef
+ %tmp441 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp442 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp442 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5710 = fadd <4 x float> %tmp442, %tmp441
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add5710, <4 x float>* undef, align 16
+ store <4 x float> %add5710, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp443 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp443 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5711 = extractelement <4 x float> %tmp443, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5712 = fadd float %vecext5711, 1.850000e+01
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp444 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp444 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5713 = insertelement <4 x float> %tmp444, float %add5712, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5713, <4 x float>* undef, align 16
+ store <4 x float> %vecins5713, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp445 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp445 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp446 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp446 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5716 = insertelement <4 x float> %tmp446, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp447 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp447 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5724 = fadd <4 x float> %tmp447, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add5724, <4 x float>* undef, align 16
+ store <4 x float> %add5724, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp448 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp448 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5748 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp449 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp449 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5750 = insertelement <4 x float> %tmp449, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40692999A0000000, float 0xC07C4CCCC0000000, float 0x407D1E6660000000, float 0x407B4199A0000000>, <4 x float>* undef
+ store <4 x float> <float 0x40692999A0000000, float 0xC07C4CCCC0000000, float 0x407D1E6660000000, float 0x407B4199A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp450 = load <4 x float>, <4 x float>* undef
+ %tmp450 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5752 = fadd <4 x float> undef, %tmp450
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5754 = fadd float undef, 0xC064033340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp451 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp451 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5755 = insertelement <4 x float> %tmp451, float %add5754, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5755, <4 x float>* undef, align 16
+ store <4 x float> %vecins5755, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp452 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp452 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5756 = extractelement <4 x float> %tmp452, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5757 = fadd float %vecext5756, 0x40787B3340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp453 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp453 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5758 = insertelement <4 x float> %tmp453, float %add5757, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5758, <4 x float>* undef, align 16
+ store <4 x float> %vecins5758, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp454 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp454 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5759 = extractelement <4 x float> %tmp454, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp455 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp455 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5761 = insertelement <4 x float> %tmp455, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5761, <4 x float>* undef, align 16
+ store <4 x float> %vecins5761, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp456 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp456 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5762 = extractelement <4 x float> %tmp456, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5763 = fadd float %vecext5762, 0x40703E6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp457 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp457 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5764 = insertelement <4 x float> %tmp457, float %add5763, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5764, <4 x float>* undef, align 16
+ store <4 x float> %vecins5764, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x407A6B3340000000, float 0x40470CCCC0000000, float 0xC076F4CCC0000000, float 0x40791999A0000000>, <4 x float>* undef
+ store <4 x float> <float 0x407A6B3340000000, float 0x40470CCCC0000000, float 0xC076F4CCC0000000, float 0x40791999A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5766 = fadd <4 x float> undef, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add5766, <4 x float>* undef, align 16
+ store <4 x float> %add5766, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp458 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp458 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5767 = extractelement <4 x float> %tmp458, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5768 = fadd float %vecext5767, 0x4065533340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp459 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp459 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5769 = insertelement <4 x float> %tmp459, float %add5768, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5769, <4 x float>* undef, align 16
+ store <4 x float> %vecins5769, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5771 = fadd float undef, 8.000000e+00
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp460 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp460 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5772 = insertelement <4 x float> %tmp460, float %add5771, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp461 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp461 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5796 = fadd float undef, 0x4058ECCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5797 = insertelement <4 x float> undef, float %add5796, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5797, <4 x float>* undef, align 16
+ store <4 x float> %vecins5797, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp462 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp462 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5798 = extractelement <4 x float> %tmp462, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp463 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp463 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5800 = insertelement <4 x float> %tmp463, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp464 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp464 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5801 = extractelement <4 x float> %tmp464, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5802 = fadd float %vecext5801, 0xC072A199A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp465 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp465 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5803 = insertelement <4 x float> %tmp465, float %add5802, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5803, <4 x float>* undef, align 16
+ store <4 x float> %vecins5803, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp466 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp466 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5804 = extractelement <4 x float> %tmp466, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5805 = fadd float %vecext5804, 0x40785999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp467 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp467 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5806 = insertelement <4 x float> %tmp467, float %add5805, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5806, <4 x float>* undef, align 16
+ store <4 x float> %vecins5806, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp468 = load <4 x float>, <4 x float>* undef
+ %tmp468 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp469 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp469 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5809 = extractelement <4 x float> %tmp469, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5810 = fadd float %vecext5809, 0x407B7B3340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp470 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp470 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp471 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp471 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5818 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5819 = fadd float %vecext5818, 0x4071733340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp472 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp472 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5820 = insertelement <4 x float> %tmp472, float %add5819, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5820, <4 x float>* undef, align 16
+ store <4 x float> %vecins5820, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40514CCCC0000000, float 0x406A7999A0000000, float 0xC078766660000000, float 0xC0522CCCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0x40514CCCC0000000, float 0x406A7999A0000000, float 0xC078766660000000, float 0xC0522CCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp473 = load <4 x float>, <4 x float>* undef
+ %tmp473 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp474 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp474 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5822 = fadd <4 x float> %tmp474, %tmp473
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add5822, <4 x float>* undef, align 16
+ store <4 x float> %add5822, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp475 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp475 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5823 = extractelement <4 x float> %tmp475, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp476 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp476 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5825 = insertelement <4 x float> %tmp476, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp477 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp477 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5826 = extractelement <4 x float> %tmp477, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5827 = fadd float %vecext5826, 0x407F14CCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp478 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp478 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5828 = insertelement <4 x float> %tmp478, float %add5827, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5828, <4 x float>* undef, align 16
+ store <4 x float> %vecins5828, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp479 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp479 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5829 = extractelement <4 x float> %tmp479, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5830 = fadd float %vecext5829, 3.350000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp480 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp480 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5831 = insertelement <4 x float> %tmp480, float %add5830, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float -3.370000e+02, float 0xC072DE6660000000, float -2.670000e+02, float 0x4062333340000000>, <4 x float>* undef
+ store <4 x float> <float -3.370000e+02, float 0xC072DE6660000000, float -2.670000e+02, float 0x4062333340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp481 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp481 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5837 = extractelement <4 x float> %tmp481, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5839 = insertelement <4 x float> undef, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5839, <4 x float>* undef, align 16
+ store <4 x float> %vecins5839, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp482 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp482 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5840 = extractelement <4 x float> %tmp482, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp483 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp483 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5842 = insertelement <4 x float> %tmp483, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5842, <4 x float>* undef, align 16
+ store <4 x float> %vecins5842, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp484 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp484 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp485 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp485 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5845 = insertelement <4 x float> %tmp485, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5845, <4 x float>* undef, align 16
+ store <4 x float> %vecins5845, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC06EC999A0000000, float 0x406D5999A0000000, float 0x4056F33340000000, float 0xC07E14CCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0xC06EC999A0000000, float 0x406D5999A0000000, float 0x4056F33340000000, float 0xC07E14CCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5850 = fadd <4 x float> undef, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add5850, <4 x float>* undef, align 16
+ store <4 x float> %add5850, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp486 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp486 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5852 = fadd float undef, 2.985000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp487 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp487 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5853 = insertelement <4 x float> %tmp487, float %add5852, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5853, <4 x float>* undef, align 16
+ store <4 x float> %vecins5853, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp488 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp488 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5854 = extractelement <4 x float> %tmp488, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5855 = fadd float %vecext5854, 0xC053F999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp489 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp489 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5856 = insertelement <4 x float> %tmp489, float %add5855, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5856, <4 x float>* undef, align 16
+ store <4 x float> %vecins5856, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp490 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp490 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5858 = fadd float undef, 0x4071666660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp491 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp491 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5859 = insertelement <4 x float> %tmp491, float %add5858, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5859, <4 x float>* undef, align 16
+ store <4 x float> %vecins5859, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp492 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp492 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5860 = extractelement <4 x float> %tmp492, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp493 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp493 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5899 = extractelement <4 x float> %tmp493, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5900 = fadd float %vecext5899, -2.700000e+01
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp494 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp494 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5901 = insertelement <4 x float> %tmp494, float %add5900, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5901, <4 x float>* undef, align 16
+ store <4 x float> %vecins5901, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5914 = fadd float undef, 0x40786E6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5918 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5918, <4 x float>* undef, align 16
+ store <4 x float> %vecins5918, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x406F266660000000, float 7.900000e+01, float -4.695000e+02, float -4.880000e+02>, <4 x float>* undef
+ store <4 x float> <float 0x406F266660000000, float 7.900000e+01, float -4.695000e+02, float -4.880000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5920 = fadd <4 x float> undef, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add5920, <4 x float>* undef, align 16
+ store <4 x float> %add5920, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5934 = fadd <4 x float> undef, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -3119,11 +3119,11 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add5936 = fadd float %vecext5935, 0xC056B999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp495 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp495 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp496 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp496 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5994 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -3131,89 +3131,89 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins5996 = insertelement <4 x float> undef, float %add5995, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins5996, <4 x float>* undef, align 16
+ store <4 x float> %vecins5996, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp497 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp497 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext5997 = extractelement <4 x float> %tmp497, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp498 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp498 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6000 = extractelement <4 x float> %tmp498, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6001 = fadd float %vecext6000, -7.600000e+01
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp499 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp499 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6002 = insertelement <4 x float> %tmp499, float %add6001, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6002, <4 x float>* undef, align 16
+ store <4 x float> %vecins6002, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC07EA199A0000000, float 0x407DC33340000000, float 0xC0753199A0000000, float -3.895000e+02>, <4 x float>* undef
+ store <4 x float> <float 0xC07EA199A0000000, float 0x407DC33340000000, float 0xC0753199A0000000, float -3.895000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp500 = load <4 x float>, <4 x float>* undef
+ %tmp500 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6004 = fadd <4 x float> undef, %tmp500
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6004, <4 x float>* undef, align 16
+ store <4 x float> %add6004, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp501 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp501 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6005 = extractelement <4 x float> %tmp501, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp502 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp502 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6007 = insertelement <4 x float> %tmp502, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp503 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp503 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6008 = extractelement <4 x float> %tmp503, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp504 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp504 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6024 = insertelement <4 x float> %tmp504, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6024, <4 x float>* undef, align 16
+ store <4 x float> %vecins6024, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp505 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp505 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6025 = extractelement <4 x float> %tmp505, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6026 = fadd float %vecext6025, 3.700000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp506 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp506 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6027 = insertelement <4 x float> %tmp506, float %add6026, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6027, <4 x float>* undef, align 16
+ store <4 x float> %vecins6027, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6028 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6029 = fadd float %vecext6028, 0x4071666660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp507 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp507 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6030 = insertelement <4 x float> %tmp507, float %add6029, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6030, <4 x float>* undef, align 16
+ store <4 x float> %vecins6030, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC0527999A0000000, float 0xC06AD999A0000000, float 0x3FF6666660000000, float 0xC03F666660000000>, <4 x float>* undef
+ store <4 x float> <float 0xC0527999A0000000, float 0xC06AD999A0000000, float 0x3FF6666660000000, float 0xC03F666660000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp508 = load <4 x float>, <4 x float>* undef
+ %tmp508 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp509 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp509 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp510 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp510 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6033 = extractelement <4 x float> %tmp510, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp511 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp511 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6036 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -3221,49 +3221,49 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6038 = insertelement <4 x float> undef, float %add6037, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6038, <4 x float>* undef, align 16
+ store <4 x float> %vecins6038, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp512 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp512 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6040 = fadd float undef, 0x4071ECCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp513 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp513 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6041 = insertelement <4 x float> %tmp513, float %add6040, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6041, <4 x float>* undef, align 16
+ store <4 x float> %vecins6041, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp514 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp514 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6042 = extractelement <4 x float> %tmp514, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6043 = fadd float %vecext6042, 0xC07DD33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp515 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp515 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6044 = insertelement <4 x float> %tmp515, float %add6043, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6044, <4 x float>* undef, align 16
+ store <4 x float> %vecins6044, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC065FCCCC0000000, float 0x40767CCCC0000000, float 0x4079D4CCC0000000, float 0xC07314CCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0xC065FCCCC0000000, float 0x40767CCCC0000000, float 0x4079D4CCC0000000, float 0xC07314CCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp516 = load <4 x float>, <4 x float>* undef
+ %tmp516 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp517 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp517 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6046 = fadd <4 x float> %tmp517, %tmp516
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6046, <4 x float>* undef, align 16
+ store <4 x float> %add6046, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6047 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp518 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp518 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6049 = insertelement <4 x float> %tmp518, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6049, <4 x float>* undef, align 16
+ store <4 x float> %vecins6049, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp519 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp519 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6050 = extractelement <4 x float> %tmp519, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -3273,17 +3273,17 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6056 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp520 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp520 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6061 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp521 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp521 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp522 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp522 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6067 = extractelement <4 x float> %tmp522, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -3295,47 +3295,47 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6072 = insertelement <4 x float> undef, float %add6071, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6072, <4 x float>* undef, align 16
+ store <4 x float> %vecins6072, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40546CCCC0000000, float 0x4067D66660000000, float 0xC060E33340000000, float 0x4061533340000000>, <4 x float>* undef
+ store <4 x float> <float 0x40546CCCC0000000, float 0x4067D66660000000, float 0xC060E33340000000, float 0x4061533340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp523 = load <4 x float>, <4 x float>* undef
+ %tmp523 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp524 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp524 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6074 = fadd <4 x float> %tmp524, %tmp523
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6074, <4 x float>* undef, align 16
+ store <4 x float> %add6074, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp525 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp525 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6075 = extractelement <4 x float> %tmp525, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6076 = fadd float %vecext6075, 0x405D733340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp526 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp526 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6077 = insertelement <4 x float> %tmp526, float %add6076, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6077, <4 x float>* undef, align 16
+ store <4 x float> %vecins6077, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp527 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp527 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6079 = fadd float undef, 0xC07E9B3340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp528 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp528 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp529 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp529 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6082 = fadd float undef, 0x407DCE6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6083 = insertelement <4 x float> undef, float %add6082, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6083, <4 x float>* undef, align 16
+ store <4 x float> %vecins6083, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp530 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp530 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6084 = extractelement <4 x float> %tmp530, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -3343,97 +3343,97 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6086 = insertelement <4 x float> undef, float %add6085, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6086, <4 x float>* undef, align 16
+ store <4 x float> %vecins6086, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x4055C66660000000, float 0x40735199A0000000, float 0xC0713199A0000000, float 0x40729B3340000000>, <4 x float>* undef
+ store <4 x float> <float 0x4055C66660000000, float 0x40735199A0000000, float 0xC0713199A0000000, float 0x40729B3340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp531 = load <4 x float>, <4 x float>* undef
+ %tmp531 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp532 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp532 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6088 = fadd <4 x float> %tmp532, %tmp531
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6088, <4 x float>* undef, align 16
+ store <4 x float> %add6088, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp533 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp533 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6089 = extractelement <4 x float> %tmp533, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6107 = fadd float undef, 0xC06A166660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp534 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp534 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6108 = insertelement <4 x float> %tmp534, float %add6107, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6108, <4 x float>* undef, align 16
+ store <4 x float> %vecins6108, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp535 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp535 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6109 = extractelement <4 x float> %tmp535, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6110 = fadd float %vecext6109, 0x4070FB3340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp536 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp536 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp537 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp537 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6112 = extractelement <4 x float> %tmp537, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6113 = fadd float %vecext6112, 0xC04AF33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp538 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp538 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp539 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp539 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6117 = extractelement <4 x float> %tmp539, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6118 = fadd float %vecext6117, 0x407AB33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp540 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp540 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6119 = insertelement <4 x float> %tmp540, float %add6118, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6119, <4 x float>* undef, align 16
+ store <4 x float> %vecins6119, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp541 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp541 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6120 = extractelement <4 x float> %tmp541, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6121 = fadd float %vecext6120, 0x405AE66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp542 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp542 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6122 = insertelement <4 x float> %tmp542, float %add6121, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6122, <4 x float>* undef, align 16
+ store <4 x float> %vecins6122, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6123 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6124 = fadd float %vecext6123, -4.385000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp543 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp543 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6126 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp544 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp544 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6128 = insertelement <4 x float> %tmp544, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6128, <4 x float>* undef, align 16
+ store <4 x float> %vecins6128, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float -2.980000e+02, float 0xC06F0CCCC0000000, float 0xC054A66660000000, float 0xC040CCCCC0000000>, <4 x float>* undef
+ store <4 x float> <float -2.980000e+02, float 0xC06F0CCCC0000000, float 0xC054A66660000000, float 0xC040CCCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp545 = load <4 x float>, <4 x float>* undef
+ %tmp545 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp546 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp546 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6130 = fadd <4 x float> %tmp546, %tmp545
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp547 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp547 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6131 = extractelement <4 x float> %tmp547, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -3441,13 +3441,13 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6133 = insertelement <4 x float> undef, float %add6132, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6133, <4 x float>* undef, align 16
+ store <4 x float> %vecins6133, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6134 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6135 = fadd float %vecext6134, 0xC06B7999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp548 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp548 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6136 = insertelement <4 x float> %tmp548, float %add6135, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -3455,113 +3455,113 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6138 = fadd float %vecext6137, 0x40752199A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp549 = load <4 x float>, <4 x float>* undef
+ %tmp549 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6172 = fadd <4 x float> undef, %tmp549
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp550 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp550 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp551 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp551 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6178 = insertelement <4 x float> %tmp551, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6178, <4 x float>* undef, align 16
+ store <4 x float> %vecins6178, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp552 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp552 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6179 = extractelement <4 x float> %tmp552, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6180 = fadd float %vecext6179, -3.905000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp553 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp553 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6181 = insertelement <4 x float> %tmp553, float %add6180, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp554 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp554 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6182 = extractelement <4 x float> %tmp554, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6183 = fadd float %vecext6182, 1.515000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp555 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp555 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6184 = insertelement <4 x float> %tmp555, float %add6183, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6184, <4 x float>* undef, align 16
+ store <4 x float> %vecins6184, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp556 = load <4 x float>, <4 x float>* undef
+ %tmp556 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6189 = insertelement <4 x float> undef, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6189, <4 x float>* undef, align 16
+ store <4 x float> %vecins6189, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp557 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp557 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6190 = extractelement <4 x float> %tmp557, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6191 = fadd float %vecext6190, 0xC07BD33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp558 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp558 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6192 = insertelement <4 x float> %tmp558, float %add6191, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6192, <4 x float>* undef, align 16
+ store <4 x float> %vecins6192, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp559 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp559 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp560 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp560 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6196 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6197 = fadd float %vecext6196, -4.070000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp561 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp561 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6198 = insertelement <4 x float> %tmp561, float %add6197, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x407904CCC0000000, float 0x406A833340000000, float 4.895000e+02, float 0x40648999A0000000>, <4 x float>* undef
+ store <4 x float> <float 0x407904CCC0000000, float 0x406A833340000000, float 4.895000e+02, float 0x40648999A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp562 = load <4 x float>, <4 x float>* undef
+ %tmp562 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp563 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp563 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6200 = fadd <4 x float> %tmp563, %tmp562
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6200, <4 x float>* undef, align 16
+ store <4 x float> %add6200, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp564 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp564 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6201 = extractelement <4 x float> %tmp564, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp565 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp565 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6203 = insertelement <4 x float> %tmp565, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp566 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp566 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6204 = extractelement <4 x float> %tmp566, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6205 = fadd float %vecext6204, 1.740000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp567 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp567 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6206 = insertelement <4 x float> %tmp567, float %add6205, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp568 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp568 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6209 = insertelement <4 x float> %tmp568, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6209, <4 x float>* undef, align 16
+ store <4 x float> %vecins6209, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp569 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp569 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6210 = extractelement <4 x float> %tmp569, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp570 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp570 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6219 = fadd float undef, 0xC0596CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp571 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp571 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6220 = insertelement <4 x float> %tmp571, float %add6219, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -3569,33 +3569,33 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6225 = fadd float %vecext6224, 0xC074533340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp572 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp572 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6228 = fadd <4 x float> undef, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6228, <4 x float>* undef, align 16
+ store <4 x float> %add6228, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6229 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6230 = fadd float %vecext6229, 1.695000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp573 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp573 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6231 = insertelement <4 x float> %tmp573, float %add6230, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6231, <4 x float>* undef, align 16
+ store <4 x float> %vecins6231, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp574 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp574 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6232 = extractelement <4 x float> %tmp574, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6233 = fadd float %vecext6232, 0x4079C33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp575 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp575 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6234 = insertelement <4 x float> %tmp575, float %add6233, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6234, <4 x float>* undef, align 16
+ store <4 x float> %vecins6234, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6235 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -3603,135 +3603,135 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6237 = insertelement <4 x float> undef, float %add6236, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6237, <4 x float>* undef, align 16
+ store <4 x float> %vecins6237, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp576 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp576 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6245 = insertelement <4 x float> undef, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6245, <4 x float>* undef, align 16
+ store <4 x float> %vecins6245, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp577 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp577 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6246 = extractelement <4 x float> %tmp577, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6247 = fadd float %vecext6246, 0x40631999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp578 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp578 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6251 = insertelement <4 x float> undef, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp579 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp579 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6253 = fadd float undef, 0xC0692999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6254 = insertelement <4 x float> undef, float %add6253, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6254, <4 x float>* undef, align 16
+ store <4 x float> %vecins6254, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 4.600000e+02, float 0xC0777B3340000000, float 0x40351999A0000000, float 0xC06E433340000000>, <4 x float>* undef
+ store <4 x float> <float 4.600000e+02, float 0xC0777B3340000000, float 0x40351999A0000000, float 0xC06E433340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp580 = load <4 x float>, <4 x float>* undef
+ %tmp580 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp581 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp581 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6256 = fadd <4 x float> %tmp581, %tmp580
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6256, <4 x float>* undef, align 16
+ store <4 x float> %add6256, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp582 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp582 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6257 = extractelement <4 x float> %tmp582, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6258 = fadd float %vecext6257, 4.670000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp583 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp583 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6259 = insertelement <4 x float> %tmp583, float %add6258, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6259, <4 x float>* undef, align 16
+ store <4 x float> %vecins6259, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp584 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp584 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6260 = extractelement <4 x float> %tmp584, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6261 = fadd float %vecext6260, 0xC05F733340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp585 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp585 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6262 = insertelement <4 x float> %tmp585, float %add6261, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6262, <4 x float>* undef, align 16
+ store <4 x float> %vecins6262, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp586 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp586 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6263 = extractelement <4 x float> %tmp586, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp587 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp587 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6265 = insertelement <4 x float> %tmp587, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6265, <4 x float>* undef, align 16
+ store <4 x float> %vecins6265, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp588 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp588 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6266 = extractelement <4 x float> %tmp588, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6267 = fadd float %vecext6266, 0x407174CCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp589 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp589 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6268 = insertelement <4 x float> %tmp589, float %add6267, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6268, <4 x float>* undef, align 16
+ store <4 x float> %vecins6268, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float -3.130000e+02, float 0xC079733340000000, float -4.660000e+02, float 0xC064E66660000000>, <4 x float>* undef
+ store <4 x float> <float -3.130000e+02, float 0xC079733340000000, float -4.660000e+02, float 0xC064E66660000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp590 = load <4 x float>, <4 x float>* undef
+ %tmp590 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp591 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp591 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6270 = fadd <4 x float> %tmp591, %tmp590
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6270, <4 x float>* undef, align 16
+ store <4 x float> %add6270, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp592 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp592 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6271 = extractelement <4 x float> %tmp592, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6272 = fadd float %vecext6271, 1.765000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp593 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp593 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6273 = insertelement <4 x float> %tmp593, float %add6272, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6273, <4 x float>* undef, align 16
+ store <4 x float> %vecins6273, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp594 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp594 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6274 = extractelement <4 x float> %tmp594, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6275 = fadd float %vecext6274, 0x402C666660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp595 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp595 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6276 = insertelement <4 x float> %tmp595, float %add6275, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6276, <4 x float>* undef, align 16
+ store <4 x float> %vecins6276, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp596 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp596 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6277 = extractelement <4 x float> %tmp596, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6278 = fadd float %vecext6277, -8.450000e+01
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp597 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp597 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6279 = insertelement <4 x float> %tmp597, float %add6278, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6279, <4 x float>* undef, align 16
+ store <4 x float> %vecins6279, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp598 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp598 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6280 = extractelement <4 x float> %tmp598, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -3739,9 +3739,9 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6282 = insertelement <4 x float> undef, float %add6281, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6282, <4 x float>* undef, align 16
+ store <4 x float> %vecins6282, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x4067ECCCC0000000, float 0xC040CCCCC0000000, float 0xC0762E6660000000, float -4.750000e+02>, <4 x float>* undef
+ store <4 x float> <float 0x4067ECCCC0000000, float 0xC040CCCCC0000000, float 0xC0762E6660000000, float -4.750000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6284 = fadd <4 x float> undef, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -3749,13 +3749,13 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6289 = fadd float undef, 0xC0738999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp599 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp599 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6293 = insertelement <4 x float> %tmp599, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6293, <4 x float>* undef, align 16
+ store <4 x float> %vecins6293, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp600 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp600 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6294 = extractelement <4 x float> %tmp600, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -3763,41 +3763,41 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6296 = insertelement <4 x float> undef, float %add6295, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6296, <4 x float>* undef, align 16
+ store <4 x float> %vecins6296, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40704199A0000000, float 0x40753CCCC0000000, float 0xC07E2199A0000000, float 0xC068833340000000>, <4 x float>* undef
+ store <4 x float> <float 0x40704199A0000000, float 0x40753CCCC0000000, float 0xC07E2199A0000000, float 0xC068833340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp601 = load <4 x float>, <4 x float>* undef
+ %tmp601 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6298 = fadd <4 x float> undef, %tmp601
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6298, <4 x float>* undef, align 16
+ store <4 x float> %add6298, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp602 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp602 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6299 = extractelement <4 x float> %tmp602, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6300 = fadd float %vecext6299, 0x4074B33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp603 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp603 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6301 = insertelement <4 x float> %tmp603, float %add6300, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6301, <4 x float>* undef, align 16
+ store <4 x float> %vecins6301, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp604 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp604 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6302 = extractelement <4 x float> %tmp604, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6303 = fadd float %vecext6302, 0xC05B333340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp605 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp605 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6304 = insertelement <4 x float> %tmp605, float %add6303, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6304, <4 x float>* undef, align 16
+ store <4 x float> %vecins6304, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp606 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp606 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6305 = extractelement <4 x float> %tmp606, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -3805,93 +3805,93 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6307 = insertelement <4 x float> undef, float %add6306, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6307, <4 x float>* undef, align 16
+ store <4 x float> %vecins6307, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp607 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp607 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6308 = extractelement <4 x float> %tmp607, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6309 = fadd float %vecext6308, 0x40707E6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp608 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp608 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6310 = insertelement <4 x float> %tmp608, float %add6309, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6310, <4 x float>* undef, align 16
+ store <4 x float> %vecins6310, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x407A233340000000, float 0x406DA33340000000, float 3.725000e+02, float 0x40761199A0000000>, <4 x float>* undef
+ store <4 x float> <float 0x407A233340000000, float 0x406DA33340000000, float 3.725000e+02, float 0x40761199A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp609 = load <4 x float>, <4 x float>* undef
+ %tmp609 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp610 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp610 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6312 = fadd <4 x float> %tmp610, %tmp609
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6312, <4 x float>* undef, align 16
+ store <4 x float> %add6312, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp611 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp611 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6313 = extractelement <4 x float> %tmp611, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6314 = fadd float %vecext6313, 0xC07CF33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp612 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp612 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6315 = insertelement <4 x float> %tmp612, float %add6314, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp613 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp613 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6655 = extractelement <4 x float> %tmp613, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6656 = fadd float %vecext6655, 2.185000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp614 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp614 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6657 = insertelement <4 x float> %tmp614, float %add6656, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6657, <4 x float>* undef, align 16
+ store <4 x float> %vecins6657, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6660 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6660, <4 x float>* undef, align 16
+ store <4 x float> %vecins6660, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC064E33340000000, float 0xC064833340000000, float 0xC0673CCCC0000000, float 0xC074266660000000>, <4 x float>* undef
+ store <4 x float> <float 0xC064E33340000000, float 0xC064833340000000, float 0xC0673CCCC0000000, float 0xC074266660000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp615 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp615 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6663 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6664 = fadd float %vecext6663, 0xC05B7999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp616 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp616 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6665 = insertelement <4 x float> %tmp616, float %add6664, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp617 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp617 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6669 = extractelement <4 x float> %tmp617, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp618 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp618 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC07CC4CCC0000000, float 0x404EE66660000000, float 0xC0754CCCC0000000, float 0xC0744B3340000000>, <4 x float>* undef
+ store <4 x float> <float 0xC07CC4CCC0000000, float 0x404EE66660000000, float 0xC0754CCCC0000000, float 0xC0744B3340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp619 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp619 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6676 = fadd <4 x float> %tmp619, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6676, <4 x float>* undef, align 16
+ store <4 x float> %add6676, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp620 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp620 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6677 = extractelement <4 x float> %tmp620, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6678 = fadd float %vecext6677, 0x4077F4CCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp621 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp621 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6679 = insertelement <4 x float> %tmp621, float %add6678, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -3899,115 +3899,115 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6681 = fadd float %vecext6680, 0x4061766660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp622 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp622 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp623 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp623 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6683 = extractelement <4 x float> %tmp623, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6684 = fadd float %vecext6683, 0x40718999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp624 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp624 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6685 = insertelement <4 x float> %tmp624, float %add6684, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6685, <4 x float>* undef, align 16
+ store <4 x float> %vecins6685, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp625 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp625 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6686 = extractelement <4 x float> %tmp625, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6687 = fadd float %vecext6686, 0x4076D66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp626 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp626 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6688 = insertelement <4 x float> %tmp626, float %add6687, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6688, <4 x float>* undef, align 16
+ store <4 x float> %vecins6688, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 7.500000e+00, float 0x4077E33340000000, float 0xC0596CCCC0000000, float 0xC07D4E6660000000>, <4 x float>* undef
+ store <4 x float> <float 7.500000e+00, float 0x4077E33340000000, float 0xC0596CCCC0000000, float 0xC07D4E6660000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp627 = load <4 x float>, <4 x float>* undef
+ %tmp627 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6690 = fadd <4 x float> undef, %tmp627
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6690, <4 x float>* undef, align 16
+ store <4 x float> %add6690, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp628 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp628 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6691 = extractelement <4 x float> %tmp628, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6692 = fadd float %vecext6691, 3.250000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp629 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp629 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6693 = insertelement <4 x float> %tmp629, float %add6692, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6693, <4 x float>* undef, align 16
+ store <4 x float> %vecins6693, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp630 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp630 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6694 = extractelement <4 x float> %tmp630, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6695 = fadd float %vecext6694, 0x407DF999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp631 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp631 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6696 = insertelement <4 x float> %tmp631, float %add6695, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6696, <4 x float>* undef, align 16
+ store <4 x float> %vecins6696, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp632 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp632 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6697 = extractelement <4 x float> %tmp632, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6698 = fadd float %vecext6697, 0xC075FE6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp633 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp633 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6699 = insertelement <4 x float> %tmp633, float %add6698, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6699, <4 x float>* undef, align 16
+ store <4 x float> %vecins6699, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp634 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp634 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6700 = extractelement <4 x float> %tmp634, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6701 = fadd float %vecext6700, 0xC07BCE6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp635 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp635 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6702 = insertelement <4 x float> %tmp635, float %add6701, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6702, <4 x float>* undef, align 16
+ store <4 x float> %vecins6702, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40772CCCC0000000, float 0xC0625CCCC0000000, float 6.200000e+01, float 0xC06ADCCCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0x40772CCCC0000000, float 0xC0625CCCC0000000, float 6.200000e+01, float 0xC06ADCCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp636 = load <4 x float>, <4 x float>* undef
+ %tmp636 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp637 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp637 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6707 = insertelement <4 x float> undef, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6707, <4 x float>* undef, align 16
+ store <4 x float> %vecins6707, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp638 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp638 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6708 = extractelement <4 x float> %tmp638, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp639 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp639 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp640 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp640 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6714 = extractelement <4 x float> %tmp640, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6715 = fadd float %vecext6714, 0xC0537999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp641 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp641 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6716 = insertelement <4 x float> %tmp641, float %add6715, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -4015,117 +4015,117 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6720 = fadd float %vecext6719, 2.870000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp642 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp642 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6721 = insertelement <4 x float> %tmp642, float %add6720, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp643 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp643 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6722 = extractelement <4 x float> %tmp643, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6723 = fadd float %vecext6722, 0xC07704CCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp644 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp644 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6724 = insertelement <4 x float> %tmp644, float %add6723, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp645 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp645 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6726 = fadd float undef, 0x4059B999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp646 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp646 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6727 = insertelement <4 x float> %tmp646, float %add6726, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6727, <4 x float>* undef, align 16
+ store <4 x float> %vecins6727, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6728 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6729 = fadd float %vecext6728, 0xC073466660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC0309999A0000000, float -2.715000e+02, float 1.620000e+02, float 0x40674CCCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0xC0309999A0000000, float -2.715000e+02, float 1.620000e+02, float 0x40674CCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp647 = load <4 x float>, <4 x float>* undef
+ %tmp647 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp648 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp648 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6732 = fadd <4 x float> %tmp648, %tmp647
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6732, <4 x float>* undef, align 16
+ store <4 x float> %add6732, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp649 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp649 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6733 = extractelement <4 x float> %tmp649, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6734 = fadd float %vecext6733, 0x4040733340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp650 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp650 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6735 = insertelement <4 x float> %tmp650, float %add6734, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6735, <4 x float>* undef, align 16
+ store <4 x float> %vecins6735, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp651 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp651 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6736 = extractelement <4 x float> %tmp651, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6737 = fadd float %vecext6736, 0xC07B74CCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp652 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp652 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6738 = insertelement <4 x float> %tmp652, float %add6737, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6738, <4 x float>* undef, align 16
+ store <4 x float> %vecins6738, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp653 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp653 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6739 = extractelement <4 x float> %tmp653, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6740 = fadd float %vecext6739, 0x40699CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp654 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp654 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6741 = insertelement <4 x float> %tmp654, float %add6740, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6741, <4 x float>* undef, align 16
+ store <4 x float> %vecins6741, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp655 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp655 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6742 = extractelement <4 x float> %tmp655, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6743 = fadd float %vecext6742, 0x4078533340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp656 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp656 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6744 = insertelement <4 x float> %tmp656, float %add6743, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6744, <4 x float>* undef, align 16
+ store <4 x float> %vecins6744, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp657 = load <4 x float>, <4 x float>* undef
+ %tmp657 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp658 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp658 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6746 = fadd <4 x float> %tmp658, %tmp657
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6746, <4 x float>* undef, align 16
+ store <4 x float> %add6746, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp659 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp659 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6749 = insertelement <4 x float> undef, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6749, <4 x float>* undef, align 16
+ store <4 x float> %vecins6749, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp660 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp660 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6751 = fadd float undef, 0x4075DE6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6752 = insertelement <4 x float> undef, float %add6751, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6752, <4 x float>* undef, align 16
+ store <4 x float> %vecins6752, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp661 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp661 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6753 = extractelement <4 x float> %tmp661, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -4133,29 +4133,29 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6755 = insertelement <4 x float> undef, float %add6754, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6755, <4 x float>* undef, align 16
+ store <4 x float> %vecins6755, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp662 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp662 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6756 = extractelement <4 x float> %tmp662, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6757 = fadd float %vecext6756, 0x406CA999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp663 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp663 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6758 = insertelement <4 x float> %tmp663, float %add6757, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6758, <4 x float>* undef, align 16
+ store <4 x float> %vecins6758, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x403D1999A0000000, float 0xC05F533340000000, float 3.945000e+02, float 3.950000e+01>, <4 x float>* undef
+ store <4 x float> <float 0x403D1999A0000000, float 0xC05F533340000000, float 3.945000e+02, float 3.950000e+01>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp664 = load <4 x float>, <4 x float>* undef
+ %tmp664 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6760 = fadd <4 x float> undef, %tmp664
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6760, <4 x float>* undef, align 16
+ store <4 x float> %add6760, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp665 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp665 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6761 = extractelement <4 x float> %tmp665, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -4163,43 +4163,43 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6763 = insertelement <4 x float> undef, float %add6762, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp666 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp666 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC079BE6660000000, float 4.930000e+02, float 0x406CC33340000000, float 0xC062E999A0000000>, <4 x float>* undef
+ store <4 x float> <float 0xC079BE6660000000, float 4.930000e+02, float 0x406CC33340000000, float 0xC062E999A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp667 = load <4 x float>, <4 x float>* undef
+ %tmp667 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6774 = fadd <4 x float> undef, %tmp667
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp668 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp668 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6775 = extractelement <4 x float> %tmp668, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6776 = fadd float %vecext6775, 0x407B8199A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp669 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp669 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6777 = insertelement <4 x float> %tmp669, float %add6776, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6777, <4 x float>* undef, align 16
+ store <4 x float> %vecins6777, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp670 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp670 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6778 = extractelement <4 x float> %tmp670, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6779 = fadd float %vecext6778, 0x401C666660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp671 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp671 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6784 = extractelement <4 x float> %tmp671, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6875 = insertelement <4 x float> undef, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6875, <4 x float>* undef, align 16
+ store <4 x float> %vecins6875, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp672 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp672 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6876 = extractelement <4 x float> %tmp672, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -4207,135 +4207,135 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6878 = insertelement <4 x float> undef, float %add6877, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6878, <4 x float>* undef, align 16
+ store <4 x float> %vecins6878, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6888 = fadd float undef, 0x4057CCCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp673 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp673 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6889 = insertelement <4 x float> %tmp673, float %add6888, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6889, <4 x float>* undef, align 16
+ store <4 x float> %vecins6889, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp674 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp674 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6890 = extractelement <4 x float> %tmp674, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6891 = fadd float %vecext6890, -4.430000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp675 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp675 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6892 = insertelement <4 x float> %tmp675, float %add6891, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6892, <4 x float>* undef, align 16
+ store <4 x float> %vecins6892, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp676 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp676 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6893 = extractelement <4 x float> %tmp676, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6894 = fadd float %vecext6893, -3.280000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp677 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp677 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6895 = insertelement <4 x float> %tmp677, float %add6894, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6895, <4 x float>* undef, align 16
+ store <4 x float> %vecins6895, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp678 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp678 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp679 = load <4 x float>, <4 x float>* undef
+ %tmp679 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp680 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp680 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6900 = fadd <4 x float> %tmp680, %tmp679
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6900, <4 x float>* undef, align 16
+ store <4 x float> %add6900, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp681 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp681 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6901 = extractelement <4 x float> %tmp681, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6902 = fadd float %vecext6901, 0x4079DCCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp682 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp682 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6903 = insertelement <4 x float> %tmp682, float %add6902, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6903, <4 x float>* undef, align 16
+ store <4 x float> %vecins6903, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6905 = fadd float undef, 0x4031B33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp683 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp683 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6906 = insertelement <4 x float> %tmp683, float %add6905, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp684 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp684 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6912 = insertelement <4 x float> %tmp684, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 3.315000e+02, float 0xC066C999A0000000, float 0xC061F33340000000, float 0x4071166660000000>, <4 x float>* undef
+ store <4 x float> <float 3.315000e+02, float 0xC066C999A0000000, float 0xC061F33340000000, float 0x4071166660000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp685 = load <4 x float>, <4 x float>* undef
+ %tmp685 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp686 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp686 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6914 = fadd <4 x float> %tmp686, %tmp685
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6914, <4 x float>* undef, align 16
+ store <4 x float> %add6914, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6915 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6920 = insertelement <4 x float> undef, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6920, <4 x float>* undef, align 16
+ store <4 x float> %vecins6920, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6921 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6922 = fadd float %vecext6921, 0xC064066660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp687 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp687 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6926 = insertelement <4 x float> %tmp687, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6926, <4 x float>* undef, align 16
+ store <4 x float> %vecins6926, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC03C4CCCC0000000, float 0xC07E5199A0000000, float -8.250000e+01, float 0xC043B33340000000>, <4 x float>* undef
+ store <4 x float> <float 0xC03C4CCCC0000000, float 0xC07E5199A0000000, float -8.250000e+01, float 0xC043B33340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp688 = load <4 x float>, <4 x float>* undef
+ %tmp688 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp689 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp689 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6928 = fadd <4 x float> %tmp689, %tmp688
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6928, <4 x float>* undef, align 16
+ store <4 x float> %add6928, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6930 = fadd float undef, -4.590000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6931 = insertelement <4 x float> undef, float %add6930, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6931, <4 x float>* undef, align 16
+ store <4 x float> %vecins6931, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp690 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp690 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6932 = extractelement <4 x float> %tmp690, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6933 = fadd float %vecext6932, 0xC063F999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp691 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp691 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp692 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp692 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6935 = extractelement <4 x float> %tmp692, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6936 = fadd float %vecext6935, -3.335000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp693 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp693 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6937 = insertelement <4 x float> %tmp693, float %add6936, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp694 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp694 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6938 = extractelement <4 x float> %tmp694, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -4347,137 +4347,137 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6944 = fadd float %vecext6943, 0x40530CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp695 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp695 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6950 = fadd float undef, 0xC078F33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp696 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp696 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6951 = insertelement <4 x float> %tmp696, float %add6950, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6951, <4 x float>* undef, align 16
+ store <4 x float> %vecins6951, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp697 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp697 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6952 = extractelement <4 x float> %tmp697, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6953 = fadd float %vecext6952, 0xC06E5999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp698 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp698 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6954 = insertelement <4 x float> %tmp698, float %add6953, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6954, <4 x float>* undef, align 16
+ store <4 x float> %vecins6954, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp699 = load <4 x float>, <4 x float>* undef
+ %tmp699 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp700 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp700 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6956 = fadd <4 x float> %tmp700, %tmp699
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6956, <4 x float>* undef, align 16
+ store <4 x float> %add6956, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp701 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp701 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6957 = extractelement <4 x float> %tmp701, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6958 = fadd float %vecext6957, 0xC077633340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp702 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp702 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6959 = insertelement <4 x float> %tmp702, float %add6958, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6959, <4 x float>* undef, align 16
+ store <4 x float> %vecins6959, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp703 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp703 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6963 = extractelement <4 x float> %tmp703, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6964 = fadd float %vecext6963, 0x4068666660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp704 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp704 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6965 = insertelement <4 x float> %tmp704, float %add6964, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6965, <4 x float>* undef, align 16
+ store <4 x float> %vecins6965, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6975 = fadd float undef, 0x406AF33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp705 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp705 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6976 = insertelement <4 x float> %tmp705, float %add6975, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6976, <4 x float>* undef, align 16
+ store <4 x float> %vecins6976, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp706 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp706 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp707 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp707 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6984 = fadd <4 x float> %tmp707, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6984, <4 x float>* undef, align 16
+ store <4 x float> %add6984, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp708 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp708 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6985 = extractelement <4 x float> %tmp708, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6986 = fadd float %vecext6985, 0xC05E266660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp709 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp709 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6987 = insertelement <4 x float> %tmp709, float %add6986, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6987, <4 x float>* undef, align 16
+ store <4 x float> %vecins6987, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp710 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp710 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6988 = extractelement <4 x float> %tmp710, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6989 = fadd float %vecext6988, 0x40706E6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp711 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp711 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins6996 = insertelement <4 x float> %tmp711, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins6996, <4 x float>* undef, align 16
+ store <4 x float> %vecins6996, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x4077A4CCC0000000, float 0xC0757199A0000000, float 0xC072F4CCC0000000, float 0xC071DCCCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0x4077A4CCC0000000, float 0xC0757199A0000000, float 0xC072F4CCC0000000, float 0xC071DCCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp712 = load <4 x float>, <4 x float>* undef
+ %tmp712 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp713 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp713 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add6998 = fadd <4 x float> %tmp713, %tmp712
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add6998, <4 x float>* undef, align 16
+ store <4 x float> %add6998, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp714 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp714 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext6999 = extractelement <4 x float> %tmp714, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7000 = fadd float %vecext6999, 0x4076233340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp715 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp715 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7001 = insertelement <4 x float> %tmp715, float %add7000, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7001, <4 x float>* undef, align 16
+ store <4 x float> %vecins7001, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp716 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp716 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7002 = extractelement <4 x float> %tmp716, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7003 = fadd float %vecext7002, 0x403BCCCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp717 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp717 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7004 = insertelement <4 x float> %tmp717, float %add7003, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp718 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp718 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7140 = fadd float undef, 0x403D333340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -4489,55 +4489,55 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7144 = insertelement <4 x float> undef, float %add7143, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp719 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp719 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7148 = extractelement <4 x float> %tmp719, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7149 = fadd float %vecext7148, 0x4075333340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp720 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp720 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7150 = insertelement <4 x float> %tmp720, float %add7149, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7150, <4 x float>* undef, align 16
+ store <4 x float> %vecins7150, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 1.700000e+02, float 0xC077B4CCC0000000, float 0x40625999A0000000, float 0x406C166660000000>, <4 x float>* undef
+ store <4 x float> <float 1.700000e+02, float 0xC077B4CCC0000000, float 0x40625999A0000000, float 0x406C166660000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp721 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp721 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7152 = fadd <4 x float> %tmp721, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add7152, <4 x float>* undef, align 16
+ store <4 x float> %add7152, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7156 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7157 = fadd float %vecext7156, 0xC05F533340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp722 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp722 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7158 = insertelement <4 x float> %tmp722, float %add7157, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7158, <4 x float>* undef, align 16
+ store <4 x float> %vecins7158, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp723 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp723 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7159 = extractelement <4 x float> %tmp723, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7160 = fadd float %vecext7159, 0x407A5999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp724 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp724 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7161 = insertelement <4 x float> %tmp724, float %add7160, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7161, <4 x float>* undef, align 16
+ store <4 x float> %vecins7161, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7168 = fadd float undef, 0xC072F199A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp725 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp725 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7170 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -4545,13 +4545,13 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7172 = insertelement <4 x float> undef, float %add7171, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7172, <4 x float>* undef, align 16
+ store <4 x float> %vecins7172, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7173 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp726 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp726 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7419 = extractelement <4 x float> %tmp726, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -4559,75 +4559,75 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7421 = insertelement <4 x float> undef, float %add7420, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7421, <4 x float>* undef, align 16
+ store <4 x float> %vecins7421, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp727 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp727 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7422 = extractelement <4 x float> %tmp727, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7423 = fadd float %vecext7422, 4.800000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp728 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp728 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7424 = insertelement <4 x float> %tmp728, float %add7423, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7424, <4 x float>* undef, align 16
+ store <4 x float> %vecins7424, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp729 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp729 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7425 = extractelement <4 x float> %tmp729, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7426 = fadd float %vecext7425, 0xC072C999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp730 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp730 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7427 = insertelement <4 x float> %tmp730, float %add7426, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7427, <4 x float>* undef, align 16
+ store <4 x float> %vecins7427, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7428 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp731 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp731 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7568 = extractelement <4 x float> %tmp731, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7569 = fadd float %vecext7568, 1.090000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp732 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp732 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7570 = insertelement <4 x float> %tmp732, float %add7569, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7570, <4 x float>* undef, align 16
+ store <4 x float> %vecins7570, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40745199A0000000, float 0xC0411999A0000000, float -5.650000e+01, float -4.005000e+02>, <4 x float>* undef
+ store <4 x float> <float 0x40745199A0000000, float 0xC0411999A0000000, float -5.650000e+01, float -4.005000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp733 = load <4 x float>, <4 x float>* undef
+ %tmp733 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp734 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp734 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7572 = fadd <4 x float> %tmp734, %tmp733
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add7572, <4 x float>* undef, align 16
+ store <4 x float> %add7572, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7573 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7574 = fadd float %vecext7573, -3.920000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp735 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp735 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7575 = insertelement <4 x float> %tmp735, float %add7574, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7575, <4 x float>* undef, align 16
+ store <4 x float> %vecins7575, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp736 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp736 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7577 = fadd float undef, 0xC051666660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp737 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp737 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp738 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp738 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7579 = extractelement <4 x float> %tmp738, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -4635,215 +4635,215 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7581 = insertelement <4 x float> undef, float %add7580, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7581, <4 x float>* undef, align 16
+ store <4 x float> %vecins7581, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp739 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp739 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7582 = extractelement <4 x float> %tmp739, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7583 = fadd float %vecext7582, 2.760000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp740 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp740 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7584 = insertelement <4 x float> %tmp740, float %add7583, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC057533340000000, float 0x4060A33340000000, float 0x40791E6660000000, float 2.455000e+02>, <4 x float>* undef
+ store <4 x float> <float 0xC057533340000000, float 0x4060A33340000000, float 0x40791E6660000000, float 2.455000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp741 = load <4 x float>, <4 x float>* undef
+ %tmp741 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp742 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp742 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7586 = fadd <4 x float> %tmp742, %tmp741
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add7586, <4 x float>* undef, align 16
+ store <4 x float> %add7586, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp743 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp743 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7587 = extractelement <4 x float> %tmp743, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7588 = fadd float %vecext7587, 6.100000e+01
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp744 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp744 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp745 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp745 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7590 = extractelement <4 x float> %tmp745, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7591 = fadd float %vecext7590, -3.935000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp746 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp746 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7592 = insertelement <4 x float> %tmp746, float %add7591, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7592, <4 x float>* undef, align 16
+ store <4 x float> %vecins7592, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp747 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp747 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7593 = extractelement <4 x float> %tmp747, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7595 = insertelement <4 x float> undef, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7595, <4 x float>* undef, align 16
+ store <4 x float> %vecins7595, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp748 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp748 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7596 = extractelement <4 x float> %tmp748, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7597 = fadd float %vecext7596, 0x407E666660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x406A766660000000, float 0xBFC99999A0000000, float 0xC0751B3340000000, float -4.075000e+02>, <4 x float>* undef
+ store <4 x float> <float 0x406A766660000000, float 0xBFC99999A0000000, float 0xC0751B3340000000, float -4.075000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp749 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp749 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7616 = fadd float undef, 0xC04DE66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp750 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp750 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7617 = insertelement <4 x float> %tmp750, float %add7616, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7617, <4 x float>* undef, align 16
+ store <4 x float> %vecins7617, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp751 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp751 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7618 = extractelement <4 x float> %tmp751, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7619 = fadd float %vecext7618, 6.050000e+01
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp752 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp752 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7620 = insertelement <4 x float> %tmp752, float %add7619, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7620, <4 x float>* undef, align 16
+ store <4 x float> %vecins7620, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp753 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp753 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7622 = fadd float undef, 0xC054B999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp754 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp754 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7626 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7626, <4 x float>* undef, align 16
+ store <4 x float> %vecins7626, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp755 = load <4 x float>, <4 x float>* undef
+ %tmp755 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp756 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp756 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7628 = fadd <4 x float> %tmp756, %tmp755
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add7628, <4 x float>* undef, align 16
+ store <4 x float> %add7628, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp757 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp757 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7629 = extractelement <4 x float> %tmp757, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7630 = fadd float %vecext7629, 0xC05E2CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp758 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp758 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7631 = insertelement <4 x float> %tmp758, float %add7630, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7639 = fadd float undef, 0x407C5999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp759 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp759 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7640 = insertelement <4 x float> %tmp759, float %add7639, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x406AA66660000000, float 0x4067C66660000000, float 0xC054866660000000, float -2.400000e+01>, <4 x float>* undef
+ store <4 x float> <float 0x406AA66660000000, float 0x4067C66660000000, float 0xC054866660000000, float -2.400000e+01>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp760 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp760 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7642 = fadd <4 x float> %tmp760, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp761 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp761 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7644 = fadd float undef, 0xC0758999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp762 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp762 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7646 = extractelement <4 x float> %tmp762, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7647 = fadd float %vecext7646, 0xC07A3B3340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp763 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp763 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7648 = insertelement <4 x float> %tmp763, float %add7647, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7648, <4 x float>* undef, align 16
+ store <4 x float> %vecins7648, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp764 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp764 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7649 = extractelement <4 x float> %tmp764, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7650 = fadd float %vecext7649, 0x40760CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp765 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp765 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7651 = insertelement <4 x float> %tmp765, float %add7650, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7651, <4 x float>* undef, align 16
+ store <4 x float> %vecins7651, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp766 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp766 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7652 = extractelement <4 x float> %tmp766, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7653 = fadd float %vecext7652, 0x40620CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp767 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp767 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7654 = insertelement <4 x float> %tmp767, float %add7653, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7654, <4 x float>* undef, align 16
+ store <4 x float> %vecins7654, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp768 = load <4 x float>, <4 x float>* undef
+ %tmp768 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp769 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp769 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7656 = fadd <4 x float> %tmp769, %tmp768
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add7656, <4 x float>* undef, align 16
+ store <4 x float> %add7656, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp770 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp770 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7657 = extractelement <4 x float> %tmp770, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7658 = fadd float %vecext7657, 0xC06EF999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp771 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp771 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7659 = insertelement <4 x float> %tmp771, float %add7658, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7659, <4 x float>* undef, align 16
+ store <4 x float> %vecins7659, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp772 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp772 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7660 = extractelement <4 x float> %tmp772, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7661 = fadd float %vecext7660, 0x404B9999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp773 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp773 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7662 = insertelement <4 x float> %tmp773, float %add7661, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7662, <4 x float>* undef, align 16
+ store <4 x float> %vecins7662, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp774 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp774 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7663 = extractelement <4 x float> %tmp774, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7664 = fadd float %vecext7663, 0x4074B66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp775 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp775 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7665 = insertelement <4 x float> %tmp775, float %add7664, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7665, <4 x float>* undef, align 16
+ store <4 x float> %vecins7665, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp776 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp776 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7666 = extractelement <4 x float> %tmp776, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -4851,15 +4851,15 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7668 = insertelement <4 x float> undef, float %add7667, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7668, <4 x float>* undef, align 16
+ store <4 x float> %vecins7668, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp777 = load <4 x float>, <4 x float>* undef
+ %tmp777 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp778 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp778 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7670 = fadd <4 x float> %tmp778, %tmp777
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp779 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp779 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7671 = extractelement <4 x float> %tmp779, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -4867,31 +4867,31 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7726 = fadd <4 x float> undef, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp780 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp780 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7727 = extractelement <4 x float> %tmp780, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp781 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp781 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp782 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp782 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7731 = fadd float undef, 1.900000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp783 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp783 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7732 = insertelement <4 x float> %tmp783, float %add7731, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7732, <4 x float>* undef, align 16
+ store <4 x float> %vecins7732, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp784 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp784 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7735 = insertelement <4 x float> %tmp784, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7735, <4 x float>* undef, align 16
+ store <4 x float> %vecins7735, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp785 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp785 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext7736 = extractelement <4 x float> %tmp785, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -4899,487 +4899,487 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins7850 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins7850, <4 x float>* undef, align 16
+ store <4 x float> %vecins7850, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x4062A33340000000, float 2.290000e+02, float 0x40509999A0000000, float 0xC078BE6660000000>, <4 x float>* undef
+ store <4 x float> <float 0x4062A33340000000, float 2.290000e+02, float 0x40509999A0000000, float 0xC078BE6660000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp786 = load <4 x float>, <4 x float>* undef
+ %tmp786 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp787 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp787 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add7852 = fadd <4 x float> %tmp787, %tmp786
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add7852, <4 x float>* undef, align 16
+ store <4 x float> %add7852, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp788 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp788 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9396 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9397 = fadd float %vecext9396, 0xC074533340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp789 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp789 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9398 = insertelement <4 x float> %tmp789, float %add9397, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9398, <4 x float>* undef, align 16
+ store <4 x float> %vecins9398, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9399 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp790 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp790 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9401 = insertelement <4 x float> %tmp790, float undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp791 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp791 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9402 = extractelement <4 x float> %tmp791, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9403 = fadd float %vecext9402, 0xC03E4CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp792 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp792 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9404 = insertelement <4 x float> %tmp792, float %add9403, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9404, <4 x float>* undef, align 16
+ store <4 x float> %vecins9404, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp793 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp793 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp794 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp794 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9407 = extractelement <4 x float> %tmp794, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9408 = fadd float %vecext9407, 0x407B2999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp795 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp795 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9410 = extractelement <4 x float> %tmp795, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9411 = fadd float %vecext9410, 0x40726E6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp796 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp796 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp797 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp797 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9413 = extractelement <4 x float> %tmp797, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9414 = fadd float %vecext9413, 0xC057ECCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp798 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp798 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9415 = insertelement <4 x float> %tmp798, float %add9414, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9415, <4 x float>* undef, align 16
+ store <4 x float> %vecins9415, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp799 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp799 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9416 = extractelement <4 x float> %tmp799, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9417 = fadd float %vecext9416, 0x406B0CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp800 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp800 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9418 = insertelement <4 x float> %tmp800, float %add9417, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9418, <4 x float>* undef, align 16
+ store <4 x float> %vecins9418, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 3.555000e+02, float 0xC062E33340000000, float 0x4065C66660000000, float -3.645000e+02>, <4 x float>* undef
+ store <4 x float> <float 3.555000e+02, float 0xC062E33340000000, float 0x4065C66660000000, float -3.645000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp801 = load <4 x float>, <4 x float>* undef
+ %tmp801 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp802 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp802 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9420 = fadd <4 x float> %tmp802, %tmp801
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add9420, <4 x float>* undef, align 16
+ store <4 x float> %add9420, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp803 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp803 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9421 = extractelement <4 x float> %tmp803, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp804 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp804 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9423 = insertelement <4 x float> %tmp804, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9423, <4 x float>* undef, align 16
+ store <4 x float> %vecins9423, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp805 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp805 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9424 = extractelement <4 x float> %tmp805, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9425 = fadd float %vecext9424, 0x4079C199A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp806 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp806 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9426 = insertelement <4 x float> %tmp806, float %add9425, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9426, <4 x float>* undef, align 16
+ store <4 x float> %vecins9426, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp807 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp807 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9428 = fadd float undef, 0xC065466660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp808 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp808 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9429 = insertelement <4 x float> %tmp808, float %add9428, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9429, <4 x float>* undef, align 16
+ store <4 x float> %vecins9429, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp809 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp809 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9430 = extractelement <4 x float> %tmp809, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9431 = fadd float %vecext9430, 0xC0742CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp810 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp810 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9432 = insertelement <4 x float> %tmp810, float %add9431, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC07C7E6660000000, float 1.205000e+02, float 0x4050D999A0000000, float 0xC06B233340000000>, <4 x float>* undef
+ store <4 x float> <float 0xC07C7E6660000000, float 1.205000e+02, float 0x4050D999A0000000, float 0xC06B233340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp811 = load <4 x float>, <4 x float>* undef
+ %tmp811 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp812 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp812 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9434 = fadd <4 x float> %tmp812, %tmp811
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9436 = fadd float undef, -3.185000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp813 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp813 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9437 = insertelement <4 x float> %tmp813, float %add9436, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp814 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp814 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp815 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp815 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9441 = extractelement <4 x float> %tmp815, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9442 = fadd float %vecext9441, 0xC079CE6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp816 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp816 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9443 = insertelement <4 x float> %tmp816, float %add9442, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9443, <4 x float>* undef, align 16
+ store <4 x float> %vecins9443, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp817 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp817 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9444 = extractelement <4 x float> %tmp817, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9445 = fadd float %vecext9444, 0xC06F533340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp818 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp818 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9446 = insertelement <4 x float> %tmp818, float %add9445, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9446, <4 x float>* undef, align 16
+ store <4 x float> %vecins9446, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp819 = load <4 x float>, <4 x float>* undef
+ %tmp819 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp820 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp820 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9448 = fadd <4 x float> %tmp820, %tmp819
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add9448, <4 x float>* undef, align 16
+ store <4 x float> %add9448, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9450 = fadd float undef, 0xC0718199A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp821 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp821 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9451 = insertelement <4 x float> %tmp821, float %add9450, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9451, <4 x float>* undef, align 16
+ store <4 x float> %vecins9451, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp822 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp822 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp823 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp823 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9454 = insertelement <4 x float> %tmp823, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9454, <4 x float>* undef, align 16
+ store <4 x float> %vecins9454, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp824 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp824 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9455 = extractelement <4 x float> %tmp824, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9456 = fadd float %vecext9455, -3.380000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp825 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp825 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9457 = insertelement <4 x float> %tmp825, float %add9456, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9457, <4 x float>* undef, align 16
+ store <4 x float> %vecins9457, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9458 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp826 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp826 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9460 = insertelement <4 x float> %tmp826, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9460, <4 x float>* undef, align 16
+ store <4 x float> %vecins9460, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x407B5E6660000000, float 0x40648999A0000000, float 0xC06B966660000000, float 0x40341999A0000000>, <4 x float>* undef
+ store <4 x float> <float 0x407B5E6660000000, float 0x40648999A0000000, float 0xC06B966660000000, float 0x40341999A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp827 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp827 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9462 = fadd <4 x float> %tmp827, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add9462, <4 x float>* undef, align 16
+ store <4 x float> %add9462, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp828 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp828 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9463 = extractelement <4 x float> %tmp828, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp829 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp829 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9465 = insertelement <4 x float> %tmp829, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9467 = fadd float undef, 0x405D666660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp830 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp830 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9468 = insertelement <4 x float> %tmp830, float %add9467, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9468, <4 x float>* undef, align 16
+ store <4 x float> %vecins9468, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp831 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp831 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9470 = fadd float undef, 0x4077033340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp832 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp832 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9472 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9473 = fadd float %vecext9472, 0x402DCCCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp833 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp833 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9474 = insertelement <4 x float> %tmp833, float %add9473, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9474, <4 x float>* undef, align 16
+ store <4 x float> %vecins9474, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x404F733340000000, float 0x407AB4CCC0000000, float 0x40605999A0000000, float 0xC03E4CCCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0x404F733340000000, float 0x407AB4CCC0000000, float 0x40605999A0000000, float 0xC03E4CCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp834 = load <4 x float>, <4 x float>* undef
+ %tmp834 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp835 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp835 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9476 = fadd <4 x float> %tmp835, %tmp834
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add9476, <4 x float>* undef, align 16
+ store <4 x float> %add9476, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp836 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp836 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9477 = extractelement <4 x float> %tmp836, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9478 = fadd float %vecext9477, 0xC07F266660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp837 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp837 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9479 = insertelement <4 x float> %tmp837, float %add9478, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9479, <4 x float>* undef, align 16
+ store <4 x float> %vecins9479, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp838 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp838 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9481 = fadd float undef, 0x407BE33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp839 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp839 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9482 = insertelement <4 x float> %tmp839, float %add9481, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9482, <4 x float>* undef, align 16
+ store <4 x float> %vecins9482, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9483 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9484 = fadd float %vecext9483, 0xC073E999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp840 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp840 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9485 = insertelement <4 x float> %tmp840, float %add9484, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9485, <4 x float>* undef, align 16
+ store <4 x float> %vecins9485, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp841 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp841 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9486 = extractelement <4 x float> %tmp841, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9487 = fadd float %vecext9486, 0x4076E66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp842 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp842 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC076B999A0000000, float 0xC0706CCCC0000000, float 0x407904CCC0000000, float 0x407EE199A0000000>, <4 x float>* undef
+ store <4 x float> <float 0xC076B999A0000000, float 0xC0706CCCC0000000, float 0x407904CCC0000000, float 0x407EE199A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp843 = load <4 x float>, <4 x float>* undef
+ %tmp843 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp844 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp844 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9491 = extractelement <4 x float> %tmp844, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9492 = fadd float %vecext9491, 0x407C166660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9495 = fadd float undef, 0x407DBB3340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp845 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp845 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9496 = insertelement <4 x float> %tmp845, float %add9495, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9496, <4 x float>* undef, align 16
+ store <4 x float> %vecins9496, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp846 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp846 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9497 = extractelement <4 x float> %tmp846, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9498 = fadd float %vecext9497, 0x4042CCCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp847 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp847 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9499 = insertelement <4 x float> %tmp847, float %add9498, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9499, <4 x float>* undef, align 16
+ store <4 x float> %vecins9499, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp848 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp848 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9501 = fadd float undef, 0x407D5CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp849 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp849 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9502 = insertelement <4 x float> %tmp849, float %add9501, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9502, <4 x float>* undef, align 16
+ store <4 x float> %vecins9502, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp850 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp850 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9504 = fadd <4 x float> %tmp850, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add9504, <4 x float>* undef, align 16
+ store <4 x float> %add9504, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp851 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp851 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9506 = fadd float undef, 0x4076EE6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp852 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp852 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9507 = insertelement <4 x float> %tmp852, float %add9506, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9507, <4 x float>* undef, align 16
+ store <4 x float> %vecins9507, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp853 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp853 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9509 = fadd float undef, 0xC0535999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp854 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp854 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp855 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp855 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9511 = extractelement <4 x float> %tmp855, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9512 = fadd float %vecext9511, 0xC076766660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp856 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp856 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9513 = insertelement <4 x float> %tmp856, float %add9512, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9513, <4 x float>* undef, align 16
+ store <4 x float> %vecins9513, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp857 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp857 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9514 = extractelement <4 x float> %tmp857, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp858 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp858 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9516 = insertelement <4 x float> %tmp858, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9516, <4 x float>* undef, align 16
+ store <4 x float> %vecins9516, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x407254CCC0000000, float 0x407844CCC0000000, float 0xC04D9999A0000000, float 0xC0550CCCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0x407254CCC0000000, float 0x407844CCC0000000, float 0xC04D9999A0000000, float 0xC0550CCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp859 = load <4 x float>, <4 x float>* undef
+ %tmp859 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp860 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp860 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9518 = fadd <4 x float> %tmp860, %tmp859
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp861 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp861 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp862 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp862 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9521 = insertelement <4 x float> %tmp862, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9521, <4 x float>* undef, align 16
+ store <4 x float> %vecins9521, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp863 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp863 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9522 = extractelement <4 x float> %tmp863, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9523 = fadd float %vecext9522, 0x4029333340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp864 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp864 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9524 = insertelement <4 x float> %tmp864, float %add9523, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9524, <4 x float>* undef, align 16
+ store <4 x float> %vecins9524, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp865 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp865 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9526 = fadd float undef, 0x4072833340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp866 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp866 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9527 = insertelement <4 x float> %tmp866, float %add9526, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9527, <4 x float>* undef, align 16
+ store <4 x float> %vecins9527, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp867 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp867 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9530 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9530, <4 x float>* undef, align 16
+ store <4 x float> %vecins9530, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x4072F4CCC0000000, float 0x4065CCCCC0000000, float 0x4051D33340000000, float 0x40680CCCC0000000>, <4 x float>* undef
+ store <4 x float> <float 0x4072F4CCC0000000, float 0x4065CCCCC0000000, float 0x4051D33340000000, float 0x40680CCCC0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp868 = load <4 x float>, <4 x float>* undef
+ %tmp868 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp869 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp869 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9532 = fadd <4 x float> %tmp869, %tmp868
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9533 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp870 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp870 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9535 = insertelement <4 x float> %tmp870, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9535, <4 x float>* undef, align 16
+ store <4 x float> %vecins9535, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp871 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp871 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9536 = extractelement <4 x float> %tmp871, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9537 = fadd float %vecext9536, 0xC079F199A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp872 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp872 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9538 = insertelement <4 x float> %tmp872, float %add9537, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9538, <4 x float>* undef, align 16
+ store <4 x float> %vecins9538, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp873 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp873 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9542 = extractelement <4 x float> %tmp873, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -5389,77 +5389,77 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9577 = insertelement <4 x float> undef, float %add9576, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9577, <4 x float>* undef, align 16
+ store <4 x float> %vecins9577, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp874 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp874 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9580 = insertelement <4 x float> undef, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9580, <4 x float>* undef, align 16
+ store <4 x float> %vecins9580, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp875 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp875 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9581 = extractelement <4 x float> %tmp875, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9582 = fadd float %vecext9581, 0xC07EF33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp876 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp876 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9583 = insertelement <4 x float> %tmp876, float %add9582, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9583, <4 x float>* undef, align 16
+ store <4 x float> %vecins9583, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp877 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp877 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9673 = extractelement <4 x float> undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9674 = fadd float %vecext9673, 0xC04CF33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp878 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp878 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9675 = insertelement <4 x float> %tmp878, float %add9674, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9675, <4 x float>* undef, align 16
+ store <4 x float> %vecins9675, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9676 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9677 = fadd float %vecext9676, 1.455000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp879 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp879 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9678 = insertelement <4 x float> %tmp879, float %add9677, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp880 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp880 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9679 = extractelement <4 x float> %tmp880, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9680 = fadd float %vecext9679, 0x4073A33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp881 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp881 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9681 = insertelement <4 x float> %tmp881, float %add9680, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9681, <4 x float>* undef, align 16
+ store <4 x float> %vecins9681, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp882 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp882 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9682 = extractelement <4 x float> %tmp882, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp883 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp883 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9686 = fadd <4 x float> %tmp883, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add9686, <4 x float>* undef, align 16
+ store <4 x float> %add9686, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp884 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp884 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9687 = extractelement <4 x float> %tmp884, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9688 = fadd float %vecext9687, 0xC046666660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp885 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp885 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9689 = insertelement <4 x float> %tmp885, float %add9688, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -5467,193 +5467,193 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9691 = fadd float %vecext9690, 0x4034CCCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp886 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp886 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9692 = insertelement <4 x float> %tmp886, float %add9691, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp887 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp887 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9693 = extractelement <4 x float> %tmp887, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9694 = fadd float %vecext9693, -3.710000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp888 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp888 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9695 = insertelement <4 x float> %tmp888, float %add9694, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9695, <4 x float>* undef, align 16
+ store <4 x float> %vecins9695, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp889 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp889 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9697 = fadd float undef, 0x4058D33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp890 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp890 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9698 = insertelement <4 x float> %tmp890, float %add9697, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9698, <4 x float>* undef, align 16
+ store <4 x float> %vecins9698, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x4062CCCCC0000000, float 0x407AD999A0000000, float 0x40582CCCC0000000, float 0xC0712B3340000000>, <4 x float>* undef
+ store <4 x float> <float 0x4062CCCCC0000000, float 0x407AD999A0000000, float 0x40582CCCC0000000, float 0xC0712B3340000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp891 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp891 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9700 = fadd <4 x float> %tmp891, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp892 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp892 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9701 = extractelement <4 x float> %tmp892, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9702 = fadd float %vecext9701, 0x406DC33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp893 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp893 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9703 = insertelement <4 x float> %tmp893, float %add9702, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9703, <4 x float>* undef, align 16
+ store <4 x float> %vecins9703, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp894 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp894 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9704 = extractelement <4 x float> %tmp894, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9705 = fadd float %vecext9704, 0xC073B33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp895 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp895 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9706 = insertelement <4 x float> %tmp895, float %add9705, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9706, <4 x float>* undef, align 16
+ store <4 x float> %vecins9706, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9707 = extractelement <4 x float> undef, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9708 = fadd float %vecext9707, 0xC0729999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp896 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp896 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9709 = insertelement <4 x float> %tmp896, float %add9708, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9709, <4 x float>* undef, align 16
+ store <4 x float> %vecins9709, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp897 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp897 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9710 = extractelement <4 x float> %tmp897, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9712 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9712, <4 x float>* undef, align 16
+ store <4 x float> %vecins9712, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x4069F33340000000, float 0xC048266660000000, float 0x40638CCCC0000000, float 0xC07EC199A0000000>, <4 x float>* undef
+ store <4 x float> <float 0x4069F33340000000, float 0xC048266660000000, float 0x40638CCCC0000000, float 0xC07EC199A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp898 = load <4 x float>, <4 x float>* undef
+ %tmp898 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9714 = fadd <4 x float> undef, %tmp898
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add9714, <4 x float>* undef, align 16
+ store <4 x float> %add9714, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp899 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp899 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9715 = extractelement <4 x float> %tmp899, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp900 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp900 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9717 = insertelement <4 x float> %tmp900, float undef, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9717, <4 x float>* undef, align 16
+ store <4 x float> %vecins9717, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp901 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp901 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9718 = extractelement <4 x float> %tmp901, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9719 = fadd float %vecext9718, 0x406BC66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp902 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp902 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9720 = insertelement <4 x float> %tmp902, float %add9719, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9720, <4 x float>* undef, align 16
+ store <4 x float> %vecins9720, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp903 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp903 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9721 = extractelement <4 x float> %tmp903, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9722 = fadd float %vecext9721, -3.860000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp904 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp904 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9723 = insertelement <4 x float> %tmp904, float %add9722, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9723, <4 x float>* undef, align 16
+ store <4 x float> %vecins9723, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp905 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp905 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9724 = extractelement <4 x float> %tmp905, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9725 = fadd float %vecext9724, 0x407CF199A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp906 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp906 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9726 = insertelement <4 x float> %tmp906, float %add9725, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9726, <4 x float>* undef, align 16
+ store <4 x float> %vecins9726, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float -4.575000e+02, float 0x40713E6660000000, float 0x407D133340000000, float -1.425000e+02>, <4 x float>* undef
+ store <4 x float> <float -4.575000e+02, float 0x40713E6660000000, float 0x407D133340000000, float -1.425000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp907 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp907 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9728 = fadd <4 x float> %tmp907, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add9728, <4 x float>* undef, align 16
+ store <4 x float> %add9728, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp908 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp908 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9729 = extractelement <4 x float> %tmp908, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9730 = fadd float %vecext9729, 0x4079FB3340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp909 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp909 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9731 = insertelement <4 x float> %tmp909, float %add9730, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9731, <4 x float>* undef, align 16
+ store <4 x float> %vecins9731, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp910 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp910 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9733 = fadd float undef, 0xC050F33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp911 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp911 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9734 = insertelement <4 x float> %tmp911, float %add9733, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9734, <4 x float>* undef, align 16
+ store <4 x float> %vecins9734, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp912 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp912 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9735 = extractelement <4 x float> %tmp912, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9736 = fadd float %vecext9735, 0x40582CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp913 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp913 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9737 = insertelement <4 x float> %tmp913, float %add9736, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9737, <4 x float>* undef, align 16
+ store <4 x float> %vecins9737, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp914 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp914 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9738 = extractelement <4 x float> %tmp914, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9740 = insertelement <4 x float> undef, float undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9740, <4 x float>* undef, align 16
+ store <4 x float> %vecins9740, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 2.150000e+02, float 0x405A2CCCC0000000, float 2.310000e+02, float 0x404E1999A0000000>, <4 x float>* undef
+ store <4 x float> <float 2.150000e+02, float 0x405A2CCCC0000000, float 2.310000e+02, float 0x404E1999A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp915 = load <4 x float>, <4 x float>* undef
+ %tmp915 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp916 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp916 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp917 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp917 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9743 = extractelement <4 x float> %tmp917, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -5661,313 +5661,313 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9745 = insertelement <4 x float> undef, float %add9744, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9745, <4 x float>* undef, align 16
+ store <4 x float> %vecins9745, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp918 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp918 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9746 = extractelement <4 x float> %tmp918, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9747 = fadd float %vecext9746, 4.685000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp919 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp919 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9748 = insertelement <4 x float> %tmp919, float %add9747, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9748, <4 x float>* undef, align 16
+ store <4 x float> %vecins9748, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp920 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp920 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9749 = extractelement <4 x float> %tmp920, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9750 = fadd float %vecext9749, 1.600000e+01
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp921 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp921 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9751 = insertelement <4 x float> %tmp921, float %add9750, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9751, <4 x float>* undef, align 16
+ store <4 x float> %vecins9751, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp922 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp922 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9752 = extractelement <4 x float> %tmp922, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9753 = fadd float %vecext9752, -2.600000e+01
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp923 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp923 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9754 = insertelement <4 x float> %tmp923, float %add9753, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9754, <4 x float>* undef, align 16
+ store <4 x float> %vecins9754, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 2.590000e+02, float 0x407B7199A0000000, float 0xC07ED199A0000000, float 0xC064FCCCC0000000>, <4 x float>* %.compoundliteral9755
+ store <4 x float> <float 2.590000e+02, float 0x407B7199A0000000, float 0xC07ED199A0000000, float 0xC064FCCCC0000000>, ptr %.compoundliteral9755
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp924 = load <4 x float>, <4 x float>* %.compoundliteral9755
+ %tmp924 = load <4 x float>, ptr %.compoundliteral9755
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp925 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp925 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9756 = fadd <4 x float> %tmp925, %tmp924
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp926 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp926 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9757 = extractelement <4 x float> %tmp926, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9758 = fadd float %vecext9757, -1.810000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp927 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp927 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9759 = insertelement <4 x float> %tmp927, float %add9758, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9759, <4 x float>* undef, align 16
+ store <4 x float> %vecins9759, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp928 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp928 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9760 = extractelement <4 x float> %tmp928, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9761 = fadd float %vecext9760, 0xC07C3E6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp929 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp929 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9762 = insertelement <4 x float> %tmp929, float %add9761, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9762, <4 x float>* undef, align 16
+ store <4 x float> %vecins9762, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp930 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp930 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9764 = fadd float undef, 0xC060E66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp931 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp931 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9765 = insertelement <4 x float> %tmp931, float %add9764, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9765, <4 x float>* undef, align 16
+ store <4 x float> %vecins9765, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp932 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp932 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9766 = extractelement <4 x float> %tmp932, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9767 = fadd float %vecext9766, 0xC0753E6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp933 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp933 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9768 = insertelement <4 x float> %tmp933, float %add9767, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9768, <4 x float>* undef, align 16
+ store <4 x float> %vecins9768, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x4032CCCCC0000000, float -9.600000e+01, float -5.000000e+02, float 0x4078EE6660000000>, <4 x float>* %.compoundliteral9769
+ store <4 x float> <float 0x4032CCCCC0000000, float -9.600000e+01, float -5.000000e+02, float 0x4078EE6660000000>, ptr %.compoundliteral9769
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp934 = load <4 x float>, <4 x float>* %.compoundliteral9769
+ %tmp934 = load <4 x float>, ptr %.compoundliteral9769
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp935 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp935 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9770 = fadd <4 x float> %tmp935, %tmp934
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add9770, <4 x float>* undef, align 16
+ store <4 x float> %add9770, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp936 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp936 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9771 = extractelement <4 x float> %tmp936, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9772 = fadd float %vecext9771, 0xC0733E6660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp937 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp937 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9773 = insertelement <4 x float> %tmp937, float %add9772, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9773, <4 x float>* undef, align 16
+ store <4 x float> %vecins9773, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp938 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp938 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9774 = extractelement <4 x float> %tmp938, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add9775 = fadd float %vecext9774, 1.715000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp939 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp939 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9776 = insertelement <4 x float> %tmp939, float %add9775, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins9776, <4 x float>* undef, align 16
+ store <4 x float> %vecins9776, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext9816 = extractelement <4 x float> undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp940 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp940 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins9818 = insertelement <4 x float> %tmp940, float undef, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp941 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp941 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10388 = fadd float undef, 4.755000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp942 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp942 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10389 = insertelement <4 x float> %tmp942, float %add10388, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10389, <4 x float>* undef, align 16
+ store <4 x float> %vecins10389, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp943 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp943 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10390 = extractelement <4 x float> %tmp943, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10391 = fadd float %vecext10390, 0xC05AECCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp944 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp944 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10392 = insertelement <4 x float> %tmp944, float %add10391, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10392, <4 x float>* undef, align 16
+ store <4 x float> %vecins10392, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp945 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp945 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp946 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp946 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10405 = fadd float undef, -5.650000e+01
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp947 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp947 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10406 = insertelement <4 x float> %tmp947, float %add10405, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10406, <4 x float>* undef, align 16
+ store <4 x float> %vecins10406, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp948 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp948 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10407 = extractelement <4 x float> %tmp948, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10408 = fadd float %vecext10407, 0xC06A633340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp949 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp949 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10409 = insertelement <4 x float> %tmp949, float %add10408, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10409, <4 x float>* undef, align 16
+ store <4 x float> %vecins10409, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp950 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp950 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10410 = extractelement <4 x float> %tmp950, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10411 = fadd float %vecext10410, 0xC078D66660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp951 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp951 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float -2.340000e+02, float -4.720000e+02, float 4.350000e+02, float 0xC059A66660000000>, <4 x float>* %.compoundliteral10413
+ store <4 x float> <float -2.340000e+02, float -4.720000e+02, float 4.350000e+02, float 0xC059A66660000000>, ptr %.compoundliteral10413
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp952 = load <4 x float>, <4 x float>* %.compoundliteral10413
+ %tmp952 = load <4 x float>, ptr %.compoundliteral10413
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp953 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp953 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10414 = fadd <4 x float> %tmp953, %tmp952
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add10414, <4 x float>* undef, align 16
+ store <4 x float> %add10414, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp954 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp954 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10415 = extractelement <4 x float> %tmp954, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10416 = fadd float %vecext10415, 3.450000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp955 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp955 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10417 = insertelement <4 x float> %tmp955, float %add10416, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10417, <4 x float>* undef, align 16
+ store <4 x float> %vecins10417, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp956 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp956 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10418 = extractelement <4 x float> %tmp956, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10419 = fadd float %vecext10418, -6.000000e+00
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp957 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp957 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10420 = insertelement <4 x float> %tmp957, float %add10419, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10420, <4 x float>* undef, align 16
+ store <4 x float> %vecins10420, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10422 = fadd float undef, 0xC0662CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10424 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x402B333340000000, float 0x40735E6660000000, float 0xC0567999A0000000, float 2.050000e+02>, <4 x float>* undef
+ store <4 x float> <float 0x402B333340000000, float 0x40735E6660000000, float 0xC0567999A0000000, float 2.050000e+02>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp958 = load <4 x float>, <4 x float>* undef
+ %tmp958 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp959 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp959 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10428 = fadd <4 x float> %tmp959, %tmp958
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add10428, <4 x float>* undef, align 16
+ store <4 x float> %add10428, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp960 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp960 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10429 = extractelement <4 x float> %tmp960, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10430 = fadd float %vecext10429, 0xC075166660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp961 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp961 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10436 = fadd float undef, 0xC06AF33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp962 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp962 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10437 = insertelement <4 x float> %tmp962, float %add10436, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10437, <4 x float>* undef, align 16
+ store <4 x float> %vecins10437, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10438 = extractelement <4 x float> undef, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10439 = fadd float %vecext10438, 0x405C7999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp963 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp963 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10440 = insertelement <4 x float> %tmp963, float %add10439, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10440, <4 x float>* undef, align 16
+ store <4 x float> %vecins10440, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC065E999A0000000, float 0x4067D33340000000, float 0xC070133340000000, float 0x406B666660000000>, <4 x float>* undef
+ store <4 x float> <float 0xC065E999A0000000, float 0x4067D33340000000, float 0xC070133340000000, float 0x406B666660000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp964 = load <4 x float>, <4 x float>* undef
+ %tmp964 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp965 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp965 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10443 = extractelement <4 x float> %tmp965, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10444 = fadd float %vecext10443, 0xC06CA999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp966 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp966 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10445 = insertelement <4 x float> %tmp966, float %add10444, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10445, <4 x float>* undef, align 16
+ store <4 x float> %vecins10445, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp967 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp967 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10446 = extractelement <4 x float> %tmp967, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10447 = fadd float %vecext10446, 0x4064B999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp968 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp968 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10448 = insertelement <4 x float> %tmp968, float %add10447, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10448, <4 x float>* undef, align 16
+ store <4 x float> %vecins10448, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp969 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp969 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10449 = extractelement <4 x float> %tmp969, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10450 = fadd float %vecext10449, 0x407B3CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp970 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp970 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10451 = insertelement <4 x float> %tmp970, float %add10450, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10451, <4 x float>* undef, align 16
+ store <4 x float> %vecins10451, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp971 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp971 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10452 = extractelement <4 x float> %tmp971, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -5975,17 +5975,17 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10454 = insertelement <4 x float> undef, float %add10453, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x406AFCCCC0000000, float 0xC07604CCC0000000, float 6.900000e+01, float 0xC060A66660000000>, <4 x float>* undef
+ store <4 x float> <float 0x406AFCCCC0000000, float 0xC07604CCC0000000, float 6.900000e+01, float 0xC060A66660000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp972 = load <4 x float>, <4 x float>* undef
+ %tmp972 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp973 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp973 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10456 = fadd <4 x float> %tmp973, %tmp972
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %add10456, <4 x float>* undef, align 16
+ store <4 x float> %add10456, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp974 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp974 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10457 = extractelement <4 x float> %tmp974, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
@@ -5993,852 +5993,852 @@ entry:
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10459 = insertelement <4 x float> undef, float %add10458, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10459, <4 x float>* undef, align 16
+ store <4 x float> %vecins10459, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp975 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp975 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10460 = extractelement <4 x float> %tmp975, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10461 = fadd float %vecext10460, 0xC06B3999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp976 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp976 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10462 = insertelement <4 x float> %tmp976, float %add10461, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp977 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp977 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10463 = extractelement <4 x float> %tmp977, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10464 = fadd float %vecext10463, 0x40655999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp978 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp978 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10465 = insertelement <4 x float> %tmp978, float %add10464, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10465, <4 x float>* undef, align 16
+ store <4 x float> %vecins10465, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp979 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp979 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10466 = extractelement <4 x float> %tmp979, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10467 = fadd float %vecext10466, 0xC07B6999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp980 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp980 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10468 = insertelement <4 x float> %tmp980, float %add10467, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10468, <4 x float>* undef, align 16
+ store <4 x float> %vecins10468, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x4078833340000000, float 0x40786CCCC0000000, float 0xC0468CCCC0000000, float 0xC0793199A0000000>, <4 x float>* undef
+ store <4 x float> <float 0x4078833340000000, float 0x40786CCCC0000000, float 0xC0468CCCC0000000, float 0xC0793199A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp981 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp981 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10470 = fadd <4 x float> %tmp981, undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp982 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp982 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10471 = extractelement <4 x float> %tmp982, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10472 = fadd float %vecext10471, 0x40710CCCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp983 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp983 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10473 = insertelement <4 x float> %tmp983, float %add10472, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10473, <4 x float>* undef, align 16
+ store <4 x float> %vecins10473, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp984 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp984 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10474 = extractelement <4 x float> %tmp984, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10475 = fadd float %vecext10474, 0x40709B3340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp985 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp985 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10476 = insertelement <4 x float> %tmp985, float %add10475, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10476, <4 x float>* undef, align 16
+ store <4 x float> %vecins10476, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10489 = fadd float undef, 0x4074666660000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp986 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp986 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10490 = insertelement <4 x float> %tmp986, float %add10489, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10490, <4 x float>* undef, align 16
+ store <4 x float> %vecins10490, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp987 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp987 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp988 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp988 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10508 = extractelement <4 x float> %tmp988, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10509 = fadd float %vecext10508, 0xC027333340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp989 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp989 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10510 = insertelement <4 x float> %tmp989, float %add10509, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10510, <4 x float>* undef, align 16
+ store <4 x float> %vecins10510, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0x40656999A0000000, float 0xC073766660000000, float 1.685000e+02, float 0x40765199A0000000>, <4 x float>* undef
+ store <4 x float> <float 0x40656999A0000000, float 0xC073766660000000, float 1.685000e+02, float 0x40765199A0000000>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp990 = load <4 x float>, <4 x float>* undef
+ %tmp990 = load <4 x float>, ptr undef
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10512 = fadd <4 x float> undef, %tmp990
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp991 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp991 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10513 = extractelement <4 x float> %tmp991, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10514 = fadd float %vecext10513, 0x405BB999A0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp992 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp992 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10515 = insertelement <4 x float> %tmp992, float %add10514, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10515, <4 x float>* undef, align 16
+ store <4 x float> %vecins10515, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp993 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp993 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10562 = fadd float undef, 2.035000e+02
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp994 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp994 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10563 = insertelement <4 x float> %tmp994, float %add10562, i32 2
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10563, <4 x float>* undef, align 16
+ store <4 x float> %vecins10563, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp995 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp995 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10564 = extractelement <4 x float> %tmp995, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10565 = fadd float %vecext10564, 0x407AE4CCC0000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp996 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp996 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10566 = insertelement <4 x float> %tmp996, float %add10565, i32 3
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10566, <4 x float>* undef, align 16
+ store <4 x float> %vecins10566, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> <float 0xC068B999A0000000, float 0xC050E66660000000, float 0xC0725999A0000000, float 0xC054D33340000000>, <4 x float>* %.compoundliteral10567
+ store <4 x float> <float 0xC068B999A0000000, float 0xC050E66660000000, float 0xC0725999A0000000, float 0xC054D33340000000>, ptr %.compoundliteral10567
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp997 = load <4 x float>, <4 x float>* %.compoundliteral10567
+ %tmp997 = load <4 x float>, ptr %.compoundliteral10567
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp998 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp998 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10568 = fadd <4 x float> %tmp998, %tmp997
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp999 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp999 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10569 = extractelement <4 x float> %tmp999, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10570 = fadd float %vecext10569, 0x4074C33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp1000 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1000 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10571 = insertelement <4 x float> %tmp1000, float %add10570, i32 0
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10571, <4 x float>* undef, align 16
+ store <4 x float> %vecins10571, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp1001 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1001 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecext10572 = extractelement <4 x float> %tmp1001, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%add10573 = fadd float %vecext10572, 0x407DF33340000000
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- %tmp1002 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1002 = load <4 x float>, ptr undef, align 16
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
%vecins10574 = insertelement <4 x float> %tmp1002, float %add10573, i32 1
tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"()
- store <4 x float> %vecins10574, <4 x float>* undef, align 16
- %tmp1003 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10574, ptr undef, align 16
+ %tmp1003 = load <4 x float>, ptr undef, align 16
%vecext10575 = extractelement <4 x float> %tmp1003, i32 2
- %tmp1004 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1004 = load <4 x float>, ptr undef, align 16
%vecins10577 = insertelement <4 x float> %tmp1004, float undef, i32 2
- store <4 x float> %vecins10577, <4 x float>* undef, align 16
- %tmp1005 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10577, ptr undef, align 16
+ %tmp1005 = load <4 x float>, ptr undef, align 16
%vecext10578 = extractelement <4 x float> %tmp1005, i32 3
%add10579 = fadd float %vecext10578, 0x4076566660000000
- %tmp1006 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1006 = load <4 x float>, ptr undef, align 16
%vecins10580 = insertelement <4 x float> %tmp1006, float %add10579, i32 3
- store <4 x float> %vecins10580, <4 x float>* undef, align 16
- store <4 x float> <float 0x407CAB3340000000, float 1.685000e+02, float 0xC07B866660000000, float 0xC061ACCCC0000000>, <4 x float>* %.compoundliteral10581
- %tmp1007 = load <4 x float>, <4 x float>* %.compoundliteral10581
- store <4 x float> undef, <4 x float>* undef, align 16
- %tmp1008 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10580, ptr undef, align 16
+ store <4 x float> <float 0x407CAB3340000000, float 1.685000e+02, float 0xC07B866660000000, float 0xC061ACCCC0000000>, ptr %.compoundliteral10581
+ %tmp1007 = load <4 x float>, ptr %.compoundliteral10581
+ store <4 x float> undef, ptr undef, align 16
+ %tmp1008 = load <4 x float>, ptr undef, align 16
%vecext10583 = extractelement <4 x float> %tmp1008, i32 0
%add10584 = fadd float %vecext10583, 0xC060533340000000
- %tmp1009 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1009 = load <4 x float>, ptr undef, align 16
%vecins10585 = insertelement <4 x float> %tmp1009, float %add10584, i32 0
- store <4 x float> %vecins10585, <4 x float>* undef, align 16
- %tmp1010 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10585, ptr undef, align 16
+ %tmp1010 = load <4 x float>, ptr undef, align 16
%vecext10586 = extractelement <4 x float> %tmp1010, i32 1
%add10587 = fadd float %vecext10586, 0xC0694CCCC0000000
- %tmp1011 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1011 = load <4 x float>, ptr undef, align 16
%vecins10588 = insertelement <4 x float> %tmp1011, float %add10587, i32 1
- store <4 x float> %vecins10588, <4 x float>* undef, align 16
- %tmp1012 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10588, ptr undef, align 16
+ %tmp1012 = load <4 x float>, ptr undef, align 16
%vecext10589 = extractelement <4 x float> %tmp1012, i32 2
%add10590 = fadd float %vecext10589, 0xC0541999A0000000
- %tmp1013 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1013 = load <4 x float>, ptr undef, align 16
%vecins10591 = insertelement <4 x float> %tmp1013, float %add10590, i32 2
- store <4 x float> %vecins10591, <4 x float>* undef, align 16
- %tmp1014 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10591, ptr undef, align 16
+ %tmp1014 = load <4 x float>, ptr undef, align 16
%vecext10592 = extractelement <4 x float> %tmp1014, i32 3
%add10593 = fadd float %vecext10592, 0xC06C566660000000
- %tmp1015 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1015 = load <4 x float>, ptr undef, align 16
%vecins10594 = insertelement <4 x float> %tmp1015, float %add10593, i32 3
- store <4 x float> %vecins10594, <4 x float>* undef, align 16
- store <4 x float> <float 0x407A3199A0000000, float 0xC0659999A0000000, float 0x407E0999A0000000, float 0xC0334CCCC0000000>, <4 x float>* %.compoundliteral10595
- %tmp1016 = load <4 x float>, <4 x float>* %.compoundliteral10595
- %tmp1017 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10594, ptr undef, align 16
+ store <4 x float> <float 0x407A3199A0000000, float 0xC0659999A0000000, float 0x407E0999A0000000, float 0xC0334CCCC0000000>, ptr %.compoundliteral10595
+ %tmp1016 = load <4 x float>, ptr %.compoundliteral10595
+ %tmp1017 = load <4 x float>, ptr undef, align 16
%add10596 = fadd <4 x float> %tmp1017, %tmp1016
- store <4 x float> %add10596, <4 x float>* undef, align 16
- %tmp1018 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %add10596, ptr undef, align 16
+ %tmp1018 = load <4 x float>, ptr undef, align 16
%vecext10597 = extractelement <4 x float> %tmp1018, i32 0
%add10598 = fadd float %vecext10597, 0x40640999A0000000
- %tmp1019 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1019 = load <4 x float>, ptr undef, align 16
%vecins10599 = insertelement <4 x float> %tmp1019, float %add10598, i32 0
- store <4 x float> %vecins10599, <4 x float>* undef, align 16
- %tmp1020 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10599, ptr undef, align 16
+ %tmp1020 = load <4 x float>, ptr undef, align 16
%vecext10600 = extractelement <4 x float> %tmp1020, i32 1
%add10601 = fadd float %vecext10600, 0xC073966660000000
- %tmp1021 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1021 = load <4 x float>, ptr undef, align 16
%vecins10602 = insertelement <4 x float> %tmp1021, float %add10601, i32 1
- %tmp1022 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1022 = load <4 x float>, ptr undef, align 16
%vecext10603 = extractelement <4 x float> %tmp1022, i32 2
%add10604 = fadd float %vecext10603, 1.780000e+02
- %tmp1023 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1023 = load <4 x float>, ptr undef, align 16
%vecins10605 = insertelement <4 x float> %tmp1023, float %add10604, i32 2
- store <4 x float> %vecins10605, <4 x float>* undef, align 16
- %tmp1024 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10605, ptr undef, align 16
+ %tmp1024 = load <4 x float>, ptr undef, align 16
%add10607 = fadd float undef, 0x4070A33340000000
- %tmp1025 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> <float 0x407C5999A0000000, float 0x4046733340000000, float 0xC06E6CCCC0000000, float 0xC063C33340000000>, <4 x float>* %.compoundliteral10609
- %tmp1026 = load <4 x float>, <4 x float>* %.compoundliteral10609
- %tmp1027 = load <4 x float>, <4 x float>* undef, align 16
- %tmp1028 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1025 = load <4 x float>, ptr undef, align 16
+ store <4 x float> <float 0x407C5999A0000000, float 0x4046733340000000, float 0xC06E6CCCC0000000, float 0xC063C33340000000>, ptr %.compoundliteral10609
+ %tmp1026 = load <4 x float>, ptr %.compoundliteral10609
+ %tmp1027 = load <4 x float>, ptr undef, align 16
+ %tmp1028 = load <4 x float>, ptr undef, align 16
%vecext10611 = extractelement <4 x float> %tmp1028, i32 0
%add10612 = fadd float %vecext10611, 0x40757199A0000000
%vecins10613 = insertelement <4 x float> undef, float %add10612, i32 0
- store <4 x float> %vecins10613, <4 x float>* undef, align 16
- %tmp1029 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10613, ptr undef, align 16
+ %tmp1029 = load <4 x float>, ptr undef, align 16
%vecext10614 = extractelement <4 x float> %tmp1029, i32 1
%add10615 = fadd float %vecext10614, 0x40740CCCC0000000
- %tmp1030 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1030 = load <4 x float>, ptr undef, align 16
%vecins10616 = insertelement <4 x float> %tmp1030, float %add10615, i32 1
- store <4 x float> %vecins10616, <4 x float>* undef, align 16
- %tmp1031 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10616, ptr undef, align 16
+ %tmp1031 = load <4 x float>, ptr undef, align 16
%vecext10617 = extractelement <4 x float> %tmp1031, i32 2
%add10618 = fadd float %vecext10617, 0xC012CCCCC0000000
- %tmp1032 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1032 = load <4 x float>, ptr undef, align 16
%vecins10619 = insertelement <4 x float> %tmp1032, float %add10618, i32 2
- store <4 x float> %vecins10619, <4 x float>* undef, align 16
- %tmp1033 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10619, ptr undef, align 16
+ %tmp1033 = load <4 x float>, ptr undef, align 16
%vecext10620 = extractelement <4 x float> %tmp1033, i32 3
%add10621 = fadd float %vecext10620, 0x406E566660000000
- %tmp1034 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> <float 0x407B2199A0000000, float 0xC07D9CCCC0000000, float -4.350000e+01, float 0xC07D3B3340000000>, <4 x float>* %.compoundliteral10623
- %tmp1035 = load <4 x float>, <4 x float>* %.compoundliteral10623
+ %tmp1034 = load <4 x float>, ptr undef, align 16
+ store <4 x float> <float 0x407B2199A0000000, float 0xC07D9CCCC0000000, float -4.350000e+01, float 0xC07D3B3340000000>, ptr %.compoundliteral10623
+ %tmp1035 = load <4 x float>, ptr %.compoundliteral10623
%add10624 = fadd <4 x float> undef, %tmp1035
- %tmp1036 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1036 = load <4 x float>, ptr undef, align 16
%vecext10625 = extractelement <4 x float> %tmp1036, i32 0
- %tmp1037 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1037 = load <4 x float>, ptr undef, align 16
%vecins10627 = insertelement <4 x float> %tmp1037, float undef, i32 0
- store <4 x float> %vecins10627, <4 x float>* undef, align 16
- %tmp1038 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10627, ptr undef, align 16
+ %tmp1038 = load <4 x float>, ptr undef, align 16
%vecext10628 = extractelement <4 x float> %tmp1038, i32 1
%add10629 = fadd float %vecext10628, 0x407E3CCCC0000000
- %tmp1039 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1039 = load <4 x float>, ptr undef, align 16
%vecins10630 = insertelement <4 x float> %tmp1039, float %add10629, i32 1
- store <4 x float> %vecins10630, <4 x float>* undef, align 16
- %tmp1040 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10630, ptr undef, align 16
+ %tmp1040 = load <4 x float>, ptr undef, align 16
%vecext10631 = extractelement <4 x float> %tmp1040, i32 2
- %tmp1041 = load <4 x float>, <4 x float>* undef, align 16
- %tmp1042 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1041 = load <4 x float>, ptr undef, align 16
+ %tmp1042 = load <4 x float>, ptr undef, align 16
%vecext10634 = extractelement <4 x float> %tmp1042, i32 3
%add10635 = fadd float %vecext10634, 0xC067533340000000
- %tmp1043 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1043 = load <4 x float>, ptr undef, align 16
%vecins10636 = insertelement <4 x float> %tmp1043, float %add10635, i32 3
- store <4 x float> %vecins10636, <4 x float>* undef, align 16
- store <4 x float> <float 1.950000e+02, float 0x407E8E6660000000, float 0x407D7CCCC0000000, float 0x407E166660000000>, <4 x float>* %.compoundliteral10637
- %tmp1044 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10636, ptr undef, align 16
+ store <4 x float> <float 1.950000e+02, float 0x407E8E6660000000, float 0x407D7CCCC0000000, float 0x407E166660000000>, ptr %.compoundliteral10637
+ %tmp1044 = load <4 x float>, ptr undef, align 16
%add10638 = fadd <4 x float> %tmp1044, undef
- %tmp1045 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1045 = load <4 x float>, ptr undef, align 16
%vecext10639 = extractelement <4 x float> %tmp1045, i32 0
%add10640 = fadd float %vecext10639, 0x406CA33340000000
- %tmp1046 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1046 = load <4 x float>, ptr undef, align 16
%vecins10641 = insertelement <4 x float> %tmp1046, float %add10640, i32 0
- store <4 x float> %vecins10641, <4 x float>* undef, align 16
- %tmp1047 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10641, ptr undef, align 16
+ %tmp1047 = load <4 x float>, ptr undef, align 16
%vecext10642 = extractelement <4 x float> %tmp1047, i32 1
%add10643 = fadd float %vecext10642, 0xC07C8999A0000000
- %tmp1048 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1048 = load <4 x float>, ptr undef, align 16
%vecins10644 = insertelement <4 x float> %tmp1048, float %add10643, i32 1
- store <4 x float> %vecins10644, <4 x float>* undef, align 16
- %tmp1049 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10644, ptr undef, align 16
+ %tmp1049 = load <4 x float>, ptr undef, align 16
%vecext10645 = extractelement <4 x float> %tmp1049, i32 2
- %tmp1050 = load <4 x float>, <4 x float>* undef, align 16
- %tmp1051 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1050 = load <4 x float>, ptr undef, align 16
+ %tmp1051 = load <4 x float>, ptr undef, align 16
%vecins10748 = insertelement <4 x float> undef, float undef, i32 3
- %tmp1052 = load <4 x float>, <4 x float>* %.compoundliteral10749
+ %tmp1052 = load <4 x float>, ptr %.compoundliteral10749
%add10750 = fadd <4 x float> undef, %tmp1052
- store <4 x float> %add10750, <4 x float>* undef, align 16
- %tmp1053 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %add10750, ptr undef, align 16
+ %tmp1053 = load <4 x float>, ptr undef, align 16
%vecext10751 = extractelement <4 x float> %tmp1053, i32 0
%add10752 = fadd float %vecext10751, 0x4071B33340000000
- %tmp1054 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1054 = load <4 x float>, ptr undef, align 16
%vecins10753 = insertelement <4 x float> %tmp1054, float %add10752, i32 0
- store <4 x float> %vecins10753, <4 x float>* undef, align 16
- %tmp1055 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10753, ptr undef, align 16
+ %tmp1055 = load <4 x float>, ptr undef, align 16
%vecext10754 = extractelement <4 x float> %tmp1055, i32 1
%add10755 = fadd float %vecext10754, 0xC076A66660000000
- %tmp1056 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1056 = load <4 x float>, ptr undef, align 16
%vecins10756 = insertelement <4 x float> %tmp1056, float %add10755, i32 1
- store <4 x float> %vecins10756, <4 x float>* undef, align 16
- %tmp1057 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10756, ptr undef, align 16
+ %tmp1057 = load <4 x float>, ptr undef, align 16
%vecext10757 = extractelement <4 x float> %tmp1057, i32 2
%add10758 = fadd float %vecext10757, 3.800000e+01
- %tmp1058 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1058 = load <4 x float>, ptr undef, align 16
%vecins10759 = insertelement <4 x float> %tmp1058, float %add10758, i32 2
- store <4 x float> %vecins10759, <4 x float>* undef, align 16
- %tmp1059 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10759, ptr undef, align 16
+ %tmp1059 = load <4 x float>, ptr undef, align 16
%vecext10760 = extractelement <4 x float> %tmp1059, i32 3
- store <4 x float> undef, <4 x float>* undef, align 16
- store <4 x float> <float 0xC075BB3340000000, float 0x4074D4CCC0000000, float 0xC07A466660000000, float 0xC0691CCCC0000000>, <4 x float>* %.compoundliteral10763
- %tmp1060 = load <4 x float>, <4 x float>* %.compoundliteral10763
- %tmp1061 = load <4 x float>, <4 x float>* undef, align 16
- %tmp1062 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ store <4 x float> <float 0xC075BB3340000000, float 0x4074D4CCC0000000, float 0xC07A466660000000, float 0xC0691CCCC0000000>, ptr %.compoundliteral10763
+ %tmp1060 = load <4 x float>, ptr %.compoundliteral10763
+ %tmp1061 = load <4 x float>, ptr undef, align 16
+ %tmp1062 = load <4 x float>, ptr undef, align 16
%add10985 = fadd float undef, 0x405E933340000000
- %tmp1063 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1063 = load <4 x float>, ptr undef, align 16
%vecins10986 = insertelement <4 x float> %tmp1063, float %add10985, i32 3
- store <4 x float> %vecins10986, <4 x float>* undef, align 16
- store <4 x float> <float 0xC0721E6660000000, float -4.180000e+02, float 0x406F366660000000, float 0xC055F999A0000000>, <4 x float>* %.compoundliteral10987
- %tmp1064 = load <4 x float>, <4 x float>* %.compoundliteral10987
- %tmp1065 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10986, ptr undef, align 16
+ store <4 x float> <float 0xC0721E6660000000, float -4.180000e+02, float 0x406F366660000000, float 0xC055F999A0000000>, ptr %.compoundliteral10987
+ %tmp1064 = load <4 x float>, ptr %.compoundliteral10987
+ %tmp1065 = load <4 x float>, ptr undef, align 16
%vecins10994 = insertelement <4 x float> %tmp1065, float undef, i32 1
- %tmp1066 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1066 = load <4 x float>, ptr undef, align 16
%vecext10995 = extractelement <4 x float> %tmp1066, i32 2
%add10996 = fadd float %vecext10995, 0x406F9999A0000000
- %tmp1067 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1067 = load <4 x float>, ptr undef, align 16
%vecins10997 = insertelement <4 x float> %tmp1067, float %add10996, i32 2
- store <4 x float> %vecins10997, <4 x float>* undef, align 16
- %tmp1068 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins10997, ptr undef, align 16
+ %tmp1068 = load <4 x float>, ptr undef, align 16
%vecext10998 = extractelement <4 x float> %tmp1068, i32 3
%add10999 = fadd float %vecext10998, -2.765000e+02
- %tmp1069 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1069 = load <4 x float>, ptr undef, align 16
%vecins11000 = insertelement <4 x float> %tmp1069, float %add10999, i32 3
- store <4 x float> %vecins11000, <4 x float>* undef, align 16
- store <4 x float> <float 0x4078F999A0000000, float 0xC06D166660000000, float 0x40501999A0000000, float 0x406FC999A0000000>, <4 x float>* %.compoundliteral11001
- %tmp1070 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins11000, ptr undef, align 16
+ store <4 x float> <float 0x4078F999A0000000, float 0xC06D166660000000, float 0x40501999A0000000, float 0x406FC999A0000000>, ptr %.compoundliteral11001
+ %tmp1070 = load <4 x float>, ptr undef, align 16
%add11002 = fadd <4 x float> %tmp1070, undef
%vecext11003 = extractelement <4 x float> undef, i32 0
%vecext11009 = extractelement <4 x float> undef, i32 2
- %tmp1071 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1071 = load <4 x float>, ptr undef, align 16
%vecins11033 = insertelement <4 x float> %tmp1071, float undef, i32 0
- store <4 x float> %vecins11033, <4 x float>* undef, align 16
- %tmp1072 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins11033, ptr undef, align 16
+ %tmp1072 = load <4 x float>, ptr undef, align 16
%vecext11034 = extractelement <4 x float> %tmp1072, i32 1
%add11035 = fadd float %vecext11034, 0x4056D33340000000
- %tmp1073 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1073 = load <4 x float>, ptr undef, align 16
%vecins11036 = insertelement <4 x float> %tmp1073, float %add11035, i32 1
- store <4 x float> %vecins11036, <4 x float>* undef, align 16
- %tmp1074 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins11036, ptr undef, align 16
+ %tmp1074 = load <4 x float>, ptr undef, align 16
%vecext11037 = extractelement <4 x float> %tmp1074, i32 2
%add11038 = fadd float %vecext11037, 0xC06EA33340000000
- %tmp1075 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
- %tmp1076 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1075 = load <4 x float>, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ %tmp1076 = load <4 x float>, ptr undef, align 16
%vecext11040 = extractelement <4 x float> %tmp1076, i32 3
%add11041 = fadd float %vecext11040, 0x40746CCCC0000000
- %tmp1077 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1077 = load <4 x float>, ptr undef, align 16
%vecins11042 = insertelement <4 x float> %tmp1077, float %add11041, i32 3
- store <4 x float> <float 0x405DD999A0000000, float -3.775000e+02, float -1.265000e+02, float 0xC065C66660000000>, <4 x float>* undef
- %tmp1078 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> <float 0x405DD999A0000000, float -3.775000e+02, float -1.265000e+02, float 0xC065C66660000000>, ptr undef
+ %tmp1078 = load <4 x float>, ptr undef, align 16
%add11044 = fadd <4 x float> %tmp1078, undef
- store <4 x float> %add11044, <4 x float>* undef, align 16
- %tmp1079 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %add11044, ptr undef, align 16
+ %tmp1079 = load <4 x float>, ptr undef, align 16
%vecext11045 = extractelement <4 x float> %tmp1079, i32 0
%add11046 = fadd float %vecext11045, 0xC076E66660000000
- %tmp1080 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1080 = load <4 x float>, ptr undef, align 16
%vecins11047 = insertelement <4 x float> %tmp1080, float %add11046, i32 0
- %tmp1081 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1081 = load <4 x float>, ptr undef, align 16
%vecext11048 = extractelement <4 x float> %tmp1081, i32 1
%add11049 = fadd float %vecext11048, 4.100000e+02
%vecins11064 = insertelement <4 x float> undef, float undef, i32 1
%add11074 = fadd float undef, 0xC06FF999A0000000
- %tmp1082 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1082 = load <4 x float>, ptr undef, align 16
%vecins11075 = insertelement <4 x float> %tmp1082, float %add11074, i32 0
- store <4 x float> %vecins11075, <4 x float>* undef, align 16
+ store <4 x float> %vecins11075, ptr undef, align 16
%add11077 = fadd float undef, 0xC075D33340000000
- %tmp1083 = load <4 x float>, <4 x float>* undef, align 16
- %tmp1084 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
- %tmp1085 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1083 = load <4 x float>, ptr undef, align 16
+ %tmp1084 = load <4 x float>, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ %tmp1085 = load <4 x float>, ptr undef, align 16
%vecext11093 = extractelement <4 x float> %tmp1085, i32 2
%add11094 = fadd float %vecext11093, 0xC07CD66660000000
- %tmp1086 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1086 = load <4 x float>, ptr undef, align 16
%vecins11095 = insertelement <4 x float> %tmp1086, float %add11094, i32 2
- store <4 x float> %vecins11095, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
- store <4 x float> <float 0x4061F66660000000, float 0xC076DB3340000000, float 0xC055A66660000000, float 2.415000e+02>, <4 x float>* undef
- %tmp1087 = load <4 x float>, <4 x float>* undef
- store <4 x float> undef, <4 x float>* undef, align 16
- %tmp1088 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins11095, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ store <4 x float> <float 0x4061F66660000000, float 0xC076DB3340000000, float 0xC055A66660000000, float 2.415000e+02>, ptr undef
+ %tmp1087 = load <4 x float>, ptr undef
+ store <4 x float> undef, ptr undef, align 16
+ %tmp1088 = load <4 x float>, ptr undef, align 16
%vecext11513 = extractelement <4 x float> %tmp1088, i32 2
%add11514 = fadd float %vecext11513, 0xC07C7199A0000000
%vecins11515 = insertelement <4 x float> undef, float %add11514, i32 2
- store <4 x float> %vecins11515, <4 x float>* undef, align 16
+ store <4 x float> %vecins11515, ptr undef, align 16
%add11520 = fadd <4 x float> undef, undef
- store <4 x float> %add11520, <4 x float>* undef, align 16
+ store <4 x float> %add11520, ptr undef, align 16
%vecext11521 = extractelement <4 x float> undef, i32 0
%add11522 = fadd float %vecext11521, 0x4041733340000000
- %tmp1089 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
- %tmp1090 = load <4 x float>, <4 x float>* undef
- %tmp1091 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1089 = load <4 x float>, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ %tmp1090 = load <4 x float>, ptr undef
+ %tmp1091 = load <4 x float>, ptr undef, align 16
%add11562 = fadd <4 x float> %tmp1091, %tmp1090
- %tmp1092 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1092 = load <4 x float>, ptr undef, align 16
%add11564 = fadd float undef, 0xC0411999A0000000
- %tmp1093 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1093 = load <4 x float>, ptr undef, align 16
%vecins11565 = insertelement <4 x float> %tmp1093, float %add11564, i32 0
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
%vecext11586 = extractelement <4 x float> undef, i32 3
%add11587 = fadd float %vecext11586, 3.760000e+02
- %tmp1094 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
- store <4 x float> <float 0xC06ED999A0000000, float 1.380000e+02, float 0xC073AB3340000000, float 0x4078A66660000000>, <4 x float>* undef
- %tmp1095 = load <4 x float>, <4 x float>* undef
- %tmp1096 = load <4 x float>, <4 x float>* undef, align 16
- %tmp1097 = load <4 x float>, <4 x float>* undef, align 16
- %tmp1098 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1094 = load <4 x float>, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ store <4 x float> <float 0xC06ED999A0000000, float 1.380000e+02, float 0xC073AB3340000000, float 0x4078A66660000000>, ptr undef
+ %tmp1095 = load <4 x float>, ptr undef
+ %tmp1096 = load <4 x float>, ptr undef, align 16
+ %tmp1097 = load <4 x float>, ptr undef, align 16
+ %tmp1098 = load <4 x float>, ptr undef, align 16
%vecins11593 = insertelement <4 x float> %tmp1098, float undef, i32 0
%vecext11594 = extractelement <4 x float> undef, i32 1
- %tmp1099 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1099 = load <4 x float>, ptr undef, align 16
%vecins11596 = insertelement <4 x float> %tmp1099, float undef, i32 1
- store <4 x float> %vecins11596, <4 x float>* undef, align 16
- %tmp1100 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins11596, ptr undef, align 16
+ %tmp1100 = load <4 x float>, ptr undef, align 16
%vecext11597 = extractelement <4 x float> %tmp1100, i32 2
%add11598 = fadd float %vecext11597, 0x40430CCCC0000000
- %tmp1101 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1101 = load <4 x float>, ptr undef, align 16
%vecins11599 = insertelement <4 x float> %tmp1101, float %add11598, i32 2
- %tmp1102 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1102 = load <4 x float>, ptr undef, align 16
%vecext11600 = extractelement <4 x float> %tmp1102, i32 3
- %tmp1103 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1103 = load <4 x float>, ptr undef, align 16
%vecins11602 = insertelement <4 x float> %tmp1103, float undef, i32 3
- store <4 x float> %vecins11602, <4 x float>* undef, align 16
- %tmp1104 = load <4 x float>, <4 x float>* undef
- %tmp1105 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins11602, ptr undef, align 16
+ %tmp1104 = load <4 x float>, ptr undef
+ %tmp1105 = load <4 x float>, ptr undef, align 16
%add11604 = fadd <4 x float> %tmp1105, %tmp1104
- %tmp1106 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1106 = load <4 x float>, ptr undef, align 16
%vecext11605 = extractelement <4 x float> %tmp1106, i32 0
- %tmp1107 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1107 = load <4 x float>, ptr undef, align 16
%vecins11607 = insertelement <4 x float> %tmp1107, float undef, i32 0
%vecins11621 = insertelement <4 x float> undef, float undef, i32 0
%vecins11630 = insertelement <4 x float> undef, float undef, i32 3
- store <4 x float> %vecins11630, <4 x float>* undef, align 16
- store <4 x float> <float -1.190000e+02, float 0x402F666660000000, float 0xC07BD33340000000, float -1.595000e+02>, <4 x float>* %.compoundliteral11631
- %tmp1108 = load <4 x float>, <4 x float>* %.compoundliteral11631
- %tmp1109 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> %vecins11630, ptr undef, align 16
+ store <4 x float> <float -1.190000e+02, float 0x402F666660000000, float 0xC07BD33340000000, float -1.595000e+02>, ptr %.compoundliteral11631
+ %tmp1108 = load <4 x float>, ptr %.compoundliteral11631
+ %tmp1109 = load <4 x float>, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
%add11634 = fadd float undef, -1.075000e+02
%vecext11647 = extractelement <4 x float> undef, i32 0
%add11648 = fadd float %vecext11647, 0x40775999A0000000
- %tmp1110 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1110 = load <4 x float>, ptr undef, align 16
%vecext11650 = extractelement <4 x float> undef, i32 1
- %tmp1111 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1111 = load <4 x float>, ptr undef, align 16
%vecins11784 = insertelement <4 x float> %tmp1111, float undef, i32 3
- store <4 x float> %vecins11784, <4 x float>* undef, align 16
- store <4 x float> <float 1.605000e+02, float 0x4068366660000000, float 2.820000e+02, float 0x407CF66660000000>, <4 x float>* %.compoundliteral11785
- %tmp1112 = load <4 x float>, <4 x float>* %.compoundliteral11785
+ store <4 x float> %vecins11784, ptr undef, align 16
+ store <4 x float> <float 1.605000e+02, float 0x4068366660000000, float 2.820000e+02, float 0x407CF66660000000>, ptr %.compoundliteral11785
+ %tmp1112 = load <4 x float>, ptr %.compoundliteral11785
%add11786 = fadd <4 x float> undef, %tmp1112
- store <4 x float> %add11786, <4 x float>* undef, align 16
- %tmp1113 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %add11786, ptr undef, align 16
+ %tmp1113 = load <4 x float>, ptr undef, align 16
%vecext11787 = extractelement <4 x float> %tmp1113, i32 0
%vecext11807 = extractelement <4 x float> undef, i32 2
%add11808 = fadd float %vecext11807, 4.535000e+02
- %tmp1114 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1114 = load <4 x float>, ptr undef, align 16
%vecext11810 = extractelement <4 x float> undef, i32 3
%add11811 = fadd float %vecext11810, 0x4068F66660000000
- %tmp1115 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1115 = load <4 x float>, ptr undef, align 16
%vecins11812 = insertelement <4 x float> %tmp1115, float %add11811, i32 3
- store <4 x float> %vecins11812, <4 x float>* undef, align 16
- %tmp1116 = load <4 x float>, <4 x float>* undef
- %tmp1117 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins11812, ptr undef, align 16
+ %tmp1116 = load <4 x float>, ptr undef
+ %tmp1117 = load <4 x float>, ptr undef, align 16
%vecext11958 = extractelement <4 x float> undef, i32 1
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
%vecext11961 = extractelement <4 x float> undef, i32 2
%add11962 = fadd float %vecext11961, -3.680000e+02
- %tmp1118 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
+ %tmp1118 = load <4 x float>, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
%add11965 = fadd float undef, 0x4061133340000000
- store <4 x float> undef, <4 x float>* undef, align 16
- %tmp1119 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ %tmp1119 = load <4 x float>, ptr undef, align 16
%vecext11975 = extractelement <4 x float> %tmp1119, i32 2
- %tmp1120 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1120 = load <4 x float>, ptr undef, align 16
%vecins11977 = insertelement <4 x float> %tmp1120, float undef, i32 2
- store <4 x float> %vecins11977, <4 x float>* undef, align 16
+ store <4 x float> %vecins11977, ptr undef, align 16
%vecext11978 = extractelement <4 x float> undef, i32 3
%add11979 = fadd float %vecext11978, 0xC0688999A0000000
- %tmp1121 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1121 = load <4 x float>, ptr undef, align 16
%vecins11980 = insertelement <4 x float> %tmp1121, float %add11979, i32 3
- store <4 x float> %vecins11980, <4 x float>* undef, align 16
+ store <4 x float> %vecins11980, ptr undef, align 16
%add11982 = fadd <4 x float> undef, undef
- store <4 x float> %add11982, <4 x float>* undef, align 16
- %tmp1122 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %add11982, ptr undef, align 16
+ %tmp1122 = load <4 x float>, ptr undef, align 16
%vecext11983 = extractelement <4 x float> %tmp1122, i32 0
%add11984 = fadd float %vecext11983, 0xC075966660000000
- %tmp1123 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1123 = load <4 x float>, ptr undef, align 16
%vecins12005 = insertelement <4 x float> undef, float undef, i32 2
- store <4 x float> %vecins12005, <4 x float>* undef, align 16
- %tmp1124 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins12005, ptr undef, align 16
+ %tmp1124 = load <4 x float>, ptr undef, align 16
%add12007 = fadd float undef, 0xC07124CCC0000000
%vecins12008 = insertelement <4 x float> undef, float %add12007, i32 3
- store <4 x float> %vecins12008, <4 x float>* undef, align 16
- %tmp1125 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
- %tmp1126 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins12008, ptr undef, align 16
+ %tmp1125 = load <4 x float>, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ %tmp1126 = load <4 x float>, ptr undef, align 16
%add12012 = fadd float undef, 0xC0750CCCC0000000
- %tmp1127 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1127 = load <4 x float>, ptr undef, align 16
%vecins12013 = insertelement <4 x float> %tmp1127, float %add12012, i32 0
- store <4 x float> %vecins12013, <4 x float>* undef, align 16
- %tmp1128 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins12013, ptr undef, align 16
+ %tmp1128 = load <4 x float>, ptr undef, align 16
%add12015 = fadd float undef, 0x4079CE6660000000
- %tmp1129 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1129 = load <4 x float>, ptr undef, align 16
%vecins12016 = insertelement <4 x float> %tmp1129, float %add12015, i32 1
- store <4 x float> %vecins12016, <4 x float>* undef, align 16
+ store <4 x float> %vecins12016, ptr undef, align 16
%add12018 = fadd float undef, 3.555000e+02
- %tmp1130 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1130 = load <4 x float>, ptr undef, align 16
%vecins12019 = insertelement <4 x float> %tmp1130, float %add12018, i32 2
- %tmp1131 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1131 = load <4 x float>, ptr undef, align 16
%vecext12020 = extractelement <4 x float> %tmp1131, i32 3
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
%vecext12028 = extractelement <4 x float> undef, i32 1
- store <4 x float> undef, <4 x float>* undef, align 16
- store <4 x float> <float 0x40791999A0000000, float 0x407C7CCCC0000000, float 0x4070F33340000000, float 0xC056ECCCC0000000>, <4 x float>* undef
- %tmp1132 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ store <4 x float> <float 0x40791999A0000000, float 0x407C7CCCC0000000, float 0x4070F33340000000, float 0xC056ECCCC0000000>, ptr undef
+ %tmp1132 = load <4 x float>, ptr undef, align 16
%add12038 = fadd <4 x float> %tmp1132, undef
- %tmp1133 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1133 = load <4 x float>, ptr undef, align 16
%vecext12042 = extractelement <4 x float> %tmp1133, i32 1
%add12043 = fadd float %vecext12042, 0x402F9999A0000000
- %tmp1134 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1134 = load <4 x float>, ptr undef, align 16
%vecins12044 = insertelement <4 x float> %tmp1134, float %add12043, i32 1
- store <4 x float> %vecins12044, <4 x float>* undef, align 16
+ store <4 x float> %vecins12044, ptr undef, align 16
%vecext12045 = extractelement <4 x float> undef, i32 2
%add12046 = fadd float %vecext12045, 0xC07EF33340000000
- %tmp1135 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1135 = load <4 x float>, ptr undef, align 16
%vecins12047 = insertelement <4 x float> %tmp1135, float %add12046, i32 2
- store <4 x float> %vecins12047, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
- %tmp1136 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins12047, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ %tmp1136 = load <4 x float>, ptr undef, align 16
%vecext12112 = extractelement <4 x float> %tmp1136, i32 1
- %tmp1137 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
+ %tmp1137 = load <4 x float>, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
%add12116 = fadd float undef, 0xC074F4CCC0000000
- %tmp1138 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1138 = load <4 x float>, ptr undef, align 16
%vecins12117 = insertelement <4 x float> %tmp1138, float %add12116, i32 2
- store <4 x float> %vecins12117, <4 x float>* undef, align 16
- %tmp1139 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins12117, ptr undef, align 16
+ %tmp1139 = load <4 x float>, ptr undef, align 16
%vecext12118 = extractelement <4 x float> %tmp1139, i32 3
%add12119 = fadd float %vecext12118, 0xC0638CCCC0000000
- %tmp1140 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1140 = load <4 x float>, ptr undef, align 16
%vecins12120 = insertelement <4 x float> %tmp1140, float %add12119, i32 3
%add12152 = fadd float undef, 0x4039333340000000
- %tmp1141 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1141 = load <4 x float>, ptr undef, align 16
%vecins12153 = insertelement <4 x float> %tmp1141, float %add12152, i32 0
%vecext12154 = extractelement <4 x float> undef, i32 1
%add12155 = fadd float %vecext12154, 0xC07BBB3340000000
- %tmp1142 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1142 = load <4 x float>, ptr undef, align 16
%vecins12156 = insertelement <4 x float> %tmp1142, float %add12155, i32 1
- %tmp1143 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1143 = load <4 x float>, ptr undef, align 16
%vecext12157 = extractelement <4 x float> %tmp1143, i32 2
%add12158 = fadd float %vecext12157, 0xC0428CCCC0000000
- %tmp1144 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1144 = load <4 x float>, ptr undef, align 16
%vecins12159 = insertelement <4 x float> %tmp1144, float %add12158, i32 2
- %tmp1145 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1145 = load <4 x float>, ptr undef, align 16
%vecext12160 = extractelement <4 x float> %tmp1145, i32 3
%add12161 = fadd float %vecext12160, 0x407B1999A0000000
- %tmp1146 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1146 = load <4 x float>, ptr undef, align 16
%vecins12162 = insertelement <4 x float> %tmp1146, float %add12161, i32 3
- store <4 x float> %vecins12162, <4 x float>* undef, align 16
- %tmp1147 = load <4 x float>, <4 x float>* undef
- %tmp1148 = load <4 x float>, <4 x float>* undef, align 16
- %tmp1149 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins12162, ptr undef, align 16
+ %tmp1147 = load <4 x float>, ptr undef
+ %tmp1148 = load <4 x float>, ptr undef, align 16
+ %tmp1149 = load <4 x float>, ptr undef, align 16
%vecext12182 = extractelement <4 x float> %tmp1149, i32 1
- %tmp1150 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
- store <4 x float> <float 0x4061833340000000, float 0x405CA66660000000, float -1.275000e+02, float 0x405BC66660000000>, <4 x float>* undef
+ %tmp1150 = load <4 x float>, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ store <4 x float> <float 0x4061833340000000, float 0x405CA66660000000, float -1.275000e+02, float 0x405BC66660000000>, ptr undef
%add12208 = fadd float undef, 0x407854CCC0000000
- %tmp1151 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
- %tmp1152 = load <4 x float>, <4 x float>* undef, align 16
- %tmp1153 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1151 = load <4 x float>, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ %tmp1152 = load <4 x float>, ptr undef, align 16
+ %tmp1153 = load <4 x float>, ptr undef, align 16
%vecins12218 = insertelement <4 x float> undef, float undef, i32 3
- store <4 x float> %vecins12218, <4 x float>* undef, align 16
- store <4 x float> <float 0x407C3CCCC0000000, float 0xC057C66660000000, float 2.605000e+02, float 0xC07974CCC0000000>, <4 x float>* undef
- %tmp1154 = load <4 x float>, <4 x float>* undef
- %tmp1155 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins12218, ptr undef, align 16
+ store <4 x float> <float 0x407C3CCCC0000000, float 0xC057C66660000000, float 2.605000e+02, float 0xC07974CCC0000000>, ptr undef
+ %tmp1154 = load <4 x float>, ptr undef
+ %tmp1155 = load <4 x float>, ptr undef, align 16
%add12220 = fadd <4 x float> %tmp1155, %tmp1154
- %tmp1156 = load <4 x float>, <4 x float>* undef, align 16
- %tmp1157 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1156 = load <4 x float>, ptr undef, align 16
+ %tmp1157 = load <4 x float>, ptr undef, align 16
%vecins12223 = insertelement <4 x float> %tmp1157, float undef, i32 0
- store <4 x float> %vecins12223, <4 x float>* undef, align 16
- %tmp1158 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins12223, ptr undef, align 16
+ %tmp1158 = load <4 x float>, ptr undef, align 16
%add12242 = fadd float undef, 0x4067E33340000000
- %tmp1159 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1159 = load <4 x float>, ptr undef, align 16
%vecins12243 = insertelement <4 x float> %tmp1159, float %add12242, i32 2
- store <4 x float> %vecins12243, <4 x float>* undef, align 16
- %tmp1160 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins12243, ptr undef, align 16
+ %tmp1160 = load <4 x float>, ptr undef, align 16
%vecext12244 = extractelement <4 x float> %tmp1160, i32 3
%add12245 = fadd float %vecext12244, 0x4071AE6660000000
- %tmp1161 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1161 = load <4 x float>, ptr undef, align 16
%vecins12246 = insertelement <4 x float> %tmp1161, float %add12245, i32 3
- store <4 x float> %vecins12246, <4 x float>* undef, align 16
- store <4 x float> <float -4.880000e+02, float 0xC079966660000000, float -8.450000e+01, float 0xC0464CCCC0000000>, <4 x float>* %.compoundliteral12247
- %tmp1162 = load <4 x float>, <4 x float>* %.compoundliteral12247
- %tmp1163 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins12246, ptr undef, align 16
+ store <4 x float> <float -4.880000e+02, float 0xC079966660000000, float -8.450000e+01, float 0xC0464CCCC0000000>, ptr %.compoundliteral12247
+ %tmp1162 = load <4 x float>, ptr %.compoundliteral12247
+ %tmp1163 = load <4 x float>, ptr undef, align 16
%add12248 = fadd <4 x float> %tmp1163, %tmp1162
- store <4 x float> %add12248, <4 x float>* undef, align 16
- %tmp1164 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %add12248, ptr undef, align 16
+ %tmp1164 = load <4 x float>, ptr undef, align 16
%vecext12249 = extractelement <4 x float> %tmp1164, i32 0
%add12250 = fadd float %vecext12249, 1.075000e+02
- %tmp1165 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
- %tmp1166 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1165 = load <4 x float>, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ %tmp1166 = load <4 x float>, ptr undef, align 16
%vecext12252 = extractelement <4 x float> %tmp1166, i32 1
%add12253 = fadd float %vecext12252, 0xC0662CCCC0000000
- %tmp1167 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1167 = load <4 x float>, ptr undef, align 16
%vecins12254 = insertelement <4 x float> %tmp1167, float %add12253, i32 1
- store <4 x float> %vecins12254, <4 x float>* undef, align 16
- %tmp1168 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins12254, ptr undef, align 16
+ %tmp1168 = load <4 x float>, ptr undef, align 16
%vecext12255 = extractelement <4 x float> %tmp1168, i32 2
%add12256 = fadd float %vecext12255, 0x40554CCCC0000000
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
%add13141 = fadd float undef, 0x40768999A0000000
- %tmp1169 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1169 = load <4 x float>, ptr undef, align 16
%vecins13142 = insertelement <4 x float> %tmp1169, float %add13141, i32 3
- store <4 x float> %vecins13142, <4 x float>* undef, align 16
- %tmp1170 = load <4 x float>, <4 x float>* undef
+ store <4 x float> %vecins13142, ptr undef, align 16
+ %tmp1170 = load <4 x float>, ptr undef
%add13144 = fadd <4 x float> undef, %tmp1170
- store <4 x float> %add13144, <4 x float>* undef, align 16
- %tmp1171 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %add13144, ptr undef, align 16
+ %tmp1171 = load <4 x float>, ptr undef, align 16
%vecext13145 = extractelement <4 x float> %tmp1171, i32 0
%add13146 = fadd float %vecext13145, 3.975000e+02
- %tmp1172 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1172 = load <4 x float>, ptr undef, align 16
%vecext13378 = extractelement <4 x float> %tmp1172, i32 3
%add13379 = fadd float %vecext13378, 0xC053B33340000000
- %tmp1173 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1173 = load <4 x float>, ptr undef, align 16
%vecins13380 = insertelement <4 x float> %tmp1173, float %add13379, i32 3
- store <4 x float> %vecins13380, <4 x float>* undef, align 16
- %tmp1174 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13380, ptr undef, align 16
+ %tmp1174 = load <4 x float>, ptr undef, align 16
%vecins13408 = insertelement <4 x float> %tmp1174, float undef, i32 3
- store <4 x float> %vecins13408, <4 x float>* undef, align 16
- store <4 x float> <float 0xC0455999A0000000, float 0xC07D366660000000, float 4.240000e+02, float -1.670000e+02>, <4 x float>* undef
- %tmp1175 = load <4 x float>, <4 x float>* undef
- %tmp1176 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13408, ptr undef, align 16
+ store <4 x float> <float 0xC0455999A0000000, float 0xC07D366660000000, float 4.240000e+02, float -1.670000e+02>, ptr undef
+ %tmp1175 = load <4 x float>, ptr undef
+ %tmp1176 = load <4 x float>, ptr undef, align 16
%add13410 = fadd <4 x float> %tmp1176, %tmp1175
- store <4 x float> %add13410, <4 x float>* undef, align 16
- %tmp1177 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %add13410, ptr undef, align 16
+ %tmp1177 = load <4 x float>, ptr undef, align 16
%add13412 = fadd float undef, 0xC0708999A0000000
- %tmp1178 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1178 = load <4 x float>, ptr undef, align 16
%vecins13413 = insertelement <4 x float> %tmp1178, float %add13412, i32 0
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
%vecext13428 = extractelement <4 x float> undef, i32 1
%add13429 = fadd float %vecext13428, 0xC063BCCCC0000000
- %tmp1179 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1179 = load <4 x float>, ptr undef, align 16
%vecins13430 = insertelement <4 x float> %tmp1179, float %add13429, i32 1
- store <4 x float> %vecins13430, <4 x float>* undef, align 16
- %tmp1180 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13430, ptr undef, align 16
+ %tmp1180 = load <4 x float>, ptr undef, align 16
%vecext13431 = extractelement <4 x float> %tmp1180, i32 2
%vecins13433 = insertelement <4 x float> undef, float undef, i32 2
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
%add13449 = fadd float undef, 4.590000e+02
- %tmp1181 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1181 = load <4 x float>, ptr undef, align 16
%vecins13450 = insertelement <4 x float> %tmp1181, float %add13449, i32 3
- store <4 x float> %vecins13450, <4 x float>* undef, align 16
- store <4 x float> <float 0xC073A66660000000, float 0xC041B33340000000, float 0x4066233340000000, float 0x4071C33340000000>, <4 x float>* undef
- %tmp1182 = load <4 x float>, <4 x float>* undef
- %tmp1183 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13450, ptr undef, align 16
+ store <4 x float> <float 0xC073A66660000000, float 0xC041B33340000000, float 0x4066233340000000, float 0x4071C33340000000>, ptr undef
+ %tmp1182 = load <4 x float>, ptr undef
+ %tmp1183 = load <4 x float>, ptr undef, align 16
%add13452 = fadd <4 x float> %tmp1183, %tmp1182
- store <4 x float> %add13452, <4 x float>* undef, align 16
- %tmp1184 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %add13452, ptr undef, align 16
+ %tmp1184 = load <4 x float>, ptr undef, align 16
%vecext13453 = extractelement <4 x float> %tmp1184, i32 0
%add13454 = fadd float %vecext13453, 0xC072866660000000
- %tmp1185 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1185 = load <4 x float>, ptr undef, align 16
%vecins13455 = insertelement <4 x float> %tmp1185, float %add13454, i32 0
%add13471 = fadd float undef, 0xC0556CCCC0000000
- %tmp1186 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1186 = load <4 x float>, ptr undef, align 16
%vecins13472 = insertelement <4 x float> %tmp1186, float %add13471, i32 1
- store <4 x float> %vecins13472, <4 x float>* undef, align 16
- %tmp1187 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13472, ptr undef, align 16
+ %tmp1187 = load <4 x float>, ptr undef, align 16
%vecext13473 = extractelement <4 x float> %tmp1187, i32 2
%add13474 = fadd float %vecext13473, 0xC0786999A0000000
- %tmp1188 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1188 = load <4 x float>, ptr undef, align 16
%vecins13475 = insertelement <4 x float> %tmp1188, float %add13474, i32 2
- store <4 x float> %vecins13475, <4 x float>* undef, align 16
+ store <4 x float> %vecins13475, ptr undef, align 16
%add13477 = fadd float undef, 0xC07C3E6660000000
- %tmp1189 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1189 = load <4 x float>, ptr undef, align 16
%vecins13478 = insertelement <4 x float> %tmp1189, float %add13477, i32 3
- store <4 x float> %vecins13478, <4 x float>* undef, align 16
- store <4 x float> <float -4.740000e+02, float 0x4023CCCCC0000000, float 0xC05C266660000000, float 0x407B7199A0000000>, <4 x float>* undef
- %tmp1190 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13478, ptr undef, align 16
+ store <4 x float> <float -4.740000e+02, float 0x4023CCCCC0000000, float 0xC05C266660000000, float 0x407B7199A0000000>, ptr undef
+ %tmp1190 = load <4 x float>, ptr undef, align 16
%add13480 = fadd <4 x float> %tmp1190, undef
- store <4 x float> %add13480, <4 x float>* undef, align 16
- %tmp1191 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %add13480, ptr undef, align 16
+ %tmp1191 = load <4 x float>, ptr undef, align 16
%vecext13481 = extractelement <4 x float> %tmp1191, i32 0
%add13482 = fadd float %vecext13481, 0xC07BA4CCC0000000
- %tmp1192 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1192 = load <4 x float>, ptr undef, align 16
%vecins13483 = insertelement <4 x float> %tmp1192, float %add13482, i32 0
- store <4 x float> %vecins13483, <4 x float>* undef, align 16
- %tmp1193 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13483, ptr undef, align 16
+ %tmp1193 = load <4 x float>, ptr undef, align 16
%add13485 = fadd float undef, 0x406B1999A0000000
- %tmp1194 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1194 = load <4 x float>, ptr undef, align 16
%vecins13486 = insertelement <4 x float> %tmp1194, float %add13485, i32 1
- store <4 x float> %vecins13486, <4 x float>* undef, align 16
- %tmp1195 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13486, ptr undef, align 16
+ %tmp1195 = load <4 x float>, ptr undef, align 16
%vecext13487 = extractelement <4 x float> %tmp1195, i32 2
%add13488 = fadd float %vecext13487, 0x40647999A0000000
- %tmp1196 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1196 = load <4 x float>, ptr undef, align 16
%vecins13489 = insertelement <4 x float> %tmp1196, float %add13488, i32 2
- store <4 x float> %vecins13489, <4 x float>* undef, align 16
- %tmp1197 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13489, ptr undef, align 16
+ %tmp1197 = load <4 x float>, ptr undef, align 16
%vecext13490 = extractelement <4 x float> %tmp1197, i32 3
- %tmp1198 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1198 = load <4 x float>, ptr undef, align 16
%vecins13492 = insertelement <4 x float> %tmp1198, float undef, i32 3
- store <4 x float> %vecins13492, <4 x float>* undef, align 16
- %tmp1199 = load <4 x float>, <4 x float>* %.compoundliteral13493
- %tmp1200 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
+ store <4 x float> %vecins13492, ptr undef, align 16
+ %tmp1199 = load <4 x float>, ptr %.compoundliteral13493
+ %tmp1200 = load <4 x float>, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
%vecins13548 = insertelement <4 x float> undef, float undef, i32 3
- store <4 x float> <float 4.540000e+02, float 3.760000e+02, float 0x406EA33340000000, float 0x405AACCCC0000000>, <4 x float>* %.compoundliteral13549
- %tmp1201 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> <float 4.540000e+02, float 3.760000e+02, float 0x406EA33340000000, float 0x405AACCCC0000000>, ptr %.compoundliteral13549
+ %tmp1201 = load <4 x float>, ptr undef, align 16
%add13552 = fadd float undef, 3.230000e+02
- %tmp1202 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1202 = load <4 x float>, ptr undef, align 16
%vecins13553 = insertelement <4 x float> %tmp1202, float %add13552, i32 0
- %tmp1203 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1203 = load <4 x float>, ptr undef, align 16
%vecext13554 = extractelement <4 x float> %tmp1203, i32 1
- %tmp1204 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1204 = load <4 x float>, ptr undef, align 16
%vecins13556 = insertelement <4 x float> %tmp1204, float undef, i32 1
- store <4 x float> %vecins13556, <4 x float>* undef, align 16
- %tmp1205 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13556, ptr undef, align 16
+ %tmp1205 = load <4 x float>, ptr undef, align 16
%add13558 = fadd float undef, 2.625000e+02
- %tmp1206 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1206 = load <4 x float>, ptr undef, align 16
%vecins13559 = insertelement <4 x float> %tmp1206, float %add13558, i32 2
- store <4 x float> %vecins13559, <4 x float>* undef, align 16
+ store <4 x float> %vecins13559, ptr undef, align 16
%add13575 = fadd float undef, -4.725000e+02
- %tmp1207 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1207 = load <4 x float>, ptr undef, align 16
%vecins13576 = insertelement <4 x float> %tmp1207, float %add13575, i32 3
- store <4 x float> %vecins13576, <4 x float>* undef, align 16
- store <4 x float> <float 0x40334CCCC0000000, float 0xC0785CCCC0000000, float 0xC078D66660000000, float 3.745000e+02>, <4 x float>* undef
- %tmp1208 = load <4 x float>, <4 x float>* undef
- %tmp1209 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13576, ptr undef, align 16
+ store <4 x float> <float 0x40334CCCC0000000, float 0xC0785CCCC0000000, float 0xC078D66660000000, float 3.745000e+02>, ptr undef
+ %tmp1208 = load <4 x float>, ptr undef
+ %tmp1209 = load <4 x float>, ptr undef, align 16
%add13578 = fadd <4 x float> %tmp1209, %tmp1208
- store <4 x float> %add13578, <4 x float>* undef, align 16
- %tmp1210 = load <4 x float>, <4 x float>* undef, align 16
- %tmp1211 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %add13578, ptr undef, align 16
+ %tmp1210 = load <4 x float>, ptr undef, align 16
+ %tmp1211 = load <4 x float>, ptr undef, align 16
%add13592 = fadd <4 x float> %tmp1211, undef
- store <4 x float> %add13592, <4 x float>* undef, align 16
- %tmp1212 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %add13592, ptr undef, align 16
+ %tmp1212 = load <4 x float>, ptr undef, align 16
%vecext13593 = extractelement <4 x float> %tmp1212, i32 0
%add13594 = fadd float %vecext13593, 0xC0708B3340000000
- %tmp1213 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
- %tmp1214 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1213 = load <4 x float>, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ %tmp1214 = load <4 x float>, ptr undef, align 16
%vecext13596 = extractelement <4 x float> %tmp1214, i32 1
%add13597 = fadd float %vecext13596, 0x40660999A0000000
%vecins13604 = insertelement <4 x float> undef, float undef, i32 3
- store <4 x float> %vecins13604, <4 x float>* undef, align 16
- store <4 x float> <float 0x407B4999A0000000, float 0xC067F66660000000, float 0xC068F999A0000000, float 0xC079233340000000>, <4 x float>* undef
- %tmp1215 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13604, ptr undef, align 16
+ store <4 x float> <float 0x407B4999A0000000, float 0xC067F66660000000, float 0xC068F999A0000000, float 0xC079233340000000>, ptr undef
+ %tmp1215 = load <4 x float>, ptr undef, align 16
%add13606 = fadd <4 x float> %tmp1215, undef
- %tmp1216 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1216 = load <4 x float>, ptr undef, align 16
%vecext13607 = extractelement <4 x float> %tmp1216, i32 0
%vecins13609 = insertelement <4 x float> undef, float undef, i32 0
- %tmp1217 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
- %tmp1218 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1217 = load <4 x float>, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ %tmp1218 = load <4 x float>, ptr undef, align 16
%add13622 = fadd float undef, -3.390000e+02
%vecins13623 = insertelement <4 x float> undef, float %add13622, i32 0
- store <4 x float> %vecins13623, <4 x float>* undef, align 16
- %tmp1219 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13623, ptr undef, align 16
+ %tmp1219 = load <4 x float>, ptr undef, align 16
%vecext13624 = extractelement <4 x float> %tmp1219, i32 1
%add13625 = fadd float %vecext13624, 0x405C3999A0000000
%vecext13627 = extractelement <4 x float> undef, i32 2
%add13628 = fadd float %vecext13627, 0xC067033340000000
- %tmp1220 = load <4 x float>, <4 x float>* undef, align 16
- %tmp1221 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1220 = load <4 x float>, ptr undef, align 16
+ %tmp1221 = load <4 x float>, ptr undef, align 16
%vecext13630 = extractelement <4 x float> %tmp1221, i32 3
%add13631 = fadd float %vecext13630, 0xC060333340000000
- %tmp1222 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1222 = load <4 x float>, ptr undef, align 16
%vecins13632 = insertelement <4 x float> %tmp1222, float %add13631, i32 3
- store <4 x float> %vecins13632, <4 x float>* undef, align 16
- store <4 x float> <float 0x4078D66660000000, float 0x4048B33340000000, float 0x4051466660000000, float -2.965000e+02>, <4 x float>* undef
- %tmp1223 = load <4 x float>, <4 x float>* undef
- %tmp1224 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13632, ptr undef, align 16
+ store <4 x float> <float 0x4078D66660000000, float 0x4048B33340000000, float 0x4051466660000000, float -2.965000e+02>, ptr undef
+ %tmp1223 = load <4 x float>, ptr undef
+ %tmp1224 = load <4 x float>, ptr undef, align 16
%add13634 = fadd <4 x float> %tmp1224, %tmp1223
- store <4 x float> %add13634, <4 x float>* undef, align 16
+ store <4 x float> %add13634, ptr undef, align 16
%vecext13635 = extractelement <4 x float> undef, i32 0
%add13636 = fadd float %vecext13635, 0x406A5999A0000000
- %tmp1225 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1225 = load <4 x float>, ptr undef, align 16
%vecins13637 = insertelement <4 x float> %tmp1225, float %add13636, i32 0
- store <4 x float> %vecins13637, <4 x float>* undef, align 16
- %tmp1226 = load <4 x float>, <4 x float>* undef, align 16
- %tmp1227 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13637, ptr undef, align 16
+ %tmp1226 = load <4 x float>, ptr undef, align 16
+ %tmp1227 = load <4 x float>, ptr undef, align 16
%vecins13643 = insertelement <4 x float> %tmp1227, float undef, i32 2
- store <4 x float> undef, <4 x float>* undef, align 16
- %tmp1228 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ %tmp1228 = load <4 x float>, ptr undef, align 16
%add13785 = fadd float undef, 0x4068866660000000
- %tmp1229 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1229 = load <4 x float>, ptr undef, align 16
%vecins13786 = insertelement <4 x float> %tmp1229, float %add13785, i32 3
- store <4 x float> %vecins13786, <4 x float>* undef, align 16
- store <4 x float> <float 0x407704CCC0000000, float 0x4047B33340000000, float 0x40797B3340000000, float 0xC0652CCCC0000000>, <4 x float>* %.compoundliteral13787
- %tmp1230 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13786, ptr undef, align 16
+ store <4 x float> <float 0x407704CCC0000000, float 0x4047B33340000000, float 0x40797B3340000000, float 0xC0652CCCC0000000>, ptr %.compoundliteral13787
+ %tmp1230 = load <4 x float>, ptr undef, align 16
%add13788 = fadd <4 x float> %tmp1230, undef
- %tmp1231 = load <4 x float>, <4 x float>* undef
- %tmp1232 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1231 = load <4 x float>, ptr undef
+ %tmp1232 = load <4 x float>, ptr undef, align 16
%add13802 = fadd <4 x float> %tmp1232, %tmp1231
- store <4 x float> %add13802, <4 x float>* undef, align 16
- %tmp1233 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %add13802, ptr undef, align 16
+ %tmp1233 = load <4 x float>, ptr undef, align 16
%vecext13803 = extractelement <4 x float> %tmp1233, i32 0
%add13804 = fadd float %vecext13803, -2.900000e+01
- %tmp1234 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1234 = load <4 x float>, ptr undef, align 16
%vecins13805 = insertelement <4 x float> %tmp1234, float %add13804, i32 0
- store <4 x float> %vecins13805, <4 x float>* undef, align 16
- %tmp1235 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13805, ptr undef, align 16
+ %tmp1235 = load <4 x float>, ptr undef, align 16
%add13807 = fadd float undef, 6.400000e+01
- %tmp1236 = load <4 x float>, <4 x float>* undef, align 16
- %tmp1237 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1236 = load <4 x float>, ptr undef, align 16
+ %tmp1237 = load <4 x float>, ptr undef, align 16
%vecext13809 = extractelement <4 x float> %tmp1237, i32 2
- %tmp1238 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1238 = load <4 x float>, ptr undef, align 16
%vecext13812 = extractelement <4 x float> %tmp1238, i32 3
%add13813 = fadd float %vecext13812, -3.615000e+02
%vecins13814 = insertelement <4 x float> undef, float %add13813, i32 3
- store <4 x float> %vecins13814, <4 x float>* undef, align 16
- store <4 x float> <float -2.270000e+02, float -1.500000e+01, float 0x407084CCC0000000, float -1.425000e+02>, <4 x float>* undef
- %tmp1239 = load <4 x float>, <4 x float>* undef
- store <4 x float> undef, <4 x float>* undef, align 16
- %tmp1240 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13814, ptr undef, align 16
+ store <4 x float> <float -2.270000e+02, float -1.500000e+01, float 0x407084CCC0000000, float -1.425000e+02>, ptr undef
+ %tmp1239 = load <4 x float>, ptr undef
+ store <4 x float> undef, ptr undef, align 16
+ %tmp1240 = load <4 x float>, ptr undef, align 16
%vecext13817 = extractelement <4 x float> %tmp1240, i32 0
%vecins13856 = insertelement <4 x float> undef, float undef, i32 3
- store <4 x float> %vecins13856, <4 x float>* undef, align 16
- store <4 x float> <float 0x40656CCCC0000000, float 0xC0656999A0000000, float 0x40778E6660000000, float 0x407ECE6660000000>, <4 x float>* undef
- %tmp1241 = load <4 x float>, <4 x float>* undef
- %tmp1242 = load <4 x float>, <4 x float>* undef, align 16
- store <4 x float> undef, <4 x float>* undef, align 16
- %tmp1243 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13856, ptr undef, align 16
+ store <4 x float> <float 0x40656CCCC0000000, float 0xC0656999A0000000, float 0x40778E6660000000, float 0x407ECE6660000000>, ptr undef
+ %tmp1241 = load <4 x float>, ptr undef
+ %tmp1242 = load <4 x float>, ptr undef, align 16
+ store <4 x float> undef, ptr undef, align 16
+ %tmp1243 = load <4 x float>, ptr undef, align 16
%vecext13859 = extractelement <4 x float> %tmp1243, i32 0
- %tmp1244 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1244 = load <4 x float>, ptr undef, align 16
%vecins13861 = insertelement <4 x float> %tmp1244, float undef, i32 0
- %tmp1245 = load <4 x float>, <4 x float>* undef, align 16
+ %tmp1245 = load <4 x float>, ptr undef, align 16
%vecext13862 = extractelement <4 x float> %tmp1245, i32 1
%add13863 = fadd float %vecext13862, -1.380000e+02
%vecins13864 = insertelement <4 x float> undef, float %add13863, i32 1
%vecins13867 = insertelement <4 x float> undef, float undef, i32 2
- store <4 x float> %vecins13867, <4 x float>* undef, align 16
- %tmp1246 = load <4 x float>, <4 x float>* undef, align 16
- %tmp1247 = load <4 x float>, <4 x float>* undef, align 16
+ store <4 x float> %vecins13867, ptr undef, align 16
+ %tmp1246 = load <4 x float>, ptr undef, align 16
+ %tmp1247 = load <4 x float>, ptr undef, align 16
ret <4 x float> undef
}
-declare i32 @printf(i8*, ...)
+declare i32 @printf(ptr, ...)
diff --git a/llvm/test/CodeGen/ARM/thumb-litpool.ll b/llvm/test/CodeGen/ARM/thumb-litpool.ll
index bd8829c22bceb..f2a644b68f6e0 100644
--- a/llvm/test/CodeGen/ARM/thumb-litpool.ll
+++ b/llvm/test/CodeGen/ARM/thumb-litpool.ll
@@ -3,13 +3,13 @@
@var = global i8 zeroinitializer
-declare void @callee(i8*)
+declare void @callee(ptr)
define void @foo() minsize {
; CHECK-LABEL: foo:
; CHECK: ldr {{r[0-7]}}, LCPI0_0
- call void @callee(i8* @var)
+ call void @callee(ptr @var)
call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7}"()
- call void @callee(i8* @var)
+ call void @callee(ptr @var)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/thumb1-ldst-opt.ll b/llvm/test/CodeGen/ARM/thumb1-ldst-opt.ll
index d61b1d8b52e32..41b0c10449f65 100644
--- a/llvm/test/CodeGen/ARM/thumb1-ldst-opt.ll
+++ b/llvm/test/CodeGen/ARM/thumb1-ldst-opt.ll
@@ -2,21 +2,21 @@
target triple = "thumbv6m-none-none"
-define i32* @foo(i32* readonly %p0) {
+define ptr @foo(ptr readonly %p0) {
entry:
- %add.ptr = getelementptr inbounds i32, i32* %p0, i32 10
- %arrayidx = getelementptr inbounds i32, i32* %p0, i32 13
- %0 = load i32, i32* %arrayidx, align 4
- %arrayidx1 = getelementptr inbounds i32, i32* %p0, i32 12
- %1 = load i32, i32* %arrayidx1, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %p0, i32 10
+ %arrayidx = getelementptr inbounds i32, ptr %p0, i32 13
+ %0 = load i32, ptr %arrayidx, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %p0, i32 12
+ %1 = load i32, ptr %arrayidx1, align 4
%add = add nsw i32 %1, %0
- %arrayidx2 = getelementptr inbounds i32, i32* %p0, i32 11
- %2 = load i32, i32* %arrayidx2, align 4
+ %arrayidx2 = getelementptr inbounds i32, ptr %p0, i32 11
+ %2 = load i32, ptr %arrayidx2, align 4
%add3 = add nsw i32 %add, %2
- %3 = load i32, i32* %add.ptr, align 4
+ %3 = load i32, ptr %add.ptr, align 4
%add5 = add nsw i32 %add3, %3
tail call void @g(i32 %add5)
- ret i32* %p0
+ ret ptr %p0
}
declare void @g(i32)
diff --git a/llvm/test/CodeGen/ARM/thumb1-varalloc.ll b/llvm/test/CodeGen/ARM/thumb1-varalloc.ll
index d16066642a8ad..6c1b5c3614ccc 100644
--- a/llvm/test/CodeGen/ARM/thumb1-varalloc.ll
+++ b/llvm/test/CodeGen/ARM/thumb1-varalloc.ll
@@ -3,58 +3,56 @@
; RUN: llc < %s -o %t -filetype=obj -mtriple=thumbv6-apple-darwin
; RUN: llvm-objdump --no-print-imm-hex --triple=thumbv6-apple-darwin -d %t | FileCheck %s
- at __bar = external hidden global i8*
- at __baz = external hidden global i8*
+ at __bar = external hidden global ptr
+ at __baz = external hidden global ptr
; rdar://8819685
-define i8* @_foo() {
+define ptr @_foo() {
entry:
; CHECK-LABEL: __foo{{>?}}:
%size = alloca i32, align 4
- %0 = load i8*, i8** @__bar, align 4
- %1 = icmp eq i8* %0, null
+ %0 = load ptr, ptr @__bar, align 4
+ %1 = icmp eq ptr %0, null
br i1 %1, label %bb1, label %bb3
; CHECK: bne
bb1:
- store i32 1026, i32* %size, align 4
+ store i32 1026, ptr %size, align 4
%2 = alloca [1026 x i8], align 1
; CHECK: mov [[R0:r[0-9]+]], sp
; CHECK: adds {{r[0-9]+}}, [[R0]], {{r[0-9]+}}
- %3 = getelementptr inbounds [1026 x i8], [1026 x i8]* %2, i32 0, i32 0
- %4 = call i32 @_called_func(i8* %3, i32* %size) nounwind
- %5 = icmp eq i32 %4, 0
- br i1 %5, label %bb2, label %bb3
+ %3 = call i32 @_called_func(ptr %2, ptr %size) nounwind
+ %4 = icmp eq i32 %3, 0
+ br i1 %4, label %bb2, label %bb3
bb2:
- %6 = call i8* @strdup(i8* %3) nounwind
- store i8* %6, i8** @__baz, align 4
+ %5 = call ptr @strdup(ptr %2) nounwind
+ store ptr %5, ptr @__baz, align 4
br label %bb3
bb3:
- %.0 = phi i8* [ %0, %entry ], [ %6, %bb2 ], [ %3, %bb1 ]
+ %.0 = phi ptr [ %0, %entry ], [ %5, %bb2 ], [ %2, %bb1 ]
; CHECK: subs r4, r7, #7
; CHECK-NEXT: subs r4, #1
; CHECK-NEXT: mov sp, r4
; CHECK-NEXT: pop {r4, r6, r7, pc}
- ret i8* %.0
+ ret ptr %.0
}
-declare noalias i8* @strdup(i8* nocapture) nounwind
-declare i32 @_called_func(i8*, i32*) nounwind
+declare noalias ptr @strdup(ptr nocapture) nounwind
+declare i32 @_called_func(ptr, ptr) nounwind
; Simple variable ending up *at* sp.
define void @test_simple_var() {
; CHECK-LABEL: test_simple_var{{>?}}:
%addr32 = alloca i32
- %addr8 = bitcast i32* %addr32 to i8*
; CHECK: mov r0, sp
; CHECK-NOT: adds r0
; CHECK: bl
- call void @take_ptr(i8* %addr8)
+ call void @take_ptr(ptr %addr32)
ret void
}
@@ -63,18 +61,16 @@ define void @test_local_var_addr_aligned() {
; CHECK-LABEL: test_local_var_addr_aligned{{>?}}:
%addr1.32 = alloca i32
- %addr1 = bitcast i32* %addr1.32 to i8*
%addr2.32 = alloca i32
- %addr2 = bitcast i32* %addr2.32 to i8*
; CHECK: add r0, sp, #{{[0-9]+}}
; CHECK: bl
- call void @take_ptr(i8* %addr1)
+ call void @take_ptr(ptr %addr1.32)
; CHECK: mov r0, sp
; CHECK-NOT: add r0
; CHECK: bl
- call void @take_ptr(i8* %addr2)
+ call void @take_ptr(ptr %addr2.32)
ret void
}
@@ -83,13 +79,12 @@ define void @test_local_var_addr_aligned() {
define void @test_local_var_big_offset() {
; CHECK-LABEL: test_local_var_big_offset{{>?}}:
%addr1.32 = alloca i32, i32 257
- %addr1 = bitcast i32* %addr1.32 to i8*
%addr2.32 = alloca i32, i32 257
; CHECK: add [[RTMP:r[0-9]+]], sp, #1020
; CHECK: adds [[RTMP]], #8
; CHECK: bl
- call void @take_ptr(i8* %addr1)
+ call void @take_ptr(ptr %addr1.32)
ret void
}
@@ -102,7 +97,7 @@ define void @test_local_var_offset_1020() {
; CHECK: add r0, sp, #1020
; CHECK-NEXT: bl
- call void @take_ptr(i8* %addr1)
+ call void @take_ptr(ptr %addr1)
ret void
}
@@ -118,9 +113,9 @@ define void @test_local_var_offset_1268() {
; CHECK: add r0, sp, #1020
; CHECK: adds r0, #248
; CHECK-NEXT: bl
- call void @take_ptr(i8* %addr1)
+ call void @take_ptr(ptr %addr1)
ret void
}
-declare void @take_ptr(i8*)
+declare void @take_ptr(ptr)
diff --git a/llvm/test/CodeGen/ARM/thumb1_return_sequence.ll b/llvm/test/CodeGen/ARM/thumb1_return_sequence.ll
index 8e4ef7a629a7c..5b554e84fe702 100644
--- a/llvm/test/CodeGen/ARM/thumb1_return_sequence.ll
+++ b/llvm/test/CodeGen/ARM/thumb1_return_sequence.ll
@@ -3,7 +3,7 @@
; CHECK-V4T-LABEL: clobberframe
; CHECK-V5T-LABEL: clobberframe
-define <4 x i32> @clobberframe(<6 x i32>* %p) #0 {
+define <4 x i32> @clobberframe(ptr %p) #0 {
entry:
; Prologue
; --------
@@ -15,10 +15,10 @@ entry:
%b = alloca <6 x i32>, align 16
%a = alloca <4 x i32>, align 16
- %stuff = load <6 x i32>, <6 x i32>* %p, align 16
- store <6 x i32> %stuff, <6 x i32>* %b, align 16
- store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16
- %0 = load <4 x i32>, <4 x i32>* %a, align 16
+ %stuff = load <6 x i32>, ptr %p, align 16
+ store <6 x i32> %stuff, ptr %b, align 16
+ store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, ptr %a, align 16
+ %0 = load <4 x i32>, ptr %a, align 16
ret <4 x i32> %0
; Epilogue
@@ -49,10 +49,10 @@ entry:
%b = alloca <4 x i32>, align 16
%a = alloca <4 x i32>, align 16
- store <4 x i32> <i32 42, i32 42, i32 42, i32 42>, <4 x i32>* %b, align 16
- store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16
- %0 = load <4 x i32>, <4 x i32>* %a, align 16
- call void @llvm.va_start(i8* null)
+ store <4 x i32> <i32 42, i32 42, i32 42, i32 42>, ptr %b, align 16
+ store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, ptr %a, align 16
+ %0 = load <4 x i32>, ptr %a, align 16
+ call void @llvm.va_start(ptr null)
ret <4 x i32> %0
; Epilogue
@@ -73,14 +73,14 @@ entry:
; CHECK-V4T-LABEL: simpleframe
; CHECK-V5T-LABEL: simpleframe
-define i32 @simpleframe(<6 x i32>* %p) #0 {
+define i32 @simpleframe(ptr %p) #0 {
entry:
; Prologue
; --------
; CHECK-V4T: push {[[SAVED:(r[4567](, )?)+]], lr}
; CHECK-V5T: push {[[SAVED:(r[4567](, )?)+]], lr}
- %0 = load <6 x i32>, <6 x i32>* %p, align 16
+ %0 = load <6 x i32>, ptr %p, align 16
%1 = extractelement <6 x i32> %0, i32 0
%2 = extractelement <6 x i32> %0, i32 1
%3 = extractelement <6 x i32> %0, i32 2
@@ -124,31 +124,31 @@ entry:
%b = alloca i32, align 4
%c = alloca i32, align 4
%d = alloca i32, align 4
- store i32 1, i32* %a, align 4
- store i32 2, i32* %b, align 4
- store i32 3, i32* %c, align 4
- store i32 4, i32* %d, align 4
- %0 = load i32, i32* %a, align 4
+ store i32 1, ptr %a, align 4
+ store i32 2, ptr %b, align 4
+ store i32 3, ptr %c, align 4
+ store i32 4, ptr %d, align 4
+ %0 = load i32, ptr %a, align 4
%inc = add nsw i32 %0, 1
- store i32 %inc, i32* %a, align 4
- %1 = load i32, i32* %b, align 4
+ store i32 %inc, ptr %a, align 4
+ %1 = load i32, ptr %b, align 4
%inc1 = add nsw i32 %1, 1
- store i32 %inc1, i32* %b, align 4
- %2 = load i32, i32* %c, align 4
+ store i32 %inc1, ptr %b, align 4
+ %2 = load i32, ptr %c, align 4
%inc2 = add nsw i32 %2, 1
- store i32 %inc2, i32* %c, align 4
- %3 = load i32, i32* %d, align 4
+ store i32 %inc2, ptr %c, align 4
+ %3 = load i32, ptr %d, align 4
%inc3 = add nsw i32 %3, 1
- store i32 %inc3, i32* %d, align 4
- %4 = load i32, i32* %a, align 4
- %5 = load i32, i32* %b, align 4
+ store i32 %inc3, ptr %d, align 4
+ %4 = load i32, ptr %a, align 4
+ %5 = load i32, ptr %b, align 4
%add = add nsw i32 %4, %5
- %6 = load i32, i32* %c, align 4
+ %6 = load i32, ptr %c, align 4
%add4 = add nsw i32 %add, %6
- %7 = load i32, i32* %d, align 4
+ %7 = load i32, ptr %d, align 4
%add5 = add nsw i32 %add4, %7
%add6 = add nsw i32 %add5, %i
- call void @llvm.va_start(i8* null)
+ call void @llvm.va_start(ptr null)
ret i32 %add6
; Epilogue
@@ -197,7 +197,7 @@ entry:
; CHECK-V5T: sub sp,
; CHECK-V5T: push {[[SAVED:(r[4567](, )?)+]], lr}
- call void @llvm.va_start(i8* null)
+ call void @llvm.va_start(ptr null)
ret i32 %i;
; Epilogue
; --------
@@ -215,4 +215,4 @@ entry:
; CHECK-V5T-NEXT: bx [[POP_REG]]
}
-declare void @llvm.va_start(i8*) nounwind
+declare void @llvm.va_start(ptr) nounwind
diff --git a/llvm/test/CodeGen/ARM/thumb2-size-opt.ll b/llvm/test/CodeGen/ARM/thumb2-size-opt.ll
index c434d33fa0d44..f9f29fc064a20 100644
--- a/llvm/test/CodeGen/ARM/thumb2-size-opt.ll
+++ b/llvm/test/CodeGen/ARM/thumb2-size-opt.ll
@@ -83,7 +83,7 @@ entry:
ret i32 %shr
}
-define i32 @bundled_instruction(i32* %addr, i32** %addr2, i1 %tst) minsize {
+define i32 @bundled_instruction(ptr %addr, ptr %addr2, i1 %tst) minsize {
; CHECK-LABEL: bundled_instruction:
; CHECK: itee ne
; CHECK: ldmeq r3!, {{{r[0-9]+}}}
@@ -93,21 +93,21 @@ true:
ret i32 0
false:
- %res = load i32, i32* %addr, align 4
- %next = getelementptr i32, i32* %addr, i32 1
- store i32* %next, i32** %addr2
+ %res = load i32, ptr %addr, align 4
+ %next = getelementptr i32, ptr %addr, i32 1
+ store ptr %next, ptr %addr2
ret i32 %res
}
; ldm instructions fault on misaligned accesses so we mustn't convert
; this post-indexed ldr into one.
-define i32* @misaligned_post(i32* %src, i32* %dest) minsize {
+define ptr @misaligned_post(ptr %src, ptr %dest) minsize {
; CHECK-LABEL: misaligned_post:
; CHECK: ldr [[VAL:.*]], [r0], #4
; CHECK: str [[VAL]], [r1]
- %val = load i32, i32* %src, align 1
- store i32 %val, i32* %dest
- %next = getelementptr i32, i32* %src, i32 1
- ret i32* %next
+ %val = load i32, ptr %src, align 1
+ store i32 %val, ptr %dest
+ %next = getelementptr i32, ptr %src, i32 1
+ ret ptr %next
}
diff --git a/llvm/test/CodeGen/ARM/thumb2-size-reduction-internal-flags.ll b/llvm/test/CodeGen/ARM/thumb2-size-reduction-internal-flags.ll
index 578777f97c503..ba81702a6b408 100644
--- a/llvm/test/CodeGen/ARM/thumb2-size-reduction-internal-flags.ll
+++ b/llvm/test/CodeGen/ARM/thumb2-size-reduction-internal-flags.ll
@@ -3,7 +3,7 @@
target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
target triple = "thumbv7s-apple-ios8.0.0"
-%struct.cells = type { i32, i32, %struct.cells* }
+%struct.cells = type { i32, i32, ptr }
@reg_len = external global i32, align 4
@@ -13,9 +13,9 @@ target triple = "thumbv7s-apple-ios8.0.0"
; CHECK-LABEL: @simulate
; Function Attrs: nounwind optsize ssp
-define i32 @simulate(i32 %iterations, %struct.cells* nocapture %present, double %prob, i8* nocapture readonly %structure) {
+define i32 @simulate(i32 %iterations, ptr nocapture %present, double %prob, ptr nocapture readonly %structure) {
entry:
- %0 = load i32, i32* @reg_len, align 4, !tbaa !3
+ %0 = load i32, ptr @reg_len, align 4, !tbaa !3
%sub = add nsw i32 %0, -1
%div = sdiv i32 %sub, 31
%rem2 = srem i32 %sub, 31
@@ -32,7 +32,7 @@ for.cond34.preheader: ; preds = %for.inc30
for.cond6.preheader: ; preds = %for.inc30, %for.cond3.preheader
%call197 = phi i32 [ %call, %for.inc30 ], [ %call192, %for.cond3.preheader ]
%i.0196 = phi i32 [ %inc31, %for.inc30 ], [ 0, %for.cond3.preheader ]
- %temp.1195 = phi %struct.cells* [ %5, %for.inc30 ], [ %present, %for.cond3.preheader ]
+ %temp.1195 = phi ptr [ %5, %for.inc30 ], [ %present, %for.cond3.preheader ]
%savefaulty.0194 = phi i32 [ %add12, %for.inc30 ], [ 0, %for.cond3.preheader ]
%savef_free.0193 = phi i32 [ %add11, %for.inc30 ], [ 0, %for.cond3.preheader ]
br label %for.body8
@@ -40,22 +40,20 @@ for.cond6.preheader: ; preds = %for.inc30, %for.con
for.body8: ; preds = %for.body8, %for.cond6.preheader
%randv.0190 = phi i32 [ %call197, %for.cond6.preheader ], [ %shr, %for.body8 ]
%j.0189 = phi i32 [ 0, %for.cond6.preheader ], [ %inc, %for.body8 ]
- %temp.2188 = phi %struct.cells* [ %temp.1195, %for.cond6.preheader ], [ %5, %for.body8 ]
+ %temp.2188 = phi ptr [ %temp.1195, %for.cond6.preheader ], [ %5, %for.body8 ]
%savefaulty.1187 = phi i32 [ %savefaulty.0194, %for.cond6.preheader ], [ %add12, %for.body8 ]
%savef_free.1186 = phi i32 [ %savef_free.0193, %for.cond6.preheader ], [ %add11, %for.body8 ]
- %f_free = getelementptr inbounds %struct.cells, %struct.cells* %temp.2188, i32 0, i32 0
- %1 = load i32, i32* %f_free, align 4, !tbaa !7
+ %1 = load i32, ptr %temp.2188, align 4, !tbaa !7
%add11 = add nsw i32 %1, %savef_free.1186
- %faulty = getelementptr inbounds %struct.cells, %struct.cells* %temp.2188, i32 0, i32 1
- %2 = load i32, i32* %faulty, align 4, !tbaa !10
+ %faulty = getelementptr inbounds %struct.cells, ptr %temp.2188, i32 0, i32 1
+ %2 = load i32, ptr %faulty, align 4, !tbaa !10
%add12 = add nsw i32 %2, %savefaulty.1187
- %next = getelementptr inbounds %struct.cells, %struct.cells* %temp.2188, i32 0, i32 2
- %3 = load %struct.cells*, %struct.cells** %next, align 4, !tbaa !11
- %f_free13 = getelementptr inbounds %struct.cells, %struct.cells* %3, i32 0, i32 0
- %4 = load i32, i32* %f_free13, align 4, !tbaa !7
+ %next = getelementptr inbounds %struct.cells, ptr %temp.2188, i32 0, i32 2
+ %3 = load ptr, ptr %next, align 4, !tbaa !11
+ %4 = load i32, ptr %3, align 4, !tbaa !7
%add14 = add nsw i32 %4, %randv.0190
%and = and i32 %add14, 1
- store i32 %and, i32* %f_free, align 4, !tbaa !7
+ store i32 %and, ptr %temp.2188, align 4, !tbaa !7
%call16 = tail call i32 @lrand48() #2
%rem17 = srem i32 %call16, 1000
%conv18 = sitofp i32 %rem17 to double
@@ -63,12 +61,12 @@ for.body8: ; preds = %for.body8, %for.con
%cmp20 = fcmp olt double %div19, %prob
%xor = zext i1 %cmp20 to i32
%randv.1 = xor i32 %xor, %randv.0190
- %5 = load %struct.cells*, %struct.cells** %next, align 4, !tbaa !11
- %faulty25 = getelementptr inbounds %struct.cells, %struct.cells* %5, i32 0, i32 1
- %6 = load i32, i32* %faulty25, align 4, !tbaa !10
+ %5 = load ptr, ptr %next, align 4, !tbaa !11
+ %faulty25 = getelementptr inbounds %struct.cells, ptr %5, i32 0, i32 1
+ %6 = load i32, ptr %faulty25, align 4, !tbaa !10
%add26 = add nsw i32 %randv.1, %6
%and27 = and i32 %add26, 1
- store i32 %and27, i32* %faulty, align 4, !tbaa !10
+ store i32 %and27, ptr %faulty, align 4, !tbaa !10
%shr = ashr i32 %randv.0190, 1
%inc = add nuw nsw i32 %j.0189, 1
%exitcond = icmp eq i32 %inc, 31
@@ -82,16 +80,14 @@ for.inc30: ; preds = %for.body8
for.body37: ; preds = %for.body37, %for.cond34.preheader
%randv.2207 = phi i32 [ %shr70, %for.body37 ], [ %call, %for.cond34.preheader ]
- %temp.3205 = phi %struct.cells* [ %9, %for.body37 ], [ %5, %for.cond34.preheader ]
- %f_free45 = getelementptr inbounds %struct.cells, %struct.cells* %temp.3205, i32 0, i32 0
- %.pre220 = getelementptr inbounds %struct.cells, %struct.cells* %temp.3205, i32 0, i32 1
- %next50 = getelementptr inbounds %struct.cells, %struct.cells* %temp.3205, i32 0, i32 2
- %7 = load %struct.cells*, %struct.cells** %next50, align 4, !tbaa !11
- %f_free51 = getelementptr inbounds %struct.cells, %struct.cells* %7, i32 0, i32 0
- %8 = load i32, i32* %f_free51, align 4, !tbaa !7
+ %temp.3205 = phi ptr [ %9, %for.body37 ], [ %5, %for.cond34.preheader ]
+ %.pre220 = getelementptr inbounds %struct.cells, ptr %temp.3205, i32 0, i32 1
+ %next50 = getelementptr inbounds %struct.cells, ptr %temp.3205, i32 0, i32 2
+ %7 = load ptr, ptr %next50, align 4, !tbaa !11
+ %8 = load i32, ptr %7, align 4, !tbaa !7
%add52 = add nsw i32 %8, %randv.2207
%and53 = and i32 %add52, 1
- store i32 %and53, i32* %f_free45, align 4, !tbaa !7
+ store i32 %and53, ptr %temp.3205, align 4, !tbaa !7
%call55 = tail call i32 @lrand48() #2
%rem56 = srem i32 %call55, 1000
%conv57 = sitofp i32 %rem56 to double
@@ -99,44 +95,43 @@ for.body37: ; preds = %for.body37, %for.co
%cmp59 = fcmp olt double %div58, %prob
%xor62 = zext i1 %cmp59 to i32
%randv.3 = xor i32 %xor62, %randv.2207
- %9 = load %struct.cells*, %struct.cells** %next50, align 4, !tbaa !11
- %faulty65 = getelementptr inbounds %struct.cells, %struct.cells* %9, i32 0, i32 1
- %10 = load i32, i32* %faulty65, align 4, !tbaa !10
+ %9 = load ptr, ptr %next50, align 4, !tbaa !11
+ %faulty65 = getelementptr inbounds %struct.cells, ptr %9, i32 0, i32 1
+ %10 = load i32, ptr %faulty65, align 4, !tbaa !10
%add66 = add nsw i32 %randv.3, %10
%and67 = and i32 %add66, 1
- store i32 %and67, i32* %.pre220, align 4, !tbaa !10
+ store i32 %and67, ptr %.pre220, align 4, !tbaa !10
%shr70 = ashr i32 %randv.2207, 1
br label %for.body37
for.end73: ; preds = %for.cond34.preheader
%call74 = tail call i32 @lrand48() #2
- %11 = load i32, i32* @reg_len, align 4, !tbaa !3
+ %11 = load i32, ptr @reg_len, align 4, !tbaa !3
%sub75 = add nsw i32 %11, -1
- %arrayidx76 = getelementptr inbounds i8, i8* %structure, i32 %sub75
- %12 = load i8, i8* %arrayidx76, align 1, !tbaa !12
+ %arrayidx76 = getelementptr inbounds i8, ptr %structure, i32 %sub75
+ %12 = load i8, ptr %arrayidx76, align 1, !tbaa !12
%cmp78 = icmp eq i8 %12, 49
- %f_free81 = getelementptr inbounds %struct.cells, %struct.cells* %5, i32 0, i32 0
br i1 %cmp78, label %if.then80, label %for.end73.if.end85_crit_edge
for.end73.if.end85_crit_edge: ; preds = %for.end73
- %.pre222 = getelementptr inbounds %struct.cells, %struct.cells* %5, i32 0, i32 1
+ %.pre222 = getelementptr inbounds %struct.cells, ptr %5, i32 0, i32 1
br label %if.end85
if.then80: ; preds = %for.end73
- %13 = load i32, i32* %f_free81, align 4, !tbaa !7
+ %13 = load i32, ptr %5, align 4, !tbaa !7
%add82 = add nsw i32 %13, %add11
- %faulty83 = getelementptr inbounds %struct.cells, %struct.cells* %5, i32 0, i32 1
- %14 = load i32, i32* %faulty83, align 4, !tbaa !10
+ %faulty83 = getelementptr inbounds %struct.cells, ptr %5, i32 0, i32 1
+ %14 = load i32, ptr %faulty83, align 4, !tbaa !10
%add84 = add nsw i32 %14, %add12
br label %if.end85
if.end85: ; preds = %if.then80, %for.end73.if.end85_crit_edge
- %faulty100.pre-phi = phi i32* [ %.pre222, %for.end73.if.end85_crit_edge ], [ %faulty83, %if.then80 ]
+ %faulty100.pre-phi = phi ptr [ %.pre222, %for.end73.if.end85_crit_edge ], [ %faulty83, %if.then80 ]
%savef_free.5 = phi i32 [ %add11, %for.end73.if.end85_crit_edge ], [ %add82, %if.then80 ]
%savefaulty.5 = phi i32 [ %add12, %for.end73.if.end85_crit_edge ], [ %add84, %if.then80 ]
%add86 = add nsw i32 %savef_free.5, %call74
%and87 = and i32 %add86, 1
- store i32 %and87, i32* %f_free81, align 4, !tbaa !7
+ store i32 %and87, ptr %5, align 4, !tbaa !7
%call89 = tail call i32 @lrand48() #2
%rem90 = srem i32 %call89, 10000
%conv91 = sitofp i32 %rem90 to double
@@ -146,7 +141,7 @@ if.end85: ; preds = %if.then80, %for.end
%randv.4 = xor i32 %xor96, %call74
%add98 = add nsw i32 %randv.4, %savefaulty.5
%and99 = and i32 %add98, 1
- store i32 %and99, i32* %faulty100.pre-phi, align 4, !tbaa !10
+ store i32 %and99, ptr %faulty100.pre-phi, align 4, !tbaa !10
br label %for.cond3.preheader
}
diff --git a/llvm/test/CodeGen/ARM/thumb_indirect_calls.ll b/llvm/test/CodeGen/ARM/thumb_indirect_calls.ll
index 317d0a424689d..cadebba4c1953 100644
--- a/llvm/test/CodeGen/ARM/thumb_indirect_calls.ll
+++ b/llvm/test/CodeGen/ARM/thumb_indirect_calls.ll
@@ -1,12 +1,12 @@
; RUN: llc -mtriple=thumbv4t-eabi %s -o - | FileCheck --check-prefix=CHECK -check-prefix=CHECK-V4T %s
; RUN: llc -mtriple=thumbv5t-eabi %s -o - | FileCheck --check-prefix=CHECK -check-prefix=CHECK-V5T %s
- at f = common global void (i32)* null, align 4
+ at f = common global ptr null, align 4
; CHECK-LABEL: foo:
define void @foo(i32 %x) {
entry:
- %0 = load void (i32)*, void (i32)** @f, align 4
+ %0 = load ptr, ptr @f, align 4
tail call void %0(i32 %x)
ret void
@@ -22,7 +22,7 @@ entry:
}
; CHECK-LABEL: bar:
-define void @bar(void (i32)* nocapture %g, i32 %x, void (i32)* nocapture %h) {
+define void @bar(ptr nocapture %g, i32 %x, ptr nocapture %h) {
entry:
tail call void %g(i32 %x)
tail call void %h(i32 %x)
diff --git a/llvm/test/CodeGen/ARM/tls-models.ll b/llvm/test/CodeGen/ARM/tls-models.ll
index 33c85299bdcc5..795162fd13107 100644
--- a/llvm/test/CodeGen/ARM/tls-models.ll
+++ b/llvm/test/CodeGen/ARM/tls-models.ll
@@ -22,9 +22,9 @@
; ----- no model specified -----
-define i32* @f1() {
+define ptr @f1() {
entry:
- ret i32* @external_gd
+ ret ptr @external_gd
; COMMON-LABEL: f1:
; Non-PIC code can use initial-exec, PIC code has to use general dynamic.
@@ -33,9 +33,9 @@ entry:
; EMU: __emutls_get_address
}
-define i32* @f2() {
+define ptr @f2() {
entry:
- ret i32* @internal_gd
+ ret ptr @internal_gd
; COMMON-LABEL: f2:
; Non-PIC code can use local exec, PIC code can use local dynamic,
@@ -48,9 +48,9 @@ entry:
; ----- localdynamic specified -----
-define i32* @f3() {
+define ptr @f3() {
entry:
- ret i32* @external_ld
+ ret ptr @external_ld
; COMMON-LABEL: f3:
; Non-PIC code can use initial exec, PIC should use local dynamic,
@@ -60,9 +60,9 @@ entry:
; EMU: __emutls_get_address
}
-define i32* @f4() {
+define ptr @f4() {
entry:
- ret i32* @internal_ld
+ ret ptr @internal_ld
; COMMON-LABEL: f4:
; Non-PIC code can use local exec, PIC code can use local dynamic,
@@ -75,9 +75,9 @@ entry:
; ----- initialexec specified -----
-define i32* @f5() {
+define ptr @f5() {
entry:
- ret i32* @external_ie
+ ret ptr @external_ie
; COMMON-LABEL: f5:
; Non-PIC and PIC code will use initial exec as specified.
@@ -86,9 +86,9 @@ entry:
; EMU: __emutls_get_address
}
-define i32* @f6() {
+define ptr @f6() {
entry:
- ret i32* @internal_ie
+ ret ptr @internal_ie
; COMMON-LABEL: f6:
; Non-PIC code can use local exec, PIC code use initial exec as specified.
@@ -100,9 +100,9 @@ entry:
; ----- localexec specified -----
-define i32* @f7() {
+define ptr @f7() {
entry:
- ret i32* @external_le
+ ret ptr @external_le
; COMMON-LABEL: f7:
; Non-PIC and PIC code will use local exec as specified.
@@ -111,9 +111,9 @@ entry:
; EMU: __emutls_get_address
}
-define i32* @f8() {
+define ptr @f8() {
entry:
- ret i32* @internal_le
+ ret ptr @internal_le
; COMMON-LABEL: f8:
; Non-PIC and PIC code will use local exec as specified.
diff --git a/llvm/test/CodeGen/ARM/tls1.ll b/llvm/test/CodeGen/ARM/tls1.ll
index 7e26800724f08..93089022789f1 100644
--- a/llvm/test/CodeGen/ARM/tls1.ll
+++ b/llvm/test/CodeGen/ARM/tls1.ll
@@ -8,15 +8,15 @@
; PIC: __tls_get_addr
- at i = dso_local thread_local global i32 15 ; <i32*> [#uses=2]
+ at i = dso_local thread_local global i32 15 ; <ptr> [#uses=2]
define dso_local i32 @f() {
entry:
- %tmp1 = load i32, i32* @i ; <i32> [#uses=1]
+ %tmp1 = load i32, ptr @i ; <i32> [#uses=1]
ret i32 %tmp1
}
-define dso_local i32* @g() {
+define dso_local ptr @g() {
entry:
- ret i32* @i
+ ret ptr @i
}
diff --git a/llvm/test/CodeGen/ARM/tls2.ll b/llvm/test/CodeGen/ARM/tls2.ll
index ddea6c053915b..dce3e70343109 100644
--- a/llvm/test/CodeGen/ARM/tls2.ll
+++ b/llvm/test/CodeGen/ARM/tls2.ll
@@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=arm-linux-gnueabi -relocation-model=pic \
; RUN: | FileCheck %s -check-prefix=CHECK-PIC
- at i = external thread_local global i32 ; <i32*> [#uses=2]
+ at i = external thread_local global i32 ; <ptr> [#uses=2]
define i32 @f() {
; CHECK-NONPIC-LABEL: f:
@@ -12,16 +12,16 @@ define i32 @f() {
; CHECK-PIC-LABEL: f:
; CHECK-PIC: __tls_get_addr
entry:
- %tmp1 = load i32, i32* @i ; <i32> [#uses=1]
+ %tmp1 = load i32, ptr @i ; <i32> [#uses=1]
ret i32 %tmp1
}
-define i32* @g() {
+define ptr @g() {
; CHECK-NONPIC-LABEL: g:
; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}]
; CHECK-NONPIC: i(GOTTPOFF)
; CHECK-PIC-LABEL: g:
; CHECK-PIC: __tls_get_addr
entry:
- ret i32* @i
+ ret ptr @i
}
diff --git a/llvm/test/CodeGen/ARM/tls3.ll b/llvm/test/CodeGen/ARM/tls3.ll
index 40954d3d96a58..3305180a77fd3 100644
--- a/llvm/test/CodeGen/ARM/tls3.ll
+++ b/llvm/test/CodeGen/ARM/tls3.ll
@@ -6,7 +6,7 @@
define i32 @main() {
entry:
- %tmp2 = load i32, i32* getelementptr (%struct.anon, %struct.anon* @teste, i32 0, i32 0), align 8
+ %tmp2 = load i32, ptr @teste, align 8
ret i32 %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/trunc_ldr.ll b/llvm/test/CodeGen/ARM/trunc_ldr.ll
index ca7ad9a2fc623..5aaf15f7041ff 100644
--- a/llvm/test/CodeGen/ARM/trunc_ldr.ll
+++ b/llvm/test/CodeGen/ARM/trunc_ldr.ll
@@ -1,21 +1,19 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
- %struct.A = type { i8, i8, i8, i8, i16, i8, i8, %struct.B** }
+ %struct.A = type { i8, i8, i8, i8, i16, i8, i8, ptr }
%struct.B = type { float, float, i32, i32, i32, [0 x i8] }
-define i8 @f1(%struct.A* %d) {
- %tmp2 = getelementptr %struct.A, %struct.A* %d, i32 0, i32 4
- %tmp23 = bitcast i16* %tmp2 to i32*
- %tmp4 = load i32, i32* %tmp23
+define i8 @f1(ptr %d) {
+ %tmp2 = getelementptr %struct.A, ptr %d, i32 0, i32 4
+ %tmp4 = load i32, ptr %tmp2
%tmp512 = lshr i32 %tmp4, 24
%tmp56 = trunc i32 %tmp512 to i8
ret i8 %tmp56
}
-define i32 @f2(%struct.A* %d) {
- %tmp2 = getelementptr %struct.A, %struct.A* %d, i32 0, i32 4
- %tmp23 = bitcast i16* %tmp2 to i32*
- %tmp4 = load i32, i32* %tmp23
+define i32 @f2(ptr %d) {
+ %tmp2 = getelementptr %struct.A, ptr %d, i32 0, i32 4
+ %tmp4 = load i32, ptr %tmp2
%tmp512 = lshr i32 %tmp4, 24
%tmp56 = trunc i32 %tmp512 to i8
%tmp57 = sext i8 %tmp56 to i32
diff --git a/llvm/test/CodeGen/ARM/truncstore-dag-combine.ll b/llvm/test/CodeGen/ARM/truncstore-dag-combine.ll
index 5142a305b3a72..de4d306610e21 100644
--- a/llvm/test/CodeGen/ARM/truncstore-dag-combine.ll
+++ b/llvm/test/CodeGen/ARM/truncstore-dag-combine.ll
@@ -3,21 +3,19 @@
; CHECK-LABEL: bar
; CHECK-NOT: orr
; CHECK-NOT: mov
-define void @bar(i8* %P, i16* %Q) {
+define void @bar(ptr %P, ptr %Q) {
entry:
- %P1 = bitcast i8* %P to i16* ; <i16*> [#uses=1]
- %tmp = load i16, i16* %Q, align 1 ; <i16> [#uses=1]
- store i16 %tmp, i16* %P1, align 1
+ %tmp = load i16, ptr %Q, align 1 ; <i16> [#uses=1]
+ store i16 %tmp, ptr %P, align 1
ret void
}
; CHECK-LABEL: foo
; CHECK-NOT: orr
; CHECK-NOT: mov
-define void @foo(i8* %P, i32* %Q) {
+define void @foo(ptr %P, ptr %Q) {
entry:
- %P1 = bitcast i8* %P to i32* ; <i32*> [#uses=1]
- %tmp = load i32, i32* %Q, align 1 ; <i32> [#uses=1]
- store i32 %tmp, i32* %P1, align 1
+ %tmp = load i32, ptr %Q, align 1 ; <i32> [#uses=1]
+ store i32 %tmp, ptr %P, align 1
ret void
}
diff --git a/llvm/test/CodeGen/ARM/twoaddrinstr.ll b/llvm/test/CodeGen/ARM/twoaddrinstr.ll
index e8c52e1b58df0..5890e09d0b0d2 100644
--- a/llvm/test/CodeGen/ARM/twoaddrinstr.ll
+++ b/llvm/test/CodeGen/ARM/twoaddrinstr.ll
@@ -13,10 +13,10 @@ define void @PR13378() nounwind {
; CHECK-NEXT: vst1.32
entry:
- %0 = load <4 x float>, <4 x float>* undef, align 4
- store <4 x float> zeroinitializer, <4 x float>* undef, align 4
- store <4 x float> %0, <4 x float>* undef, align 4
+ %0 = load <4 x float>, ptr undef, align 4
+ store <4 x float> zeroinitializer, ptr undef, align 4
+ store <4 x float> %0, ptr undef, align 4
%1 = insertelement <4 x float> %0, float 1.000000e+00, i32 3
- store <4 x float> %1, <4 x float>* undef, align 4
+ store <4 x float> %1, ptr undef, align 4
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/uint64tof64.ll b/llvm/test/CodeGen/ARM/uint64tof64.ll
index cd35ce74d8ee6..c5c0af683eaff 100644
--- a/llvm/test/CodeGen/ARM/uint64tof64.ll
+++ b/llvm/test/CodeGen/ARM/uint64tof64.ll
@@ -1,17 +1,17 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+vfp2
- %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.FILE = type { ptr, i32, i32, i16, i16, %struct.__sbuf, i32, ptr, ptr, ptr, ptr, ptr, %struct.__sbuf, ptr, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
%struct.__sFILEX = type opaque
- %struct.__sbuf = type { i8*, i32 }
-@"\01LC10" = external constant [54 x i8] ; <[54 x i8]*> [#uses=1]
+ %struct.__sbuf = type { ptr, i32 }
+@"\01LC10" = external constant [54 x i8] ; <ptr> [#uses=1]
define fastcc void @t() {
entry:
- %0 = load i64, i64* null, align 4 ; <i64> [#uses=1]
+ %0 = load i64, ptr null, align 4 ; <i64> [#uses=1]
%1 = uitofp i64 %0 to double ; <double> [#uses=1]
%2 = fdiv double 0.000000e+00, %1 ; <double> [#uses=1]
- %3 = call i32 (%struct.FILE*, i8*, ...) @fprintf(%struct.FILE* null, i8* getelementptr ([54 x i8], [54 x i8]* @"\01LC10", i32 0, i32 0), i64 0, double %2) ; <i32> [#uses=0]
+ %3 = call i32 (ptr, ptr, ...) @fprintf(ptr null, ptr @"\01LC10", i64 0, double %2) ; <i32> [#uses=0]
ret void
}
-declare i32 @fprintf(%struct.FILE*, i8*, ...)
+declare i32 @fprintf(ptr, ptr, ...)
diff --git a/llvm/test/CodeGen/ARM/umulo-32.ll b/llvm/test/CodeGen/ARM/umulo-32.ll
index cdfece4ab08e6..b5f6b3aa61fc3 100644
--- a/llvm/test/CodeGen/ARM/umulo-32.ll
+++ b/llvm/test/CodeGen/ARM/umulo-32.ll
@@ -27,7 +27,7 @@ define i32 @test1(i32 %a, i1 %x) nounwind {
declare %umul.ty @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
-define i32 @test2(i32* %m_degree) ssp {
+define i32 @test2(ptr %m_degree) ssp {
; CHECK-LABEL: test2:
; CHECK: @ %bb.0:
; CHECK-NEXT: push {r4, lr}
@@ -46,13 +46,13 @@ define i32 @test2(i32* %m_degree) ssp {
; CHECK-NEXT: bl _Znam
; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: pop {r4, pc}
-%val = load i32, i32* %m_degree, align 4
+%val = load i32, ptr %m_degree, align 4
%res = call %umul.ty @llvm.umul.with.overflow.i32(i32 %val, i32 8)
%ov = extractvalue %umul.ty %res, 1
%mul = extractvalue %umul.ty %res, 0
%sel = select i1 %ov, i32 -1, i32 %mul
-%ret = call noalias i8* @_Znam(i32 %sel)
+%ret = call noalias ptr @_Znam(i32 %sel)
ret i32 0
}
-declare noalias i8* @_Znam(i32)
+declare noalias ptr @_Znam(i32)
diff --git a/llvm/test/CodeGen/ARM/unaligned_load_store.ll b/llvm/test/CodeGen/ARM/unaligned_load_store.ll
index 75098e18fc956..f9890386a76fd 100644
--- a/llvm/test/CodeGen/ARM/unaligned_load_store.ll
+++ b/llvm/test/CodeGen/ARM/unaligned_load_store.ll
@@ -10,7 +10,7 @@
; rdar://7113725
; rdar://12091029
-define void @t(i8* nocapture %a, i8* nocapture %b) nounwind {
+define void @t(ptr nocapture %a, ptr nocapture %b) nounwind {
entry:
; EXPANDED-LABEL: t:
; EXPANDED-DAG: ldrb [[R2:r[0-9]+]]
@@ -26,14 +26,12 @@ entry:
; UNALIGNED: ldr r1
; UNALIGNED: str r1
- %__src1.i = bitcast i8* %b to i32* ; <i32*> [#uses=1]
- %__dest2.i = bitcast i8* %a to i32* ; <i32*> [#uses=1]
- %tmp.i = load i32, i32* %__src1.i, align 1 ; <i32> [#uses=1]
- store i32 %tmp.i, i32* %__dest2.i, align 1
+ %tmp.i = load i32, ptr %b, align 1 ; <i32> [#uses=1]
+ store i32 %tmp.i, ptr %a, align 1
ret void
}
-define void @hword(double* %a, double* %b) nounwind {
+define void @hword(ptr %a, ptr %b) nounwind {
entry:
; EXPANDED-LABEL: hword:
; EXPANDED-NOT: vld1
@@ -44,12 +42,12 @@ entry:
; UNALIGNED-LABEL: hword:
; UNALIGNED: vld1.16
; UNALIGNED: vst1.16
- %tmp = load double, double* %a, align 2
- store double %tmp, double* %b, align 2
+ %tmp = load double, ptr %a, align 2
+ store double %tmp, ptr %b, align 2
ret void
}
-define void @byte(double* %a, double* %b) nounwind {
+define void @byte(ptr %a, ptr %b) nounwind {
entry:
; EXPANDED-LABEL: byte:
; EXPANDED-NOT: vld1
@@ -60,12 +58,12 @@ entry:
; UNALIGNED-LABEL: byte:
; UNALIGNED: vld1.8
; UNALIGNED: vst1.8
- %tmp = load double, double* %a, align 1
- store double %tmp, double* %b, align 1
+ %tmp = load double, ptr %a, align 1
+ store double %tmp, ptr %b, align 1
ret void
}
-define void @byte_word_ops(i32* %a, i32* %b) nounwind {
+define void @byte_word_ops(ptr %a, ptr %b) nounwind {
entry:
; EXPANDED-LABEL: byte_word_ops:
; EXPANDED: ldrb
@@ -76,7 +74,7 @@ entry:
; UNALIGNED: ldr
; UNALIGNED-NOT: strb
; UNALIGNED: str
- %tmp = load i32, i32* %a, align 1
- store i32 %tmp, i32* %b, align 1
+ %tmp = load i32, ptr %a, align 1
+ store i32 %tmp, ptr %b, align 1
ret void
}
diff --git a/llvm/test/CodeGen/ARM/unaligned_load_store_vector.ll b/llvm/test/CodeGen/ARM/unaligned_load_store_vector.ll
index 72dad29353e7f..207a22218f271 100644
--- a/llvm/test/CodeGen/ARM/unaligned_load_store_vector.ll
+++ b/llvm/test/CodeGen/ARM/unaligned_load_store_vector.ll
@@ -3,17 +3,13 @@
;ALIGN = 1
;SIZE = 64
;TYPE = <8 x i8>
-define void @v64_v8i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v64_v8i8_1(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v64_v8i8_1:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <8 x i8>*
- %vo = bitcast i8* %po to <8 x i8>*
;CHECK: vld1.8
- %v1 = load <8 x i8>, <8 x i8>* %vi, align 1
+ %v1 = load <8 x i8>, ptr %in, align 1
;CHECK: vst1.8
- store <8 x i8> %v1, <8 x i8>* %vo, align 1
+ store <8 x i8> %v1, ptr %out, align 1
ret void
}
@@ -21,17 +17,13 @@ entry:
;ALIGN = 1
;SIZE = 64
;TYPE = <4 x i16>
-define void @v64_v4i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v64_v4i16_1(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v64_v4i16_1:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <4 x i16>*
- %vo = bitcast i8* %po to <4 x i16>*
;CHECK: vld1.8
- %v1 = load <4 x i16>, <4 x i16>* %vi, align 1
+ %v1 = load <4 x i16>, ptr %in, align 1
;CHECK: vst1.8
- store <4 x i16> %v1, <4 x i16>* %vo, align 1
+ store <4 x i16> %v1, ptr %out, align 1
ret void
}
@@ -39,17 +31,13 @@ entry:
;ALIGN = 1
;SIZE = 64
;TYPE = <2 x i32>
-define void @v64_v2i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v64_v2i32_1(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v64_v2i32_1:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <2 x i32>*
- %vo = bitcast i8* %po to <2 x i32>*
;CHECK: vld1.8
- %v1 = load <2 x i32>, <2 x i32>* %vi, align 1
+ %v1 = load <2 x i32>, ptr %in, align 1
;CHECK: vst1.8
- store <2 x i32> %v1, <2 x i32>* %vo, align 1
+ store <2 x i32> %v1, ptr %out, align 1
ret void
}
@@ -57,17 +45,13 @@ entry:
;ALIGN = 1
;SIZE = 64
;TYPE = <2 x float>
-define void @v64_v2f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v64_v2f32_1(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v64_v2f32_1:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <2 x float>*
- %vo = bitcast i8* %po to <2 x float>*
;CHECK: vld1.8
- %v1 = load <2 x float>, <2 x float>* %vi, align 1
+ %v1 = load <2 x float>, ptr %in, align 1
;CHECK: vst1.8
- store <2 x float> %v1, <2 x float>* %vo, align 1
+ store <2 x float> %v1, ptr %out, align 1
ret void
}
@@ -75,17 +59,13 @@ entry:
;ALIGN = 1
;SIZE = 128
;TYPE = <16 x i8>
-define void @v128_v16i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v128_v16i8_1(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v128_v16i8_1:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <16 x i8>*
- %vo = bitcast i8* %po to <16 x i8>*
;CHECK: vld1.8
- %v1 = load <16 x i8>, <16 x i8>* %vi, align 1
+ %v1 = load <16 x i8>, ptr %in, align 1
;CHECK: vst1.8
- store <16 x i8> %v1, <16 x i8>* %vo, align 1
+ store <16 x i8> %v1, ptr %out, align 1
ret void
}
@@ -93,17 +73,13 @@ entry:
;ALIGN = 1
;SIZE = 128
;TYPE = <8 x i16>
-define void @v128_v8i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v128_v8i16_1(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v128_v8i16_1:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <8 x i16>*
- %vo = bitcast i8* %po to <8 x i16>*
;CHECK: vld1.8
- %v1 = load <8 x i16>, <8 x i16>* %vi, align 1
+ %v1 = load <8 x i16>, ptr %in, align 1
;CHECK: vst1.8
- store <8 x i16> %v1, <8 x i16>* %vo, align 1
+ store <8 x i16> %v1, ptr %out, align 1
ret void
}
@@ -111,17 +87,13 @@ entry:
;ALIGN = 1
;SIZE = 128
;TYPE = <4 x i32>
-define void @v128_v4i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v128_v4i32_1(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v128_v4i32_1:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <4 x i32>*
- %vo = bitcast i8* %po to <4 x i32>*
;CHECK: vld1.8
- %v1 = load <4 x i32>, <4 x i32>* %vi, align 1
+ %v1 = load <4 x i32>, ptr %in, align 1
;CHECK: vst1.8
- store <4 x i32> %v1, <4 x i32>* %vo, align 1
+ store <4 x i32> %v1, ptr %out, align 1
ret void
}
@@ -129,17 +101,13 @@ entry:
;ALIGN = 1
;SIZE = 128
;TYPE = <2 x i64>
-define void @v128_v2i64_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v128_v2i64_1(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v128_v2i64_1:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <2 x i64>*
- %vo = bitcast i8* %po to <2 x i64>*
;CHECK: vld1.8
- %v1 = load <2 x i64>, <2 x i64>* %vi, align 1
+ %v1 = load <2 x i64>, ptr %in, align 1
;CHECK: vst1.8
- store <2 x i64> %v1, <2 x i64>* %vo, align 1
+ store <2 x i64> %v1, ptr %out, align 1
ret void
}
@@ -147,17 +115,13 @@ entry:
;ALIGN = 1
;SIZE = 128
;TYPE = <4 x float>
-define void @v128_v4f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v128_v4f32_1(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v128_v4f32_1:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <4 x float>*
- %vo = bitcast i8* %po to <4 x float>*
;CHECK: vld1.8
- %v1 = load <4 x float>, <4 x float>* %vi, align 1
+ %v1 = load <4 x float>, ptr %in, align 1
;CHECK: vst1.8
- store <4 x float> %v1, <4 x float>* %vo, align 1
+ store <4 x float> %v1, ptr %out, align 1
ret void
}
@@ -165,17 +129,13 @@ entry:
;ALIGN = 2
;SIZE = 64
;TYPE = <8 x i8>
-define void @v64_v8i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v64_v8i8_2(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v64_v8i8_2:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <8 x i8>*
- %vo = bitcast i8* %po to <8 x i8>*
;CHECK: vld1.16
- %v1 = load <8 x i8>, <8 x i8>* %vi, align 2
+ %v1 = load <8 x i8>, ptr %in, align 2
;CHECK: vst1.16
- store <8 x i8> %v1, <8 x i8>* %vo, align 2
+ store <8 x i8> %v1, ptr %out, align 2
ret void
}
@@ -183,17 +143,13 @@ entry:
;ALIGN = 2
;SIZE = 64
;TYPE = <4 x i16>
-define void @v64_v4i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v64_v4i16_2(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v64_v4i16_2:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <4 x i16>*
- %vo = bitcast i8* %po to <4 x i16>*
;CHECK: vld1.16
- %v1 = load <4 x i16>, <4 x i16>* %vi, align 2
+ %v1 = load <4 x i16>, ptr %in, align 2
;CHECK: vst1.16
- store <4 x i16> %v1, <4 x i16>* %vo, align 2
+ store <4 x i16> %v1, ptr %out, align 2
ret void
}
@@ -201,17 +157,13 @@ entry:
;ALIGN = 2
;SIZE = 64
;TYPE = <2 x i32>
-define void @v64_v2i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v64_v2i32_2(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v64_v2i32_2:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <2 x i32>*
- %vo = bitcast i8* %po to <2 x i32>*
;CHECK: vld1.16
- %v1 = load <2 x i32>, <2 x i32>* %vi, align 2
+ %v1 = load <2 x i32>, ptr %in, align 2
;CHECK: vst1.16
- store <2 x i32> %v1, <2 x i32>* %vo, align 2
+ store <2 x i32> %v1, ptr %out, align 2
ret void
}
@@ -219,17 +171,13 @@ entry:
;ALIGN = 2
;SIZE = 64
;TYPE = <2 x float>
-define void @v64_v2f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v64_v2f32_2(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v64_v2f32_2:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <2 x float>*
- %vo = bitcast i8* %po to <2 x float>*
;CHECK: vld1.16
- %v1 = load <2 x float>, <2 x float>* %vi, align 2
+ %v1 = load <2 x float>, ptr %in, align 2
;CHECK: vst1.16
- store <2 x float> %v1, <2 x float>* %vo, align 2
+ store <2 x float> %v1, ptr %out, align 2
ret void
}
@@ -237,17 +185,13 @@ entry:
;ALIGN = 2
;SIZE = 128
;TYPE = <16 x i8>
-define void @v128_v16i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v128_v16i8_2(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v128_v16i8_2:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <16 x i8>*
- %vo = bitcast i8* %po to <16 x i8>*
;CHECK: vld1.16
- %v1 = load <16 x i8>, <16 x i8>* %vi, align 2
+ %v1 = load <16 x i8>, ptr %in, align 2
;CHECK: vst1.16
- store <16 x i8> %v1, <16 x i8>* %vo, align 2
+ store <16 x i8> %v1, ptr %out, align 2
ret void
}
@@ -255,17 +199,13 @@ entry:
;ALIGN = 2
;SIZE = 128
;TYPE = <8 x i16>
-define void @v128_v8i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v128_v8i16_2(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v128_v8i16_2:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <8 x i16>*
- %vo = bitcast i8* %po to <8 x i16>*
;CHECK: vld1.16
- %v1 = load <8 x i16>, <8 x i16>* %vi, align 2
+ %v1 = load <8 x i16>, ptr %in, align 2
;CHECK: vst1.16
- store <8 x i16> %v1, <8 x i16>* %vo, align 2
+ store <8 x i16> %v1, ptr %out, align 2
ret void
}
@@ -273,17 +213,13 @@ entry:
;ALIGN = 2
;SIZE = 128
;TYPE = <4 x i32>
-define void @v128_v4i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v128_v4i32_2(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v128_v4i32_2:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <4 x i32>*
- %vo = bitcast i8* %po to <4 x i32>*
;CHECK: vld1.16
- %v1 = load <4 x i32>, <4 x i32>* %vi, align 2
+ %v1 = load <4 x i32>, ptr %in, align 2
;CHECK: vst1.16
- store <4 x i32> %v1, <4 x i32>* %vo, align 2
+ store <4 x i32> %v1, ptr %out, align 2
ret void
}
@@ -291,17 +227,13 @@ entry:
;ALIGN = 2
;SIZE = 128
;TYPE = <2 x i64>
-define void @v128_v2i64_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v128_v2i64_2(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v128_v2i64_2:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <2 x i64>*
- %vo = bitcast i8* %po to <2 x i64>*
;CHECK: vld1.16
- %v1 = load <2 x i64>, <2 x i64>* %vi, align 2
+ %v1 = load <2 x i64>, ptr %in, align 2
;CHECK: vst1.16
- store <2 x i64> %v1, <2 x i64>* %vo, align 2
+ store <2 x i64> %v1, ptr %out, align 2
ret void
}
@@ -309,17 +241,13 @@ entry:
;ALIGN = 2
;SIZE = 128
;TYPE = <4 x float>
-define void @v128_v4f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v128_v4f32_2(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v128_v4f32_2:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <4 x float>*
- %vo = bitcast i8* %po to <4 x float>*
;CHECK: vld1.16
- %v1 = load <4 x float>, <4 x float>* %vi, align 2
+ %v1 = load <4 x float>, ptr %in, align 2
;CHECK: vst1.16
- store <4 x float> %v1, <4 x float>* %vo, align 2
+ store <4 x float> %v1, ptr %out, align 2
ret void
}
@@ -327,17 +255,13 @@ entry:
;ALIGN = 4
;SIZE = 64
;TYPE = <8 x i8>
-define void @v64_v8i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v64_v8i8_4(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v64_v8i8_4:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <8 x i8>*
- %vo = bitcast i8* %po to <8 x i8>*
;CHECK: vldr
- %v1 = load <8 x i8>, <8 x i8>* %vi, align 4
+ %v1 = load <8 x i8>, ptr %in, align 4
;CHECK: vstr
- store <8 x i8> %v1, <8 x i8>* %vo, align 4
+ store <8 x i8> %v1, ptr %out, align 4
ret void
}
@@ -345,17 +269,13 @@ entry:
;ALIGN = 4
;SIZE = 64
;TYPE = <4 x i16>
-define void @v64_v4i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v64_v4i16_4(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v64_v4i16_4:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <4 x i16>*
- %vo = bitcast i8* %po to <4 x i16>*
;CHECK: vldr
- %v1 = load <4 x i16>, <4 x i16>* %vi, align 4
+ %v1 = load <4 x i16>, ptr %in, align 4
;CHECK: vstr
- store <4 x i16> %v1, <4 x i16>* %vo, align 4
+ store <4 x i16> %v1, ptr %out, align 4
ret void
}
@@ -363,17 +283,13 @@ entry:
;ALIGN = 4
;SIZE = 64
;TYPE = <2 x i32>
-define void @v64_v2i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v64_v2i32_4(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v64_v2i32_4:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <2 x i32>*
- %vo = bitcast i8* %po to <2 x i32>*
;CHECK: vldr
- %v1 = load <2 x i32>, <2 x i32>* %vi, align 4
+ %v1 = load <2 x i32>, ptr %in, align 4
;CHECK: vstr
- store <2 x i32> %v1, <2 x i32>* %vo, align 4
+ store <2 x i32> %v1, ptr %out, align 4
ret void
}
@@ -381,17 +297,13 @@ entry:
;ALIGN = 4
;SIZE = 64
;TYPE = <2 x float>
-define void @v64_v2f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v64_v2f32_4(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v64_v2f32_4:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <2 x float>*
- %vo = bitcast i8* %po to <2 x float>*
;CHECK: vldr
- %v1 = load <2 x float>, <2 x float>* %vi, align 4
+ %v1 = load <2 x float>, ptr %in, align 4
;CHECK: vstr
- store <2 x float> %v1, <2 x float>* %vo, align 4
+ store <2 x float> %v1, ptr %out, align 4
ret void
}
@@ -399,17 +311,13 @@ entry:
;ALIGN = 4
;SIZE = 128
;TYPE = <16 x i8>
-define void @v128_v16i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v128_v16i8_4(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v128_v16i8_4:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <16 x i8>*
- %vo = bitcast i8* %po to <16 x i8>*
;CHECK: vld1.32
- %v1 = load <16 x i8>, <16 x i8>* %vi, align 4
+ %v1 = load <16 x i8>, ptr %in, align 4
;CHECK: vst1.32
- store <16 x i8> %v1, <16 x i8>* %vo, align 4
+ store <16 x i8> %v1, ptr %out, align 4
ret void
}
@@ -417,17 +325,13 @@ entry:
;ALIGN = 4
;SIZE = 128
;TYPE = <8 x i16>
-define void @v128_v8i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v128_v8i16_4(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v128_v8i16_4:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <8 x i16>*
- %vo = bitcast i8* %po to <8 x i16>*
;CHECK: vld1.32
- %v1 = load <8 x i16>, <8 x i16>* %vi, align 4
+ %v1 = load <8 x i16>, ptr %in, align 4
;CHECK: vst1.32
- store <8 x i16> %v1, <8 x i16>* %vo, align 4
+ store <8 x i16> %v1, ptr %out, align 4
ret void
}
@@ -435,17 +339,13 @@ entry:
;ALIGN = 4
;SIZE = 128
;TYPE = <4 x i32>
-define void @v128_v4i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v128_v4i32_4(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v128_v4i32_4:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <4 x i32>*
- %vo = bitcast i8* %po to <4 x i32>*
;CHECK: vld1.32
- %v1 = load <4 x i32>, <4 x i32>* %vi, align 4
+ %v1 = load <4 x i32>, ptr %in, align 4
;CHECK: vst1.32
- store <4 x i32> %v1, <4 x i32>* %vo, align 4
+ store <4 x i32> %v1, ptr %out, align 4
ret void
}
@@ -453,17 +353,13 @@ entry:
;ALIGN = 4
;SIZE = 128
;TYPE = <2 x i64>
-define void @v128_v2i64_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v128_v2i64_4(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v128_v2i64_4:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <2 x i64>*
- %vo = bitcast i8* %po to <2 x i64>*
;CHECK: vld1.32
- %v1 = load <2 x i64>, <2 x i64>* %vi, align 4
+ %v1 = load <2 x i64>, ptr %in, align 4
;CHECK: vst1.32
- store <2 x i64> %v1, <2 x i64>* %vo, align 4
+ store <2 x i64> %v1, ptr %out, align 4
ret void
}
@@ -471,25 +367,21 @@ entry:
;ALIGN = 4
;SIZE = 128
;TYPE = <4 x float>
-define void @v128_v4f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
+define void @v128_v4f32_4(ptr noalias nocapture %out, ptr noalias nocapture %in) nounwind {
;CHECK-LABEL: v128_v4f32_4:
entry:
- %po = getelementptr i8, i8* %out, i32 0
- %pi = getelementptr i8, i8* %in, i32 0
- %vi = bitcast i8* %pi to <4 x float>*
- %vo = bitcast i8* %po to <4 x float>*
;CHECK: vld1.32
- %v1 = load <4 x float>, <4 x float>* %vi, align 4
+ %v1 = load <4 x float>, ptr %in, align 4
;CHECK: vst1.32
- store <4 x float> %v1, <4 x float>* %vo, align 4
+ store <4 x float> %v1, ptr %out, align 4
ret void
}
-define void @test_weird_type(<3 x double> %in, <3 x i64>* %ptr) {
+define void @test_weird_type(<3 x double> %in, ptr %ptr) {
; CHECK-LABEL: test_weird_type:
; CHECK: vst1
%vec.int = bitcast <3 x double> %in to <3 x i64>
- store <3 x i64> %vec.int, <3 x i64>* %ptr, align 8
+ store <3 x i64> %vec.int, ptr %ptr, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/unaligned_load_store_vfp.ll b/llvm/test/CodeGen/ARM/unaligned_load_store_vfp.ll
index 90d17e19c2868..748a5980b5db6 100644
--- a/llvm/test/CodeGen/ARM/unaligned_load_store_vfp.ll
+++ b/llvm/test/CodeGen/ARM/unaligned_load_store_vfp.ll
@@ -1,98 +1,98 @@
; RUN: llc -mtriple=thumbv7-linux-gnueabihf %s -o - | FileCheck %s
-define float @test_load_s32_float(i32* %addr) {
+define float @test_load_s32_float(ptr %addr) {
; CHECK-LABEL: test_load_s32_float:
; CHECK: ldr [[TMP:r[0-9]+]], [r0]
; CHECK: vmov [[RES_INT:s[0-9]+]], [[TMP]]
; CHECK: vcvt.f32.s32 s0, [[RES_INT]]
- %val = load i32, i32* %addr, align 1
+ %val = load i32, ptr %addr, align 1
%res = sitofp i32 %val to float
ret float %res
}
-define double @test_load_s32_double(i32* %addr) {
+define double @test_load_s32_double(ptr %addr) {
; CHECK-LABEL: test_load_s32_double:
; CHECK: ldr [[TMP:r[0-9]+]], [r0]
; CHECK: vmov [[RES_INT:s[0-9]+]], [[TMP]]
; CHECK: vcvt.f64.s32 d0, [[RES_INT]]
- %val = load i32, i32* %addr, align 1
+ %val = load i32, ptr %addr, align 1
%res = sitofp i32 %val to double
ret double %res
}
-define float @test_load_u32_float(i32* %addr) {
+define float @test_load_u32_float(ptr %addr) {
; CHECK-LABEL: test_load_u32_float:
; CHECK: ldr [[TMP:r[0-9]+]], [r0]
; CHECK: vmov [[RES_INT:s[0-9]+]], [[TMP]]
; CHECK: vcvt.f32.u32 s0, [[RES_INT]]
- %val = load i32, i32* %addr, align 1
+ %val = load i32, ptr %addr, align 1
%res = uitofp i32 %val to float
ret float %res
}
-define double @test_load_u32_double(i32* %addr) {
+define double @test_load_u32_double(ptr %addr) {
; CHECK-LABEL: test_load_u32_double:
; CHECK: ldr [[TMP:r[0-9]+]], [r0]
; CHECK: vmov [[RES_INT:s[0-9]+]], [[TMP]]
; CHECK: vcvt.f64.u32 d0, [[RES_INT]]
- %val = load i32, i32* %addr, align 1
+ %val = load i32, ptr %addr, align 1
%res = uitofp i32 %val to double
ret double %res
}
-define void @test_store_f32(float %in, float* %addr) {
+define void @test_store_f32(float %in, ptr %addr) {
; CHECK-LABEL: test_store_f32:
; CHECK: vmov [[TMP:r[0-9]+]], s0
; CHECK: str [[TMP]], [r0]
- store float %in, float* %addr, align 1
+ store float %in, ptr %addr, align 1
ret void
}
-define void @test_store_float_s32(float %in, i32* %addr) {
+define void @test_store_float_s32(float %in, ptr %addr) {
; CHECK-LABEL: test_store_float_s32:
; CHECK: vcvt.s32.f32 [[TMP:s[0-9]+]], s0
; CHECK: vmov [[TMP_INT:r[0-9]+]], [[TMP]]
; CHECK: str [[TMP_INT]], [r0]
%val = fptosi float %in to i32
- store i32 %val, i32* %addr, align 1
+ store i32 %val, ptr %addr, align 1
ret void
}
-define void @test_store_double_s32(double %in, i32* %addr) {
+define void @test_store_double_s32(double %in, ptr %addr) {
; CHECK-LABEL: test_store_double_s32:
; CHECK: vcvt.s32.f64 [[TMP:s[0-9]+]], d0
; CHECK: vmov [[TMP_INT:r[0-9]+]], [[TMP]]
; CHECK: str [[TMP_INT]], [r0]
%val = fptosi double %in to i32
- store i32 %val, i32* %addr, align 1
+ store i32 %val, ptr %addr, align 1
ret void
}
-define void @test_store_float_u32(float %in, i32* %addr) {
+define void @test_store_float_u32(float %in, ptr %addr) {
; CHECK-LABEL: test_store_float_u32:
; CHECK: vcvt.u32.f32 [[TMP:s[0-9]+]], s0
; CHECK: vmov [[TMP_INT:r[0-9]+]], [[TMP]]
; CHECK: str [[TMP_INT]], [r0]
%val = fptoui float %in to i32
- store i32 %val, i32* %addr, align 1
+ store i32 %val, ptr %addr, align 1
ret void
}
-define void @test_store_double_u32(double %in, i32* %addr) {
+define void @test_store_double_u32(double %in, ptr %addr) {
; CHECK-LABEL: test_store_double_u32:
; CHECK: vcvt.u32.f64 [[TMP:s[0-9]+]], d0
; CHECK: vmov [[TMP_INT:r[0-9]+]], [[TMP]]
; CHECK: str [[TMP_INT]], [r0]
%val = fptoui double %in to i32
- store i32 %val, i32* %addr, align 1
+ store i32 %val, ptr %addr, align 1
ret void
}
diff --git a/llvm/test/CodeGen/ARM/undef-sext.ll b/llvm/test/CodeGen/ARM/undef-sext.ll
index bb06bcbaf44cb..5ddc9f007f85b 100644
--- a/llvm/test/CodeGen/ARM/undef-sext.ll
+++ b/llvm/test/CodeGen/ARM/undef-sext.ll
@@ -2,13 +2,13 @@
; No need to sign-extend undef.
-define i32 @t(i32* %a) nounwind {
+define i32 @t(ptr %a) nounwind {
entry:
; CHECK-LABEL: t:
; CHECK: ldr r0, [r0]
; CHECK: bx lr
%0 = sext i16 undef to i32
- %1 = getelementptr inbounds i32, i32* %a, i32 %0
- %2 = load i32, i32* %1, align 4
+ %1 = getelementptr inbounds i32, ptr %a, i32 %0
+ %2 = load i32, ptr %1, align 4
ret i32 %2
}
diff --git a/llvm/test/CodeGen/ARM/unschedule-first-call.ll b/llvm/test/CodeGen/ARM/unschedule-first-call.ll
index 7e88afb6ae419..e0bb7873eab27 100644
--- a/llvm/test/CodeGen/ARM/unschedule-first-call.ll
+++ b/llvm/test/CodeGen/ARM/unschedule-first-call.ll
@@ -5,7 +5,7 @@ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv6kz--linux-gnueabihf"
; Function Attrs: nounwind
-define void @dradbg(i32, i32, float*, float*, float*, float*, float*) #0 {
+define void @dradbg(i32, i32, ptr, ptr, ptr, ptr, ptr) #0 {
br i1 undef, label %.critedge, label %8
.critedge: ; preds = %7
@@ -13,10 +13,10 @@ define void @dradbg(i32, i32, float*, float*, float*, float*, float*) #0 {
br label %8
; <label>:8: ; preds = %.critedge, %7
- %9 = getelementptr float, float* %3, i64 undef
- %10 = ptrtoint float* %9 to i32
+ %9 = getelementptr float, ptr %3, i64 undef
+ %10 = ptrtoint ptr %9 to i32
%11 = icmp ule i32 %10, undef
- %12 = getelementptr float, float* %5, i64 undef
+ %12 = getelementptr float, ptr %5, i64 undef
%13 = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 undef, i64 undef)
%14 = extractvalue { i64, i1 } %13, 0
%15 = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %14, i64 1)
@@ -32,9 +32,9 @@ define void @dradbg(i32, i32, float*, float*, float*, float*, float*) #0 {
%25 = extractvalue { i64, i1 } %24, 0
%26 = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %25, i64 0)
%27 = extractvalue { i64, i1 } %26, 0
- %28 = getelementptr float, float* %3, i64 %27
- %29 = ptrtoint float* %12 to i32
- %30 = ptrtoint float* %28 to i32
+ %28 = getelementptr float, ptr %3, i64 %27
+ %29 = ptrtoint ptr %12 to i32
+ %30 = ptrtoint ptr %28 to i32
%31 = icmp ule i32 %29, %30
%32 = or i1 %11, %31
%33 = and i1 false, %32
@@ -54,16 +54,16 @@ define void @dradbg(i32, i32, float*, float*, float*, float*, float*) #0 {
%47 = extractvalue { i64, i1 } %46, 0
%48 = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %47, i64 0)
%49 = extractvalue { i64, i1 } %48, 0
- %50 = getelementptr float, float* %5, i64 %49
- %51 = ptrtoint float* %50 to i32
+ %50 = getelementptr float, ptr %5, i64 %49
+ %51 = ptrtoint ptr %50 to i32
%52 = icmp ule i32 undef, %51
- %53 = getelementptr float, float* %4, i64 undef
- %54 = ptrtoint float* %53 to i32
+ %53 = getelementptr float, ptr %4, i64 undef
+ %54 = ptrtoint ptr %53 to i32
%55 = icmp ule i32 undef, %54
%56 = or i1 %52, %55
%57 = and i1 %33, %56
- %58 = getelementptr float, float* %2, i64 undef
- %59 = ptrtoint float* %58 to i32
+ %58 = getelementptr float, ptr %2, i64 undef
+ %59 = ptrtoint ptr %58 to i32
%60 = icmp ule i32 %59, undef
%61 = select i1 undef, i64 undef, i64 0
%62 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %61, i64 undef)
@@ -77,16 +77,16 @@ define void @dradbg(i32, i32, float*, float*, float*, float*, float*) #0 {
%70 = extractvalue { i64, i1 } %69, 0
%71 = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %70, i64 0)
%72 = extractvalue { i64, i1 } %71, 0
- %73 = getelementptr float, float* %5, i64 %72
- %74 = ptrtoint float* %73 to i32
+ %73 = getelementptr float, ptr %5, i64 %72
+ %74 = ptrtoint ptr %73 to i32
%75 = icmp ule i32 %74, undef
%76 = or i1 %60, %75
%77 = and i1 %57, %76
- %78 = getelementptr float, float* %6, i64 undef
- %79 = ptrtoint float* %78 to i32
+ %78 = getelementptr float, ptr %6, i64 undef
+ %79 = ptrtoint ptr %78 to i32
%80 = icmp ule i32 %79, undef
- %81 = getelementptr float, float* %5, i64 undef
- %82 = ptrtoint float* %81 to i32
+ %81 = getelementptr float, ptr %5, i64 undef
+ %82 = ptrtoint ptr %81 to i32
%83 = icmp ule i32 %82, undef
%84 = or i1 %80, %83
%85 = and i1 %77, %84
diff --git a/llvm/test/CodeGen/ARM/unwind-fp.ll b/llvm/test/CodeGen/ARM/unwind-fp.ll
index e655bbbb65913..9cf9f422c3be3 100644
--- a/llvm/test/CodeGen/ARM/unwind-fp.ll
+++ b/llvm/test/CodeGen/ARM/unwind-fp.ll
@@ -10,6 +10,6 @@ entry:
; CHECK-NEXT: vpush {[[PAD_REG:d[0-9]+]], [[SAVE_REG]]}
; CHECK: vpop {[[PAD_REG]], [[SAVE_REG]]}
%a = alloca i32, align 4
- call void asm sideeffect "", "r,~{d8}"(i32* %a)
+ call void asm sideeffect "", "r,~{d8}"(ptr %a)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/urem-opt-size.ll b/llvm/test/CodeGen/ARM/urem-opt-size.ll
index a37415d59afe2..cceca27d7bfd0 100644
--- a/llvm/test/CodeGen/ARM/urem-opt-size.ll
+++ b/llvm/test/CodeGen/ARM/urem-opt-size.ll
@@ -18,7 +18,7 @@ entry:
; CHECK-LABEL: foo1:
; CHECK:__aeabi_idiv
; CHECK-NOT: smmul
- %call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)()
+ %call = tail call i32 @GetValue()
%div = sdiv i32 %call, 1000000
ret i32 %div
}
@@ -28,7 +28,7 @@ entry:
; CHECK-LABEL: foo2:
; CHECK: __aeabi_uidiv
; CHECK-NOT: umull
- %call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)()
+ %call = tail call i32 @GetValue()
%div = udiv i32 %call, 1000000
ret i32 %div
}
@@ -43,7 +43,7 @@ entry:
; V7M: udiv [[R2:r[0-9]+]], [[R0:r[0-9]+]], [[R1:r[0-9]+]]
; V7M: mls {{r[0-9]+}}, [[R2]], [[R1]], [[R0]]
; V7M-NOT: __aeabi_uidivmod
- %call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)()
+ %call = tail call i32 @GetValue()
%rem = urem i32 %call, 1000000
%cmp = icmp eq i32 %rem, 0
%conv = zext i1 %cmp to i32
@@ -59,7 +59,7 @@ entry:
; V7M: sdiv [[R2:r[0-9]+]], [[R0:r[0-9]+]], [[R1:r[0-9]+]]
; V7M: mls {{r[0-9]+}}, [[R2]], [[R1]], [[R0]]
; V7M-NOT: __aeabi_idivmod
- %call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)()
+ %call = tail call i32 @GetValue()
%rem = srem i32 %call, 1000000
ret i32 %rem
}
@@ -76,7 +76,7 @@ entry:
; V7M-NOT: sdiv
; V7M: mls {{r[0-9]+}}, [[R2]], [[R1]], [[R0]]
; V7M-NOT: __aeabi_idivmod
- %call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)()
+ %call = tail call i32 @GetValue()
%div = sdiv i32 %call, 1000000
%rem = srem i32 %call, 1000000
%add = add i32 %div, %rem
diff --git a/llvm/test/CodeGen/ARM/useaa.ll b/llvm/test/CodeGen/ARM/useaa.ll
index 0cd4732e5e544..f8207a1056e3b 100644
--- a/llvm/test/CodeGen/ARM/useaa.ll
+++ b/llvm/test/CodeGen/ARM/useaa.ll
@@ -15,14 +15,14 @@
; USEAA: str
; USEAA: str
-define void @test(i32* nocapture %a, i32* noalias nocapture %b) {
+define void @test(ptr nocapture %a, ptr noalias nocapture %b) {
entry:
- %0 = load i32, i32* %a, align 4
+ %0 = load i32, ptr %a, align 4
%add = add nsw i32 %0, 10
- store i32 %add, i32* %a, align 4
- %1 = load i32, i32* %b, align 4
+ store i32 %add, ptr %a, align 4
+ %1 = load i32, ptr %b, align 4
%add2 = add nsw i32 %1, 20
- store i32 %add2, i32* %b, align 4
+ store i32 %add2, ptr %b, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/v7k-abi-align.ll b/llvm/test/CodeGen/ARM/v7k-abi-align.ll
index be4d876a59ecb..20c7aea5dcbe6 100644
--- a/llvm/test/CodeGen/ARM/v7k-abi-align.ll
+++ b/llvm/test/CodeGen/ARM/v7k-abi-align.ll
@@ -5,25 +5,25 @@
define i32 @test_i64_align() "frame-pointer"="all" {
; CHECK-LABEL: test_i64_align:
; CHECK: movs r0, #8
- ret i32 ptrtoint(i64* getelementptr(%struct, %struct* null, i32 0, i32 1) to i32)
+ ret i32 ptrtoint(ptr getelementptr(%struct, ptr null, i32 0, i32 1) to i32)
}
define i32 @test_f64_align() "frame-pointer"="all" {
; CHECK-LABEL: test_f64_align:
; CHECK: movs r0, #24
- ret i32 ptrtoint(double* getelementptr(%struct, %struct* null, i32 0, i32 3) to i32)
+ ret i32 ptrtoint(ptr getelementptr(%struct, ptr null, i32 0, i32 3) to i32)
}
define i32 @test_v2f32_align() "frame-pointer"="all" {
; CHECK-LABEL: test_v2f32_align:
; CHECK: movs r0, #40
- ret i32 ptrtoint(<2 x float>* getelementptr(%struct, %struct* null, i32 0, i32 5) to i32)
+ ret i32 ptrtoint(ptr getelementptr(%struct, ptr null, i32 0, i32 5) to i32)
}
define i32 @test_v4f32_align() "frame-pointer"="all" {
; CHECK-LABEL: test_v4f32_align:
; CHECK: movs r0, #64
- ret i32 ptrtoint(<4 x float>* getelementptr(%struct, %struct* null, i32 0, i32 7) to i32)
+ ret i32 ptrtoint(ptr getelementptr(%struct, ptr null, i32 0, i32 7) to i32)
}
; Key point here is than an extra register has to be saved so that the DPRs end
diff --git a/llvm/test/CodeGen/ARM/v7k-libcalls.ll b/llvm/test/CodeGen/ARM/v7k-libcalls.ll
index 8ca31ef4e6520..9783eb521b23b 100644
--- a/llvm/test/CodeGen/ARM/v7k-libcalls.ll
+++ b/llvm/test/CodeGen/ARM/v7k-libcalls.ll
@@ -7,10 +7,10 @@ entry:
; CHECK: vadd.f32
%a.addr = alloca float, align 4
%b.addr = alloca float, align 4
- store float %a, float* %a.addr, align 4
- store float %b, float* %b.addr, align 4
- %0 = load float, float* %a.addr, align 4
- %1 = load float, float* %b.addr, align 4
+ store float %a, ptr %a.addr, align 4
+ store float %b, ptr %b.addr, align 4
+ %0 = load float, ptr %a.addr, align 4
+ %1 = load float, ptr %b.addr, align 4
%add = fadd float %0, %1
ret float %add
}
@@ -22,10 +22,10 @@ entry:
; CHECK: vadd.f64
%a.addr = alloca double, align 8
%b.addr = alloca double, align 8
- store double %a, double* %a.addr, align 8
- store double %b, double* %b.addr, align 8
- %0 = load double, double* %a.addr, align 8
- %1 = load double, double* %b.addr, align 8
+ store double %a, ptr %a.addr, align 8
+ store double %b, ptr %b.addr, align 8
+ %0 = load double, ptr %a.addr, align 8
+ %1 = load double, ptr %b.addr, align 8
%add = fadd double %0, %1
ret double %add
}
diff --git a/llvm/test/CodeGen/ARM/v8m-tail-call.ll b/llvm/test/CodeGen/ARM/v8m-tail-call.ll
index c683230c3460b..4bad4ba0daf36 100644
--- a/llvm/test/CodeGen/ARM/v8m-tail-call.ll
+++ b/llvm/test/CodeGen/ARM/v8m-tail-call.ll
@@ -17,7 +17,7 @@ define hidden i32 @f0() {
; CHECK-NEXT: pop {r7}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: b h0
- %1 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
+ %1 = tail call i32 @g()
%2 = tail call i32 @h0(i32 %1, i32 1, i32 2, i32 3)
ret i32 %2
}
@@ -32,7 +32,7 @@ define hidden i32 @f1() {
; CHECK-NEXT: pop {r1}
; CHECK-NEXT: mov lr, r1
; CHECK-NEXT: b h1
- %1 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
+ %1 = tail call i32 @g()
%2 = tail call i32 @h1(i32 %1)
ret i32 %2
}
@@ -65,7 +65,7 @@ define hidden i32 @f2(i32, i32, i32, i32, i32) {
; CHECK-NEXT: mvns r0, r0
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
- %6 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
+ %6 = tail call i32 @g()
%7 = icmp eq i32 %6, 0
br i1 %7, label %10, label %8
@@ -78,7 +78,7 @@ define hidden i32 @f2(i32, i32, i32, i32, i32) {
; Make sure that tail calls to function pointers that require r0-r3 for argument
; passing do not break the compiler.
- at fnptr = global i32 (i32, i32, i32, i32)* null
+ at fnptr = global ptr null
define i32 @test3() {
; CHECK-LABEL: test3:
; CHECK: @ %bb.0:
@@ -92,12 +92,12 @@ define i32 @test3() {
; CHECK-NEXT: movs r3, #4
; CHECK-NEXT: blx r4
; CHECK-NEXT: pop {r4, pc}
- %1 = load i32 (i32, i32, i32, i32)*, i32 (i32, i32, i32, i32)** @fnptr
+ %1 = load ptr, ptr @fnptr
%2 = tail call i32 %1(i32 1, i32 2, i32 3, i32 4)
ret i32 %2
}
- at fnptr2 = global i32 (i32, i32, i64)* null
+ at fnptr2 = global ptr null
define i32 @test4() {
; CHECK-LABEL: test4:
; CHECK: @ %bb.0:
@@ -111,7 +111,7 @@ define i32 @test4() {
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: blx r4
; CHECK-NEXT: pop {r4, pc}
- %1 = load i32 (i32, i32, i64)*, i32 (i32, i32, i64)** @fnptr2
+ %1 = load ptr, ptr @fnptr2
%2 = tail call i32 %1(i32 1, i32 2, i64 3)
ret i32 %2
}
@@ -119,7 +119,7 @@ define i32 @test4() {
; Check that tail calls to function pointers where not all of r0-r3 are used for
; parameter passing are tail-call optimized.
; test5: params in r0, r1. r2 & r3 are free.
- at fnptr3 = global i32 (i32, i32)* null
+ at fnptr3 = global ptr null
define i32 @test5() {
; CHECK-LABEL: test5:
; CHECK: @ %bb.0:
@@ -129,13 +129,13 @@ define i32 @test5() {
; CHECK-NEXT: movs r0, #1
; CHECK-NEXT: movs r1, #2
; CHECK-NEXT: bx r2
- %1 = load i32 (i32, i32)*, i32 (i32, i32)** @fnptr3
+ %1 = load ptr, ptr @fnptr3
%2 = tail call i32 %1(i32 1, i32 2)
ret i32 %2
}
; test6: params in r0 and r2-r3. r1 is free.
- at fnptr4 = global i32 (i32, i64)* null
+ at fnptr4 = global ptr null
define i32 @test6() {
; CHECK-LABEL: test6:
; CHECK: @ %bb.0:
@@ -146,7 +146,7 @@ define i32 @test6() {
; CHECK-NEXT: movs r2, #2
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: bx r1
- %1 = load i32 (i32, i64)*, i32 (i32, i64)** @fnptr4
+ %1 = load ptr, ptr @fnptr4
%2 = tail call i32 %1(i32 1, i64 2)
ret i32 %2
}
@@ -171,7 +171,7 @@ declare i32 @bar(i32, i32, i32, i32)
; a stack slot.
%struct.S = type { i32 }
-define void @test8(i32 (i32, i32, i32)* nocapture %fn, i32 %x) local_unnamed_addr {
+define void @test8(ptr nocapture %fn, i32 %x) local_unnamed_addr {
; CHECK-LABEL: test8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push {r4, r5, r6, r7, lr}
@@ -200,17 +200,16 @@ define void @test8(i32 (i32, i32, i32)* nocapture %fn, i32 %x) local_unnamed_add
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: bx r3
entry:
- %call = tail call %struct.S* bitcast (%struct.S* (...)* @test8_u to %struct.S* ()*)()
- %a = getelementptr inbounds %struct.S, %struct.S* %call, i32 0, i32 0
- %0 = load i32, i32* %a, align 4
+ %call = tail call ptr @test8_u()
+ %0 = load i32, ptr %call, align 4
%call1 = tail call i32 @test8_h(i32 0)
%call2 = tail call i32 @test8_g(i32 %0, i32 %call1, i32 0)
- store i32 %x, i32* %a, align 4
+ store i32 %x, ptr %call, align 4
%call4 = tail call i32 %fn(i32 1, i32 2, i32 3)
ret void
}
-declare %struct.S* @test8_u(...)
+declare ptr @test8_u(...)
declare i32 @test8_g(i32, i32, i32)
@@ -218,7 +217,7 @@ declare i32 @test8_h(i32)
; Check that we don't introduce an unnecessary spill of lr.
declare i32 @h9(i32, i32, i32, i32)
-define i32 @test9(i32* %x, i32* %y, i32* %z, i32* %a) {
+define i32 @test9(ptr %x, ptr %y, ptr %z, ptr %a) {
; CHECK-LABEL: test9:
; CHECK: @ %bb.0:
; CHECK-NEXT: push {r4, r7}
@@ -230,12 +229,12 @@ define i32 @test9(i32* %x, i32* %y, i32* %z, i32* %a) {
; CHECK-NEXT: ldr r2, [r2]
; CHECK-NEXT: pop {r4, r7}
; CHECK-NEXT: b h9
- %zz = load i32, i32* %z
- %xx = load i32, i32* %x
- %yy = load i32, i32* %y
- %aa1 = load i32, i32* %a
- %a2 = getelementptr i32, i32* %a, i32 1
- %aa2 = load i32, i32* %a2
+ %zz = load i32, ptr %z
+ %xx = load i32, ptr %x
+ %yy = load i32, ptr %y
+ %aa1 = load i32, ptr %a
+ %a2 = getelementptr i32, ptr %a, i32 1
+ %aa2 = load i32, ptr %a2
%aa = add i32 %aa1, %aa2
%r = tail call i32 @h9(i32 %xx, i32 %yy, i32 %zz, i32 %aa)
ret i32 %r
diff --git a/llvm/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll b/llvm/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll
index eab750d2b8466..1e62f985881e0 100644
--- a/llvm/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll
+++ b/llvm/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll
@@ -8,7 +8,7 @@ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8m.base-arm-none-eabi"
@crc32_tab = external unnamed_addr global [256 x i32], align 4
- at g_566 = external global i32**, align 4
+ at g_566 = external global ptr, align 4
define void @main() {
; CHECK-LABEL: main:
@@ -52,7 +52,7 @@ define void @main() {
; CHECK-NEXT: .LBB0_7: @ %lbl_1394.i.i.i.loopexit
; CHECK-NEXT: .LBB0_8: @ %for.end476.i.i.i.loopexit
entry:
- %0 = load volatile i32**, i32*** @g_566, align 4
+ %0 = load volatile ptr, ptr @g_566, align 4
br label %func_16.exit.i.i.i
lbl_1394.i.i.i.loopexit: ; preds = %for.cond14.preheader.us.i.i.i
@@ -85,6 +85,6 @@ for.end476.i.i.i.loopexit: ; preds = %for.cond14.preheade
unreachable
func_1.exit.loopexit: ; preds = %for.cond14.preheader.us.i.i.i
- %arrayidx.i63.i.i5252 = getelementptr inbounds [256 x i32], [256 x i32]* @crc32_tab, i32 0, i32 undef
+ %arrayidx.i63.i.i5252 = getelementptr inbounds [256 x i32], ptr @crc32_tab, i32 0, i32 undef
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/va_arg.ll b/llvm/test/CodeGen/ARM/va_arg.ll
index b967a7b042a31..41556b9fa2dec 100644
--- a/llvm/test/CodeGen/ARM/va_arg.ll
+++ b/llvm/test/CodeGen/ARM/va_arg.ll
@@ -20,15 +20,14 @@ define i64 @test1(i32 %i, ...) nounwind optsize {
; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: bx lr
entry:
- %g = alloca i8*, align 4
- %g1 = bitcast i8** %g to i8*
- call void @llvm.va_start(i8* %g1)
- %0 = va_arg i8** %g, i64
- call void @llvm.va_end(i8* %g1)
+ %g = alloca ptr, align 4
+ call void @llvm.va_start(ptr %g)
+ %0 = va_arg ptr %g, i64
+ call void @llvm.va_end(ptr %g)
ret i64 %0
}
-define double @test2(i32 %a, i32* %b, ...) nounwind optsize {
+define double @test2(i32 %a, ptr %b, ...) nounwind optsize {
; CHECK-LABEL: test2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .pad #12
@@ -45,17 +44,16 @@ define double @test2(i32 %a, i32* %b, ...) nounwind optsize {
; CHECK-NEXT: add sp, sp, #12
; CHECK-NEXT: bx lr
entry:
- %ap = alloca i8*, align 4 ; <i8**> [#uses=3]
- %ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=2]
- call void @llvm.va_start(i8* %ap1)
- %0 = va_arg i8** %ap, i32 ; <i32> [#uses=0]
- store i32 %0, i32* %b
- %1 = va_arg i8** %ap, double ; <double> [#uses=1]
- call void @llvm.va_end(i8* %ap1)
+ %ap = alloca ptr, align 4 ; <ptr> [#uses=3]
+ call void @llvm.va_start(ptr %ap)
+ %0 = va_arg ptr %ap, i32 ; <i32> [#uses=0]
+ store i32 %0, ptr %b
+ %1 = va_arg ptr %ap, double ; <double> [#uses=1]
+ call void @llvm.va_end(ptr %ap)
ret double %1
}
-declare void @llvm.va_start(i8*) nounwind
+declare void @llvm.va_start(ptr) nounwind
-declare void @llvm.va_end(i8*) nounwind
+declare void @llvm.va_end(ptr) nounwind
diff --git a/llvm/test/CodeGen/ARM/vaba.ll b/llvm/test/CodeGen/ARM/vaba.ll
index 4323f31844697..e4a61ea7d91ff 100644
--- a/llvm/test/CodeGen/ARM/vaba.ll
+++ b/llvm/test/CodeGen/ARM/vaba.ll
@@ -1,132 +1,132 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+define <8 x i8> @vabas8(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabas8:
;CHECK: vaba.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = load <8 x i8>, <8 x i8>* %C
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
+ %tmp3 = load <8 x i8>, ptr %C
%tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
%tmp5 = add <8 x i8> %tmp1, %tmp4
ret <8 x i8> %tmp5
}
-define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+define <4 x i16> @vabas16(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabas16:
;CHECK: vaba.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i16>, <4 x i16>* %C
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
+ %tmp3 = load <4 x i16>, ptr %C
%tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
%tmp5 = add <4 x i16> %tmp1, %tmp4
ret <4 x i16> %tmp5
}
-define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+define <2 x i32> @vabas32(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabas32:
;CHECK: vaba.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i32>, <2 x i32>* %C
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
+ %tmp3 = load <2 x i32>, ptr %C
%tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
%tmp5 = add <2 x i32> %tmp1, %tmp4
ret <2 x i32> %tmp5
}
-define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+define <8 x i8> @vabau8(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabau8:
;CHECK: vaba.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = load <8 x i8>, <8 x i8>* %C
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
+ %tmp3 = load <8 x i8>, ptr %C
%tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
%tmp5 = add <8 x i8> %tmp1, %tmp4
ret <8 x i8> %tmp5
}
-define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+define <4 x i16> @vabau16(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabau16:
;CHECK: vaba.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i16>, <4 x i16>* %C
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
+ %tmp3 = load <4 x i16>, ptr %C
%tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
%tmp5 = add <4 x i16> %tmp1, %tmp4
ret <4 x i16> %tmp5
}
-define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+define <2 x i32> @vabau32(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabau32:
;CHECK: vaba.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i32>, <2 x i32>* %C
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
+ %tmp3 = load <2 x i32>, ptr %C
%tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
%tmp5 = add <2 x i32> %tmp1, %tmp4
ret <2 x i32> %tmp5
}
-define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
+define <16 x i8> @vabaQs8(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabaQs8:
;CHECK: vaba.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = load <16 x i8>, <16 x i8>* %C
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
+ %tmp3 = load <16 x i8>, ptr %C
%tmp4 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3)
%tmp5 = add <16 x i8> %tmp1, %tmp4
ret <16 x i8> %tmp5
}
-define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
+define <8 x i16> @vabaQs16(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabaQs16:
;CHECK: vaba.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = load <8 x i16>, <8 x i16>* %C
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
+ %tmp3 = load <8 x i16>, ptr %C
%tmp4 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3)
%tmp5 = add <8 x i16> %tmp1, %tmp4
ret <8 x i16> %tmp5
}
-define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
+define <4 x i32> @vabaQs32(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabaQs32:
;CHECK: vaba.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = load <4 x i32>, <4 x i32>* %C
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
+ %tmp3 = load <4 x i32>, ptr %C
%tmp4 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3)
%tmp5 = add <4 x i32> %tmp1, %tmp4
ret <4 x i32> %tmp5
}
-define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
+define <16 x i8> @vabaQu8(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabaQu8:
;CHECK: vaba.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = load <16 x i8>, <16 x i8>* %C
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
+ %tmp3 = load <16 x i8>, ptr %C
%tmp4 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3)
%tmp5 = add <16 x i8> %tmp1, %tmp4
ret <16 x i8> %tmp5
}
-define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
+define <8 x i16> @vabaQu16(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabaQu16:
;CHECK: vaba.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = load <8 x i16>, <8 x i16>* %C
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
+ %tmp3 = load <8 x i16>, ptr %C
%tmp4 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3)
%tmp5 = add <8 x i16> %tmp1, %tmp4
ret <8 x i16> %tmp5
}
-define <4 x i32> @vabaQu32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
+define <4 x i32> @vabaQu32(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabaQu32:
;CHECK: vaba.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = load <4 x i32>, <4 x i32>* %C
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
+ %tmp3 = load <4 x i32>, ptr %C
%tmp4 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3)
%tmp5 = add <4 x i32> %tmp1, %tmp4
ret <4 x i32> %tmp5
@@ -148,72 +148,72 @@ declare <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8>, <16 x i8>) nounwind read
declare <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+define <8 x i16> @vabals8(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabals8:
;CHECK: vabal.s8
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = load <8 x i8>, <8 x i8>* %C
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
+ %tmp3 = load <8 x i8>, ptr %C
%tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
%tmp5 = zext <8 x i8> %tmp4 to <8 x i16>
%tmp6 = add <8 x i16> %tmp1, %tmp5
ret <8 x i16> %tmp6
}
-define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+define <4 x i32> @vabals16(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabals16:
;CHECK: vabal.s16
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i16>, <4 x i16>* %C
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
+ %tmp3 = load <4 x i16>, ptr %C
%tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
%tmp5 = zext <4 x i16> %tmp4 to <4 x i32>
%tmp6 = add <4 x i32> %tmp1, %tmp5
ret <4 x i32> %tmp6
}
-define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+define <2 x i64> @vabals32(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabals32:
;CHECK: vabal.s32
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i32>, <2 x i32>* %C
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
+ %tmp3 = load <2 x i32>, ptr %C
%tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
%tmp5 = zext <2 x i32> %tmp4 to <2 x i64>
%tmp6 = add <2 x i64> %tmp1, %tmp5
ret <2 x i64> %tmp6
}
-define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+define <8 x i16> @vabalu8(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabalu8:
;CHECK: vabal.u8
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = load <8 x i8>, <8 x i8>* %C
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
+ %tmp3 = load <8 x i8>, ptr %C
%tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
%tmp5 = zext <8 x i8> %tmp4 to <8 x i16>
%tmp6 = add <8 x i16> %tmp1, %tmp5
ret <8 x i16> %tmp6
}
-define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+define <4 x i32> @vabalu16(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabalu16:
;CHECK: vabal.u16
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i16>, <4 x i16>* %C
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
+ %tmp3 = load <4 x i16>, ptr %C
%tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
%tmp5 = zext <4 x i16> %tmp4 to <4 x i32>
%tmp6 = add <4 x i32> %tmp1, %tmp5
ret <4 x i32> %tmp6
}
-define <2 x i64> @vabalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+define <2 x i64> @vabalu32(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vabalu32:
;CHECK: vabal.u32
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i32>, <2 x i32>* %C
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
+ %tmp3 = load <2 x i32>, ptr %C
%tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
%tmp5 = zext <2 x i32> %tmp4 to <2 x i64>
%tmp6 = add <2 x i64> %tmp1, %tmp5
diff --git a/llvm/test/CodeGen/ARM/vabd.ll b/llvm/test/CodeGen/ARM/vabd.ll
index 548b8a3404611..eb5eed83d4ca3 100644
--- a/llvm/test/CodeGen/ARM/vabd.ll
+++ b/llvm/test/CodeGen/ARM/vabd.ll
@@ -1,127 +1,127 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vabds8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabds8:
;CHECK: vabd.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vabds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vabds16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabds16:
;CHECK: vabd.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vabds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vabds32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabds32:
;CHECK: vabd.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <8 x i8> @vabdu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vabdu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdu8:
;CHECK: vabd.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vabdu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vabdu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdu16:
;CHECK: vabd.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vabdu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vabdu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdu32:
;CHECK: vabd.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <2 x float> @vabdf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x float> @vabdf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdf32:
;CHECK: vabd.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = call <2 x float> @llvm.arm.neon.vabds.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
ret <2 x float> %tmp3
}
-define <16 x i8> @vabdQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vabdQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdQs8:
;CHECK: vabd.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vabdQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vabdQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdQs16:
;CHECK: vabd.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vabdQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vabdQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdQs32:
;CHECK: vabd.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <16 x i8> @vabdQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vabdQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdQu8:
;CHECK: vabd.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vabdQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vabdQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdQu16:
;CHECK: vabd.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vabdQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vabdQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdQu32:
;CHECK: vabd.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <4 x float> @vabdQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x float> @vabdQf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdQf32:
;CHECK: vabd.f32
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = call <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
ret <4 x float> %tmp3
}
@@ -146,61 +146,61 @@ declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind read
declare <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float>, <4 x float>) nounwind readnone
-define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i16> @vabdls8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdls8:
;CHECK: vabdl.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
%tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
-define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i32> @vabdls16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdls16:
;CHECK: vabdl.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
%tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
-define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i64> @vabdls32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdls32:
;CHECK: vabdl.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
%tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4
}
-define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i16> @vabdlu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdlu8:
;CHECK: vabdl.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
%tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
-define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i32> @vabdlu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdlu16:
;CHECK: vabdl.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
%tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
-define <2 x i64> @vabdlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i64> @vabdlu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vabdlu32:
;CHECK: vabdl.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
%tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4
diff --git a/llvm/test/CodeGen/ARM/vabs.ll b/llvm/test/CodeGen/ARM/vabs.ll
index 4295b32d25fc7..9956b39a267ce 100644
--- a/llvm/test/CodeGen/ARM/vabs.ll
+++ b/llvm/test/CodeGen/ARM/vabs.ll
@@ -1,14 +1,14 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vabss8(ptr %A) nounwind {
;CHECK-LABEL: vabss8:
;CHECK: vabs.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1)
ret <8 x i8> %tmp2
}
-define <8 x i8> @vabss8_fold(<8 x i8>* %A) nounwind {
+define <8 x i8> @vabss8_fold(ptr %A) nounwind {
; CHECK-LABEL: vabss8_fold:
; CHECK: vldr d16, .LCPI1_0
; CHECK: .LCPI1_0:
@@ -24,10 +24,10 @@ define <8 x i8> @vabss8_fold(<8 x i8>* %A) nounwind {
ret <8 x i8> %tmp1
}
-define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vabss16(ptr %A) nounwind {
;CHECK-LABEL: vabss16:
;CHECK: vabs.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1)
ret <4 x i16> %tmp2
}
@@ -44,10 +44,10 @@ define <4 x i16> @vabss16_fold() nounwind {
ret <4 x i16> %tmp1
}
-define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vabss32(ptr %A) nounwind {
;CHECK-LABEL: vabss32:
;CHECK: vabs.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1)
ret <2 x i32> %tmp2
}
@@ -62,42 +62,42 @@ define <2 x i32> @vabss32_fold() nounwind {
ret <2 x i32> %tmp1
}
-define <2 x float> @vabsf32(<2 x float>* %A) nounwind {
+define <2 x float> @vabsf32(ptr %A) nounwind {
;CHECK-LABEL: vabsf32:
;CHECK: vabs.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %tmp1)
ret <2 x float> %tmp2
}
-define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vabsQs8(ptr %A) nounwind {
;CHECK-LABEL: vabsQs8:
;CHECK: vabs.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vabsQs16(ptr %A) nounwind {
;CHECK-LABEL: vabsQs16:
;CHECK: vabs.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vabsQs32(ptr %A) nounwind {
;CHECK-LABEL: vabsQs32:
;CHECK: vabs.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1)
ret <4 x i32> %tmp2
}
-define <4 x float> @vabsQf32(<4 x float>* %A) nounwind {
+define <4 x float> @vabsQf32(ptr %A) nounwind {
;CHECK-LABEL: vabsQf32:
;CHECK: vabs.f32
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %tmp1)
ret <4 x float> %tmp2
}
@@ -112,50 +112,50 @@ declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone
declare <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32>) nounwind readnone
declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone
-define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vqabss8(ptr %A) nounwind {
;CHECK-LABEL: vqabss8:
;CHECK: vqabs.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vqabss16(ptr %A) nounwind {
;CHECK-LABEL: vqabss16:
;CHECK: vqabs.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vqabss32(ptr %A) nounwind {
;CHECK-LABEL: vqabss32:
;CHECK: vqabs.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1)
ret <2 x i32> %tmp2
}
-define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vqabsQs8(ptr %A) nounwind {
;CHECK-LABEL: vqabsQs8:
;CHECK: vqabs.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vqabsQs16(ptr %A) nounwind {
;CHECK-LABEL: vqabsQs16:
;CHECK: vqabs.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vqabsQs32(ptr %A) nounwind {
;CHECK-LABEL: vqabsQs32:
;CHECK: vqabs.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1)
ret <4 x i32> %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/vararg_no_start.ll b/llvm/test/CodeGen/ARM/vararg_no_start.ll
index f9c8c1b754662..7c52a6704a682 100644
--- a/llvm/test/CodeGen/ARM/vararg_no_start.ll
+++ b/llvm/test/CodeGen/ARM/vararg_no_start.ll
@@ -1,10 +1,10 @@
; RUN: llc -mtriple=arm-darwin < %s | FileCheck %s
; RUN: llc -O0 -mtriple=arm-darwin < %s | FileCheck %s
-define void @foo(i8*, ...) {
+define void @foo(ptr, ...) {
ret void
}
; CHECK-LABEL: {{^_?}}foo:
; CHECK-NOT: str
; CHECK: {{bx lr|mov pc, lr}}
-declare void @llvm.va_start(i8*) nounwind
+declare void @llvm.va_start(ptr) nounwind
diff --git a/llvm/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll b/llvm/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll
index 4879d73894d6a..1dda1fed366b0 100644
--- a/llvm/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll
+++ b/llvm/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll
@@ -1,9 +1,9 @@
; RUN: llc < %s -mtriple=arm-nacl-gnueabi | FileCheck %s
-declare void @llvm.va_start(i8*)
-declare void @external_func(i8*)
+declare void @llvm.va_start(ptr)
+declare void @external_func(ptr)
- at va_list = external global i8*
+ at va_list = external global ptr
; On ARM, varargs arguments are passed in r0-r3 with the rest on the
; stack. A varargs function must therefore spill rN-r3 just below the
@@ -14,8 +14,8 @@ declare void @external_func(i8*)
; alignment.
define void @varargs_func(i32 %arg1, ...) {
- call void @llvm.va_start(i8* bitcast (i8** @va_list to i8*))
- call void @external_func(i8* bitcast (i8** @va_list to i8*))
+ call void @llvm.va_start(ptr @va_list)
+ call void @external_func(ptr @va_list)
ret void
}
; CHECK-LABEL: varargs_func:
diff --git a/llvm/test/CodeGen/ARM/vargs.ll b/llvm/test/CodeGen/ARM/vargs.ll
index 41ec03857f08f..d02ac69ad9645 100644
--- a/llvm/test/CodeGen/ARM/vargs.ll
+++ b/llvm/test/CodeGen/ARM/vargs.ll
@@ -1,13 +1,13 @@
; RUN: llc -mtriple=arm-eabi %s -o /dev/null
- at str = internal constant [43 x i8] c"Hello World %d %d %d %d %d %d %d %d %d %d\0A\00" ; <[43 x i8]*> [#uses=1]
+ at str = internal constant [43 x i8] c"Hello World %d %d %d %d %d %d %d %d %d %d\0A\00" ; <ptr> [#uses=1]
define i32 @main() {
entry:
- %tmp = call i32 (i8*, ...) @printf( i8* getelementptr ([43 x i8], [43 x i8]* @str, i32 0, i64 0), i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10 ) ; <i32> [#uses=0]
- %tmp2 = call i32 (i8*, ...) @printf( i8* getelementptr ([43 x i8], [43 x i8]* @str, i32 0, i64 0), i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1 ) ; <i32> [#uses=0]
+ %tmp = call i32 (ptr, ...) @printf( ptr @str, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10 ) ; <i32> [#uses=0]
+ %tmp2 = call i32 (ptr, ...) @printf( ptr @str, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1 ) ; <i32> [#uses=0]
ret i32 11
}
-declare i32 @printf(i8*, ...)
+declare i32 @printf(ptr, ...)
diff --git a/llvm/test/CodeGen/ARM/vargs_align.ll b/llvm/test/CodeGen/ARM/vargs_align.ll
index b86756325caed..68b6bbcdad41f 100644
--- a/llvm/test/CodeGen/ARM/vargs_align.ll
+++ b/llvm/test/CodeGen/ARM/vargs_align.ll
@@ -3,19 +3,19 @@
define i32 @f(i32 %a, ...) {
entry:
- %a_addr = alloca i32 ; <i32*> [#uses=1]
- %retval = alloca i32, align 4 ; <i32*> [#uses=2]
- %tmp = alloca i32, align 4 ; <i32*> [#uses=2]
- store i32 %a, i32* %a_addr
- store i32 0, i32* %tmp
- %tmp1 = load i32, i32* %tmp ; <i32> [#uses=1]
- store i32 %tmp1, i32* %retval
- call void @llvm.va_start(i8* null)
+ %a_addr = alloca i32 ; <ptr> [#uses=1]
+ %retval = alloca i32, align 4 ; <ptr> [#uses=2]
+ %tmp = alloca i32, align 4 ; <ptr> [#uses=2]
+ store i32 %a, ptr %a_addr
+ store i32 0, ptr %tmp
+ %tmp1 = load i32, ptr %tmp ; <i32> [#uses=1]
+ store i32 %tmp1, ptr %retval
+ call void @llvm.va_start(ptr null)
call void asm sideeffect "", "~{d8}"()
br label %return
return: ; preds = %entry
- %retval2 = load i32, i32* %retval ; <i32> [#uses=1]
+ %retval2 = load i32, ptr %retval ; <i32> [#uses=1]
ret i32 %retval2
; EABI: add sp, sp, #16
; EABI: vpop {d8}
@@ -25,4 +25,4 @@ return: ; preds = %entry
; OABI: add sp, sp, #24
}
-declare void @llvm.va_start(i8*) nounwind
+declare void @llvm.va_start(ptr) nounwind
diff --git a/llvm/test/CodeGen/ARM/vbits.ll b/llvm/test/CodeGen/ARM/vbits.ll
index 2997750ccb1a4..ac8424430cf82 100644
--- a/llvm/test/CodeGen/ARM/vbits.ll
+++ b/llvm/test/CodeGen/ARM/vbits.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a8 | FileCheck %s
-define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @v_andi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_andi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -9,13 +9,13 @@ define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vand d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = and <8 x i8> %tmp1, %tmp2
ret <8 x i8> %tmp3
}
-define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @v_andi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_andi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -23,13 +23,13 @@ define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vand d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = and <4 x i16> %tmp1, %tmp2
ret <4 x i16> %tmp3
}
-define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @v_andi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_andi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -37,13 +37,13 @@ define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: vand d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = and <2 x i32> %tmp1, %tmp2
ret <2 x i32> %tmp3
}
-define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @v_andi64(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_andi64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -51,13 +51,13 @@ define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
; CHECK-NEXT: vand d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = and <1 x i64> %tmp1, %tmp2
ret <1 x i64> %tmp3
}
-define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @v_andQi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_andQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -66,13 +66,13 @@ define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = and <16 x i8> %tmp1, %tmp2
ret <16 x i8> %tmp3
}
-define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @v_andQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_andQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -81,13 +81,13 @@ define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = and <8 x i16> %tmp1, %tmp2
ret <8 x i16> %tmp3
}
-define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @v_andQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_andQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -96,13 +96,13 @@ define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = and <4 x i32> %tmp1, %tmp2
ret <4 x i32> %tmp3
}
-define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @v_andQi64(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_andQi64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -111,13 +111,13 @@ define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = and <2 x i64> %tmp1, %tmp2
ret <2 x i64> %tmp3
}
-define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @v_bici8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_bici8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -125,14 +125,14 @@ define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vbic d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp4 = and <8 x i8> %tmp1, %tmp3
ret <8 x i8> %tmp4
}
-define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @v_bici16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_bici16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -140,14 +140,14 @@ define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vbic d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 >
%tmp4 = and <4 x i16> %tmp1, %tmp3
ret <4 x i16> %tmp4
}
-define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @v_bici32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_bici32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -155,14 +155,14 @@ define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: vbic d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 >
%tmp4 = and <2 x i32> %tmp1, %tmp3
ret <2 x i32> %tmp4
}
-define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @v_bici64(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_bici64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -170,14 +170,14 @@ define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
; CHECK-NEXT: vbic d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = xor <1 x i64> %tmp2, < i64 -1 >
%tmp4 = and <1 x i64> %tmp1, %tmp3
ret <1 x i64> %tmp4
}
-define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @v_bicQi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_bicQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -186,14 +186,14 @@ define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp4 = and <16 x i8> %tmp1, %tmp3
ret <16 x i8> %tmp4
}
-define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @v_bicQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_bicQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -202,14 +202,14 @@ define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
%tmp4 = and <8 x i16> %tmp1, %tmp3
ret <8 x i16> %tmp4
}
-define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @v_bicQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_bicQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -218,14 +218,14 @@ define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 >
%tmp4 = and <4 x i32> %tmp1, %tmp3
ret <4 x i32> %tmp4
}
-define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @v_bicQi64(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_bicQi64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -234,14 +234,14 @@ define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 >
%tmp4 = and <2 x i64> %tmp1, %tmp3
ret <2 x i64> %tmp4
}
-define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @v_eori8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_eori8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -249,13 +249,13 @@ define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: veor d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = xor <8 x i8> %tmp1, %tmp2
ret <8 x i8> %tmp3
}
-define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @v_eori16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_eori16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -263,13 +263,13 @@ define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: veor d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = xor <4 x i16> %tmp1, %tmp2
ret <4 x i16> %tmp3
}
-define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @v_eori32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_eori32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -277,13 +277,13 @@ define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: veor d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = xor <2 x i32> %tmp1, %tmp2
ret <2 x i32> %tmp3
}
-define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @v_eori64(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_eori64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -291,13 +291,13 @@ define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
; CHECK-NEXT: veor d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = xor <1 x i64> %tmp1, %tmp2
ret <1 x i64> %tmp3
}
-define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @v_eorQi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_eorQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -306,13 +306,13 @@ define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = xor <16 x i8> %tmp1, %tmp2
ret <16 x i8> %tmp3
}
-define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @v_eorQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_eorQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -321,13 +321,13 @@ define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = xor <8 x i16> %tmp1, %tmp2
ret <8 x i16> %tmp3
}
-define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @v_eorQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_eorQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -336,13 +336,13 @@ define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = xor <4 x i32> %tmp1, %tmp2
ret <4 x i32> %tmp3
}
-define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @v_eorQi64(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_eorQi64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -351,61 +351,61 @@ define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = xor <2 x i64> %tmp1, %tmp2
ret <2 x i64> %tmp3
}
-define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind {
+define <8 x i8> @v_mvni8(ptr %A) nounwind {
; CHECK-LABEL: v_mvni8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vmvn d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
ret <8 x i8> %tmp2
}
-define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind {
+define <4 x i16> @v_mvni16(ptr %A) nounwind {
; CHECK-LABEL: v_mvni16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vmvn d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 >
ret <4 x i16> %tmp2
}
-define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind {
+define <2 x i32> @v_mvni32(ptr %A) nounwind {
; CHECK-LABEL: v_mvni32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vmvn d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 >
ret <2 x i32> %tmp2
}
-define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind {
+define <1 x i64> @v_mvni64(ptr %A) nounwind {
; CHECK-LABEL: v_mvni64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vmvn d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <1 x i64>, <1 x i64>* %A
+ %tmp1 = load <1 x i64>, ptr %A
%tmp2 = xor <1 x i64> %tmp1, < i64 -1 >
ret <1 x i64> %tmp2
}
-define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind {
+define <16 x i8> @v_mvnQi8(ptr %A) nounwind {
; CHECK-LABEL: v_mvnQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -413,12 +413,12 @@ define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
ret <16 x i8> %tmp2
}
-define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind {
+define <8 x i16> @v_mvnQi16(ptr %A) nounwind {
; CHECK-LABEL: v_mvnQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -426,12 +426,12 @@ define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
ret <8 x i16> %tmp2
}
-define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind {
+define <4 x i32> @v_mvnQi32(ptr %A) nounwind {
; CHECK-LABEL: v_mvnQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -439,12 +439,12 @@ define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 >
ret <4 x i32> %tmp2
}
-define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind {
+define <2 x i64> @v_mvnQi64(ptr %A) nounwind {
; CHECK-LABEL: v_mvnQi64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -452,12 +452,12 @@ define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 >
ret <2 x i64> %tmp2
}
-define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @v_orri8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_orri8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -465,13 +465,13 @@ define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vorr d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = or <8 x i8> %tmp1, %tmp2
ret <8 x i8> %tmp3
}
-define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @v_orri16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_orri16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -479,13 +479,13 @@ define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vorr d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = or <4 x i16> %tmp1, %tmp2
ret <4 x i16> %tmp3
}
-define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @v_orri32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_orri32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -493,13 +493,13 @@ define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: vorr d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = or <2 x i32> %tmp1, %tmp2
ret <2 x i32> %tmp3
}
-define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @v_orri64(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_orri64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -507,13 +507,13 @@ define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
; CHECK-NEXT: vorr d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = or <1 x i64> %tmp1, %tmp2
ret <1 x i64> %tmp3
}
-define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @v_orrQi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_orrQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -522,13 +522,13 @@ define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = or <16 x i8> %tmp1, %tmp2
ret <16 x i8> %tmp3
}
-define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @v_orrQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_orrQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -537,13 +537,13 @@ define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = or <8 x i16> %tmp1, %tmp2
ret <8 x i16> %tmp3
}
-define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @v_orrQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_orrQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -552,13 +552,13 @@ define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = or <4 x i32> %tmp1, %tmp2
ret <4 x i32> %tmp3
}
-define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @v_orrQi64(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_orrQi64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -567,13 +567,13 @@ define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = or <2 x i64> %tmp1, %tmp2
ret <2 x i64> %tmp3
}
-define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @v_orni8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_orni8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -581,14 +581,14 @@ define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vorn d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp4 = or <8 x i8> %tmp1, %tmp3
ret <8 x i8> %tmp4
}
-define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @v_orni16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_orni16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -596,14 +596,14 @@ define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vorn d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 >
%tmp4 = or <4 x i16> %tmp1, %tmp3
ret <4 x i16> %tmp4
}
-define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @v_orni32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_orni32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -611,14 +611,14 @@ define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: vorn d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 >
%tmp4 = or <2 x i32> %tmp1, %tmp3
ret <2 x i32> %tmp4
}
-define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @v_orni64(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_orni64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -626,14 +626,14 @@ define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
; CHECK-NEXT: vorn d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = xor <1 x i64> %tmp2, < i64 -1 >
%tmp4 = or <1 x i64> %tmp1, %tmp3
ret <1 x i64> %tmp4
}
-define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @v_ornQi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_ornQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -642,14 +642,14 @@ define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp4 = or <16 x i8> %tmp1, %tmp3
ret <16 x i8> %tmp4
}
-define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @v_ornQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_ornQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -658,14 +658,14 @@ define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
%tmp4 = or <8 x i16> %tmp1, %tmp3
ret <8 x i16> %tmp4
}
-define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @v_ornQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_ornQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -674,14 +674,14 @@ define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 >
%tmp4 = or <4 x i32> %tmp1, %tmp3
ret <4 x i32> %tmp4
}
-define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @v_ornQi64(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: v_ornQi64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -690,14 +690,14 @@ define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 >
%tmp4 = or <2 x i64> %tmp1, %tmp3
ret <2 x i64> %tmp4
}
-define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vtsti8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtsti8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -705,15 +705,15 @@ define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vtst.8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = and <8 x i8> %tmp1, %tmp2
%tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
%tmp5 = sext <8 x i1> %tmp4 to <8 x i8>
ret <8 x i8> %tmp5
}
-define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vtsti16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtsti16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -721,15 +721,15 @@ define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vtst.16 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = and <4 x i16> %tmp1, %tmp2
%tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer
%tmp5 = sext <4 x i1> %tmp4 to <4 x i16>
ret <4 x i16> %tmp5
}
-define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vtsti32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtsti32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -737,15 +737,15 @@ define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: vtst.32 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = and <2 x i32> %tmp1, %tmp2
%tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer
%tmp5 = sext <2 x i1> %tmp4 to <2 x i32>
ret <2 x i32> %tmp5
}
-define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vtstQi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtstQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -754,15 +754,15 @@ define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = and <16 x i8> %tmp1, %tmp2
%tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer
%tmp5 = sext <16 x i1> %tmp4 to <16 x i8>
ret <16 x i8> %tmp5
}
-define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vtstQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtstQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -771,15 +771,15 @@ define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = and <8 x i16> %tmp1, %tmp2
%tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer
%tmp5 = sext <8 x i1> %tmp4 to <8 x i16>
ret <8 x i16> %tmp5
}
-define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vtstQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtstQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -788,27 +788,27 @@ define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = and <4 x i32> %tmp1, %tmp2
%tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer
%tmp5 = sext <4 x i1> %tmp4 to <4 x i32>
ret <4 x i32> %tmp5
}
-define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind {
+define <8 x i8> @v_orrimm(ptr %A) nounwind {
; CHECK-LABEL: v_orrimm:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vorr.i32 d16, #0x1000000
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
ret <8 x i8> %tmp3
}
-define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind {
+define <16 x i8> @v_orrimmQ(ptr %A) nounwind {
; CHECK-LABEL: v_orrimmQ:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -816,24 +816,24 @@ define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
ret <16 x i8> %tmp3
}
-define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
+define <8 x i8> @v_bicimm(ptr %A) nounwind {
; CHECK-LABEL: v_bicimm:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vbic.i32 d16, #0xff000000
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
ret <8 x i8> %tmp3
}
-define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
+define <16 x i8> @v_bicimmQ(ptr %A) nounwind {
; CHECK-LABEL: v_bicimmQ:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -841,7 +841,7 @@ define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
ret <16 x i8> %tmp3
}
diff --git a/llvm/test/CodeGen/ARM/vbsl-constant.ll b/llvm/test/CodeGen/ARM/vbsl-constant.ll
index 392bea1f19335..8ec5f3f3ff820 100644
--- a/llvm/test/CodeGen/ARM/vbsl-constant.ll
+++ b/llvm/test/CodeGen/ARM/vbsl-constant.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+neon | FileCheck %s
-define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+define <8 x i8> @v_bsli8(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bsli8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 d16, #0x3
@@ -10,16 +10,16 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
; CHECK-NEXT: vbsl d16, d18, d17
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = load <8 x i8>, <8 x i8>* %C
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
+ %tmp3 = load <8 x i8>, ptr %C
%tmp4 = and <8 x i8> %tmp1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
%tmp6 = and <8 x i8> %tmp3, <i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4>
%tmp7 = or <8 x i8> %tmp4, %tmp6
ret <8 x i8> %tmp7
}
-define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+define <4 x i16> @v_bsli16(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bsli16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 d16, #0x3
@@ -28,16 +28,16 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
; CHECK-NEXT: vbsl d16, d18, d17
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i16>, <4 x i16>* %C
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
+ %tmp3 = load <4 x i16>, ptr %C
%tmp4 = and <4 x i16> %tmp1, <i16 3, i16 3, i16 3, i16 3>
%tmp6 = and <4 x i16> %tmp3, <i16 -4, i16 -4, i16 -4, i16 -4>
%tmp7 = or <4 x i16> %tmp4, %tmp6
ret <4 x i16> %tmp7
}
-define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+define <2 x i32> @v_bsli32(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bsli32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d16, #0x3
@@ -46,16 +46,16 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
; CHECK-NEXT: vbsl d16, d18, d17
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i32>, <2 x i32>* %C
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
+ %tmp3 = load <2 x i32>, ptr %C
%tmp4 = and <2 x i32> %tmp1, <i32 3, i32 3>
%tmp6 = and <2 x i32> %tmp3, <i32 -4, i32 -4>
%tmp7 = or <2 x i32> %tmp4, %tmp6
ret <2 x i32> %tmp7
}
-define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
+define <1 x i64> @v_bsli64(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bsli64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [r2]
@@ -64,16 +64,16 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind
; CHECK-NEXT: vbsl d16, d18, d17
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
- %tmp3 = load <1 x i64>, <1 x i64>* %C
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
+ %tmp3 = load <1 x i64>, ptr %C
%tmp4 = and <1 x i64> %tmp1, <i64 3>
%tmp6 = and <1 x i64> %tmp3, <i64 -4>
%tmp7 = or <1 x i64> %tmp4, %tmp6
ret <1 x i64> %tmp7
}
-define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
+define <16 x i8> @v_bslQi8(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bslQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.32 {d16, d17}, [r2]
@@ -83,16 +83,16 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = load <16 x i8>, <16 x i8>* %C
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
+ %tmp3 = load <16 x i8>, ptr %C
%tmp4 = and <16 x i8> %tmp1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
%tmp6 = and <16 x i8> %tmp3, <i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4>
%tmp7 = or <16 x i8> %tmp4, %tmp6
ret <16 x i8> %tmp7
}
-define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
+define <8 x i16> @v_bslQi16(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bslQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.32 {d16, d17}, [r2]
@@ -102,16 +102,16 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwin
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = load <8 x i16>, <8 x i16>* %C
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
+ %tmp3 = load <8 x i16>, ptr %C
%tmp4 = and <8 x i16> %tmp1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
%tmp6 = and <8 x i16> %tmp3, <i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4>
%tmp7 = or <8 x i16> %tmp4, %tmp6
ret <8 x i16> %tmp7
}
-define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
+define <4 x i32> @v_bslQi32(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bslQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.32 {d16, d17}, [r2]
@@ -121,16 +121,16 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwin
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = load <4 x i32>, <4 x i32>* %C
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
+ %tmp3 = load <4 x i32>, ptr %C
%tmp4 = and <4 x i32> %tmp1, <i32 3, i32 3, i32 3, i32 3>
%tmp6 = and <4 x i32> %tmp3, <i32 -4, i32 -4, i32 -4, i32 -4>
%tmp7 = or <4 x i32> %tmp4, %tmp6
ret <4 x i32> %tmp7
}
-define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
+define <2 x i64> @v_bslQi64(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bslQi64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.32 {d16, d17}, [r2]
@@ -141,9 +141,9 @@ define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwin
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
- %tmp3 = load <2 x i64>, <2 x i64>* %C
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
+ %tmp3 = load <2 x i64>, ptr %C
%tmp4 = and <2 x i64> %tmp1, <i64 3, i64 3>
%tmp6 = and <2 x i64> %tmp3, <i64 -4, i64 -4>
%tmp7 = or <2 x i64> %tmp4, %tmp6
diff --git a/llvm/test/CodeGen/ARM/vbsl.ll b/llvm/test/CodeGen/ARM/vbsl.ll
index b43c709c99848..735fa5182fe75 100644
--- a/llvm/test/CodeGen/ARM/vbsl.ll
+++ b/llvm/test/CodeGen/ARM/vbsl.ll
@@ -3,7 +3,7 @@
; rdar://12471808
-define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+define <8 x i8> @v_bsli8(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bsli8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d18, [r0]
@@ -12,9 +12,9 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
; CHECK-NEXT: vbit d16, d17, d18
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = load <8 x i8>, <8 x i8>* %C
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
+ %tmp3 = load <8 x i8>, ptr %C
%tmp4 = and <8 x i8> %tmp1, %tmp2
%tmp5 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp6 = and <8 x i8> %tmp5, %tmp3
@@ -22,7 +22,7 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
ret <8 x i8> %tmp7
}
-define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+define <4 x i16> @v_bsli16(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bsli16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d18, [r0]
@@ -31,9 +31,9 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
; CHECK-NEXT: vbit d16, d17, d18
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i16>, <4 x i16>* %C
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
+ %tmp3 = load <4 x i16>, ptr %C
%tmp4 = and <4 x i16> %tmp1, %tmp2
%tmp5 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 >
%tmp6 = and <4 x i16> %tmp5, %tmp3
@@ -41,7 +41,7 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
ret <4 x i16> %tmp7
}
-define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+define <2 x i32> @v_bsli32(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bsli32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d18, [r0]
@@ -50,9 +50,9 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
; CHECK-NEXT: vbit d16, d17, d18
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i32>, <2 x i32>* %C
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
+ %tmp3 = load <2 x i32>, ptr %C
%tmp4 = and <2 x i32> %tmp1, %tmp2
%tmp5 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 >
%tmp6 = and <2 x i32> %tmp5, %tmp3
@@ -60,7 +60,7 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
ret <2 x i32> %tmp7
}
-define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
+define <1 x i64> @v_bsli64(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bsli64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d18, [r0]
@@ -69,9 +69,9 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind
; CHECK-NEXT: vbit d16, d17, d18
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
- %tmp3 = load <1 x i64>, <1 x i64>* %C
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
+ %tmp3 = load <1 x i64>, ptr %C
%tmp4 = and <1 x i64> %tmp1, %tmp2
%tmp5 = xor <1 x i64> %tmp1, < i64 -1 >
%tmp6 = and <1 x i64> %tmp5, %tmp3
@@ -79,7 +79,7 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind
ret <1 x i64> %tmp7
}
-define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
+define <16 x i8> @v_bslQi8(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bslQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
@@ -89,9 +89,9 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
- %tmp3 = load <16 x i8>, <16 x i8>* %C
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
+ %tmp3 = load <16 x i8>, ptr %C
%tmp4 = and <16 x i8> %tmp1, %tmp2
%tmp5 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp6 = and <16 x i8> %tmp5, %tmp3
@@ -99,7 +99,7 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
ret <16 x i8> %tmp7
}
-define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
+define <8 x i16> @v_bslQi16(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bslQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
@@ -109,9 +109,9 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwin
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
- %tmp3 = load <8 x i16>, <8 x i16>* %C
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
+ %tmp3 = load <8 x i16>, ptr %C
%tmp4 = and <8 x i16> %tmp1, %tmp2
%tmp5 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
%tmp6 = and <8 x i16> %tmp5, %tmp3
@@ -119,7 +119,7 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwin
ret <8 x i16> %tmp7
}
-define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
+define <4 x i32> @v_bslQi32(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bslQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
@@ -129,9 +129,9 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwin
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
- %tmp3 = load <4 x i32>, <4 x i32>* %C
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
+ %tmp3 = load <4 x i32>, ptr %C
%tmp4 = and <4 x i32> %tmp1, %tmp2
%tmp5 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 >
%tmp6 = and <4 x i32> %tmp5, %tmp3
@@ -139,7 +139,7 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwin
ret <4 x i32> %tmp7
}
-define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
+define <2 x i64> @v_bslQi64(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bslQi64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
@@ -149,9 +149,9 @@ define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwin
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
- %tmp3 = load <2 x i64>, <2 x i64>* %C
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
+ %tmp3 = load <2 x i64>, ptr %C
%tmp4 = and <2 x i64> %tmp1, %tmp2
%tmp5 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 >
%tmp6 = and <2 x i64> %tmp5, %tmp3
diff --git a/llvm/test/CodeGen/ARM/vceq.ll b/llvm/test/CodeGen/ARM/vceq.ll
index 70e8b7c841ddf..73f5edf2b58e2 100644
--- a/llvm/test/CodeGen/ARM/vceq.ll
+++ b/llvm/test/CodeGen/ARM/vceq.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon | FileCheck %s
-define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vceqi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vceqi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -9,14 +9,14 @@ define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vceq.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = icmp eq <8 x i8> %tmp1, %tmp2
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
-define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vceqi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vceqi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -24,14 +24,14 @@ define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vceq.i16 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = icmp eq <4 x i16> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
-define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vceqi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vceqi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -39,14 +39,14 @@ define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: vceq.i32 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = icmp eq <2 x i32> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
-define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vceqf32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vceqf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -54,14 +54,14 @@ define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
; CHECK-NEXT: vceq.f32 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = fcmp oeq <2 x float> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
-define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vceqQi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vceqQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -70,14 +70,14 @@ define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = icmp eq <16 x i8> %tmp1, %tmp2
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
-define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vceqQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vceqQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -86,14 +86,14 @@ define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = icmp eq <8 x i16> %tmp1, %tmp2
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
-define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vceqQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vceqQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -102,14 +102,14 @@ define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = icmp eq <4 x i32> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
-define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x i32> @vceqQf32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vceqQf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -118,21 +118,21 @@ define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = fcmp oeq <4 x float> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
-define <8 x i8> @vceqi8Z(<8 x i8>* %A) nounwind {
+define <8 x i8> @vceqi8Z(ptr %A) nounwind {
; CHECK-LABEL: vceqi8Z:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vceq.i8 d16, d16, #0
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp3 = icmp eq <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
diff --git a/llvm/test/CodeGen/ARM/vcge.ll b/llvm/test/CodeGen/ARM/vcge.ll
index ece96f61cbf6a..a327a90894c21 100644
--- a/llvm/test/CodeGen/ARM/vcge.ll
+++ b/llvm/test/CodeGen/ARM/vcge.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon | FileCheck %s
-define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vcges8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcges8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -9,14 +9,14 @@ define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vcge.s8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = icmp sge <8 x i8> %tmp1, %tmp2
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
-define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vcges16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcges16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -24,14 +24,14 @@ define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vcge.s16 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = icmp sge <4 x i16> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
-define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vcges32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcges32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -39,14 +39,14 @@ define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: vcge.s32 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = icmp sge <2 x i32> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
-define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vcgeu8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcgeu8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -54,14 +54,14 @@ define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vcge.u8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = icmp uge <8 x i8> %tmp1, %tmp2
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
-define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vcgeu16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcgeu16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -69,14 +69,14 @@ define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vcge.u16 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = icmp uge <4 x i16> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
-define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vcgeu32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcgeu32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -84,14 +84,14 @@ define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: vcge.u32 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = icmp uge <2 x i32> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
-define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vcgef32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcgef32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -99,14 +99,14 @@ define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
; CHECK-NEXT: vcge.f32 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = fcmp oge <2 x float> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
-define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vcgeQs8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcgeQs8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -115,14 +115,14 @@ define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = icmp sge <16 x i8> %tmp1, %tmp2
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
-define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vcgeQs16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcgeQs16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -131,14 +131,14 @@ define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = icmp sge <8 x i16> %tmp1, %tmp2
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
-define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vcgeQs32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcgeQs32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -147,14 +147,14 @@ define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = icmp sge <4 x i32> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
-define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vcgeQu8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcgeQu8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -163,14 +163,14 @@ define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = icmp uge <16 x i8> %tmp1, %tmp2
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
-define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vcgeQu16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcgeQu16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -179,14 +179,14 @@ define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = icmp uge <8 x i16> %tmp1, %tmp2
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
-define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vcgeQu32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcgeQu32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -195,14 +195,14 @@ define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = icmp uge <4 x i32> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
-define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x i32> @vcgeQf32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcgeQf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -211,14 +211,14 @@ define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = fcmp oge <4 x float> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
-define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vacgef32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vacgef32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -226,13 +226,13 @@ define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
; CHECK-NEXT: vacge.f32 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
ret <2 x i32> %tmp3
}
-define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x i32> @vacgeQf32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vacgeQf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -241,8 +241,8 @@ define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
ret <4 x i32> %tmp3
}
@@ -250,27 +250,27 @@ define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
declare <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone
declare <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
-define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind {
+define <8 x i8> @vcgei8Z(ptr %A) nounwind {
; CHECK-LABEL: vcgei8Z:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vcge.s8 d16, d16, #0
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp3 = icmp sge <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
-define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind {
+define <8 x i8> @vclei8Z(ptr %A) nounwind {
; CHECK-LABEL: vclei8Z:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vcle.s8 d16, d16, #0
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp3 = icmp sle <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
@@ -279,7 +279,7 @@ define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind {
; Radar 8782191
; Floating-point comparisons against zero produce results with integer
; elements, not floating-point elements.
-define void @test_vclez_fp(<4 x float>* %A) nounwind optsize {
+define void @test_vclez_fp(ptr %A) nounwind optsize {
; CHECK-LABEL: test_vclez_fp:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -290,15 +290,15 @@ define void @test_vclez_fp(<4 x float>* %A) nounwind optsize {
; CHECK-NEXT: vadd.i8 d16, d16, d17
; CHECK-NEXT: vst1.8 {d16}, [r0]
entry:
- %ld = load <4 x float>, <4 x float>* %A
+ %ld = load <4 x float>, ptr %A
%0 = fcmp ole <4 x float> %ld, zeroinitializer
%1 = sext <4 x i1> %0 to <4 x i16>
%2 = add <4 x i16> %1, zeroinitializer
%3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%4 = add <8 x i16> %3, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
%5 = trunc <8 x i16> %4 to <8 x i8>
- tail call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* undef, <8 x i8> %5, i32 1)
+ tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr undef, <8 x i8> %5, i32 1)
unreachable
}
-declare void @llvm.arm.neon.vst1.p0i8.v8i8(i8*, <8 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v8i8(ptr, <8 x i8>, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/vcgt.ll b/llvm/test/CodeGen/ARM/vcgt.ll
index 81cecb5fa29c1..da169a7a1c125 100644
--- a/llvm/test/CodeGen/ARM/vcgt.ll
+++ b/llvm/test/CodeGen/ARM/vcgt.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon | FileCheck %s --check-prefixes=CHECK,ALLOC
; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon -regalloc=basic | FileCheck %s --check-prefixes=CHECK,BASIC
-define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vcgts8(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vcgts8:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vldr d16, [r1]
@@ -18,14 +18,14 @@ define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; BASIC-NEXT: vcgt.s8 d16, d16, d17
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = icmp sgt <8 x i8> %tmp1, %tmp2
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
-define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vcgts16(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vcgts16:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vldr d16, [r1]
@@ -41,14 +41,14 @@ define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; BASIC-NEXT: vcgt.s16 d16, d16, d17
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = icmp sgt <4 x i16> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
-define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vcgts32(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vcgts32:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vldr d16, [r1]
@@ -64,14 +64,14 @@ define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; BASIC-NEXT: vcgt.s32 d16, d16, d17
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = icmp sgt <2 x i32> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
-define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vcgtu8(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vcgtu8:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vldr d16, [r1]
@@ -87,14 +87,14 @@ define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; BASIC-NEXT: vcgt.u8 d16, d16, d17
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = icmp ugt <8 x i8> %tmp1, %tmp2
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
-define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vcgtu16(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vcgtu16:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vldr d16, [r1]
@@ -110,14 +110,14 @@ define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; BASIC-NEXT: vcgt.u16 d16, d16, d17
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = icmp ugt <4 x i16> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
-define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vcgtu32(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vcgtu32:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vldr d16, [r1]
@@ -133,14 +133,14 @@ define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; BASIC-NEXT: vcgt.u32 d16, d16, d17
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = icmp ugt <2 x i32> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
-define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vcgtf32(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vcgtf32:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vldr d16, [r1]
@@ -156,14 +156,14 @@ define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
; BASIC-NEXT: vcgt.f32 d16, d16, d17
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = fcmp ogt <2 x float> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
-define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vcgtQs8(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vcgtQs8:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
@@ -181,14 +181,14 @@ define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: vmov r2, r3, d17
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = icmp sgt <16 x i8> %tmp1, %tmp2
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
-define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vcgtQs16(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vcgtQs16:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
@@ -206,14 +206,14 @@ define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: vmov r2, r3, d17
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = icmp sgt <8 x i16> %tmp1, %tmp2
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
-define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vcgtQs32(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vcgtQs32:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
@@ -231,14 +231,14 @@ define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: vmov r2, r3, d17
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = icmp sgt <4 x i32> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
-define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vcgtQu8(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vcgtQu8:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
@@ -256,14 +256,14 @@ define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: vmov r2, r3, d17
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = icmp ugt <16 x i8> %tmp1, %tmp2
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
-define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vcgtQu16(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vcgtQu16:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
@@ -281,14 +281,14 @@ define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: vmov r2, r3, d17
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = icmp ugt <8 x i16> %tmp1, %tmp2
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
-define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vcgtQu32(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vcgtQu32:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
@@ -306,14 +306,14 @@ define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: vmov r2, r3, d17
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = icmp ugt <4 x i32> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
-define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x i32> @vcgtQf32(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vcgtQf32:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
@@ -331,14 +331,14 @@ define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: vmov r2, r3, d17
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
-define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vacgtf32(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vacgtf32:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vldr d16, [r1]
@@ -354,13 +354,13 @@ define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
; BASIC-NEXT: vacgt.f32 d16, d16, d17
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
ret <2 x i32> %tmp3
}
-define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x i32> @vacgtQf32(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vacgtQf32:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
@@ -378,14 +378,14 @@ define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: vmov r2, r3, d17
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
ret <4 x i32> %tmp3
}
; rdar://7923010
-define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x i32> @vcgt_zext(ptr %A, ptr %B) nounwind {
; ALLOC-LABEL: vcgt_zext:
; ALLOC: @ %bb.0:
; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]
@@ -407,8 +407,8 @@ define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind {
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: vmov r2, r3, d17
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2
%tmp4 = zext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
@@ -417,27 +417,27 @@ define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind {
declare <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone
declare <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
-define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind {
+define <8 x i8> @vcgti8Z(ptr %A) nounwind {
; CHECK-LABEL: vcgti8Z:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vcgt.s8 d16, d16, #0
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp3 = icmp sgt <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
-define <8 x i8> @vclti8Z(<8 x i8>* %A) nounwind {
+define <8 x i8> @vclti8Z(ptr %A) nounwind {
; CHECK-LABEL: vclti8Z:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vclt.s8 d16, d16, #0
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp3 = icmp slt <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
diff --git a/llvm/test/CodeGen/ARM/vcnt.ll b/llvm/test/CodeGen/ARM/vcnt.ll
index 6d9667bda6f3e..baf17cc16b6f1 100644
--- a/llvm/test/CodeGen/ARM/vcnt.ll
+++ b/llvm/test/CodeGen/ARM/vcnt.ll
@@ -1,18 +1,18 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
; NB: this tests vcnt, vclz, and vcls
-define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vcnt8(ptr %A) nounwind {
;CHECK-LABEL: vcnt8:
;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)
ret <8 x i8> %tmp2
}
-define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vcntQ8(ptr %A) nounwind {
;CHECK-LABEL: vcntQ8:
;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)
ret <16 x i8> %tmp2
}
@@ -20,126 +20,126 @@ define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
declare <8 x i8> @llvm.ctpop.v8i8(<8 x i8>) nounwind readnone
declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone
-define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vclz8(ptr %A) nounwind {
;CHECK-LABEL: vclz8:
;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vclz16(ptr %A) nounwind {
;CHECK-LABEL: vclz16:
;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vclz32(ptr %A) nounwind {
;CHECK-LABEL: vclz32:
;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
ret <2 x i32> %tmp2
}
-define <1 x i64> @vclz64(<1 x i64>* %A) nounwind {
+define <1 x i64> @vclz64(ptr %A) nounwind {
;CHECK-LABEL: vclz64:
- %tmp1 = load <1 x i64>, <1 x i64>* %A
+ %tmp1 = load <1 x i64>, ptr %A
%tmp2 = call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %tmp1, i1 0)
ret <1 x i64> %tmp2
}
-define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vclzQ8(ptr %A) nounwind {
;CHECK-LABEL: vclzQ8:
;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vclzQ16(ptr %A) nounwind {
;CHECK-LABEL: vclzQ16:
;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vclzQ32(ptr %A) nounwind {
;CHECK-LABEL: vclzQ32:
;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
ret <4 x i32> %tmp2
}
-define <2 x i64> @vclzQ64(<2 x i64>* %A) nounwind {
+define <2 x i64> @vclzQ64(ptr %A) nounwind {
;CHECK-LABEL: vclzQ64:
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %tmp1, i1 0)
ret <2 x i64> %tmp2
}
-define <8 x i8> @vclz8b(<8 x i8>* %A) nounwind {
+define <8 x i8> @vclz8b(ptr %A) nounwind {
;CHECK-LABEL: vclz8b:
;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 1)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vclz16b(<4 x i16>* %A) nounwind {
+define <4 x i16> @vclz16b(ptr %A) nounwind {
;CHECK-LABEL: vclz16b:
;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 1)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vclz32b(<2 x i32>* %A) nounwind {
+define <2 x i32> @vclz32b(ptr %A) nounwind {
;CHECK-LABEL: vclz32b:
;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 1)
ret <2 x i32> %tmp2
}
-define <1 x i64> @vclz64b(<1 x i64>* %A) nounwind {
+define <1 x i64> @vclz64b(ptr %A) nounwind {
;CHECK-LABEL: vclz64b:
- %tmp1 = load <1 x i64>, <1 x i64>* %A
+ %tmp1 = load <1 x i64>, ptr %A
%tmp2 = call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %tmp1, i1 1)
ret <1 x i64> %tmp2
}
-define <16 x i8> @vclzQ8b(<16 x i8>* %A) nounwind {
+define <16 x i8> @vclzQ8b(ptr %A) nounwind {
;CHECK-LABEL: vclzQ8b:
;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 1)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vclzQ16b(<8 x i16>* %A) nounwind {
+define <8 x i16> @vclzQ16b(ptr %A) nounwind {
;CHECK-LABEL: vclzQ16b:
;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 1)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vclzQ32b(<4 x i32>* %A) nounwind {
+define <4 x i32> @vclzQ32b(ptr %A) nounwind {
;CHECK-LABEL: vclzQ32b:
;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 1)
ret <4 x i32> %tmp2
}
-define <2 x i64> @vclzQ64b(<2 x i64>* %A) nounwind {
+define <2 x i64> @vclzQ64b(ptr %A) nounwind {
;CHECK-LABEL: vclzQ64b:
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %tmp1, i1 1)
ret <2 x i64> %tmp2
}
@@ -154,50 +154,50 @@ declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone
-define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vclss8(ptr %A) nounwind {
;CHECK-LABEL: vclss8:
;CHECK: vcls.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vclss16(ptr %A) nounwind {
;CHECK-LABEL: vclss16:
;CHECK: vcls.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vclss32(ptr %A) nounwind {
;CHECK-LABEL: vclss32:
;CHECK: vcls.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
ret <2 x i32> %tmp2
}
-define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vclsQs8(ptr %A) nounwind {
;CHECK-LABEL: vclsQs8:
;CHECK: vcls.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vclsQs16(ptr %A) nounwind {
;CHECK-LABEL: vclsQs16:
;CHECK: vcls.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vclsQs32(ptr %A) nounwind {
;CHECK-LABEL: vclsQs32:
;CHECK: vcls.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
ret <4 x i32> %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/vcombine.ll b/llvm/test/CodeGen/ARM/vcombine.ll
index de234b6879eea..3871f8ceddce9 100644
--- a/llvm/test/CodeGen/ARM/vcombine.ll
+++ b/llvm/test/CodeGen/ARM/vcombine.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
; RUN: llc -mtriple=armeb-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
-define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <16 x i8> @vcombine8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcombine8
; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
@@ -11,13 +11,13 @@ define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-BE-DAG: vmov r1, r0, d16
; CHECK-BE-DAG: vmov r3, r2, d17
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %tmp3
}
-define <8 x i16> @vcombine16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <8 x i16> @vcombine16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcombine16
; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
@@ -27,13 +27,13 @@ define <8 x i16> @vcombine16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-BE-DAG: vmov r1, r0, d16
; CHECK-BE-DAG: vmov r3, r2, d17
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %tmp3
}
-define <4 x i32> @vcombine32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <4 x i32> @vcombine32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcombine32
; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
@@ -44,13 +44,13 @@ define <4 x i32> @vcombine32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-BE: vmov r1, r0, d16
; CHECK-BE: vmov r3, r2, d17
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x i32> %tmp3
}
-define <4 x float> @vcombinefloat(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <4 x float> @vcombinefloat(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcombinefloat
; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
@@ -61,13 +61,13 @@ define <4 x float> @vcombinefloat(<2 x float>* %A, <2 x float>* %B) nounwind {
; CHECK-BE: vmov r1, r0, d16
; CHECK-BE: vmov r3, r2, d17
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x float> %tmp3
}
-define <2 x i64> @vcombine64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <2 x i64> @vcombine64(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vcombine64
; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
@@ -77,8 +77,8 @@ define <2 x i64> @vcombine64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
; CHECK-BE: vmov r3, r2, [[LD1]]
; CHECK-BE: vmov r1, r0, [[LD0]]
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = shufflevector <1 x i64> %tmp1, <1 x i64> %tmp2, <2 x i32> <i32 0, i32 1>
ret <2 x i64> %tmp3
}
@@ -86,40 +86,40 @@ define <2 x i64> @vcombine64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
; Check for vget_low and vget_high implemented with shufflevector. PR8411.
; They should not require storing to the stack.
-define <4 x i16> @vget_low16(<8 x i16>* %A) nounwind {
+define <4 x i16> @vget_low16(ptr %A) nounwind {
; CHECK: vget_low16
; CHECK-NOT: vst
; CHECK-LE: vmov r0, r1, d16
; CHECK-BE: vmov r1, r0, d16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x i16> %tmp2
}
-define <8 x i8> @vget_high8(<16 x i8>* %A) nounwind {
+define <8 x i8> @vget_high8(ptr %A) nounwind {
; CHECK: vget_high8
; CHECK-NOT: vst
; CHECK-LE-NOT: vld1.64 {d16, d17}, [r0]
; CHECK-LE: vldr d16, [r0, #8]
; CHECK-LE: vmov r0, r1, d16
; CHECK-BE: vmov r1, r0, d16
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <8 x i8> %tmp2
}
; vcombine(vld1_dup(p), vld1_dup(p2))
-define <8 x i16> @vcombine_vdup(<8 x i16> %src, i16* nocapture readonly %p) {
+define <8 x i16> @vcombine_vdup(<8 x i16> %src, ptr nocapture readonly %p) {
; CHECK-LABEL: vcombine_vdup:
; CHECK: vld1.16 {d16[]},
; CHECK: vld1.16 {d17[]},
; CHECK-LE: vmov r0, r1, d16
; CHECK-LE: vmov r2, r3, d17
- %a1 = load i16, i16* %p, align 2
+ %a1 = load i16, ptr %p, align 2
%a2 = insertelement <4 x i16> undef, i16 %a1, i32 0
%a3 = shufflevector <4 x i16> %a2, <4 x i16> undef, <4 x i32> zeroinitializer
- %p2 = getelementptr inbounds i16, i16* %p, i32 1
- %b1 = load i16, i16* %p2, align 2
+ %p2 = getelementptr inbounds i16, ptr %p, i32 1
+ %b1 = load i16, ptr %p2, align 2
%b2 = insertelement <4 x i16> undef, i16 %b1, i32 0
%b3 = shufflevector <4 x i16> %b2, <4 x i16> undef, <4 x i32> zeroinitializer
%shuffle = shufflevector <4 x i16> %a3, <4 x i16> %b3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
diff --git a/llvm/test/CodeGen/ARM/vcvt-cost.ll b/llvm/test/CodeGen/ARM/vcvt-cost.ll
index 3147eb357ef1b..28f0fca60f97d 100644
--- a/llvm/test/CodeGen/ARM/vcvt-cost.ll
+++ b/llvm/test/CodeGen/ARM/vcvt-cost.ll
@@ -5,15 +5,15 @@
%T0_5 = type <8 x i8>
%T1_5 = type <8 x i32>
; CHECK-LABEL: func_cvt5:
-define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
+define void @func_cvt5(ptr %loadaddr, ptr %storeaddr) {
; CHECK: vmovl.s8
; CHECK: vmovl.s16
; CHECK: vmovl.s16
- %v0 = load %T0_5, %T0_5* %loadaddr
+ %v0 = load %T0_5, ptr %loadaddr
; COST: func_cvt5
; COST: cost of 3 {{.*}} sext
%r = sext %T0_5 %v0 to %T1_5
- store %T1_5 %r, %T1_5* %storeaddr
+ store %T1_5 %r, ptr %storeaddr
ret void
}
;; We currently estimate the cost of this instruction as expensive. If lowering
@@ -21,46 +21,46 @@ define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
%TA0_5 = type <8 x i8>
%TA1_5 = type <8 x i32>
; CHECK-LABEL: func_cvt1:
-define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) {
+define void @func_cvt1(ptr %loadaddr, ptr %storeaddr) {
; CHECK: vmovl.u8
; CHECK: vmovl.u16
; CHECK: vmovl.u16
- %v0 = load %TA0_5, %TA0_5* %loadaddr
+ %v0 = load %TA0_5, ptr %loadaddr
; COST: func_cvt1
; COST: cost of 3 {{.*}} zext
%r = zext %TA0_5 %v0 to %TA1_5
- store %TA1_5 %r, %TA1_5* %storeaddr
+ store %TA1_5 %r, ptr %storeaddr
ret void
}
%T0_51 = type <8 x i32>
%T1_51 = type <8 x i8>
; CHECK-LABEL: func_cvt51:
-define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) {
+define void @func_cvt51(ptr %loadaddr, ptr %storeaddr) {
; CHECK: vmovn.i32
; CHECK: vmovn.i32
; CHECK: vmovn.i16
- %v0 = load %T0_51, %T0_51* %loadaddr
+ %v0 = load %T0_51, ptr %loadaddr
; COST: func_cvt51
; COST: cost of 3 {{.*}} trunc
%r = trunc %T0_51 %v0 to %T1_51
- store %T1_51 %r, %T1_51* %storeaddr
+ store %T1_51 %r, ptr %storeaddr
ret void
}
%TT0_5 = type <16 x i8>
%TT1_5 = type <16 x i32>
; CHECK-LABEL: func_cvt52:
-define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
+define void @func_cvt52(ptr %loadaddr, ptr %storeaddr) {
; CHECK: vmovl.s16
; CHECK: vmovl.s16
; CHECK: vmovl.s16
; CHECK: vmovl.s16
- %v0 = load %TT0_5, %TT0_5* %loadaddr
+ %v0 = load %TT0_5, ptr %loadaddr
; COST: func_cvt52
; COST: cost of 6 {{.*}} sext
%r = sext %TT0_5 %v0 to %TT1_5
- store %TT1_5 %r, %TT1_5* %storeaddr
+ store %TT1_5 %r, ptr %storeaddr
ret void
}
;; We currently estimate the cost of this instruction as expensive. If lowering
@@ -68,86 +68,86 @@ define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
%TTA0_5 = type <16 x i8>
%TTA1_5 = type <16 x i32>
; CHECK-LABEL: func_cvt12:
-define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) {
+define void @func_cvt12(ptr %loadaddr, ptr %storeaddr) {
; CHECK: vmovl.u16
; CHECK: vmovl.u16
; CHECK: vmovl.u16
; CHECK: vmovl.u16
- %v0 = load %TTA0_5, %TTA0_5* %loadaddr
+ %v0 = load %TTA0_5, ptr %loadaddr
; COST: func_cvt12
; COST: cost of 6 {{.*}} zext
%r = zext %TTA0_5 %v0 to %TTA1_5
- store %TTA1_5 %r, %TTA1_5* %storeaddr
+ store %TTA1_5 %r, ptr %storeaddr
ret void
}
%TT0_51 = type <16 x i32>
%TT1_51 = type <16 x i8>
; CHECK-LABEL: func_cvt512:
-define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) {
+define void @func_cvt512(ptr %loadaddr, ptr %storeaddr) {
; CHECK: vmovn.i32
; CHECK: vmovn.i32
; CHECK: vmovn.i32
; CHECK: vmovn.i32
; CHECK: vmovn.i16
; CHECK: vmovn.i16
- %v0 = load %TT0_51, %TT0_51* %loadaddr
+ %v0 = load %TT0_51, ptr %loadaddr
; COST: func_cvt512
; COST: cost of 6 {{.*}} trunc
%r = trunc %TT0_51 %v0 to %TT1_51
- store %TT1_51 %r, %TT1_51* %storeaddr
+ store %TT1_51 %r, ptr %storeaddr
ret void
}
; CHECK-LABEL: sext_v4i16_v4i64:
-define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
+define void @sext_v4i16_v4i64(ptr %loadaddr, ptr %storeaddr) {
; CHECK: vmovl.s32
; CHECK: vmovl.s32
- %v0 = load <4 x i16>, <4 x i16>* %loadaddr
+ %v0 = load <4 x i16>, ptr %loadaddr
; COST: sext_v4i16_v4i64
; COST: cost of 3 {{.*}} sext
%r = sext <4 x i16> %v0 to <4 x i64>
- store <4 x i64> %r, <4 x i64>* %storeaddr
+ store <4 x i64> %r, ptr %storeaddr
ret void
}
; CHECK-LABEL: zext_v4i16_v4i64:
-define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
+define void @zext_v4i16_v4i64(ptr %loadaddr, ptr %storeaddr) {
; CHECK: vmovl.u32
; CHECK: vmovl.u32
- %v0 = load <4 x i16>, <4 x i16>* %loadaddr
+ %v0 = load <4 x i16>, ptr %loadaddr
; COST: zext_v4i16_v4i64
; COST: cost of 3 {{.*}} zext
%r = zext <4 x i16> %v0 to <4 x i64>
- store <4 x i64> %r, <4 x i64>* %storeaddr
+ store <4 x i64> %r, ptr %storeaddr
ret void
}
; CHECK-LABEL: sext_v8i16_v8i64:
-define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
+define void @sext_v8i16_v8i64(ptr %loadaddr, ptr %storeaddr) {
; CHECK: vmovl.s32
; CHECK: vmovl.s32
; CHECK: vmovl.s32
; CHECK: vmovl.s32
- %v0 = load <8 x i16>, <8 x i16>* %loadaddr
+ %v0 = load <8 x i16>, ptr %loadaddr
; COST: sext_v8i16_v8i64
; COST: cost of 6 {{.*}} sext
%r = sext <8 x i16> %v0 to <8 x i64>
- store <8 x i64> %r, <8 x i64>* %storeaddr
+ store <8 x i64> %r, ptr %storeaddr
ret void
}
; CHECK-LABEL: zext_v8i16_v8i64:
-define void @zext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
+define void @zext_v8i16_v8i64(ptr %loadaddr, ptr %storeaddr) {
; CHECK: vmovl.u32
; CHECK: vmovl.u32
; CHECK: vmovl.u32
; CHECK: vmovl.u32
- %v0 = load <8 x i16>, <8 x i16>* %loadaddr
+ %v0 = load <8 x i16>, ptr %loadaddr
; COST: zext_v8i16_v8i64
; COST: cost of 6 {{.*}} zext
%r = zext <8 x i16> %v0 to <8 x i64>
- store <8 x i64> %r, <8 x i64>* %storeaddr
+ store <8 x i64> %r, ptr %storeaddr
ret void
}
diff --git a/llvm/test/CodeGen/ARM/vcvt-v8.ll b/llvm/test/CodeGen/ARM/vcvt-v8.ll
index 9d5972fa4da57..8bcb633f8d1cf 100644
--- a/llvm/test/CodeGen/ARM/vcvt-v8.ll
+++ b/llvm/test/CodeGen/ARM/vcvt-v8.ll
@@ -1,128 +1,128 @@
; RUN: llc < %s -mtriple=armv8 -mattr=+neon | FileCheck %s
-define <4 x i32> @vcvtasq(<4 x float>* %A) {
+define <4 x i32> @vcvtasq(ptr %A) {
; CHECK: vcvtasq
; CHECK: vcvta.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %tmp1)
ret <4 x i32> %tmp2
}
-define <2 x i32> @vcvtasd(<2 x float>* %A) {
+define <2 x i32> @vcvtasd(ptr %A) {
; CHECK: vcvtasd
; CHECK: vcvta.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %tmp1)
ret <2 x i32> %tmp2
}
-define <4 x i32> @vcvtnsq(<4 x float>* %A) {
+define <4 x i32> @vcvtnsq(ptr %A) {
; CHECK: vcvtnsq
; CHECK: vcvtn.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %tmp1)
ret <4 x i32> %tmp2
}
-define <2 x i32> @vcvtnsd(<2 x float>* %A) {
+define <2 x i32> @vcvtnsd(ptr %A) {
; CHECK: vcvtnsd
; CHECK: vcvtn.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %tmp1)
ret <2 x i32> %tmp2
}
-define <4 x i32> @vcvtpsq(<4 x float>* %A) {
+define <4 x i32> @vcvtpsq(ptr %A) {
; CHECK: vcvtpsq
; CHECK: vcvtp.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %tmp1)
ret <4 x i32> %tmp2
}
-define <2 x i32> @vcvtpsd(<2 x float>* %A) {
+define <2 x i32> @vcvtpsd(ptr %A) {
; CHECK: vcvtpsd
; CHECK: vcvtp.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %tmp1)
ret <2 x i32> %tmp2
}
-define <4 x i32> @vcvtmsq(<4 x float>* %A) {
+define <4 x i32> @vcvtmsq(ptr %A) {
; CHECK: vcvtmsq
; CHECK: vcvtm.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float> %tmp1)
ret <4 x i32> %tmp2
}
-define <2 x i32> @vcvtmsd(<2 x float>* %A) {
+define <2 x i32> @vcvtmsd(ptr %A) {
; CHECK: vcvtmsd
; CHECK: vcvtm.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float> %tmp1)
ret <2 x i32> %tmp2
}
-define <4 x i32> @vcvtauq(<4 x float>* %A) {
+define <4 x i32> @vcvtauq(ptr %A) {
; CHECK: vcvtauq
; CHECK: vcvta.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %tmp1)
ret <4 x i32> %tmp2
}
-define <2 x i32> @vcvtaud(<2 x float>* %A) {
+define <2 x i32> @vcvtaud(ptr %A) {
; CHECK: vcvtaud
; CHECK: vcvta.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %tmp1)
ret <2 x i32> %tmp2
}
-define <4 x i32> @vcvtnuq(<4 x float>* %A) {
+define <4 x i32> @vcvtnuq(ptr %A) {
; CHECK: vcvtnuq
; CHECK: vcvtn.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %tmp1)
ret <4 x i32> %tmp2
}
-define <2 x i32> @vcvtnud(<2 x float>* %A) {
+define <2 x i32> @vcvtnud(ptr %A) {
; CHECK: vcvtnud
; CHECK: vcvtn.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %tmp1)
ret <2 x i32> %tmp2
}
-define <4 x i32> @vcvtpuq(<4 x float>* %A) {
+define <4 x i32> @vcvtpuq(ptr %A) {
; CHECK: vcvtpuq
; CHECK: vcvtp.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %tmp1)
ret <4 x i32> %tmp2
}
-define <2 x i32> @vcvtpud(<2 x float>* %A) {
+define <2 x i32> @vcvtpud(ptr %A) {
; CHECK: vcvtpud
; CHECK: vcvtp.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %tmp1)
ret <2 x i32> %tmp2
}
-define <4 x i32> @vcvtmuq(<4 x float>* %A) {
+define <4 x i32> @vcvtmuq(ptr %A) {
; CHECK: vcvtmuq
; CHECK: vcvtm.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float> %tmp1)
ret <4 x i32> %tmp2
}
-define <2 x i32> @vcvtmud(<2 x float>* %A) {
+define <2 x i32> @vcvtmud(ptr %A) {
; CHECK: vcvtmud
; CHECK: vcvtm.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtmu.v2i32.v2f32(<2 x float> %tmp1)
ret <2 x i32> %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/vcvt.ll b/llvm/test/CodeGen/ARM/vcvt.ll
index 1da6dee2aff74..4df18457f9be1 100644
--- a/llvm/test/CodeGen/ARM/vcvt.ll
+++ b/llvm/test/CodeGen/ARM/vcvt.ll
@@ -1,55 +1,55 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm-eabi -mattr=+neon,+fp16 %s -o - | FileCheck %s
-define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
+define <2 x i32> @vcvt_f32tos32(ptr %A) nounwind {
; CHECK-LABEL: vcvt_f32tos32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vcvt.s32.f32 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = fptosi <2 x float> %tmp1 to <2 x i32>
ret <2 x i32> %tmp2
}
-define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
+define <2 x i32> @vcvt_f32tou32(ptr %A) nounwind {
; CHECK-LABEL: vcvt_f32tou32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vcvt.u32.f32 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = fptoui <2 x float> %tmp1 to <2 x i32>
ret <2 x i32> %tmp2
}
-define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
+define <2 x float> @vcvt_s32tof32(ptr %A) nounwind {
; CHECK-LABEL: vcvt_s32tof32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vcvt.f32.s32 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = sitofp <2 x i32> %tmp1 to <2 x float>
ret <2 x float> %tmp2
}
-define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
+define <2 x float> @vcvt_u32tof32(ptr %A) nounwind {
; CHECK-LABEL: vcvt_u32tof32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vcvt.f32.u32 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = uitofp <2 x i32> %tmp1 to <2 x float>
ret <2 x float> %tmp2
}
-define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
+define <4 x i32> @vcvtQ_f32tos32(ptr %A) nounwind {
; CHECK-LABEL: vcvtQ_f32tos32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -57,12 +57,12 @@ define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = fptosi <4 x float> %tmp1 to <4 x i32>
ret <4 x i32> %tmp2
}
-define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
+define <4 x i32> @vcvtQ_f32tou32(ptr %A) nounwind {
; CHECK-LABEL: vcvtQ_f32tou32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -70,12 +70,12 @@ define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = fptoui <4 x float> %tmp1 to <4 x i32>
ret <4 x i32> %tmp2
}
-define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
+define <4 x float> @vcvtQ_s32tof32(ptr %A) nounwind {
; CHECK-LABEL: vcvtQ_s32tof32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -83,12 +83,12 @@ define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = sitofp <4 x i32> %tmp1 to <4 x float>
ret <4 x float> %tmp2
}
-define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
+define <4 x float> @vcvtQ_u32tof32(ptr %A) nounwind {
; CHECK-LABEL: vcvtQ_u32tof32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -96,55 +96,55 @@ define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = uitofp <4 x i32> %tmp1 to <4 x float>
ret <4 x float> %tmp2
}
-define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
+define <2 x i32> @vcvt_n_f32tos32(ptr %A) nounwind {
; CHECK-LABEL: vcvt_n_f32tos32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vcvt.s32.f32 d16, d16, #1
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
ret <2 x i32> %tmp2
}
-define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
+define <2 x i32> @vcvt_n_f32tou32(ptr %A) nounwind {
; CHECK-LABEL: vcvt_n_f32tou32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vcvt.u32.f32 d16, d16, #1
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
ret <2 x i32> %tmp2
}
-define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
+define <2 x float> @vcvt_n_s32tof32(ptr %A) nounwind {
; CHECK-LABEL: vcvt_n_s32tof32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vcvt.f32.s32 d16, d16, #1
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
ret <2 x float> %tmp2
}
-define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind {
+define <2 x float> @vcvt_n_u32tof32(ptr %A) nounwind {
; CHECK-LABEL: vcvt_n_u32tof32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vcvt.f32.u32 d16, d16, #1
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
ret <2 x float> %tmp2
}
@@ -154,7 +154,7 @@ declare <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwi
declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
-define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
+define <4 x i32> @vcvtQ_n_f32tos32(ptr %A) nounwind {
; CHECK-LABEL: vcvtQ_n_f32tos32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -162,12 +162,12 @@ define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
ret <4 x i32> %tmp2
}
-define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
+define <4 x i32> @vcvtQ_n_f32tou32(ptr %A) nounwind {
; CHECK-LABEL: vcvtQ_n_f32tou32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -175,12 +175,12 @@ define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
ret <4 x i32> %tmp2
}
-define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
+define <4 x float> @vcvtQ_n_s32tof32(ptr %A) nounwind {
; CHECK-LABEL: vcvtQ_n_s32tof32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -188,12 +188,12 @@ define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
ret <4 x float> %tmp2
}
-define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind {
+define <4 x float> @vcvtQ_n_u32tof32(ptr %A) nounwind {
; CHECK-LABEL: vcvtQ_n_u32tof32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -201,7 +201,7 @@ define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
ret <4 x float> %tmp2
}
@@ -211,7 +211,7 @@ declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwi
declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
-define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind {
+define <4 x float> @vcvt_f16tof32(ptr %A) nounwind {
; CHECK-LABEL: vcvt_f16tof32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -219,19 +219,19 @@ define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %tmp1)
ret <4 x float> %tmp2
}
-define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind {
+define <4 x i16> @vcvt_f32tof16(ptr %A) nounwind {
; CHECK-LABEL: vcvt_f32tof16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vcvt.f16.f32 d16, q8
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %tmp1)
ret <4 x i16> %tmp2
}
@@ -344,7 +344,7 @@ define <2 x i64> @fix_double_to_i64(<2 x double> %in) {
ret <2 x i64> %conv
}
-define i32 @multi_sint(double %c, i32* nocapture %p, i32* nocapture %q) {
+define i32 @multi_sint(double %c, ptr nocapture %p, ptr nocapture %q) {
; CHECK-LABEL: multi_sint:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov d16, r0, r1
@@ -354,12 +354,12 @@ define i32 @multi_sint(double %c, i32* nocapture %p, i32* nocapture %q) {
; CHECK-NEXT: vstr s0, [r3]
; CHECK-NEXT: mov pc, lr
%conv = fptosi double %c to i32
- store i32 %conv, i32* %p, align 4
- store i32 %conv, i32* %q, align 4
+ store i32 %conv, ptr %p, align 4
+ store i32 %conv, ptr %q, align 4
ret i32 %conv
}
-define i32 @multi_uint(double %c, i32* nocapture %p, i32* nocapture %q) {
+define i32 @multi_uint(double %c, ptr nocapture %p, ptr nocapture %q) {
; CHECK-LABEL: multi_uint:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov d16, r0, r1
@@ -369,12 +369,12 @@ define i32 @multi_uint(double %c, i32* nocapture %p, i32* nocapture %q) {
; CHECK-NEXT: vstr s0, [r3]
; CHECK-NEXT: mov pc, lr
%conv = fptoui double %c to i32
- store i32 %conv, i32* %p, align 4
- store i32 %conv, i32* %q, align 4
+ store i32 %conv, ptr %p, align 4
+ store i32 %conv, ptr %q, align 4
ret i32 %conv
}
-define void @double_to_sint_store(double %c, i32* nocapture %p) {
+define void @double_to_sint_store(double %c, ptr nocapture %p) {
; CHECK-LABEL: double_to_sint_store:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov d16, r0, r1
@@ -382,11 +382,11 @@ define void @double_to_sint_store(double %c, i32* nocapture %p) {
; CHECK-NEXT: vstr s0, [r2]
; CHECK-NEXT: mov pc, lr
%conv = fptosi double %c to i32
- store i32 %conv, i32* %p, align 4
+ store i32 %conv, ptr %p, align 4
ret void
}
-define void @double_to_uint_store(double %c, i32* nocapture %p) {
+define void @double_to_uint_store(double %c, ptr nocapture %p) {
; CHECK-LABEL: double_to_uint_store:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov d16, r0, r1
@@ -394,11 +394,11 @@ define void @double_to_uint_store(double %c, i32* nocapture %p) {
; CHECK-NEXT: vstr s0, [r2]
; CHECK-NEXT: mov pc, lr
%conv = fptoui double %c to i32
- store i32 %conv, i32* %p, align 4
+ store i32 %conv, ptr %p, align 4
ret void
}
-define void @float_to_sint_store(float %c, i32* nocapture %p) {
+define void @float_to_sint_store(float %c, ptr nocapture %p) {
; CHECK-LABEL: float_to_sint_store:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov s0, r0
@@ -406,11 +406,11 @@ define void @float_to_sint_store(float %c, i32* nocapture %p) {
; CHECK-NEXT: vstr s0, [r1]
; CHECK-NEXT: mov pc, lr
%conv = fptosi float %c to i32
- store i32 %conv, i32* %p, align 4
+ store i32 %conv, ptr %p, align 4
ret void
}
-define void @float_to_uint_store(float %c, i32* nocapture %p) {
+define void @float_to_uint_store(float %c, ptr nocapture %p) {
; CHECK-LABEL: float_to_uint_store:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov s0, r0
@@ -418,6 +418,6 @@ define void @float_to_uint_store(float %c, i32* nocapture %p) {
; CHECK-NEXT: vstr s0, [r1]
; CHECK-NEXT: mov pc, lr
%conv = fptoui float %c to i32
- store i32 %conv, i32* %p, align 4
+ store i32 %conv, ptr %p, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/vdiv_combine.ll b/llvm/test/CodeGen/ARM/vdiv_combine.ll
index d88fe31a59d26..d71604dcb8ce9 100644
--- a/llvm/test/CodeGen/ARM/vdiv_combine.ll
+++ b/llvm/test/CodeGen/ARM/vdiv_combine.ll
@@ -11,7 +11,7 @@ declare void @foo_int32x4_t(<4 x i32>)
; CHECK-NOT: {{vdiv|vmul}}
define void @t1() nounwind {
entry:
- %tmp = load i32, i32* @iin, align 4
+ %tmp = load i32, ptr @iin, align 4
%vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
%vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
%vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
@@ -27,7 +27,7 @@ declare void @foo_float32x2_t(<2 x float>)
; CHECK-NOT: {{vdiv|vmul}}
define void @t2() nounwind {
entry:
- %tmp = load i32, i32* @uin, align 4
+ %tmp = load i32, ptr @uin, align 4
%vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
%vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
%vcvt.i = uitofp <2 x i32> %vecinit2.i to <2 x float>
@@ -41,7 +41,7 @@ entry:
; CHECK: {{vdiv|vmul}}
define void @t3() nounwind {
entry:
- %tmp = load i32, i32* @iin, align 4
+ %tmp = load i32, ptr @iin, align 4
%vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
%vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
%vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
@@ -55,7 +55,7 @@ entry:
; CHECK: {{vdiv|vmul}}
define void @t4() nounwind {
entry:
- %tmp = load i32, i32* @iin, align 4
+ %tmp = load i32, ptr @iin, align 4
%vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
%vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
%vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
@@ -69,7 +69,7 @@ entry:
; CHECK-NOT: {{vdiv|vmul}}
define void @t5() nounwind {
entry:
- %tmp = load i32, i32* @iin, align 4
+ %tmp = load i32, ptr @iin, align 4
%vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
%vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
%vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
@@ -83,7 +83,7 @@ entry:
; CHECK-NOT: {{vdiv|vmul}}
define void @t6() nounwind {
entry:
- %tmp = load i32, i32* @iin, align 4
+ %tmp = load i32, ptr @iin, align 4
%vecinit.i = insertelement <4 x i32> undef, i32 %tmp, i32 0
%vecinit2.i = insertelement <4 x i32> %vecinit.i, i32 %tmp, i32 1
%vecinit4.i = insertelement <4 x i32> %vecinit2.i, i32 %tmp, i32 2
diff --git a/llvm/test/CodeGen/ARM/vdup.ll b/llvm/test/CodeGen/ARM/vdup.ll
index 564e3665115c4..9a792035a469b 100644
--- a/llvm/test/CodeGen/ARM/vdup.ll
+++ b/llvm/test/CodeGen/ARM/vdup.ll
@@ -219,55 +219,55 @@ define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
ret <4 x float> %tmp2
}
-define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vduplane8(ptr %A) nounwind {
; CHECK-LABEL: vduplane8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vdup.8 d16, d16[1]
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
ret <8 x i8> %tmp2
}
-define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vduplane16(ptr %A) nounwind {
; CHECK-LABEL: vduplane16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vdup.16 d16, d16[1]
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
ret <4 x i16> %tmp2
}
-define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vduplane32(ptr %A) nounwind {
; CHECK-LABEL: vduplane32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vdup.32 d16, d16[1]
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
ret <2 x i32> %tmp2
}
-define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
+define <2 x float> @vduplanefloat(ptr %A) nounwind {
; CHECK-LABEL: vduplanefloat:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vdup.32 d16, d16[1]
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 >
ret <2 x float> %tmp2
}
-define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
+define <16 x i8> @vduplaneQ8(ptr %A) nounwind {
; CHECK-LABEL: vduplaneQ8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -275,12 +275,12 @@ define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
ret <16 x i8> %tmp2
}
-define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
+define <8 x i16> @vduplaneQ16(ptr %A) nounwind {
; CHECK-LABEL: vduplaneQ16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -288,12 +288,12 @@ define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
ret <8 x i16> %tmp2
}
-define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
+define <4 x i32> @vduplaneQ32(ptr %A) nounwind {
; CHECK-LABEL: vduplaneQ32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -301,12 +301,12 @@ define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
ret <4 x i32> %tmp2
}
-define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
+define <4 x float> @vduplaneQfloat(ptr %A) nounwind {
; CHECK-LABEL: vduplaneQfloat:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -314,7 +314,7 @@ define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
ret <4 x float> %tmp2
}
@@ -364,7 +364,7 @@ entry:
}
; Radar 7373643
-define void @redundantVdup(<8 x i8>* %ptr) nounwind {
+define void @redundantVdup(ptr %ptr) nounwind {
; CHECK-LABEL: redundantVdup:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 d16, #0x80
@@ -372,7 +372,7 @@ define void @redundantVdup(<8 x i8>* %ptr) nounwind {
; CHECK-NEXT: mov pc, lr
%1 = insertelement <8 x i8> undef, i8 -128, i32 0
%2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
- store <8 x i8> %2, <8 x i8>* %ptr, align 8
+ store <8 x i8> %2, ptr %ptr, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/vector-DAGCombine.ll b/llvm/test/CodeGen/ARM/vector-DAGCombine.ll
index 3d3401f1d672e..2ba3423b834f2 100644
--- a/llvm/test/CodeGen/ARM/vector-DAGCombine.ll
+++ b/llvm/test/CodeGen/ARM/vector-DAGCombine.ll
@@ -28,10 +28,10 @@ define void @test_illegal_build_vector() nounwind {
; CHECK-LABEL: test_illegal_build_vector:
; CHECK: @ %bb.0: @ %entry
entry:
- store <2 x i64> undef, <2 x i64>* undef, align 16
- %0 = load <16 x i8>, <16 x i8>* undef, align 16 ; <<16 x i8>> [#uses=1]
+ store <2 x i64> undef, ptr undef, align 16
+ %0 = load <16 x i8>, ptr undef, align 16 ; <<16 x i8>> [#uses=1]
%1 = or <16 x i8> zeroinitializer, %0 ; <<16 x i8>> [#uses=1]
- store <16 x i8> %1, <16 x i8>* undef, align 16
+ store <16 x i8> %1, ptr undef, align 16
ret void
}
@@ -41,7 +41,7 @@ define void @test_pr22678() {
; CHECK-LABEL: test_pr22678:
; CHECK: @ %bb.0:
%1 = fptoui <16 x float> undef to <16 x i8>
- store <16 x i8> %1, <16 x i8>* undef
+ store <16 x i8> %1, ptr undef
ret void
}
@@ -81,7 +81,7 @@ bb2:
; Test trying to do a ShiftCombine on illegal types.
; The vector should be split first.
-define void @lshrIllegalType(<8 x i32>* %A) nounwind {
+define void @lshrIllegalType(ptr %A) nounwind {
; CHECK-LABEL: lshrIllegalType:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0:128]
@@ -91,9 +91,9 @@ define void @lshrIllegalType(<8 x i32>* %A) nounwind {
; CHECK-NEXT: vshr.u32 q8, q8, #3
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: bx lr
- %tmp1 = load <8 x i32>, <8 x i32>* %A
+ %tmp1 = load <8 x i32>, ptr %A
%tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
- store <8 x i32> %tmp2, <8 x i32>* %A
+ store <8 x i32> %tmp2, ptr %A
ret void
}
@@ -111,54 +111,54 @@ entry:
%2 = shufflevector <4 x i16> %1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%3 = add <8 x i16> %2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
%4 = trunc <8 x i16> %3 to <8 x i8>
- tail call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* undef, <8 x i8> %4, i32 1)
+ tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr undef, <8 x i8> %4, i32 1)
ret void
}
-declare void @llvm.arm.neon.vst1.p0i8.v8i8(i8*, <8 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v8i8(ptr, <8 x i8>, i32) nounwind
; Test that loads and stores of i64 vector elements are handled as f64 values
; so they are not split up into i32 values. Radar 8755338.
-define void @i64_buildvector(i64* %ptr, <2 x i64>* %vp) nounwind {
+define void @i64_buildvector(ptr %ptr, ptr %vp) nounwind {
; CHECK-LABEL: i64_buildvector:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
; CHECK-NEXT: bx lr
- %t0 = load i64, i64* %ptr, align 4
+ %t0 = load i64, ptr %ptr, align 4
%t1 = insertelement <2 x i64> undef, i64 %t0, i32 0
- store <2 x i64> %t1, <2 x i64>* %vp
+ store <2 x i64> %t1, ptr %vp
ret void
}
-define void @i64_insertelement(i64* %ptr, <2 x i64>* %vp) nounwind {
+define void @i64_insertelement(ptr %ptr, ptr %vp) nounwind {
; CHECK-LABEL: i64_insertelement:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
; CHECK-NEXT: bx lr
- %t0 = load i64, i64* %ptr, align 4
- %vec = load <2 x i64>, <2 x i64>* %vp
+ %t0 = load i64, ptr %ptr, align 4
+ %vec = load <2 x i64>, ptr %vp
%t1 = insertelement <2 x i64> %vec, i64 %t0, i32 0
- store <2 x i64> %t1, <2 x i64>* %vp
+ store <2 x i64> %t1, ptr %vp
ret void
}
-define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind {
+define void @i64_extractelement(ptr %ptr, ptr %vp) nounwind {
; CHECK-LABEL: i64_extractelement:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vstr d16, [r0]
; CHECK-NEXT: bx lr
- %vec = load <2 x i64>, <2 x i64>* %vp
+ %vec = load <2 x i64>, ptr %vp
%t1 = extractelement <2 x i64> %vec, i32 0
- store i64 %t1, i64* %ptr
+ store i64 %t1, ptr %ptr
ret void
}
; Test trying to do a AND Combine on illegal types.
-define void @andVec(<3 x i8>* %A) nounwind {
+define void @andVec(ptr %A) nounwind {
; CHECK-LABEL: andVec:
; CHECK: @ %bb.0:
; CHECK-NEXT: .pad #8
@@ -182,15 +182,15 @@ define void @andVec(<3 x i8>* %A) nounwind {
; CHECK-NEXT: strh r2, [r0]
; CHECK-NEXT: add sp, sp, #8
; CHECK-NEXT: bx lr
- %tmp = load <3 x i8>, <3 x i8>* %A, align 4
+ %tmp = load <3 x i8>, ptr %A, align 4
%and = and <3 x i8> %tmp, <i8 7, i8 7, i8 7>
- store <3 x i8> %and, <3 x i8>* %A
+ store <3 x i8> %and, ptr %A
ret void
}
; Test trying to do an OR Combine on illegal types.
-define void @orVec(<3 x i8>* %A) nounwind {
+define void @orVec(ptr %A) nounwind {
; CHECK-LABEL: orVec:
; CHECK: @ %bb.0:
; CHECK-NEXT: .pad #8
@@ -213,9 +213,9 @@ define void @orVec(<3 x i8>* %A) nounwind {
; CHECK-NEXT: strh r2, [r0]
; CHECK-NEXT: add sp, sp, #8
; CHECK-NEXT: bx lr
- %tmp = load <3 x i8>, <3 x i8>* %A, align 4
+ %tmp = load <3 x i8>, ptr %A, align 4
%or = or <3 x i8> %tmp, <i8 7, i8 7, i8 7>
- store <3 x i8> %or, <3 x i8>* %A
+ store <3 x i8> %or, ptr %A
ret void
}
@@ -236,7 +236,7 @@ define i16 @foldBuildVectors() {
; Test that we are generating vrev and vext for reverse shuffles of v8i16
; shuffles.
-define void @reverse_v8i16(<8 x i16>* %loadaddr, <8 x i16>* %storeaddr) {
+define void @reverse_v8i16(ptr %loadaddr, ptr %storeaddr) {
; CHECK-LABEL: reverse_v8i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -244,16 +244,16 @@ define void @reverse_v8i16(<8 x i16>* %loadaddr, <8 x i16>* %storeaddr) {
; CHECK-NEXT: vext.16 q8, q8, q8, #4
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
; CHECK-NEXT: bx lr
- %v0 = load <8 x i16>, <8 x i16>* %loadaddr
+ %v0 = load <8 x i16>, ptr %loadaddr
%v1 = shufflevector <8 x i16> %v0, <8 x i16> undef,
<8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- store <8 x i16> %v1, <8 x i16>* %storeaddr
+ store <8 x i16> %v1, ptr %storeaddr
ret void
}
; Test that we are generating vrev and vext for reverse shuffles of v16i8
; shuffles.
-define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) {
+define void @reverse_v16i8(ptr %loadaddr, ptr %storeaddr) {
; CHECK-LABEL: reverse_v16i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -261,11 +261,11 @@ define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) {
; CHECK-NEXT: vext.8 q8, q8, q8, #8
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
; CHECK-NEXT: bx lr
- %v0 = load <16 x i8>, <16 x i8>* %loadaddr
+ %v0 = load <16 x i8>, ptr %loadaddr
%v1 = shufflevector <16 x i8> %v0, <16 x i8> undef,
<16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8,
i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- store <16 x i8> %v1, <16 x i8>* %storeaddr
+ store <16 x i8> %v1, ptr %storeaddr
ret void
}
@@ -273,7 +273,7 @@ define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) {
; vldr cannot handle unaligned loads.
; Fall back to vld1.32, which can, instead of using the general purpose loads
; followed by a costly sequence of instructions to build the vector register.
-define <8 x i16> @t3(i8 zeroext %xf, i8* nocapture %sp0, i8* nocapture %sp1, i32* nocapture %outp) {
+define <8 x i16> @t3(i8 zeroext %xf, ptr nocapture %sp0, ptr nocapture %sp1, ptr nocapture %outp) {
; CHECK-LABEL: t3:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.32 {d16[0]}, [r1]
@@ -283,10 +283,8 @@ define <8 x i16> @t3(i8 zeroext %xf, i8* nocapture %sp0, i8* nocapture %sp1, i32
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
entry:
- %pix_sp0.0.cast = bitcast i8* %sp0 to i32*
- %pix_sp0.0.copyload = load i32, i32* %pix_sp0.0.cast, align 1
- %pix_sp1.0.cast = bitcast i8* %sp1 to i32*
- %pix_sp1.0.copyload = load i32, i32* %pix_sp1.0.cast, align 1
+ %pix_sp0.0.copyload = load i32, ptr %sp0, align 1
+ %pix_sp1.0.copyload = load i32, ptr %sp1, align 1
%vecinit = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
%vecinit1 = insertelement <2 x i32> %vecinit, i32 %pix_sp1.0.copyload, i32 1
%0 = bitcast <2 x i32> %vecinit1 to <8 x i8>
@@ -299,7 +297,7 @@ declare <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8>, <8 x i8>)
; Check that (insert_vector_elt (load)) => (vector_load).
; Thus, check that scalar_to_vector do not interfer with that.
-define <8 x i16> @t4(i8* nocapture %sp0) {
+define <8 x i16> @t4(ptr nocapture %sp0) {
; CHECK-LABEL: t4:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.32 {d16[0]}, [r0]
@@ -308,8 +306,7 @@ define <8 x i16> @t4(i8* nocapture %sp0) {
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
entry:
- %pix_sp0.0.cast = bitcast i8* %sp0 to i32*
- %pix_sp0.0.copyload = load i32, i32* %pix_sp0.0.cast, align 1
+ %pix_sp0.0.copyload = load i32, ptr %sp0, align 1
%vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
%0 = bitcast <2 x i32> %vec to <8 x i8>
%vmull.i = tail call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %0, <8 x i8> %0)
@@ -319,7 +316,7 @@ entry:
; Make sure vector load is used for all three loads.
; Lowering to build vector was breaking the single use property of the load of
; %pix_sp0.0.copyload.
-define <8 x i16> @t5(i8* nocapture %sp0, i8* nocapture %sp1, i8* nocapture %sp2) {
+define <8 x i16> @t5(ptr nocapture %sp0, ptr nocapture %sp1, ptr nocapture %sp2) {
; CHECK-LABEL: t5:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.32 {d16[1]}, [r0]
@@ -331,12 +328,9 @@ define <8 x i16> @t5(i8* nocapture %sp0, i8* nocapture %sp1, i8* nocapture %sp2)
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: bx lr
entry:
- %pix_sp0.0.cast = bitcast i8* %sp0 to i32*
- %pix_sp0.0.copyload = load i32, i32* %pix_sp0.0.cast, align 1
- %pix_sp1.0.cast = bitcast i8* %sp1 to i32*
- %pix_sp1.0.copyload = load i32, i32* %pix_sp1.0.cast, align 1
- %pix_sp2.0.cast = bitcast i8* %sp2 to i32*
- %pix_sp2.0.copyload = load i32, i32* %pix_sp2.0.cast, align 1
+ %pix_sp0.0.copyload = load i32, ptr %sp0, align 1
+ %pix_sp1.0.copyload = load i32, ptr %sp1, align 1
+ %pix_sp2.0.copyload = load i32, ptr %sp2, align 1
%vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 1
%vecinit1 = insertelement <2 x i32> %vec, i32 %pix_sp1.0.copyload, i32 0
%vecinit2 = insertelement <2 x i32> %vec, i32 %pix_sp2.0.copyload, i32 0
diff --git a/llvm/test/CodeGen/ARM/vector-extend-narrow.ll b/llvm/test/CodeGen/ARM/vector-extend-narrow.ll
index 1aaffcc302d2a..3264b1513ec01 100644
--- a/llvm/test/CodeGen/ARM/vector-extend-narrow.ll
+++ b/llvm/test/CodeGen/ARM/vector-extend-narrow.ll
@@ -1,10 +1,10 @@
; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
; CHECK-LABEL: f:
-define float @f(<4 x i16>* nocapture %in) {
+define float @f(ptr nocapture %in) {
; CHECK: vld1
; CHECK: vmovl.u16
- %1 = load <4 x i16>, <4 x i16>* %in
+ %1 = load <4 x i16>, ptr %in
; CHECK: vcvt.f32.u32
%2 = uitofp <4 x i16> %1 to <4 x float>
%3 = extractelement <4 x float> %2, i32 0
@@ -19,13 +19,13 @@ define float @f(<4 x i16>* nocapture %in) {
}
; CHECK-LABEL: g:
-define float @g(<4 x i8>* nocapture %in) {
+define float @g(ptr nocapture %in) {
; Note: vld1 here is reasonably important. Mixing VFP and NEON
; instructions is bad on some cores
; CHECK: vld1
; CHECK: vmovl.u8
; CHECK: vmovl.u16
- %1 = load <4 x i8>, <4 x i8>* %in
+ %1 = load <4 x i8>, ptr %in
; CHECK: vcvt.f32.u32
%2 = uitofp <4 x i8> %1 to <4 x float>
%3 = extractelement <4 x float> %2, i32 0
@@ -48,7 +48,7 @@ define <4 x i8> @h(<4 x float> %v) {
}
; CHECK-LABEL: i:
-define <4 x i8> @i(<4 x i8>* %x, <4 x i8> %y) {
+define <4 x i8> @i(ptr %x, <4 x i8> %y) {
; Note: vld1 here is reasonably important. Mixing VFP and NEON
; instructions is bad on some cores
; CHECK: vld1
@@ -58,17 +58,17 @@ define <4 x i8> @i(<4 x i8>* %x, <4 x i8> %y) {
; CHECK: vrecps
; CHECK: vmul
; CHECK: vmovn
- %1 = load <4 x i8>, <4 x i8>* %x, align 4
+ %1 = load <4 x i8>, ptr %x, align 4
%2 = sdiv <4 x i8> %y, %1
ret <4 x i8> %2
}
; CHECK-LABEL: j:
-define <4 x i32> @j(<4 x i8>* %in) nounwind {
+define <4 x i32> @j(ptr %in) nounwind {
; CHECK: vld1
; CHECK: vmovl.u8
; CHECK: vmovl.u16
; CHECK-NOT: vand
- %1 = load <4 x i8>, <4 x i8>* %in, align 4
+ %1 = load <4 x i8>, ptr %in, align 4
%2 = zext <4 x i8> %1 to <4 x i32>
ret <4 x i32> %2
}
diff --git a/llvm/test/CodeGen/ARM/vector-extract.ll b/llvm/test/CodeGen/ARM/vector-extract.ll
index 59eaf3a70b218..26e3a00103878 100644
--- a/llvm/test/CodeGen/ARM/vector-extract.ll
+++ b/llvm/test/CodeGen/ARM/vector-extract.ll
@@ -5,7 +5,7 @@
%struct.__neon_int32x4x4_t = type { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> }
-define i32 @vld4Qi32(i32* %A) nounwind {
+define i32 @vld4Qi32(ptr %A) nounwind {
; CHECK-LABEL: vld4Qi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld4.32 {d16, d18, d20, d22}, [r0]!
@@ -14,8 +14,7 @@ define i32 @vld4Qi32(i32* %A) nounwind {
; CHECK-NEXT: vmov.32 r1, d16[0]
; CHECK-NEXT: add r0, r1, r0
; CHECK-NEXT: bx lr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 0
%tmp3 = extractelement <4 x i32> %tmp2, i32 0
%tmp4 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 1
@@ -24,4 +23,4 @@ define i32 @vld4Qi32(i32* %A) nounwind {
ret i32 %tmp6
}
-declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0i8(i8*, i32) nounwind readonly
+declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0(ptr, i32) nounwind readonly
diff --git a/llvm/test/CodeGen/ARM/vector-load.ll b/llvm/test/CodeGen/ARM/vector-load.ll
index 396d74d4040a7..b753dacebb81f 100644
--- a/llvm/test/CodeGen/ARM/vector-load.ll
+++ b/llvm/test/CodeGen/ARM/vector-load.ll
@@ -3,240 +3,240 @@
target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
target triple = "thumbv7s-apple-ios8.0.0"
-define <8 x i8> @load_v8i8(<8 x i8>** %ptr) {
+define <8 x i8> @load_v8i8(ptr %ptr) {
;CHECK-LABEL: load_v8i8:
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <8 x i8>*, <8 x i8>** %ptr
- %lA = load <8 x i8>, <8 x i8>* %A, align 1
+ %A = load ptr, ptr %ptr
+ %lA = load <8 x i8>, ptr %A, align 1
ret <8 x i8> %lA
}
-define <8 x i8> @load_v8i8_update(<8 x i8>** %ptr) {
+define <8 x i8> @load_v8i8_update(ptr %ptr) {
;CHECK-LABEL: load_v8i8_update:
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <8 x i8>*, <8 x i8>** %ptr
- %lA = load <8 x i8>, <8 x i8>* %A, align 1
- %inc = getelementptr <8 x i8>, <8 x i8>* %A, i38 1
- store <8 x i8>* %inc, <8 x i8>** %ptr
+ %A = load ptr, ptr %ptr
+ %lA = load <8 x i8>, ptr %A, align 1
+ %inc = getelementptr <8 x i8>, ptr %A, i38 1
+ store ptr %inc, ptr %ptr
ret <8 x i8> %lA
}
-define <4 x i16> @load_v4i16(<4 x i16>** %ptr) {
+define <4 x i16> @load_v4i16(ptr %ptr) {
;CHECK-LABEL: load_v4i16:
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <4 x i16>*, <4 x i16>** %ptr
- %lA = load <4 x i16>, <4 x i16>* %A, align 1
+ %A = load ptr, ptr %ptr
+ %lA = load <4 x i16>, ptr %A, align 1
ret <4 x i16> %lA
}
-define <4 x i16> @load_v4i16_update(<4 x i16>** %ptr) {
+define <4 x i16> @load_v4i16_update(ptr %ptr) {
;CHECK-LABEL: load_v4i16_update:
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <4 x i16>*, <4 x i16>** %ptr
- %lA = load <4 x i16>, <4 x i16>* %A, align 1
- %inc = getelementptr <4 x i16>, <4 x i16>* %A, i34 1
- store <4 x i16>* %inc, <4 x i16>** %ptr
+ %A = load ptr, ptr %ptr
+ %lA = load <4 x i16>, ptr %A, align 1
+ %inc = getelementptr <4 x i16>, ptr %A, i34 1
+ store ptr %inc, ptr %ptr
ret <4 x i16> %lA
}
-define <2 x i32> @load_v2i32(<2 x i32>** %ptr) {
+define <2 x i32> @load_v2i32(ptr %ptr) {
;CHECK-LABEL: load_v2i32:
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <2 x i32>*, <2 x i32>** %ptr
- %lA = load <2 x i32>, <2 x i32>* %A, align 1
+ %A = load ptr, ptr %ptr
+ %lA = load <2 x i32>, ptr %A, align 1
ret <2 x i32> %lA
}
-define <2 x i32> @load_v2i32_update(<2 x i32>** %ptr) {
+define <2 x i32> @load_v2i32_update(ptr %ptr) {
;CHECK-LABEL: load_v2i32_update:
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x i32>*, <2 x i32>** %ptr
- %lA = load <2 x i32>, <2 x i32>* %A, align 1
- %inc = getelementptr <2 x i32>, <2 x i32>* %A, i32 1
- store <2 x i32>* %inc, <2 x i32>** %ptr
+ %A = load ptr, ptr %ptr
+ %lA = load <2 x i32>, ptr %A, align 1
+ %inc = getelementptr <2 x i32>, ptr %A, i32 1
+ store ptr %inc, ptr %ptr
ret <2 x i32> %lA
}
-define <2 x float> @load_v2f32(<2 x float>** %ptr) {
+define <2 x float> @load_v2f32(ptr %ptr) {
;CHECK-LABEL: load_v2f32:
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <2 x float>*, <2 x float>** %ptr
- %lA = load <2 x float>, <2 x float>* %A, align 1
+ %A = load ptr, ptr %ptr
+ %lA = load <2 x float>, ptr %A, align 1
ret <2 x float> %lA
}
-define <2 x float> @load_v2f32_update(<2 x float>** %ptr) {
+define <2 x float> @load_v2f32_update(ptr %ptr) {
;CHECK-LABEL: load_v2f32_update:
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x float>*, <2 x float>** %ptr
- %lA = load <2 x float>, <2 x float>* %A, align 1
- %inc = getelementptr <2 x float>, <2 x float>* %A, i32 1
- store <2 x float>* %inc, <2 x float>** %ptr
+ %A = load ptr, ptr %ptr
+ %lA = load <2 x float>, ptr %A, align 1
+ %inc = getelementptr <2 x float>, ptr %A, i32 1
+ store ptr %inc, ptr %ptr
ret <2 x float> %lA
}
-define <1 x i64> @load_v1i64(<1 x i64>** %ptr) {
+define <1 x i64> @load_v1i64(ptr %ptr) {
;CHECK-LABEL: load_v1i64:
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <1 x i64>*, <1 x i64>** %ptr
- %lA = load <1 x i64>, <1 x i64>* %A, align 1
+ %A = load ptr, ptr %ptr
+ %lA = load <1 x i64>, ptr %A, align 1
ret <1 x i64> %lA
}
-define <1 x i64> @load_v1i64_update(<1 x i64>** %ptr) {
+define <1 x i64> @load_v1i64_update(ptr %ptr) {
;CHECK-LABEL: load_v1i64_update:
;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <1 x i64>*, <1 x i64>** %ptr
- %lA = load <1 x i64>, <1 x i64>* %A, align 1
- %inc = getelementptr <1 x i64>, <1 x i64>* %A, i31 1
- store <1 x i64>* %inc, <1 x i64>** %ptr
+ %A = load ptr, ptr %ptr
+ %lA = load <1 x i64>, ptr %A, align 1
+ %inc = getelementptr <1 x i64>, ptr %A, i31 1
+ store ptr %inc, ptr %ptr
ret <1 x i64> %lA
}
-define <16 x i8> @load_v16i8(<16 x i8>** %ptr) {
+define <16 x i8> @load_v16i8(ptr %ptr) {
;CHECK-LABEL: load_v16i8:
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <16 x i8>*, <16 x i8>** %ptr
- %lA = load <16 x i8>, <16 x i8>* %A, align 1
+ %A = load ptr, ptr %ptr
+ %lA = load <16 x i8>, ptr %A, align 1
ret <16 x i8> %lA
}
-define <16 x i8> @load_v16i8_update(<16 x i8>** %ptr) {
+define <16 x i8> @load_v16i8_update(ptr %ptr) {
;CHECK-LABEL: load_v16i8_update:
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <16 x i8>*, <16 x i8>** %ptr
- %lA = load <16 x i8>, <16 x i8>* %A, align 1
- %inc = getelementptr <16 x i8>, <16 x i8>* %A, i316 1
- store <16 x i8>* %inc, <16 x i8>** %ptr
+ %A = load ptr, ptr %ptr
+ %lA = load <16 x i8>, ptr %A, align 1
+ %inc = getelementptr <16 x i8>, ptr %A, i316 1
+ store ptr %inc, ptr %ptr
ret <16 x i8> %lA
}
-define <8 x i16> @load_v8i16(<8 x i16>** %ptr) {
+define <8 x i16> @load_v8i16(ptr %ptr) {
;CHECK-LABEL: load_v8i16:
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <8 x i16>*, <8 x i16>** %ptr
- %lA = load <8 x i16>, <8 x i16>* %A, align 1
+ %A = load ptr, ptr %ptr
+ %lA = load <8 x i16>, ptr %A, align 1
ret <8 x i16> %lA
}
-define <8 x i16> @load_v8i16_update(<8 x i16>** %ptr) {
+define <8 x i16> @load_v8i16_update(ptr %ptr) {
;CHECK-LABEL: load_v8i16_update:
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <8 x i16>*, <8 x i16>** %ptr
- %lA = load <8 x i16>, <8 x i16>* %A, align 1
- %inc = getelementptr <8 x i16>, <8 x i16>* %A, i38 1
- store <8 x i16>* %inc, <8 x i16>** %ptr
+ %A = load ptr, ptr %ptr
+ %lA = load <8 x i16>, ptr %A, align 1
+ %inc = getelementptr <8 x i16>, ptr %A, i38 1
+ store ptr %inc, ptr %ptr
ret <8 x i16> %lA
}
-define <4 x i32> @load_v4i32(<4 x i32>** %ptr) {
+define <4 x i32> @load_v4i32(ptr %ptr) {
;CHECK-LABEL: load_v4i32:
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <4 x i32>*, <4 x i32>** %ptr
- %lA = load <4 x i32>, <4 x i32>* %A, align 1
+ %A = load ptr, ptr %ptr
+ %lA = load <4 x i32>, ptr %A, align 1
ret <4 x i32> %lA
}
-define <4 x i32> @load_v4i32_update(<4 x i32>** %ptr) {
+define <4 x i32> @load_v4i32_update(ptr %ptr) {
;CHECK-LABEL: load_v4i32_update:
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <4 x i32>*, <4 x i32>** %ptr
- %lA = load <4 x i32>, <4 x i32>* %A, align 1
- %inc = getelementptr <4 x i32>, <4 x i32>* %A, i34 1
- store <4 x i32>* %inc, <4 x i32>** %ptr
+ %A = load ptr, ptr %ptr
+ %lA = load <4 x i32>, ptr %A, align 1
+ %inc = getelementptr <4 x i32>, ptr %A, i34 1
+ store ptr %inc, ptr %ptr
ret <4 x i32> %lA
}
-define <4 x float> @load_v4f32(<4 x float>** %ptr) {
+define <4 x float> @load_v4f32(ptr %ptr) {
;CHECK-LABEL: load_v4f32:
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <4 x float>*, <4 x float>** %ptr
- %lA = load <4 x float>, <4 x float>* %A, align 1
+ %A = load ptr, ptr %ptr
+ %lA = load <4 x float>, ptr %A, align 1
ret <4 x float> %lA
}
-define <4 x float> @load_v4f32_update(<4 x float>** %ptr) {
+define <4 x float> @load_v4f32_update(ptr %ptr) {
;CHECK-LABEL: load_v4f32_update:
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <4 x float>*, <4 x float>** %ptr
- %lA = load <4 x float>, <4 x float>* %A, align 1
- %inc = getelementptr <4 x float>, <4 x float>* %A, i34 1
- store <4 x float>* %inc, <4 x float>** %ptr
+ %A = load ptr, ptr %ptr
+ %lA = load <4 x float>, ptr %A, align 1
+ %inc = getelementptr <4 x float>, ptr %A, i34 1
+ store ptr %inc, ptr %ptr
ret <4 x float> %lA
}
-define <2 x i64> @load_v2i64(<2 x i64>** %ptr) {
+define <2 x i64> @load_v2i64(ptr %ptr) {
;CHECK-LABEL: load_v2i64:
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <2 x i64>*, <2 x i64>** %ptr
- %lA = load <2 x i64>, <2 x i64>* %A, align 1
+ %A = load ptr, ptr %ptr
+ %lA = load <2 x i64>, ptr %A, align 1
ret <2 x i64> %lA
}
-define <2 x i64> @load_v2i64_update(<2 x i64>** %ptr) {
+define <2 x i64> @load_v2i64_update(ptr %ptr) {
;CHECK-LABEL: load_v2i64_update:
;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x i64>*, <2 x i64>** %ptr
- %lA = load <2 x i64>, <2 x i64>* %A, align 1
- %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
+ %A = load ptr, ptr %ptr
+ %lA = load <2 x i64>, ptr %A, align 1
+ %inc = getelementptr <2 x i64>, ptr %A, i32 1
+ store ptr %inc, ptr %ptr
ret <2 x i64> %lA
}
; Make sure we change the type to match alignment if necessary.
-define <2 x i64> @load_v2i64_update_aligned2(<2 x i64>** %ptr) {
+define <2 x i64> @load_v2i64_update_aligned2(ptr %ptr) {
;CHECK-LABEL: load_v2i64_update_aligned2:
;CHECK: vld1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x i64>*, <2 x i64>** %ptr
- %lA = load <2 x i64>, <2 x i64>* %A, align 2
- %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
+ %A = load ptr, ptr %ptr
+ %lA = load <2 x i64>, ptr %A, align 2
+ %inc = getelementptr <2 x i64>, ptr %A, i32 1
+ store ptr %inc, ptr %ptr
ret <2 x i64> %lA
}
-define <2 x i64> @load_v2i64_update_aligned4(<2 x i64>** %ptr) {
+define <2 x i64> @load_v2i64_update_aligned4(ptr %ptr) {
;CHECK-LABEL: load_v2i64_update_aligned4:
;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x i64>*, <2 x i64>** %ptr
- %lA = load <2 x i64>, <2 x i64>* %A, align 4
- %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
+ %A = load ptr, ptr %ptr
+ %lA = load <2 x i64>, ptr %A, align 4
+ %inc = getelementptr <2 x i64>, ptr %A, i32 1
+ store ptr %inc, ptr %ptr
ret <2 x i64> %lA
}
-define <2 x i64> @load_v2i64_update_aligned8(<2 x i64>** %ptr) {
+define <2 x i64> @load_v2i64_update_aligned8(ptr %ptr) {
;CHECK-LABEL: load_v2i64_update_aligned8:
;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x i64>*, <2 x i64>** %ptr
- %lA = load <2 x i64>, <2 x i64>* %A, align 8
- %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
+ %A = load ptr, ptr %ptr
+ %lA = load <2 x i64>, ptr %A, align 8
+ %inc = getelementptr <2 x i64>, ptr %A, i32 1
+ store ptr %inc, ptr %ptr
ret <2 x i64> %lA
}
-define <2 x i64> @load_v2i64_update_aligned16(<2 x i64>** %ptr) {
+define <2 x i64> @load_v2i64_update_aligned16(ptr %ptr) {
;CHECK-LABEL: load_v2i64_update_aligned16:
;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]!
- %A = load <2 x i64>*, <2 x i64>** %ptr
- %lA = load <2 x i64>, <2 x i64>* %A, align 16
- %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
+ %A = load ptr, ptr %ptr
+ %lA = load <2 x i64>, ptr %A, align 16
+ %inc = getelementptr <2 x i64>, ptr %A, i32 1
+ store ptr %inc, ptr %ptr
ret <2 x i64> %lA
}
; Make sure we don't break smaller-than-dreg extloads.
-define <4 x i32> @zextload_v8i8tov8i32(<4 x i8>** %ptr) {
+define <4 x i32> @zextload_v8i8tov8i32(ptr %ptr) {
;CHECK-LABEL: zextload_v8i8tov8i32:
;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [{{r[0-9]+}}:32]
;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
- %A = load <4 x i8>*, <4 x i8>** %ptr
- %lA = load <4 x i8>, <4 x i8>* %A, align 4
+ %A = load ptr, ptr %ptr
+ %lA = load <4 x i8>, ptr %A, align 4
%zlA = zext <4 x i8> %lA to <4 x i32>
ret <4 x i32> %zlA
}
-define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) {
+define <4 x i32> @zextload_v8i8tov8i32_fake_update(ptr %ptr) {
;CHECK-LABEL: zextload_v8i8tov8i32_fake_update:
;CHECK: ldr r[[PTRREG:[0-9]+]], [r0]
;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r[[PTRREG]]:32]
@@ -244,10 +244,10 @@ define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) {
;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
;CHECK: add.w r[[INCREG:[0-9]+]], r[[PTRREG]], #16
;CHECK: str r[[INCREG]], [r0]
- %A = load <4 x i8>*, <4 x i8>** %ptr
- %lA = load <4 x i8>, <4 x i8>* %A, align 4
- %inc = getelementptr <4 x i8>, <4 x i8>* %A, i38 4
- store <4 x i8>* %inc, <4 x i8>** %ptr
+ %A = load ptr, ptr %ptr
+ %lA = load <4 x i8>, ptr %A, align 4
+ %inc = getelementptr <4 x i8>, ptr %A, i38 4
+ store ptr %inc, ptr %ptr
%zlA = zext <4 x i8> %lA to <4 x i32>
ret <4 x i32> %zlA
}
@@ -257,17 +257,17 @@ define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) {
; CHECK: vld1.8 {d{{[0-9]+}}}, [r0:64]!
; CHECK: ldr {{r[0-9]+}}, [r0]
-define void @test_silly_load(<28 x i8>* %addr) {
- load volatile <28 x i8>, <28 x i8>* %addr
+define void @test_silly_load(ptr %addr) {
+ load volatile <28 x i8>, ptr %addr
ret void
}
-define <4 x i32>* @test_vld1_immoffset(<4 x i32>* %ptr.in, <4 x i32>* %ptr.out) {
+define ptr @test_vld1_immoffset(ptr %ptr.in, ptr %ptr.out) {
; CHECK-LABEL: test_vld1_immoffset:
; CHECK: movs [[INC:r[0-9]+]], #32
; CHECK: vld1.32 {{{d[0-9]+}}, {{d[0-9]+}}}, [r0], [[INC]]
- %val = load <4 x i32>, <4 x i32>* %ptr.in
- store <4 x i32> %val, <4 x i32>* %ptr.out
- %next = getelementptr <4 x i32>, <4 x i32>* %ptr.in, i32 2
- ret <4 x i32>* %next
+ %val = load <4 x i32>, ptr %ptr.in
+ store <4 x i32> %val, ptr %ptr.out
+ %next = getelementptr <4 x i32>, ptr %ptr.in, i32 2
+ ret ptr %next
}
diff --git a/llvm/test/CodeGen/ARM/vector-promotion.ll b/llvm/test/CodeGen/ARM/vector-promotion.ll
index 014b61c69f88f..3e314306ff083 100644
--- a/llvm/test/CodeGen/ARM/vector-promotion.ll
+++ b/llvm/test/CodeGen/ARM/vector-promotion.ll
@@ -3,10 +3,10 @@
; RUN: llc -mtriple=thumbv7-apple-ios %s -o - -mattr=+neon | FileCheck --check-prefix=ASM %s
; IR-BOTH-LABEL: @simpleOneInstructionPromotion
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, ptr %addr1
; IR-BOTH-NEXT: [[VECTOR_OR:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[LOAD]], <i32 undef, i32 1>
; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[VECTOR_OR]], i32 1
-; IR-BOTH-NEXT: store i32 [[EXTRACT]], i32* %dest
+; IR-BOTH-NEXT: store i32 [[EXTRACT]], ptr %dest
; IR-BOTH-NEXT: ret
;
; Make sure we got rid of any expensive vmov.32 instructions.
@@ -15,62 +15,62 @@
; ASM-NEXT: vorr.i32 [[LOAD]], #0x1
; ASM-NEXT: vst1.32 {[[LOAD]][1]}, [r1:32]
; ASM-NEXT: bx
-define void @simpleOneInstructionPromotion(<2 x i32>* %addr1, i32* %dest) {
- %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
+define void @simpleOneInstructionPromotion(ptr %addr1, ptr %dest) {
+ %in1 = load <2 x i32>, ptr %addr1, align 8
%extract = extractelement <2 x i32> %in1, i32 1
%out = or i32 %extract, 1
- store i32 %out, i32* %dest, align 4
+ store i32 %out, ptr %dest, align 4
ret void
}
; IR-BOTH-LABEL: @unsupportedInstructionForPromotion
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, ptr %addr1
; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 0
; IR-BOTH-NEXT: [[CMP:%[a-zA-Z_0-9-]+]] = icmp eq i32 [[EXTRACT]], %in2
-; IR-BOTH-NEXT: store i1 [[CMP]], i1* %dest
+; IR-BOTH-NEXT: store i1 [[CMP]], ptr %dest
; IR-BOTH-NEXT: ret
;
; ASM-LABEL: unsupportedInstructionForPromotion:
; ASM: vldr [[LOAD:d[0-9]+]], [r0]
; ASM: vmov.32 {{r[0-9]+}}, [[LOAD]]
; ASM: bx
-define void @unsupportedInstructionForPromotion(<2 x i32>* %addr1, i32 %in2, i1* %dest) {
- %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
+define void @unsupportedInstructionForPromotion(ptr %addr1, i32 %in2, ptr %dest) {
+ %in1 = load <2 x i32>, ptr %addr1, align 8
%extract = extractelement <2 x i32> %in1, i32 0
%out = icmp eq i32 %extract, %in2
- store i1 %out, i1* %dest, align 4
+ store i1 %out, ptr %dest, align 4
ret void
}
; IR-BOTH-LABEL: @unsupportedChainInDifferentBBs
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, ptr %addr1
; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 0
; IR-BOTH-NEXT: br i1 %bool, label %bb2, label %end
; BB2
; IR-BOTH: [[OR:%[a-zA-Z_0-9-]+]] = or i32 [[EXTRACT]], 1
-; IR-BOTH-NEXT: store i32 [[OR]], i32* %dest, align 4
+; IR-BOTH-NEXT: store i32 [[OR]], ptr %dest, align 4
; IR-BOTH: ret
;
; ASM-LABEL: unsupportedChainInDifferentBBs:
; ASM: vldr [[LOAD:d[0-9]+]], [r0]
; ASM: vmov.32 {{r[0-9]+}}, [[LOAD]]
; ASM: bx
-define void @unsupportedChainInDifferentBBs(<2 x i32>* %addr1, i32* %dest, i1 %bool) {
+define void @unsupportedChainInDifferentBBs(ptr %addr1, ptr %dest, i1 %bool) {
bb1:
- %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
+ %in1 = load <2 x i32>, ptr %addr1, align 8
%extract = extractelement <2 x i32> %in1, i32 0
br i1 %bool, label %bb2, label %end
bb2:
%out = or i32 %extract, 1
- store i32 %out, i32* %dest, align 4
+ store i32 %out, ptr %dest, align 4
br label %end
end:
ret void
}
; IR-LABEL: @chainOfInstructionsToPromote
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, ptr %addr1
; IR-BOTH-NEXT: [[VECTOR_OR1:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[LOAD]], <i32 1, i32 undef>
; IR-BOTH-NEXT: [[VECTOR_OR2:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[VECTOR_OR1]], <i32 1, i32 undef>
; IR-BOTH-NEXT: [[VECTOR_OR3:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[VECTOR_OR2]], <i32 1, i32 undef>
@@ -79,15 +79,15 @@ end:
; IR-BOTH-NEXT: [[VECTOR_OR6:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[VECTOR_OR5]], <i32 1, i32 undef>
; IR-BOTH-NEXT: [[VECTOR_OR7:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[VECTOR_OR6]], <i32 1, i32 undef>
; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[VECTOR_OR7]], i32 0
-; IR-BOTH-NEXT: store i32 [[EXTRACT]], i32* %dest
+; IR-BOTH-NEXT: store i32 [[EXTRACT]], ptr %dest
; IR-BOTH-NEXT: ret
;
; ASM-LABEL: chainOfInstructionsToPromote:
; ASM: vldr [[LOAD:d[0-9]+]], [r0]
; ASM-NOT: vmov.32 {{r[0-9]+}}, [[LOAD]]
; ASM: bx
-define void @chainOfInstructionsToPromote(<2 x i32>* %addr1, i32* %dest) {
- %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
+define void @chainOfInstructionsToPromote(ptr %addr1, ptr %dest) {
+ %in1 = load <2 x i32>, ptr %addr1, align 8
%extract = extractelement <2 x i32> %in1, i32 0
%out1 = or i32 %extract, 1
%out2 = or i32 %out1, 1
@@ -96,33 +96,33 @@ define void @chainOfInstructionsToPromote(<2 x i32>* %addr1, i32* %dest) {
%out5 = or i32 %out4, 1
%out6 = or i32 %out5, 1
%out7 = or i32 %out6, 1
- store i32 %out7, i32* %dest, align 4
+ store i32 %out7, ptr %dest, align 4
ret void
}
; IR-BOTH-LABEL: @unsupportedMultiUses
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, ptr %addr1
; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
; IR-BOTH-NEXT: [[OR:%[a-zA-Z_0-9-]+]] = or i32 [[EXTRACT]], 1
-; IR-BOTH-NEXT: store i32 [[OR]], i32* %dest
+; IR-BOTH-NEXT: store i32 [[OR]], ptr %dest
; IR-BOTH-NEXT: ret i32 [[OR]]
;
; ASM-LABEL: unsupportedMultiUses:
; ASM: vldr [[LOAD:d[0-9]+]], [r0]
; ASM: vmov.32 {{r[0-9]+}}, [[LOAD]]
; ASM: bx
-define i32 @unsupportedMultiUses(<2 x i32>* %addr1, i32* %dest) {
- %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
+define i32 @unsupportedMultiUses(ptr %addr1, ptr %dest) {
+ %in1 = load <2 x i32>, ptr %addr1, align 8
%extract = extractelement <2 x i32> %in1, i32 1
%out = or i32 %extract, 1
- store i32 %out, i32* %dest, align 4
+ store i32 %out, ptr %dest, align 4
ret i32 %out
}
; Check that we promote we a splat constant when this is a division.
; The NORMAL mode does not promote anything as divisions are not legal.
; IR-BOTH-LABEL: @udivCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, ptr %addr1
; Scalar version:
; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 [[EXTRACT]], 7
@@ -130,18 +130,18 @@ define i32 @unsupportedMultiUses(<2 x i32>* %addr1, i32* %dest) {
; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = udiv <2 x i32> [[LOAD]], <i32 7, i32 7>
; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1
;
-; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
+; IR-BOTH-NEXT: store i32 [[RES]], ptr %dest
; IR-BOTH-NEXT: ret
-define void @udivCase(<2 x i32>* %addr1, i32* %dest) {
- %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
+define void @udivCase(ptr %addr1, ptr %dest) {
+ %in1 = load <2 x i32>, ptr %addr1, align 8
%extract = extractelement <2 x i32> %in1, i32 1
%out = udiv i32 %extract, 7
- store i32 %out, i32* %dest, align 4
+ store i32 %out, ptr %dest, align 4
ret void
}
; IR-BOTH-LABEL: @uremCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, ptr %addr1
; Scalar version:
; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = urem i32 [[EXTRACT]], 7
@@ -149,18 +149,18 @@ define void @udivCase(<2 x i32>* %addr1, i32* %dest) {
; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = urem <2 x i32> [[LOAD]], <i32 7, i32 7>
; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1
;
-; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
+; IR-BOTH-NEXT: store i32 [[RES]], ptr %dest
; IR-BOTH-NEXT: ret
-define void @uremCase(<2 x i32>* %addr1, i32* %dest) {
- %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
+define void @uremCase(ptr %addr1, ptr %dest) {
+ %in1 = load <2 x i32>, ptr %addr1, align 8
%extract = extractelement <2 x i32> %in1, i32 1
%out = urem i32 %extract, 7
- store i32 %out, i32* %dest, align 4
+ store i32 %out, ptr %dest, align 4
ret void
}
; IR-BOTH-LABEL: @sdivCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, ptr %addr1
; Scalar version:
; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sdiv i32 [[EXTRACT]], 7
@@ -168,18 +168,18 @@ define void @uremCase(<2 x i32>* %addr1, i32* %dest) {
; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = sdiv <2 x i32> [[LOAD]], <i32 7, i32 7>
; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1
;
-; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
+; IR-BOTH-NEXT: store i32 [[RES]], ptr %dest
; IR-BOTH-NEXT: ret
-define void @sdivCase(<2 x i32>* %addr1, i32* %dest) {
- %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
+define void @sdivCase(ptr %addr1, ptr %dest) {
+ %in1 = load <2 x i32>, ptr %addr1, align 8
%extract = extractelement <2 x i32> %in1, i32 1
%out = sdiv i32 %extract, 7
- store i32 %out, i32* %dest, align 4
+ store i32 %out, ptr %dest, align 4
ret void
}
; IR-BOTH-LABEL: @sremCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, ptr %addr1
; Scalar version:
; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = srem i32 [[EXTRACT]], 7
@@ -187,18 +187,18 @@ define void @sdivCase(<2 x i32>* %addr1, i32* %dest) {
; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = srem <2 x i32> [[LOAD]], <i32 7, i32 7>
; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1
;
-; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
+; IR-BOTH-NEXT: store i32 [[RES]], ptr %dest
; IR-BOTH-NEXT: ret
-define void @sremCase(<2 x i32>* %addr1, i32* %dest) {
- %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
+define void @sremCase(ptr %addr1, ptr %dest) {
+ %in1 = load <2 x i32>, ptr %addr1, align 8
%extract = extractelement <2 x i32> %in1, i32 1
%out = srem i32 %extract, 7
- store i32 %out, i32* %dest, align 4
+ store i32 %out, ptr %dest, align 4
ret void
}
; IR-BOTH-LABEL: @fdivCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, ptr %addr1
; Scalar version:
; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1
; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = fdiv float [[EXTRACT]], 7.0
@@ -206,18 +206,18 @@ define void @sremCase(<2 x i32>* %addr1, i32* %dest) {
; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = fdiv <2 x float> [[LOAD]], <float 7.000000e+00, float 7.000000e+00>
; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[DIV]], i32 1
;
-; IR-BOTH-NEXT: store float [[RES]], float* %dest
+; IR-BOTH-NEXT: store float [[RES]], ptr %dest
; IR-BOTH-NEXT: ret
-define void @fdivCase(<2 x float>* %addr1, float* %dest) {
- %in1 = load <2 x float>, <2 x float>* %addr1, align 8
+define void @fdivCase(ptr %addr1, ptr %dest) {
+ %in1 = load <2 x float>, ptr %addr1, align 8
%extract = extractelement <2 x float> %in1, i32 1
%out = fdiv float %extract, 7.0
- store float %out, float* %dest, align 4
+ store float %out, ptr %dest, align 4
ret void
}
; IR-BOTH-LABEL: @fremCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, ptr %addr1
; Scalar version:
; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1
; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = frem float [[EXTRACT]], 7.0
@@ -225,29 +225,29 @@ define void @fdivCase(<2 x float>* %addr1, float* %dest) {
; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = frem <2 x float> [[LOAD]], <float 7.000000e+00, float 7.000000e+00>
; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[DIV]], i32 1
;
-; IR-BOTH-NEXT: store float [[RES]], float* %dest
+; IR-BOTH-NEXT: store float [[RES]], ptr %dest
; IR-BOTH-NEXT: ret
-define void @fremCase(<2 x float>* %addr1, float* %dest) {
- %in1 = load <2 x float>, <2 x float>* %addr1, align 8
+define void @fremCase(ptr %addr1, ptr %dest) {
+ %in1 = load <2 x float>, ptr %addr1, align 8
%extract = extractelement <2 x float> %in1, i32 1
%out = frem float %extract, 7.0
- store float %out, float* %dest, align 4
+ store float %out, ptr %dest, align 4
ret void
}
; Check that we do not promote when we may introduce undefined behavior
; like division by zero.
; IR-BOTH-LABEL: @undefDivCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, ptr %addr1
; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
; IR-BOTH-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 7, [[EXTRACT]]
-; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
+; IR-BOTH-NEXT: store i32 [[RES]], ptr %dest
; IR-BOTH-NEXT: ret
-define void @undefDivCase(<2 x i32>* %addr1, i32* %dest) {
- %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
+define void @undefDivCase(ptr %addr1, ptr %dest) {
+ %in1 = load <2 x i32>, ptr %addr1, align 8
%extract = extractelement <2 x i32> %in1, i32 1
%out = udiv i32 7, %extract
- store i32 %out, i32* %dest, align 4
+ store i32 %out, ptr %dest, align 4
ret void
}
@@ -255,23 +255,23 @@ define void @undefDivCase(<2 x i32>* %addr1, i32* %dest) {
; Check that we do not promote when we may introduce undefined behavior
; like division by zero.
; IR-BOTH-LABEL: @undefRemCase
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, ptr %addr1
; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
; IR-BOTH-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = srem i32 7, [[EXTRACT]]
-; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
+; IR-BOTH-NEXT: store i32 [[RES]], ptr %dest
; IR-BOTH-NEXT: ret
-define void @undefRemCase(<2 x i32>* %addr1, i32* %dest) {
- %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
+define void @undefRemCase(ptr %addr1, ptr %dest) {
+ %in1 = load <2 x i32>, ptr %addr1, align 8
%extract = extractelement <2 x i32> %in1, i32 1
%out = srem i32 7, %extract
- store i32 %out, i32* %dest, align 4
+ store i32 %out, ptr %dest, align 4
ret void
}
; Check that we use an undef mask for undefined behavior if the fast-math
; flag is set.
; IR-BOTH-LABEL: @undefConstantFRemCaseWithFastMath
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, ptr %addr1
; Scalar version:
; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1
; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = frem nnan float [[EXTRACT]], 7.0
@@ -279,20 +279,20 @@ define void @undefRemCase(<2 x i32>* %addr1, i32* %dest) {
; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = frem nnan <2 x float> [[LOAD]], <float undef, float 7.000000e+00>
; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[DIV]], i32 1
;
-; IR-BOTH-NEXT: store float [[RES]], float* %dest
+; IR-BOTH-NEXT: store float [[RES]], ptr %dest
; IR-BOTH-NEXT: ret
-define void @undefConstantFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest) {
- %in1 = load <2 x float>, <2 x float>* %addr1, align 8
+define void @undefConstantFRemCaseWithFastMath(ptr %addr1, ptr %dest) {
+ %in1 = load <2 x float>, ptr %addr1, align 8
%extract = extractelement <2 x float> %in1, i32 1
%out = frem nnan float %extract, 7.0
- store float %out, float* %dest, align 4
+ store float %out, ptr %dest, align 4
ret void
}
; Check that we use an undef mask for undefined behavior if the fast-math
; flag is set.
; IR-BOTH-LABEL: @undefVectorFRemCaseWithFastMath
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, ptr %addr1
; Scalar version:
; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1
; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = frem nnan float 7.000000e+00, [[EXTRACT]]
@@ -300,13 +300,13 @@ define void @undefConstantFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest
; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = frem nnan <2 x float> <float undef, float 7.000000e+00>, [[LOAD]]
; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[DIV]], i32 1
;
-; IR-BOTH-NEXT: store float [[RES]], float* %dest
+; IR-BOTH-NEXT: store float [[RES]], ptr %dest
; IR-BOTH-NEXT: ret
-define void @undefVectorFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest) {
- %in1 = load <2 x float>, <2 x float>* %addr1, align 8
+define void @undefVectorFRemCaseWithFastMath(ptr %addr1, ptr %dest) {
+ %in1 = load <2 x float>, ptr %addr1, align 8
%extract = extractelement <2 x float> %in1, i32 1
%out = frem nnan float 7.0, %extract
- store float %out, float* %dest, align 4
+ store float %out, ptr %dest, align 4
ret void
}
@@ -314,7 +314,7 @@ define void @undefVectorFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest)
; This requires the STRESS mode, as floating point value are
; not promote on armv7.
; IR-BOTH-LABEL: @simpleOneInstructionPromotionFloat
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, ptr %addr1
; Scalar version:
; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1
; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = fadd float [[EXTRACT]], 1.0
@@ -322,13 +322,13 @@ define void @undefVectorFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest)
; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = fadd <2 x float> [[LOAD]], <float undef, float 1.000000e+00>
; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[DIV]], i32 1
;
-; IR-BOTH-NEXT: store float [[RES]], float* %dest
+; IR-BOTH-NEXT: store float [[RES]], ptr %dest
; IR-BOTH-NEXT: ret
-define void @simpleOneInstructionPromotionFloat(<2 x float>* %addr1, float* %dest) {
- %in1 = load <2 x float>, <2 x float>* %addr1, align 8
+define void @simpleOneInstructionPromotionFloat(ptr %addr1, ptr %dest) {
+ %in1 = load <2 x float>, ptr %addr1, align 8
%extract = extractelement <2 x float> %in1, i32 1
%out = fadd float %extract, 1.0
- store float %out, float* %dest, align 4
+ store float %out, ptr %dest, align 4
ret void
}
@@ -337,7 +337,7 @@ define void @simpleOneInstructionPromotionFloat(<2 x float>* %addr1, float* %des
; This requires the STRESS modes, as variable index are expensive
; to lower.
; IR-BOTH-LABEL: @simpleOneInstructionPromotionVariableIdx
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, ptr %addr1
; Scalar version:
; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 %idx
; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = or i32 [[EXTRACT]], 1
@@ -345,38 +345,38 @@ define void @simpleOneInstructionPromotionFloat(<2 x float>* %addr1, float* %des
; IR-STRESS-NEXT: [[OR:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[LOAD]], <i32 1, i32 1>
; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[OR]], i32 %idx
;
-; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
+; IR-BOTH-NEXT: store i32 [[RES]], ptr %dest
; IR-BOTH-NEXT: ret
-define void @simpleOneInstructionPromotionVariableIdx(<2 x i32>* %addr1, i32* %dest, i32 %idx) {
- %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
+define void @simpleOneInstructionPromotionVariableIdx(ptr %addr1, ptr %dest, i32 %idx) {
+ %in1 = load <2 x i32>, ptr %addr1, align 8
%extract = extractelement <2 x i32> %in1, i32 %idx
%out = or i32 %extract, 1
- store i32 %out, i32* %dest, align 4
+ store i32 %out, ptr %dest, align 4
ret void
}
; Check a vector with more than 2 elements.
; IR-BOTH-LABEL: @simpleOneInstructionPromotion8x8
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <8 x i8>, <8 x i8>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <8 x i8>, ptr %addr1
; IR-BOTH-NEXT: [[OR:%[a-zA-Z_0-9-]+]] = or <8 x i8> [[LOAD]], <i8 undef, i8 1, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>
; IR-BOTH-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <8 x i8> [[OR]], i32 1
-; IR-BOTH-NEXT: store i8 [[RES]], i8* %dest
+; IR-BOTH-NEXT: store i8 [[RES]], ptr %dest
; IR-BOTH-NEXT: ret
-define void @simpleOneInstructionPromotion8x8(<8 x i8>* %addr1, i8* %dest) {
- %in1 = load <8 x i8>, <8 x i8>* %addr1, align 8
+define void @simpleOneInstructionPromotion8x8(ptr %addr1, ptr %dest) {
+ %in1 = load <8 x i8>, ptr %addr1, align 8
%extract = extractelement <8 x i8> %in1, i32 1
%out = or i8 %extract, 1
- store i8 %out, i8* %dest, align 4
+ store i8 %out, ptr %dest, align 4
ret void
}
; Check that we optimized the sequence correctly when it can be
; lowered on a Q register.
; IR-BOTH-LABEL: @simpleOneInstructionPromotion
-; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <4 x i32>, <4 x i32>* %addr1
+; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <4 x i32>, ptr %addr1
; IR-BOTH-NEXT: [[VECTOR_OR:%[a-zA-Z_0-9-]+]] = or <4 x i32> [[LOAD]], <i32 undef, i32 1, i32 undef, i32 undef>
; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <4 x i32> [[VECTOR_OR]], i32 1
-; IR-BOTH-NEXT: store i32 [[EXTRACT]], i32* %dest
+; IR-BOTH-NEXT: store i32 [[EXTRACT]], ptr %dest
; IR-BOTH-NEXT: ret
;
; Make sure we got rid of any expensive vmov.32 instructions.
@@ -386,10 +386,10 @@ define void @simpleOneInstructionPromotion8x8(<8 x i8>* %addr1, i8* %dest) {
; ASM-NEXT: vorr.i32 q{{[[0-9]+}}, #0x1
; ASM-NEXT: vst1.32 {[[LOAD]][1]}, [r1]
; ASM-NEXT: bx
-define void @simpleOneInstructionPromotion4x32(<4 x i32>* %addr1, i32* %dest) {
- %in1 = load <4 x i32>, <4 x i32>* %addr1, align 8
+define void @simpleOneInstructionPromotion4x32(ptr %addr1, ptr %dest) {
+ %in1 = load <4 x i32>, ptr %addr1, align 8
%extract = extractelement <4 x i32> %in1, i32 1
%out = or i32 %extract, 1
- store i32 %out, i32* %dest, align 1
+ store i32 %out, ptr %dest, align 1
ret void
}
diff --git a/llvm/test/CodeGen/ARM/vector-spilling.ll b/llvm/test/CodeGen/ARM/vector-spilling.ll
index 2d77393d65a8a..5dc20a8aa9b1b 100644
--- a/llvm/test/CodeGen/ARM/vector-spilling.ll
+++ b/llvm/test/CodeGen/ARM/vector-spilling.ll
@@ -8,24 +8,23 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
; CHECK: test:
; CHECK: vstmia
; CHECK: vldmia
-define void @test(<8 x i64>* %src) #0 {
+define void @test(ptr %src) #0 {
entry:
- %0 = getelementptr inbounds <8 x i64>, <8 x i64>* %src, i32 0
- %1 = load <8 x i64>, <8 x i64>* %0, align 8
+ %0 = load <8 x i64>, ptr %src, align 8
- %2 = getelementptr inbounds <8 x i64>, <8 x i64>* %src, i32 1
- %3 = load <8 x i64>, <8 x i64>* %2, align 8
+ %1 = getelementptr inbounds <8 x i64>, ptr %src, i32 1
+ %2 = load <8 x i64>, ptr %1, align 8
- %4 = getelementptr inbounds <8 x i64>, <8 x i64>* %src, i32 2
- %5 = load <8 x i64>, <8 x i64>* %4, align 8
+ %3 = getelementptr inbounds <8 x i64>, ptr %src, i32 2
+ %4 = load <8 x i64>, ptr %3, align 8
- %6 = getelementptr inbounds <8 x i64>, <8 x i64>* %src, i32 3
- %7 = load <8 x i64>, <8 x i64>* %6, align 8
+ %5 = getelementptr inbounds <8 x i64>, ptr %src, i32 3
+ %6 = load <8 x i64>, ptr %5, align 8
- %8 = shufflevector <8 x i64> %1, <8 x i64> %3, <8 x i32> <i32 12, i32 4, i32 15, i32 14, i32 8, i32 13, i32 2, i32 9>
- %9 = shufflevector <8 x i64> %1, <8 x i64> %3, <8 x i32> <i32 1, i32 0, i32 3, i32 10, i32 5, i32 11, i32 7, i32 6>
+ %7 = shufflevector <8 x i64> %0, <8 x i64> %2, <8 x i32> <i32 12, i32 4, i32 15, i32 14, i32 8, i32 13, i32 2, i32 9>
+ %8 = shufflevector <8 x i64> %0, <8 x i64> %2, <8 x i32> <i32 1, i32 0, i32 3, i32 10, i32 5, i32 11, i32 7, i32 6>
- tail call void(<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>) @foo(<8 x i64> %1, <8 x i64> %3, <8 x i64> %5, <8 x i64> %7, <8 x i64> %8, <8 x i64> %9)
+ tail call void(<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>) @foo(<8 x i64> %0, <8 x i64> %2, <8 x i64> %4, <8 x i64> %6, <8 x i64> %7, <8 x i64> %8)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/vector-store.ll b/llvm/test/CodeGen/ARM/vector-store.ll
index 5d799be33505c..a8a1031637afc 100644
--- a/llvm/test/CodeGen/ARM/vector-store.ll
+++ b/llvm/test/CodeGen/ARM/vector-store.ll
@@ -4,19 +4,19 @@
target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
target triple = "thumbv7-none-eabi"
-define void @store_v8i8(<8 x i8>** %ptr, <8 x i8> %val) {
+define void @store_v8i8(ptr %ptr, <8 x i8> %val) {
; CHECK-LABEL: store_v8i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0]
; CHECK-NEXT: str r3, [r0, #4]
; CHECK-NEXT: str r2, [r0]
; CHECK-NEXT: bx lr
- %A = load <8 x i8>*, <8 x i8>** %ptr
- store <8 x i8> %val, <8 x i8>* %A, align 1
+ %A = load ptr, ptr %ptr
+ store <8 x i8> %val, ptr %A, align 1
ret void
}
-define void @store_v8i8_update(<8 x i8>** %ptr, <8 x i8> %val) {
+define void @store_v8i8_update(ptr %ptr, <8 x i8> %val) {
; CHECK-LABEL: store_v8i8_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r1, [r0]
@@ -24,26 +24,26 @@ define void @store_v8i8_update(<8 x i8>** %ptr, <8 x i8> %val) {
; CHECK-NEXT: vst1.8 {d16}, [r1]!
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %A = load <8 x i8>*, <8 x i8>** %ptr
- store <8 x i8> %val, <8 x i8>* %A, align 1
- %inc = getelementptr <8 x i8>, <8 x i8>* %A, i38 1
- store <8 x i8>* %inc, <8 x i8>** %ptr
+ %A = load ptr, ptr %ptr
+ store <8 x i8> %val, ptr %A, align 1
+ %inc = getelementptr <8 x i8>, ptr %A, i38 1
+ store ptr %inc, ptr %ptr
ret void
}
-define void @store_v4i16(<4 x i16>** %ptr, <4 x i16> %val) {
+define void @store_v4i16(ptr %ptr, <4 x i16> %val) {
; CHECK-LABEL: store_v4i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0]
; CHECK-NEXT: str r3, [r0, #4]
; CHECK-NEXT: str r2, [r0]
; CHECK-NEXT: bx lr
- %A = load <4 x i16>*, <4 x i16>** %ptr
- store <4 x i16> %val, <4 x i16>* %A, align 1
+ %A = load ptr, ptr %ptr
+ store <4 x i16> %val, ptr %A, align 1
ret void
}
-define void @store_v4i16_update(<4 x i16>** %ptr, <4 x i16> %val) {
+define void @store_v4i16_update(ptr %ptr, <4 x i16> %val) {
; CHECK-LABEL: store_v4i16_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r1, [r0]
@@ -51,26 +51,26 @@ define void @store_v4i16_update(<4 x i16>** %ptr, <4 x i16> %val) {
; CHECK-NEXT: vst1.8 {d16}, [r1]!
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %A = load <4 x i16>*, <4 x i16>** %ptr
- store <4 x i16> %val, <4 x i16>* %A, align 1
- %inc = getelementptr <4 x i16>, <4 x i16>* %A, i34 1
- store <4 x i16>* %inc, <4 x i16>** %ptr
+ %A = load ptr, ptr %ptr
+ store <4 x i16> %val, ptr %A, align 1
+ %inc = getelementptr <4 x i16>, ptr %A, i34 1
+ store ptr %inc, ptr %ptr
ret void
}
-define void @store_v2i32(<2 x i32>** %ptr, <2 x i32> %val) {
+define void @store_v2i32(ptr %ptr, <2 x i32> %val) {
; CHECK-LABEL: store_v2i32:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0]
; CHECK-NEXT: str r3, [r0, #4]
; CHECK-NEXT: str r2, [r0]
; CHECK-NEXT: bx lr
- %A = load <2 x i32>*, <2 x i32>** %ptr
- store <2 x i32> %val, <2 x i32>* %A, align 1
+ %A = load ptr, ptr %ptr
+ store <2 x i32> %val, ptr %A, align 1
ret void
}
-define void @store_v2i32_update(<2 x i32>** %ptr, <2 x i32> %val) {
+define void @store_v2i32_update(ptr %ptr, <2 x i32> %val) {
; CHECK-LABEL: store_v2i32_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r1, [r0]
@@ -78,26 +78,26 @@ define void @store_v2i32_update(<2 x i32>** %ptr, <2 x i32> %val) {
; CHECK-NEXT: vst1.8 {d16}, [r1]!
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %A = load <2 x i32>*, <2 x i32>** %ptr
- store <2 x i32> %val, <2 x i32>* %A, align 1
- %inc = getelementptr <2 x i32>, <2 x i32>* %A, i32 1
- store <2 x i32>* %inc, <2 x i32>** %ptr
+ %A = load ptr, ptr %ptr
+ store <2 x i32> %val, ptr %A, align 1
+ %inc = getelementptr <2 x i32>, ptr %A, i32 1
+ store ptr %inc, ptr %ptr
ret void
}
-define void @store_v2f32(<2 x float>** %ptr, <2 x float> %val) {
+define void @store_v2f32(ptr %ptr, <2 x float> %val) {
; CHECK-LABEL: store_v2f32:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0]
; CHECK-NEXT: str r3, [r0, #4]
; CHECK-NEXT: str r2, [r0]
; CHECK-NEXT: bx lr
- %A = load <2 x float>*, <2 x float>** %ptr
- store <2 x float> %val, <2 x float>* %A, align 1
+ %A = load ptr, ptr %ptr
+ store <2 x float> %val, ptr %A, align 1
ret void
}
-define void @store_v2f32_update(<2 x float>** %ptr, <2 x float> %val) {
+define void @store_v2f32_update(ptr %ptr, <2 x float> %val) {
; CHECK-LABEL: store_v2f32_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r1, [r0]
@@ -105,26 +105,26 @@ define void @store_v2f32_update(<2 x float>** %ptr, <2 x float> %val) {
; CHECK-NEXT: vst1.8 {d16}, [r1]!
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %A = load <2 x float>*, <2 x float>** %ptr
- store <2 x float> %val, <2 x float>* %A, align 1
- %inc = getelementptr <2 x float>, <2 x float>* %A, i32 1
- store <2 x float>* %inc, <2 x float>** %ptr
+ %A = load ptr, ptr %ptr
+ store <2 x float> %val, ptr %A, align 1
+ %inc = getelementptr <2 x float>, ptr %A, i32 1
+ store ptr %inc, ptr %ptr
ret void
}
-define void @store_v1i64(<1 x i64>** %ptr, <1 x i64> %val) {
+define void @store_v1i64(ptr %ptr, <1 x i64> %val) {
; CHECK-LABEL: store_v1i64:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0]
; CHECK-NEXT: str r3, [r0, #4]
; CHECK-NEXT: str r2, [r0]
; CHECK-NEXT: bx lr
- %A = load <1 x i64>*, <1 x i64>** %ptr
- store <1 x i64> %val, <1 x i64>* %A, align 1
+ %A = load ptr, ptr %ptr
+ store <1 x i64> %val, ptr %A, align 1
ret void
}
-define void @store_v1i64_update(<1 x i64>** %ptr, <1 x i64> %val) {
+define void @store_v1i64_update(ptr %ptr, <1 x i64> %val) {
; CHECK-LABEL: store_v1i64_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r1, [r0]
@@ -132,14 +132,14 @@ define void @store_v1i64_update(<1 x i64>** %ptr, <1 x i64> %val) {
; CHECK-NEXT: vst1.8 {d16}, [r1]!
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %A = load <1 x i64>*, <1 x i64>** %ptr
- store <1 x i64> %val, <1 x i64>* %A, align 1
- %inc = getelementptr <1 x i64>, <1 x i64>* %A, i31 1
- store <1 x i64>* %inc, <1 x i64>** %ptr
+ %A = load ptr, ptr %ptr
+ store <1 x i64> %val, ptr %A, align 1
+ %inc = getelementptr <1 x i64>, ptr %A, i31 1
+ store ptr %inc, ptr %ptr
ret void
}
-define void @store_v16i8(<16 x i8>** %ptr, <16 x i8> %val) {
+define void @store_v16i8(ptr %ptr, <16 x i8> %val) {
; CHECK-LABEL: store_v16i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -147,12 +147,12 @@ define void @store_v16i8(<16 x i8>** %ptr, <16 x i8> %val) {
; CHECK-NEXT: vmov d16, r2, r3
; CHECK-NEXT: vst1.8 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
- %A = load <16 x i8>*, <16 x i8>** %ptr
- store <16 x i8> %val, <16 x i8>* %A, align 1
+ %A = load ptr, ptr %ptr
+ store <16 x i8> %val, ptr %A, align 1
ret void
}
-define void @store_v16i8_update(<16 x i8>** %ptr, <16 x i8> %val) {
+define void @store_v16i8_update(ptr %ptr, <16 x i8> %val) {
; CHECK-LABEL: store_v16i8_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -161,14 +161,14 @@ define void @store_v16i8_update(<16 x i8>** %ptr, <16 x i8> %val) {
; CHECK-NEXT: vst1.8 {d16, d17}, [r1]!
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %A = load <16 x i8>*, <16 x i8>** %ptr
- store <16 x i8> %val, <16 x i8>* %A, align 1
- %inc = getelementptr <16 x i8>, <16 x i8>* %A, i316 1
- store <16 x i8>* %inc, <16 x i8>** %ptr
+ %A = load ptr, ptr %ptr
+ store <16 x i8> %val, ptr %A, align 1
+ %inc = getelementptr <16 x i8>, ptr %A, i316 1
+ store ptr %inc, ptr %ptr
ret void
}
-define void @store_v8i16(<8 x i16>** %ptr, <8 x i16> %val) {
+define void @store_v8i16(ptr %ptr, <8 x i16> %val) {
; CHECK-LABEL: store_v8i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -176,12 +176,12 @@ define void @store_v8i16(<8 x i16>** %ptr, <8 x i16> %val) {
; CHECK-NEXT: vmov d16, r2, r3
; CHECK-NEXT: vst1.8 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
- %A = load <8 x i16>*, <8 x i16>** %ptr
- store <8 x i16> %val, <8 x i16>* %A, align 1
+ %A = load ptr, ptr %ptr
+ store <8 x i16> %val, ptr %A, align 1
ret void
}
-define void @store_v8i16_update(<8 x i16>** %ptr, <8 x i16> %val) {
+define void @store_v8i16_update(ptr %ptr, <8 x i16> %val) {
; CHECK-LABEL: store_v8i16_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -190,14 +190,14 @@ define void @store_v8i16_update(<8 x i16>** %ptr, <8 x i16> %val) {
; CHECK-NEXT: vst1.8 {d16, d17}, [r1]!
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %A = load <8 x i16>*, <8 x i16>** %ptr
- store <8 x i16> %val, <8 x i16>* %A, align 1
- %inc = getelementptr <8 x i16>, <8 x i16>* %A, i38 1
- store <8 x i16>* %inc, <8 x i16>** %ptr
+ %A = load ptr, ptr %ptr
+ store <8 x i16> %val, ptr %A, align 1
+ %inc = getelementptr <8 x i16>, ptr %A, i38 1
+ store ptr %inc, ptr %ptr
ret void
}
-define void @store_v4i32(<4 x i32>** %ptr, <4 x i32> %val) {
+define void @store_v4i32(ptr %ptr, <4 x i32> %val) {
; CHECK-LABEL: store_v4i32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -205,12 +205,12 @@ define void @store_v4i32(<4 x i32>** %ptr, <4 x i32> %val) {
; CHECK-NEXT: vmov d16, r2, r3
; CHECK-NEXT: vst1.8 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
- %A = load <4 x i32>*, <4 x i32>** %ptr
- store <4 x i32> %val, <4 x i32>* %A, align 1
+ %A = load ptr, ptr %ptr
+ store <4 x i32> %val, ptr %A, align 1
ret void
}
-define void @store_v4i32_update(<4 x i32>** %ptr, <4 x i32> %val) {
+define void @store_v4i32_update(ptr %ptr, <4 x i32> %val) {
; CHECK-LABEL: store_v4i32_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -219,14 +219,14 @@ define void @store_v4i32_update(<4 x i32>** %ptr, <4 x i32> %val) {
; CHECK-NEXT: vst1.8 {d16, d17}, [r1]!
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %A = load <4 x i32>*, <4 x i32>** %ptr
- store <4 x i32> %val, <4 x i32>* %A, align 1
- %inc = getelementptr <4 x i32>, <4 x i32>* %A, i34 1
- store <4 x i32>* %inc, <4 x i32>** %ptr
+ %A = load ptr, ptr %ptr
+ store <4 x i32> %val, ptr %A, align 1
+ %inc = getelementptr <4 x i32>, ptr %A, i34 1
+ store ptr %inc, ptr %ptr
ret void
}
-define void @store_v4f32(<4 x float>** %ptr, <4 x float> %val) {
+define void @store_v4f32(ptr %ptr, <4 x float> %val) {
; CHECK-LABEL: store_v4f32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -234,12 +234,12 @@ define void @store_v4f32(<4 x float>** %ptr, <4 x float> %val) {
; CHECK-NEXT: vmov d16, r2, r3
; CHECK-NEXT: vst1.8 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
- %A = load <4 x float>*, <4 x float>** %ptr
- store <4 x float> %val, <4 x float>* %A, align 1
+ %A = load ptr, ptr %ptr
+ store <4 x float> %val, ptr %A, align 1
ret void
}
-define void @store_v4f32_update(<4 x float>** %ptr, <4 x float> %val) {
+define void @store_v4f32_update(ptr %ptr, <4 x float> %val) {
; CHECK-LABEL: store_v4f32_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -248,14 +248,14 @@ define void @store_v4f32_update(<4 x float>** %ptr, <4 x float> %val) {
; CHECK-NEXT: vst1.8 {d16, d17}, [r1]!
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %A = load <4 x float>*, <4 x float>** %ptr
- store <4 x float> %val, <4 x float>* %A, align 1
- %inc = getelementptr <4 x float>, <4 x float>* %A, i34 1
- store <4 x float>* %inc, <4 x float>** %ptr
+ %A = load ptr, ptr %ptr
+ store <4 x float> %val, ptr %A, align 1
+ %inc = getelementptr <4 x float>, ptr %A, i34 1
+ store ptr %inc, ptr %ptr
ret void
}
-define void @store_v2i64(<2 x i64>** %ptr, <2 x i64> %val) {
+define void @store_v2i64(ptr %ptr, <2 x i64> %val) {
; CHECK-LABEL: store_v2i64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -263,12 +263,12 @@ define void @store_v2i64(<2 x i64>** %ptr, <2 x i64> %val) {
; CHECK-NEXT: vmov d16, r2, r3
; CHECK-NEXT: vst1.8 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
- %A = load <2 x i64>*, <2 x i64>** %ptr
- store <2 x i64> %val, <2 x i64>* %A, align 1
+ %A = load ptr, ptr %ptr
+ store <2 x i64> %val, ptr %A, align 1
ret void
}
-define void @store_v2i64_update(<2 x i64>** %ptr, <2 x i64> %val) {
+define void @store_v2i64_update(ptr %ptr, <2 x i64> %val) {
; CHECK-LABEL: store_v2i64_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -277,14 +277,14 @@ define void @store_v2i64_update(<2 x i64>** %ptr, <2 x i64> %val) {
; CHECK-NEXT: vst1.8 {d16, d17}, [r1]!
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %A = load <2 x i64>*, <2 x i64>** %ptr
- store <2 x i64> %val, <2 x i64>* %A, align 1
- %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
+ %A = load ptr, ptr %ptr
+ store <2 x i64> %val, ptr %A, align 1
+ %inc = getelementptr <2 x i64>, ptr %A, i32 1
+ store ptr %inc, ptr %ptr
ret void
}
-define void @store_v2i64_update_aligned2(<2 x i64>** %ptr, <2 x i64> %val) {
+define void @store_v2i64_update_aligned2(ptr %ptr, <2 x i64> %val) {
; CHECK-LABEL: store_v2i64_update_aligned2:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -293,14 +293,14 @@ define void @store_v2i64_update_aligned2(<2 x i64>** %ptr, <2 x i64> %val) {
; CHECK-NEXT: vst1.16 {d16, d17}, [r1]!
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %A = load <2 x i64>*, <2 x i64>** %ptr
- store <2 x i64> %val, <2 x i64>* %A, align 2
- %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
+ %A = load ptr, ptr %ptr
+ store <2 x i64> %val, ptr %A, align 2
+ %inc = getelementptr <2 x i64>, ptr %A, i32 1
+ store ptr %inc, ptr %ptr
ret void
}
-define void @store_v2i64_update_aligned4(<2 x i64>** %ptr, <2 x i64> %val) {
+define void @store_v2i64_update_aligned4(ptr %ptr, <2 x i64> %val) {
; CHECK-LABEL: store_v2i64_update_aligned4:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -309,14 +309,14 @@ define void @store_v2i64_update_aligned4(<2 x i64>** %ptr, <2 x i64> %val) {
; CHECK-NEXT: vst1.32 {d16, d17}, [r1]!
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %A = load <2 x i64>*, <2 x i64>** %ptr
- store <2 x i64> %val, <2 x i64>* %A, align 4
- %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
+ %A = load ptr, ptr %ptr
+ store <2 x i64> %val, ptr %A, align 4
+ %inc = getelementptr <2 x i64>, ptr %A, i32 1
+ store ptr %inc, ptr %ptr
ret void
}
-define void @store_v2i64_update_aligned8(<2 x i64>** %ptr, <2 x i64> %val) {
+define void @store_v2i64_update_aligned8(ptr %ptr, <2 x i64> %val) {
; CHECK-LABEL: store_v2i64_update_aligned8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -325,14 +325,14 @@ define void @store_v2i64_update_aligned8(<2 x i64>** %ptr, <2 x i64> %val) {
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]!
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %A = load <2 x i64>*, <2 x i64>** %ptr
- store <2 x i64> %val, <2 x i64>* %A, align 8
- %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
+ %A = load ptr, ptr %ptr
+ store <2 x i64> %val, ptr %A, align 8
+ %inc = getelementptr <2 x i64>, ptr %A, i32 1
+ store ptr %inc, ptr %ptr
ret void
}
-define void @store_v2i64_update_aligned16(<2 x i64>** %ptr, <2 x i64> %val) {
+define void @store_v2i64_update_aligned16(ptr %ptr, <2 x i64> %val) {
; CHECK-LABEL: store_v2i64_update_aligned16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -341,14 +341,14 @@ define void @store_v2i64_update_aligned16(<2 x i64>** %ptr, <2 x i64> %val) {
; CHECK-NEXT: vst1.64 {d16, d17}, [r1:128]!
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %A = load <2 x i64>*, <2 x i64>** %ptr
- store <2 x i64> %val, <2 x i64>* %A, align 16
- %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
+ %A = load ptr, ptr %ptr
+ store <2 x i64> %val, ptr %A, align 16
+ %inc = getelementptr <2 x i64>, ptr %A, i32 1
+ store ptr %inc, ptr %ptr
ret void
}
-define void @truncstore_v4i32tov4i8(<4 x i8>** %ptr, <4 x i32> %val) {
+define void @truncstore_v4i32tov4i8(ptr %ptr, <4 x i32> %val) {
; CHECK-LABEL: truncstore_v4i32tov4i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -358,13 +358,13 @@ define void @truncstore_v4i32tov4i8(<4 x i8>** %ptr, <4 x i32> %val) {
; CHECK-NEXT: vuzp.8 d16, d17
; CHECK-NEXT: vst1.32 {d16[0]}, [r0:32]
; CHECK-NEXT: bx lr
- %A = load <4 x i8>*, <4 x i8>** %ptr
+ %A = load ptr, ptr %ptr
%trunc = trunc <4 x i32> %val to <4 x i8>
- store <4 x i8> %trunc, <4 x i8>* %A, align 4
+ store <4 x i8> %trunc, ptr %A, align 4
ret void
}
-define void @truncstore_v4i32tov4i8_fake_update(<4 x i8>** %ptr, <4 x i32> %val) {
+define void @truncstore_v4i32tov4i8_fake_update(ptr %ptr, <4 x i32> %val) {
; CHECK-LABEL: truncstore_v4i32tov4i8_fake_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [sp]
@@ -376,15 +376,15 @@ define void @truncstore_v4i32tov4i8_fake_update(<4 x i8>** %ptr, <4 x i32> %val)
; CHECK-NEXT: vst1.32 {d16[0]}, [r1:32], r2
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: bx lr
- %A = load <4 x i8>*, <4 x i8>** %ptr
+ %A = load ptr, ptr %ptr
%trunc = trunc <4 x i32> %val to <4 x i8>
- store <4 x i8> %trunc, <4 x i8>* %A, align 4
- %inc = getelementptr <4 x i8>, <4 x i8>* %A, i38 4
- store <4 x i8>* %inc, <4 x i8>** %ptr
+ store <4 x i8> %trunc, ptr %A, align 4
+ %inc = getelementptr <4 x i8>, ptr %A, i38 4
+ store ptr %inc, ptr %ptr
ret void
}
-define <4 x i32>* @test_vst1_1reg(<4 x i32>* %ptr.in, <4 x i32>* %ptr.out) {
+define ptr @test_vst1_1reg(ptr %ptr.in, ptr %ptr.out) {
; CHECK-LABEL: test_vst1_1reg:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -392,14 +392,14 @@ define <4 x i32>* @test_vst1_1reg(<4 x i32>* %ptr.in, <4 x i32>* %ptr.out) {
; CHECK-NEXT: vst1.32 {d16, d17}, [r1], r0
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bx lr
- %val = load <4 x i32>, <4 x i32>* %ptr.in
- store <4 x i32> %val, <4 x i32>* %ptr.out
- %next = getelementptr <4 x i32>, <4 x i32>* %ptr.out, i32 2
- ret <4 x i32>* %next
+ %val = load <4 x i32>, ptr %ptr.in
+ store <4 x i32> %val, ptr %ptr.out
+ %next = getelementptr <4 x i32>, ptr %ptr.out, i32 2
+ ret ptr %next
}
; PR56970
-define void @v3i8store(<3 x i8> *%p) {
+define void @v3i8store(ptr %p) {
; CHECK-LABEL: v3i8store:
; CHECK: @ %bb.0:
; CHECK-NEXT: sub sp, #4
@@ -416,11 +416,11 @@ define void @v3i8store(<3 x i8> *%p) {
; CHECK-NEXT: strh r1, [r0]
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: bx lr
- store <3 x i8> zeroinitializer, <3 x i8> *%p, align 4
+ store <3 x i8> zeroinitializer, ptr %p, align 4
ret void
}
-define void @v3i64shuffle(<3 x i64> *%p, <3 x i64> %a) {
+define void @v3i64shuffle(ptr %p, <3 x i64> %a) {
; CHECK-LABEL: v3i64shuffle:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q8, #0x0
@@ -432,7 +432,7 @@ define void @v3i64shuffle(<3 x i64> *%p, <3 x i64> %a) {
; CHECK-NEXT: str.w r12, [r0]
; CHECK-NEXT: bx lr
%b = shufflevector <3 x i64> %a, <3 x i64> zeroinitializer, <3 x i32> <i32 0, i32 3, i32 2>
- store <3 x i64> %b, <3 x i64> *%p, align 4
+ store <3 x i64> %b, ptr %p, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/vext.ll b/llvm/test/CodeGen/ARM/vext.ll
index 3a47d3d95dfb7..7ddf1d02834c3 100644
--- a/llvm/test/CodeGen/ARM/vext.ll
+++ b/llvm/test/CodeGen/ARM/vext.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - -lower-interleaved-accesses=false | FileCheck %s
-define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @test_vextd(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: test_vextd:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -9,13 +9,13 @@ define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vext.8 d16, d17, d16, #3
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
ret <8 x i8> %tmp3
}
-define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @test_vextRd(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: test_vextRd:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -23,13 +23,13 @@ define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vext.8 d16, d17, d16, #5
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
ret <8 x i8> %tmp3
}
-define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @test_vextq(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: test_vextq:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -38,13 +38,13 @@ define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
ret <16 x i8> %tmp3
}
-define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @test_vextRq(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: test_vextRq:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -53,13 +53,13 @@ define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
ret <16 x i8> %tmp3
}
-define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @test_vextd16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: test_vextd16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -67,13 +67,13 @@ define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vext.16 d16, d17, d16, #3
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
ret <4 x i16> %tmp3
}
-define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @test_vextq32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: test_vextq32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -82,15 +82,15 @@ define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
ret <4 x i32> %tmp3
}
; Undef shuffle indices should not prevent matching to VEXT:
-define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @test_vextd_undef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: test_vextd_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -98,13 +98,13 @@ define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vext.8 d16, d17, d16, #3
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10>
ret <8 x i8> %tmp3
}
-define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @test_vextRq_undef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: test_vextRq_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -113,8 +113,8 @@ define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 undef, i32 undef, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6>
ret <16 x i8> %tmp3
}
@@ -178,7 +178,7 @@ entry:
; One vector needs vext, the other can be handled by extract_subvector
; Also checks interleaving of sources is handled correctly.
; Essence: a vext is used on %A and something saner than stack load/store for final result.
-define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <4 x i16> @test_interleaved(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: test_interleaved:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -189,14 +189,14 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vzip.16 d16, d17
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 3, i32 8, i32 5, i32 9>
ret <4 x i16> %tmp3
}
; An undef in the shuffle list should still be optimizable
-define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <4 x i16> @test_undef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: test_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -204,8 +204,8 @@ define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vzip.16 d17, d16
; CHECK-NEXT: vmov r0, r1, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9>
ret <4 x i16> %tmp3
}
@@ -213,7 +213,7 @@ define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; We should ignore a build_vector with more than two sources.
; Use illegal <32 x i16> type to produce such a shuffle after legalizing types.
; Try to look for fallback to by-element inserts.
-define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind {
+define <4 x i16> @test_multisource(ptr %B) nounwind {
; CHECK-LABEL: test_multisource:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.16 {d16, d17}, [r0:128]!
@@ -228,14 +228,14 @@ define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind {
; CHECK-NEXT: vext.16 d16, d16, d16, #2
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <32 x i16>, <32 x i16>* %B
+ %tmp1 = load <32 x i16>, ptr %B
%tmp2 = shufflevector <32 x i16> %tmp1, <32 x i16> undef, <4 x i32> <i32 0, i32 8, i32 16, i32 24>
ret <4 x i16> %tmp2
}
; We don't handle shuffles using more than half of a 128-bit vector.
; Again, test for fallback to by-element inserts.
-define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
+define <4 x i16> @test_largespan(ptr %B) nounwind {
; CHECK-LABEL: test_largespan:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -243,7 +243,7 @@ define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
; CHECK-NEXT: vuzp.16 d18, d17
; CHECK-NEXT: vmov r0, r1, d18
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %B
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
ret <4 x i16> %tmp2
}
@@ -253,7 +253,7 @@ define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
; lowering loop can result otherwise).
; (There are probably better ways to lower this shuffle, but it's not
; really important.)
-define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @test_illegal(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: test_illegal:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -274,15 +274,15 @@ define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d20
; CHECK-NEXT: vmov r2, r3, d21
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9>
ret <8 x i16> %tmp3
}
; PR11129
; Make sure this doesn't crash
-define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind {
+define arm_aapcscc void @test_elem_mismatch(ptr nocapture %src, ptr nocapture %dest) nounwind {
; CHECK-LABEL: test_elem_mismatch:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0:128]
@@ -292,7 +292,7 @@ define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>
; CHECK-NEXT: vmov.16 d16[1], r2
; CHECK-NEXT: vstr d16, [r1]
; CHECK-NEXT: mov pc, lr
- %tmp0 = load <2 x i64>, <2 x i64>* %src, align 16
+ %tmp0 = load <2 x i64>, ptr %src, align 16
%tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32>
%tmp2 = extractelement <4 x i32> %tmp1, i32 0
%tmp3 = extractelement <4 x i32> %tmp1, i32 2
@@ -300,11 +300,11 @@ define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>
%tmp5 = trunc i32 %tmp3 to i16
%tmp6 = insertelement <4 x i16> undef, i16 %tmp4, i32 0
%tmp7 = insertelement <4 x i16> %tmp6, i16 %tmp5, i32 1
- store <4 x i16> %tmp7, <4 x i16>* %dest, align 4
+ store <4 x i16> %tmp7, ptr %dest, align 4
ret void
}
-define <4 x i32> @test_reverse_and_extract(<2 x i32>* %A) {
+define <4 x i32> @test_reverse_and_extract(ptr %A) {
; CHECK-LABEL: test_reverse_and_extract:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, [r0]
@@ -314,12 +314,12 @@ define <4 x i32> @test_reverse_and_extract(<2 x i32>* %A) {
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
entry:
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 0>
ret <4 x i32> %0
}
-define <4 x i32> @test_dup_and_extract(<2 x i32>* %A) {
+define <4 x i32> @test_dup_and_extract(ptr %A) {
; CHECK-LABEL: test_dup_and_extract:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, [r0]
@@ -329,12 +329,12 @@ define <4 x i32> @test_dup_and_extract(<2 x i32>* %A) {
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
entry:
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
ret <4 x i32> %0
}
-define <4 x i32> @test_zip_and_extract(<2 x i32>* %A) {
+define <4 x i32> @test_zip_and_extract(ptr %A) {
; CHECK-LABEL: test_zip_and_extract:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, [r0]
@@ -346,7 +346,7 @@ define <4 x i32> @test_zip_and_extract(<2 x i32>* %A) {
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
entry:
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 1>
ret <4 x i32> %0
}
diff --git a/llvm/test/CodeGen/ARM/vfcmp.ll b/llvm/test/CodeGen/ARM/vfcmp.ll
index 79b23a535344f..f7e95d0b5e1db 100644
--- a/llvm/test/CodeGen/ARM/vfcmp.ll
+++ b/llvm/test/CodeGen/ARM/vfcmp.ll
@@ -3,136 +3,136 @@
; This tests fcmp operations that do not map directly to NEON instructions.
; une is implemented with VCEQ/VMVN
-define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vcunef32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcunef32:
;CHECK: vceq.f32
;CHECK-NEXT: vmvn
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = fcmp une <2 x float> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
; olt is implemented with VCGT
-define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vcoltf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcoltf32:
;CHECK: vcgt.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = fcmp olt <2 x float> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
; ole is implemented with VCGE
-define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vcolef32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcolef32:
;CHECK: vcge.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = fcmp ole <2 x float> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
; uge is implemented with VCGT/VMVN
-define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vcugef32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcugef32:
;CHECK: vcgt.f32
;CHECK-NEXT: vmvn
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = fcmp uge <2 x float> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
; ule is implemented with VCGT/VMVN
-define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vculef32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vculef32:
;CHECK: vcgt.f32
;CHECK-NEXT: vmvn
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = fcmp ule <2 x float> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
; ugt is implemented with VCGE/VMVN
-define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vcugtf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcugtf32:
;CHECK: vcge.f32
;CHECK-NEXT: vmvn
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = fcmp ugt <2 x float> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
; ult is implemented with VCGE/VMVN
-define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vcultf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcultf32:
;CHECK: vcge.f32
;CHECK-NEXT: vmvn
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = fcmp ult <2 x float> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
; ueq is implemented with VCGT/VCGT/VORR/VMVN
-define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vcueqf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcueqf32:
;CHECK: vcgt.f32
;CHECK-NEXT: vcgt.f32
;CHECK-NEXT: vorr
;CHECK-NEXT: vmvn
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = fcmp ueq <2 x float> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
; one is implemented with VCGT/VCGT/VORR
-define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vconef32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vconef32:
;CHECK: vcgt.f32
;CHECK-NEXT: vcgt.f32
;CHECK-NEXT: vorr
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = fcmp one <2 x float> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
; uno is implemented with VCGT/VCGE/VORR/VMVN
-define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vcunof32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcunof32:
;CHECK: vcge.f32
;CHECK-NEXT: vcgt.f32
;CHECK-NEXT: vorr
;CHECK-NEXT: vmvn
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = fcmp uno <2 x float> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
; ord is implemented with VCGT/VCGE/VORR
-define <2 x i32> @vcordf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x i32> @vcordf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcordf32:
;CHECK: vcge.f32
;CHECK-NEXT: vcgt.f32
;CHECK-NEXT: vorr
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = fcmp ord <2 x float> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
diff --git a/llvm/test/CodeGen/ARM/vfp.ll b/llvm/test/CodeGen/ARM/vfp.ll
index c18855abd877f..6f5bfc9aac018 100644
--- a/llvm/test/CodeGen/ARM/vfp.ll
+++ b/llvm/test/CodeGen/ARM/vfp.ll
@@ -1,11 +1,11 @@
; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+vfp2 -disable-post-ra | FileCheck %s
; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+vfp2 -disable-post-ra -regalloc=basic | FileCheck %s
-define void @test(float* %P, double* %D) {
- %A = load float, float* %P ; <float> [#uses=1]
- %B = load double, double* %D ; <double> [#uses=1]
- store float %A, float* %P
- store double %B, double* %D
+define void @test(ptr %P, ptr %D) {
+ %A = load float, ptr %P ; <float> [#uses=1]
+ %B = load double, ptr %D ; <double> [#uses=1]
+ store float %A, ptr %P
+ store double %B, ptr %D
ret void
}
@@ -13,109 +13,109 @@ declare float @fabsf(float)
declare double @fabs(double)
-define void @test_abs(float* %P, double* %D) {
+define void @test_abs(ptr %P, ptr %D) {
;CHECK-LABEL: test_abs:
- %a = load float, float* %P ; <float> [#uses=1]
+ %a = load float, ptr %P ; <float> [#uses=1]
;CHECK: vabs.f32
%b = call float @fabsf( float %a ) readnone ; <float> [#uses=1]
- store float %b, float* %P
- %A = load double, double* %D ; <double> [#uses=1]
+ store float %b, ptr %P
+ %A = load double, ptr %D ; <double> [#uses=1]
;CHECK: vabs.f64
%B = call double @fabs( double %A ) readnone ; <double> [#uses=1]
- store double %B, double* %D
+ store double %B, ptr %D
ret void
}
-define void @test_add(float* %P, double* %D) {
+define void @test_add(ptr %P, ptr %D) {
;CHECK-LABEL: test_add:
- %a = load float, float* %P ; <float> [#uses=2]
+ %a = load float, ptr %P ; <float> [#uses=2]
%b = fadd float %a, %a ; <float> [#uses=1]
- store float %b, float* %P
- %A = load double, double* %D ; <double> [#uses=2]
+ store float %b, ptr %P
+ %A = load double, ptr %D ; <double> [#uses=2]
%B = fadd double %A, %A ; <double> [#uses=1]
- store double %B, double* %D
+ store double %B, ptr %D
ret void
}
-define void @test_ext_round(float* %P, double* %D) {
+define void @test_ext_round(ptr %P, ptr %D) {
;CHECK-LABEL: test_ext_round:
- %a = load float, float* %P ; <float> [#uses=1]
+ %a = load float, ptr %P ; <float> [#uses=1]
;CHECK-DAG: vcvt.f64.f32
;CHECK-DAG: vcvt.f32.f64
%b = fpext float %a to double ; <double> [#uses=1]
- %A = load double, double* %D ; <double> [#uses=1]
+ %A = load double, ptr %D ; <double> [#uses=1]
%B = fptrunc double %A to float ; <float> [#uses=1]
- store double %b, double* %D
- store float %B, float* %P
+ store double %b, ptr %D
+ store float %B, ptr %P
ret void
}
-define void @test_fma(float* %P1, float* %P2, float* %P3) {
+define void @test_fma(ptr %P1, ptr %P2, ptr %P3) {
;CHECK-LABEL: test_fma:
- %a1 = load float, float* %P1 ; <float> [#uses=1]
- %a2 = load float, float* %P2 ; <float> [#uses=1]
- %a3 = load float, float* %P3 ; <float> [#uses=1]
+ %a1 = load float, ptr %P1 ; <float> [#uses=1]
+ %a2 = load float, ptr %P2 ; <float> [#uses=1]
+ %a3 = load float, ptr %P3 ; <float> [#uses=1]
;CHECK: vnmls.f32
%X = fmul float %a1, %a2 ; <float> [#uses=1]
%Y = fsub float %X, %a3 ; <float> [#uses=1]
- store float %Y, float* %P1
+ store float %Y, ptr %P1
ret void
}
-define i32 @test_ftoi(float* %P1) {
+define i32 @test_ftoi(ptr %P1) {
;CHECK-LABEL: test_ftoi:
- %a1 = load float, float* %P1 ; <float> [#uses=1]
+ %a1 = load float, ptr %P1 ; <float> [#uses=1]
;CHECK: vcvt.s32.f32
%b1 = fptosi float %a1 to i32 ; <i32> [#uses=1]
ret i32 %b1
}
-define i32 @test_ftou(float* %P1) {
+define i32 @test_ftou(ptr %P1) {
;CHECK-LABEL: test_ftou:
- %a1 = load float, float* %P1 ; <float> [#uses=1]
+ %a1 = load float, ptr %P1 ; <float> [#uses=1]
;CHECK: vcvt.u32.f32
%b1 = fptoui float %a1 to i32 ; <i32> [#uses=1]
ret i32 %b1
}
-define i32 @test_dtoi(double* %P1) {
+define i32 @test_dtoi(ptr %P1) {
;CHECK-LABEL: test_dtoi:
- %a1 = load double, double* %P1 ; <double> [#uses=1]
+ %a1 = load double, ptr %P1 ; <double> [#uses=1]
;CHECK: vcvt.s32.f64
%b1 = fptosi double %a1 to i32 ; <i32> [#uses=1]
ret i32 %b1
}
-define i32 @test_dtou(double* %P1) {
+define i32 @test_dtou(ptr %P1) {
;CHECK-LABEL: test_dtou:
- %a1 = load double, double* %P1 ; <double> [#uses=1]
+ %a1 = load double, ptr %P1 ; <double> [#uses=1]
;CHECK: vcvt.u32.f64
%b1 = fptoui double %a1 to i32 ; <i32> [#uses=1]
ret i32 %b1
}
-define void @test_utod(double* %P1, i32 %X) {
+define void @test_utod(ptr %P1, i32 %X) {
;CHECK-LABEL: test_utod:
;CHECK: vcvt.f64.u32
%b1 = uitofp i32 %X to double ; <double> [#uses=1]
- store double %b1, double* %P1
+ store double %b1, ptr %P1
ret void
}
-define void @test_utod2(double* %P1, i8 %X) {
+define void @test_utod2(ptr %P1, i8 %X) {
;CHECK-LABEL: test_utod2:
;CHECK: vcvt.f64.u32
%b1 = uitofp i8 %X to double ; <double> [#uses=1]
- store double %b1, double* %P1
+ store double %b1, ptr %P1
ret void
}
-define void @test_cmp(float* %glob, i32 %X) {
+define void @test_cmp(ptr %glob, i32 %X) {
;CHECK-LABEL: test_cmp:
entry:
- %tmp = load float, float* %glob ; <float> [#uses=2]
- %tmp3 = getelementptr float, float* %glob, i32 2 ; <float*> [#uses=1]
- %tmp4 = load float, float* %tmp3 ; <float> [#uses=2]
+ %tmp = load float, ptr %glob ; <float> [#uses=2]
+ %tmp3 = getelementptr float, ptr %glob, i32 2 ; <ptr> [#uses=1]
+ %tmp4 = load float, ptr %tmp3 ; <float> [#uses=2]
%tmp.upgrd.1 = fcmp oeq float %tmp, %tmp4 ; <i1> [#uses=1]
%tmp5 = fcmp uno float %tmp, %tmp4 ; <i1> [#uses=1]
%tmp6 = or i1 %tmp.upgrd.1, %tmp5 ; <i1> [#uses=1]
@@ -138,10 +138,10 @@ declare i32 @bar(...)
declare i32 @baz(...)
-define void @test_cmpfp0(float* %glob, i32 %X) {
+define void @test_cmpfp0(ptr %glob, i32 %X) {
;CHECK-LABEL: test_cmpfp0:
entry:
- %tmp = load float, float* %glob ; <float> [#uses=1]
+ %tmp = load float, ptr %glob ; <float> [#uses=1]
;CHECK: vcmp.f32
%tmp.upgrd.3 = fcmp ogt float %tmp, 0.000000e+00 ; <i1> [#uses=1]
br i1 %tmp.upgrd.3, label %cond_true, label %cond_false
diff --git a/llvm/test/CodeGen/ARM/vget_lane.ll b/llvm/test/CodeGen/ARM/vget_lane.ll
index d4cbfad5be6f4..ca7f05b35c36e 100644
--- a/llvm/test/CodeGen/ARM/vget_lane.ll
+++ b/llvm/test/CodeGen/ARM/vget_lane.ll
@@ -2,93 +2,93 @@
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
target triple = "thumbv7-elf"
-define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
+define i32 @vget_lanes8(ptr %A) nounwind {
;CHECK-LABEL: vget_lanes8:
;CHECK: vmov.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = extractelement <8 x i8> %tmp1, i32 1
%tmp3 = sext i8 %tmp2 to i32
ret i32 %tmp3
}
-define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
+define i32 @vget_lanes16(ptr %A) nounwind {
;CHECK-LABEL: vget_lanes16:
;CHECK: vmov.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = extractelement <4 x i16> %tmp1, i32 1
%tmp3 = sext i16 %tmp2 to i32
ret i32 %tmp3
}
-define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
+define i32 @vget_laneu8(ptr %A) nounwind {
;CHECK-LABEL: vget_laneu8:
;CHECK: vmov.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = extractelement <8 x i8> %tmp1, i32 1
%tmp3 = zext i8 %tmp2 to i32
ret i32 %tmp3
}
-define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
+define i32 @vget_laneu16(ptr %A) nounwind {
;CHECK-LABEL: vget_laneu16:
;CHECK: vmov.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = extractelement <4 x i16> %tmp1, i32 1
%tmp3 = zext i16 %tmp2 to i32
ret i32 %tmp3
}
; Do a vector add to keep the extraction from being done directly from memory.
-define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
+define i32 @vget_lanei32(ptr %A) nounwind {
;CHECK-LABEL: vget_lanei32:
;CHECK: vmov.32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = add <2 x i32> %tmp1, %tmp1
%tmp3 = extractelement <2 x i32> %tmp2, i32 1
ret i32 %tmp3
}
-define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
+define i32 @vgetQ_lanes8(ptr %A) nounwind {
;CHECK-LABEL: vgetQ_lanes8:
;CHECK: vmov.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = extractelement <16 x i8> %tmp1, i32 1
%tmp3 = sext i8 %tmp2 to i32
ret i32 %tmp3
}
-define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
+define i32 @vgetQ_lanes16(ptr %A) nounwind {
;CHECK-LABEL: vgetQ_lanes16:
;CHECK: vmov.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = extractelement <8 x i16> %tmp1, i32 1
%tmp3 = sext i16 %tmp2 to i32
ret i32 %tmp3
}
-define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
+define i32 @vgetQ_laneu8(ptr %A) nounwind {
;CHECK-LABEL: vgetQ_laneu8:
;CHECK: vmov.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = extractelement <16 x i8> %tmp1, i32 1
%tmp3 = zext i8 %tmp2 to i32
ret i32 %tmp3
}
-define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
+define i32 @vgetQ_laneu16(ptr %A) nounwind {
;CHECK-LABEL: vgetQ_laneu16:
;CHECK: vmov.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = extractelement <8 x i16> %tmp1, i32 1
%tmp3 = zext i16 %tmp2 to i32
ret i32 %tmp3
}
; Do a vector add to keep the extraction from being done directly from memory.
-define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind {
+define i32 @vgetQ_lanei32(ptr %A) nounwind {
;CHECK-LABEL: vgetQ_lanei32:
;CHECK: vmov.32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = add <4 x i32> %tmp1, %tmp1
%tmp3 = extractelement <4 x i32> %tmp2, i32 1
ret i32 %tmp3
@@ -97,13 +97,13 @@ define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind {
define arm_aapcs_vfpcc void @test_vget_laneu16() nounwind {
entry:
; CHECK: vmov.u16 r0, d{{.*}}[1]
- %arg0_uint16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1]
- %out_uint16_t = alloca i16 ; <i16*> [#uses=1]
+ %arg0_uint16x4_t = alloca <4 x i16> ; <ptr> [#uses=1]
+ %out_uint16_t = alloca i16 ; <ptr> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
- %0 = load <4 x i16>, <4 x i16>* %arg0_uint16x4_t, align 8 ; <<4 x i16>> [#uses=1]
+ %0 = load <4 x i16>, ptr %arg0_uint16x4_t, align 8 ; <<4 x i16>> [#uses=1]
%1 = extractelement <4 x i16> %0, i32 1 ; <i16> [#uses=1]
%2 = add i16 %1, %1
- store i16 %2, i16* %out_uint16_t, align 2
+ store i16 %2, ptr %out_uint16_t, align 2
br label %return
return: ; preds = %entry
@@ -113,13 +113,13 @@ return: ; preds = %entry
define arm_aapcs_vfpcc void @test_vget_laneu8() nounwind {
entry:
; CHECK: vmov.u8 r0, d{{.*}}[1]
- %arg0_uint8x8_t = alloca <8 x i8> ; <<8 x i8>*> [#uses=1]
- %out_uint8_t = alloca i8 ; <i8*> [#uses=1]
+ %arg0_uint8x8_t = alloca <8 x i8> ; <ptr> [#uses=1]
+ %out_uint8_t = alloca i8 ; <ptr> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
- %0 = load <8 x i8>, <8 x i8>* %arg0_uint8x8_t, align 8 ; <<8 x i8>> [#uses=1]
+ %0 = load <8 x i8>, ptr %arg0_uint8x8_t, align 8 ; <<8 x i8>> [#uses=1]
%1 = extractelement <8 x i8> %0, i32 1 ; <i8> [#uses=1]
%2 = add i8 %1, %1
- store i8 %2, i8* %out_uint8_t, align 1
+ store i8 %2, ptr %out_uint8_t, align 1
br label %return
return: ; preds = %entry
@@ -129,13 +129,13 @@ return: ; preds = %entry
define arm_aapcs_vfpcc void @test_vgetQ_laneu16() nounwind {
entry:
; CHECK: vmov.u16 r0, d{{.*}}[1]
- %arg0_uint16x8_t = alloca <8 x i16> ; <<8 x i16>*> [#uses=1]
- %out_uint16_t = alloca i16 ; <i16*> [#uses=1]
+ %arg0_uint16x8_t = alloca <8 x i16> ; <ptr> [#uses=1]
+ %out_uint16_t = alloca i16 ; <ptr> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
- %0 = load <8 x i16>, <8 x i16>* %arg0_uint16x8_t, align 16 ; <<8 x i16>> [#uses=1]
+ %0 = load <8 x i16>, ptr %arg0_uint16x8_t, align 16 ; <<8 x i16>> [#uses=1]
%1 = extractelement <8 x i16> %0, i32 1 ; <i16> [#uses=1]
%2 = add i16 %1, %1
- store i16 %2, i16* %out_uint16_t, align 2
+ store i16 %2, ptr %out_uint16_t, align 2
br label %return
return: ; preds = %entry
@@ -145,63 +145,63 @@ return: ; preds = %entry
define arm_aapcs_vfpcc void @test_vgetQ_laneu8() nounwind {
entry:
; CHECK: vmov.u8 r0, d{{.*}}[1]
- %arg0_uint8x16_t = alloca <16 x i8> ; <<16 x i8>*> [#uses=1]
- %out_uint8_t = alloca i8 ; <i8*> [#uses=1]
+ %arg0_uint8x16_t = alloca <16 x i8> ; <ptr> [#uses=1]
+ %out_uint8_t = alloca i8 ; <ptr> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
- %0 = load <16 x i8>, <16 x i8>* %arg0_uint8x16_t, align 16 ; <<16 x i8>> [#uses=1]
+ %0 = load <16 x i8>, ptr %arg0_uint8x16_t, align 16 ; <<16 x i8>> [#uses=1]
%1 = extractelement <16 x i8> %0, i32 1 ; <i8> [#uses=1]
%2 = add i8 %1, %1
- store i8 %2, i8* %out_uint8_t, align 1
+ store i8 %2, ptr %out_uint8_t, align 1
br label %return
return: ; preds = %entry
ret void
}
-define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind {
+define <8 x i8> @vset_lane8(ptr %A, i8 %B) nounwind {
;CHECK-LABEL: vset_lane8:
;CHECK: vmov.8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = insertelement <8 x i8> %tmp1, i8 %B, i32 1
ret <8 x i8> %tmp2
}
-define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind {
+define <4 x i16> @vset_lane16(ptr %A, i16 %B) nounwind {
;CHECK-LABEL: vset_lane16:
;CHECK: vmov.16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = insertelement <4 x i16> %tmp1, i16 %B, i32 1
ret <4 x i16> %tmp2
}
-define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind {
+define <2 x i32> @vset_lane32(ptr %A, i32 %B) nounwind {
;CHECK-LABEL: vset_lane32:
;CHECK: vmov.32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = insertelement <2 x i32> %tmp1, i32 %B, i32 1
ret <2 x i32> %tmp2
}
-define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind {
+define <16 x i8> @vsetQ_lane8(ptr %A, i8 %B) nounwind {
;CHECK-LABEL: vsetQ_lane8:
;CHECK: vmov.8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = insertelement <16 x i8> %tmp1, i8 %B, i32 1
ret <16 x i8> %tmp2
}
-define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind {
+define <8 x i16> @vsetQ_lane16(ptr %A, i16 %B) nounwind {
;CHECK-LABEL: vsetQ_lane16:
;CHECK: vmov.16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = insertelement <8 x i16> %tmp1, i16 %B, i32 1
ret <8 x i16> %tmp2
}
-define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
+define <4 x i32> @vsetQ_lane32(ptr %A, i32 %B) nounwind {
;CHECK-LABEL: vsetQ_lane32:
;CHECK: vmov.32 d{{.*}}[1], r1
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1
ret <4 x i32> %tmp2
}
@@ -218,15 +218,15 @@ entry:
; The llvm extractelement instruction does not require that the lane number
; be an immediate constant. Make sure a variable lane number is handled.
-define i32 @vget_variable_lanes8(<8 x i8>* %A, i32 %B) nounwind {
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+define i32 @vget_variable_lanes8(ptr %A, i32 %B) nounwind {
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = extractelement <8 x i8> %tmp1, i32 %B
%tmp3 = sext i8 %tmp2 to i32
ret i32 %tmp3
}
-define i32 @vgetQ_variable_lanei32(<4 x i32>* %A, i32 %B) nounwind {
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+define i32 @vgetQ_variable_lanei32(ptr %A, i32 %B) nounwind {
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = add <4 x i32> %tmp1, %tmp1
%tmp3 = extractelement <4 x i32> %tmp2, i32 %B
ret i32 %tmp3
diff --git a/llvm/test/CodeGen/ARM/vhadd.ll b/llvm/test/CodeGen/ARM/vhadd.ll
index 01e239d5c73a1..1cea02ac488c8 100644
--- a/llvm/test/CodeGen/ARM/vhadd.ll
+++ b/llvm/test/CodeGen/ARM/vhadd.ll
@@ -1,109 +1,109 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vhadds8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhadds8:
;CHECK: vhadd.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vhadds16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhadds16:
;CHECK: vhadd.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vhadds32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhadds32:
;CHECK: vhadd.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vhaddu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhaddu8:
;CHECK: vhadd.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vhaddu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhaddu16:
;CHECK: vhadd.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vhaddu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhaddu32:
;CHECK: vhadd.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vhaddQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhaddQs8:
;CHECK: vhadd.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vhaddQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhaddQs16:
;CHECK: vhadd.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vhaddQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhaddQs32:
;CHECK: vhadd.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vhaddQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhaddQu8:
;CHECK: vhadd.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vhaddQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhaddQu16:
;CHECK: vhadd.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vhaddQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhaddQu32:
;CHECK: vhadd.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
@@ -124,110 +124,110 @@ declare <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8>, <16 x i8>) nounwind rea
declare <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
declare <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-define <8 x i8> @vrhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vrhadds8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrhadds8:
;CHECK: vrhadd.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vrhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vrhadds16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrhadds16:
;CHECK: vrhadd.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vrhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vrhadds32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrhadds32:
;CHECK: vrhadd.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vrhadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <8 x i8> @vrhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vrhaddu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrhaddu8:
;CHECK: vrhadd.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vrhaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vrhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vrhaddu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrhaddu16:
;CHECK: vrhadd.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vrhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vrhaddu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrhaddu32:
;CHECK: vrhadd.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vrhaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <16 x i8> @vrhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vrhaddQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrhaddQs8:
;CHECK: vrhadd.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vrhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vrhaddQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrhaddQs16:
;CHECK: vrhadd.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vrhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vrhaddQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrhaddQs32:
;CHECK: vrhadd.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <16 x i8> @vrhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vrhaddQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrhaddQu8:
;CHECK: vrhadd.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vrhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vrhaddQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrhaddQu16:
;CHECK: vrhadd.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vrhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vrhaddQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrhaddQu32:
;CHECK: vrhadd.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
diff --git a/llvm/test/CodeGen/ARM/vhsub.ll b/llvm/test/CodeGen/ARM/vhsub.ll
index 7b3b29ac6e1ae..15e8dc4635bcd 100644
--- a/llvm/test/CodeGen/ARM/vhsub.ll
+++ b/llvm/test/CodeGen/ARM/vhsub.ll
@@ -1,109 +1,109 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vhsubs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhsubs8:
;CHECK: vhsub.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vhsubs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhsubs16:
;CHECK: vhsub.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vhsubs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhsubs32:
;CHECK: vhsub.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vhsubu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhsubu8:
;CHECK: vhsub.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vhsubu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhsubu16:
;CHECK: vhsub.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vhsubu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhsubu32:
;CHECK: vhsub.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vhsubQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhsubQs8:
;CHECK: vhsub.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vhsubQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhsubQs16:
;CHECK: vhsub.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vhsubQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhsubQs32:
;CHECK: vhsub.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vhsubQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhsubQu8:
;CHECK: vhsub.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vhsubQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhsubQu16:
;CHECK: vhsub.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vhsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vhsubQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vhsubQu32:
;CHECK: vhsub.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
diff --git a/llvm/test/CodeGen/ARM/vicmp-64.ll b/llvm/test/CodeGen/ARM/vicmp-64.ll
index 57e036bde22db..5ea4c1005fd23 100644
--- a/llvm/test/CodeGen/ARM/vicmp-64.ll
+++ b/llvm/test/CodeGen/ARM/vicmp-64.ll
@@ -3,7 +3,7 @@
; Check codegen for 64-bit icmp operations, which don't directly map to any
; instruction.
-define <2 x i64> @vne(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vne(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vne:
;CHECK: vceq.i32
;CHECK-NEXT: vrev64.32
@@ -12,14 +12,14 @@ define <2 x i64> @vne(<2 x i64>* %A, <2 x i64>* %B) nounwind {
;CHECK-NEXT: vmov
;CHECK-NEXT: vmov
;CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = icmp ne <2 x i64> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4
}
-define <2 x i64> @veq(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @veq(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: veq:
;CHECK: vceq.i32
;CHECK-NEXT: vrev64.32
@@ -27,8 +27,8 @@ define <2 x i64> @veq(<2 x i64>* %A, <2 x i64>* %B) nounwind {
;CHECK-NEXT: vmov
;CHECK-NEXT: vmov
;CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = icmp eq <2 x i64> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4
@@ -38,14 +38,14 @@ define <2 x i64> @veq(<2 x i64>* %A, <2 x i64>* %B) nounwind {
; (Atop < Btop) | ((ATop == BTop) & (ABottom < BBottom))
; would come out to roughly 6 instructions, but we currently
; scalarize it.
-define <2 x i64> @vult(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vult(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vult:
;CHECK: subs
;CHECK: sbcs
;CHECK: subs
;CHECK: sbcs
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = icmp ult <2 x i64> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4
diff --git a/llvm/test/CodeGen/ARM/vicmp.ll b/llvm/test/CodeGen/ARM/vicmp.ll
index 21b104a0d0455..1db82a7da92ab 100644
--- a/llvm/test/CodeGen/ARM/vicmp.ll
+++ b/llvm/test/CodeGen/ARM/vicmp.ll
@@ -6,107 +6,107 @@
; to VCGT and VCGE. Test all the operand types for not-equal but only sample
; the other operations.
-define <8 x i8> @vcnei8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vcnei8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcnei8:
;CHECK: vceq.i8
;CHECK-NEXT: vmvn
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = icmp ne <8 x i8> %tmp1, %tmp2
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
-define <4 x i16> @vcnei16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vcnei16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcnei16:
;CHECK: vceq.i16
;CHECK-NEXT: vmvn
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = icmp ne <4 x i16> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
-define <2 x i32> @vcnei32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vcnei32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcnei32:
;CHECK: vceq.i32
;CHECK-NEXT: vmvn
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = icmp ne <2 x i32> %tmp1, %tmp2
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
-define <16 x i8> @vcneQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vcneQi8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcneQi8:
;CHECK: vceq.i8
;CHECK-NEXT: vmvn
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = icmp ne <16 x i8> %tmp1, %tmp2
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
-define <8 x i16> @vcneQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vcneQi16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcneQi16:
;CHECK: vceq.i16
;CHECK-NEXT: vmvn
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = icmp ne <8 x i16> %tmp1, %tmp2
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
-define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vcneQi32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcneQi32:
;CHECK: vceq.i32
;CHECK-NEXT: vmvn
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = icmp ne <4 x i32> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
-define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vcltQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcltQs8:
;CHECK: vcgt.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = icmp slt <16 x i8> %tmp1, %tmp2
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
-define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vcles16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcles16:
;CHECK: vcge.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = icmp sle <4 x i16> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
-define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vcltu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcltu16:
;CHECK: vcgt.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = icmp ult <4 x i16> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
-define <4 x i32> @vcleQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vcleQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vcleQu32:
;CHECK: vcge.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = icmp ule <4 x i32> %tmp1, %tmp2
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
diff --git a/llvm/test/CodeGen/ARM/vld-vst-upgrade.ll b/llvm/test/CodeGen/ARM/vld-vst-upgrade.ll
index 8964e2a7e8946..4e773600a8f45 100644
--- a/llvm/test/CodeGen/ARM/vld-vst-upgrade.ll
+++ b/llvm/test/CodeGen/ARM/vld-vst-upgrade.ll
@@ -9,132 +9,132 @@
; CHECK-LABEL: test_vld1_upgrade:
; CHECK: vld1.32 {d16}, [r0]
-define <2 x i32> @test_vld1_upgrade(i8* %ptr) {
- %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %ptr, i32 1)
+define <2 x i32> @test_vld1_upgrade(ptr %ptr) {
+ %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(ptr %ptr, i32 1)
ret <2 x i32> %tmp1
}
-declare <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) nounwind readonly
+declare <2 x i32> @llvm.arm.neon.vld1.v2i32(ptr, i32) nounwind readonly
; CHECK-LABEL: test_vld2_upgrade:
; CHECK: vld2.32 {d16, d17}, [r0]
-define %struct.__neon_int32x2x2_t @test_vld2_upgrade(i8* %ptr) {
- %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8* %ptr, i32 1)
+define %struct.__neon_int32x2x2_t @test_vld2_upgrade(ptr %ptr) {
+ %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(ptr %ptr, i32 1)
ret %struct.__neon_int32x2x2_t %tmp1
}
-declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8*, i32) nounwind readonly
+declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(ptr, i32) nounwind readonly
; CHECK-LABEL: test_vld3_upgrade:
; CHECK: vld3.32 {d16, d17, d18}, [r1]
-define %struct.__neon_int32x2x3_t @test_vld3_upgrade(i8* %ptr) {
- %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %ptr, i32 1)
+define %struct.__neon_int32x2x3_t @test_vld3_upgrade(ptr %ptr) {
+ %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(ptr %ptr, i32 1)
ret %struct.__neon_int32x2x3_t %tmp1
}
-declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8*, i32) nounwind readonly
+declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(ptr, i32) nounwind readonly
; CHECK-LABEL: test_vld4_upgrade:
; CHECK: vld4.32 {d16, d17, d18, d19}, [r1]
-define %struct.__neon_int32x2x4_t @test_vld4_upgrade(i8* %ptr) {
- %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %ptr, i32 1)
+define %struct.__neon_int32x2x4_t @test_vld4_upgrade(ptr %ptr) {
+ %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(ptr %ptr, i32 1)
ret %struct.__neon_int32x2x4_t %tmp1
}
-declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8*, i32) nounwind readonly
+declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(ptr, i32) nounwind readonly
; vld[234]lane auto-upgrade tests
; CHECK-LABEL: test_vld2lane_upgrade:
; CHECK: vld2.32 {d16[1], d17[1]}, [r0]
-define %struct.__neon_int32x2x2_t @test_vld2lane_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B) {
- %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, i32 1, i32 1)
+define %struct.__neon_int32x2x2_t @test_vld2lane_upgrade(ptr %ptr, <2 x i32> %A, <2 x i32> %B) {
+ %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(ptr %ptr, <2 x i32> %A, <2 x i32> %B, i32 1, i32 1)
ret %struct.__neon_int32x2x2_t %tmp1
}
-declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
+declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(ptr, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
; CHECK-LABEL: test_vld3lane_upgrade:
; CHECK: vld3.32 {d16[1], d17[1], d18[1]}, [r1]
-define %struct.__neon_int32x2x3_t @test_vld3lane_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
- %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32 1, i32 1)
+define %struct.__neon_int32x2x3_t @test_vld3lane_upgrade(ptr %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
+ %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(ptr %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32 1, i32 1)
ret %struct.__neon_int32x2x3_t %tmp1
}
-declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
+declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(ptr, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
; CHECK-LABEL: test_vld4lane_upgrade:
; CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r1]
-define %struct.__neon_int32x2x4_t @test_vld4lane_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) {
- %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32 1, i32 1)
+define %struct.__neon_int32x2x4_t @test_vld4lane_upgrade(ptr %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) {
+ %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(ptr %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32 1, i32 1)
ret %struct.__neon_int32x2x4_t %tmp1
}
-declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
+declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(ptr, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
; vst[1234] auto-upgrade tests
; CHECK-LABEL: test_vst1_upgrade:
; CHECK: vst1.32 {d16}, [r0]
-define void @test_vst1_upgrade(i8* %ptr, <2 x i32> %A) {
- call void @llvm.arm.neon.vst1.v2i32(i8* %ptr, <2 x i32> %A, i32 1)
+define void @test_vst1_upgrade(ptr %ptr, <2 x i32> %A) {
+ call void @llvm.arm.neon.vst1.v2i32(ptr %ptr, <2 x i32> %A, i32 1)
ret void
}
-declare void @llvm.arm.neon.vst1.v2i32(i8*, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst1.v2i32(ptr, <2 x i32>, i32) nounwind
; CHECK-LABEL: test_vst2_upgrade:
; CHECK: vst2.32 {d16, d17}, [r0]
-define void @test_vst2_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B) {
- call void @llvm.arm.neon.vst2.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, i32 1)
+define void @test_vst2_upgrade(ptr %ptr, <2 x i32> %A, <2 x i32> %B) {
+ call void @llvm.arm.neon.vst2.v2i32(ptr %ptr, <2 x i32> %A, <2 x i32> %B, i32 1)
ret void
}
-declare void @llvm.arm.neon.vst2.v2i32(i8*, <2 x i32>, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst2.v2i32(ptr, <2 x i32>, <2 x i32>, i32) nounwind
; CHECK-LABEL: test_vst3_upgrade:
; CHECK: vst3.32 {d16, d17, d18}, [r0]
-define void @test_vst3_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
- call void @llvm.arm.neon.vst3.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32 1)
+define void @test_vst3_upgrade(ptr %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
+ call void @llvm.arm.neon.vst3.v2i32(ptr %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32 1)
ret void
}
-declare void @llvm.arm.neon.vst3.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst3.v2i32(ptr, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
; CHECK-LABEL: test_vst4_upgrade:
; CHECK: vst4.32 {d16, d17, d18, d19}, [r0]
-define void @test_vst4_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) {
- call void @llvm.arm.neon.vst4.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32 1)
+define void @test_vst4_upgrade(ptr %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) {
+ call void @llvm.arm.neon.vst4.v2i32(ptr %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32 1)
ret void
}
-declare void @llvm.arm.neon.vst4.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst4.v2i32(ptr, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
; vst[234]lane auto-upgrade tests
; CHECK-LABEL: test_vst2lane_upgrade:
; CHECK: vst2.32 {d16[1], d17[1]}, [r0]
-define void @test_vst2lane_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B) {
- call void @llvm.arm.neon.vst2lane.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, i32 1, i32 1)
+define void @test_vst2lane_upgrade(ptr %ptr, <2 x i32> %A, <2 x i32> %B) {
+ call void @llvm.arm.neon.vst2lane.v2i32(ptr %ptr, <2 x i32> %A, <2 x i32> %B, i32 1, i32 1)
ret void
}
-declare void @llvm.arm.neon.vst2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.v2i32(ptr, <2 x i32>, <2 x i32>, i32, i32) nounwind
; CHECK-LABEL: test_vst3lane_upgrade:
; CHECK: vst3.32 {d16[1], d17[1], d18[1]}, [r0]
-define void @test_vst3lane_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
- call void @llvm.arm.neon.vst3lane.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32 1, i32 1)
+define void @test_vst3lane_upgrade(ptr %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
+ call void @llvm.arm.neon.vst3lane.v2i32(ptr %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32 1, i32 1)
ret void
}
-declare void @llvm.arm.neon.vst3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.v2i32(ptr, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind
; CHECK-LABEL: test_vst4lane_upgrade:
; CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0]
-define void @test_vst4lane_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) {
- call void @llvm.arm.neon.vst4lane.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32 1, i32 1)
+define void @test_vst4lane_upgrade(ptr %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) {
+ call void @llvm.arm.neon.vst4lane.v2i32(ptr %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32 1, i32 1)
ret void
}
-declare void @llvm.arm.neon.vst4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.v2i32(ptr, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/vld1.ll b/llvm/test/CodeGen/ARM/vld1.ll
index c50e0beea4d1e..5a41c040d5dd0 100644
--- a/llvm/test/CodeGen/ARM/vld1.ll
+++ b/llvm/test/CodeGen/ARM/vld1.ll
@@ -3,148 +3,137 @@
; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon -regalloc=basic %s -o - \
; RUN: | FileCheck %s
-define <8 x i8> @vld1i8(i8* %A) nounwind {
+define <8 x i8> @vld1i8(ptr %A) nounwind {
;CHECK-LABEL: vld1i8:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld1.8 {d16}, [r0:64]
- %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %A, i32 16)
+ %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr %A, i32 16)
ret <8 x i8> %tmp1
}
-define <4 x i16> @vld1i16(i16* %A) nounwind {
+define <4 x i16> @vld1i16(ptr %A) nounwind {
;CHECK-LABEL: vld1i16:
;CHECK: vld1.16
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0(ptr %A, i32 1)
ret <4 x i16> %tmp1
}
;Check for a post-increment updating load.
-define <4 x i16> @vld1i16_update(i16** %ptr) nounwind {
+define <4 x i16> @vld1i16_update(ptr %ptr) nounwind {
;CHECK-LABEL: vld1i16_update:
;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]!
- %A = load i16*, i16** %ptr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* %tmp0, i32 1)
- %tmp2 = getelementptr i16, i16* %A, i32 4
- store i16* %tmp2, i16** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0(ptr %A, i32 1)
+ %tmp2 = getelementptr i16, ptr %A, i32 4
+ store ptr %tmp2, ptr %ptr
ret <4 x i16> %tmp1
}
-define <2 x i32> @vld1i32(i32* %A) nounwind {
+define <2 x i32> @vld1i32(ptr %A) nounwind {
;CHECK-LABEL: vld1i32:
;CHECK: vld1.32
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0(ptr %A, i32 1)
ret <2 x i32> %tmp1
}
;Check for a post-increment updating load with register increment.
-define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind {
+define <2 x i32> @vld1i32_update(ptr %ptr, i32 %inc) nounwind {
;CHECK-LABEL: vld1i32_update:
;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}}
- %A = load i32*, i32** %ptr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8* %tmp0, i32 1)
- %tmp2 = getelementptr i32, i32* %A, i32 %inc
- store i32* %tmp2, i32** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0(ptr %A, i32 1)
+ %tmp2 = getelementptr i32, ptr %A, i32 %inc
+ store ptr %tmp2, ptr %ptr
ret <2 x i32> %tmp1
}
-define <2 x float> @vld1f(float* %A) nounwind {
+define <2 x float> @vld1f(ptr %A) nounwind {
;CHECK-LABEL: vld1f:
;CHECK: vld1.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32.p0(ptr %A, i32 1)
ret <2 x float> %tmp1
}
-define <1 x i64> @vld1i64(i64* %A) nounwind {
+define <1 x i64> @vld1i64(ptr %A) nounwind {
;CHECK-LABEL: vld1i64:
;CHECK: vld1.64
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr %A, i32 1)
ret <1 x i64> %tmp1
}
-define <16 x i8> @vld1Qi8(i8* %A) nounwind {
+define <16 x i8> @vld1Qi8(ptr %A) nounwind {
;CHECK-LABEL: vld1Qi8:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld1.8 {d16, d17}, [r0:64]
- %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %A, i32 8)
+ %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr %A, i32 8)
ret <16 x i8> %tmp1
}
;Check for a post-increment updating load.
-define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
+define <16 x i8> @vld1Qi8_update(ptr %ptr) nounwind {
;CHECK-LABEL: vld1Qi8_update:
;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+|lr}}:64]!
- %A = load i8*, i8** %ptr
- %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %A, i32 8)
- %tmp2 = getelementptr i8, i8* %A, i32 16
- store i8* %tmp2, i8** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr %A, i32 8)
+ %tmp2 = getelementptr i8, ptr %A, i32 16
+ store ptr %tmp2, ptr %ptr
ret <16 x i8> %tmp1
}
-define <8 x i16> @vld1Qi16(i16* %A) nounwind {
+define <8 x i16> @vld1Qi16(ptr %A) nounwind {
;CHECK-LABEL: vld1Qi16:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld1.16 {d16, d17}, [r0:128]
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %tmp0, i32 32)
+ %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0(ptr %A, i32 32)
ret <8 x i16> %tmp1
}
-define <4 x i32> @vld1Qi32(i32* %A) nounwind {
+define <4 x i32> @vld1Qi32(ptr %A) nounwind {
;CHECK-LABEL: vld1Qi32:
;CHECK: vld1.32
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32.p0(ptr %A, i32 1)
ret <4 x i32> %tmp1
}
-define <4 x float> @vld1Qf(float* %A) nounwind {
+define <4 x float> @vld1Qf(ptr %A) nounwind {
;CHECK-LABEL: vld1Qf:
;CHECK: vld1.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr %A, i32 1)
ret <4 x float> %tmp1
}
-define <2 x i64> @vld1Qi64(i64* %A) nounwind {
+define <2 x i64> @vld1Qi64(ptr %A) nounwind {
;CHECK-LABEL: vld1Qi64:
;CHECK: vld1.64
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0(ptr %A, i32 1)
ret <2 x i64> %tmp1
}
-define <2 x double> @vld1Qf64(double* %A) nounwind {
+define <2 x double> @vld1Qf64(ptr %A) nounwind {
;CHECK-LABEL: vld1Qf64:
;CHECK: vld1.64
- %tmp0 = bitcast double* %A to i8*
- %tmp1 = call <2 x double> @llvm.arm.neon.vld1.v2f64.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call <2 x double> @llvm.arm.neon.vld1.v2f64.p0(ptr %A, i32 1)
ret <2 x double> %tmp1
}
-declare <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8*, i32) nounwind readonly
-declare <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8*, i32) nounwind readonly
-declare <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) nounwind readonly
-declare <2 x float> @llvm.arm.neon.vld1.v2f32.p0i8(i8*, i32) nounwind readonly
-declare <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8*, i32) nounwind readonly
+declare <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr, i32) nounwind readonly
+declare <4 x i16> @llvm.arm.neon.vld1.v4i16.p0(ptr, i32) nounwind readonly
+declare <2 x i32> @llvm.arm.neon.vld1.v2i32.p0(ptr, i32) nounwind readonly
+declare <2 x float> @llvm.arm.neon.vld1.v2f32.p0(ptr, i32) nounwind readonly
+declare <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr, i32) nounwind readonly
-declare <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8*, i32) nounwind readonly
-declare <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8*, i32) nounwind readonly
-declare <4 x i32> @llvm.arm.neon.vld1.v4i32.p0i8(i8*, i32) nounwind readonly
-declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8*, i32) nounwind readonly
-declare <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8*, i32) nounwind readonly
-declare <2 x double> @llvm.arm.neon.vld1.v2f64.p0i8(i8*, i32) nounwind readonly
+declare <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr, i32) nounwind readonly
+declare <8 x i16> @llvm.arm.neon.vld1.v8i16.p0(ptr, i32) nounwind readonly
+declare <4 x i32> @llvm.arm.neon.vld1.v4i32.p0(ptr, i32) nounwind readonly
+declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr, i32) nounwind readonly
+declare <2 x i64> @llvm.arm.neon.vld1.v2i64.p0(ptr, i32) nounwind readonly
+declare <2 x double> @llvm.arm.neon.vld1.v2f64.p0(ptr, i32) nounwind readonly
; Radar 8355607
; Do not crash if the vld1 result is not used.
define void @unused_vld1_result() {
entry:
- %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1)
+ %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr undef, i32 1)
call void @llvm.trap()
unreachable
}
diff --git a/llvm/test/CodeGen/ARM/vld2.ll b/llvm/test/CodeGen/ARM/vld2.ll
index 6ef37c1b66782..8d77684b67c90 100644
--- a/llvm/test/CodeGen/ARM/vld2.ll
+++ b/llvm/test/CodeGen/ARM/vld2.ll
@@ -11,45 +11,42 @@
%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }
%struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
-define <8 x i8> @vld2i8(i8* %A) nounwind {
+define <8 x i8> @vld2i8(ptr %A) nounwind {
;CHECK-LABEL: vld2i8:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld2.8 {d16, d17}, [{{r[0-9]+|lr}}:64]
- %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0i8(i8* %A, i32 8)
+ %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0(ptr %A, i32 8)
%tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1
%tmp4 = add <8 x i8> %tmp2, %tmp3
ret <8 x i8> %tmp4
}
-define <4 x i16> @vld2i16(i16* %A) nounwind {
+define <4 x i16> @vld2i16(ptr %A) nounwind {
;CHECK-LABEL: vld2i16:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld2.16 {d16, d17}, [{{r[0-9]+|lr}}:128]
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0i8(i8* %tmp0, i32 32)
+ %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0(ptr %A, i32 32)
%tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 1
%tmp4 = add <4 x i16> %tmp2, %tmp3
ret <4 x i16> %tmp4
}
-define <2 x i32> @vld2i32(i32* %A) nounwind {
+define <2 x i32> @vld2i32(ptr %A) nounwind {
;CHECK-LABEL: vld2i32:
;CHECK: vld2.32
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 1
%tmp4 = add <2 x i32> %tmp2, %tmp3
ret <2 x i32> %tmp4
}
-define <2 x float> @vld2f(float* %A) nounwind {
+define <2 x float> @vld2f(ptr %A) nounwind {
;CHECK-LABEL: vld2f:
;CHECK: vld2.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
%tmp4 = fadd <2 x float> %tmp2, %tmp3
@@ -57,37 +54,35 @@ define <2 x float> @vld2f(float* %A) nounwind {
}
;Check for a post-increment updating load.
-define <2 x float> @vld2f_update(float** %ptr) nounwind {
+define <2 x float> @vld2f_update(ptr %ptr) nounwind {
;CHECK-LABEL: vld2f_update:
;CHECK: vld2.32 {d16, d17}, [{{r[0-9]+|lr}}]!
- %A = load float*, float** %ptr
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0i8(i8* %tmp0, i32 1)
+ %A = load ptr, ptr %ptr
+ %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
%tmp4 = fadd <2 x float> %tmp2, %tmp3
- %tmp5 = getelementptr float, float* %A, i32 4
- store float* %tmp5, float** %ptr
+ %tmp5 = getelementptr float, ptr %A, i32 4
+ store ptr %tmp5, ptr %ptr
ret <2 x float> %tmp4
}
-define <1 x i64> @vld2i64(i64* %A) nounwind {
+define <1 x i64> @vld2i64(ptr %A) nounwind {
;CHECK-LABEL: vld2i64:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld1.64 {d16, d17}, [{{r[0-9]+|lr}}:128]
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64.p0i8(i8* %tmp0, i32 32)
+ %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64.p0(ptr %A, i32 32)
%tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1
%tmp4 = add <1 x i64> %tmp2, %tmp3
ret <1 x i64> %tmp4
}
-define <16 x i8> @vld2Qi8(i8* %A) nounwind {
+define <16 x i8> @vld2Qi8(ptr %A) nounwind {
;CHECK-LABEL: vld2Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld2.8 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:64]
- %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0i8(i8* %A, i32 8)
+ %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0(ptr %A, i32 8)
%tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
%tmp4 = add <16 x i8> %tmp2, %tmp3
@@ -95,61 +90,58 @@ define <16 x i8> @vld2Qi8(i8* %A) nounwind {
}
;Check for a post-increment updating load with register increment.
-define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind {
+define <16 x i8> @vld2Qi8_update(ptr %ptr, i32 %inc) nounwind {
;CHECK-LABEL: vld2Qi8_update:
;CHECK: vld2.8 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:128], r1
- %A = load i8*, i8** %ptr
- %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0i8(i8* %A, i32 16)
+ %A = load ptr, ptr %ptr
+ %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0(ptr %A, i32 16)
%tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
%tmp4 = add <16 x i8> %tmp2, %tmp3
- %tmp5 = getelementptr i8, i8* %A, i32 %inc
- store i8* %tmp5, i8** %ptr
+ %tmp5 = getelementptr i8, ptr %A, i32 %inc
+ store ptr %tmp5, ptr %ptr
ret <16 x i8> %tmp4
}
-define <8 x i16> @vld2Qi16(i16* %A) nounwind {
+define <8 x i16> @vld2Qi16(ptr %A) nounwind {
;CHECK-LABEL: vld2Qi16:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld2.16 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:128]
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16.p0i8(i8* %tmp0, i32 16)
+ %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16.p0(ptr %A, i32 16)
%tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 1
%tmp4 = add <8 x i16> %tmp2, %tmp3
ret <8 x i16> %tmp4
}
-define <4 x i32> @vld2Qi32(i32* %A) nounwind {
+define <4 x i32> @vld2Qi32(ptr %A) nounwind {
;CHECK-LABEL: vld2Qi32:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld2.32 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:256]
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8* %tmp0, i32 64)
+ %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %A, i32 64)
%tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 1
%tmp4 = add <4 x i32> %tmp2, %tmp3
ret <4 x i32> %tmp4
}
-define <4 x float> @vld2Qf(float* %A) nounwind {
+define <4 x float> @vld2Qf(ptr %A) nounwind {
;CHECK-LABEL: vld2Qf:
;CHECK: vld2.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 1
%tmp4 = fadd <4 x float> %tmp2, %tmp3
ret <4 x float> %tmp4
}
-declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64.p0i8(i8*, i32) nounwind readonly
+declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32.p0i8(i8*, i32) nounwind readonly
+declare %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32.p0(ptr, i32) nounwind readonly
diff --git a/llvm/test/CodeGen/ARM/vld3.ll b/llvm/test/CodeGen/ARM/vld3.ll
index 142b0f1b643cc..8db93498c5fdb 100644
--- a/llvm/test/CodeGen/ARM/vld3.ll
+++ b/llvm/test/CodeGen/ARM/vld3.ll
@@ -12,22 +12,21 @@
%struct.__neon_int32x4x3_t = type { <4 x i32>, <4 x i32>, <4 x i32> }
%struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
-define <8 x i8> @vld3i8(i8* %A) nounwind {
+define <8 x i8> @vld3i8(ptr %A) nounwind {
;CHECK-LABEL: vld3i8:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld3.8 {d16, d17, d18}, [{{r[0-9]+|lr}}:64]
- %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A, i32 32)
+ %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr %A, i32 32)
%tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2
%tmp4 = add <8 x i8> %tmp2, %tmp3
ret <8 x i8> %tmp4
}
-define <4 x i16> @vld3i16(i16* %A) nounwind {
+define <4 x i16> @vld3i16(ptr %A) nounwind {
;CHECK-LABEL: vld3i16:
;CHECK: vld3.16
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 2
%tmp4 = add <4 x i16> %tmp2, %tmp3
@@ -35,110 +34,102 @@ define <4 x i16> @vld3i16(i16* %A) nounwind {
}
;Check for a post-increment updating load with register increment.
-define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind {
+define <4 x i16> @vld3i16_update(ptr %ptr, i32 %inc) nounwind {
;CHECK-LABEL: vld3i16_update:
;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+|lr}}], {{r[0-9]+|lr}}
- %A = load i16*, i16** %ptr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0i8(i8* %tmp0, i32 1)
+ %A = load ptr, ptr %ptr
+ %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 2
%tmp4 = add <4 x i16> %tmp2, %tmp3
- %tmp5 = getelementptr i16, i16* %A, i32 %inc
- store i16* %tmp5, i16** %ptr
+ %tmp5 = getelementptr i16, ptr %A, i32 %inc
+ store ptr %tmp5, ptr %ptr
ret <4 x i16> %tmp4
}
-define <2 x i32> @vld3i32(i32* %A) nounwind {
+define <2 x i32> @vld3i32(ptr %A) nounwind {
;CHECK-LABEL: vld3i32:
;CHECK: vld3.32
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_int32x2x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp1, 2
%tmp4 = add <2 x i32> %tmp2, %tmp3
ret <2 x i32> %tmp4
}
-define <2 x float> @vld3f(float* %A) nounwind {
+define <2 x float> @vld3f(ptr %A) nounwind {
;CHECK-LABEL: vld3f:
;CHECK: vld3.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_float32x2x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_float32x2x3_t %tmp1, 2
%tmp4 = fadd <2 x float> %tmp2, %tmp3
ret <2 x float> %tmp4
}
-define <1 x i64> @vld3i64(i64* %A) nounwind {
+define <1 x i64> @vld3i64(ptr %A) nounwind {
;CHECK-LABEL: vld3i64:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld1.64 {d16, d17, d18}, [{{r[0-9]+|lr}}:64]
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64.p0i8(i8* %tmp0, i32 16)
+ %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64.p0(ptr %A, i32 16)
%tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 2
%tmp4 = add <1 x i64> %tmp2, %tmp3
ret <1 x i64> %tmp4
}
-define <1 x i64> @vld3i64_update(i64** %ptr, i64* %A) nounwind {
+define <1 x i64> @vld3i64_update(ptr %ptr, ptr %A) nounwind {
;CHECK-LABEL: vld3i64_update:
;CHECK: vld1.64 {d16, d17, d18}, [{{r[0-9]+|lr}}:64]!
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64.p0i8(i8* %tmp0, i32 16)
- %tmp5 = getelementptr i64, i64* %A, i32 3
- store i64* %tmp5, i64** %ptr
+ %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64.p0(ptr %A, i32 16)
+ %tmp5 = getelementptr i64, ptr %A, i32 3
+ store ptr %tmp5, ptr %ptr
%tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 2
%tmp4 = add <1 x i64> %tmp2, %tmp3
ret <1 x i64> %tmp4
}
-define <1 x i64> @vld3i64_reg_update(i64** %ptr, i64* %A) nounwind {
+define <1 x i64> @vld3i64_reg_update(ptr %ptr, ptr %A) nounwind {
;CHECK-LABEL: vld3i64_reg_update:
;CHECK: vld1.64 {d16, d17, d18}, [{{r[0-9]+|lr}}:64], {{r[0-9]+|lr}}
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64.p0i8(i8* %tmp0, i32 16)
- %tmp5 = getelementptr i64, i64* %A, i32 1
- store i64* %tmp5, i64** %ptr
+ %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64.p0(ptr %A, i32 16)
+ %tmp5 = getelementptr i64, ptr %A, i32 1
+ store ptr %tmp5, ptr %ptr
%tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 2
%tmp4 = add <1 x i64> %tmp2, %tmp3
ret <1 x i64> %tmp4
}
-define <16 x i8> @vld3Qi8(i8* %A) nounwind {
+define <16 x i8> @vld3Qi8(ptr %A) nounwind {
;CHECK-LABEL: vld3Qi8:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld3.8 {d16, d18, d20}, [{{r[0-9]+|lr}}:64]!
;CHECK: vld3.8 {d17, d19, d21}, [{{r[0-9]+|lr}}:64]
- %tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8.p0i8(i8* %A, i32 32)
+ %tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8.p0(ptr %A, i32 32)
%tmp2 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 2
%tmp4 = add <16 x i8> %tmp2, %tmp3
ret <16 x i8> %tmp4
}
-define <8 x i16> @vld3Qi16(i16* %A) nounwind {
+define <8 x i16> @vld3Qi16(ptr %A) nounwind {
;CHECK-LABEL: vld3Qi16:
;CHECK: vld3.16
;CHECK: vld3.16
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_int16x8x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp1, 2
%tmp4 = add <8 x i16> %tmp2, %tmp3
ret <8 x i16> %tmp4
}
-define <4 x i32> @vld3Qi32(i32* %A) nounwind {
+define <4 x i32> @vld3Qi32(ptr %A) nounwind {
;CHECK-LABEL: vld3Qi32:
;CHECK: vld3.32
;CHECK: vld3.32
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2
%tmp4 = add <4 x i32> %tmp2, %tmp3
@@ -146,40 +137,38 @@ define <4 x i32> @vld3Qi32(i32* %A) nounwind {
}
;Check for a post-increment updating load.
-define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind {
+define <4 x i32> @vld3Qi32_update(ptr %ptr) nounwind {
;CHECK-LABEL: vld3Qi32_update:
;CHECK: vld3.32 {d16, d18, d20}, [[[R:r[0-9]+|lr]]]!
;CHECK: vld3.32 {d17, d19, d21}, [[[R]]]!
- %A = load i32*, i32** %ptr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32.p0i8(i8* %tmp0, i32 1)
+ %A = load ptr, ptr %ptr
+ %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2
%tmp4 = add <4 x i32> %tmp2, %tmp3
- %tmp5 = getelementptr i32, i32* %A, i32 12
- store i32* %tmp5, i32** %ptr
+ %tmp5 = getelementptr i32, ptr %A, i32 12
+ store ptr %tmp5, ptr %ptr
ret <4 x i32> %tmp4
}
-define <4 x float> @vld3Qf(float* %A) nounwind {
+define <4 x float> @vld3Qf(ptr %A) nounwind {
;CHECK-LABEL: vld3Qf:
;CHECK: vld3.32
;CHECK: vld3.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_float32x4x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp1, 2
%tmp4 = fadd <4 x float> %tmp2, %tmp3
ret <4 x float> %tmp4
}
-declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64.p0i8(i8*, i32) nounwind readonly
+declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32.p0i8(i8*, i32) nounwind readonly
+declare %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32.p0(ptr, i32) nounwind readonly
diff --git a/llvm/test/CodeGen/ARM/vld4.ll b/llvm/test/CodeGen/ARM/vld4.ll
index 679c9ae4450eb..b1a34f863cfc8 100644
--- a/llvm/test/CodeGen/ARM/vld4.ll
+++ b/llvm/test/CodeGen/ARM/vld4.ll
@@ -11,11 +11,11 @@
%struct.__neon_int32x4x4_t = type { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> }
%struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
-define <8 x i8> @vld4i8(i8* %A) nounwind {
+define <8 x i8> @vld4i8(ptr %A) nounwind {
;CHECK-LABEL: vld4i8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.8 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:64]
- %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8* %A, i32 8)
+ %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0(ptr %A, i32 8)
%tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2
%tmp4 = add <8 x i8> %tmp2, %tmp3
@@ -23,111 +23,104 @@ define <8 x i8> @vld4i8(i8* %A) nounwind {
}
;Check for a post-increment updating load with register increment.
-define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind {
+define <8 x i8> @vld4i8_update(ptr %ptr, i32 %inc) nounwind {
;CHECK-LABEL: vld4i8_update:
;CHECK: vld4.8 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:128], r1
- %A = load i8*, i8** %ptr
- %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8* %A, i32 16)
+ %A = load ptr, ptr %ptr
+ %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0(ptr %A, i32 16)
%tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2
%tmp4 = add <8 x i8> %tmp2, %tmp3
- %tmp5 = getelementptr i8, i8* %A, i32 %inc
- store i8* %tmp5, i8** %ptr
+ %tmp5 = getelementptr i8, ptr %A, i32 %inc
+ store ptr %tmp5, ptr %ptr
ret <8 x i8> %tmp4
}
-define <4 x i16> @vld4i16(i16* %A) nounwind {
+define <4 x i16> @vld4i16(ptr %A) nounwind {
;CHECK-LABEL: vld4i16:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.16 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:128]
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16.p0i8(i8* %tmp0, i32 16)
+ %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16.p0(ptr %A, i32 16)
%tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 2
%tmp4 = add <4 x i16> %tmp2, %tmp3
ret <4 x i16> %tmp4
}
-define <2 x i32> @vld4i32(i32* %A) nounwind {
+define <2 x i32> @vld4i32(ptr %A) nounwind {
;CHECK-LABEL: vld4i32:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.32 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:256]
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32.p0i8(i8* %tmp0, i32 32)
+ %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32.p0(ptr %A, i32 32)
%tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 2
%tmp4 = add <2 x i32> %tmp2, %tmp3
ret <2 x i32> %tmp4
}
-define <2 x float> @vld4f(float* %A) nounwind {
+define <2 x float> @vld4f(ptr %A) nounwind {
;CHECK-LABEL: vld4f:
;CHECK: vld4.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 2
%tmp4 = fadd <2 x float> %tmp2, %tmp3
ret <2 x float> %tmp4
}
-define <1 x i64> @vld4i64(i64* %A) nounwind {
+define <1 x i64> @vld4i64(ptr %A) nounwind {
;CHECK-LABEL: vld4i64:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld1.64 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:256]
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0i8(i8* %tmp0, i32 64)
+ %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0(ptr %A, i32 64)
%tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2
%tmp4 = add <1 x i64> %tmp2, %tmp3
ret <1 x i64> %tmp4
}
-define <1 x i64> @vld4i64_update(i64** %ptr, i64* %A) nounwind {
+define <1 x i64> @vld4i64_update(ptr %ptr, ptr %A) nounwind {
;CHECK-LABEL: vld4i64_update:
;CHECK: vld1.64 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:256]!
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0i8(i8* %tmp0, i32 64)
- %tmp5 = getelementptr i64, i64* %A, i32 4
- store i64* %tmp5, i64** %ptr
+ %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0(ptr %A, i32 64)
+ %tmp5 = getelementptr i64, ptr %A, i32 4
+ store ptr %tmp5, ptr %ptr
%tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2
%tmp4 = add <1 x i64> %tmp2, %tmp3
ret <1 x i64> %tmp4
}
-define <1 x i64> @vld4i64_reg_update(i64** %ptr, i64* %A) nounwind {
+define <1 x i64> @vld4i64_reg_update(ptr %ptr, ptr %A) nounwind {
;CHECK-LABEL: vld4i64_reg_update:
;CHECK: vld1.64 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:256], {{r[0-9]+|lr}}
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0i8(i8* %tmp0, i32 64)
- %tmp5 = getelementptr i64, i64* %A, i32 1
- store i64* %tmp5, i64** %ptr
+ %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0(ptr %A, i32 64)
+ %tmp5 = getelementptr i64, ptr %A, i32 1
+ store ptr %tmp5, ptr %ptr
%tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2
%tmp4 = add <1 x i64> %tmp2, %tmp3
ret <1 x i64> %tmp4
}
-define <16 x i8> @vld4Qi8(i8* %A) nounwind {
+define <16 x i8> @vld4Qi8(ptr %A) nounwind {
;CHECK-LABEL: vld4Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.8 {d16, d18, d20, d22}, [{{r[0-9]+|lr}}:256]!
;CHECK: vld4.8 {d17, d19, d21, d23}, [{{r[0-9]+|lr}}:256]
- %tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8.p0i8(i8* %A, i32 64)
+ %tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8.p0(ptr %A, i32 64)
%tmp2 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 2
%tmp4 = add <16 x i8> %tmp2, %tmp3
ret <16 x i8> %tmp4
}
-define <8 x i16> @vld4Qi16(i16* %A) nounwind {
+define <8 x i16> @vld4Qi16(ptr %A) nounwind {
;CHECK-LABEL: vld4Qi16:
;Check for no alignment specifier.
;CHECK: vld4.16 {d16, d18, d20, d22}, [{{r[0-9]+|lr}}]!
;CHECK: vld4.16 {d17, d19, d21, d23}, [{{r[0-9]+|lr}}]
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2
%tmp4 = add <8 x i16> %tmp2, %tmp3
@@ -135,52 +128,49 @@ define <8 x i16> @vld4Qi16(i16* %A) nounwind {
}
;Check for a post-increment updating load.
-define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind {
+define <8 x i16> @vld4Qi16_update(ptr %ptr) nounwind {
;CHECK-LABEL: vld4Qi16_update:
;CHECK: vld4.16 {d16, d18, d20, d22}, [{{r[0-9]+|lr}}:64]!
;CHECK: vld4.16 {d17, d19, d21, d23}, [{{r[0-9]+|lr}}:64]!
- %A = load i16*, i16** %ptr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16.p0i8(i8* %tmp0, i32 8)
+ %A = load ptr, ptr %ptr
+ %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16.p0(ptr %A, i32 8)
%tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2
%tmp4 = add <8 x i16> %tmp2, %tmp3
- %tmp5 = getelementptr i16, i16* %A, i32 32
- store i16* %tmp5, i16** %ptr
+ %tmp5 = getelementptr i16, ptr %A, i32 32
+ store ptr %tmp5, ptr %ptr
ret <8 x i16> %tmp4
}
-define <4 x i32> @vld4Qi32(i32* %A) nounwind {
+define <4 x i32> @vld4Qi32(ptr %A) nounwind {
;CHECK-LABEL: vld4Qi32:
;CHECK: vld4.32
;CHECK: vld4.32
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 2
%tmp4 = add <4 x i32> %tmp2, %tmp3
ret <4 x i32> %tmp4
}
-define <4 x float> @vld4Qf(float* %A) nounwind {
+define <4 x float> @vld4Qf(ptr %A) nounwind {
;CHECK-LABEL: vld4Qf:
;CHECK: vld4.32
;CHECK: vld4.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32.p0i8(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32.p0(ptr %A, i32 1)
%tmp2 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 2
%tmp4 = fadd <4 x float> %tmp2, %tmp3
ret <4 x float> %tmp4
}
-declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0i8(i8*, i32) nounwind readonly
+declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0i8(i8*, i32) nounwind readonly
-declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32.p0i8(i8*, i32) nounwind readonly
+declare %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0(ptr, i32) nounwind readonly
+declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32.p0(ptr, i32) nounwind readonly
diff --git a/llvm/test/CodeGen/ARM/vlddup.ll b/llvm/test/CodeGen/ARM/vlddup.ll
index 53f996d24ce4c..a11087de90f16 100644
--- a/llvm/test/CodeGen/ARM/vlddup.ll
+++ b/llvm/test/CodeGen/ARM/vlddup.ll
@@ -1,118 +1,118 @@
; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vld1dupi8(i8* %A) nounwind {
+define <8 x i8> @vld1dupi8(ptr %A) nounwind {
;CHECK-LABEL: vld1dupi8:
;Check the (default) alignment value.
;CHECK: vld1.8 {d16[]}, [{{r[0-9]+|lr}}]
- %tmp1 = load i8, i8* %A, align 8
+ %tmp1 = load i8, ptr %A, align 8
%tmp2 = insertelement <8 x i8> undef, i8 %tmp1, i32 0
%tmp3 = shufflevector <8 x i8> %tmp2, <8 x i8> undef, <8 x i32> zeroinitializer
ret <8 x i8> %tmp3
}
-define <8 x i8> @vld1dupi8_preinc(i8** noalias nocapture %a, i32 %b) nounwind {
+define <8 x i8> @vld1dupi8_preinc(ptr noalias nocapture %a, i32 %b) nounwind {
entry:
;CHECK-LABEL: vld1dupi8_preinc:
;CHECK: vld1.8 {d16[]}, [{{r[0-9]+|lr}}]
- %0 = load i8*, i8** %a, align 4
- %add.ptr = getelementptr inbounds i8, i8* %0, i32 %b
- %1 = load i8, i8* %add.ptr, align 1
+ %0 = load ptr, ptr %a, align 4
+ %add.ptr = getelementptr inbounds i8, ptr %0, i32 %b
+ %1 = load i8, ptr %add.ptr, align 1
%2 = insertelement <8 x i8> undef, i8 %1, i32 0
%lane = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer
- store i8* %add.ptr, i8** %a, align 4
+ store ptr %add.ptr, ptr %a, align 4
ret <8 x i8> %lane
}
-define <8 x i8> @vld1dupi8_postinc_fixed(i8** noalias nocapture %a) nounwind {
+define <8 x i8> @vld1dupi8_postinc_fixed(ptr noalias nocapture %a) nounwind {
entry:
;CHECK-LABEL: vld1dupi8_postinc_fixed:
;CHECK: vld1.8 {d16[]}, [{{r[0-9]+|lr}}]!
- %0 = load i8*, i8** %a, align 4
- %1 = load i8, i8* %0, align 1
+ %0 = load ptr, ptr %a, align 4
+ %1 = load i8, ptr %0, align 1
%2 = insertelement <8 x i8> undef, i8 %1, i32 0
%lane = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer
- %add.ptr = getelementptr inbounds i8, i8* %0, i32 1
- store i8* %add.ptr, i8** %a, align 4
+ %add.ptr = getelementptr inbounds i8, ptr %0, i32 1
+ store ptr %add.ptr, ptr %a, align 4
ret <8 x i8> %lane
}
-define <8 x i8> @vld1dupi8_postinc_register(i8** noalias nocapture %a, i32 %n) nounwind {
+define <8 x i8> @vld1dupi8_postinc_register(ptr noalias nocapture %a, i32 %n) nounwind {
entry:
;CHECK-LABEL: vld1dupi8_postinc_register:
;CHECK: vld1.8 {d16[]}, [{{r[0-9]+|lr}}], r1
- %0 = load i8*, i8** %a, align 4
- %1 = load i8, i8* %0, align 1
+ %0 = load ptr, ptr %a, align 4
+ %1 = load i8, ptr %0, align 1
%2 = insertelement <8 x i8> undef, i8 %1, i32 0
%lane = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer
- %add.ptr = getelementptr inbounds i8, i8* %0, i32 %n
- store i8* %add.ptr, i8** %a, align 4
+ %add.ptr = getelementptr inbounds i8, ptr %0, i32 %n
+ store ptr %add.ptr, ptr %a, align 4
ret <8 x i8> %lane
}
-define <16 x i8> @vld1dupqi8_preinc(i8** noalias nocapture %a, i32 %b) nounwind {
+define <16 x i8> @vld1dupqi8_preinc(ptr noalias nocapture %a, i32 %b) nounwind {
entry:
;CHECK-LABEL: vld1dupqi8_preinc:
;CHECK: vld1.8 {d16[], d17[]}, [{{r[0-9]+|lr}}]
- %0 = load i8*, i8** %a, align 4
- %add.ptr = getelementptr inbounds i8, i8* %0, i32 %b
- %1 = load i8, i8* %add.ptr, align 1
+ %0 = load ptr, ptr %a, align 4
+ %add.ptr = getelementptr inbounds i8, ptr %0, i32 %b
+ %1 = load i8, ptr %add.ptr, align 1
%2 = insertelement <16 x i8> undef, i8 %1, i32 0
%lane = shufflevector <16 x i8> %2, <16 x i8> undef, <16 x i32> zeroinitializer
- store i8* %add.ptr, i8** %a, align 4
+ store ptr %add.ptr, ptr %a, align 4
ret <16 x i8> %lane
}
-define <16 x i8> @vld1dupqi8_postinc_fixed(i8** noalias nocapture %a) nounwind {
+define <16 x i8> @vld1dupqi8_postinc_fixed(ptr noalias nocapture %a) nounwind {
entry:
;CHECK-LABEL: vld1dupqi8_postinc_fixed:
;CHECK: vld1.8 {d16[], d17[]}, [{{r[0-9]+|lr}}]!
- %0 = load i8*, i8** %a, align 4
- %1 = load i8, i8* %0, align 1
+ %0 = load ptr, ptr %a, align 4
+ %1 = load i8, ptr %0, align 1
%2 = insertelement <16 x i8> undef, i8 %1, i32 0
%lane = shufflevector <16 x i8> %2, <16 x i8> undef, <16 x i32> zeroinitializer
- %add.ptr = getelementptr inbounds i8, i8* %0, i32 1
- store i8* %add.ptr, i8** %a, align 4
+ %add.ptr = getelementptr inbounds i8, ptr %0, i32 1
+ store ptr %add.ptr, ptr %a, align 4
ret <16 x i8> %lane
}
-define <16 x i8> @vld1dupqi8_postinc_register(i8** noalias nocapture %a, i32 %n) nounwind {
+define <16 x i8> @vld1dupqi8_postinc_register(ptr noalias nocapture %a, i32 %n) nounwind {
entry:
;CHECK-LABEL: vld1dupqi8_postinc_register:
;CHECK: vld1.8 {d16[], d17[]}, [{{r[0-9]+|lr}}], r1
- %0 = load i8*, i8** %a, align 4
- %1 = load i8, i8* %0, align 1
+ %0 = load ptr, ptr %a, align 4
+ %1 = load i8, ptr %0, align 1
%2 = insertelement <16 x i8> undef, i8 %1, i32 0
%lane = shufflevector <16 x i8> %2, <16 x i8> undef, <16 x i32> zeroinitializer
- %add.ptr = getelementptr inbounds i8, i8* %0, i32 %n
- store i8* %add.ptr, i8** %a, align 4
+ %add.ptr = getelementptr inbounds i8, ptr %0, i32 %n
+ store ptr %add.ptr, ptr %a, align 4
ret <16 x i8> %lane
}
-define <4 x i16> @vld1dupi16(i16* %A) nounwind {
+define <4 x i16> @vld1dupi16(ptr %A) nounwind {
;CHECK-LABEL: vld1dupi16:
;Check the alignment value. Max for this instruction is 16 bits:
;CHECK: vld1.16 {d16[]}, [{{r[0-9]+|lr}}:16]
- %tmp1 = load i16, i16* %A, align 8
+ %tmp1 = load i16, ptr %A, align 8
%tmp2 = insertelement <4 x i16> undef, i16 %tmp1, i32 0
%tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> undef, <4 x i32> zeroinitializer
ret <4 x i16> %tmp3
}
-define <4 x i16> @vld1dupi16_misaligned(i16* %A) nounwind {
+define <4 x i16> @vld1dupi16_misaligned(ptr %A) nounwind {
;CHECK-LABEL: vld1dupi16_misaligned:
;CHECK: vld1.16 {d16[]}, [{{r[0-9]+|lr}}]
- %tmp1 = load i16, i16* %A, align 1
+ %tmp1 = load i16, ptr %A, align 1
%tmp2 = insertelement <4 x i16> undef, i16 %tmp1, i32 0
%tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> undef, <4 x i32> zeroinitializer
ret <4 x i16> %tmp3
}
; This sort of looks like a vld1dup, but there's an extension in the way.
-define <4 x i16> @load_i16_dup_zext(i8* %A) nounwind {
+define <4 x i16> @load_i16_dup_zext(ptr %A) nounwind {
;CHECK-LABEL: load_i16_dup_zext:
;CHECK: ldrb r0, [{{r[0-9]+|lr}}]
;CHECK-NEXT: vdup.16 d16, r0
- %tmp1 = load i8, i8* %A, align 1
+ %tmp1 = load i8, ptr %A, align 1
%tmp2 = zext i8 %tmp1 to i16
%tmp3 = insertelement <4 x i16> undef, i16 %tmp2, i32 0
%tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer
@@ -120,11 +120,11 @@ define <4 x i16> @load_i16_dup_zext(i8* %A) nounwind {
}
; This sort of looks like a vld1dup, but there's an extension in the way.
-define <4 x i16> @load_i16_dup_sext(i8* %A) nounwind {
+define <4 x i16> @load_i16_dup_sext(ptr %A) nounwind {
;CHECK-LABEL: load_i16_dup_sext:
;CHECK: ldrsb r0, [{{r[0-9]+|lr}}]
;CHECK-NEXT: vdup.16 d16, r0
- %tmp1 = load i8, i8* %A, align 1
+ %tmp1 = load i8, ptr %A, align 1
%tmp2 = sext i8 %tmp1 to i16
%tmp3 = insertelement <4 x i16> undef, i16 %tmp2, i32 0
%tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer
@@ -132,33 +132,33 @@ define <4 x i16> @load_i16_dup_sext(i8* %A) nounwind {
}
; This sort of looks like a vld1dup, but there's an extension in the way.
-define <8 x i16> @load_i16_dupq_zext(i8* %A) nounwind {
+define <8 x i16> @load_i16_dupq_zext(ptr %A) nounwind {
;CHECK-LABEL: load_i16_dupq_zext:
;CHECK: ldrb r0, [{{r[0-9]+|lr}}]
;CHECK-NEXT: vdup.16 q8, r0
- %tmp1 = load i8, i8* %A, align 1
+ %tmp1 = load i8, ptr %A, align 1
%tmp2 = zext i8 %tmp1 to i16
%tmp3 = insertelement <8 x i16> undef, i16 %tmp2, i32 0
%tmp4 = shufflevector <8 x i16> %tmp3, <8 x i16> undef, <8 x i32> zeroinitializer
ret <8 x i16> %tmp4
}
-define <2 x i32> @vld1dupi32(i32* %A) nounwind {
+define <2 x i32> @vld1dupi32(ptr %A) nounwind {
;CHECK-LABEL: vld1dupi32:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vld1.32 {d16[]}, [{{r[0-9]+|lr}}:32]
- %tmp1 = load i32, i32* %A, align 8
+ %tmp1 = load i32, ptr %A, align 8
%tmp2 = insertelement <2 x i32> undef, i32 %tmp1, i32 0
%tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> undef, <2 x i32> zeroinitializer
ret <2 x i32> %tmp3
}
; This sort of looks like a vld1dup, but there's an extension in the way.
-define <4 x i32> @load_i32_dup_zext(i8* %A) nounwind {
+define <4 x i32> @load_i32_dup_zext(ptr %A) nounwind {
;CHECK-LABEL: load_i32_dup_zext:
;CHECK: ldrb r0, [{{r[0-9]+|lr}}]
;CHECK-NEXT: vdup.32 q8, r0
- %tmp1 = load i8, i8* %A, align 1
+ %tmp1 = load i8, ptr %A, align 1
%tmp2 = zext i8 %tmp1 to i32
%tmp3 = insertelement <4 x i32> undef, i32 %tmp2, i32 0
%tmp4 = shufflevector <4 x i32> %tmp3, <4 x i32> undef, <4 x i32> zeroinitializer
@@ -166,40 +166,40 @@ define <4 x i32> @load_i32_dup_zext(i8* %A) nounwind {
}
; This sort of looks like a vld1dup, but there's an extension in the way.
-define <4 x i32> @load_i32_dup_sext(i8* %A) nounwind {
+define <4 x i32> @load_i32_dup_sext(ptr %A) nounwind {
;CHECK-LABEL: load_i32_dup_sext:
;CHECK: ldrsb r0, [{{r[0-9]+|lr}}]
;CHECK-NEXT: vdup.32 q8, r0
- %tmp1 = load i8, i8* %A, align 1
+ %tmp1 = load i8, ptr %A, align 1
%tmp2 = sext i8 %tmp1 to i32
%tmp3 = insertelement <4 x i32> undef, i32 %tmp2, i32 0
%tmp4 = shufflevector <4 x i32> %tmp3, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %tmp4
}
-define <2 x float> @vld1dupf(float* %A) nounwind {
+define <2 x float> @vld1dupf(ptr %A) nounwind {
;CHECK-LABEL: vld1dupf:
;CHECK: vld1.32 {d16[]}, [{{r[0-9]+|lr}}:32]
- %tmp0 = load float, float* %A
+ %tmp0 = load float, ptr %A
%tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
ret <2 x float> %tmp2
}
-define <16 x i8> @vld1dupQi8(i8* %A) nounwind {
+define <16 x i8> @vld1dupQi8(ptr %A) nounwind {
;CHECK-LABEL: vld1dupQi8:
;Check the (default) alignment value.
;CHECK: vld1.8 {d16[], d17[]}, [{{r[0-9]+|lr}}]
- %tmp1 = load i8, i8* %A, align 8
+ %tmp1 = load i8, ptr %A, align 8
%tmp2 = insertelement <16 x i8> undef, i8 %tmp1, i32 0
%tmp3 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <16 x i32> zeroinitializer
ret <16 x i8> %tmp3
}
-define <4 x float> @vld1dupQf(float* %A) nounwind {
+define <4 x float> @vld1dupQf(ptr %A) nounwind {
;CHECK-LABEL: vld1dupQf:
;CHECK: vld1.32 {d16[], d17[]}, [{{r[0-9]+|lr}}:32]
- %tmp0 = load float, float* %A
+ %tmp0 = load float, ptr %A
%tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
ret <4 x float> %tmp2
@@ -209,11 +209,11 @@ define <4 x float> @vld1dupQf(float* %A) nounwind {
%struct.__neon_int4x16x2_t = type { <4 x i16>, <4 x i16> }
%struct.__neon_int2x32x2_t = type { <2 x i32>, <2 x i32> }
-define <8 x i8> @vld2dupi8(i8* %A) nounwind {
+define <8 x i8> @vld2dupi8(ptr %A) nounwind {
;CHECK-LABEL: vld2dupi8:
;Check the (default) alignment value.
;CHECK: vld2.8 {d16[0], d17[0]}, [{{r[0-9]+|lr}}]
- %tmp0 = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8* %A, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
+ %tmp0 = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr %A, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
%tmp1 = extractvalue %struct.__neon_int8x8x2_t %tmp0, 0
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp0, 1
@@ -222,69 +222,66 @@ define <8 x i8> @vld2dupi8(i8* %A) nounwind {
ret <8 x i8> %tmp5
}
-define void @vld2dupi8_preinc(%struct.__neon_int8x8x2_t* noalias nocapture sret(%struct.__neon_int8x8x2_t) %agg.result, i8** noalias nocapture %a, i32 %b) nounwind {
+define void @vld2dupi8_preinc(ptr noalias nocapture sret(%struct.__neon_int8x8x2_t) %agg.result, ptr noalias nocapture %a, i32 %b) nounwind {
;CHECK-LABEL: vld2dupi8_preinc:
;CHECK: vld2.8 {d16[], d17[]}, [r2]
entry:
- %0 = load i8*, i8** %a, align 4
- %add.ptr = getelementptr inbounds i8, i8* %0, i32 %b
- %vld_dup = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8* %add.ptr, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
+ %0 = load ptr, ptr %a, align 4
+ %add.ptr = getelementptr inbounds i8, ptr %0, i32 %b
+ %vld_dup = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr %add.ptr, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
%1 = extractvalue %struct.__neon_int8x8x2_t %vld_dup, 0
%lane = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
%2 = extractvalue %struct.__neon_int8x8x2_t %vld_dup, 1
%lane1 = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer
- store i8* %add.ptr, i8** %a, align 4
- %r8 = getelementptr inbounds %struct.__neon_int8x8x2_t, %struct.__neon_int8x8x2_t* %agg.result, i32 0, i32 0
- store <8 x i8> %lane, <8 x i8>* %r8, align 8
- %r11 = getelementptr inbounds %struct.__neon_int8x8x2_t, %struct.__neon_int8x8x2_t* %agg.result, i32 0, i32 1
- store <8 x i8> %lane1, <8 x i8>* %r11, align 8
+ store ptr %add.ptr, ptr %a, align 4
+ store <8 x i8> %lane, ptr %agg.result, align 8
+ %r11 = getelementptr inbounds %struct.__neon_int8x8x2_t, ptr %agg.result, i32 0, i32 1
+ store <8 x i8> %lane1, ptr %r11, align 8
ret void
}
-define void @vld2dupi8_postinc_fixed(%struct.__neon_int8x8x2_t* noalias nocapture sret(%struct.__neon_int8x8x2_t) %agg.result, i8** noalias nocapture %a) nounwind {
+define void @vld2dupi8_postinc_fixed(ptr noalias nocapture sret(%struct.__neon_int8x8x2_t) %agg.result, ptr noalias nocapture %a) nounwind {
entry:
;CHECK-LABEL: vld2dupi8_postinc_fixed:
;CHECK: vld2.8 {d16[], d17[]}, [r2]!
- %0 = load i8*, i8** %a, align 4
- %vld_dup = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8* %0, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
+ %0 = load ptr, ptr %a, align 4
+ %vld_dup = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr %0, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
%1 = extractvalue %struct.__neon_int8x8x2_t %vld_dup, 0
%lane = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
%2 = extractvalue %struct.__neon_int8x8x2_t %vld_dup, 1
%lane1 = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer
- %add.ptr = getelementptr inbounds i8, i8* %0, i32 2
- store i8* %add.ptr, i8** %a, align 4
- %r7 = getelementptr inbounds %struct.__neon_int8x8x2_t, %struct.__neon_int8x8x2_t* %agg.result, i32 0, i32 0
- store <8 x i8> %lane, <8 x i8>* %r7, align 8
- %r10 = getelementptr inbounds %struct.__neon_int8x8x2_t, %struct.__neon_int8x8x2_t* %agg.result, i32 0, i32 1
- store <8 x i8> %lane1, <8 x i8>* %r10, align 8
+ %add.ptr = getelementptr inbounds i8, ptr %0, i32 2
+ store ptr %add.ptr, ptr %a, align 4
+ store <8 x i8> %lane, ptr %agg.result, align 8
+ %r10 = getelementptr inbounds %struct.__neon_int8x8x2_t, ptr %agg.result, i32 0, i32 1
+ store <8 x i8> %lane1, ptr %r10, align 8
ret void
}
-define void @vld2dupi8_postinc_variable(%struct.__neon_int8x8x2_t* noalias nocapture sret(%struct.__neon_int8x8x2_t) %agg.result, i8** noalias nocapture %a, i32 %n) nounwind {
+define void @vld2dupi8_postinc_variable(ptr noalias nocapture sret(%struct.__neon_int8x8x2_t) %agg.result, ptr noalias nocapture %a, i32 %n) nounwind {
entry:
;CHECK-LABEL: vld2dupi8_postinc_variable:
;CHECK: vld2.8 {d16[], d17[]}, [r3], r2
- %0 = load i8*, i8** %a, align 4
- %vld_dup = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8* %0, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
+ %0 = load ptr, ptr %a, align 4
+ %vld_dup = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr %0, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
%1 = extractvalue %struct.__neon_int8x8x2_t %vld_dup, 0
%lane = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
%2 = extractvalue %struct.__neon_int8x8x2_t %vld_dup, 1
%lane1 = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer
- %add.ptr = getelementptr inbounds i8, i8* %0, i32 %n
- store i8* %add.ptr, i8** %a, align 4
- %r7 = getelementptr inbounds %struct.__neon_int8x8x2_t, %struct.__neon_int8x8x2_t* %agg.result, i32 0, i32 0
- store <8 x i8> %lane, <8 x i8>* %r7, align 8
- %r10 = getelementptr inbounds %struct.__neon_int8x8x2_t, %struct.__neon_int8x8x2_t* %agg.result, i32 0, i32 1
- store <8 x i8> %lane1, <8 x i8>* %r10, align 8
+ %add.ptr = getelementptr inbounds i8, ptr %0, i32 %n
+ store ptr %add.ptr, ptr %a, align 4
+ store <8 x i8> %lane, ptr %agg.result, align 8
+ %r10 = getelementptr inbounds %struct.__neon_int8x8x2_t, ptr %agg.result, i32 0, i32 1
+ store <8 x i8> %lane1, ptr %r10, align 8
ret void
}
-define <4 x i16> @vld2dupi16(i8* %A) nounwind {
+define <4 x i16> @vld2dupi16(ptr %A) nounwind {
;CHECK-LABEL: vld2dupi16:
;Check that a power-of-two alignment smaller than the total size of the memory
;being loaded is ignored.
;CHECK: vld2.16 {d16[0], d17[0]}, [{{r[0-9]+|lr}}]
- %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0i8(i8* %A, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2)
+ %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0(ptr %A, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2)
%tmp1 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 0
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
%tmp3 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 1
@@ -294,44 +291,42 @@ define <4 x i16> @vld2dupi16(i8* %A) nounwind {
}
;Check for a post-increment updating load.
-define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind {
+define <4 x i16> @vld2dupi16_update(ptr %ptr) nounwind {
;CHECK-LABEL: vld2dupi16_update:
;CHECK: vld2.16 {d16[0], d17[0]}, [{{r[0-9]+|lr}}]!
- %A = load i16*, i16** %ptr
- %A2 = bitcast i16* %A to i8*
- %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0i8(i8* %A2, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2)
+ %A = load ptr, ptr %ptr
+ %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0(ptr %A, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2)
%tmp1 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 0
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
%tmp3 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 1
%tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer
%tmp5 = add <4 x i16> %tmp2, %tmp4
- %tmp6 = getelementptr i16, i16* %A, i32 2
- store i16* %tmp6, i16** %ptr
+ %tmp6 = getelementptr i16, ptr %A, i32 2
+ store ptr %tmp6, ptr %ptr
ret <4 x i16> %tmp5
}
-define <4 x i16> @vld2dupi16_odd_update(i16** %ptr) nounwind {
+define <4 x i16> @vld2dupi16_odd_update(ptr %ptr) nounwind {
;CHECK-LABEL: vld2dupi16_odd_update:
;CHECK: mov [[INC:r[0-9]+]], #6
;CHECK: vld2.16 {d16[0], d17[0]}, [{{r[0-9]+|lr}}], [[INC]]
- %A = load i16*, i16** %ptr
- %A2 = bitcast i16* %A to i8*
- %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0i8(i8* %A2, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2)
+ %A = load ptr, ptr %ptr
+ %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0(ptr %A, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2)
%tmp1 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 0
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
%tmp3 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 1
%tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer
%tmp5 = add <4 x i16> %tmp2, %tmp4
- %tmp6 = getelementptr i16, i16* %A, i32 3
- store i16* %tmp6, i16** %ptr
+ %tmp6 = getelementptr i16, ptr %A, i32 3
+ store ptr %tmp6, ptr %ptr
ret <4 x i16> %tmp5
}
-define <2 x i32> @vld2dupi32(i8* %A) nounwind {
+define <2 x i32> @vld2dupi32(ptr %A) nounwind {
;CHECK-LABEL: vld2dupi32:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld2.32 {d16[0], d17[0]}, [{{r[0-9]+|lr}}:64]
- %tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32.p0i8(i8* %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16)
+ %tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32.p0(ptr %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16)
%tmp1 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 0
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
%tmp3 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 1
@@ -340,19 +335,19 @@ define <2 x i32> @vld2dupi32(i8* %A) nounwind {
ret <2 x i32> %tmp5
}
-declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
-declare %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0i8(i8*, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
-declare %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32.p0i8(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
+declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
+declare %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0(ptr, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
+declare %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32.p0(ptr, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
%struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> }
;Check for a post-increment updating load with register increment.
-define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind {
+define <8 x i8> @vld3dupi8_update(ptr %ptr, i32 %inc) nounwind {
;CHECK-LABEL: vld3dupi8_update:
;CHECK: vld3.8 {d16[0], d17[0], d18[0]}, [{{r[0-9]+|lr}}], r1
- %A = load i8*, i8** %ptr
- %tmp0 = tail call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0i8(i8* %A, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 8)
+ %A = load ptr, ptr %ptr
+ %tmp0 = tail call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0(ptr %A, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 8)
%tmp1 = extractvalue %struct.__neon_int8x8x3_t %tmp0, 0
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp0, 1
@@ -361,16 +356,16 @@ define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind {
%tmp6 = shufflevector <8 x i8> %tmp5, <8 x i8> undef, <8 x i32> zeroinitializer
%tmp7 = add <8 x i8> %tmp2, %tmp4
%tmp8 = add <8 x i8> %tmp7, %tmp6
- %tmp9 = getelementptr i8, i8* %A, i32 %inc
- store i8* %tmp9, i8** %ptr
+ %tmp9 = getelementptr i8, ptr %A, i32 %inc
+ store ptr %tmp9, ptr %ptr
ret <8 x i8> %tmp8
}
-define <4 x i16> @vld3dupi16(i8* %A) nounwind {
+define <4 x i16> @vld3dupi16(ptr %A) nounwind {
;CHECK-LABEL: vld3dupi16:
;Check the (default) alignment value. VLD3 does not support alignment.
;CHECK: vld3.16 {d16[0], d17[0], d18[0]}, [{{r[0-9]+|lr}}]
- %tmp0 = tail call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0i8(i8* %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 8)
+ %tmp0 = tail call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0(ptr %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 8)
%tmp1 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 0
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
%tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 1
@@ -382,19 +377,18 @@ define <4 x i16> @vld3dupi16(i8* %A) nounwind {
ret <4 x i16> %tmp8
}
-declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
-declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0i8(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
+declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0(ptr, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
+declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0(ptr, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
;Check for a post-increment updating load.
-define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind {
+define <4 x i16> @vld4dupi16_update(ptr %ptr) nounwind {
;CHECK-LABEL: vld4dupi16_update:
;CHECK: vld4.16 {d16[0], d17[0], d18[0], d19[0]}, [{{r[0-9]+|lr}}]!
- %A = load i16*, i16** %ptr
- %A2 = bitcast i16* %A to i8*
- %tmp0 = tail call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16.p0i8(i8* %A2, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 1)
+ %A = load ptr, ptr %ptr
+ %tmp0 = tail call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16.p0(ptr %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 1)
%tmp1 = extractvalue %struct.__neon_int16x4x4_t %tmp0, 0
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
%tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp0, 1
@@ -406,17 +400,17 @@ define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind {
%tmp9 = add <4 x i16> %tmp2, %tmp4
%tmp10 = add <4 x i16> %tmp6, %tmp8
%tmp11 = add <4 x i16> %tmp9, %tmp10
- %tmp12 = getelementptr i16, i16* %A, i32 4
- store i16* %tmp12, i16** %ptr
+ %tmp12 = getelementptr i16, ptr %A, i32 4
+ store ptr %tmp12, ptr %ptr
ret <4 x i16> %tmp11
}
-define <2 x i32> @vld4dupi32(i8* %A) nounwind {
+define <2 x i32> @vld4dupi32(ptr %A) nounwind {
;CHECK-LABEL: vld4dupi32:
;Check the alignment value. An 8-byte alignment is allowed here even though
;it is smaller than the total size of the memory being loaded.
;CHECK: vld4.32 {d16[0], d17[0], d18[0], d19[0]}, [{{r[0-9]+|lr}}:64]
- %tmp0 = tail call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32.p0i8(i8* %A, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 8)
+ %tmp0 = tail call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32.p0(ptr %A, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 8)
%tmp1 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 0
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
%tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 1
@@ -431,5 +425,5 @@ define <2 x i32> @vld4dupi32(i8* %A) nounwind {
ret <2 x i32> %tmp11
}
-declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16.p0i8(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
-declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32.p0i8(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
+declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16.p0(ptr, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
+declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32.p0(ptr, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
diff --git a/llvm/test/CodeGen/ARM/vldlane.ll b/llvm/test/CodeGen/ARM/vldlane.ll
index 312337e246f54..f6ddc9988877e 100644
--- a/llvm/test/CodeGen/ARM/vldlane.ll
+++ b/llvm/test/CodeGen/ARM/vldlane.ll
@@ -3,75 +3,75 @@
; RUN: llc < %s -mtriple=arm-eabi -float-abi=soft -mattr=+neon -regalloc=basic | FileCheck %s --check-prefixes=CHECK,BASIC
;Check the (default) alignment value.
-define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vld1lanei8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld1lanei8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vld1.8 {d16[3]}, [r0]
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %B
- %tmp2 = load i8, i8* %A, align 8
+ %tmp1 = load <8 x i8>, ptr %B
+ %tmp2 = load i8, ptr %A, align 8
%tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 3
ret <8 x i8> %tmp3
}
;Check the alignment value. Max for this instruction is 16 bits:
-define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vld1lanei16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld1lanei16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vld1.16 {d16[2]}, [r0:16]
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %B
- %tmp2 = load i16, i16* %A, align 8
+ %tmp1 = load <4 x i16>, ptr %B
+ %tmp2 = load i16, ptr %A, align 8
%tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 2
ret <4 x i16> %tmp3
}
;Check the alignment value. Max for this instruction is 32 bits:
-define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vld1lanei32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld1lanei32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vld1.32 {d16[1]}, [r0:32]
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %B
- %tmp2 = load i32, i32* %A, align 8
+ %tmp1 = load <2 x i32>, ptr %B
+ %tmp2 = load i32, ptr %A, align 8
%tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
ret <2 x i32> %tmp3
}
;Check the alignment value. Legal values are none or :32.
-define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vld1lanei32a32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld1lanei32a32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vld1.32 {d16[1]}, [r0:32]
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %B
- %tmp2 = load i32, i32* %A, align 4
+ %tmp1 = load <2 x i32>, ptr %B
+ %tmp2 = load i32, ptr %A, align 4
%tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
ret <2 x i32> %tmp3
}
-define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind {
+define <2 x float> @vld1lanef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld1lanef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vld1.32 {d16[1]}, [r0:32]
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %B
- %tmp2 = load float, float* %A, align 4
+ %tmp1 = load <2 x float>, ptr %B
+ %tmp2 = load float, ptr %A, align 4
%tmp3 = insertelement <2 x float> %tmp1, float %tmp2, i32 1
ret <2 x float> %tmp3
}
-define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vld1laneQi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld1laneQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -79,13 +79,13 @@ define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %B
- %tmp2 = load i8, i8* %A, align 8
+ %tmp1 = load <16 x i8>, ptr %B
+ %tmp2 = load i8, ptr %A, align 8
%tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 9
ret <16 x i8> %tmp3
}
-define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vld1laneQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld1laneQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -93,13 +93,13 @@ define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %B
- %tmp2 = load i16, i16* %A, align 8
+ %tmp1 = load <8 x i16>, ptr %B
+ %tmp2 = load i16, ptr %A, align 8
%tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 5
ret <8 x i16> %tmp3
}
-define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vld1laneQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld1laneQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -107,13 +107,13 @@ define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %B
- %tmp2 = load i32, i32* %A, align 8
+ %tmp1 = load <4 x i32>, ptr %B
+ %tmp2 = load i32, ptr %A, align 8
%tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 3
ret <4 x i32> %tmp3
}
-define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind {
+define <4 x float> @vld1laneQf(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld1laneQf:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -121,8 +121,8 @@ define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind {
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %B
- %tmp2 = load float, float* %A
+ %tmp1 = load <4 x float>, ptr %B
+ %tmp2 = load float, ptr %A
%tmp3 = insertelement <4 x float> %tmp1, float %tmp2, i32 0
ret <4 x float> %tmp3
}
@@ -137,7 +137,7 @@ define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind {
%struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
;Check the alignment value. Max for this instruction is 16 bits:
-define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vld2lanei8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld2lanei8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -146,8 +146,8 @@ define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vadd.i8 d16, d16, d17
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %B
- %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
+ %tmp1 = load <8 x i8>, ptr %B
+ %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1
%tmp5 = add <8 x i8> %tmp3, %tmp4
@@ -155,7 +155,7 @@ define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
}
;Check the alignment value. Max for this instruction is 32 bits:
-define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vld2lanei16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld2lanei16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -164,16 +164,15 @@ define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vadd.i16 d16, d16, d17
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <4 x i16>, <4 x i16>* %B
- %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16.p0i8(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
+ %tmp1 = load <4 x i16>, ptr %B
+ %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16.p0(ptr %A, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
%tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 1
%tmp5 = add <4 x i16> %tmp3, %tmp4
ret <4 x i16> %tmp5
}
-define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vld2lanei32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld2lanei32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -182,9 +181,8 @@ define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: vadd.i32 d16, d16, d17
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <2 x i32>, <2 x i32>* %B
- %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32.p0i8(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
+ %tmp1 = load <2 x i32>, ptr %B
+ %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32.p0(ptr %A, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
%tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1
%tmp5 = add <2 x i32> %tmp3, %tmp4
@@ -192,7 +190,7 @@ define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind {
}
;Check for a post-increment updating load.
-define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind {
+define <2 x i32> @vld2lanei32_update(ptr %ptr, ptr %B) nounwind {
; DEFAULT-LABEL: vld2lanei32_update:
; DEFAULT: @ %bb.0:
; DEFAULT-NEXT: vldr d16, [r1]
@@ -219,19 +217,18 @@ define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind {
; BASIC-NEXT: mov r0, r2
; BASIC-NEXT: mov r1, r3
; BASIC-NEXT: mov pc, lr
- %A = load i32*, i32** %ptr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <2 x i32>, <2 x i32>* %B
- %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32.p0i8(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <2 x i32>, ptr %B
+ %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32.p0(ptr %A, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
%tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1
%tmp5 = add <2 x i32> %tmp3, %tmp4
- %tmp6 = getelementptr i32, i32* %A, i32 2
- store i32* %tmp6, i32** %ptr
+ %tmp6 = getelementptr i32, ptr %A, i32 2
+ store ptr %tmp6, ptr %ptr
ret <2 x i32> %tmp5
}
-define <2 x i32> @vld2lanei32_odd_update(i32** %ptr, <2 x i32>* %B) nounwind {
+define <2 x i32> @vld2lanei32_odd_update(ptr %ptr, ptr %B) nounwind {
; DEFAULT-LABEL: vld2lanei32_odd_update:
; DEFAULT: @ %bb.0:
; DEFAULT-NEXT: vldr d16, [r1]
@@ -260,19 +257,18 @@ define <2 x i32> @vld2lanei32_odd_update(i32** %ptr, <2 x i32>* %B) nounwind {
; BASIC-NEXT: mov r0, r2
; BASIC-NEXT: mov r1, r3
; BASIC-NEXT: mov pc, lr
- %A = load i32*, i32** %ptr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <2 x i32>, <2 x i32>* %B
- %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32.p0i8(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <2 x i32>, ptr %B
+ %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32.p0(ptr %A, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
%tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1
%tmp5 = add <2 x i32> %tmp3, %tmp4
- %tmp6 = getelementptr i32, i32* %A, i32 3
- store i32* %tmp6, i32** %ptr
+ %tmp6 = getelementptr i32, ptr %A, i32 3
+ store ptr %tmp6, ptr %ptr
ret <2 x i32> %tmp5
}
-define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind {
+define <2 x float> @vld2lanef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld2lanef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -281,9 +277,8 @@ define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind {
; CHECK-NEXT: vadd.f32 d16, d16, d17
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <2 x float>, <2 x float>* %B
- %tmp2 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32.p0i8(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
+ %tmp1 = load <2 x float>, ptr %B
+ %tmp2 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32.p0(ptr %A, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
%tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 1
%tmp5 = fadd <2 x float> %tmp3, %tmp4
@@ -291,7 +286,7 @@ define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind {
}
;Check the (default) alignment.
-define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vld2laneQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld2laneQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -301,9 +296,8 @@ define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <8 x i16>, <8 x i16>* %B
- %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0i8(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1)
+ %tmp1 = load <8 x i16>, ptr %B
+ %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0(ptr %A, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1)
%tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1
%tmp5 = add <8 x i16> %tmp3, %tmp4
@@ -311,7 +305,7 @@ define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
}
;Check the alignment value. Max for this instruction is 64 bits:
-define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vld2laneQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld2laneQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -321,16 +315,15 @@ define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <4 x i32>, <4 x i32>* %B
- %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32.p0i8(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16)
+ %tmp1 = load <4 x i32>, ptr %B
+ %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32.p0(ptr %A, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16)
%tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1
%tmp5 = add <4 x i32> %tmp3, %tmp4
ret <4 x i32> %tmp5
}
-define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind {
+define <4 x float> @vld2laneQf(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld2laneQf:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -340,23 +333,22 @@ define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <4 x float>, <4 x float>* %B
- %tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32.p0i8(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
+ %tmp1 = load <4 x float>, ptr %B
+ %tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32.p0(ptr %A, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
%tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 1
%tmp5 = fadd <4 x float> %tmp3, %tmp4
ret <4 x float> %tmp5
}
-declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
-declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16.p0i8(i8*, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
-declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32.p0i8(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
-declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32.p0i8(i8*, <2 x float>, <2 x float>, i32, i32) nounwind readonly
+declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
+declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16.p0(ptr, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
+declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32.p0(ptr, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
+declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32.p0(ptr, <2 x float>, <2 x float>, i32, i32) nounwind readonly
-declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0i8(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
-declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32.p0i8(i8*, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly
-declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32.p0i8(i8*, <4 x float>, <4 x float>, i32, i32) nounwind readonly
+declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0(ptr, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
+declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32.p0(ptr, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly
+declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32.p0(ptr, <4 x float>, <4 x float>, i32, i32) nounwind readonly
%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
%struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> }
@@ -367,7 +359,7 @@ declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32.p0i8(i8*, <4
%struct.__neon_int32x4x3_t = type { <4 x i32>, <4 x i32>, <4 x i32> }
%struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
-define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vld3lanei8(ptr %A, ptr %B) nounwind {
; DEFAULT-LABEL: vld3lanei8:
; DEFAULT: @ %bb.0:
; DEFAULT-NEXT: vldr d16, [r1]
@@ -389,8 +381,8 @@ define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
; BASIC-NEXT: vadd.i8 d16, d20, d16
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %B
- %tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
+ %tmp1 = load <8 x i8>, ptr %B
+ %tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0(ptr %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2
@@ -400,7 +392,7 @@ define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
}
;Check the (default) alignment value. VLD3 does not support alignment.
-define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vld3lanei16(ptr %A, ptr %B) nounwind {
; DEFAULT-LABEL: vld3lanei16:
; DEFAULT: @ %bb.0:
; DEFAULT-NEXT: vldr d16, [r1]
@@ -422,9 +414,8 @@ define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind {
; BASIC-NEXT: vadd.i16 d16, d20, d16
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: mov pc, lr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <4 x i16>, <4 x i16>* %B
- %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0i8(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
+ %tmp1 = load <4 x i16>, ptr %B
+ %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0(ptr %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
%tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 2
@@ -433,7 +424,7 @@ define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind {
ret <4 x i16> %tmp7
}
-define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vld3lanei32(ptr %A, ptr %B) nounwind {
; DEFAULT-LABEL: vld3lanei32:
; DEFAULT: @ %bb.0:
; DEFAULT-NEXT: vldr d16, [r1]
@@ -455,9 +446,8 @@ define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind {
; BASIC-NEXT: vadd.i32 d16, d20, d16
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: mov pc, lr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <2 x i32>, <2 x i32>* %B
- %tmp2 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32.p0i8(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
+ %tmp1 = load <2 x i32>, ptr %B
+ %tmp2 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32.p0(ptr %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
%tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 2
@@ -466,7 +456,7 @@ define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind {
ret <2 x i32> %tmp7
}
-define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
+define <2 x float> @vld3lanef(ptr %A, ptr %B) nounwind {
; DEFAULT-LABEL: vld3lanef:
; DEFAULT: @ %bb.0:
; DEFAULT-NEXT: vldr d16, [r1]
@@ -488,9 +478,8 @@ define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
; BASIC-NEXT: vadd.f32 d16, d20, d16
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: mov pc, lr
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <2 x float>, <2 x float>* %B
- %tmp2 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32.p0i8(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
+ %tmp1 = load <2 x float>, ptr %B
+ %tmp2 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32.p0(ptr %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
%tmp3 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 2
@@ -500,7 +489,7 @@ define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
}
;Check the (default) alignment value. VLD3 does not support alignment.
-define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vld3laneQi16(ptr %A, ptr %B) nounwind {
; DEFAULT-LABEL: vld3laneQi16:
; DEFAULT: @ %bb.0:
; DEFAULT-NEXT: vld1.64 {d16, d17}, [r1]
@@ -524,9 +513,8 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: vmov r2, r3, d17
; BASIC-NEXT: mov pc, lr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <8 x i16>, <8 x i16>* %B
- %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16.p0i8(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8)
+ %tmp1 = load <8 x i16>, ptr %B
+ %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16.p0(ptr %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8)
%tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2
@@ -536,7 +524,7 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
}
;Check for a post-increment updating load with register increment.
-define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
+define <8 x i16> @vld3laneQi16_update(ptr %ptr, ptr %B, i32 %inc) nounwind {
; DEFAULT-LABEL: vld3laneQi16_update:
; DEFAULT: @ %bb.0:
; DEFAULT-NEXT: .save {r11, lr}
@@ -577,21 +565,20 @@ define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounw
; BASIC-NEXT: mov r3, r12
; BASIC-NEXT: pop {r11, lr}
; BASIC-NEXT: mov pc, lr
- %A = load i16*, i16** %ptr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <8 x i16>, <8 x i16>* %B
- %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16.p0i8(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8)
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <8 x i16>, ptr %B
+ %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16.p0(ptr %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8)
%tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2
%tmp6 = add <8 x i16> %tmp3, %tmp4
%tmp7 = add <8 x i16> %tmp5, %tmp6
- %tmp8 = getelementptr i16, i16* %A, i32 %inc
- store i16* %tmp8, i16** %ptr
+ %tmp8 = getelementptr i16, ptr %A, i32 %inc
+ store ptr %tmp8, ptr %ptr
ret <8 x i16> %tmp7
}
-define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vld3laneQi32(ptr %A, ptr %B) nounwind {
; DEFAULT-LABEL: vld3laneQi32:
; DEFAULT: @ %bb.0:
; DEFAULT-NEXT: vld1.64 {d16, d17}, [r1]
@@ -615,9 +602,8 @@ define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: vmov r2, r3, d17
; BASIC-NEXT: mov pc, lr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <4 x i32>, <4 x i32>* %B
- %tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32.p0i8(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 3, i32 1)
+ %tmp1 = load <4 x i32>, ptr %B
+ %tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32.p0(ptr %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 3, i32 1)
%tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 2
@@ -626,7 +612,7 @@ define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
ret <4 x i32> %tmp7
}
-define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind {
+define <4 x float> @vld3laneQf(ptr %A, ptr %B) nounwind {
; DEFAULT-LABEL: vld3laneQf:
; DEFAULT: @ %bb.0:
; DEFAULT-NEXT: vld1.64 {d16, d17}, [r1]
@@ -650,9 +636,8 @@ define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind {
; BASIC-NEXT: vmov r0, r1, d16
; BASIC-NEXT: vmov r2, r3, d17
; BASIC-NEXT: mov pc, lr
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <4 x float>, <4 x float>* %B
- %tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32.p0i8(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
+ %tmp1 = load <4 x float>, ptr %B
+ %tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32.p0(ptr %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
%tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 2
@@ -661,14 +646,14 @@ define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind {
ret <4 x float> %tmp7
}
-declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
-declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0i8(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
-declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32.p0i8(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
-declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32.p0i8(i8*, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind readonly
+declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0(ptr, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
+declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0(ptr, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
+declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32.p0(ptr, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
+declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32.p0(ptr, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind readonly
-declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16.p0i8(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
-declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32.p0i8(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly
-declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32.p0i8(i8*, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly
+declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16.p0(ptr, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
+declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32.p0(ptr, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly
+declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32.p0(ptr, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly
%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
@@ -680,7 +665,7 @@ declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32.p0i8(i8*, <4
%struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
;Check the alignment value. Max for this instruction is 32 bits:
-define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vld4lanei8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld4lanei8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -693,8 +678,8 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vadd.i8 d16, d16, d20
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %B
- %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
+ %tmp1 = load <8 x i8>, ptr %B
+ %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8.p0(ptr %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
@@ -706,7 +691,7 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
}
;Check for a post-increment updating load.
-define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
+define <8 x i8> @vld4lanei8_update(ptr %ptr, ptr %B) nounwind {
; DEFAULT-LABEL: vld4lanei8_update:
; DEFAULT: @ %bb.0:
; DEFAULT-NEXT: vldr d16, [r1]
@@ -740,9 +725,9 @@ define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
; BASIC-NEXT: mov r0, r1
; BASIC-NEXT: mov r1, r2
; BASIC-NEXT: mov pc, lr
- %A = load i8*, i8** %ptr
- %tmp1 = load <8 x i8>, <8 x i8>* %B
- %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <8 x i8>, ptr %B
+ %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8.p0(ptr %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
@@ -750,14 +735,14 @@ define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
%tmp7 = add <8 x i8> %tmp3, %tmp4
%tmp8 = add <8 x i8> %tmp5, %tmp6
%tmp9 = add <8 x i8> %tmp7, %tmp8
- %tmp10 = getelementptr i8, i8* %A, i32 4
- store i8* %tmp10, i8** %ptr
+ %tmp10 = getelementptr i8, ptr %A, i32 4
+ store ptr %tmp10, ptr %ptr
ret <8 x i8> %tmp9
}
;Check that a power-of-two alignment smaller than the total size of the memory
;being loaded is ignored.
-define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vld4lanei16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld4lanei16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -770,9 +755,8 @@ define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vadd.i16 d16, d16, d20
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <4 x i16>, <4 x i16>* %B
- %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16.p0i8(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 4)
+ %tmp1 = load <4 x i16>, ptr %B
+ %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16.p0(ptr %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 4)
%tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 2
@@ -785,7 +769,7 @@ define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind {
;Check the alignment value. An 8-byte alignment is allowed here even though
;it is smaller than the total size of the memory being loaded.
-define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vld4lanei32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld4lanei32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -798,9 +782,8 @@ define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: vadd.i32 d16, d16, d20
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <2 x i32>, <2 x i32>* %B
- %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32.p0i8(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 8)
+ %tmp1 = load <2 x i32>, ptr %B
+ %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32.p0(ptr %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 8)
%tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 2
@@ -811,7 +794,7 @@ define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind {
ret <2 x i32> %tmp9
}
-define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind {
+define <2 x float> @vld4lanef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld4lanef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -824,9 +807,8 @@ define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind {
; CHECK-NEXT: vadd.f32 d16, d16, d20
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <2 x float>, <2 x float>* %B
- %tmp2 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32.p0i8(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
+ %tmp1 = load <2 x float>, ptr %B
+ %tmp2 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32.p0(ptr %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
%tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 2
@@ -838,7 +820,7 @@ define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind {
}
;Check the alignment value. Max for this instruction is 64 bits:
-define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vld4laneQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld4laneQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -852,9 +834,8 @@ define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <8 x i16>, <8 x i16>* %B
- %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16.p0i8(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 16)
+ %tmp1 = load <8 x i16>, ptr %B
+ %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16.p0(ptr %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 16)
%tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 2
@@ -866,7 +847,7 @@ define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
}
;Check the (default) alignment.
-define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vld4laneQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld4laneQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -880,9 +861,8 @@ define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <4 x i32>, <4 x i32>* %B
- %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32.p0i8(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1)
+ %tmp1 = load <4 x i32>, ptr %B
+ %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32.p0(ptr %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1)
%tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 2
@@ -893,7 +873,7 @@ define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
ret <4 x i32> %tmp9
}
-define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind {
+define <4 x float> @vld4laneQf(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vld4laneQf:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -907,9 +887,8 @@ define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <4 x float>, <4 x float>* %B
- %tmp2 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32.p0i8(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
+ %tmp1 = load <4 x float>, ptr %B
+ %tmp2 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32.p0(ptr %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
%tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 2
@@ -920,14 +899,14 @@ define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind {
ret <4 x float> %tmp9
}
-declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
-declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16.p0i8(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
-declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32.p0i8(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
-declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32.p0i8(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind readonly
+declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8.p0(ptr, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
+declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16.p0(ptr, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
+declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32.p0(ptr, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
+declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32.p0(ptr, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind readonly
-declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16.p0i8(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
-declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32.p0i8(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly
-declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32.p0i8(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly
+declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16.p0(ptr, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
+declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32.p0(ptr, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly
+declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32.p0(ptr, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly
; Radar 8776599: If one of the operands to a QQQQ REG_SEQUENCE is a register
; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because
@@ -966,7 +945,7 @@ define <8 x i16> @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind {
%tmp65 = shl i128 %tmp64, 64
%ins67 = or i128 %tmp65, 0
%tmp78 = bitcast i128 %ins67 to <8 x i16>
- %vld3_lane = tail call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16.p0i8(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> %tmp78, i32 1, i32 2)
+ %vld3_lane = tail call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16.p0(ptr undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> %tmp78, i32 1, i32 2)
%tmp3 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 0
%tmp4 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 1
%tmp5 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 2
diff --git a/llvm/test/CodeGen/ARM/vldm-liveness.ll b/llvm/test/CodeGen/ARM/vldm-liveness.ll
index 63dc9d61ebcca..347a4de5bbe6a 100644
--- a/llvm/test/CodeGen/ARM/vldm-liveness.ll
+++ b/llvm/test/CodeGen/ARM/vldm-liveness.ll
@@ -4,19 +4,18 @@
;
; See vldm-liveness.mir for the bug this file originally testing.
-define arm_aapcs_vfpcc <4 x float> @foo(float* %ptr) {
+define arm_aapcs_vfpcc <4 x float> @foo(ptr %ptr) {
; CHECK-LABEL: foo:
; CHECK: vldmia r0, {s0, s1}
; CHECK: vldr s3, [r0, #8]
; CHECK: vldr s2, [r0, #16]
- %off0 = getelementptr float, float* %ptr, i32 0
- %val0 = load float, float* %off0
- %off1 = getelementptr float, float* %ptr, i32 1
- %val1 = load float, float* %off1
- %off4 = getelementptr float, float* %ptr, i32 4
- %val4 = load float, float* %off4
- %off2 = getelementptr float, float* %ptr, i32 2
- %val2 = load float, float* %off2
+ %val0 = load float, ptr %ptr
+ %off1 = getelementptr float, ptr %ptr, i32 1
+ %val1 = load float, ptr %off1
+ %off4 = getelementptr float, ptr %ptr, i32 4
+ %val4 = load float, ptr %off4
+ %off2 = getelementptr float, ptr %ptr, i32 2
+ %val2 = load float, ptr %off2
%vec1 = insertelement <4 x float> undef, float %val0, i32 0
%vec2 = insertelement <4 x float> %vec1, float %val1, i32 1
diff --git a/llvm/test/CodeGen/ARM/vldm-sched-a9.ll b/llvm/test/CodeGen/ARM/vldm-sched-a9.ll
index 1e4692bfc636a..892b2610c73b2 100644
--- a/llvm/test/CodeGen/ARM/vldm-sched-a9.ll
+++ b/llvm/test/CodeGen/ARM/vldm-sched-a9.ll
@@ -28,73 +28,71 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
; CHECK: test:
; CHECK: vldmia r{{.*}}, {d{{.*}}, d{{.*}}}
; CHECK: vldmia r{{.*}}, {d{{.*}}, d{{.*}}}
-define <16 x i64> @test(i64* %src0, i64* %src1) #0 {
+define <16 x i64> @test(ptr %src0, ptr %src1) #0 {
entry:
- %addr.0 = getelementptr inbounds i64, i64* %src0, i32 0
- %el.0 = load i64, i64* %addr.0, align 8
- %addr.1 = getelementptr inbounds i64, i64* %src0, i32 1
- %el.1 = load i64, i64* %addr.1, align 8
- %addr.2 = getelementptr inbounds i64, i64* %src0, i32 2
- %el.2 = load i64, i64* %addr.2, align 8
- %addr.3 = getelementptr inbounds i64, i64* %src0, i32 3
- %el.3 = load i64, i64* %addr.3, align 8
- %addr.4 = getelementptr inbounds i64, i64* %src0, i32 4
- %el.4 = load i64, i64* %addr.4, align 8
- %addr.5 = getelementptr inbounds i64, i64* %src0, i32 5
- %el.5 = load i64, i64* %addr.5, align 8
- %addr.6 = getelementptr inbounds i64, i64* %src0, i32 6
- %el.6 = load i64, i64* %addr.6, align 8
- %addr.7 = getelementptr inbounds i64, i64* %src0, i32 7
- %el.7 = load i64, i64* %addr.7, align 8
- %addr.8 = getelementptr inbounds i64, i64* %src0, i32 8
- %el.8 = load i64, i64* %addr.8, align 8
- %addr.9 = getelementptr inbounds i64, i64* %src0, i32 9
- %el.9 = load i64, i64* %addr.9, align 8
- %addr.10 = getelementptr inbounds i64, i64* %src0, i32 10
- %el.10 = load i64, i64* %addr.10, align 8
- %addr.11 = getelementptr inbounds i64, i64* %src0, i32 11
- %el.11 = load i64, i64* %addr.11, align 8
- %addr.12 = getelementptr inbounds i64, i64* %src0, i32 12
- %el.12 = load i64, i64* %addr.12, align 8
- %addr.13 = getelementptr inbounds i64, i64* %src0, i32 13
- %el.13 = load i64, i64* %addr.13, align 8
- %addr.14 = getelementptr inbounds i64, i64* %src0, i32 14
- %el.14 = load i64, i64* %addr.14, align 8
- %addr.15 = getelementptr inbounds i64, i64* %src0, i32 15
- %el.15 = load i64, i64* %addr.15, align 8
+ %el.0 = load i64, ptr %src0, align 8
+ %addr.1 = getelementptr inbounds i64, ptr %src0, i32 1
+ %el.1 = load i64, ptr %addr.1, align 8
+ %addr.2 = getelementptr inbounds i64, ptr %src0, i32 2
+ %el.2 = load i64, ptr %addr.2, align 8
+ %addr.3 = getelementptr inbounds i64, ptr %src0, i32 3
+ %el.3 = load i64, ptr %addr.3, align 8
+ %addr.4 = getelementptr inbounds i64, ptr %src0, i32 4
+ %el.4 = load i64, ptr %addr.4, align 8
+ %addr.5 = getelementptr inbounds i64, ptr %src0, i32 5
+ %el.5 = load i64, ptr %addr.5, align 8
+ %addr.6 = getelementptr inbounds i64, ptr %src0, i32 6
+ %el.6 = load i64, ptr %addr.6, align 8
+ %addr.7 = getelementptr inbounds i64, ptr %src0, i32 7
+ %el.7 = load i64, ptr %addr.7, align 8
+ %addr.8 = getelementptr inbounds i64, ptr %src0, i32 8
+ %el.8 = load i64, ptr %addr.8, align 8
+ %addr.9 = getelementptr inbounds i64, ptr %src0, i32 9
+ %el.9 = load i64, ptr %addr.9, align 8
+ %addr.10 = getelementptr inbounds i64, ptr %src0, i32 10
+ %el.10 = load i64, ptr %addr.10, align 8
+ %addr.11 = getelementptr inbounds i64, ptr %src0, i32 11
+ %el.11 = load i64, ptr %addr.11, align 8
+ %addr.12 = getelementptr inbounds i64, ptr %src0, i32 12
+ %el.12 = load i64, ptr %addr.12, align 8
+ %addr.13 = getelementptr inbounds i64, ptr %src0, i32 13
+ %el.13 = load i64, ptr %addr.13, align 8
+ %addr.14 = getelementptr inbounds i64, ptr %src0, i32 14
+ %el.14 = load i64, ptr %addr.14, align 8
+ %addr.15 = getelementptr inbounds i64, ptr %src0, i32 15
+ %el.15 = load i64, ptr %addr.15, align 8
- %addr.0.1 = getelementptr inbounds i64, i64* %src1, i32 0
- %el.0.1 = load i64, i64* %addr.0.1, align 8
- %addr.1.1 = getelementptr inbounds i64, i64* %src1, i32 1
- %el.1.1 = load i64, i64* %addr.1.1, align 8
- %addr.2.1 = getelementptr inbounds i64, i64* %src1, i32 2
- %el.2.1 = load i64, i64* %addr.2.1, align 8
- %addr.3.1 = getelementptr inbounds i64, i64* %src1, i32 3
- %el.3.1 = load i64, i64* %addr.3.1, align 8
- %addr.4.1 = getelementptr inbounds i64, i64* %src1, i32 4
- %el.4.1 = load i64, i64* %addr.4.1, align 8
- %addr.5.1 = getelementptr inbounds i64, i64* %src1, i32 5
- %el.5.1 = load i64, i64* %addr.5.1, align 8
- %addr.6.1 = getelementptr inbounds i64, i64* %src1, i32 6
- %el.6.1 = load i64, i64* %addr.6.1, align 8
- %addr.7.1 = getelementptr inbounds i64, i64* %src1, i32 7
- %el.7.1 = load i64, i64* %addr.7.1, align 8
- %addr.8.1 = getelementptr inbounds i64, i64* %src1, i32 8
- %el.8.1 = load i64, i64* %addr.8.1, align 8
- %addr.9.1 = getelementptr inbounds i64, i64* %src1, i32 9
- %el.9.1 = load i64, i64* %addr.9.1, align 8
- %addr.10.1 = getelementptr inbounds i64, i64* %src1, i32 10
- %el.10.1 = load i64, i64* %addr.10.1, align 8
- %addr.11.1 = getelementptr inbounds i64, i64* %src1, i32 11
- %el.11.1 = load i64, i64* %addr.11.1, align 8
- %addr.12.1 = getelementptr inbounds i64, i64* %src1, i32 12
- %el.12.1 = load i64, i64* %addr.12.1, align 8
- %addr.13.1 = getelementptr inbounds i64, i64* %src1, i32 13
- %el.13.1 = load i64, i64* %addr.13.1, align 8
- %addr.14.1 = getelementptr inbounds i64, i64* %src1, i32 14
- %el.14.1 = load i64, i64* %addr.14.1, align 8
- %addr.15.1 = getelementptr inbounds i64, i64* %src1, i32 15
- %el.15.1 = load i64, i64* %addr.15.1, align 8
+ %el.0.1 = load i64, ptr %src1, align 8
+ %addr.1.1 = getelementptr inbounds i64, ptr %src1, i32 1
+ %el.1.1 = load i64, ptr %addr.1.1, align 8
+ %addr.2.1 = getelementptr inbounds i64, ptr %src1, i32 2
+ %el.2.1 = load i64, ptr %addr.2.1, align 8
+ %addr.3.1 = getelementptr inbounds i64, ptr %src1, i32 3
+ %el.3.1 = load i64, ptr %addr.3.1, align 8
+ %addr.4.1 = getelementptr inbounds i64, ptr %src1, i32 4
+ %el.4.1 = load i64, ptr %addr.4.1, align 8
+ %addr.5.1 = getelementptr inbounds i64, ptr %src1, i32 5
+ %el.5.1 = load i64, ptr %addr.5.1, align 8
+ %addr.6.1 = getelementptr inbounds i64, ptr %src1, i32 6
+ %el.6.1 = load i64, ptr %addr.6.1, align 8
+ %addr.7.1 = getelementptr inbounds i64, ptr %src1, i32 7
+ %el.7.1 = load i64, ptr %addr.7.1, align 8
+ %addr.8.1 = getelementptr inbounds i64, ptr %src1, i32 8
+ %el.8.1 = load i64, ptr %addr.8.1, align 8
+ %addr.9.1 = getelementptr inbounds i64, ptr %src1, i32 9
+ %el.9.1 = load i64, ptr %addr.9.1, align 8
+ %addr.10.1 = getelementptr inbounds i64, ptr %src1, i32 10
+ %el.10.1 = load i64, ptr %addr.10.1, align 8
+ %addr.11.1 = getelementptr inbounds i64, ptr %src1, i32 11
+ %el.11.1 = load i64, ptr %addr.11.1, align 8
+ %addr.12.1 = getelementptr inbounds i64, ptr %src1, i32 12
+ %el.12.1 = load i64, ptr %addr.12.1, align 8
+ %addr.13.1 = getelementptr inbounds i64, ptr %src1, i32 13
+ %el.13.1 = load i64, ptr %addr.13.1, align 8
+ %addr.14.1 = getelementptr inbounds i64, ptr %src1, i32 14
+ %el.14.1 = load i64, ptr %addr.14.1, align 8
+ %addr.15.1 = getelementptr inbounds i64, ptr %src1, i32 15
+ %el.15.1 = load i64, ptr %addr.15.1, align 8
%vec.0 = insertelement <16 x i64> undef, i64 %el.0, i32 0
%vec.1 = insertelement <16 x i64> %vec.0, i64 %el.1, i32 1
%vec.2 = insertelement <16 x i64> %vec.1, i64 %el.2, i32 2
@@ -111,7 +109,7 @@ entry:
%vec.13 = insertelement <16 x i64> %vec.12, i64 %el.13, i32 13
%vec.14 = insertelement <16 x i64> %vec.13, i64 %el.14, i32 14
%vec.15 = insertelement <16 x i64> %vec.14, i64 %el.15, i32 15
- call void @capture(i64* %src0, i64* %src1)
+ call void @capture(ptr %src0, ptr %src1)
%vec.0.1 = insertelement <16 x i64> undef, i64 %el.0.1, i32 0
%vec.1.1 = insertelement <16 x i64> %vec.0.1, i64 %el.1.1, i32 1
%vec.2.1 = insertelement <16 x i64> %vec.1.1, i64 %el.2.1, i32 2
@@ -132,6 +130,6 @@ entry:
ret <16 x i64> %res
}
-declare void @capture(i64*, i64*)
+declare void @capture(ptr, ptr)
attributes #0 = { noredzone "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/CodeGen/ARM/vminmax.ll b/llvm/test/CodeGen/ARM/vminmax.ll
index 974fc4710940b..dc4a6ac2a79b0 100644
--- a/llvm/test/CodeGen/ARM/vminmax.ll
+++ b/llvm/test/CodeGen/ARM/vminmax.ll
@@ -1,127 +1,127 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vmins8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmins8:
;CHECK: vmin.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vmins16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmins16:
;CHECK: vmin.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vmins32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmins32:
;CHECK: vmin.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vminu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vminu8:
;CHECK: vmin.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vminu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vminu16:
;CHECK: vmin.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vminu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vminu32:
;CHECK: vmin.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x float> @vminf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vminf32:
;CHECK: vmin.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = call <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
ret <2 x float> %tmp3
}
-define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vminQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vminQs8:
;CHECK: vmin.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vminQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vminQs16:
;CHECK: vmin.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vminQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vminQs32:
;CHECK: vmin.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vminQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vminQu8:
;CHECK: vmin.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vminQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vminQu16:
;CHECK: vmin.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vminQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vminQu32:
;CHECK: vmin.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <4 x float> @vminQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x float> @vminQf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vminQf32:
;CHECK: vmin.f32
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
ret <4 x float> %tmp3
}
@@ -146,128 +146,128 @@ declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>) nounwind read
declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
-define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vmaxs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmaxs8:
;CHECK: vmax.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vmaxs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmaxs16:
;CHECK: vmax.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vmaxs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmaxs32:
;CHECK: vmax.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vmaxu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmaxu8:
;CHECK: vmax.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vmaxu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmaxu16:
;CHECK: vmax.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vmaxu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmaxu32:
;CHECK: vmax.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x float> @vmaxf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmaxf32:
;CHECK: vmax.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = call <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
ret <2 x float> %tmp3
}
-define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vmaxQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmaxQs8:
;CHECK: vmax.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vmaxQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmaxQs16:
;CHECK: vmax.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vmaxQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmaxQs32:
;CHECK: vmax.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vmaxQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmaxQu8:
;CHECK: vmax.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vmaxQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmaxQu16:
;CHECK: vmax.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vmaxQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmaxQu32:
;CHECK: vmax.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <4 x float> @vmaxQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x float> @vmaxQf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vmaxQf32:
;CHECK: vmax.f32
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
ret <4 x float> %tmp3
}
diff --git a/llvm/test/CodeGen/ARM/vminmaxnm-safe.ll b/llvm/test/CodeGen/ARM/vminmaxnm-safe.ll
index 3d88957437def..feb23ea1f3982 100644
--- a/llvm/test/CodeGen/ARM/vminmaxnm-safe.ll
+++ b/llvm/test/CodeGen/ARM/vminmaxnm-safe.ll
@@ -2,38 +2,38 @@
; vectors
-define <4 x float> @vmaxnmq(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x float> @vmaxnmq(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vmaxnmq:
; CHECK: vmaxnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
ret <4 x float> %tmp3
}
-define <2 x float> @vmaxnmd(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x float> @vmaxnmd(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vmaxnmd:
; CHECK: vmaxnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
ret <2 x float> %tmp3
}
-define <4 x float> @vminnmq(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x float> @vminnmq(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vminnmq:
; CHECK: vminnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
ret <4 x float> %tmp3
}
-define <2 x float> @vminnmd(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x float> @vminnmd(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vminnmd:
; CHECK: vminnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
ret <2 x float> %tmp3
}
diff --git a/llvm/test/CodeGen/ARM/vmov.ll b/llvm/test/CodeGen/ARM/vmov.ll
index 9310bbc82faa2..8835497669b32 100644
--- a/llvm/test/CodeGen/ARM/vmov.ll
+++ b/llvm/test/CodeGen/ARM/vmov.ll
@@ -228,31 +228,31 @@ define arm_aapcs_vfpcc <2 x i64> @v_movQi64() nounwind {
; Check for correct assembler printing for immediate values.
%struct.int8x8_t = type { <8 x i8> }
-define arm_aapcs_vfpcc void @vdupn128(%struct.int8x8_t* noalias nocapture sret(%struct.int8x8_t) %agg.result) nounwind {
+define arm_aapcs_vfpcc void @vdupn128(ptr noalias nocapture sret(%struct.int8x8_t) %agg.result) nounwind {
; CHECK-LABEL: vdupn128:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i8 d16, #0x80
; CHECK-NEXT: vstr d16, [r0]
; CHECK-NEXT: mov pc, lr
entry:
- %0 = getelementptr inbounds %struct.int8x8_t, %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
- store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, <8 x i8>* %0, align 8
+ %0 = getelementptr inbounds %struct.int8x8_t, ptr %agg.result, i32 0, i32 0 ; <ptr> [#uses=1]
+ store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, ptr %0, align 8
ret void
}
-define arm_aapcs_vfpcc void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret(%struct.int8x8_t) %agg.result) nounwind {
+define arm_aapcs_vfpcc void @vdupnneg75(ptr noalias nocapture sret(%struct.int8x8_t) %agg.result) nounwind {
; CHECK-LABEL: vdupnneg75:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i8 d16, #0xb5
; CHECK-NEXT: vstr d16, [r0]
; CHECK-NEXT: mov pc, lr
entry:
- %0 = getelementptr inbounds %struct.int8x8_t, %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
- store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, <8 x i8>* %0, align 8
+ %0 = getelementptr inbounds %struct.int8x8_t, ptr %agg.result, i32 0, i32 0 ; <ptr> [#uses=1]
+ store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, ptr %0, align 8
ret void
}
-define arm_aapcs_vfpcc <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
+define arm_aapcs_vfpcc <8 x i16> @vmovls8(ptr %A) nounwind {
; CHECK-LE-LABEL: vmovls8:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.8 {d16}, [r0:64]
@@ -265,12 +265,12 @@ define arm_aapcs_vfpcc <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
; CHECK-BE-NEXT: vmovl.s8 q8, d16
; CHECK-BE-NEXT: vrev64.16 q0, q8
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
ret <8 x i16> %tmp2
}
-define arm_aapcs_vfpcc <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
+define arm_aapcs_vfpcc <4 x i32> @vmovls16(ptr %A) nounwind {
; CHECK-LE-LABEL: vmovls16:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.16 {d16}, [r0:64]
@@ -283,23 +283,23 @@ define arm_aapcs_vfpcc <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
; CHECK-BE-NEXT: vmovl.s16 q8, d16
; CHECK-BE-NEXT: vrev64.32 q0, q8
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
ret <4 x i32> %tmp2
}
-define arm_aapcs_vfpcc <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
+define arm_aapcs_vfpcc <2 x i64> @vmovls32(ptr %A) nounwind {
; CHECK-LABEL: vmovls32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.32 {d16}, [r0:64]
; CHECK-NEXT: vmovl.s32 q0, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
ret <2 x i64> %tmp2
}
-define arm_aapcs_vfpcc <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
+define arm_aapcs_vfpcc <8 x i16> @vmovlu8(ptr %A) nounwind {
; CHECK-LE-LABEL: vmovlu8:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.8 {d16}, [r0:64]
@@ -312,12 +312,12 @@ define arm_aapcs_vfpcc <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
; CHECK-BE-NEXT: vmovl.u8 q8, d16
; CHECK-BE-NEXT: vrev64.16 q0, q8
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
ret <8 x i16> %tmp2
}
-define arm_aapcs_vfpcc <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
+define arm_aapcs_vfpcc <4 x i32> @vmovlu16(ptr %A) nounwind {
; CHECK-LE-LABEL: vmovlu16:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.16 {d16}, [r0:64]
@@ -330,23 +330,23 @@ define arm_aapcs_vfpcc <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
; CHECK-BE-NEXT: vmovl.u16 q8, d16
; CHECK-BE-NEXT: vrev64.32 q0, q8
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
ret <4 x i32> %tmp2
}
-define arm_aapcs_vfpcc <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
+define arm_aapcs_vfpcc <2 x i64> @vmovlu32(ptr %A) nounwind {
; CHECK-LABEL: vmovlu32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.32 {d16}, [r0:64]
; CHECK-NEXT: vmovl.u32 q0, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
ret <2 x i64> %tmp2
}
-define arm_aapcs_vfpcc <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
+define arm_aapcs_vfpcc <8 x i8> @vmovni16(ptr %A) nounwind {
; CHECK-LE-LABEL: vmovni16:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]
@@ -360,12 +360,12 @@ define arm_aapcs_vfpcc <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
; CHECK-BE-NEXT: vmovn.i16 d16, q8
; CHECK-BE-NEXT: vrev64.8 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = trunc <8 x i16> %tmp1 to <8 x i8>
ret <8 x i8> %tmp2
}
-define arm_aapcs_vfpcc <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
+define arm_aapcs_vfpcc <4 x i16> @vmovni32(ptr %A) nounwind {
; CHECK-LE-LABEL: vmovni32:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]
@@ -379,12 +379,12 @@ define arm_aapcs_vfpcc <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
; CHECK-BE-NEXT: vmovn.i32 d16, q8
; CHECK-BE-NEXT: vrev64.16 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
ret <4 x i16> %tmp2
}
-define arm_aapcs_vfpcc <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
+define arm_aapcs_vfpcc <2 x i32> @vmovni64(ptr %A) nounwind {
; CHECK-LE-LABEL: vmovni64:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]
@@ -397,12 +397,12 @@ define arm_aapcs_vfpcc <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
; CHECK-BE-NEXT: vmovn.i64 d16, q8
; CHECK-BE-NEXT: vrev64.32 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>
ret <2 x i32> %tmp2
}
-define arm_aapcs_vfpcc <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
+define arm_aapcs_vfpcc <8 x i8> @vqmovns16(ptr %A) nounwind {
; CHECK-LE-LABEL: vqmovns16:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]
@@ -416,12 +416,12 @@ define arm_aapcs_vfpcc <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
; CHECK-BE-NEXT: vqmovn.s16 d16, q8
; CHECK-BE-NEXT: vrev64.8 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
ret <8 x i8> %tmp2
}
-define arm_aapcs_vfpcc <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
+define arm_aapcs_vfpcc <4 x i16> @vqmovns32(ptr %A) nounwind {
; CHECK-LE-LABEL: vqmovns32:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]
@@ -435,12 +435,12 @@ define arm_aapcs_vfpcc <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
; CHECK-BE-NEXT: vqmovn.s32 d16, q8
; CHECK-BE-NEXT: vrev64.16 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
ret <4 x i16> %tmp2
}
-define arm_aapcs_vfpcc <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
+define arm_aapcs_vfpcc <2 x i32> @vqmovns64(ptr %A) nounwind {
; CHECK-LE-LABEL: vqmovns64:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]
@@ -453,12 +453,12 @@ define arm_aapcs_vfpcc <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
; CHECK-BE-NEXT: vqmovn.s64 d16, q8
; CHECK-BE-NEXT: vrev64.32 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
ret <2 x i32> %tmp2
}
-define arm_aapcs_vfpcc <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
+define arm_aapcs_vfpcc <8 x i8> @vqmovnu16(ptr %A) nounwind {
; CHECK-LE-LABEL: vqmovnu16:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]
@@ -472,12 +472,12 @@ define arm_aapcs_vfpcc <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
; CHECK-BE-NEXT: vqmovn.u16 d16, q8
; CHECK-BE-NEXT: vrev64.8 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
ret <8 x i8> %tmp2
}
-define arm_aapcs_vfpcc <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
+define arm_aapcs_vfpcc <4 x i16> @vqmovnu32(ptr %A) nounwind {
; CHECK-LE-LABEL: vqmovnu32:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]
@@ -491,12 +491,12 @@ define arm_aapcs_vfpcc <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
; CHECK-BE-NEXT: vqmovn.u32 d16, q8
; CHECK-BE-NEXT: vrev64.16 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
ret <4 x i16> %tmp2
}
-define arm_aapcs_vfpcc <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
+define arm_aapcs_vfpcc <2 x i32> @vqmovnu64(ptr %A) nounwind {
; CHECK-LE-LABEL: vqmovnu64:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]
@@ -509,12 +509,12 @@ define arm_aapcs_vfpcc <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
; CHECK-BE-NEXT: vqmovn.u64 d16, q8
; CHECK-BE-NEXT: vrev64.32 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
ret <2 x i32> %tmp2
}
-define arm_aapcs_vfpcc <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
+define arm_aapcs_vfpcc <8 x i8> @vqmovuns16(ptr %A) nounwind {
; CHECK-LE-LABEL: vqmovuns16:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]
@@ -528,12 +528,12 @@ define arm_aapcs_vfpcc <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
; CHECK-BE-NEXT: vqmovun.s16 d16, q8
; CHECK-BE-NEXT: vrev64.8 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
ret <8 x i8> %tmp2
}
-define arm_aapcs_vfpcc <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
+define arm_aapcs_vfpcc <4 x i16> @vqmovuns32(ptr %A) nounwind {
; CHECK-LE-LABEL: vqmovuns32:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]
@@ -547,12 +547,12 @@ define arm_aapcs_vfpcc <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
; CHECK-BE-NEXT: vqmovun.s32 d16, q8
; CHECK-BE-NEXT: vrev64.16 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
ret <4 x i16> %tmp2
}
-define arm_aapcs_vfpcc <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
+define arm_aapcs_vfpcc <2 x i32> @vqmovuns64(ptr %A) nounwind {
; CHECK-LE-LABEL: vqmovuns64:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]
@@ -565,7 +565,7 @@ define arm_aapcs_vfpcc <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
; CHECK-BE-NEXT: vqmovun.s64 d16, q8
; CHECK-BE-NEXT: vrev64.32 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
ret <2 x i32> %tmp2
}
@@ -584,7 +584,7 @@ declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone
; Truncating vector stores are not supported. The following should not crash.
; Radar 8598391.
-define arm_aapcs_vfpcc void @noTruncStore(<4 x i32>* %a, <4 x i16>* %b) nounwind {
+define arm_aapcs_vfpcc void @noTruncStore(ptr %a, ptr %b) nounwind {
; CHECK-LE-LABEL: noTruncStore:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0:128]
@@ -600,26 +600,26 @@ define arm_aapcs_vfpcc void @noTruncStore(<4 x i32>* %a, <4 x i16>* %b) nounwind
; CHECK-BE-NEXT: vrev64.16 d16, d16
; CHECK-BE-NEXT: vstr d16, [r1]
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %a, align 16
+ %tmp1 = load <4 x i32>, ptr %a, align 16
%tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
- store <4 x i16> %tmp2, <4 x i16>* %b, align 8
+ store <4 x i16> %tmp2, ptr %b, align 8
ret void
}
; Use vmov.f32 to materialize f32 immediate splats
; rdar://10437054
-define arm_aapcs_vfpcc void @v_mov_v2f32(<2 x float>* nocapture %p) nounwind {
+define arm_aapcs_vfpcc void @v_mov_v2f32(ptr nocapture %p) nounwind {
; CHECK-LABEL: v_mov_v2f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 d16, #-1.600000e+01
; CHECK-NEXT: vstr d16, [r0]
; CHECK-NEXT: mov pc, lr
entry:
- store <2 x float> <float -1.600000e+01, float -1.600000e+01>, <2 x float>* %p, align 4
+ store <2 x float> <float -1.600000e+01, float -1.600000e+01>, ptr %p, align 4
ret void
}
-define arm_aapcs_vfpcc void @v_mov_v4f32(<4 x float>* nocapture %p) nounwind {
+define arm_aapcs_vfpcc void @v_mov_v4f32(ptr nocapture %p) nounwind {
; CHECK-LE-LABEL: v_mov_v4f32:
; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vmov.f32 q8, #3.100000e+01
@@ -632,11 +632,11 @@ define arm_aapcs_vfpcc void @v_mov_v4f32(<4 x float>* nocapture %p) nounwind {
; CHECK-BE-NEXT: vstmia r0, {d16, d17}
; CHECK-BE-NEXT: mov pc, lr
entry:
- store <4 x float> <float 3.100000e+01, float 3.100000e+01, float 3.100000e+01, float 3.100000e+01>, <4 x float>* %p, align 4
+ store <4 x float> <float 3.100000e+01, float 3.100000e+01, float 3.100000e+01, float 3.100000e+01>, ptr %p, align 4
ret void
}
-define arm_aapcs_vfpcc void @v_mov_v4f32_undef(<4 x float> * nocapture %p) nounwind {
+define arm_aapcs_vfpcc void @v_mov_v4f32_undef(ptr nocapture %p) nounwind {
; CHECK-LE-LABEL: v_mov_v4f32_undef:
; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vmov.f32 q8, #1.000000e+00
@@ -655,9 +655,9 @@ define arm_aapcs_vfpcc void @v_mov_v4f32_undef(<4 x float> * nocapture %p) nounw
; CHECK-BE-NEXT: vst1.64 {d16, d17}, [r0]
; CHECK-BE-NEXT: mov pc, lr
entry:
- %a = load <4 x float> , <4 x float> *%p
+ %a = load <4 x float> , ptr %p
%b = fadd <4 x float> %a, <float undef, float 1.0, float 1.0, float 1.0>
- store <4 x float> %b, <4 x float> *%p
+ store <4 x float> %b, ptr %p
ret void
}
@@ -689,172 +689,172 @@ entry:
%sub.i = sub <4 x i32> %add.i185, zeroinitializer
%add.i = add <4 x i32> %sub.i, zeroinitializer
%vmovn.i = trunc <4 x i32> %add.i to <4 x i16>
- tail call void @llvm.arm.neon.vst1.p0i8.v4i16(i8* undef, <4 x i16> %vmovn.i, i32 2)
+ tail call void @llvm.arm.neon.vst1.p0.v4i16(ptr undef, <4 x i16> %vmovn.i, i32 2)
unreachable
}
-define arm_aapcs_vfpcc void @v_movi8_sti8(i8* %p) {
+define arm_aapcs_vfpcc void @v_movi8_sti8(ptr %p) {
; CHECK-LABEL: v_movi8_sti8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 d16, #0x1
; CHECK-NEXT: vst1.8 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
- call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* %p, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, i32 1)
+ call void @llvm.arm.neon.vst1.p0.v8i8(ptr %p, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, i32 1)
ret void
}
-define arm_aapcs_vfpcc void @v_movi8_sti16(i8* %p) {
+define arm_aapcs_vfpcc void @v_movi8_sti16(ptr %p) {
; CHECK-LABEL: v_movi8_sti16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 d16, #0x1
; CHECK-NEXT: vst1.16 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <4 x i16>
- call void @llvm.arm.neon.vst1.p0i8.v4i16(i8* %p, <4 x i16> %val, i32 2)
+ call void @llvm.arm.neon.vst1.p0.v4i16(ptr %p, <4 x i16> %val, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @v_movi8_stf16(i8* %p) {
+define arm_aapcs_vfpcc void @v_movi8_stf16(ptr %p) {
; CHECK-LABEL: v_movi8_stf16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 d16, #0x1
; CHECK-NEXT: vst1.16 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <4 x half>
- call void @llvm.arm.neon.vst1.p0i8.v4f16(i8* %p, <4 x half> %val, i32 2)
+ call void @llvm.arm.neon.vst1.p0.v4f16(ptr %p, <4 x half> %val, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @v_movi8_sti32(i8* %p) {
+define arm_aapcs_vfpcc void @v_movi8_sti32(ptr %p) {
; CHECK-LABEL: v_movi8_sti32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 d16, #0x1
; CHECK-NEXT: vst1.32 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <2 x i32>
- call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %p, <2 x i32> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v2i32(ptr %p, <2 x i32> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_movi8_stf32(i8* %p) {
+define arm_aapcs_vfpcc void @v_movi8_stf32(ptr %p) {
; CHECK-LABEL: v_movi8_stf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 d16, #0x1
; CHECK-NEXT: vst1.32 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <2 x float>
- call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %p, <2 x float> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v2f32(ptr %p, <2 x float> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_movi8_sti64(i8* %p) {
+define arm_aapcs_vfpcc void @v_movi8_sti64(ptr %p) {
; CHECK-LABEL: v_movi8_sti64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 d16, #0x1
; CHECK-NEXT: vst1.64 {d16}, [r0:64]
; CHECK-NEXT: mov pc, lr
%val = bitcast <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <1 x i64>
- call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %p, <1 x i64> %val, i32 8)
+ call void @llvm.arm.neon.vst1.p0.v1i64(ptr %p, <1 x i64> %val, i32 8)
ret void
}
-define arm_aapcs_vfpcc void @v_movi16_sti16(i8* %p) {
+define arm_aapcs_vfpcc void @v_movi16_sti16(ptr %p) {
; CHECK-LABEL: v_movi16_sti16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 d16, #0x1
; CHECK-NEXT: vst1.16 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
- call void @llvm.arm.neon.vst1.p0i8.v4i16(i8* %p, <4 x i16> <i16 1, i16 1, i16 1, i16 1>, i32 2)
+ call void @llvm.arm.neon.vst1.p0.v4i16(ptr %p, <4 x i16> <i16 1, i16 1, i16 1, i16 1>, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @v_movi16_stf16(i8* %p) {
+define arm_aapcs_vfpcc void @v_movi16_stf16(ptr %p) {
; CHECK-LABEL: v_movi16_stf16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 d16, #0x1
; CHECK-NEXT: vst1.16 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <4 x i16> <i16 1, i16 1, i16 1, i16 1> to <4 x half>
- call void @llvm.arm.neon.vst1.p0i8.v4f16(i8* %p, <4 x half> %val, i32 2)
+ call void @llvm.arm.neon.vst1.p0.v4f16(ptr %p, <4 x half> %val, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @v_movi16_sti32(i8* %p) {
+define arm_aapcs_vfpcc void @v_movi16_sti32(ptr %p) {
; CHECK-LABEL: v_movi16_sti32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 d16, #0x1
; CHECK-NEXT: vst1.32 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <4 x i16> <i16 1, i16 1, i16 1, i16 1> to <2 x i32>
- call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %p, <2 x i32> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v2i32(ptr %p, <2 x i32> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_movi16_stf32(i8* %p) {
+define arm_aapcs_vfpcc void @v_movi16_stf32(ptr %p) {
; CHECK-LABEL: v_movi16_stf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 d16, #0x1
; CHECK-NEXT: vst1.32 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <4 x i16> <i16 1, i16 1, i16 1, i16 1> to <2 x float>
- call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %p, <2 x float> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v2f32(ptr %p, <2 x float> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_movi16_sti64(i8* %p) {
+define arm_aapcs_vfpcc void @v_movi16_sti64(ptr %p) {
; CHECK-LABEL: v_movi16_sti64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 d16, #0x1
; CHECK-NEXT: vst1.64 {d16}, [r0:64]
; CHECK-NEXT: mov pc, lr
%val = bitcast <4 x i16> <i16 1, i16 1, i16 1, i16 1> to <1 x i64>
- call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %p, <1 x i64> %val, i32 8)
+ call void @llvm.arm.neon.vst1.p0.v1i64(ptr %p, <1 x i64> %val, i32 8)
ret void
}
-define arm_aapcs_vfpcc void @v_movi32_sti32(i8* %p) {
+define arm_aapcs_vfpcc void @v_movi32_sti32(ptr %p) {
; CHECK-LABEL: v_movi32_sti32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d16, #0x1
; CHECK-NEXT: vst1.32 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
- call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %p, <2 x i32> <i32 1, i32 1>, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v2i32(ptr %p, <2 x i32> <i32 1, i32 1>, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_movi32_stf32(i8* %p) {
+define arm_aapcs_vfpcc void @v_movi32_stf32(ptr %p) {
; CHECK-LABEL: v_movi32_stf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d16, #0x1
; CHECK-NEXT: vst1.32 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <2 x i32> <i32 1, i32 1> to <2 x float>
- call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %p, <2 x float> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v2f32(ptr %p, <2 x float> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_movi32_sti64(i8* %p) {
+define arm_aapcs_vfpcc void @v_movi32_sti64(ptr %p) {
; CHECK-LABEL: v_movi32_sti64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d16, #0x1
; CHECK-NEXT: vst1.64 {d16}, [r0:64]
; CHECK-NEXT: mov pc, lr
%val = bitcast <2 x i32> <i32 1, i32 1> to <1 x i64>
- call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %p, <1 x i64> %val, i32 8)
+ call void @llvm.arm.neon.vst1.p0.v1i64(ptr %p, <1 x i64> %val, i32 8)
ret void
}
-define arm_aapcs_vfpcc void @v_movf32_stf32(i8* %p) {
+define arm_aapcs_vfpcc void @v_movf32_stf32(ptr %p) {
; CHECK-LABEL: v_movf32_stf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.f32 d16, #1.000000e+00
; CHECK-NEXT: vst1.32 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
- call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %p, <2 x float> <float 1.0, float 1.0>, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v2f32(ptr %p, <2 x float> <float 1.0, float 1.0>, i32 4)
ret void
}
-define arm_aapcs_vfpcc void at v_movf32_sti32(i8* %p) {
+define arm_aapcs_vfpcc void at v_movf32_sti32(ptr %p) {
; FIXME: We should use vmov.f32 instead of mov then vdup
; CHECK-LABEL: v_movf32_sti32:
; CHECK: @ %bb.0:
@@ -863,11 +863,11 @@ define arm_aapcs_vfpcc void at v_movf32_sti32(i8* %p) {
; CHECK-NEXT: vst1.32 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <2 x float> <float 1.0, float 1.0> to <2 x i32>
- call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %p, <2 x i32> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v2i32(ptr %p, <2 x i32> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_movf32_sti64(i8* %p) {
+define arm_aapcs_vfpcc void @v_movf32_sti64(ptr %p) {
; CHECK-LE-LABEL: v_movf32_sti64:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: mov r1, #1065353216
@@ -884,182 +884,182 @@ define arm_aapcs_vfpcc void @v_movf32_sti64(i8* %p) {
; CHECK-BE-NEXT: vst1.64 {d16}, [r0:64]
; CHECK-BE-NEXT: mov pc, lr
%val = bitcast <2 x float> <float 1.0, float 1.0> to <1 x i64>
- call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %p, <1 x i64> %val, i32 8)
+ call void @llvm.arm.neon.vst1.p0.v1i64(ptr %p, <1 x i64> %val, i32 8)
ret void
}
-define arm_aapcs_vfpcc void @v_movi64_sti64(i8* %p) {
+define arm_aapcs_vfpcc void @v_movi64_sti64(ptr %p) {
; CHECK-LABEL: v_movi64_sti64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i64 d16, #0xff
; CHECK-NEXT: vst1.64 {d16}, [r0:64]
; CHECK-NEXT: mov pc, lr
- call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %p, <1 x i64> <i64 255>, i32 8)
+ call void @llvm.arm.neon.vst1.p0.v1i64(ptr %p, <1 x i64> <i64 255>, i32 8)
ret void
}
-define arm_aapcs_vfpcc void @v_movQi8_sti8(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQi8_sti8(ptr %p) {
; CHECK-LABEL: v_movQi8_sti8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 q8, #0x1
; CHECK-NEXT: vst1.8 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
- call void @llvm.arm.neon.vst1.p0i8.v16i8(i8* %p, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, i32 1)
+ call void @llvm.arm.neon.vst1.p0.v16i8(ptr %p, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, i32 1)
ret void
}
-define arm_aapcs_vfpcc void @v_movQi8_sti16(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQi8_sti16(ptr %p) {
; CHECK-LABEL: v_movQi8_sti16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 q8, #0x1
; CHECK-NEXT: vst1.16 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <8 x i16>
- call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %p, <8 x i16> %val, i32 2)
+ call void @llvm.arm.neon.vst1.p0.v8i16(ptr %p, <8 x i16> %val, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @v_movQi8_stf16(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQi8_stf16(ptr %p) {
; CHECK-LABEL: v_movQi8_stf16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 q8, #0x1
; CHECK-NEXT: vst1.16 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <8 x half>
- call void @llvm.arm.neon.vst1.p0i8.v8f16(i8* %p, <8 x half> %val, i32 2)
+ call void @llvm.arm.neon.vst1.p0.v8f16(ptr %p, <8 x half> %val, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @v_movQi8_sti32(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQi8_sti32(ptr %p) {
; CHECK-LABEL: v_movQi8_sti32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 q8, #0x1
; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <4 x i32>
- call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %p, <4 x i32> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v4i32(ptr %p, <4 x i32> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_movQi8_stf32(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQi8_stf32(ptr %p) {
; CHECK-LABEL: v_movQi8_stf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 q8, #0x1
; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <4 x float>
- call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %p, <4 x float> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v4f32(ptr %p, <4 x float> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_movQi8_sti64(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQi8_sti64(ptr %p) {
; CHECK-LABEL: v_movQi8_sti64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 q8, #0x1
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64]
; CHECK-NEXT: mov pc, lr
%val = bitcast <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <2 x i64>
- call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %p, <2 x i64> %val, i32 8)
+ call void @llvm.arm.neon.vst1.p0.v2i64(ptr %p, <2 x i64> %val, i32 8)
ret void
}
-define arm_aapcs_vfpcc void @v_movQi16_sti16(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQi16_sti16(ptr %p) {
; CHECK-LABEL: v_movQi16_sti16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 q8, #0x1
; CHECK-NEXT: vst1.16 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
- call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %p, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, i32 2)
+ call void @llvm.arm.neon.vst1.p0.v8i16(ptr %p, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @v_movQi16_stf16(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQi16_stf16(ptr %p) {
; CHECK-LABEL: v_movQi16_stf16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 q8, #0x1
; CHECK-NEXT: vst1.16 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> to <8 x half>
- call void @llvm.arm.neon.vst1.p0i8.v8f16(i8* %p, <8 x half> %val, i32 2)
+ call void @llvm.arm.neon.vst1.p0.v8f16(ptr %p, <8 x half> %val, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @v_movQi16_sti32(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQi16_sti32(ptr %p) {
; CHECK-LABEL: v_movQi16_sti32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 q8, #0x1
; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> to <4 x i32>
- call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %p, <4 x i32> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v4i32(ptr %p, <4 x i32> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_movQi16_stf32(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQi16_stf32(ptr %p) {
; CHECK-LABEL: v_movQi16_stf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 q8, #0x1
; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> to <4 x float>
- call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %p, <4 x float> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v4f32(ptr %p, <4 x float> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_movQi16_sti64(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQi16_sti64(ptr %p) {
; CHECK-LABEL: v_movQi16_sti64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 q8, #0x1
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64]
; CHECK-NEXT: mov pc, lr
%val = bitcast <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> to <2 x i64>
- call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %p, <2 x i64> %val, i32 8)
+ call void @llvm.arm.neon.vst1.p0.v2i64(ptr %p, <2 x i64> %val, i32 8)
ret void
}
-define arm_aapcs_vfpcc void @v_movQi32_sti32(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQi32_sti32(ptr %p) {
; CHECK-LABEL: v_movQi32_sti32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q8, #0x1
; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
- call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %p, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v4i32(ptr %p, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_movQi32_stf32(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQi32_stf32(ptr %p) {
; CHECK-LABEL: v_movQi32_stf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q8, #0x1
; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <4 x i32> <i32 1, i32 1, i32 1, i32 1> to <4 x float>
- call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %p, <4 x float> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v4f32(ptr %p, <4 x float> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_movQi32_sti64(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQi32_sti64(ptr %p) {
; CHECK-LABEL: v_movQi32_sti64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q8, #0x1
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64]
; CHECK-NEXT: mov pc, lr
%val = bitcast <4 x i32> <i32 1, i32 1, i32 1, i32 1> to <2 x i64>
- call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %p, <2 x i64> %val, i32 8)
+ call void @llvm.arm.neon.vst1.p0.v2i64(ptr %p, <2 x i64> %val, i32 8)
ret void
}
-define arm_aapcs_vfpcc void @v_movQf32_stf32(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQf32_stf32(ptr %p) {
; CHECK-LABEL: v_movQf32_stf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.f32 q8, #1.000000e+00
; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
- call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %p, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v4f32(ptr %p, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_movQf32_sti32(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQf32_sti32(ptr %p) {
; FIXME: We should use vmov.f32 instead of mov then vdup
; CHECK-LABEL: v_movQf32_sti32:
; CHECK: @ %bb.0:
@@ -1068,11 +1068,11 @@ define arm_aapcs_vfpcc void @v_movQf32_sti32(i8* %p) {
; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0> to <4 x i32>
- call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %p, <4 x i32> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v4i32(ptr %p, <4 x i32> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_movQf32_sti64(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQf32_sti64(ptr %p) {
; CHECK-LE-LABEL: v_movQf32_sti64:
; CHECK-LE: @ %bb.0:
; CHECK-LE-NEXT: mov r1, #1065353216
@@ -1089,203 +1089,203 @@ define arm_aapcs_vfpcc void @v_movQf32_sti64(i8* %p) {
; CHECK-BE-NEXT: vst1.64 {d16, d17}, [r0:64]
; CHECK-BE-NEXT: mov pc, lr
%val = bitcast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0> to <2 x i64>
- call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %p, <2 x i64> %val, i32 8)
+ call void @llvm.arm.neon.vst1.p0.v2i64(ptr %p, <2 x i64> %val, i32 8)
ret void
}
-define arm_aapcs_vfpcc void @v_movQi64_sti64(i8* %p) {
+define arm_aapcs_vfpcc void @v_movQi64_sti64(ptr %p) {
; CHECK-LABEL: v_movQi64_sti64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i64 q8, #0xff
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64]
; CHECK-NEXT: mov pc, lr
- call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %p, <2 x i64> <i64 255, i64 255>, i32 8)
+ call void @llvm.arm.neon.vst1.p0.v2i64(ptr %p, <2 x i64> <i64 255, i64 255>, i32 8)
ret void
}
-define arm_aapcs_vfpcc void @v_mvni16_sti16(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvni16_sti16(ptr %p) {
; CHECK-LABEL: v_mvni16_sti16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i16 d16, #0xfe
; CHECK-NEXT: vst1.16 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
- call void @llvm.arm.neon.vst1.p0i8.v4i16(i8* %p, <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281>, i32 2)
+ call void @llvm.arm.neon.vst1.p0.v4i16(ptr %p, <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281>, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @v_mvni16_stf16(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvni16_stf16(ptr %p) {
; CHECK-LABEL: v_mvni16_stf16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i16 d16, #0xfe
; CHECK-NEXT: vst1.16 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281> to <4 x half>
- call void @llvm.arm.neon.vst1.p0i8.v4f16(i8* %p, <4 x half> %val, i32 2)
+ call void @llvm.arm.neon.vst1.p0.v4f16(ptr %p, <4 x half> %val, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @v_mvni16_sti32(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvni16_sti32(ptr %p) {
; CHECK-LABEL: v_mvni16_sti32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i16 d16, #0xfe
; CHECK-NEXT: vst1.32 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281> to <2 x i32>
- call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %p, <2 x i32> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v2i32(ptr %p, <2 x i32> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_mvni16_stf32(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvni16_stf32(ptr %p) {
; CHECK-LABEL: v_mvni16_stf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i16 d16, #0xfe
; CHECK-NEXT: vst1.32 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281> to <2 x float>
- call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %p, <2 x float> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v2f32(ptr %p, <2 x float> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_mvni16_sti64(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvni16_sti64(ptr %p) {
; CHECK-LABEL: v_mvni16_sti64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i16 d16, #0xfe
; CHECK-NEXT: vst1.64 {d16}, [r0:64]
; CHECK-NEXT: mov pc, lr
%val = bitcast <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281> to <1 x i64>
- call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %p, <1 x i64> %val, i32 8)
+ call void @llvm.arm.neon.vst1.p0.v1i64(ptr %p, <1 x i64> %val, i32 8)
ret void
}
-define arm_aapcs_vfpcc void @v_mvni32_sti32(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvni32_sti32(ptr %p) {
; CHECK-LABEL: v_mvni32_sti32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 d16, #0xfe
; CHECK-NEXT: vst1.32 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
- call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %p, <2 x i32> <i32 4294967041, i32 4294967041>, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v2i32(ptr %p, <2 x i32> <i32 4294967041, i32 4294967041>, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_mvni32_stf32(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvni32_stf32(ptr %p) {
; CHECK-LABEL: v_mvni32_stf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 d16, #0xfe
; CHECK-NEXT: vst1.32 {d16}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <2 x i32> <i32 4294967041, i32 4294967041> to <2 x float>
- call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %p, <2 x float> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v2f32(ptr %p, <2 x float> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_mvni32_sti64(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvni32_sti64(ptr %p) {
; CHECK-LABEL: v_mvni32_sti64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 d16, #0xfe
; CHECK-NEXT: vst1.64 {d16}, [r0:64]
; CHECK-NEXT: mov pc, lr
%val = bitcast <2 x i32> <i32 4294967041, i32 4294967041> to <1 x i64>
- call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %p, <1 x i64> %val, i32 8)
+ call void @llvm.arm.neon.vst1.p0.v1i64(ptr %p, <1 x i64> %val, i32 8)
ret void
}
-define arm_aapcs_vfpcc void @v_mvnQi16_sti16(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvnQi16_sti16(ptr %p) {
; CHECK-LABEL: v_mvnQi16_sti16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i16 q8, #0xfe
; CHECK-NEXT: vst1.16 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
- call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %p, <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281>, i32 2)
+ call void @llvm.arm.neon.vst1.p0.v8i16(ptr %p, <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281>, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @v_mvnQi16_stf16(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvnQi16_stf16(ptr %p) {
; CHECK-LABEL: v_mvnQi16_stf16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i16 q8, #0xfe
; CHECK-NEXT: vst1.16 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281> to <8 x half>
- call void @llvm.arm.neon.vst1.p0i8.v8f16(i8* %p, <8 x half> %val, i32 2)
+ call void @llvm.arm.neon.vst1.p0.v8f16(ptr %p, <8 x half> %val, i32 2)
ret void
}
-define arm_aapcs_vfpcc void @v_mvnQi16_sti32(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvnQi16_sti32(ptr %p) {
; CHECK-LABEL: v_mvnQi16_sti32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i16 q8, #0xfe
; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281> to <4 x i32>
- call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %p, <4 x i32> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v4i32(ptr %p, <4 x i32> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_mvnQi16_stf32(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvnQi16_stf32(ptr %p) {
; CHECK-LABEL: v_mvnQi16_stf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i16 q8, #0xfe
; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281> to <4 x float>
- call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %p, <4 x float> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v4f32(ptr %p, <4 x float> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_mvnQi16_sti64(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvnQi16_sti64(ptr %p) {
; CHECK-LABEL: v_mvnQi16_sti64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i16 q8, #0xfe
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64]
; CHECK-NEXT: mov pc, lr
%val = bitcast <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281> to <2 x i64>
- call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %p, <2 x i64> %val, i32 8)
+ call void @llvm.arm.neon.vst1.p0.v2i64(ptr %p, <2 x i64> %val, i32 8)
ret void
}
-define arm_aapcs_vfpcc void @v_mvnQi32_sti32(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvnQi32_sti32(ptr %p) {
; CHECK-LABEL: v_mvnQi32_sti32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 q8, #0xfe
; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
- call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %p, <4 x i32> <i32 4294967041, i32 4294967041, i32 4294967041, i32 4294967041>, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v4i32(ptr %p, <4 x i32> <i32 4294967041, i32 4294967041, i32 4294967041, i32 4294967041>, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_mvnQi32_stf32(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvnQi32_stf32(ptr %p) {
; CHECK-LABEL: v_mvnQi32_stf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 q8, #0xfe
; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
%val = bitcast <4 x i32> <i32 4294967041, i32 4294967041, i32 4294967041, i32 4294967041> to <4 x float>
- call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %p, <4 x float> %val, i32 4)
+ call void @llvm.arm.neon.vst1.p0.v4f32(ptr %p, <4 x float> %val, i32 4)
ret void
}
-define arm_aapcs_vfpcc void @v_mvnQi32_sti64(i8* %p) {
+define arm_aapcs_vfpcc void @v_mvnQi32_sti64(ptr %p) {
; CHECK-LABEL: v_mvnQi32_sti64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 q8, #0xfe
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64]
; CHECK-NEXT: mov pc, lr
%val = bitcast <4 x i32> <i32 4294967041, i32 4294967041, i32 4294967041, i32 4294967041> to <2 x i64>
- call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %p, <2 x i64> %val, i32 8)
+ call void @llvm.arm.neon.vst1.p0.v2i64(ptr %p, <2 x i64> %val, i32 8)
ret void
}
-declare void @llvm.arm.neon.vst1.p0i8.v8i8(i8*, <8 x i8>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v4i16(i8*, <4 x i16>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v4f16(i8*, <4 x half>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v2i32(i8*, <2 x i32>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v2f32(i8*, <2 x float>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v1i64(i8*, <1 x i64>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v8i8(ptr, <8 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v4i16(ptr, <4 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v4f16(ptr, <4 x half>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v2i32(ptr, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v2f32(ptr, <2 x float>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v1i64(ptr, <1 x i64>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v16i8(i8*, <16 x i8>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v8i16(i8*, <8 x i16>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v8f16(i8*, <8 x half>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v4i32(i8*, <4 x i32>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v2i64(i8*, <2 x i64>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v16i8(ptr, <16 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v8i16(ptr, <8 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v8f16(ptr, <8 x half>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v4i32(ptr, <4 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v4f32(ptr, <4 x float>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v2i64(ptr, <2 x i64>, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/vmul.ll b/llvm/test/CodeGen/ARM/vmul.ll
index c1a63d7df52e5..9915e050de2a6 100644
--- a/llvm/test/CodeGen/ARM/vmul.ll
+++ b/llvm/test/CodeGen/ARM/vmul.ll
@@ -609,7 +609,7 @@ define <2 x i64> @vmull_extvec_u32(<2 x i32> %arg) nounwind {
}
; rdar://9197392
-define void @distribute(i16* %dst, i8* %src, i32 %mul) nounwind {
+define void @distribute(ptr %dst, ptr %src, i32 %mul) nounwind {
; CHECK-LABEL: distribute:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.8 {d16, d17}, [r1]
@@ -622,7 +622,7 @@ entry:
%0 = trunc i32 %mul to i8
%1 = insertelement <8 x i8> undef, i8 %0, i32 0
%2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
- %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %src, i32 1)
+ %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr %src, i32 1)
%4 = bitcast <16 x i8> %3 to <2 x double>
%5 = extractelement <2 x double> %4, i32 1
%6 = bitcast double %5 to <8 x i8>
@@ -633,20 +633,19 @@ entry:
%11 = zext <8 x i8> %10 to <8 x i16>
%12 = add <8 x i16> %7, %11
%13 = mul <8 x i16> %12, %8
- %14 = bitcast i16* %dst to i8*
- tail call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %14, <8 x i16> %13, i32 2)
+ tail call void @llvm.arm.neon.vst1.p0.v8i16(ptr %dst, <8 x i16> %13, i32 2)
ret void
}
-declare <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8*, i32) nounwind readonly
+declare <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr, i32) nounwind readonly
-declare void @llvm.arm.neon.vst1.p0i8.v8i16(i8*, <8 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v8i16(ptr, <8 x i16>, i32) nounwind
; Take advantage of the Cortex-A8 multiplier accumulator forward.
%struct.uint8x8_t = type { <8 x i8> }
-define void @distribute2(%struct.uint8x8_t* nocapture %dst, i8* %src, i32 %mul) nounwind {
+define void @distribute2(ptr nocapture %dst, ptr %src, i32 %mul) nounwind {
; CHECK-LABEL: distribute2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.8 {d16, d17}, [r1]
@@ -659,7 +658,7 @@ entry:
%0 = trunc i32 %mul to i8
%1 = insertelement <8 x i8> undef, i8 %0, i32 0
%2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
- %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %src, i32 1)
+ %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr %src, i32 1)
%4 = bitcast <16 x i8> %3 to <2 x double>
%5 = extractelement <2 x double> %4, i32 1
%6 = bitcast double %5 to <8 x i8>
@@ -667,12 +666,11 @@ entry:
%8 = bitcast double %7 to <8 x i8>
%9 = add <8 x i8> %6, %8
%10 = mul <8 x i8> %9, %2
- %11 = getelementptr inbounds %struct.uint8x8_t, %struct.uint8x8_t* %dst, i32 0, i32 0
- store <8 x i8> %10, <8 x i8>* %11, align 8
+ store <8 x i8> %10, ptr %dst, align 8
ret void
}
-define void @distribute2_commutative(%struct.uint8x8_t* nocapture %dst, i8* %src, i32 %mul) nounwind {
+define void @distribute2_commutative(ptr nocapture %dst, ptr %src, i32 %mul) nounwind {
; CHECK-LABEL: distribute2_commutative:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.8 {d16, d17}, [r1]
@@ -685,7 +683,7 @@ entry:
%0 = trunc i32 %mul to i8
%1 = insertelement <8 x i8> undef, i8 %0, i32 0
%2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
- %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %src, i32 1)
+ %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr %src, i32 1)
%4 = bitcast <16 x i8> %3 to <2 x double>
%5 = extractelement <2 x double> %4, i32 1
%6 = bitcast double %5 to <8 x i8>
@@ -693,8 +691,7 @@ entry:
%8 = bitcast double %7 to <8 x i8>
%9 = add <8 x i8> %6, %8
%10 = mul <8 x i8> %2, %9
- %11 = getelementptr inbounds %struct.uint8x8_t, %struct.uint8x8_t* %dst, i32 0, i32 0
- store <8 x i8> %10, <8 x i8>* %11, align 8
+ store <8 x i8> %10, ptr %dst, align 8
ret void
}
@@ -749,8 +746,8 @@ for.body33.lr.ph: ; preds = %for.body
for.body33: ; preds = %for.body33, %for.body33.lr.ph
%add45 = add i32 undef, undef
- %vld155 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* undef, i32 1)
- %0 = load i32*, i32** undef, align 4
+ %vld155 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr undef, i32 1)
+ %0 = load ptr, ptr undef, align 4
%shuffle.i250 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer
%1 = bitcast <1 x i64> %shuffle.i250 to <8 x i8>
%vmovl.i249 = zext <8 x i8> %1 to <8 x i16>
@@ -789,7 +786,7 @@ for.body33: ; preds = %for.body33, %for.bo
%4 = bitcast <8 x i8> %vqmovn1.i180 to <1 x i64>
%shuffle.i = shufflevector <1 x i64> %4, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
%5 = bitcast <2 x i64> %shuffle.i to <16 x i8>
- store <16 x i8> %5, <16 x i8>* undef, align 16
+ store <16 x i8> %5, ptr undef, align 16
%add177 = add nsw i32 undef, 16
br i1 undef, label %for.body33, label %for.cond.loopexit
@@ -808,28 +805,28 @@ define void @no_illegal_types_vmull_sext(<4 x i32> %a) {
; CHECK-LABEL: no_illegal_types_vmull_sext:
; CHECK: @ %bb.0: @ %entry
entry:
- %wide.load283.i = load <4 x i8>, <4 x i8>* undef, align 1
+ %wide.load283.i = load <4 x i8>, ptr undef, align 1
%0 = sext <4 x i8> %wide.load283.i to <4 x i32>
%1 = sub nsw <4 x i32> %0, %a
%2 = mul nsw <4 x i32> %1, %1
%predphi290.v.i = select <4 x i1> undef, <4 x i32> undef, <4 x i32> %2
- store <4 x i32> %predphi290.v.i, <4 x i32>* undef, align 4
+ store <4 x i32> %predphi290.v.i, ptr undef, align 4
ret void
}
define void @no_illegal_types_vmull_zext(<4 x i32> %a) {
; CHECK-LABEL: no_illegal_types_vmull_zext:
; CHECK: @ %bb.0: @ %entry
entry:
- %wide.load283.i = load <4 x i8>, <4 x i8>* undef, align 1
+ %wide.load283.i = load <4 x i8>, ptr undef, align 1
%0 = zext <4 x i8> %wide.load283.i to <4 x i32>
%1 = sub nsw <4 x i32> %0, %a
%2 = mul nsw <4 x i32> %1, %1
%predphi290.v.i = select <4 x i1> undef, <4 x i32> undef, <4 x i32> %2
- store <4 x i32> %predphi290.v.i, <4 x i32>* undef, align 4
+ store <4 x i32> %predphi290.v.i, ptr undef, align 4
ret void
}
-define void @fmul_splat(<4 x float>* %A, <4 x float>* nocapture %dst, float %tmp) nounwind {
+define void @fmul_splat(ptr %A, ptr nocapture %dst, float %tmp) nounwind {
; Look for a scalar float rather than a splat, then a vector*scalar multiply.
; CHECK-LABEL: fmul_splat:
; CHECK: @ %bb.0:
@@ -838,17 +835,17 @@ define void @fmul_splat(<4 x float>* %A, <4 x float>* nocapture %dst, float %tmp
; CHECK-NEXT: vmul.f32 q8, q8, d0[0]
; CHECK-NEXT: vst1.32 {d16, d17}, [r1]
; CHECK-NEXT: bx lr
- %tmp5 = load <4 x float>, <4 x float>* %A, align 4
+ %tmp5 = load <4 x float>, ptr %A, align 4
%tmp6 = insertelement <4 x float> undef, float %tmp, i32 0
%tmp7 = insertelement <4 x float> %tmp6, float %tmp, i32 1
%tmp8 = insertelement <4 x float> %tmp7, float %tmp, i32 2
%tmp9 = insertelement <4 x float> %tmp8, float %tmp, i32 3
%tmp10 = fmul <4 x float> %tmp9, %tmp5
- store <4 x float> %tmp10, <4 x float>* %dst, align 4
+ store <4 x float> %tmp10, ptr %dst, align 4
ret void
}
-define void @fmul_splat_load(<4 x float>* %A, <4 x float>* nocapture %dst, float* nocapture readonly %src) nounwind {
+define void @fmul_splat_load(ptr %A, ptr nocapture %dst, ptr nocapture readonly %src) nounwind {
; Look for doing a normal scalar FP load rather than an to-all-lanes load,
; then a vector*scalar multiply.
; FIXME: Temporarily broken due to splat representation changes.
@@ -859,13 +856,13 @@ define void @fmul_splat_load(<4 x float>* %A, <4 x float>* nocapture %dst, float
; CHECK-NEXT: vmul.f32 q8, q9, q8
; CHECK-NEXT: vst1.32 {d16, d17}, [r1]
; CHECK-NEXT: bx lr
- %tmp = load float, float* %src, align 4
- %tmp5 = load <4 x float>, <4 x float>* %A, align 4
+ %tmp = load float, ptr %src, align 4
+ %tmp5 = load <4 x float>, ptr %A, align 4
%tmp6 = insertelement <4 x float> undef, float %tmp, i32 0
%tmp7 = insertelement <4 x float> %tmp6, float %tmp, i32 1
%tmp8 = insertelement <4 x float> %tmp7, float %tmp, i32 2
%tmp9 = insertelement <4 x float> %tmp8, float %tmp, i32 3
%tmp10 = fmul <4 x float> %tmp9, %tmp5
- store <4 x float> %tmp10, <4 x float>* %dst, align 4
+ store <4 x float> %tmp10, ptr %dst, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/vneg.ll b/llvm/test/CodeGen/ARM/vneg.ll
index 24a585f65a4b7..93a5d01c25c17 100644
--- a/llvm/test/CodeGen/ARM/vneg.ll
+++ b/llvm/test/CodeGen/ARM/vneg.ll
@@ -1,113 +1,113 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vnegs8(ptr %A) nounwind {
;CHECK-LABEL: vnegs8:
;CHECK: vneg.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = sub <8 x i8> zeroinitializer, %tmp1
ret <8 x i8> %tmp2
}
-define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vnegs16(ptr %A) nounwind {
;CHECK-LABEL: vnegs16:
;CHECK: vneg.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = sub <4 x i16> zeroinitializer, %tmp1
ret <4 x i16> %tmp2
}
-define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vnegs32(ptr %A) nounwind {
;CHECK-LABEL: vnegs32:
;CHECK: vneg.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = sub <2 x i32> zeroinitializer, %tmp1
ret <2 x i32> %tmp2
}
-define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
+define <2 x float> @vnegf32(ptr %A) nounwind {
;CHECK-LABEL: vnegf32:
;CHECK: vneg.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = fsub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1
ret <2 x float> %tmp2
}
-define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vnegQs8(ptr %A) nounwind {
;CHECK-LABEL: vnegQs8:
;CHECK: vneg.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = sub <16 x i8> zeroinitializer, %tmp1
ret <16 x i8> %tmp2
}
-define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vnegQs16(ptr %A) nounwind {
;CHECK-LABEL: vnegQs16:
;CHECK: vneg.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = sub <8 x i16> zeroinitializer, %tmp1
ret <8 x i16> %tmp2
}
-define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vnegQs32(ptr %A) nounwind {
;CHECK-LABEL: vnegQs32:
;CHECK: vneg.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = sub <4 x i32> zeroinitializer, %tmp1
ret <4 x i32> %tmp2
}
-define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
+define <4 x float> @vnegQf32(ptr %A) nounwind {
;CHECK-LABEL: vnegQf32:
;CHECK: vneg.f32
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1
ret <4 x float> %tmp2
}
-define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vqnegs8(ptr %A) nounwind {
;CHECK-LABEL: vqnegs8:
;CHECK: vqneg.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vqnegs16(ptr %A) nounwind {
;CHECK-LABEL: vqnegs16:
;CHECK: vqneg.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vqnegs32(ptr %A) nounwind {
;CHECK-LABEL: vqnegs32:
;CHECK: vqneg.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1)
ret <2 x i32> %tmp2
}
-define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vqnegQs8(ptr %A) nounwind {
;CHECK-LABEL: vqnegQs8:
;CHECK: vqneg.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vqnegQs16(ptr %A) nounwind {
;CHECK-LABEL: vqnegQs16:
;CHECK: vqneg.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vqnegQs32(ptr %A) nounwind {
;CHECK-LABEL: vqnegQs32:
;CHECK: vqneg.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1)
ret <4 x i32> %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/vpadal.ll b/llvm/test/CodeGen/ARM/vpadal.ll
index ffb69243b884e..f4f169aae6060 100644
--- a/llvm/test/CodeGen/ARM/vpadal.ll
+++ b/llvm/test/CodeGen/ARM/vpadal.ll
@@ -1,109 +1,109 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
+define <4 x i16> @vpadals8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpadals8:
;CHECK: vpadal.s8
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
+define <2 x i32> @vpadals16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpadals16:
;CHECK: vpadal.s16
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
+define <1 x i64> @vpadals32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpadals32:
;CHECK: vpadal.s32
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
ret <1 x i64> %tmp3
}
-define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
+define <4 x i16> @vpadalu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpadalu8:
;CHECK: vpadal.u8
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
+define <2 x i32> @vpadalu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpadalu16:
;CHECK: vpadal.u16
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
+define <1 x i64> @vpadalu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpadalu32:
;CHECK: vpadal.u32
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
ret <1 x i64> %tmp3
}
-define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
+define <8 x i16> @vpadalQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpadalQs8:
;CHECK: vpadal.s8
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
+define <4 x i32> @vpadalQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpadalQs16:
;CHECK: vpadal.s16
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
+define <2 x i64> @vpadalQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpadalQs32:
;CHECK: vpadal.s32
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
ret <2 x i64> %tmp3
}
-define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
+define <8 x i16> @vpadalQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpadalQu8:
;CHECK: vpadal.u8
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
+define <4 x i32> @vpadalQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpadalQu16:
;CHECK: vpadal.u16
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
+define <2 x i64> @vpadalQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpadalQu32:
;CHECK: vpadal.u32
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
ret <2 x i64> %tmp3
}
diff --git a/llvm/test/CodeGen/ARM/vpadd.ll b/llvm/test/CodeGen/ARM/vpadd.ll
index f5c0a4109e159..cc1d1e6a15fe7 100644
--- a/llvm/test/CodeGen/ARM/vpadd.ll
+++ b/llvm/test/CodeGen/ARM/vpadd.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - -lower-interleaved-accesses=false | FileCheck %s
-define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vpaddi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vpaddi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -9,13 +9,13 @@ define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vpadd.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vpaddi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vpaddi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -23,13 +23,13 @@ define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vpadd.i16 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vpaddi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vpaddi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -37,13 +37,13 @@ define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: vpadd.i32 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x float> @vpaddf32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vpaddf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -51,8 +51,8 @@ define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
; CHECK-NEXT: vpadd.f32 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
ret <2 x float> %tmp3
}
@@ -63,79 +63,79 @@ declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind read
declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
-define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
+define <4 x i16> @vpaddls8(ptr %A) nounwind {
; CHECK-LABEL: vpaddls8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vpaddl.s8 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
+define <2 x i32> @vpaddls16(ptr %A) nounwind {
; CHECK-LABEL: vpaddls16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vpaddl.s16 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1)
ret <2 x i32> %tmp2
}
-define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
+define <1 x i64> @vpaddls32(ptr %A) nounwind {
; CHECK-LABEL: vpaddls32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vpaddl.s32 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1)
ret <1 x i64> %tmp2
}
-define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
+define <4 x i16> @vpaddlu8(ptr %A) nounwind {
; CHECK-LABEL: vpaddlu8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vpaddl.u8 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
+define <2 x i32> @vpaddlu16(ptr %A) nounwind {
; CHECK-LABEL: vpaddlu16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vpaddl.u16 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1)
ret <2 x i32> %tmp2
}
-define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
+define <1 x i64> @vpaddlu32(ptr %A) nounwind {
; CHECK-LABEL: vpaddlu32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vpaddl.u32 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1)
ret <1 x i64> %tmp2
}
-define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
+define <8 x i16> @vpaddlQs8(ptr %A) nounwind {
; CHECK-LABEL: vpaddlQs8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -143,12 +143,12 @@ define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
+define <4 x i32> @vpaddlQs16(ptr %A) nounwind {
; CHECK-LABEL: vpaddlQs16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -156,12 +156,12 @@ define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1)
ret <4 x i32> %tmp2
}
-define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
+define <2 x i64> @vpaddlQs32(ptr %A) nounwind {
; CHECK-LABEL: vpaddlQs32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -169,12 +169,12 @@ define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1)
ret <2 x i64> %tmp2
}
-define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
+define <8 x i16> @vpaddlQu8(ptr %A) nounwind {
; CHECK-LABEL: vpaddlQu8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -182,12 +182,12 @@ define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
+define <4 x i32> @vpaddlQu16(ptr %A) nounwind {
; CHECK-LABEL: vpaddlQu16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -195,12 +195,12 @@ define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1)
ret <4 x i32> %tmp2
}
-define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind {
+define <2 x i64> @vpaddlQu32(ptr %A) nounwind {
; CHECK-LABEL: vpaddlQu32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -208,81 +208,81 @@ define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)
ret <2 x i64> %tmp2
}
; Combine vuzp+vadd->vpadd.
-define void @addCombineToVPADD_i8(<16 x i8> *%cbcr, <8 x i8> *%X) nounwind ssp {
+define void @addCombineToVPADD_i8(ptr %cbcr, ptr %X) nounwind ssp {
; CHECK-LABEL: addCombineToVPADD_i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vpadd.i8 d16, d16, d17
; CHECK-NEXT: vstr d16, [r1]
; CHECK-NEXT: mov pc, lr
- %tmp = load <16 x i8>, <16 x i8>* %cbcr
+ %tmp = load <16 x i8>, ptr %cbcr
%tmp1 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%add = add <8 x i8> %tmp3, %tmp1
- store <8 x i8> %add, <8 x i8>* %X, align 8
+ store <8 x i8> %add, ptr %X, align 8
ret void
}
; Combine vuzp+vadd->vpadd.
-define void @addCombineToVPADD_i16(<8 x i16> *%cbcr, <4 x i16> *%X) nounwind ssp {
+define void @addCombineToVPADD_i16(ptr %cbcr, ptr %X) nounwind ssp {
; CHECK-LABEL: addCombineToVPADD_i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vpadd.i16 d16, d16, d17
; CHECK-NEXT: vstr d16, [r1]
; CHECK-NEXT: mov pc, lr
- %tmp = load <8 x i16>, <8 x i16>* %cbcr
+ %tmp = load <8 x i16>, ptr %cbcr
%tmp1 = shufflevector <8 x i16> %tmp, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%tmp3 = shufflevector <8 x i16> %tmp, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%add = add <4 x i16> %tmp3, %tmp1
- store <4 x i16> %add, <4 x i16>* %X, align 8
+ store <4 x i16> %add, ptr %X, align 8
ret void
}
; Combine vtrn+vadd->vpadd.
-define void @addCombineToVPADD_i32(<4 x i32> *%cbcr, <2 x i32> *%X) nounwind ssp {
+define void @addCombineToVPADD_i32(ptr %cbcr, ptr %X) nounwind ssp {
; CHECK-LABEL: addCombineToVPADD_i32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vpadd.i32 d16, d16, d17
; CHECK-NEXT: vstr d16, [r1]
; CHECK-NEXT: mov pc, lr
- %tmp = load <4 x i32>, <4 x i32>* %cbcr
+ %tmp = load <4 x i32>, ptr %cbcr
%tmp1 = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
%tmp3 = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
%add = add <2 x i32> %tmp3, %tmp1
- store <2 x i32> %add, <2 x i32>* %X, align 8
+ store <2 x i32> %add, ptr %X, align 8
ret void
}
; Combine vuzp+vaddl->vpaddl
-define void @addCombineToVPADDLq_s8(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind ssp {
+define void @addCombineToVPADDLq_s8(ptr %cbcr, ptr %X) nounwind ssp {
; CHECK-LABEL: addCombineToVPADDLq_s8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vpaddl.s8 q8, q8
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
; CHECK-NEXT: mov pc, lr
- %tmp = load <16 x i8>, <16 x i8>* %cbcr
+ %tmp = load <16 x i8>, ptr %cbcr
%tmp1 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%tmp4 = sext <8 x i8> %tmp3 to <8 x i16>
%tmp5 = sext <8 x i8> %tmp1 to <8 x i16>
%add = add <8 x i16> %tmp4, %tmp5
- store <8 x i16> %add, <8 x i16>* %X, align 8
+ store <8 x i16> %add, ptr %X, align 8
ret void
}
; Combine vuzp+vaddl->vpaddl
; FIXME: Legalization butchers the shuffles.
-define void @addCombineToVPADDL_s8(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp {
+define void @addCombineToVPADDL_s8(ptr %cbcr, ptr %X) nounwind ssp {
; CHECK-LABEL: addCombineToVPADDL_s8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -293,37 +293,37 @@ define void @addCombineToVPADDL_s8(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp
; CHECK-NEXT: vsra.s16 d17, d16, #8
; CHECK-NEXT: vstr d17, [r1]
; CHECK-NEXT: mov pc, lr
- %tmp = load <16 x i8>, <16 x i8>* %cbcr
+ %tmp = load <16 x i8>, ptr %cbcr
%tmp1 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%tmp4 = sext <4 x i8> %tmp3 to <4 x i16>
%tmp5 = sext <4 x i8> %tmp1 to <4 x i16>
%add = add <4 x i16> %tmp4, %tmp5
- store <4 x i16> %add, <4 x i16>* %X, align 8
+ store <4 x i16> %add, ptr %X, align 8
ret void
}
; Combine vuzp+vaddl->vpaddl
-define void @addCombineToVPADDLq_u8(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind ssp {
+define void @addCombineToVPADDLq_u8(ptr %cbcr, ptr %X) nounwind ssp {
; CHECK-LABEL: addCombineToVPADDLq_u8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vpaddl.u8 q8, q8
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
; CHECK-NEXT: mov pc, lr
- %tmp = load <16 x i8>, <16 x i8>* %cbcr
+ %tmp = load <16 x i8>, ptr %cbcr
%tmp1 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
%tmp5 = zext <8 x i8> %tmp1 to <8 x i16>
%add = add <8 x i16> %tmp4, %tmp5
- store <8 x i16> %add, <8 x i16>* %X, align 8
+ store <8 x i16> %add, ptr %X, align 8
ret void
}
; In theory, it's possible to match this to vpaddl, but rearranging the
; shuffle is awkward, so this doesn't match at the moment.
-define void @addCombineToVPADDLq_u8_early_zext(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind ssp {
+define void @addCombineToVPADDLq_u8_early_zext(ptr %cbcr, ptr %X) nounwind ssp {
; CHECK-LABEL: addCombineToVPADDLq_u8_early_zext:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -333,18 +333,18 @@ define void @addCombineToVPADDLq_u8_early_zext(<16 x i8> *%cbcr, <8 x i16> *%X)
; CHECK-NEXT: vadd.i16 q8, q8, q9
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
; CHECK-NEXT: mov pc, lr
- %tmp = load <16 x i8>, <16 x i8>* %cbcr
+ %tmp = load <16 x i8>, ptr %cbcr
%tmp1 = zext <16 x i8> %tmp to <16 x i16>
%tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%add = add <8 x i16> %tmp2, %tmp3
- store <8 x i16> %add, <8 x i16>* %X, align 8
+ store <8 x i16> %add, ptr %X, align 8
ret void
}
; Combine vuzp+vaddl->vpaddl
; FIXME: Legalization butchers the shuffle.
-define void @addCombineToVPADDL_u8(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp {
+define void @addCombineToVPADDL_u8(ptr %cbcr, ptr %X) nounwind ssp {
; CHECK-LABEL: addCombineToVPADDL_u8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -354,18 +354,18 @@ define void @addCombineToVPADDL_u8(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp
; CHECK-NEXT: vadd.i16 d16, d17, d16
; CHECK-NEXT: vstr d16, [r1]
; CHECK-NEXT: mov pc, lr
- %tmp = load <16 x i8>, <16 x i8>* %cbcr
+ %tmp = load <16 x i8>, ptr %cbcr
%tmp1 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%tmp4 = zext <4 x i8> %tmp3 to <4 x i16>
%tmp5 = zext <4 x i8> %tmp1 to <4 x i16>
%add = add <4 x i16> %tmp4, %tmp5
- store <4 x i16> %add, <4 x i16>* %X, align 8
+ store <4 x i16> %add, ptr %X, align 8
ret void
}
; Matching to vpaddl.8 requires matching shuffle(zext()).
-define void @addCombineToVPADDL_u8_early_zext(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp {
+define void @addCombineToVPADDL_u8_early_zext(ptr %cbcr, ptr %X) nounwind ssp {
; CHECK-LABEL: addCombineToVPADDL_u8_early_zext:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
@@ -373,84 +373,84 @@ define void @addCombineToVPADDL_u8_early_zext(<16 x i8> *%cbcr, <4 x i16> *%X) n
; CHECK-NEXT: vpadd.i16 d16, d16, d17
; CHECK-NEXT: vstr d16, [r1]
; CHECK-NEXT: mov pc, lr
- %tmp = load <16 x i8>, <16 x i8>* %cbcr
+ %tmp = load <16 x i8>, ptr %cbcr
%tmp1 = zext <16 x i8> %tmp to <16 x i16>
%tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%add = add <4 x i16> %tmp2, %tmp3
- store <4 x i16> %add, <4 x i16>* %X, align 8
+ store <4 x i16> %add, ptr %X, align 8
ret void
}
; Combine vuzp+vaddl->vpaddl
-define void @addCombineToVPADDLq_s16(<8 x i16> *%cbcr, <4 x i32> *%X) nounwind ssp {
+define void @addCombineToVPADDLq_s16(ptr %cbcr, ptr %X) nounwind ssp {
; CHECK-LABEL: addCombineToVPADDLq_s16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vpaddl.s16 q8, q8
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
; CHECK-NEXT: mov pc, lr
- %tmp = load <8 x i16>, <8 x i16>* %cbcr
+ %tmp = load <8 x i16>, ptr %cbcr
%tmp1 = shufflevector <8 x i16> %tmp, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%tmp3 = shufflevector <8 x i16> %tmp, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%tmp4 = sext <4 x i16> %tmp3 to <4 x i32>
%tmp5 = sext <4 x i16> %tmp1 to <4 x i32>
%add = add <4 x i32> %tmp4, %tmp5
- store <4 x i32> %add, <4 x i32>* %X, align 8
+ store <4 x i32> %add, ptr %X, align 8
ret void
}
; Combine vuzp+vaddl->vpaddl
-define void @addCombineToVPADDLq_u16(<8 x i16> *%cbcr, <4 x i32> *%X) nounwind ssp {
+define void @addCombineToVPADDLq_u16(ptr %cbcr, ptr %X) nounwind ssp {
; CHECK-LABEL: addCombineToVPADDLq_u16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vpaddl.u16 q8, q8
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
; CHECK-NEXT: mov pc, lr
- %tmp = load <8 x i16>, <8 x i16>* %cbcr
+ %tmp = load <8 x i16>, ptr %cbcr
%tmp1 = shufflevector <8 x i16> %tmp, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%tmp3 = shufflevector <8 x i16> %tmp, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
%tmp5 = zext <4 x i16> %tmp1 to <4 x i32>
%add = add <4 x i32> %tmp4, %tmp5
- store <4 x i32> %add, <4 x i32>* %X, align 8
+ store <4 x i32> %add, ptr %X, align 8
ret void
}
; Combine vtrn+vaddl->vpaddl
-define void @addCombineToVPADDLq_s32(<4 x i32> *%cbcr, <2 x i64> *%X) nounwind ssp {
+define void @addCombineToVPADDLq_s32(ptr %cbcr, ptr %X) nounwind ssp {
; CHECK-LABEL: addCombineToVPADDLq_s32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vpaddl.s32 q8, q8
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
; CHECK-NEXT: mov pc, lr
- %tmp = load <4 x i32>, <4 x i32>* %cbcr
+ %tmp = load <4 x i32>, ptr %cbcr
%tmp1 = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
%tmp3 = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
%tmp4 = sext <2 x i32> %tmp3 to <2 x i64>
%tmp5 = sext <2 x i32> %tmp1 to <2 x i64>
%add = add <2 x i64> %tmp4, %tmp5
- store <2 x i64> %add, <2 x i64>* %X, align 8
+ store <2 x i64> %add, ptr %X, align 8
ret void
}
; Combine vtrn+vaddl->vpaddl
-define void @addCombineToVPADDLq_u32(<4 x i32> *%cbcr, <2 x i64> *%X) nounwind ssp {
+define void @addCombineToVPADDLq_u32(ptr %cbcr, ptr %X) nounwind ssp {
; CHECK-LABEL: addCombineToVPADDLq_u32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vpaddl.u32 q8, q8
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
; CHECK-NEXT: mov pc, lr
- %tmp = load <4 x i32>, <4 x i32>* %cbcr
+ %tmp = load <4 x i32>, ptr %cbcr
%tmp1 = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
%tmp3 = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
%tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
%tmp5 = zext <2 x i32> %tmp1 to <2 x i64>
%add = add <2 x i64> %tmp4, %tmp5
- store <2 x i64> %add, <2 x i64>* %X, align 8
+ store <2 x i64> %add, ptr %X, align 8
ret void
}
diff --git a/llvm/test/CodeGen/ARM/vpminmax.ll b/llvm/test/CodeGen/ARM/vpminmax.ll
index 9ea8c69612c5e..22c8d69da9e79 100644
--- a/llvm/test/CodeGen/ARM/vpminmax.ll
+++ b/llvm/test/CodeGen/ARM/vpminmax.ll
@@ -1,64 +1,64 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vpmins8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpmins8:
;CHECK: vpmin.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vpmins16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpmins16:
;CHECK: vpmin.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vpmins32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpmins32:
;CHECK: vpmin.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vpminu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpminu8:
;CHECK: vpmin.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vpminu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpminu16:
;CHECK: vpmin.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vpminu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpminu32:
;CHECK: vpmin.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <2 x float> @vpminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x float> @vpminf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpminf32:
;CHECK: vpmin.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = call <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
ret <2 x float> %tmp3
}
@@ -73,65 +73,65 @@ declare <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32>, <2 x i32>) nounwind rea
declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
-define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vpmaxs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpmaxs8:
;CHECK: vpmax.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vpmaxs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpmaxs16:
;CHECK: vpmax.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vpmaxs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpmaxs32:
;CHECK: vpmax.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vpmaxu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpmaxu8:
;CHECK: vpmax.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vpmaxu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpmaxu16:
;CHECK: vpmax.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vpmaxu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpmaxu32:
;CHECK: vpmax.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <2 x float> @vpmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x float> @vpmaxf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vpmaxf32:
;CHECK: vpmax.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = call <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
ret <2 x float> %tmp3
}
diff --git a/llvm/test/CodeGen/ARM/vqadd.ll b/llvm/test/CodeGen/ARM/vqadd.ll
index 47432c7b732d6..7f0bb31910f1a 100644
--- a/llvm/test/CodeGen/ARM/vqadd.ll
+++ b/llvm/test/CodeGen/ARM/vqadd.ll
@@ -1,145 +1,145 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vqadds8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqadds8:
;CHECK: vqadd.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vqadds16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqadds16:
;CHECK: vqadd.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vqadds32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqadds32:
;CHECK: vqadd.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vqadds64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqadds64:
;CHECK: vqadd.s64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.sadd.sat.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vqaddu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddu8:
;CHECK: vqadd.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vqaddu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddu16:
;CHECK: vqadd.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vqaddu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddu32:
;CHECK: vqadd.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vqaddu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddu64:
;CHECK: vqadd.u64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.uadd.sat.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vqaddQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQs8:
;CHECK: vqadd.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vqaddQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQs16:
;CHECK: vqadd.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vqaddQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQs32:
;CHECK: vqadd.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vqaddQs64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQs64:
;CHECK: vqadd.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
-define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vqaddQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQu8:
;CHECK: vqadd.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vqaddQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQu16:
;CHECK: vqadd.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vqaddQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQu32:
;CHECK: vqadd.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vqaddQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vqaddQu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqaddQu64:
;CHECK: vqadd.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
diff --git a/llvm/test/CodeGen/ARM/vqdmul.ll b/llvm/test/CodeGen/ARM/vqdmul.ll
index fa938d45becfb..cf1f81790eff4 100644
--- a/llvm/test/CodeGen/ARM/vqdmul.ll
+++ b/llvm/test/CodeGen/ARM/vqdmul.ll
@@ -2,38 +2,38 @@
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
target triple = "thumbv7-elf"
-define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vqdmulhs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqdmulhs16:
;CHECK: vqdmulh.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vqdmulhs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqdmulhs32:
;CHECK: vqdmulh.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vqdmulhQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqdmulhQs16:
;CHECK: vqdmulh.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vqdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vqdmulhQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqdmulhQs32:
;CHECK: vqdmulh.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
@@ -80,38 +80,38 @@ declare <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind re
declare <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vqrdmulhs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrdmulhs16:
;CHECK: vqrdmulh.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vqrdmulhs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrdmulhs32:
;CHECK: vqrdmulh.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vqrdmulhQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrdmulhQs16:
;CHECK: vqrdmulh.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vqrdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vqrdmulhQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrdmulhQs32:
;CHECK: vqrdmulh.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
@@ -158,20 +158,20 @@ declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind r
declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i32> @vqdmulls16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqdmulls16:
;CHECK: vqdmull.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vqdmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i64> @vqdmulls32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqdmulls32:
;CHECK: vqdmull.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i64> %tmp3
}
@@ -197,23 +197,23 @@ entry:
declare <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
declare <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
-define <4 x i32> @vqdmlals16_natural(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+define <4 x i32> @vqdmlals16_natural(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vqdmlals16_natural:
;CHECK: vqdmlal.s16
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i16>, <4 x i16>* %C
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
+ %tmp3 = load <4 x i16>, ptr %C
%tmp4 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp2, <4 x i16> %tmp3)
%tmp5 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp4)
ret <4 x i32> %tmp5
}
-define <2 x i64> @vqdmlals32_natural(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+define <2 x i64> @vqdmlals32_natural(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vqdmlals32_natural:
;CHECK: vqdmlal.s32
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i32>, <2 x i32>* %C
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
+ %tmp3 = load <2 x i32>, ptr %C
%tmp4 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp2, <2 x i32> %tmp3)
%tmp5 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp4)
ret <2 x i64> %tmp5
@@ -242,23 +242,23 @@ entry:
declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
declare <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
-define <4 x i32> @vqdmlsls16_natural(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+define <4 x i32> @vqdmlsls16_natural(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vqdmlsls16_natural:
;CHECK: vqdmlsl.s16
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
- %tmp3 = load <4 x i16>, <4 x i16>* %C
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
+ %tmp3 = load <4 x i16>, ptr %C
%tmp4 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp2, <4 x i16> %tmp3)
%tmp5 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp4)
ret <4 x i32> %tmp5
}
-define <2 x i64> @vqdmlsls32_natural(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+define <2 x i64> @vqdmlsls32_natural(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vqdmlsls32_natural:
;CHECK: vqdmlsl.s32
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
- %tmp3 = load <2 x i32>, <2 x i32>* %C
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
+ %tmp3 = load <2 x i32>, ptr %C
%tmp4 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp2, <2 x i32> %tmp3)
%tmp5 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp4)
ret <2 x i64> %tmp5
diff --git a/llvm/test/CodeGen/ARM/vqshl.ll b/llvm/test/CodeGen/ARM/vqshl.ll
index 6a6d9af7a2b3b..3ba5fa9c87222 100644
--- a/llvm/test/CodeGen/ARM/vqshl.ll
+++ b/llvm/test/CodeGen/ARM/vqshl.ll
@@ -1,337 +1,337 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vqshls8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshls8:
;CHECK: vqshl.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vqshls16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshls16:
;CHECK: vqshl.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vqshls32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshls32:
;CHECK: vqshl.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vqshls64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshls64:
;CHECK: vqshl.s64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vqshlu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshlu8:
;CHECK: vqshl.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vqshlu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshlu16:
;CHECK: vqshl.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vqshlu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshlu32:
;CHECK: vqshl.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vqshlu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshlu64:
;CHECK: vqshl.u64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vqshlQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshlQs8:
;CHECK: vqshl.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vqshlQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshlQs16:
;CHECK: vqshl.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vqshlQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshlQs32:
;CHECK: vqshl.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vqshlQs64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshlQs64:
;CHECK: vqshl.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
-define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vqshlQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshlQu8:
;CHECK: vqshl.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vqshlQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshlQu16:
;CHECK: vqshl.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vqshlQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshlQu32:
;CHECK: vqshl.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vqshlQu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqshlQu64:
;CHECK: vqshl.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
-define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vqshls_n8(ptr %A) nounwind {
;CHECK-LABEL: vqshls_n8:
;CHECK: vqshl.s8{{.*#7}}
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vqshls_n16(ptr %A) nounwind {
;CHECK-LABEL: vqshls_n16:
;CHECK: vqshl.s16{{.*#15}}
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vqshls_n32(ptr %A) nounwind {
;CHECK-LABEL: vqshls_n32:
;CHECK: vqshl.s32{{.*#31}}
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
ret <2 x i32> %tmp2
}
-define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind {
+define <1 x i64> @vqshls_n64(ptr %A) nounwind {
;CHECK-LABEL: vqshls_n64:
;CHECK: vqshl.s64{{.*#63}}
- %tmp1 = load <1 x i64>, <1 x i64>* %A
+ %tmp1 = load <1 x i64>, ptr %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
ret <1 x i64> %tmp2
}
-define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vqshlu_n8(ptr %A) nounwind {
;CHECK-LABEL: vqshlu_n8:
;CHECK: vqshl.u8{{.*#7}}
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vqshlu_n16(ptr %A) nounwind {
;CHECK-LABEL: vqshlu_n16:
;CHECK: vqshl.u16{{.*#15}}
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vqshlu_n32(ptr %A) nounwind {
;CHECK-LABEL: vqshlu_n32:
;CHECK: vqshl.u32{{.*#31}}
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
ret <2 x i32> %tmp2
}
-define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind {
+define <1 x i64> @vqshlu_n64(ptr %A) nounwind {
;CHECK-LABEL: vqshlu_n64:
;CHECK: vqshl.u64{{.*#63}}
- %tmp1 = load <1 x i64>, <1 x i64>* %A
+ %tmp1 = load <1 x i64>, ptr %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
ret <1 x i64> %tmp2
}
-define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vqshlsu_n8(ptr %A) nounwind {
;CHECK-LABEL: vqshlsu_n8:
;CHECK: vqshlu.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vqshlsu_n16(ptr %A) nounwind {
;CHECK-LABEL: vqshlsu_n16:
;CHECK: vqshlu.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vqshlsu_n32(ptr %A) nounwind {
;CHECK-LABEL: vqshlsu_n32:
;CHECK: vqshlu.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
ret <2 x i32> %tmp2
}
-define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind {
+define <1 x i64> @vqshlsu_n64(ptr %A) nounwind {
;CHECK-LABEL: vqshlsu_n64:
;CHECK: vqshlu.s64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
+ %tmp1 = load <1 x i64>, ptr %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
ret <1 x i64> %tmp2
}
-define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vqshlQs_n8(ptr %A) nounwind {
;CHECK-LABEL: vqshlQs_n8:
;CHECK: vqshl.s8{{.*#7}}
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vqshlQs_n16(ptr %A) nounwind {
;CHECK-LABEL: vqshlQs_n16:
;CHECK: vqshl.s16{{.*#15}}
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vqshlQs_n32(ptr %A) nounwind {
;CHECK-LABEL: vqshlQs_n32:
;CHECK: vqshl.s32{{.*#31}}
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
ret <4 x i32> %tmp2
}
-define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind {
+define <2 x i64> @vqshlQs_n64(ptr %A) nounwind {
;CHECK-LABEL: vqshlQs_n64:
;CHECK: vqshl.s64{{.*#63}}
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
ret <2 x i64> %tmp2
}
-define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vqshlQu_n8(ptr %A) nounwind {
;CHECK-LABEL: vqshlQu_n8:
;CHECK: vqshl.u8{{.*#7}}
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vqshlQu_n16(ptr %A) nounwind {
;CHECK-LABEL: vqshlQu_n16:
;CHECK: vqshl.u16{{.*#15}}
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vqshlQu_n32(ptr %A) nounwind {
;CHECK-LABEL: vqshlQu_n32:
;CHECK: vqshl.u32{{.*#31}}
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
ret <4 x i32> %tmp2
}
-define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind {
+define <2 x i64> @vqshlQu_n64(ptr %A) nounwind {
;CHECK-LABEL: vqshlQu_n64:
;CHECK: vqshl.u64{{.*#63}}
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
ret <2 x i64> %tmp2
}
-define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vqshlQsu_n8(ptr %A) nounwind {
;CHECK-LABEL: vqshlQsu_n8:
;CHECK: vqshlu.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vqshlQsu_n16(ptr %A) nounwind {
;CHECK-LABEL: vqshlQsu_n16:
;CHECK: vqshlu.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vqshlQsu_n32(ptr %A) nounwind {
;CHECK-LABEL: vqshlQsu_n32:
;CHECK: vqshlu.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
ret <4 x i32> %tmp2
}
-define <2 x i64> @vqshlQsu_n64(<2 x i64>* %A) nounwind {
+define <2 x i64> @vqshlQsu_n64(ptr %A) nounwind {
;CHECK-LABEL: vqshlQsu_n64:
;CHECK: vqshlu.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
ret <2 x i64> %tmp2
}
@@ -366,146 +366,146 @@ declare <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16>, <8 x i16>) nounwind
declare <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
declare <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
-define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vqrshls8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshls8:
;CHECK: vqrshl.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vqrshls16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshls16:
;CHECK: vqrshl.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vqrshls32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshls32:
;CHECK: vqrshl.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vqrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vqrshls64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshls64:
;CHECK: vqrshl.s64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vqrshlu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshlu8:
;CHECK: vqrshl.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vqrshlu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshlu16:
;CHECK: vqrshl.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vqrshlu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshlu32:
;CHECK: vqrshl.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vqrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vqrshlu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshlu64:
;CHECK: vqrshl.u64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vqrshlQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshlQs8:
;CHECK: vqrshl.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vqrshlQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshlQs16:
;CHECK: vqrshl.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vqrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vqrshlQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshlQs32:
;CHECK: vqrshl.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vqrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vqrshlQs64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshlQs64:
;CHECK: vqrshl.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vqrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
-define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vqrshlQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshlQu8:
;CHECK: vqrshl.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vqrshlQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshlQu16:
;CHECK: vqrshl.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vqrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vqrshlQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshlQu32:
;CHECK: vqrshl.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vqrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vqrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vqrshlQu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqrshlQu64:
;CHECK: vqrshl.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vqrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
diff --git a/llvm/test/CodeGen/ARM/vqshrn.ll b/llvm/test/CodeGen/ARM/vqshrn.ll
index b4b5e96d4579b..2896a22a6c4a3 100644
--- a/llvm/test/CodeGen/ARM/vqshrn.ll
+++ b/llvm/test/CodeGen/ARM/vqshrn.ll
@@ -1,73 +1,73 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
+define <8 x i8> @vqshrns8(ptr %A) nounwind {
;CHECK-LABEL: vqshrns8:
;CHECK: vqshrn.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
+define <4 x i16> @vqshrns16(ptr %A) nounwind {
;CHECK-LABEL: vqshrns16:
;CHECK: vqshrn.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
+define <2 x i32> @vqshrns32(ptr %A) nounwind {
;CHECK-LABEL: vqshrns32:
;CHECK: vqshrn.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
ret <2 x i32> %tmp2
}
-define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
+define <8 x i8> @vqshrnu8(ptr %A) nounwind {
;CHECK-LABEL: vqshrnu8:
;CHECK: vqshrn.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
+define <4 x i16> @vqshrnu16(ptr %A) nounwind {
;CHECK-LABEL: vqshrnu16:
;CHECK: vqshrn.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
+define <2 x i32> @vqshrnu32(ptr %A) nounwind {
;CHECK-LABEL: vqshrnu32:
;CHECK: vqshrn.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
ret <2 x i32> %tmp2
}
-define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
+define <8 x i8> @vqshruns8(ptr %A) nounwind {
;CHECK-LABEL: vqshruns8:
;CHECK: vqshrun.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
+define <4 x i16> @vqshruns16(ptr %A) nounwind {
;CHECK-LABEL: vqshruns16:
;CHECK: vqshrun.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind {
+define <2 x i32> @vqshruns32(ptr %A) nounwind {
;CHECK-LABEL: vqshruns32:
;CHECK: vqshrun.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
ret <2 x i32> %tmp2
}
@@ -84,74 +84,74 @@ declare <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind
declare <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
-define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
+define <8 x i8> @vqrshrns8(ptr %A) nounwind {
;CHECK-LABEL: vqrshrns8:
;CHECK: vqrshrn.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
+define <4 x i16> @vqrshrns16(ptr %A) nounwind {
;CHECK-LABEL: vqrshrns16:
;CHECK: vqrshrn.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
+define <2 x i32> @vqrshrns32(ptr %A) nounwind {
;CHECK-LABEL: vqrshrns32:
;CHECK: vqrshrn.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
ret <2 x i32> %tmp2
}
-define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
+define <8 x i8> @vqrshrnu8(ptr %A) nounwind {
;CHECK-LABEL: vqrshrnu8:
;CHECK: vqrshrn.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
+define <4 x i16> @vqrshrnu16(ptr %A) nounwind {
;CHECK-LABEL: vqrshrnu16:
;CHECK: vqrshrn.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
+define <2 x i32> @vqrshrnu32(ptr %A) nounwind {
;CHECK-LABEL: vqrshrnu32:
;CHECK: vqrshrn.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
ret <2 x i32> %tmp2
}
-define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
+define <8 x i8> @vqrshruns8(ptr %A) nounwind {
;CHECK-LABEL: vqrshruns8:
;CHECK: vqrshrun.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
+define <4 x i16> @vqrshruns16(ptr %A) nounwind {
;CHECK-LABEL: vqrshruns16:
;CHECK: vqrshrun.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind {
+define <2 x i32> @vqrshruns32(ptr %A) nounwind {
;CHECK-LABEL: vqrshruns32:
;CHECK: vqrshrun.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
ret <2 x i32> %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/vqsub.ll b/llvm/test/CodeGen/ARM/vqsub.ll
index 9864f6421cb3d..866a75f094ac8 100644
--- a/llvm/test/CodeGen/ARM/vqsub.ll
+++ b/llvm/test/CodeGen/ARM/vqsub.ll
@@ -1,145 +1,145 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vqsubs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubs8:
;CHECK: vqsub.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vqsubs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubs16:
;CHECK: vqsub.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vqsubs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubs32:
;CHECK: vqsub.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vqsubs64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubs64:
;CHECK: vqsub.s64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.ssub.sat.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vqsubu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubu8:
;CHECK: vqsub.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vqsubu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubu16:
;CHECK: vqsub.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vqsubu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubu32:
;CHECK: vqsub.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vqsubu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubu64:
;CHECK: vqsub.u64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.usub.sat.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vqsubQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQs8:
;CHECK: vqsub.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vqsubQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQs16:
;CHECK: vqsub.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vqsubQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQs32:
;CHECK: vqsub.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vqsubQs64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQs64:
;CHECK: vqsub.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
-define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vqsubQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQu8:
;CHECK: vqsub.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vqsubQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQu16:
;CHECK: vqsub.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vqsubQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQu32:
;CHECK: vqsub.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vqsubQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vqsubQu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vqsubQu64:
;CHECK: vqsub.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
diff --git a/llvm/test/CodeGen/ARM/vrec.ll b/llvm/test/CodeGen/ARM/vrec.ll
index a7ebd79289d8f..91d5f6000d06d 100644
--- a/llvm/test/CodeGen/ARM/vrec.ll
+++ b/llvm/test/CodeGen/ARM/vrec.ll
@@ -1,33 +1,33 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vrecpei32(ptr %A) nounwind {
;CHECK-LABEL: vrecpei32:
;CHECK: vrecpe.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
ret <2 x i32> %tmp2
}
-define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vrecpeQi32(ptr %A) nounwind {
;CHECK-LABEL: vrecpeQi32:
;CHECK: vrecpe.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
ret <4 x i32> %tmp2
}
-define <2 x float> @vrecpef32(<2 x float>* %A) nounwind {
+define <2 x float> @vrecpef32(ptr %A) nounwind {
;CHECK-LABEL: vrecpef32:
;CHECK: vrecpe.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
ret <2 x float> %tmp2
}
-define <4 x float> @vrecpeQf32(<4 x float>* %A) nounwind {
+define <4 x float> @vrecpeQf32(ptr %A) nounwind {
;CHECK-LABEL: vrecpeQf32:
;CHECK: vrecpe.f32
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
ret <4 x float> %tmp2
}
@@ -38,20 +38,20 @@ declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) nounwind readnone
declare <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float>) nounwind readnone
declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
-define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x float> @vrecpsf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrecpsf32:
;CHECK: vrecps.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = call <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
ret <2 x float> %tmp3
}
-define <4 x float> @vrecpsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x float> @vrecpsQf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrecpsQf32:
;CHECK: vrecps.f32
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
ret <4 x float> %tmp3
}
@@ -59,34 +59,34 @@ define <4 x float> @vrecpsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
declare <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
-define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vrsqrtei32(ptr %A) nounwind {
;CHECK-LABEL: vrsqrtei32:
;CHECK: vrsqrte.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
ret <2 x i32> %tmp2
}
-define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vrsqrteQi32(ptr %A) nounwind {
;CHECK-LABEL: vrsqrteQi32:
;CHECK: vrsqrte.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
ret <4 x i32> %tmp2
}
-define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind {
+define <2 x float> @vrsqrtef32(ptr %A) nounwind {
;CHECK-LABEL: vrsqrtef32:
;CHECK: vrsqrte.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
ret <2 x float> %tmp2
}
-define <4 x float> @vrsqrteQf32(<4 x float>* %A) nounwind {
+define <4 x float> @vrsqrteQf32(ptr %A) nounwind {
;CHECK-LABEL: vrsqrteQf32:
;CHECK: vrsqrte.f32
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
ret <4 x float> %tmp2
}
@@ -97,20 +97,20 @@ declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>) nounwind readnone
declare <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float>) nounwind readnone
declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
-define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x float> @vrsqrtsf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsqrtsf32:
;CHECK: vrsqrts.f32
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
ret <2 x float> %tmp3
}
-define <4 x float> @vrsqrtsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x float> @vrsqrtsQf32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsqrtsQf32:
;CHECK: vrsqrts.f32
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
ret <4 x float> %tmp3
}
diff --git a/llvm/test/CodeGen/ARM/vrev.ll b/llvm/test/CodeGen/ARM/vrev.ll
index 4bea880218d93..df286b0118069 100644
--- a/llvm/test/CodeGen/ARM/vrev.ll
+++ b/llvm/test/CodeGen/ARM/vrev.ll
@@ -1,67 +1,67 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm-eabi -mattr=+neon,+fullfp16 %s -o - | FileCheck %s
-define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
+define <8 x i8> @test_vrev64D8(ptr %A) nounwind {
; CHECK-LABEL: test_vrev64D8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vrev64.8 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i8> %tmp2
}
-define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
+define <4 x i16> @test_vrev64D16(ptr %A) nounwind {
; CHECK-LABEL: test_vrev64D16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vrev64.16 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x i16> %tmp2
}
-define <4 x half> @test_vrev64Df16(<4 x half>* %A) nounwind {
+define <4 x half> @test_vrev64Df16(ptr %A) nounwind {
; CHECK-LABEL: test_vrev64Df16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vrev64.16 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x half>, <4 x half>* %A
+ %tmp1 = load <4 x half>, ptr %A
%tmp2 = shufflevector <4 x half> %tmp1, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x half> %tmp2
}
-define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
+define <2 x i32> @test_vrev64D32(ptr %A) nounwind {
; CHECK-LABEL: test_vrev64D32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vrev64.32 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
ret <2 x i32> %tmp2
}
-define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
+define <2 x float> @test_vrev64Df(ptr %A) nounwind {
; CHECK-LABEL: test_vrev64Df:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vrev64.32 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %A
+ %tmp1 = load <2 x float>, ptr %A
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
ret <2 x float> %tmp2
}
-define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
+define <16 x i8> @test_vrev64Q8(ptr %A) nounwind {
; CHECK-LABEL: test_vrev64Q8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -69,12 +69,12 @@ define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
ret <16 x i8> %tmp2
}
-define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
+define <8 x i16> @test_vrev64Q16(ptr %A) nounwind {
; CHECK-LABEL: test_vrev64Q16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -82,12 +82,12 @@ define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
ret <8 x i16> %tmp2
}
-define <8 x half> @test_vrev64Qf16(<8 x half>* %A) nounwind {
+define <8 x half> @test_vrev64Qf16(ptr %A) nounwind {
; CHECK-LABEL: test_vrev64Qf16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -95,12 +95,12 @@ define <8 x half> @test_vrev64Qf16(<8 x half>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x half>, <8 x half>* %A
+ %tmp1 = load <8 x half>, ptr %A
%tmp2 = shufflevector <8 x half> %tmp1, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
ret <8 x half> %tmp2
}
-define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
+define <4 x i32> @test_vrev64Q32(ptr %A) nounwind {
; CHECK-LABEL: test_vrev64Q32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -108,12 +108,12 @@ define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
ret <4 x i32> %tmp2
}
-define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
+define <4 x float> @test_vrev64Qf(ptr %A) nounwind {
; CHECK-LABEL: test_vrev64Qf:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -121,48 +121,48 @@ define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
+ %tmp1 = load <4 x float>, ptr %A
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
ret <4 x float> %tmp2
}
-define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
+define <8 x i8> @test_vrev32D8(ptr %A) nounwind {
; CHECK-LABEL: test_vrev32D8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vrev32.8 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
ret <8 x i8> %tmp2
}
-define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
+define <4 x i16> @test_vrev32D16(ptr %A) nounwind {
; CHECK-LABEL: test_vrev32D16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vrev32.16 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
ret <4 x i16> %tmp2
}
-define <4 x half> @test_vrev32Df16(<4 x half>* %A) nounwind {
+define <4 x half> @test_vrev32Df16(ptr %A) nounwind {
; CHECK-LABEL: test_vrev32Df16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vrev32.16 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x half>, <4 x half>* %A
+ %tmp1 = load <4 x half>, ptr %A
%tmp2 = shufflevector <4 x half> %tmp1, <4 x half> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
ret <4 x half> %tmp2
}
-define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
+define <16 x i8> @test_vrev32Q8(ptr %A) nounwind {
; CHECK-LABEL: test_vrev32Q8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -170,12 +170,12 @@ define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
ret <16 x i8> %tmp2
}
-define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
+define <8 x i16> @test_vrev32Q16(ptr %A) nounwind {
; CHECK-LABEL: test_vrev32Q16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -183,12 +183,12 @@ define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
ret <8 x i16> %tmp2
}
-define <8 x half> @test_vrev32Qf16(<8 x half>* %A) nounwind {
+define <8 x half> @test_vrev32Qf16(ptr %A) nounwind {
; CHECK-LABEL: test_vrev32Qf16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -196,24 +196,24 @@ define <8 x half> @test_vrev32Qf16(<8 x half>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x half>, <8 x half>* %A
+ %tmp1 = load <8 x half>, ptr %A
%tmp2 = shufflevector <8 x half> %tmp1, <8 x half> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
ret <8 x half> %tmp2
}
-define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
+define <8 x i8> @test_vrev16D8(ptr %A) nounwind {
; CHECK-LABEL: test_vrev16D8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vrev16.8 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
ret <8 x i8> %tmp2
}
-define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
+define <16 x i8> @test_vrev16Q8(ptr %A) nounwind {
; CHECK-LABEL: test_vrev16Q8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -221,26 +221,26 @@ define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
ret <16 x i8> %tmp2
}
; Undef shuffle indices should not prevent matching to VREV:
-define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
+define <8 x i8> @test_vrev64D8_undef(ptr %A) nounwind {
; CHECK-LABEL: test_vrev64D8_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vrev64.8 d16, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i8> %tmp2
}
-define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
+define <8 x i16> @test_vrev32Q16_undef(ptr %A) nounwind {
; CHECK-LABEL: test_vrev32Q16_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -248,12 +248,12 @@ define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
ret <8 x i16> %tmp2
}
-define <8 x half> @test_vrev32Qf16_undef(<8 x half>* %A) nounwind {
+define <8 x half> @test_vrev32Qf16_undef(ptr %A) nounwind {
; CHECK-LABEL: test_vrev32Qf16_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -261,14 +261,14 @@ define <8 x half> @test_vrev32Qf16_undef(<8 x half>* %A) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x half>, <8 x half>* %A
+ %tmp1 = load <8 x half>, ptr %A
%tmp2 = shufflevector <8 x half> %tmp1, <8 x half> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
ret <8 x half> %tmp2
}
; A vcombine feeding a VREV should not obscure things. Radar 8597007.
-define void @test_with_vcombine(<4 x float>* %v) nounwind {
+define void @test_with_vcombine(ptr %v) nounwind {
; CHECK-LABEL: test_with_vcombine:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0:128]
@@ -277,7 +277,7 @@ define void @test_with_vcombine(<4 x float>* %v) nounwind {
; CHECK-NEXT: vrev64.32 d17, d18
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %v, align 16
+ %tmp1 = load <4 x float>, ptr %v, align 16
%tmp2 = bitcast <4 x float> %tmp1 to <2 x double>
%tmp3 = extractelement <2 x double> %tmp2, i32 0
%tmp4 = bitcast double %tmp3 to <2 x float>
@@ -285,13 +285,13 @@ define void @test_with_vcombine(<4 x float>* %v) nounwind {
%tmp6 = bitcast double %tmp5 to <2 x float>
%tmp7 = fadd <2 x float> %tmp6, %tmp6
%tmp8 = shufflevector <2 x float> %tmp4, <2 x float> %tmp7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
- store <4 x float> %tmp8, <4 x float>* %v, align 16
+ store <4 x float> %tmp8, ptr %v, align 16
ret void
}
; The type <2 x i16> is legalized to <2 x i32> and need to be trunc-stored
; to <2 x i16> when stored to memory.
-define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
+define void @test_vrev64(ptr nocapture %source, ptr nocapture %dst) nounwind ssp {
; CHECK-LABEL: test_vrev64:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.32 {d16, d17}, [r0]
@@ -303,18 +303,17 @@ define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst
; CHECK-NEXT: vst1.32 {d16[0]}, [r1:32]
; CHECK-NEXT: mov pc, lr
entry:
- %0 = bitcast <4 x i16>* %source to <8 x i16>*
- %tmp2 = load <8 x i16>, <8 x i16>* %0, align 4
+ %tmp2 = load <8 x i16>, ptr %source, align 4
%tmp3 = extractelement <8 x i16> %tmp2, i32 6
%tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0
%tmp9 = extractelement <8 x i16> %tmp2, i32 5
%tmp11 = insertelement <2 x i16> %tmp5, i16 %tmp9, i32 1
- store <2 x i16> %tmp11, <2 x i16>* %dst, align 4
+ store <2 x i16> %tmp11, ptr %dst, align 4
ret void
}
; Test vrev of float4
-define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest) nounwind noinline ssp {
+define void @float_vrev64(ptr nocapture %source, ptr nocapture %dest) nounwind noinline ssp {
; CHECK-LABEL: float_vrev64:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q8, #0x0
@@ -325,11 +324,10 @@ define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest
; CHECK-NEXT: vst1.32 {d16, d17}, [r0]
; CHECK-NEXT: mov pc, lr
entry:
- %0 = bitcast float* %source to <4 x float>*
- %tmp2 = load <4 x float>, <4 x float>* %0, align 4
+ %tmp2 = load <4 x float>, ptr %source, align 4
%tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0>
- %arrayidx8 = getelementptr inbounds <4 x float>, <4 x float>* %dest, i32 11
- store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4
+ %arrayidx8 = getelementptr inbounds <4 x float>, ptr %dest, i32 11
+ store <4 x float> %tmp5, ptr %arrayidx8, align 4
ret void
}
diff --git a/llvm/test/CodeGen/ARM/vrint.ll b/llvm/test/CodeGen/ARM/vrint.ll
index 55a6253735ffe..908be673295ff 100644
--- a/llvm/test/CodeGen/ARM/vrint.ll
+++ b/llvm/test/CodeGen/ARM/vrint.ll
@@ -4,8 +4,8 @@ declare float @llvm.arm.neon.vrintn.f32(float) nounwind readnone
; CHECK-LABEL: vrintn_f32:
; CHECK: vrintn.f32
-define float @vrintn_f32(float* %A) nounwind {
- %tmp1 = load float, float* %A
+define float @vrintn_f32(ptr %A) nounwind {
+ %tmp1 = load float, ptr %A
%tmp2 = call float @llvm.arm.neon.vrintn.f32(float %tmp1)
ret float %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/vsel-fp16.ll b/llvm/test/CodeGen/ARM/vsel-fp16.ll
index fda1fcb5f87cd..c4eebe17f4d1e 100644
--- a/llvm/test/CodeGen/ARM/vsel-fp16.ll
+++ b/llvm/test/CodeGen/ARM/vsel-fp16.ll
@@ -3,7 +3,7 @@
@varhalf = global half 0.0
@vardouble = global double 0.0
-define void @test_vsel32sgt(i32 %lhs, i32 %rhs, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32sgt(i32 %lhs, i32 %rhs, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32sgt:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -14,15 +14,15 @@ define void @test_vsel32sgt(i32 %lhs, i32 %rhs, half* %a_ptr, half* %b_ptr) {
; CHECK-NEXT: movt r0, :upper16:varhalf
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
%tst1 = icmp sgt i32 %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32sge(i32 %lhs, i32 %rhs, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32sge(i32 %lhs, i32 %rhs, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32sge:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -33,15 +33,15 @@ define void @test_vsel32sge(i32 %lhs, i32 %rhs, half* %a_ptr, half* %b_ptr) {
; CHECK-NEXT: movt r0, :upper16:varhalf
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
%tst1 = icmp sge i32 %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32eq(i32 %lhs, i32 %rhs, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32eq(i32 %lhs, i32 %rhs, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32eq:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -52,15 +52,15 @@ define void @test_vsel32eq(i32 %lhs, i32 %rhs, half* %a_ptr, half* %b_ptr) {
; CHECK-NEXT: movt r0, :upper16:varhalf
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
%tst1 = icmp eq i32 %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32slt(i32 %lhs, i32 %rhs, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32slt(i32 %lhs, i32 %rhs, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32slt:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -71,15 +71,15 @@ define void @test_vsel32slt(i32 %lhs, i32 %rhs, half* %a_ptr, half* %b_ptr) {
; CHECK-NEXT: movt r0, :upper16:varhalf
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
%tst1 = icmp slt i32 %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32sle(i32 %lhs, i32 %rhs, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32sle(i32 %lhs, i32 %rhs, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32sle:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -90,15 +90,15 @@ define void @test_vsel32sle(i32 %lhs, i32 %rhs, half* %a_ptr, half* %b_ptr) {
; CHECK-NEXT: movt r0, :upper16:varhalf
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
%tst1 = icmp sle i32 %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32ogt(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32ogt(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32ogt:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -112,17 +112,17 @@ define void @test_vsel32ogt(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half*
; CHECK-NEXT: vselgt.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp ogt half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32oge(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32oge(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32oge:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -136,17 +136,17 @@ define void @test_vsel32oge(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half*
; CHECK-NEXT: vselge.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp oge half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32oeq(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32oeq(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32oeq:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -160,17 +160,17 @@ define void @test_vsel32oeq(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half*
; CHECK-NEXT: vseleq.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp oeq half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32ugt(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32ugt(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32ugt:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -184,17 +184,17 @@ define void @test_vsel32ugt(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half*
; CHECK-NEXT: vselge.f16 s0, s2, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp ugt half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32uge(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32uge(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32uge:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -208,17 +208,17 @@ define void @test_vsel32uge(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half*
; CHECK-NEXT: vselgt.f16 s0, s2, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp uge half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32olt(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32olt(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32olt:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -232,17 +232,17 @@ define void @test_vsel32olt(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half*
; CHECK-NEXT: vselgt.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp olt half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32ult(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32ult(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32ult:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -256,17 +256,17 @@ define void @test_vsel32ult(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half*
; CHECK-NEXT: vselge.f16 s0, s2, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp ult half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32ole(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32ole(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32ole:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -280,17 +280,17 @@ define void @test_vsel32ole(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half*
; CHECK-NEXT: vselge.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp ole half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32ule(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32ule(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32ule:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -304,17 +304,17 @@ define void @test_vsel32ule(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half*
; CHECK-NEXT: vselgt.f16 s0, s2, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp ule half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32ord(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32ord(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32ord:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -328,17 +328,17 @@ define void @test_vsel32ord(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half*
; CHECK-NEXT: vselvs.f16 s0, s2, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp ord half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32une(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32une(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32une:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -352,17 +352,17 @@ define void @test_vsel32une(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half*
; CHECK-NEXT: vseleq.f16 s0, s2, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp une half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32uno(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32uno(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32uno:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -376,18 +376,18 @@ define void @test_vsel32uno(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half*
; CHECK-NEXT: vselvs.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp uno half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32ogt_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32ogt_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32ogt_nnan:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -401,17 +401,17 @@ define void @test_vsel32ogt_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, h
; CHECK-NEXT: vselgt.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp nnan ogt half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32oge_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32oge_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32oge_nnan:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -425,17 +425,17 @@ define void @test_vsel32oge_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, h
; CHECK-NEXT: vselge.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp nnan oge half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32oeq_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32oeq_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32oeq_nnan:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -449,17 +449,17 @@ define void @test_vsel32oeq_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, h
; CHECK-NEXT: vseleq.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp nnan oeq half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32ugt_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32ugt_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32ugt_nnan:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -473,17 +473,17 @@ define void @test_vsel32ugt_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, h
; CHECK-NEXT: vselgt.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp nnan ugt half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32uge_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32uge_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32uge_nnan:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -497,17 +497,17 @@ define void @test_vsel32uge_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, h
; CHECK-NEXT: vselge.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp nnan uge half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32olt_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32olt_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32olt_nnan:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -521,17 +521,17 @@ define void @test_vsel32olt_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, h
; CHECK-NEXT: vselgt.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp nnan olt half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32ult_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32ult_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32ult_nnan:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -545,17 +545,17 @@ define void @test_vsel32ult_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, h
; CHECK-NEXT: vselgt.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp nnan ult half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32ole_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32ole_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32ole_nnan:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -569,17 +569,17 @@ define void @test_vsel32ole_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, h
; CHECK-NEXT: vselge.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp nnan ole half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32ule_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32ule_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32ule_nnan:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -593,17 +593,17 @@ define void @test_vsel32ule_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, h
; CHECK-NEXT: vselge.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp nnan ule half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32ord_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32ord_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32ord_nnan:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -617,17 +617,17 @@ define void @test_vsel32ord_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, h
; CHECK-NEXT: vselvs.f16 s0, s2, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp nnan ord half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32une_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32une_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32une_nnan:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -641,17 +641,17 @@ define void @test_vsel32une_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, h
; CHECK-NEXT: vseleq.f16 s0, s2, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp nnan une half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
-define void @test_vsel32uno_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, half* %b_ptr) {
+define void @test_vsel32uno_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-LABEL: test_vsel32uno_nnan:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r2]
@@ -665,12 +665,12 @@ define void @test_vsel32uno_nnan(half* %lhs_ptr, half* %rhs_ptr, half* %a_ptr, h
; CHECK-NEXT: vselvs.f16 s0, s0, s2
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
- %a = load volatile half, half* %a_ptr
- %b = load volatile half, half* %b_ptr
- %lhs = load volatile half, half* %lhs_ptr
- %rhs = load volatile half, half* %rhs_ptr
+ %a = load volatile half, ptr %a_ptr
+ %b = load volatile half, ptr %b_ptr
+ %lhs = load volatile half, ptr %lhs_ptr
+ %rhs = load volatile half, ptr %rhs_ptr
%tst1 = fcmp nnan uno half %lhs, %rhs
%val1 = select i1 %tst1, half %a, half %b
- store half %val1, half* @varhalf
+ store half %val1, ptr @varhalf
ret void
}
diff --git a/llvm/test/CodeGen/ARM/vsel.ll b/llvm/test/CodeGen/ARM/vsel.ll
index 33d16ad45e242..272e3361bd470 100644
--- a/llvm/test/CodeGen/ARM/vsel.ll
+++ b/llvm/test/CodeGen/ARM/vsel.ll
@@ -5,7 +5,7 @@ define void @test_vsel32sgt(i32 %lhs32, i32 %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32sgt
%tst1 = icmp sgt i32 %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: cmp r0, r1
; CHECK: vselgt.f32 s0, s0, s1
ret void
@@ -14,7 +14,7 @@ define void @test_vsel64sgt(i32 %lhs32, i32 %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64sgt
%tst1 = icmp sgt i32 %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: cmp r0, r1
; CHECK: vselgt.f64 d16, d0, d1
ret void
@@ -23,7 +23,7 @@ define void @test_vsel32sge(i32 %lhs32, i32 %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32sge
%tst1 = icmp sge i32 %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: cmp r0, r1
; CHECK: vselge.f32 s0, s0, s1
ret void
@@ -32,7 +32,7 @@ define void @test_vsel64sge(i32 %lhs32, i32 %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64sge
%tst1 = icmp sge i32 %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: cmp r0, r1
; CHECK: vselge.f64 d16, d0, d1
ret void
@@ -41,7 +41,7 @@ define void @test_vsel32eq(i32 %lhs32, i32 %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32eq
%tst1 = icmp eq i32 %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: cmp r0, r1
; CHECK: vseleq.f32 s0, s0, s1
ret void
@@ -50,7 +50,7 @@ define void @test_vsel64eq(i32 %lhs32, i32 %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64eq
%tst1 = icmp eq i32 %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: cmp r0, r1
; CHECK: vseleq.f64 d16, d0, d1
ret void
@@ -59,7 +59,7 @@ define void @test_vsel32slt(i32 %lhs32, i32 %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32slt
%tst1 = icmp slt i32 %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: cmp r0, r1
; CHECK: vselge.f32 s0, s1, s0
ret void
@@ -68,7 +68,7 @@ define void @test_vsel64slt(i32 %lhs32, i32 %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64slt
%tst1 = icmp slt i32 %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: cmp r0, r1
; CHECK: vselge.f64 d16, d1, d0
ret void
@@ -77,7 +77,7 @@ define void @test_vsel32sle(i32 %lhs32, i32 %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32sle
%tst1 = icmp sle i32 %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: cmp r0, r1
; CHECK: vselgt.f32 s0, s1, s0
ret void
@@ -86,7 +86,7 @@ define void @test_vsel64sle(i32 %lhs32, i32 %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64sle
%tst1 = icmp sle i32 %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: cmp r0, r1
; CHECK: vselgt.f64 d16, d1, d0
ret void
@@ -95,7 +95,7 @@ define void @test_vsel32ogt(float %lhs32, float %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32ogt
%tst1 = fcmp ogt float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vselgt.f32 s0, s2, s3
ret void
@@ -104,7 +104,7 @@ define void @test_vsel64ogt(float %lhs32, float %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64ogt
%tst1 = fcmp ogt float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vselgt.f64 d16, d1, d2
ret void
@@ -113,7 +113,7 @@ define void @test_vsel32oge(float %lhs32, float %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32oge
%tst1 = fcmp oge float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vselge.f32 s0, s2, s3
ret void
@@ -122,7 +122,7 @@ define void @test_vsel64oge(float %lhs32, float %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64oge
%tst1 = fcmp oge float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vselge.f64 d16, d1, d2
ret void
@@ -131,7 +131,7 @@ define void @test_vsel32oeq(float %lhs32, float %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32oeq
%tst1 = fcmp oeq float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vseleq.f32 s0, s2, s3
ret void
@@ -140,7 +140,7 @@ define void @test_vsel64oeq(float %lhs32, float %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64oeq
%tst1 = fcmp oeq float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vseleq.f64 d16, d1, d2
ret void
@@ -149,7 +149,7 @@ define void @test_vsel32ugt(float %lhs32, float %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32ugt
%tst1 = fcmp ugt float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s1, s0
; CHECK: vselge.f32 s0, s3, s2
ret void
@@ -158,7 +158,7 @@ define void @test_vsel64ugt(float %lhs32, float %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64ugt
%tst1 = fcmp ugt float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s1, s0
; CHECK: vselge.f64 d16, d2, d1
ret void
@@ -167,7 +167,7 @@ define void @test_vsel32uge(float %lhs32, float %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32uge
%tst1 = fcmp uge float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s1, s0
; CHECK: vselgt.f32 s0, s3, s2
ret void
@@ -176,7 +176,7 @@ define void @test_vsel64uge(float %lhs32, float %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64uge
%tst1 = fcmp uge float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s1, s0
; CHECK: vselgt.f64 d16, d2, d1
ret void
@@ -185,7 +185,7 @@ define void @test_vsel32olt(float %lhs32, float %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32olt
%tst1 = fcmp olt float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s1, s0
; CHECK: vselgt.f32 s0, s2, s3
ret void
@@ -194,7 +194,7 @@ define void @test_vsel64olt(float %lhs32, float %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64olt
%tst1 = fcmp olt float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s1, s0
; CHECK: vselgt.f64 d16, d1, d2
ret void
@@ -203,7 +203,7 @@ define void @test_vsel32ult(float %lhs32, float %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32ult
%tst1 = fcmp ult float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vselge.f32 s0, s3, s2
ret void
@@ -212,7 +212,7 @@ define void @test_vsel64ult(float %lhs32, float %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64ult
%tst1 = fcmp ult float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vselge.f64 d16, d2, d1
ret void
@@ -221,7 +221,7 @@ define void @test_vsel32ole(float %lhs32, float %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32ole
%tst1 = fcmp ole float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s1, s0
; CHECK: vselge.f32 s0, s2, s3
ret void
@@ -230,7 +230,7 @@ define void @test_vsel64ole(float %lhs32, float %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64ole
%tst1 = fcmp ole float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s1, s0
; CHECK: vselge.f64 d16, d1, d2
ret void
@@ -239,7 +239,7 @@ define void @test_vsel32ule(float %lhs32, float %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32ule
%tst1 = fcmp ule float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vselgt.f32 s0, s3, s2
ret void
@@ -248,7 +248,7 @@ define void @test_vsel64ule(float %lhs32, float %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64ule
%tst1 = fcmp ule float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vselgt.f64 d16, d2, d1
ret void
@@ -257,7 +257,7 @@ define void @test_vsel32ord(float %lhs32, float %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32ord
%tst1 = fcmp ord float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vselvs.f32 s0, s3, s2
ret void
@@ -266,7 +266,7 @@ define void @test_vsel64ord(float %lhs32, float %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64ord
%tst1 = fcmp ord float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vselvs.f64 d16, d2, d1
ret void
@@ -275,7 +275,7 @@ define void @test_vsel32une(float %lhs32, float %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32une
%tst1 = fcmp une float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vseleq.f32 s0, s3, s2
ret void
@@ -284,7 +284,7 @@ define void @test_vsel64une(float %lhs32, float %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64une
%tst1 = fcmp une float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vseleq.f64 d16, d2, d1
ret void
@@ -293,7 +293,7 @@ define void @test_vsel32uno(float %lhs32, float %rhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel32uno
%tst1 = fcmp uno float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vselvs.f32 s0, s2, s3
ret void
@@ -302,7 +302,7 @@ define void @test_vsel64uno(float %lhs32, float %rhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel64uno
%tst1 = fcmp uno float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vselvs.f64 d16, d1, d2
ret void
@@ -312,7 +312,7 @@ define void @test_vsel32ogt_nnan(float %lhs32, float %rhs32, float %a, float %b)
; CHECK-LABEL: test_vsel32ogt_nnan
%tst1 = fcmp nnan ogt float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vselgt.f32 s0, s2, s3
ret void
@@ -321,7 +321,7 @@ define void @test_vsel64ogt_nnan(float %lhs32, float %rhs32, double %a, double %
; CHECK-LABEL: test_vsel64ogt_nnan
%tst1 = fcmp nnan ogt float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vselgt.f64 d16, d1, d2
ret void
@@ -330,7 +330,7 @@ define void @test_vsel32oge_nnan(float %lhs32, float %rhs32, float %a, float %b)
; CHECK-LABEL: test_vsel32oge_nnan
%tst1 = fcmp nnan oge float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vselge.f32 s0, s2, s3
ret void
@@ -339,7 +339,7 @@ define void @test_vsel64oge_nnan(float %lhs32, float %rhs32, double %a, double %
; CHECK-LABEL: test_vsel64oge_nnan
%tst1 = fcmp nnan oge float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vselge.f64 d16, d1, d2
ret void
@@ -348,7 +348,7 @@ define void @test_vsel32oeq_nnan(float %lhs32, float %rhs32, float %a, float %b)
; CHECK-LABEL: test_vsel32oeq_nnan
%tst1 = fcmp nnan oeq float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vseleq.f32 s0, s2, s3
ret void
@@ -357,7 +357,7 @@ define void @test_vsel64oeq_nnan(float %lhs32, float %rhs32, double %a, double %
; CHECK-LABEL: test_vsel64oeq_nnan
%tst1 = fcmp nnan oeq float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vseleq.f64 d16, d1, d2
ret void
@@ -366,7 +366,7 @@ define void @test_vsel32ugt_nnan(float %lhs32, float %rhs32, float %a, float %b)
; CHECK-LABEL: test_vsel32ugt_nnan
%tst1 = fcmp nnan ugt float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vselgt.f32 s0, s2, s3
ret void
@@ -375,7 +375,7 @@ define void @test_vsel64ugt_nnan(float %lhs32, float %rhs32, double %a, double %
; CHECK-LABEL: test_vsel64ugt_nnan
%tst1 = fcmp nnan ugt float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vselgt.f64 d16, d1, d2
ret void
@@ -384,7 +384,7 @@ define void @test_vsel32uge_nnan(float %lhs32, float %rhs32, float %a, float %b)
; CHECK-LABEL: test_vsel32uge_nnan
%tst1 = fcmp nnan uge float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vselge.f32 s0, s2, s3
ret void
@@ -393,7 +393,7 @@ define void @test_vsel64uge_nnan(float %lhs32, float %rhs32, double %a, double %
; CHECK-LABEL: test_vsel64uge_nnan
%tst1 = fcmp nnan uge float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vselge.f64 d16, d1, d2
ret void
@@ -402,7 +402,7 @@ define void @test_vsel32olt_nnan(float %lhs32, float %rhs32, float %a, float %b)
; CHECK-LABEL: test_vsel32olt_nnan
%tst1 = fcmp nnan olt float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s1, s0
; CHECK: vselgt.f32 s0, s2, s3
ret void
@@ -411,7 +411,7 @@ define void @test_vsel64olt_nnan(float %lhs32, float %rhs32, double %a, double %
; CHECK-LABEL: test_vsel64olt_nnan
%tst1 = fcmp nnan olt float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s1, s0
; CHECK: vselgt.f64 d16, d1, d2
ret void
@@ -420,7 +420,7 @@ define void @test_vsel32ult_nnan(float %lhs32, float %rhs32, float %a, float %b)
; CHECK-LABEL: test_vsel32ult_nnan
%tst1 = fcmp nnan ult float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s1, s0
; CHECK: vselgt.f32 s0, s2, s3
ret void
@@ -429,7 +429,7 @@ define void @test_vsel64ult_nnan(float %lhs32, float %rhs32, double %a, double %
; CHECK-LABEL: test_vsel64ult_nnan
%tst1 = fcmp nnan ult float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s1, s0
; CHECK: vselgt.f64 d16, d1, d2
ret void
@@ -438,7 +438,7 @@ define void @test_vsel32ole_nnan(float %lhs32, float %rhs32, float %a, float %b)
; CHECK-LABEL: test_vsel32ole_nnan
%tst1 = fcmp nnan ole float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s1, s0
; CHECK: vselge.f32 s0, s2, s3
ret void
@@ -447,7 +447,7 @@ define void @test_vsel64ole_nnan(float %lhs32, float %rhs32, double %a, double %
; CHECK-LABEL: test_vsel64ole_nnan
%tst1 = fcmp nnan ole float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s1, s0
; CHECK: vselge.f64 d16, d1, d2
ret void
@@ -456,7 +456,7 @@ define void @test_vsel32ule_nnan(float %lhs32, float %rhs32, float %a, float %b)
; CHECK-LABEL: test_vsel32ule_nnan
%tst1 = fcmp nnan ule float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s1, s0
; CHECK: vselge.f32 s0, s2, s3
ret void
@@ -465,7 +465,7 @@ define void @test_vsel64ule_nnan(float %lhs32, float %rhs32, double %a, double %
; CHECK-LABEL: test_vsel64ule_nnan
%tst1 = fcmp nnan ule float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s1, s0
; CHECK: vselge.f64 d16, d1, d2
ret void
@@ -474,7 +474,7 @@ define void @test_vsel32ord_nnan(float %lhs32, float %rhs32, float %a, float %b)
; CHECK-LABEL: test_vsel32ord_nnan
%tst1 = fcmp nnan ord float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vselvs.f32 s0, s3, s2
ret void
@@ -483,7 +483,7 @@ define void @test_vsel64ord_nnan(float %lhs32, float %rhs32, double %a, double %
; CHECK-LABEL: test_vsel64ord_nnan
%tst1 = fcmp nnan ord float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vselvs.f64 d16, d2, d1
ret void
@@ -492,7 +492,7 @@ define void @test_vsel32une_nnan(float %lhs32, float %rhs32, float %a, float %b)
; CHECK-LABEL: test_vsel32une_nnan
%tst1 = fcmp nnan une float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vseleq.f32 s0, s3, s2
ret void
@@ -501,7 +501,7 @@ define void @test_vsel64une_nnan(float %lhs32, float %rhs32, double %a, double %
; CHECK-LABEL: test_vsel64une_nnan
%tst1 = fcmp nnan une float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vseleq.f64 d16, d2, d1
ret void
@@ -510,7 +510,7 @@ define void @test_vsel32uno_nnan(float %lhs32, float %rhs32, float %a, float %b)
; CHECK-LABEL: test_vsel32uno_nnan
%tst1 = fcmp nnan uno float %lhs32, %rhs32
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: vcmp.f32 s0, s1
; CHECK: vselvs.f32 s0, s2, s3
ret void
@@ -519,7 +519,7 @@ define void @test_vsel64uno_nnan(float %lhs32, float %rhs32, double %a, double %
; CHECK-LABEL: test_vsel64uno_nnan
%tst1 = fcmp nnan uno float %lhs32, %rhs32
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: vcmp.f32 s0, s1
; CHECK: vselvs.f64 d16, d1, d2
ret void
@@ -529,7 +529,7 @@ define void @test_vsel_ltzero(i32 %lhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel_ltzero
%tst1 = icmp slt i32 %lhs32, 0
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: cmp r0, #0
; CHECK: vselge.f32 s0, s1, s0
ret void
@@ -539,7 +539,7 @@ define void @test_vsel_lezero(i32 %lhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel_lezero
%tst1 = icmp sle i32 %lhs32, 0
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: cmp r0, #1
; CHECK: vselge.f32 s0, s1, s0
ret void
@@ -549,7 +549,7 @@ define void @test_vsel_gtzero(i32 %lhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel_gtzero
%tst1 = icmp sgt i32 %lhs32, 0
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: cmp r0, #0
; CHECK: vselgt.f32 s0, s0, s1
ret void
@@ -559,7 +559,7 @@ define void @test_vsel_gezero(i32 %lhs32, float %a, float %b) {
; CHECK-LABEL: test_vsel_gezero
%tst1 = icmp sge i32 %lhs32, 0
%val1 = select i1 %tst1, float %a, float %b
- store float %val1, float* @varfloat
+ store float %val1, ptr @varfloat
; CHECK: cmn r0, #1
; CHECK: vselgt.f32 s0, s0, s1
ret void
@@ -569,7 +569,7 @@ define void @test_vsel_ltzero64(i32 %lhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel_ltzero
%tst1 = icmp slt i32 %lhs32, 0
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: cmp r0, #0
; CHECK: vselge.f64 d16, d1, d0
ret void
@@ -579,7 +579,7 @@ define void @test_vsel_lezero64(i32 %lhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel_lezero
%tst1 = icmp sle i32 %lhs32, 0
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: cmp r0, #1
; CHECK: vselge.f64 d16, d1, d0
ret void
@@ -589,7 +589,7 @@ define void @test_vsel_gtzero64(i32 %lhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel_gtzero
%tst1 = icmp sgt i32 %lhs32, 0
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: cmp r0, #0
; CHECK: vselgt.f64 d16, d0, d1
ret void
@@ -599,7 +599,7 @@ define void @test_vsel_gezero64(i32 %lhs32, double %a, double %b) {
; CHECK-LABEL: test_vsel_gezero
%tst1 = icmp sge i32 %lhs32, 0
%val1 = select i1 %tst1, double %a, double %b
- store double %val1, double* @vardouble
+ store double %val1, ptr @vardouble
; CHECK: cmn r0, #1
; CHECK: vselgt.f64 d16, d0, d1
ret void
diff --git a/llvm/test/CodeGen/ARM/vselect_imax.ll b/llvm/test/CodeGen/ARM/vselect_imax.ll
index 11e7f86a06071..37f511fcc68cc 100644
--- a/llvm/test/CodeGen/ARM/vselect_imax.ll
+++ b/llvm/test/CodeGen/ARM/vselect_imax.ll
@@ -2,21 +2,21 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
; Make sure that ARM backend with NEON handles vselect.
-define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) {
+define void @vmax_v4i32(ptr %m, <4 x i32> %a, <4 x i32> %b) {
; CHECK: vmax.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
%cmpres = icmp sgt <4 x i32> %a, %b
%maxres = select <4 x i1> %cmpres, <4 x i32> %a, <4 x i32> %b
- store <4 x i32> %maxres, <4 x i32>* %m
+ store <4 x i32> %maxres, ptr %m
ret void
}
%T0_10 = type <16 x i16>
%T1_10 = type <16 x i1>
; CHECK-LABEL: func_blend10:
-define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2,
- %T1_10* %blend, %T0_10* %storeaddr) {
- %v0 = load %T0_10, %T0_10* %loadaddr
- %v1 = load %T0_10, %T0_10* %loadaddr2
+define void @func_blend10(ptr %loadaddr, ptr %loadaddr2,
+ ptr %blend, ptr %storeaddr) {
+ %v0 = load %T0_10, ptr %loadaddr
+ %v1 = load %T0_10, ptr %loadaddr2
%c = icmp slt %T0_10 %v0, %v1
; CHECK: vmin.s16
; CHECK: vmin.s16
@@ -24,16 +24,16 @@ define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2,
; COST: cost of 0 {{.*}} icmp
; COST: cost of 4 {{.*}} select
%r = select %T1_10 %c, %T0_10 %v0, %T0_10 %v1
- store %T0_10 %r, %T0_10* %storeaddr
+ store %T0_10 %r, ptr %storeaddr
ret void
}
%T0_14 = type <8 x i32>
%T1_14 = type <8 x i1>
; CHECK-LABEL: func_blend14:
-define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2,
- %T1_14* %blend, %T0_14* %storeaddr) {
- %v0 = load %T0_14, %T0_14* %loadaddr
- %v1 = load %T0_14, %T0_14* %loadaddr2
+define void @func_blend14(ptr %loadaddr, ptr %loadaddr2,
+ ptr %blend, ptr %storeaddr) {
+ %v0 = load %T0_14, ptr %loadaddr
+ %v1 = load %T0_14, ptr %loadaddr2
%c = icmp slt %T0_14 %v0, %v1
; CHECK: vmin.s32
; CHECK: vmin.s32
@@ -41,24 +41,24 @@ define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2,
; COST: cost of 0 {{.*}} icmp
; COST: cost of 4 {{.*}} select
%r = select %T1_14 %c, %T0_14 %v0, %T0_14 %v1
- store %T0_14 %r, %T0_14* %storeaddr
+ store %T0_14 %r, ptr %storeaddr
ret void
}
%T0_15 = type <16 x i32>
%T1_15 = type <16 x i1>
; CHECK-LABEL: func_blend15:
-define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2,
- %T1_15* %blend, %T0_15* %storeaddr) {
+define void @func_blend15(ptr %loadaddr, ptr %loadaddr2,
+ ptr %blend, ptr %storeaddr) {
; CHECK: vmin.s32
; CHECK: vmin.s32
- %v0 = load %T0_15, %T0_15* %loadaddr
- %v1 = load %T0_15, %T0_15* %loadaddr2
+ %v0 = load %T0_15, ptr %loadaddr
+ %v1 = load %T0_15, ptr %loadaddr2
%c = icmp slt %T0_15 %v0, %v1
; COST: func_blend15
; COST: cost of 0 {{.*}} icmp
; COST: cost of 8 {{.*}} select
%r = select %T1_15 %c, %T0_15 %v0, %T0_15 %v1
- store %T0_15 %r, %T0_15* %storeaddr
+ store %T0_15 %r, ptr %storeaddr
ret void
}
@@ -66,8 +66,8 @@ define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2,
; lowering we also need to adjust the cost.
%T0_18 = type <4 x i64>
%T1_18 = type <4 x i1>
-define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2,
- %T1_18* %blend, %T0_18* %storeaddr) {
+define void @func_blend18(ptr %loadaddr, ptr %loadaddr2,
+ ptr %blend, ptr %storeaddr) {
; CHECK-LABEL: func_blend18:
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
@@ -118,20 +118,20 @@ define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2,
; CHECK-NEXT: vst1.64 {d18, d19}, [r3:128]
; CHECK-NEXT: pop {r4, r5, r6, r7, r11, lr}
; CHECK-NEXT: mov pc, lr
- %v0 = load %T0_18, %T0_18* %loadaddr
- %v1 = load %T0_18, %T0_18* %loadaddr2
+ %v0 = load %T0_18, ptr %loadaddr
+ %v1 = load %T0_18, ptr %loadaddr2
%c = icmp slt %T0_18 %v0, %v1
; COST: func_blend18
; COST: cost of 0 {{.*}} icmp
; COST: cost of 21 {{.*}} select
%r = select %T1_18 %c, %T0_18 %v0, %T0_18 %v1
- store %T0_18 %r, %T0_18* %storeaddr
+ store %T0_18 %r, ptr %storeaddr
ret void
}
%T0_19 = type <8 x i64>
%T1_19 = type <8 x i1>
-define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2,
- %T1_19* %blend, %T0_19* %storeaddr) {
+define void @func_blend19(ptr %loadaddr, ptr %loadaddr2,
+ ptr %blend, ptr %storeaddr) {
; CHECK-LABEL: func_blend19:
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, lr}
@@ -226,20 +226,20 @@ define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2,
; CHECK-NEXT: vst1.64 {d16, d17}, [r3:128]
; CHECK-NEXT: pop {r4, r5, r6, lr}
; CHECK-NEXT: mov pc, lr
- %v0 = load %T0_19, %T0_19* %loadaddr
- %v1 = load %T0_19, %T0_19* %loadaddr2
+ %v0 = load %T0_19, ptr %loadaddr
+ %v1 = load %T0_19, ptr %loadaddr2
%c = icmp slt %T0_19 %v0, %v1
; COST: func_blend19
; COST: cost of 0 {{.*}} icmp
; COST: cost of 54 {{.*}} select
%r = select %T1_19 %c, %T0_19 %v0, %T0_19 %v1
- store %T0_19 %r, %T0_19* %storeaddr
+ store %T0_19 %r, ptr %storeaddr
ret void
}
%T0_20 = type <16 x i64>
%T1_20 = type <16 x i1>
-define void @func_blend20(%T0_20* %loadaddr, %T0_20* %loadaddr2,
- %T1_20* %blend, %T0_20* %storeaddr) {
+define void @func_blend20(ptr %loadaddr, ptr %loadaddr2,
+ ptr %blend, ptr %storeaddr) {
; CHECK-LABEL: func_blend20:
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
@@ -435,13 +435,13 @@ define void @func_blend20(%T0_20* %loadaddr, %T0_20* %loadaddr2,
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, lr}
; CHECK-NEXT: mov pc, lr
- %v0 = load %T0_20, %T0_20* %loadaddr
- %v1 = load %T0_20, %T0_20* %loadaddr2
+ %v0 = load %T0_20, ptr %loadaddr
+ %v1 = load %T0_20, ptr %loadaddr2
%c = icmp slt %T0_20 %v0, %v1
; COST: func_blend20
; COST: cost of 0 {{.*}} icmp
; COST: cost of 108 {{.*}} select
%r = select %T1_20 %c, %T0_20 %v0, %T0_20 %v1
- store %T0_20 %r, %T0_20* %storeaddr
+ store %T0_20 %r, ptr %storeaddr
ret void
}
diff --git a/llvm/test/CodeGen/ARM/vshift.ll b/llvm/test/CodeGen/ARM/vshift.ll
index 31e4cb05dd207..ac732ccceba8f 100644
--- a/llvm/test/CodeGen/ARM/vshift.ll
+++ b/llvm/test/CodeGen/ARM/vshift.ll
@@ -1,281 +1,281 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vshls8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshls8:
;CHECK: vshl.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shl <8 x i8> %tmp1, %tmp2
ret <8 x i8> %tmp3
}
-define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vshls16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshls16:
;CHECK: vshl.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = shl <4 x i16> %tmp1, %tmp2
ret <4 x i16> %tmp3
}
-define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vshls32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshls32:
;CHECK: vshl.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = shl <2 x i32> %tmp1, %tmp2
ret <2 x i32> %tmp3
}
-define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vshls64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshls64:
;CHECK: vshl.u64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = shl <1 x i64> %tmp1, %tmp2
ret <1 x i64> %tmp3
}
-define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vshli8(ptr %A) nounwind {
;CHECK-LABEL: vshli8:
;CHECK: vshl.i8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
ret <8 x i8> %tmp2
}
-define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vshli16(ptr %A) nounwind {
;CHECK-LABEL: vshli16:
;CHECK: vshl.i16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = shl <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >
ret <4 x i16> %tmp2
}
-define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vshli32(ptr %A) nounwind {
;CHECK-LABEL: vshli32:
;CHECK: vshl.i32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = shl <2 x i32> %tmp1, < i32 31, i32 31 >
ret <2 x i32> %tmp2
}
-define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
+define <1 x i64> @vshli64(ptr %A) nounwind {
;CHECK-LABEL: vshli64:
;CHECK: vshl.i64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
+ %tmp1 = load <1 x i64>, ptr %A
%tmp2 = shl <1 x i64> %tmp1, < i64 63 >
ret <1 x i64> %tmp2
}
-define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vshlQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlQs8:
;CHECK: vshl.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = shl <16 x i8> %tmp1, %tmp2
ret <16 x i8> %tmp3
}
-define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vshlQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlQs16:
;CHECK: vshl.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = shl <8 x i16> %tmp1, %tmp2
ret <8 x i16> %tmp3
}
-define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vshlQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlQs32:
;CHECK: vshl.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = shl <4 x i32> %tmp1, %tmp2
ret <4 x i32> %tmp3
}
-define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vshlQs64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlQs64:
;CHECK: vshl.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = shl <2 x i64> %tmp1, %tmp2
ret <2 x i64> %tmp3
}
-define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vshlQi8(ptr %A) nounwind {
;CHECK-LABEL: vshlQi8:
;CHECK: vshl.i8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = shl <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
ret <16 x i8> %tmp2
}
-define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vshlQi16(ptr %A) nounwind {
;CHECK-LABEL: vshlQi16:
;CHECK: vshl.i16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = shl <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
ret <8 x i16> %tmp2
}
-define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vshlQi32(ptr %A) nounwind {
;CHECK-LABEL: vshlQi32:
;CHECK: vshl.i32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = shl <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >
ret <4 x i32> %tmp2
}
-define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
+define <2 x i64> @vshlQi64(ptr %A) nounwind {
;CHECK-LABEL: vshlQi64:
;CHECK: vshl.i64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 >
ret <2 x i64> %tmp2
}
-define <8 x i8> @vlshru8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vlshru8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vlshru8:
;CHECK: vneg.s8
;CHECK: vshl.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = lshr <8 x i8> %tmp1, %tmp2
ret <8 x i8> %tmp3
}
-define <4 x i16> @vlshru16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vlshru16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vlshru16:
;CHECK: vneg.s16
;CHECK: vshl.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = lshr <4 x i16> %tmp1, %tmp2
ret <4 x i16> %tmp3
}
-define <2 x i32> @vlshru32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vlshru32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vlshru32:
;CHECK: vneg.s32
;CHECK: vshl.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = lshr <2 x i32> %tmp1, %tmp2
ret <2 x i32> %tmp3
}
-define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vlshru64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vlshru64:
;CHECK: vsub.i64
;CHECK: vshl.u64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = lshr <1 x i64> %tmp1, %tmp2
ret <1 x i64> %tmp3
}
-define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vlshri8(ptr %A) nounwind {
;CHECK-LABEL: vlshri8:
;CHECK: vshr.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = lshr <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
ret <8 x i8> %tmp2
}
-define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vlshri16(ptr %A) nounwind {
;CHECK-LABEL: vlshri16:
;CHECK: vshr.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = lshr <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >
ret <4 x i16> %tmp2
}
-define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vlshri32(ptr %A) nounwind {
;CHECK-LABEL: vlshri32:
;CHECK: vshr.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = lshr <2 x i32> %tmp1, < i32 31, i32 31 >
ret <2 x i32> %tmp2
}
-define <1 x i64> @vlshri64(<1 x i64>* %A) nounwind {
+define <1 x i64> @vlshri64(ptr %A) nounwind {
;CHECK-LABEL: vlshri64:
;CHECK: vshr.u64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
+ %tmp1 = load <1 x i64>, ptr %A
%tmp2 = lshr <1 x i64> %tmp1, < i64 63 >
ret <1 x i64> %tmp2
}
-define <16 x i8> @vlshrQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vlshrQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vlshrQu8:
;CHECK: vneg.s8
;CHECK: vshl.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = lshr <16 x i8> %tmp1, %tmp2
ret <16 x i8> %tmp3
}
-define <8 x i16> @vlshrQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vlshrQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vlshrQu16:
;CHECK: vneg.s16
;CHECK: vshl.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = lshr <8 x i16> %tmp1, %tmp2
ret <8 x i16> %tmp3
}
-define <4 x i32> @vlshrQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vlshrQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vlshrQu32:
;CHECK: vneg.s32
;CHECK: vshl.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = lshr <4 x i32> %tmp1, %tmp2
ret <4 x i32> %tmp3
}
-define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vlshrQu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vlshrQu64:
;CHECK: vsub.i64
;CHECK: vshl.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = lshr <2 x i64> %tmp1, %tmp2
ret <2 x i64> %tmp3
}
-define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vlshrQi8(ptr %A) nounwind {
;CHECK-LABEL: vlshrQi8:
;CHECK: vshr.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = lshr <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
ret <16 x i8> %tmp2
}
-define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vlshrQi16(ptr %A) nounwind {
;CHECK-LABEL: vlshrQi16:
;CHECK: vshr.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = lshr <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
ret <8 x i16> %tmp2
}
-define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vlshrQi32(ptr %A) nounwind {
;CHECK-LABEL: vlshrQi32:
;CHECK: vshr.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = lshr <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >
ret <4 x i32> %tmp2
}
-define <2 x i64> @vlshrQi64(<2 x i64>* %A) nounwind {
+define <2 x i64> @vlshrQi64(ptr %A) nounwind {
;CHECK-LABEL: vlshrQi64:
;CHECK: vshr.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = lshr <2 x i64> %tmp1, < i64 63, i64 63 >
ret <2 x i64> %tmp2
}
@@ -287,146 +287,146 @@ entry:
ret <2 x i64> %shr
}
-define <8 x i8> @vashrs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vashrs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vashrs8:
;CHECK: vneg.s8
;CHECK: vshl.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = ashr <8 x i8> %tmp1, %tmp2
ret <8 x i8> %tmp3
}
-define <4 x i16> @vashrs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vashrs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vashrs16:
;CHECK: vneg.s16
;CHECK: vshl.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = ashr <4 x i16> %tmp1, %tmp2
ret <4 x i16> %tmp3
}
-define <2 x i32> @vashrs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vashrs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vashrs32:
;CHECK: vneg.s32
;CHECK: vshl.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = ashr <2 x i32> %tmp1, %tmp2
ret <2 x i32> %tmp3
}
-define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vashrs64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vashrs64:
;CHECK: vsub.i64
;CHECK: vshl.s64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = ashr <1 x i64> %tmp1, %tmp2
ret <1 x i64> %tmp3
}
-define <8 x i8> @vashri8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vashri8(ptr %A) nounwind {
;CHECK-LABEL: vashri8:
;CHECK: vshr.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = ashr <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
ret <8 x i8> %tmp2
}
-define <4 x i16> @vashri16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vashri16(ptr %A) nounwind {
;CHECK-LABEL: vashri16:
;CHECK: vshr.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = ashr <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >
ret <4 x i16> %tmp2
}
-define <2 x i32> @vashri32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vashri32(ptr %A) nounwind {
;CHECK-LABEL: vashri32:
;CHECK: vshr.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = ashr <2 x i32> %tmp1, < i32 31, i32 31 >
ret <2 x i32> %tmp2
}
-define <1 x i64> @vashri64(<1 x i64>* %A) nounwind {
+define <1 x i64> @vashri64(ptr %A) nounwind {
;CHECK-LABEL: vashri64:
;CHECK: vshr.s64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
+ %tmp1 = load <1 x i64>, ptr %A
%tmp2 = ashr <1 x i64> %tmp1, < i64 63 >
ret <1 x i64> %tmp2
}
-define <16 x i8> @vashrQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vashrQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vashrQs8:
;CHECK: vneg.s8
;CHECK: vshl.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = ashr <16 x i8> %tmp1, %tmp2
ret <16 x i8> %tmp3
}
-define <8 x i16> @vashrQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vashrQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vashrQs16:
;CHECK: vneg.s16
;CHECK: vshl.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = ashr <8 x i16> %tmp1, %tmp2
ret <8 x i16> %tmp3
}
-define <4 x i32> @vashrQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vashrQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vashrQs32:
;CHECK: vneg.s32
;CHECK: vshl.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = ashr <4 x i32> %tmp1, %tmp2
ret <4 x i32> %tmp3
}
-define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vashrQs64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vashrQs64:
;CHECK: vsub.i64
;CHECK: vshl.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = ashr <2 x i64> %tmp1, %tmp2
ret <2 x i64> %tmp3
}
-define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vashrQi8(ptr %A) nounwind {
;CHECK-LABEL: vashrQi8:
;CHECK: vshr.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = ashr <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
ret <16 x i8> %tmp2
}
-define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vashrQi16(ptr %A) nounwind {
;CHECK-LABEL: vashrQi16:
;CHECK: vshr.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = ashr <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
ret <8 x i16> %tmp2
}
-define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vashrQi32(ptr %A) nounwind {
;CHECK-LABEL: vashrQi32:
;CHECK: vshr.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = ashr <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >
ret <4 x i32> %tmp2
}
-define <2 x i64> @vashrQi64(<2 x i64>* %A) nounwind {
+define <2 x i64> @vashrQi64(ptr %A) nounwind {
;CHECK-LABEL: vashrQi64:
;CHECK: vshr.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = ashr <2 x i64> %tmp1, < i64 63, i64 63 >
ret <2 x i64> %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/vshiftins.ll b/llvm/test/CodeGen/ARM/vshiftins.ll
index 29487378317d8..306db31d84f15 100644
--- a/llvm/test/CodeGen/ARM/vshiftins.ll
+++ b/llvm/test/CodeGen/ARM/vshiftins.ll
@@ -1,145 +1,145 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vsli8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsli8:
;CHECK: vsli.8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vsli16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsli16:
;CHECK: vsli.16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vsli32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsli32:
;CHECK: vsli.32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 31, i32 31 >)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vsli64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsli64:
;CHECK: vsli.64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 63 >)
ret <1 x i64> %tmp3
}
-define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vsliQ8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsliQ8:
;CHECK: vsli.8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vsliQ16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsliQ16:
;CHECK: vsli.16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vsliQ32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsliQ32:
;CHECK: vsli.32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vsliQ64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsliQ64:
;CHECK: vsli.64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 63, i64 63 >)
ret <2 x i64> %tmp3
}
-define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vsri8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsri8:
;CHECK: vsri.8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vsri16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsri16:
;CHECK: vsri.16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vsri32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsri32:
;CHECK: vsri.32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vsri64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsri64:
;CHECK: vsri.64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 -64 >)
ret <1 x i64> %tmp3
}
-define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vsriQ8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsriQ8:
;CHECK: vsri.8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vsriQ16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsriQ16:
;CHECK: vsri.16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vsriQ32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsriQ32:
;CHECK: vsri.32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vsriQ64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsriQ64:
;CHECK: vsri.64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
ret <2 x i64> %tmp3
}
diff --git a/llvm/test/CodeGen/ARM/vshl.ll b/llvm/test/CodeGen/ARM/vshl.ll
index ef76e3d9a36cd..5314cf33b09f1 100644
--- a/llvm/test/CodeGen/ARM/vshl.ll
+++ b/llvm/test/CodeGen/ARM/vshl.ll
@@ -1,145 +1,145 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vshls8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshls8:
;CHECK: vshl.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vshls16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshls16:
;CHECK: vshl.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vshls32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshls32:
;CHECK: vshl.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vshls64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshls64:
;CHECK: vshl.s64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vshlu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlu8:
;CHECK: vshl.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vshlu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlu16:
;CHECK: vshl.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vshlu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlu32:
;CHECK: vshl.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vshlu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlu64:
;CHECK: vshl.u64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vshlQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlQs8:
;CHECK: vshl.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vshlQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlQs16:
;CHECK: vshl.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vshlQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlQs32:
;CHECK: vshl.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vshlQs64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlQs64:
;CHECK: vshl.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
-define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vshlQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlQu8:
;CHECK: vshl.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vshlQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlQu16:
;CHECK: vshl.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vshlQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlQu32:
;CHECK: vshl.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vshlQu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vshlQu64:
;CHECK: vshl.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
@@ -147,196 +147,196 @@ define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
; For left shifts by immediates, the signedness is irrelevant.
; Test a mix of both signed and unsigned intrinsics.
-define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vshli8(ptr %A) nounwind {
;CHECK-LABEL: vshli8:
;CHECK: vshl.i8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vshli16(ptr %A) nounwind {
;CHECK-LABEL: vshli16:
;CHECK: vshl.i16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vshli32(ptr %A) nounwind {
;CHECK-LABEL: vshli32:
;CHECK: vshl.i32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
ret <2 x i32> %tmp2
}
-define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
+define <1 x i64> @vshli64(ptr %A) nounwind {
;CHECK-LABEL: vshli64:
;CHECK: vshl.i64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
+ %tmp1 = load <1 x i64>, ptr %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
ret <1 x i64> %tmp2
}
-define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vshlQi8(ptr %A) nounwind {
;CHECK-LABEL: vshlQi8:
;CHECK: vshl.i8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vshlQi16(ptr %A) nounwind {
;CHECK-LABEL: vshlQi16:
;CHECK: vshl.i16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vshlQi32(ptr %A) nounwind {
;CHECK-LABEL: vshlQi32:
;CHECK: vshl.i32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
ret <4 x i32> %tmp2
}
-define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
+define <2 x i64> @vshlQi64(ptr %A) nounwind {
;CHECK-LABEL: vshlQi64:
;CHECK: vshl.i64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
ret <2 x i64> %tmp2
}
; Right shift by immediate:
-define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vshrs8(ptr %A) nounwind {
;CHECK-LABEL: vshrs8:
;CHECK: vshr.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vshrs16(ptr %A) nounwind {
;CHECK-LABEL: vshrs16:
;CHECK: vshr.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vshrs32(ptr %A) nounwind {
;CHECK-LABEL: vshrs32:
;CHECK: vshr.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
ret <2 x i32> %tmp2
}
-define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind {
+define <1 x i64> @vshrs64(ptr %A) nounwind {
;CHECK-LABEL: vshrs64:
;CHECK: vshr.s64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
+ %tmp1 = load <1 x i64>, ptr %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
ret <1 x i64> %tmp2
}
-define <8 x i8> @vshru8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vshru8(ptr %A) nounwind {
;CHECK-LABEL: vshru8:
;CHECK: vshr.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vshru16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vshru16(ptr %A) nounwind {
;CHECK-LABEL: vshru16:
;CHECK: vshr.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vshru32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vshru32(ptr %A) nounwind {
;CHECK-LABEL: vshru32:
;CHECK: vshr.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
ret <2 x i32> %tmp2
}
-define <1 x i64> @vshru64(<1 x i64>* %A) nounwind {
+define <1 x i64> @vshru64(ptr %A) nounwind {
;CHECK-LABEL: vshru64:
;CHECK: vshr.u64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
+ %tmp1 = load <1 x i64>, ptr %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
ret <1 x i64> %tmp2
}
-define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vshrQs8(ptr %A) nounwind {
;CHECK-LABEL: vshrQs8:
;CHECK: vshr.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vshrQs16(ptr %A) nounwind {
;CHECK-LABEL: vshrQs16:
;CHECK: vshr.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vshrQs32(ptr %A) nounwind {
;CHECK-LABEL: vshrQs32:
;CHECK: vshr.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
ret <4 x i32> %tmp2
}
-define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind {
+define <2 x i64> @vshrQs64(ptr %A) nounwind {
;CHECK-LABEL: vshrQs64:
;CHECK: vshr.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
ret <2 x i64> %tmp2
}
-define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vshrQu8(ptr %A) nounwind {
;CHECK-LABEL: vshrQu8:
;CHECK: vshr.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vshrQu16(ptr %A) nounwind {
;CHECK-LABEL: vshrQu16:
;CHECK: vshr.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vshrQu32(ptr %A) nounwind {
;CHECK-LABEL: vshrQu32:
;CHECK: vshr.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
ret <4 x i32> %tmp2
}
-define <2 x i64> @vshrQu64(<2 x i64>* %A) nounwind {
+define <2 x i64> @vshrQu64(ptr %A) nounwind {
;CHECK-LABEL: vshrQu64:
;CHECK: vshr.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
ret <2 x i64> %tmp2
}
@@ -361,274 +361,274 @@ declare <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind re
declare <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
-define <8 x i8> @vrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vrshls8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshls8:
;CHECK: vrshl.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vrshls16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshls16:
;CHECK: vrshl.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vrshls32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshls32:
;CHECK: vrshl.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vrshls64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshls64:
;CHECK: vrshl.s64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <8 x i8> @vrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vrshlu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshlu8:
;CHECK: vrshl.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <4 x i16> @vrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vrshlu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshlu16:
;CHECK: vrshl.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
ret <4 x i16> %tmp3
}
-define <2 x i32> @vrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vrshlu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshlu32:
;CHECK: vrshl.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
ret <2 x i32> %tmp3
}
-define <1 x i64> @vrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vrshlu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshlu64:
;CHECK: vrshl.u64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
ret <1 x i64> %tmp3
}
-define <16 x i8> @vrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vrshlQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshlQs8:
;CHECK: vrshl.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vrshlQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshlQs16:
;CHECK: vrshl.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vrshlQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshlQs32:
;CHECK: vrshl.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vrshlQs64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshlQs64:
;CHECK: vrshl.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
-define <16 x i8> @vrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vrshlQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshlQu8:
;CHECK: vrshl.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
ret <16 x i8> %tmp3
}
-define <8 x i16> @vrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vrshlQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshlQu16:
;CHECK: vrshl.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
ret <8 x i16> %tmp3
}
-define <4 x i32> @vrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vrshlQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshlQu32:
;CHECK: vrshl.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
ret <4 x i32> %tmp3
}
-define <2 x i64> @vrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vrshlQu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrshlQu64:
;CHECK: vrshl.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
ret <2 x i64> %tmp3
}
-define <8 x i8> @vrshrs8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vrshrs8(ptr %A) nounwind {
;CHECK-LABEL: vrshrs8:
;CHECK: vrshr.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vrshrs16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vrshrs16(ptr %A) nounwind {
;CHECK-LABEL: vrshrs16:
;CHECK: vrshr.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vrshrs32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vrshrs32(ptr %A) nounwind {
;CHECK-LABEL: vrshrs32:
;CHECK: vrshr.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
ret <2 x i32> %tmp2
}
-define <1 x i64> @vrshrs64(<1 x i64>* %A) nounwind {
+define <1 x i64> @vrshrs64(ptr %A) nounwind {
;CHECK-LABEL: vrshrs64:
;CHECK: vrshr.s64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
+ %tmp1 = load <1 x i64>, ptr %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
ret <1 x i64> %tmp2
}
-define <8 x i8> @vrshru8(<8 x i8>* %A) nounwind {
+define <8 x i8> @vrshru8(ptr %A) nounwind {
;CHECK-LABEL: vrshru8:
;CHECK: vrshr.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vrshru16(<4 x i16>* %A) nounwind {
+define <4 x i16> @vrshru16(ptr %A) nounwind {
;CHECK-LABEL: vrshru16:
;CHECK: vrshr.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vrshru32(<2 x i32>* %A) nounwind {
+define <2 x i32> @vrshru32(ptr %A) nounwind {
;CHECK-LABEL: vrshru32:
;CHECK: vrshr.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
ret <2 x i32> %tmp2
}
-define <1 x i64> @vrshru64(<1 x i64>* %A) nounwind {
+define <1 x i64> @vrshru64(ptr %A) nounwind {
;CHECK-LABEL: vrshru64:
;CHECK: vrshr.u64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
+ %tmp1 = load <1 x i64>, ptr %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
ret <1 x i64> %tmp2
}
-define <16 x i8> @vrshrQs8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vrshrQs8(ptr %A) nounwind {
;CHECK-LABEL: vrshrQs8:
;CHECK: vrshr.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vrshrQs16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vrshrQs16(ptr %A) nounwind {
;CHECK-LABEL: vrshrQs16:
;CHECK: vrshr.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vrshrQs32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vrshrQs32(ptr %A) nounwind {
;CHECK-LABEL: vrshrQs32:
;CHECK: vrshr.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
ret <4 x i32> %tmp2
}
-define <2 x i64> @vrshrQs64(<2 x i64>* %A) nounwind {
+define <2 x i64> @vrshrQs64(ptr %A) nounwind {
;CHECK-LABEL: vrshrQs64:
;CHECK: vrshr.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
ret <2 x i64> %tmp2
}
-define <16 x i8> @vrshrQu8(<16 x i8>* %A) nounwind {
+define <16 x i8> @vrshrQu8(ptr %A) nounwind {
;CHECK-LABEL: vrshrQu8:
;CHECK: vrshr.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp1 = load <16 x i8>, ptr %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
ret <16 x i8> %tmp2
}
-define <8 x i16> @vrshrQu16(<8 x i16>* %A) nounwind {
+define <8 x i16> @vrshrQu16(ptr %A) nounwind {
;CHECK-LABEL: vrshrQu16:
;CHECK: vrshr.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
ret <8 x i16> %tmp2
}
-define <4 x i32> @vrshrQu32(<4 x i32>* %A) nounwind {
+define <4 x i32> @vrshrQu32(ptr %A) nounwind {
;CHECK-LABEL: vrshrQu32:
;CHECK: vrshr.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
ret <4 x i32> %tmp2
}
-define <2 x i64> @vrshrQu64(<2 x i64>* %A) nounwind {
+define <2 x i64> @vrshrQu64(ptr %A) nounwind {
;CHECK-LABEL: vrshrQu64:
;CHECK: vrshr.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
ret <2 x i64> %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/vshll.ll b/llvm/test/CodeGen/ARM/vshll.ll
index 61de4fa9db8d5..461693120c3d7 100644
--- a/llvm/test/CodeGen/ARM/vshll.ll
+++ b/llvm/test/CodeGen/ARM/vshll.ll
@@ -1,54 +1,54 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind {
+define <8 x i16> @vshlls8(ptr %A) nounwind {
;CHECK-LABEL: vshlls8:
;CHECK: vshll.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%sext = sext <8 x i8> %tmp1 to <8 x i16>
%shift = shl <8 x i16> %sext, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
ret <8 x i16> %shift
}
-define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind {
+define <4 x i32> @vshlls16(ptr %A) nounwind {
;CHECK-LABEL: vshlls16:
;CHECK: vshll.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%sext = sext <4 x i16> %tmp1 to <4 x i32>
%shift = shl <4 x i32> %sext, <i32 15, i32 15, i32 15, i32 15>
ret <4 x i32> %shift
}
-define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind {
+define <2 x i64> @vshlls32(ptr %A) nounwind {
;CHECK-LABEL: vshlls32:
;CHECK: vshll.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%sext = sext <2 x i32> %tmp1 to <2 x i64>
%shift = shl <2 x i64> %sext, <i64 31, i64 31>
ret <2 x i64> %shift
}
-define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind {
+define <8 x i16> @vshllu8(ptr %A) nounwind {
;CHECK-LABEL: vshllu8:
;CHECK: vshll.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%zext = zext <8 x i8> %tmp1 to <8 x i16>
%shift = shl <8 x i16> %zext, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
ret <8 x i16> %shift
}
-define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind {
+define <4 x i32> @vshllu16(ptr %A) nounwind {
;CHECK-LABEL: vshllu16:
;CHECK: vshll.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%zext = zext <4 x i16> %tmp1 to <4 x i32>
%shift = shl <4 x i32> %zext, <i32 15, i32 15, i32 15, i32 15>
ret <4 x i32> %shift
}
-define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind {
+define <2 x i64> @vshllu32(ptr %A) nounwind {
;CHECK-LABEL: vshllu32:
;CHECK: vshll.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%zext = zext <2 x i32> %tmp1 to <2 x i64>
%shift = shl <2 x i64> %zext, <i64 31, i64 31>
ret <2 x i64> %shift
@@ -56,28 +56,28 @@ define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind {
; The following tests use the maximum shift count, so the signedness is
; irrelevant. Test both signed and unsigned versions.
-define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind {
+define <8 x i16> @vshlli8(ptr %A) nounwind {
;CHECK-LABEL: vshlli8:
;CHECK: vshll.i8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%sext = sext <8 x i8> %tmp1 to <8 x i16>
%shift = shl <8 x i16> %sext, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
ret <8 x i16> %shift
}
-define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind {
+define <4 x i32> @vshlli16(ptr %A) nounwind {
;CHECK-LABEL: vshlli16:
;CHECK: vshll.i16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%zext = zext <4 x i16> %tmp1 to <4 x i32>
%shift = shl <4 x i32> %zext, <i32 16, i32 16, i32 16, i32 16>
ret <4 x i32> %shift
}
-define <2 x i64> @vshlli32(<2 x i32>* %A) nounwind {
+define <2 x i64> @vshlli32(ptr %A) nounwind {
;CHECK-LABEL: vshlli32:
;CHECK: vshll.i32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%zext = zext <2 x i32> %tmp1 to <2 x i64>
%shift = shl <2 x i64> %zext, <i64 32, i64 32>
ret <2 x i64> %shift
@@ -85,31 +85,31 @@ define <2 x i64> @vshlli32(<2 x i32>* %A) nounwind {
; And these have a shift just out of range so separate vmovl and vshl
; instructions are needed.
-define <8 x i16> @vshllu8_bad(<8 x i8>* %A) nounwind {
+define <8 x i16> @vshllu8_bad(ptr %A) nounwind {
; CHECK-LABEL: vshllu8_bad:
; CHECK: vmovl.u8
; CHECK: vshl.i16
- %tmp1 = load <8 x i8>, <8 x i8>* %A
+ %tmp1 = load <8 x i8>, ptr %A
%zext = zext <8 x i8> %tmp1 to <8 x i16>
%shift = shl <8 x i16> %zext, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
ret <8 x i16> %shift
}
-define <4 x i32> @vshlls16_bad(<4 x i16>* %A) nounwind {
+define <4 x i32> @vshlls16_bad(ptr %A) nounwind {
; CHECK-LABEL: vshlls16_bad:
; CHECK: vmovl.u16
; CHECK: vshl.i32
- %tmp1 = load <4 x i16>, <4 x i16>* %A
+ %tmp1 = load <4 x i16>, ptr %A
%sext = sext <4 x i16> %tmp1 to <4 x i32>
%shift = shl <4 x i32> %sext, <i32 17, i32 17, i32 17, i32 17>
ret <4 x i32> %shift
}
-define <2 x i64> @vshllu32_bad(<2 x i32>* %A) nounwind {
+define <2 x i64> @vshllu32_bad(ptr %A) nounwind {
; CHECK-LABEL: vshllu32_bad:
; CHECK: vmovl.u32
; CHECK: vshl.i64
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%zext = zext <2 x i32> %tmp1 to <2 x i64>
%shift = shl <2 x i64> %zext, <i64 33, i64 33>
ret <2 x i64> %shift
diff --git a/llvm/test/CodeGen/ARM/vshrn.ll b/llvm/test/CodeGen/ARM/vshrn.ll
index e033486562c6c..5f3c332a8ee55 100644
--- a/llvm/test/CodeGen/ARM/vshrn.ll
+++ b/llvm/test/CodeGen/ARM/vshrn.ll
@@ -1,82 +1,82 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind {
+define <8 x i8> @vshrns8(ptr %A) nounwind {
;CHECK-LABEL: vshrns8:
;CHECK: vshrn.i16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = lshr <8 x i16> %tmp1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
%tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>
ret <8 x i8> %tmp3
}
-define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind {
+define <4 x i16> @vshrns16(ptr %A) nounwind {
;CHECK-LABEL: vshrns16:
;CHECK: vshrn.i32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = ashr <4 x i32> %tmp1, <i32 16, i32 16, i32 16, i32 16>
%tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>
ret <4 x i16> %tmp3
}
-define <2 x i32> @vshrns32(<2 x i64>* %A) nounwind {
+define <2 x i32> @vshrns32(ptr %A) nounwind {
;CHECK-LABEL: vshrns32:
;CHECK: vshrn.i64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = ashr <2 x i64> %tmp1, <i64 32, i64 32>
%tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>
ret <2 x i32> %tmp3
}
-define <8 x i8> @vshrns8_bad(<8 x i16>* %A) nounwind {
+define <8 x i8> @vshrns8_bad(ptr %A) nounwind {
; CHECK-LABEL: vshrns8_bad:
; CHECK: vshr.s16
; CHECK: vmovn.i16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = ashr <8 x i16> %tmp1, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
%tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>
ret <8 x i8> %tmp3
}
-define <4 x i16> @vshrns16_bad(<4 x i32>* %A) nounwind {
+define <4 x i16> @vshrns16_bad(ptr %A) nounwind {
; CHECK-LABEL: vshrns16_bad:
; CHECK: vshr.u32
; CHECK: vmovn.i32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = lshr <4 x i32> %tmp1, <i32 17, i32 17, i32 17, i32 17>
%tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>
ret <4 x i16> %tmp3
}
-define <2 x i32> @vshrns32_bad(<2 x i64>* %A) nounwind {
+define <2 x i32> @vshrns32_bad(ptr %A) nounwind {
; CHECK-LABEL: vshrns32_bad:
; CHECK: vshr.u64
; CHECK: vmovn.i64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = lshr <2 x i64> %tmp1, <i64 33, i64 33>
%tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>
ret <2 x i32> %tmp3
}
-define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind {
+define <8 x i8> @vrshrns8(ptr %A) nounwind {
;CHECK-LABEL: vrshrns8:
;CHECK: vrshrn.i16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
ret <8 x i8> %tmp2
}
-define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind {
+define <4 x i16> @vrshrns16(ptr %A) nounwind {
;CHECK-LABEL: vrshrns16:
;CHECK: vrshrn.i32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
+ %tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
ret <4 x i16> %tmp2
}
-define <2 x i32> @vrshrns32(<2 x i64>* %A) nounwind {
+define <2 x i32> @vrshrns32(ptr %A) nounwind {
;CHECK-LABEL: vrshrns32:
;CHECK: vrshrn.i64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
+ %tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
ret <2 x i32> %tmp2
}
diff --git a/llvm/test/CodeGen/ARM/vsra.ll b/llvm/test/CodeGen/ARM/vsra.ll
index cb758fa2f3868..ecaed4d3e899e 100644
--- a/llvm/test/CodeGen/ARM/vsra.ll
+++ b/llvm/test/CodeGen/ARM/vsra.ll
@@ -1,320 +1,320 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vsras8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsras8:
;CHECK: vsra.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = ashr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
%tmp4 = add <8 x i8> %tmp1, %tmp3
ret <8 x i8> %tmp4
}
-define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vsras16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsras16:
;CHECK: vsra.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = ashr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
%tmp4 = add <4 x i16> %tmp1, %tmp3
ret <4 x i16> %tmp4
}
-define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vsras32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsras32:
;CHECK: vsra.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = ashr <2 x i32> %tmp2, < i32 31, i32 31 >
%tmp4 = add <2 x i32> %tmp1, %tmp3
ret <2 x i32> %tmp4
}
-define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vsras64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsras64:
;CHECK: vsra.s64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = ashr <1 x i64> %tmp2, < i64 63 >
%tmp4 = add <1 x i64> %tmp1, %tmp3
ret <1 x i64> %tmp4
}
-define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vsraQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsraQs8:
;CHECK: vsra.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = ashr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
%tmp4 = add <16 x i8> %tmp1, %tmp3
ret <16 x i8> %tmp4
}
-define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vsraQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsraQs16:
;CHECK: vsra.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = ashr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
%tmp4 = add <8 x i16> %tmp1, %tmp3
ret <8 x i16> %tmp4
}
-define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vsraQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsraQs32:
;CHECK: vsra.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = ashr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
%tmp4 = add <4 x i32> %tmp1, %tmp3
ret <4 x i32> %tmp4
}
-define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vsraQs64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsraQs64:
;CHECK: vsra.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = ashr <2 x i64> %tmp2, < i64 63, i64 63 >
%tmp4 = add <2 x i64> %tmp1, %tmp3
ret <2 x i64> %tmp4
}
-define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vsrau8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsrau8:
;CHECK: vsra.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = lshr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
%tmp4 = add <8 x i8> %tmp1, %tmp3
ret <8 x i8> %tmp4
}
-define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vsrau16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsrau16:
;CHECK: vsra.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = lshr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
%tmp4 = add <4 x i16> %tmp1, %tmp3
ret <4 x i16> %tmp4
}
-define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vsrau32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsrau32:
;CHECK: vsra.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = lshr <2 x i32> %tmp2, < i32 31, i32 31 >
%tmp4 = add <2 x i32> %tmp1, %tmp3
ret <2 x i32> %tmp4
}
-define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vsrau64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsrau64:
;CHECK: vsra.u64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = lshr <1 x i64> %tmp2, < i64 63 >
%tmp4 = add <1 x i64> %tmp1, %tmp3
ret <1 x i64> %tmp4
}
-define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vsraQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsraQu8:
;CHECK: vsra.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = lshr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
%tmp4 = add <16 x i8> %tmp1, %tmp3
ret <16 x i8> %tmp4
}
-define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vsraQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsraQu16:
;CHECK: vsra.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = lshr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
%tmp4 = add <8 x i16> %tmp1, %tmp3
ret <8 x i16> %tmp4
}
-define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vsraQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsraQu32:
;CHECK: vsra.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = lshr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
%tmp4 = add <4 x i32> %tmp1, %tmp3
ret <4 x i32> %tmp4
}
-define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vsraQu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vsraQu64:
;CHECK: vsra.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = lshr <2 x i64> %tmp2, < i64 63, i64 63 >
%tmp4 = add <2 x i64> %tmp1, %tmp3
ret <2 x i64> %tmp4
}
-define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vrsras8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsras8:
;CHECK: vrsra.s8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
%tmp4 = add <8 x i8> %tmp1, %tmp3
ret <8 x i8> %tmp4
}
-define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vrsras16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsras16:
;CHECK: vrsra.s16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
%tmp4 = add <4 x i16> %tmp1, %tmp3
ret <4 x i16> %tmp4
}
-define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vrsras32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsras32:
;CHECK: vrsra.s32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
%tmp4 = add <2 x i32> %tmp1, %tmp3
ret <2 x i32> %tmp4
}
-define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vrsras64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsras64:
;CHECK: vrsra.s64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
%tmp4 = add <1 x i64> %tmp1, %tmp3
ret <1 x i64> %tmp4
}
-define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vrsrau8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsrau8:
;CHECK: vrsra.u8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
%tmp4 = add <8 x i8> %tmp1, %tmp3
ret <8 x i8> %tmp4
}
-define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vrsrau16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsrau16:
;CHECK: vrsra.u16
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
%tmp4 = add <4 x i16> %tmp1, %tmp3
ret <4 x i16> %tmp4
}
-define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vrsrau32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsrau32:
;CHECK: vrsra.u32
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
%tmp4 = add <2 x i32> %tmp1, %tmp3
ret <2 x i32> %tmp4
}
-define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+define <1 x i64> @vrsrau64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsrau64:
;CHECK: vrsra.u64
- %tmp1 = load <1 x i64>, <1 x i64>* %A
- %tmp2 = load <1 x i64>, <1 x i64>* %B
+ %tmp1 = load <1 x i64>, ptr %A
+ %tmp2 = load <1 x i64>, ptr %B
%tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
%tmp4 = add <1 x i64> %tmp1, %tmp3
ret <1 x i64> %tmp4
}
-define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vrsraQs8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsraQs8:
;CHECK: vrsra.s8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
%tmp4 = add <16 x i8> %tmp1, %tmp3
ret <16 x i8> %tmp4
}
-define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vrsraQs16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsraQs16:
;CHECK: vrsra.s16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
%tmp4 = add <8 x i16> %tmp1, %tmp3
ret <8 x i16> %tmp4
}
-define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vrsraQs32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsraQs32:
;CHECK: vrsra.s32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
%tmp4 = add <4 x i32> %tmp1, %tmp3
ret <4 x i32> %tmp4
}
-define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vrsraQs64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsraQs64:
;CHECK: vrsra.s64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
%tmp4 = add <2 x i64> %tmp1, %tmp3
ret <2 x i64> %tmp4
}
-define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vrsraQu8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsraQu8:
;CHECK: vrsra.u8
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
%tmp4 = add <16 x i8> %tmp1, %tmp3
ret <16 x i8> %tmp4
}
-define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vrsraQu16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsraQu16:
;CHECK: vrsra.u16
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
%tmp4 = add <8 x i16> %tmp1, %tmp3
ret <8 x i16> %tmp4
}
-define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vrsraQu32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsraQu32:
;CHECK: vrsra.u32
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
%tmp4 = add <4 x i32> %tmp1, %tmp3
ret <4 x i32> %tmp4
}
-define <2 x i64> @vrsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+define <2 x i64> @vrsraQu64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vrsraQu64:
;CHECK: vrsra.u64
- %tmp1 = load <2 x i64>, <2 x i64>* %A
- %tmp2 = load <2 x i64>, <2 x i64>* %B
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = load <2 x i64>, ptr %B
%tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
%tmp4 = add <2 x i64> %tmp1, %tmp3
ret <2 x i64> %tmp4
diff --git a/llvm/test/CodeGen/ARM/vst1.ll b/llvm/test/CodeGen/ARM/vst1.ll
index e351a2ec23739..bcd61e3caed6e 100644
--- a/llvm/test/CodeGen/ARM/vst1.ll
+++ b/llvm/test/CodeGen/ARM/vst1.ll
@@ -1,140 +1,129 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
+define void @vst1i8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst1i8:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vst1.8 {d16}, [r0:64]
- %tmp1 = load <8 x i8>, <8 x i8>* %B
- call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, i32 16)
+ %tmp1 = load <8 x i8>, ptr %B
+ call void @llvm.arm.neon.vst1.p0.v8i8(ptr %A, <8 x i8> %tmp1, i32 16)
ret void
}
-define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind {
+define void @vst1i16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst1i16:
;CHECK: vst1.16
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <4 x i16>, <4 x i16>* %B
- call void @llvm.arm.neon.vst1.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, i32 1)
+ %tmp1 = load <4 x i16>, ptr %B
+ call void @llvm.arm.neon.vst1.p0.v4i16(ptr %A, <4 x i16> %tmp1, i32 1)
ret void
}
-define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind {
+define void @vst1i32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst1i32:
;CHECK: vst1.32
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <2 x i32>, <2 x i32>* %B
- call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, i32 1)
+ %tmp1 = load <2 x i32>, ptr %B
+ call void @llvm.arm.neon.vst1.p0.v2i32(ptr %A, <2 x i32> %tmp1, i32 1)
ret void
}
-define void @vst1f(float* %A, <2 x float>* %B) nounwind {
+define void @vst1f(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst1f:
;CHECK: vst1.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <2 x float>, <2 x float>* %B
- call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1)
+ %tmp1 = load <2 x float>, ptr %B
+ call void @llvm.arm.neon.vst1.p0.v2f32(ptr %A, <2 x float> %tmp1, i32 1)
ret void
}
;Check for a post-increment updating store.
-define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind {
+define void @vst1f_update(ptr %ptr, ptr %B) nounwind {
;CHECK-LABEL: vst1f_update:
;CHECK: vst1.32 {d16}, [r{{[0-9]+}}]!
- %A = load float*, float** %ptr
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <2 x float>, <2 x float>* %B
- call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1)
- %tmp2 = getelementptr float, float* %A, i32 2
- store float* %tmp2, float** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <2 x float>, ptr %B
+ call void @llvm.arm.neon.vst1.p0.v2f32(ptr %A, <2 x float> %tmp1, i32 1)
+ %tmp2 = getelementptr float, ptr %A, i32 2
+ store ptr %tmp2, ptr %ptr
ret void
}
-define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind {
+define void @vst1i64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst1i64:
;CHECK: vst1.64
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = load <1 x i64>, <1 x i64>* %B
- call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, i32 1)
+ %tmp1 = load <1 x i64>, ptr %B
+ call void @llvm.arm.neon.vst1.p0.v1i64(ptr %A, <1 x i64> %tmp1, i32 1)
ret void
}
-define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind {
+define void @vst1Qi8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst1Qi8:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst1.8 {d16, d17}, [r0:64]
- %tmp1 = load <16 x i8>, <16 x i8>* %B
- call void @llvm.arm.neon.vst1.p0i8.v16i8(i8* %A, <16 x i8> %tmp1, i32 8)
+ %tmp1 = load <16 x i8>, ptr %B
+ call void @llvm.arm.neon.vst1.p0.v16i8(ptr %A, <16 x i8> %tmp1, i32 8)
ret void
}
-define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
+define void @vst1Qi16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst1Qi16:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst1.16 {d16, d17}, [r0:128]
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <8 x i16>, <8 x i16>* %B
- call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 32)
+ %tmp1 = load <8 x i16>, ptr %B
+ call void @llvm.arm.neon.vst1.p0.v8i16(ptr %A, <8 x i16> %tmp1, i32 32)
ret void
}
;Check for a post-increment updating store with register increment.
-define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
+define void @vst1Qi16_update(ptr %ptr, ptr %B, i32 %inc) nounwind {
;CHECK-LABEL: vst1Qi16_update:
;CHECK: vst1.16 {d16, d17}, [r1:64], r2
- %A = load i16*, i16** %ptr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <8 x i16>, <8 x i16>* %B
- call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 8)
- %tmp2 = getelementptr i16, i16* %A, i32 %inc
- store i16* %tmp2, i16** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <8 x i16>, ptr %B
+ call void @llvm.arm.neon.vst1.p0.v8i16(ptr %A, <8 x i16> %tmp1, i32 8)
+ %tmp2 = getelementptr i16, ptr %A, i32 %inc
+ store ptr %tmp2, ptr %ptr
ret void
}
-define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind {
+define void @vst1Qi32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst1Qi32:
;CHECK: vst1.32
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <4 x i32>, <4 x i32>* %B
- call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, i32 1)
+ %tmp1 = load <4 x i32>, ptr %B
+ call void @llvm.arm.neon.vst1.p0.v4i32(ptr %A, <4 x i32> %tmp1, i32 1)
ret void
}
-define void @vst1Qf(float* %A, <4 x float>* %B) nounwind {
+define void @vst1Qf(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst1Qf:
;CHECK: vst1.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <4 x float>, <4 x float>* %B
- call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, i32 1)
+ %tmp1 = load <4 x float>, ptr %B
+ call void @llvm.arm.neon.vst1.p0.v4f32(ptr %A, <4 x float> %tmp1, i32 1)
ret void
}
-define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind {
+define void @vst1Qi64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst1Qi64:
;CHECK: vst1.64
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = load <2 x i64>, <2 x i64>* %B
- call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %tmp0, <2 x i64> %tmp1, i32 1)
+ %tmp1 = load <2 x i64>, ptr %B
+ call void @llvm.arm.neon.vst1.p0.v2i64(ptr %A, <2 x i64> %tmp1, i32 1)
ret void
}
-define void @vst1Qf64(double* %A, <2 x double>* %B) nounwind {
+define void @vst1Qf64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst1Qf64:
;CHECK: vst1.64
- %tmp0 = bitcast double* %A to i8*
- %tmp1 = load <2 x double>, <2 x double>* %B
- call void @llvm.arm.neon.vst1.p0i8.v2f64(i8* %tmp0, <2 x double> %tmp1, i32 1)
+ %tmp1 = load <2 x double>, ptr %B
+ call void @llvm.arm.neon.vst1.p0.v2f64(ptr %A, <2 x double> %tmp1, i32 1)
ret void
}
-declare void @llvm.arm.neon.vst1.p0i8.v8i8(i8*, <8 x i8>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v4i16(i8*, <4 x i16>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v2i32(i8*, <2 x i32>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v2f32(i8*, <2 x float>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v1i64(i8*, <1 x i64>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v8i8(ptr, <8 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v4i16(ptr, <4 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v2i32(ptr, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v2f32(ptr, <2 x float>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v1i64(ptr, <1 x i64>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v16i8(i8*, <16 x i8>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v8i16(i8*, <8 x i16>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v4i32(i8*, <4 x i32>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v2i64(i8*, <2 x i64>, i32) nounwind
-declare void @llvm.arm.neon.vst1.p0i8.v2f64(i8*, <2 x double>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v16i8(ptr, <16 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v8i16(ptr, <8 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v4i32(ptr, <4 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v4f32(ptr, <4 x float>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v2i64(ptr, <2 x i64>, i32) nounwind
+declare void @llvm.arm.neon.vst1.p0.v2f64(ptr, <2 x double>, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/vst2.ll b/llvm/test/CodeGen/ARM/vst2.ll
index e0846ff512ea3..90e0882f3e807 100644
--- a/llvm/test/CodeGen/ARM/vst2.ll
+++ b/llvm/test/CodeGen/ARM/vst2.ll
@@ -1,140 +1,132 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
+define void @vst2i8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst2i8:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst2.8 {d16, d17}, [r0:64]
- %tmp1 = load <8 x i8>, <8 x i8>* %B
- call void @llvm.arm.neon.vst2.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8)
+ %tmp1 = load <8 x i8>, ptr %B
+ call void @llvm.arm.neon.vst2.p0.v8i8(ptr %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8)
ret void
}
;Check for a post-increment updating store with register increment.
-define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
+define void @vst2i8_update(ptr %ptr, ptr %B, i32 %inc) nounwind {
;CHECK-LABEL: vst2i8_update:
;CHECK: vst2.8 {d16, d17}, [r1], r2
- %A = load i8*, i8** %ptr
- %tmp1 = load <8 x i8>, <8 x i8>* %B
- call void @llvm.arm.neon.vst2.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 4)
- %tmp2 = getelementptr i8, i8* %A, i32 %inc
- store i8* %tmp2, i8** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <8 x i8>, ptr %B
+ call void @llvm.arm.neon.vst2.p0.v8i8(ptr %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 4)
+ %tmp2 = getelementptr i8, ptr %A, i32 %inc
+ store ptr %tmp2, ptr %ptr
ret void
}
-define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind {
+define void @vst2i16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst2i16:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst2.16 {d16, d17}, [r0:128]
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <4 x i16>, <4 x i16>* %B
- call void @llvm.arm.neon.vst2.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 32)
+ %tmp1 = load <4 x i16>, ptr %B
+ call void @llvm.arm.neon.vst2.p0.v4i16(ptr %A, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 32)
ret void
}
-define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind {
+define void @vst2i32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst2i32:
;CHECK: vst2.32
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <2 x i32>, <2 x i32>* %B
- call void @llvm.arm.neon.vst2.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+ %tmp1 = load <2 x i32>, ptr %B
+ call void @llvm.arm.neon.vst2.p0.v2i32(ptr %A, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
ret void
}
-define void @vst2f(float* %A, <2 x float>* %B) nounwind {
+define void @vst2f(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst2f:
;CHECK: vst2.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <2 x float>, <2 x float>* %B
- call void @llvm.arm.neon.vst2.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
+ %tmp1 = load <2 x float>, ptr %B
+ call void @llvm.arm.neon.vst2.p0.v2f32(ptr %A, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
ret void
}
-define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind {
+define void @vst2i64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst2i64:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst1.64 {d16, d17}, [r0:128]
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = load <1 x i64>, <1 x i64>* %B
- call void @llvm.arm.neon.vst2.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 32)
+ %tmp1 = load <1 x i64>, ptr %B
+ call void @llvm.arm.neon.vst2.p0.v1i64(ptr %A, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 32)
ret void
}
;Check for a post-increment updating store.
-define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind {
+define void @vst2i64_update(ptr %ptr, ptr %B) nounwind {
;CHECK-LABEL: vst2i64_update:
;CHECK: vst1.64 {d16, d17}, [r1:64]!
- %A = load i64*, i64** %ptr
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = load <1 x i64>, <1 x i64>* %B
- call void @llvm.arm.neon.vst2.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 8)
- %tmp2 = getelementptr i64, i64* %A, i32 2
- store i64* %tmp2, i64** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <1 x i64>, ptr %B
+ call void @llvm.arm.neon.vst2.p0.v1i64(ptr %A, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 8)
+ %tmp2 = getelementptr i64, ptr %A, i32 2
+ store ptr %tmp2, ptr %ptr
ret void
}
-define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind {
+define void @vst2Qi8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst2Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64]
- %tmp1 = load <16 x i8>, <16 x i8>* %B
- call void @llvm.arm.neon.vst2.p0i8.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 8)
+ %tmp1 = load <16 x i8>, ptr %B
+ call void @llvm.arm.neon.vst2.p0.v16i8(ptr %A, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 8)
ret void
}
-define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind {
+define void @vst2Qi16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst2Qi16:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128]
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <8 x i16>, <8 x i16>* %B
- call void @llvm.arm.neon.vst2.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 16)
+ %tmp1 = load <8 x i16>, ptr %B
+ call void @llvm.arm.neon.vst2.p0.v8i16(ptr %A, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 16)
ret void
}
-define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind {
+define void @vst2Qi32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst2Qi32:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256]
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <4 x i32>, <4 x i32>* %B
- call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 64)
+ %tmp1 = load <4 x i32>, ptr %B
+ call void @llvm.arm.neon.vst2.p0.v4i32(ptr %A, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 64)
ret void
}
-define void @vst2Qf(float* %A, <4 x float>* %B) nounwind {
+define void @vst2Qf(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst2Qf:
;CHECK: vst2.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <4 x float>, <4 x float>* %B
- call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
+ %tmp1 = load <4 x float>, ptr %B
+ call void @llvm.arm.neon.vst2.p0.v4f32(ptr %A, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
ret void
}
-define i8* @vst2update(i8* %out, <4 x i16>* %B) nounwind {
+define ptr @vst2update(ptr %out, ptr %B) nounwind {
;CHECK-LABEL: vst2update:
;CHECK: vst2.16 {d16, d17}, [r0]!
- %tmp1 = load <4 x i16>, <4 x i16>* %B
- tail call void @llvm.arm.neon.vst2.p0i8.v4i16(i8* %out, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 2)
- %t5 = getelementptr inbounds i8, i8* %out, i32 16
- ret i8* %t5
+ %tmp1 = load <4 x i16>, ptr %B
+ tail call void @llvm.arm.neon.vst2.p0.v4i16(ptr %out, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 2)
+ %t5 = getelementptr inbounds i8, ptr %out, i32 16
+ ret ptr %t5
}
-define i8* @vst2update2(i8 * %out, <4 x float> * %this) nounwind optsize ssp align 2 {
+define ptr @vst2update2(ptr %out, ptr %this) nounwind optsize ssp align 2 {
;CHECK-LABEL: vst2update2:
;CHECK: vst2.32 {d16, d17, d18, d19}, [r0]!
- %tmp1 = load <4 x float>, <4 x float>* %this
- call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %out, <4 x float> %tmp1, <4 x float> %tmp1, i32 4) nounwind
- %tmp2 = getelementptr inbounds i8, i8* %out, i32 32
- ret i8* %tmp2
+ %tmp1 = load <4 x float>, ptr %this
+ call void @llvm.arm.neon.vst2.p0.v4f32(ptr %out, <4 x float> %tmp1, <4 x float> %tmp1, i32 4) nounwind
+ %tmp2 = getelementptr inbounds i8, ptr %out, i32 32
+ ret ptr %tmp2
}
-declare void @llvm.arm.neon.vst2.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind
-declare void @llvm.arm.neon.vst2.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, i32) nounwind
-declare void @llvm.arm.neon.vst2.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, i32) nounwind
-declare void @llvm.arm.neon.vst2.p0i8.v2f32(i8*, <2 x float>, <2 x float>, i32) nounwind
-declare void @llvm.arm.neon.vst2.p0i8.v1i64(i8*, <1 x i64>, <1 x i64>, i32) nounwind
+declare void @llvm.arm.neon.vst2.p0.v8i8(ptr, <8 x i8>, <8 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst2.p0.v4i16(ptr, <4 x i16>, <4 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst2.p0.v2i32(ptr, <2 x i32>, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst2.p0.v2f32(ptr, <2 x float>, <2 x float>, i32) nounwind
+declare void @llvm.arm.neon.vst2.p0.v1i64(ptr, <1 x i64>, <1 x i64>, i32) nounwind
-declare void @llvm.arm.neon.vst2.p0i8.v16i8(i8*, <16 x i8>, <16 x i8>, i32) nounwind
-declare void @llvm.arm.neon.vst2.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, i32) nounwind
-declare void @llvm.arm.neon.vst2.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, i32) nounwind
-declare void @llvm.arm.neon.vst2.p0i8.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind
+declare void @llvm.arm.neon.vst2.p0.v16i8(ptr, <16 x i8>, <16 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst2.p0.v8i16(ptr, <8 x i16>, <8 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst2.p0.v4i32(ptr, <4 x i32>, <4 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst2.p0.v4f32(ptr, <4 x float>, <4 x float>, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/vst3.ll b/llvm/test/CodeGen/ARM/vst3.ll
index 1723304e82b38..930513e450013 100644
--- a/llvm/test/CodeGen/ARM/vst3.ll
+++ b/llvm/test/CodeGen/ARM/vst3.ll
@@ -1,152 +1,141 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon -fast-isel=0 -O0 %s -o - | FileCheck %s
-define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind {
+define void @vst3i8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst3i8:
;Check the alignment value. Max for this instruction is 64 bits:
;This test runs at -O0 so do not check for specific register numbers.
;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
- %tmp1 = load <8 x i8>, <8 x i8>* %B
- call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 32)
+ %tmp1 = load <8 x i8>, ptr %B
+ call void @llvm.arm.neon.vst3.p0.v8i8(ptr %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 32)
ret void
}
-define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind {
+define void @vst3i16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst3i16:
;CHECK: vst3.16
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <4 x i16>, <4 x i16>* %B
- call void @llvm.arm.neon.vst3.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
+ %tmp1 = load <4 x i16>, ptr %B
+ call void @llvm.arm.neon.vst3.p0.v4i16(ptr %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
ret void
}
-define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind {
+define void @vst3i32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst3i32:
;CHECK: vst3.32
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <2 x i32>, <2 x i32>* %B
- call void @llvm.arm.neon.vst3.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+ %tmp1 = load <2 x i32>, ptr %B
+ call void @llvm.arm.neon.vst3.p0.v2i32(ptr %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
ret void
}
;Check for a post-increment updating store.
-define void @vst3i32_update(i32** %ptr, <2 x i32>* %B) nounwind {
+define void @vst3i32_update(ptr %ptr, ptr %B) nounwind {
;CHECK-LABEL: vst3i32_update:
;CHECK: vst3.32 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
- %A = load i32*, i32** %ptr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <2 x i32>, <2 x i32>* %B
- call void @llvm.arm.neon.vst3.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
- %tmp2 = getelementptr i32, i32* %A, i32 6
- store i32* %tmp2, i32** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <2 x i32>, ptr %B
+ call void @llvm.arm.neon.vst3.p0.v2i32(ptr %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+ %tmp2 = getelementptr i32, ptr %A, i32 6
+ store ptr %tmp2, ptr %ptr
ret void
}
-define void @vst3f(float* %A, <2 x float>* %B) nounwind {
+define void @vst3f(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst3f:
;CHECK: vst3.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <2 x float>, <2 x float>* %B
- call void @llvm.arm.neon.vst3.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
+ %tmp1 = load <2 x float>, ptr %B
+ call void @llvm.arm.neon.vst3.p0.v2f32(ptr %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
ret void
}
-define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind {
+define void @vst3i64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst3i64:
;Check the alignment value. Max for this instruction is 64 bits:
;This test runs at -O0 so do not check for specific register numbers.
;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = load <1 x i64>, <1 x i64>* %B
- call void @llvm.arm.neon.vst3.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 16)
+ %tmp1 = load <1 x i64>, ptr %B
+ call void @llvm.arm.neon.vst3.p0.v1i64(ptr %A, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 16)
ret void
}
-define void @vst3i64_update(i64** %ptr, <1 x i64>* %B) nounwind {
+define void @vst3i64_update(ptr %ptr, ptr %B) nounwind {
;CHECK-LABEL: vst3i64_update
;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
- %A = load i64*, i64** %ptr
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = load <1 x i64>, <1 x i64>* %B
- call void @llvm.arm.neon.vst3.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1)
- %tmp2 = getelementptr i64, i64* %A, i32 3
- store i64* %tmp2, i64** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <1 x i64>, ptr %B
+ call void @llvm.arm.neon.vst3.p0.v1i64(ptr %A, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1)
+ %tmp2 = getelementptr i64, ptr %A, i32 3
+ store ptr %tmp2, ptr %ptr
ret void
}
-define void @vst3i64_reg_update(i64** %ptr, <1 x i64>* %B) nounwind {
+define void @vst3i64_reg_update(ptr %ptr, ptr %B) nounwind {
;CHECK-LABEL: vst3i64_reg_update
;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}], r{{.*}}
- %A = load i64*, i64** %ptr
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = load <1 x i64>, <1 x i64>* %B
- call void @llvm.arm.neon.vst3.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1)
- %tmp2 = getelementptr i64, i64* %A, i32 1
- store i64* %tmp2, i64** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <1 x i64>, ptr %B
+ call void @llvm.arm.neon.vst3.p0.v1i64(ptr %A, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1)
+ %tmp2 = getelementptr i64, ptr %A, i32 1
+ store ptr %tmp2, ptr %ptr
ret void
}
-define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind {
+define void @vst3Qi8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst3Qi8:
;Check the alignment value. Max for this instruction is 64 bits:
;This test runs at -O0 so do not check for specific register numbers.
;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]!
;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
- %tmp1 = load <16 x i8>, <16 x i8>* %B
- call void @llvm.arm.neon.vst3.p0i8.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 32)
+ %tmp1 = load <16 x i8>, ptr %B
+ call void @llvm.arm.neon.vst3.p0.v16i8(ptr %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 32)
ret void
}
-define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind {
+define void @vst3Qi16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst3Qi16:
;CHECK: vst3.16
;CHECK: vst3.16
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <8 x i16>, <8 x i16>* %B
- call void @llvm.arm.neon.vst3.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
+ %tmp1 = load <8 x i16>, ptr %B
+ call void @llvm.arm.neon.vst3.p0.v8i16(ptr %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
ret void
}
;Check for a post-increment updating store.
-define void @vst3Qi16_update(i16** %ptr, <8 x i16>* %B) nounwind {
+define void @vst3Qi16_update(ptr %ptr, ptr %B) nounwind {
;CHECK-LABEL: vst3Qi16_update:
;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
- %A = load i16*, i16** %ptr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <8 x i16>, <8 x i16>* %B
- call void @llvm.arm.neon.vst3.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
- %tmp2 = getelementptr i16, i16* %A, i32 24
- store i16* %tmp2, i16** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <8 x i16>, ptr %B
+ call void @llvm.arm.neon.vst3.p0.v8i16(ptr %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
+ %tmp2 = getelementptr i16, ptr %A, i32 24
+ store ptr %tmp2, ptr %ptr
ret void
}
-define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind {
+define void @vst3Qi32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst3Qi32:
;CHECK: vst3.32
;CHECK: vst3.32
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <4 x i32>, <4 x i32>* %B
- call void @llvm.arm.neon.vst3.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1)
+ %tmp1 = load <4 x i32>, ptr %B
+ call void @llvm.arm.neon.vst3.p0.v4i32(ptr %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1)
ret void
}
-define void @vst3Qf(float* %A, <4 x float>* %B) nounwind {
+define void @vst3Qf(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst3Qf:
;CHECK: vst3.32
;CHECK: vst3.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <4 x float>, <4 x float>* %B
- call void @llvm.arm.neon.vst3.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
+ %tmp1 = load <4 x float>, ptr %B
+ call void @llvm.arm.neon.vst3.p0.v4f32(ptr %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
ret void
}
-declare void @llvm.arm.neon.vst3.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind
-declare void @llvm.arm.neon.vst3.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind
-declare void @llvm.arm.neon.vst3.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
-declare void @llvm.arm.neon.vst3.p0i8.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32) nounwind
-declare void @llvm.arm.neon.vst3.p0i8.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, i32) nounwind
+declare void @llvm.arm.neon.vst3.p0.v8i8(ptr, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst3.p0.v4i16(ptr, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst3.p0.v2i32(ptr, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst3.p0.v2f32(ptr, <2 x float>, <2 x float>, <2 x float>, i32) nounwind
+declare void @llvm.arm.neon.vst3.p0.v1i64(ptr, <1 x i64>, <1 x i64>, <1 x i64>, i32) nounwind
-declare void @llvm.arm.neon.vst3.p0i8.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, i32) nounwind
-declare void @llvm.arm.neon.vst3.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind
-declare void @llvm.arm.neon.vst3.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind
-declare void @llvm.arm.neon.vst3.p0i8.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32) nounwind
+declare void @llvm.arm.neon.vst3.p0.v16i8(ptr, <16 x i8>, <16 x i8>, <16 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst3.p0.v8i16(ptr, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst3.p0.v4i32(ptr, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst3.p0.v4f32(ptr, <4 x float>, <4 x float>, <4 x float>, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/vst4.ll b/llvm/test/CodeGen/ARM/vst4.ll
index ca9e5e7a59df7..f7a436a19efb4 100644
--- a/llvm/test/CodeGen/ARM/vst4.ll
+++ b/llvm/test/CodeGen/ARM/vst4.ll
@@ -1,151 +1,141 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
+define void @vst4i8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst4i8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64]
- %tmp1 = load <8 x i8>, <8 x i8>* %B
- call void @llvm.arm.neon.vst4.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8)
+ %tmp1 = load <8 x i8>, ptr %B
+ call void @llvm.arm.neon.vst4.p0.v8i8(ptr %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8)
ret void
}
;Check for a post-increment updating store with register increment.
-define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
+define void @vst4i8_update(ptr %ptr, ptr %B, i32 %inc) nounwind {
;CHECK-LABEL: vst4i8_update:
;CHECK: vst4.8 {d16, d17, d18, d19}, [r{{[0-9]+}}:128], r2
- %A = load i8*, i8** %ptr
- %tmp1 = load <8 x i8>, <8 x i8>* %B
- call void @llvm.arm.neon.vst4.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 16)
- %tmp2 = getelementptr i8, i8* %A, i32 %inc
- store i8* %tmp2, i8** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <8 x i8>, ptr %B
+ call void @llvm.arm.neon.vst4.p0.v8i8(ptr %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 16)
+ %tmp2 = getelementptr i8, ptr %A, i32 %inc
+ store ptr %tmp2, ptr %ptr
ret void
}
-define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind {
+define void @vst4i16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst4i16:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128]
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <4 x i16>, <4 x i16>* %B
- call void @llvm.arm.neon.vst4.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 16)
+ %tmp1 = load <4 x i16>, ptr %B
+ call void @llvm.arm.neon.vst4.p0.v4i16(ptr %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 16)
ret void
}
-define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind {
+define void @vst4i32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst4i32:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst4.32 {d16, d17, d18, d19}, [r0:256]
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <2 x i32>, <2 x i32>* %B
- call void @llvm.arm.neon.vst4.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 32)
+ %tmp1 = load <2 x i32>, ptr %B
+ call void @llvm.arm.neon.vst4.p0.v2i32(ptr %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 32)
ret void
}
-define void @vst4f(float* %A, <2 x float>* %B) nounwind {
+define void @vst4f(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst4f:
;CHECK: vst4.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <2 x float>, <2 x float>* %B
- call void @llvm.arm.neon.vst4.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
+ %tmp1 = load <2 x float>, ptr %B
+ call void @llvm.arm.neon.vst4.p0.v2f32(ptr %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
ret void
}
-define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind {
+define void @vst4i64(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst4i64:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst1.64 {d16, d17, d18, d19}, [r0:256]
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = load <1 x i64>, <1 x i64>* %B
- call void @llvm.arm.neon.vst4.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 64)
+ %tmp1 = load <1 x i64>, ptr %B
+ call void @llvm.arm.neon.vst4.p0.v1i64(ptr %A, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 64)
ret void
}
-define void @vst4i64_update(i64** %ptr, <1 x i64>* %B) nounwind {
+define void @vst4i64_update(ptr %ptr, ptr %B) nounwind {
;CHECK-LABEL: vst4i64_update:
;CHECK: vst1.64 {d16, d17, d18, d19}, [r{{[0-9]+}}]!
- %A = load i64*, i64** %ptr
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = load <1 x i64>, <1 x i64>* %B
- call void @llvm.arm.neon.vst4.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1)
- %tmp2 = getelementptr i64, i64* %A, i32 4
- store i64* %tmp2, i64** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <1 x i64>, ptr %B
+ call void @llvm.arm.neon.vst4.p0.v1i64(ptr %A, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1)
+ %tmp2 = getelementptr i64, ptr %A, i32 4
+ store ptr %tmp2, ptr %ptr
ret void
}
-define void @vst4i64_reg_update(i64** %ptr, <1 x i64>* %B) nounwind {
+define void @vst4i64_reg_update(ptr %ptr, ptr %B) nounwind {
;CHECK-LABEL: vst4i64_reg_update:
;CHECK: vst1.64 {d16, d17, d18, d19}, [r{{[0-9]+}}], r{{[0-9]+}}
- %A = load i64*, i64** %ptr
- %tmp0 = bitcast i64* %A to i8*
- %tmp1 = load <1 x i64>, <1 x i64>* %B
- call void @llvm.arm.neon.vst4.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1)
- %tmp2 = getelementptr i64, i64* %A, i32 1
- store i64* %tmp2, i64** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <1 x i64>, ptr %B
+ call void @llvm.arm.neon.vst4.p0.v1i64(ptr %A, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1)
+ %tmp2 = getelementptr i64, ptr %A, i32 1
+ store ptr %tmp2, ptr %ptr
ret void
}
-define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind {
+define void @vst4Qi8(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst4Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]!
;CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]
- %tmp1 = load <16 x i8>, <16 x i8>* %B
- call void @llvm.arm.neon.vst4.p0i8.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 64)
+ %tmp1 = load <16 x i8>, ptr %B
+ call void @llvm.arm.neon.vst4.p0.v16i8(ptr %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 64)
ret void
}
-define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind {
+define void @vst4Qi16(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst4Qi16:
;Check for no alignment specifier.
;CHECK: vst4.16 {d16, d18, d20, d22}, [r0]!
;CHECK: vst4.16 {d17, d19, d21, d23}, [r0]
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <8 x i16>, <8 x i16>* %B
- call void @llvm.arm.neon.vst4.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
+ %tmp1 = load <8 x i16>, ptr %B
+ call void @llvm.arm.neon.vst4.p0.v8i16(ptr %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
ret void
}
-define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind {
+define void @vst4Qi32(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst4Qi32:
;CHECK: vst4.32
;CHECK: vst4.32
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <4 x i32>, <4 x i32>* %B
- call void @llvm.arm.neon.vst4.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1)
+ %tmp1 = load <4 x i32>, ptr %B
+ call void @llvm.arm.neon.vst4.p0.v4i32(ptr %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1)
ret void
}
-define void @vst4Qf(float* %A, <4 x float>* %B) nounwind {
+define void @vst4Qf(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vst4Qf:
;CHECK: vst4.32
;CHECK: vst4.32
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <4 x float>, <4 x float>* %B
- call void @llvm.arm.neon.vst4.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
+ %tmp1 = load <4 x float>, ptr %B
+ call void @llvm.arm.neon.vst4.p0.v4f32(ptr %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
ret void
}
;Check for a post-increment updating store.
-define void @vst4Qf_update(float** %ptr, <4 x float>* %B) nounwind {
+define void @vst4Qf_update(ptr %ptr, ptr %B) nounwind {
;CHECK-LABEL: vst4Qf_update:
;CHECK: vst4.32 {d16, d18, d20, d22}, [r[[REG:[0-9]+]]]!
;CHECK: vst4.32 {d17, d19, d21, d23}, [r[[REG]]]!
- %A = load float*, float** %ptr
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <4 x float>, <4 x float>* %B
- call void @llvm.arm.neon.vst4.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
- %tmp2 = getelementptr float, float* %A, i32 16
- store float* %tmp2, float** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <4 x float>, ptr %B
+ call void @llvm.arm.neon.vst4.p0.v4f32(ptr %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
+ %tmp2 = getelementptr float, ptr %A, i32 16
+ store ptr %tmp2, ptr %ptr
ret void
}
-declare void @llvm.arm.neon.vst4.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind
-declare void @llvm.arm.neon.vst4.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind
-declare void @llvm.arm.neon.vst4.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
-declare void @llvm.arm.neon.vst4.p0i8.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32) nounwind
-declare void @llvm.arm.neon.vst4.p0i8.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32) nounwind
+declare void @llvm.arm.neon.vst4.p0.v8i8(ptr, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst4.p0.v4i16(ptr, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst4.p0.v2i32(ptr, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst4.p0.v2f32(ptr, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32) nounwind
+declare void @llvm.arm.neon.vst4.p0.v1i64(ptr, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32) nounwind
-declare void @llvm.arm.neon.vst4.p0i8.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32) nounwind
-declare void @llvm.arm.neon.vst4.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind
-declare void @llvm.arm.neon.vst4.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind
-declare void @llvm.arm.neon.vst4.p0i8.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) nounwind
+declare void @llvm.arm.neon.vst4.p0.v16i8(ptr, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst4.p0.v8i16(ptr, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst4.p0.v4i32(ptr, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst4.p0.v4f32(ptr, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/vstlane.ll b/llvm/test/CodeGen/ARM/vstlane.ll
index 2515034fb780e..32e569db6158c 100644
--- a/llvm/test/CodeGen/ARM/vstlane.ll
+++ b/llvm/test/CodeGen/ARM/vstlane.ll
@@ -2,20 +2,20 @@
; RUN: llc < %s -mtriple=arm -mattr=+neon | FileCheck %s
;Check the (default) alignment.
-define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
+define void @vst1lanei8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst1lanei8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vst1.8 {d16[3]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %B
%tmp2 = extractelement <8 x i8> %tmp1, i32 3
- store i8 %tmp2, i8* %A, align 8
+ store i8 %tmp2, ptr %A, align 8
ret void
}
;Check for a post-increment updating store.
-define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
+define void @vst1lanei8_update(ptr %ptr, ptr %B) nounwind {
; CHECK-LABEL: vst1lanei8_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r2, [r0]
@@ -23,97 +23,97 @@ define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vst1.8 {d16[3]}, [r2]!
; CHECK-NEXT: str r2, [r0]
; CHECK-NEXT: mov pc, lr
- %A = load i8*, i8** %ptr
- %tmp1 = load <8 x i8>, <8 x i8>* %B
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <8 x i8>, ptr %B
%tmp2 = extractelement <8 x i8> %tmp1, i32 3
- store i8 %tmp2, i8* %A, align 8
- %tmp3 = getelementptr i8, i8* %A, i32 1
- store i8* %tmp3, i8** %ptr
+ store i8 %tmp2, ptr %A, align 8
+ %tmp3 = getelementptr i8, ptr %A, i32 1
+ store ptr %tmp3, ptr %ptr
ret void
}
;Check the alignment value. Max for this instruction is 16 bits:
-define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind {
+define void @vst1lanei16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst1lanei16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vst1.16 {d16[2]}, [r0:16]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %B
%tmp2 = extractelement <4 x i16> %tmp1, i32 2
- store i16 %tmp2, i16* %A, align 8
+ store i16 %tmp2, ptr %A, align 8
ret void
}
;Check the alignment value. Max for this instruction is 32 bits:
-define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind {
+define void @vst1lanei32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst1lanei32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vst1.32 {d16[1]}, [r0:32]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %B
%tmp2 = extractelement <2 x i32> %tmp1, i32 1
- store i32 %tmp2, i32* %A, align 8
+ store i32 %tmp2, ptr %A, align 8
ret void
}
-define void @vst1lanef(float* %A, <2 x float>* %B) nounwind {
+define void @vst1lanef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst1lanef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vst1.32 {d16[1]}, [r0:32]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %B
%tmp2 = extractelement <2 x float> %tmp1, i32 1
- store float %tmp2, float* %A
+ store float %tmp2, ptr %A
ret void
}
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.8 {d17[1]}, [r0]
-define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
+define void @vst1laneQi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst1laneQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vst1.8 {d17[1]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %B
%tmp2 = extractelement <16 x i8> %tmp1, i32 9
- store i8 %tmp2, i8* %A, align 8
+ store i8 %tmp2, ptr %A, align 8
ret void
}
-define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
+define void @vst1laneQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst1laneQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vst1.16 {d17[1]}, [r0:16]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %B
%tmp2 = extractelement <8 x i16> %tmp1, i32 5
- store i16 %tmp2, i16* %A, align 8
+ store i16 %tmp2, ptr %A, align 8
ret void
}
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.32 {d17[1]}, [r0:32]
-define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
+define void @vst1laneQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst1laneQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r1, [r1, #12]
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %B
%tmp2 = extractelement <4 x i32> %tmp1, i32 3
- store i32 %tmp2, i32* %A, align 8
+ store i32 %tmp2, ptr %A, align 8
ret void
}
;Check for a post-increment updating store.
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.32 {d17[1]}, [r1:32]!
-define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
+define void @vst1laneQi32_update(ptr %ptr, ptr %B) nounwind {
; CHECK-LABEL: vst1laneQi32_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r2, [r0]
@@ -121,58 +121,57 @@ define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
; CHECK-NEXT: str r1, [r2], #4
; CHECK-NEXT: str r2, [r0]
; CHECK-NEXT: mov pc, lr
- %A = load i32*, i32** %ptr
- %tmp1 = load <4 x i32>, <4 x i32>* %B
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <4 x i32>, ptr %B
%tmp2 = extractelement <4 x i32> %tmp1, i32 3
- store i32 %tmp2, i32* %A, align 8
- %tmp3 = getelementptr i32, i32* %A, i32 1
- store i32* %tmp3, i32** %ptr
+ store i32 %tmp2, ptr %A, align 8
+ %tmp3 = getelementptr i32, ptr %A, i32 1
+ store ptr %tmp3, ptr %ptr
ret void
}
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.32 {d17[1]}, [r0]
-define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind {
+define void @vst1laneQf(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst1laneQf:
; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r1, [r1, #12]
; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %B
%tmp2 = extractelement <4 x float> %tmp1, i32 3
- store float %tmp2, float* %A
+ store float %tmp2, ptr %A
ret void
}
;Check the alignment value. Max for this instruction is 16 bits:
-define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
+define void @vst2lanei8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst2lanei8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vst2.8 {d16[1], d17[1]}, [r0:16]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %B
- call void @llvm.arm.neon.vst2lane.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
+ %tmp1 = load <8 x i8>, ptr %B
+ call void @llvm.arm.neon.vst2lane.p0.v8i8(ptr %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
ret void
}
;Check the alignment value. Max for this instruction is 32 bits:
-define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
+define void @vst2lanei16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst2lanei16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vst2.16 {d16[1], d17[1]}, [r0:32]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <4 x i16>, <4 x i16>* %B
- call void @llvm.arm.neon.vst2lane.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
+ %tmp1 = load <4 x i16>, ptr %B
+ call void @llvm.arm.neon.vst2lane.p0.v4i16(ptr %A, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
ret void
}
;Check for a post-increment updating store with register increment.
-define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind {
+define void @vst2lanei16_update(ptr %ptr, ptr %B, i32 %inc) nounwind {
; CHECK-LABEL: vst2lanei16_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -182,92 +181,86 @@ define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind {
; CHECK-NEXT: vst2.16 {d16[1], d17[1]}, [r3], r1
; CHECK-NEXT: str r3, [r0]
; CHECK-NEXT: mov pc, lr
- %A = load i16*, i16** %ptr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <4 x i16>, <4 x i16>* %B
- call void @llvm.arm.neon.vst2lane.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 2)
- %tmp2 = getelementptr i16, i16* %A, i32 %inc
- store i16* %tmp2, i16** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <4 x i16>, ptr %B
+ call void @llvm.arm.neon.vst2lane.p0.v4i16(ptr %A, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 2)
+ %tmp2 = getelementptr i16, ptr %A, i32 %inc
+ store ptr %tmp2, ptr %ptr
ret void
}
-define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind {
+define void @vst2lanei32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst2lanei32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vst2.32 {d16[1], d17[1]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <2 x i32>, <2 x i32>* %B
- call void @llvm.arm.neon.vst2lane.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
+ %tmp1 = load <2 x i32>, ptr %B
+ call void @llvm.arm.neon.vst2lane.p0.v2i32(ptr %A, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
ret void
}
-define void @vst2lanef(float* %A, <2 x float>* %B) nounwind {
+define void @vst2lanef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst2lanef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vst2.32 {d16[1], d17[1]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <2 x float>, <2 x float>* %B
- call void @llvm.arm.neon.vst2lane.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
+ %tmp1 = load <2 x float>, ptr %B
+ call void @llvm.arm.neon.vst2lane.p0.v2f32(ptr %A, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
ret void
}
;Check the (default) alignment.
-define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
+define void @vst2laneQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst2laneQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vst2.16 {d17[1], d19[1]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <8 x i16>, <8 x i16>* %B
- call void @llvm.arm.neon.vst2lane.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1)
+ %tmp1 = load <8 x i16>, ptr %B
+ call void @llvm.arm.neon.vst2lane.p0.v8i16(ptr %A, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1)
ret void
}
;Check the alignment value. Max for this instruction is 64 bits:
-define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
+define void @vst2laneQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst2laneQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vst2.32 {d17[0], d19[0]}, [r0:64]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <4 x i32>, <4 x i32>* %B
- call void @llvm.arm.neon.vst2lane.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16)
+ %tmp1 = load <4 x i32>, ptr %B
+ call void @llvm.arm.neon.vst2lane.p0.v4i32(ptr %A, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16)
ret void
}
-define void @vst2laneQf(float* %A, <4 x float>* %B) nounwind {
+define void @vst2laneQf(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst2laneQf:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vst2.32 {d17[1], d19[1]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <4 x float>, <4 x float>* %B
- call void @llvm.arm.neon.vst2lane.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 3, i32 1)
+ %tmp1 = load <4 x float>, ptr %B
+ call void @llvm.arm.neon.vst2lane.p0.v4f32(ptr %A, <4 x float> %tmp1, <4 x float> %tmp1, i32 3, i32 1)
ret void
}
-declare void @llvm.arm.neon.vst2lane.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst2lane.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst2lane.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst2lane.p0i8.v2f32(i8*, <2 x float>, <2 x float>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.p0.v8i8(ptr, <8 x i8>, <8 x i8>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.p0.v4i16(ptr, <4 x i16>, <4 x i16>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.p0.v2i32(ptr, <2 x i32>, <2 x i32>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.p0.v2f32(ptr, <2 x float>, <2 x float>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst2lane.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst2lane.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst2lane.p0i8.v4f32(i8*, <4 x float>, <4 x float>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.p0.v8i16(ptr, <8 x i16>, <8 x i16>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.p0.v4i32(ptr, <4 x i32>, <4 x i32>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.p0.v4f32(ptr, <4 x float>, <4 x float>, i32, i32) nounwind
-define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind {
+define void @vst3lanei8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst3lanei8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -275,13 +268,13 @@ define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vorr d18, d16, d16
; CHECK-NEXT: vst3.8 {d16[1], d17[1], d18[1]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %B
- call void @llvm.arm.neon.vst3lane.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
+ %tmp1 = load <8 x i8>, ptr %B
+ call void @llvm.arm.neon.vst3lane.p0.v8i8(ptr %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
ret void
}
;Check the (default) alignment value. VST3 does not support alignment.
-define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind {
+define void @vst3lanei16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst3lanei16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -289,13 +282,12 @@ define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vorr d18, d16, d16
; CHECK-NEXT: vst3.16 {d16[1], d17[1], d18[1]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <4 x i16>, <4 x i16>* %B
- call void @llvm.arm.neon.vst3lane.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
+ %tmp1 = load <4 x i16>, ptr %B
+ call void @llvm.arm.neon.vst3lane.p0.v4i16(ptr %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
ret void
}
-define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind {
+define void @vst3lanei32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst3lanei32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -303,13 +295,12 @@ define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: vorr d18, d16, d16
; CHECK-NEXT: vst3.32 {d16[1], d17[1], d18[1]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <2 x i32>, <2 x i32>* %B
- call void @llvm.arm.neon.vst3lane.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
+ %tmp1 = load <2 x i32>, ptr %B
+ call void @llvm.arm.neon.vst3lane.p0.v2i32(ptr %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
ret void
}
-define void @vst3lanef(float* %A, <2 x float>* %B) nounwind {
+define void @vst3lanef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst3lanef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -317,13 +308,12 @@ define void @vst3lanef(float* %A, <2 x float>* %B) nounwind {
; CHECK-NEXT: vorr d18, d16, d16
; CHECK-NEXT: vst3.32 {d16[1], d17[1], d18[1]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <2 x float>, <2 x float>* %B
- call void @llvm.arm.neon.vst3lane.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
+ %tmp1 = load <2 x float>, ptr %B
+ call void @llvm.arm.neon.vst3lane.p0.v2f32(ptr %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
ret void
}
-define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
+define void @vst3laneQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst3laneQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -332,13 +322,12 @@ define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vst3.16 {d17[2], d19[2], d21[2]}, [r0]
; CHECK-NEXT: mov pc, lr
;Check the (default) alignment value. VST3 does not support alignment.
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <8 x i16>, <8 x i16>* %B
- call void @llvm.arm.neon.vst3lane.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6, i32 8)
+ %tmp1 = load <8 x i16>, ptr %B
+ call void @llvm.arm.neon.vst3lane.p0.v8i16(ptr %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6, i32 8)
ret void
}
-define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
+define void @vst3laneQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst3laneQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -346,14 +335,13 @@ define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vorr q10, q8, q8
; CHECK-NEXT: vst3.32 {d16[0], d18[0], d20[0]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <4 x i32>, <4 x i32>* %B
- call void @llvm.arm.neon.vst3lane.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1)
+ %tmp1 = load <4 x i32>, ptr %B
+ call void @llvm.arm.neon.vst3lane.p0.v4i32(ptr %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1)
ret void
}
;Check for a post-increment updating store.
-define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
+define void @vst3laneQi32_update(ptr %ptr, ptr %B) nounwind {
; CHECK-LABEL: vst3laneQi32_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -363,16 +351,15 @@ define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vst3.32 {d16[0], d18[0], d20[0]}, [r2]!
; CHECK-NEXT: str r2, [r0]
; CHECK-NEXT: mov pc, lr
- %A = load i32*, i32** %ptr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <4 x i32>, <4 x i32>* %B
- call void @llvm.arm.neon.vst3lane.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1)
- %tmp2 = getelementptr i32, i32* %A, i32 3
- store i32* %tmp2, i32** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <4 x i32>, ptr %B
+ call void @llvm.arm.neon.vst3lane.p0.v4i32(ptr %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1)
+ %tmp2 = getelementptr i32, ptr %A, i32 3
+ store ptr %tmp2, ptr %ptr
ret void
}
-define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind {
+define void @vst3laneQf(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst3laneQf:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -380,24 +367,23 @@ define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind {
; CHECK-NEXT: vorr q10, q8, q8
; CHECK-NEXT: vst3.32 {d16[1], d18[1], d20[1]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <4 x float>, <4 x float>* %B
- call void @llvm.arm.neon.vst3lane.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
+ %tmp1 = load <4 x float>, ptr %B
+ call void @llvm.arm.neon.vst3lane.p0.v4f32(ptr %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
ret void
}
-declare void @llvm.arm.neon.vst3lane.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst3lane.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst3lane.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst3lane.p0i8.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.p0.v8i8(ptr, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.p0.v4i16(ptr, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.p0.v2i32(ptr, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.p0.v2f32(ptr, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst3lane.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst3lane.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst3lane.p0i8.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.p0.v8i16(ptr, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.p0.v4i32(ptr, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.p0.v4f32(ptr, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind
;Check the alignment value. Max for this instruction is 32 bits:
-define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
+define void @vst4lanei8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst4lanei8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -406,13 +392,13 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vorr d19, d16, d16
; CHECK-NEXT: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %B
- call void @llvm.arm.neon.vst4lane.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
+ %tmp1 = load <8 x i8>, ptr %B
+ call void @llvm.arm.neon.vst4lane.p0.v8i8(ptr %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
ret void
}
;Check for a post-increment updating store.
-define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
+define void @vst4lanei8_update(ptr %ptr, ptr %B) nounwind {
; CHECK-LABEL: vst4lanei8_update:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -423,15 +409,15 @@ define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r2:32]!
; CHECK-NEXT: str r2, [r0]
; CHECK-NEXT: mov pc, lr
- %A = load i8*, i8** %ptr
- %tmp1 = load <8 x i8>, <8 x i8>* %B
- call void @llvm.arm.neon.vst4lane.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
- %tmp2 = getelementptr i8, i8* %A, i32 4
- store i8* %tmp2, i8** %ptr
+ %A = load ptr, ptr %ptr
+ %tmp1 = load <8 x i8>, ptr %B
+ call void @llvm.arm.neon.vst4lane.p0.v8i8(ptr %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
+ %tmp2 = getelementptr i8, ptr %A, i32 4
+ store ptr %tmp2, ptr %ptr
ret void
}
-define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
+define void @vst4lanei16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst4lanei16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -440,14 +426,13 @@ define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vorr d19, d16, d16
; CHECK-NEXT: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <4 x i16>, <4 x i16>* %B
- call void @llvm.arm.neon.vst4lane.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 1)
+ %tmp1 = load <4 x i16>, ptr %B
+ call void @llvm.arm.neon.vst4lane.p0.v4i16(ptr %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 1)
ret void
}
;Check the alignment value. Max for this instruction is 128 bits:
-define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
+define void @vst4lanei32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst4lanei32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -456,13 +441,12 @@ define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: vorr d19, d16, d16
; CHECK-NEXT: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <2 x i32>, <2 x i32>* %B
- call void @llvm.arm.neon.vst4lane.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 16)
+ %tmp1 = load <2 x i32>, ptr %B
+ call void @llvm.arm.neon.vst4lane.p0.v2i32(ptr %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 16)
ret void
}
-define void @vst4lanef(float* %A, <2 x float>* %B) nounwind {
+define void @vst4lanef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst4lanef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -471,14 +455,13 @@ define void @vst4lanef(float* %A, <2 x float>* %B) nounwind {
; CHECK-NEXT: vorr d19, d16, d16
; CHECK-NEXT: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <2 x float>, <2 x float>* %B
- call void @llvm.arm.neon.vst4lane.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
+ %tmp1 = load <2 x float>, ptr %B
+ call void @llvm.arm.neon.vst4lane.p0.v2f32(ptr %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
ret void
}
;Check the alignment value. Max for this instruction is 64 bits:
-define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
+define void @vst4laneQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst4laneQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -487,14 +470,13 @@ define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vorr q11, q8, q8
; CHECK-NEXT: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i16* %A to i8*
- %tmp1 = load <8 x i16>, <8 x i16>* %B
- call void @llvm.arm.neon.vst4lane.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7, i32 16)
+ %tmp1 = load <8 x i16>, ptr %B
+ call void @llvm.arm.neon.vst4lane.p0.v8i16(ptr %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7, i32 16)
ret void
}
;Check the (default) alignment.
-define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
+define void @vst4laneQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst4laneQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -503,13 +485,12 @@ define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vorr q11, q8, q8
; CHECK-NEXT: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast i32* %A to i8*
- %tmp1 = load <4 x i32>, <4 x i32>* %B
- call void @llvm.arm.neon.vst4lane.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1)
+ %tmp1 = load <4 x i32>, ptr %B
+ call void @llvm.arm.neon.vst4lane.p0.v4i32(ptr %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1)
ret void
}
-define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind {
+define void @vst4laneQf(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vst4laneQf:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -518,9 +499,8 @@ define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind {
; CHECK-NEXT: vorr q11, q8, q8
; CHECK-NEXT: vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r0]
; CHECK-NEXT: mov pc, lr
- %tmp0 = bitcast float* %A to i8*
- %tmp1 = load <4 x float>, <4 x float>* %B
- call void @llvm.arm.neon.vst4lane.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
+ %tmp1 = load <4 x float>, ptr %B
+ call void @llvm.arm.neon.vst4lane.p0.v4f32(ptr %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
ret void
}
@@ -552,11 +532,11 @@ define <8 x i16> @variable_insertelement(<8 x i16> %a, i16 %b, i32 %c) nounwind
ret <8 x i16> %r
}
-declare void @llvm.arm.neon.vst4lane.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst4lane.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst4lane.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst4lane.p0i8.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.p0.v8i8(ptr, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.p0.v4i16(ptr, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.p0.v2i32(ptr, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.p0.v2f32(ptr, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst4lane.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst4lane.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind
-declare void @llvm.arm.neon.vst4lane.p0i8.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.p0.v8i16(ptr, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.p0.v4i32(ptr, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.p0.v4f32(ptr, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/vtbl.ll b/llvm/test/CodeGen/ARM/vtbl.ll
index 2e0718877e96d..c5c9436c002b8 100644
--- a/llvm/test/CodeGen/ARM/vtbl.ll
+++ b/llvm/test/CodeGen/ARM/vtbl.ll
@@ -4,31 +4,31 @@
%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
-define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vtbl1(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vtbl1:
;CHECK: vtbl.8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8> %tmp1, <8 x i8> %tmp2)
ret <8 x i8> %tmp3
}
-define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind {
+define <8 x i8> @vtbl2(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vtbl2:
;CHECK: vtbl.8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load %struct.__neon_int8x8x2_t, %struct.__neon_int8x8x2_t* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load %struct.__neon_int8x8x2_t, ptr %B
%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1
%tmp5 = call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4)
ret <8 x i8> %tmp5
}
-define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind {
+define <8 x i8> @vtbl3(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vtbl3:
;CHECK: vtbl.8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load %struct.__neon_int8x8x3_t, %struct.__neon_int8x8x3_t* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load %struct.__neon_int8x8x3_t, ptr %B
%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2
@@ -36,11 +36,11 @@ define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind {
ret <8 x i8> %tmp6
}
-define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind {
+define <8 x i8> @vtbl4(ptr %A, ptr %B) nounwind {
;CHECK-LABEL: vtbl4:
;CHECK: vtbl.8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load %struct.__neon_int8x8x4_t, ptr %B
%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
@@ -49,51 +49,51 @@ define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind {
ret <8 x i8> %tmp7
}
-define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+define <8 x i8> @vtbx1(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vtbx1:
;CHECK: vtbx.8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
- %tmp3 = load <8 x i8>, <8 x i8>* %C
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
+ %tmp3 = load <8 x i8>, ptr %C
%tmp4 = call <8 x i8> @llvm.arm.neon.vtbx1(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
ret <8 x i8> %tmp4
}
-define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C) nounwind {
+define <8 x i8> @vtbx2(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vtbx2:
;CHECK: vtbx.8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load %struct.__neon_int8x8x2_t, %struct.__neon_int8x8x2_t* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load %struct.__neon_int8x8x2_t, ptr %B
%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1
- %tmp5 = load <8 x i8>, <8 x i8>* %C
+ %tmp5 = load <8 x i8>, ptr %C
%tmp6 = call <8 x i8> @llvm.arm.neon.vtbx2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5)
ret <8 x i8> %tmp6
}
-define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C) nounwind {
+define <8 x i8> @vtbx3(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vtbx3:
;CHECK: vtbx.8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load %struct.__neon_int8x8x3_t, %struct.__neon_int8x8x3_t* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load %struct.__neon_int8x8x3_t, ptr %B
%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2
- %tmp6 = load <8 x i8>, <8 x i8>* %C
+ %tmp6 = load <8 x i8>, ptr %C
%tmp7 = call <8 x i8> @llvm.arm.neon.vtbx3(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6)
ret <8 x i8> %tmp7
}
-define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
+define <8 x i8> @vtbx4(ptr %A, ptr %B, ptr %C) nounwind {
;CHECK-LABEL: vtbx4:
;CHECK: vtbx.8
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load %struct.__neon_int8x8x4_t, ptr %B
%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
%tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
- %tmp7 = load <8 x i8>, <8 x i8>* %C
+ %tmp7 = load <8 x i8>, ptr %C
%tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
ret <8 x i8> %tmp8
}
diff --git a/llvm/test/CodeGen/ARM/vtrn.ll b/llvm/test/CodeGen/ARM/vtrn.ll
index 6b200176e1fef..136fec3ac3167 100644
--- a/llvm/test/CodeGen/ARM/vtrn.ll
+++ b/llvm/test/CodeGen/ARM/vtrn.ll
@@ -1,6 +1,6 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vtrni8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrni8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -9,15 +9,15 @@ define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vadd.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
%tmp5 = add <8 x i8> %tmp3, %tmp4
ret <8 x i8> %tmp5
}
-define <16 x i8> @vtrni8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <16 x i8> @vtrni8_Qres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrni8_Qres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
@@ -26,13 +26,13 @@ define <16 x i8> @vtrni8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
ret <16 x i8> %tmp3
}
-define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vtrni16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrni16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -41,15 +41,15 @@ define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vadd.i16 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
%tmp5 = add <4 x i16> %tmp3, %tmp4
ret <4 x i16> %tmp5
}
-define <8 x i16> @vtrni16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <8 x i16> @vtrni16_Qres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrni16_Qres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
@@ -58,13 +58,13 @@ define <8 x i16> @vtrni16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>
ret <8 x i16> %tmp3
}
-define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <2 x i32> @vtrni32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrni32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -73,15 +73,15 @@ define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: vmul.i32 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>
%tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>
%tmp5 = mul <2 x i32> %tmp3, %tmp4
ret <2 x i32> %tmp5
}
-define <4 x i32> @vtrni32_Qres(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+define <4 x i32> @vtrni32_Qres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrni32_Qres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
@@ -90,13 +90,13 @@ define <4 x i32> @vtrni32_Qres(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x i32> %tmp3
}
-define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <2 x float> @vtrnf(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrnf:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -105,15 +105,15 @@ define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
; CHECK-NEXT: vadd.f32 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2>
%tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3>
%tmp5 = fadd <2 x float> %tmp3, %tmp4
ret <2 x float> %tmp5
}
-define <4 x float> @vtrnf_Qres(<2 x float>* %A, <2 x float>* %B) nounwind {
+define <4 x float> @vtrnf_Qres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrnf_Qres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
@@ -122,13 +122,13 @@ define <4 x float> @vtrnf_Qres(<2 x float>* %A, <2 x float>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x float>, <2 x float>* %A
- %tmp2 = load <2 x float>, <2 x float>* %B
+ %tmp1 = load <2 x float>, ptr %A
+ %tmp2 = load <2 x float>, ptr %B
%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x float> %tmp3
}
-define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vtrnQi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrnQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -138,15 +138,15 @@ define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
%tmp5 = add <16 x i8> %tmp3, %tmp4
ret <16 x i8> %tmp5
}
-define <32 x i8> @vtrnQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <32 x i8> @vtrnQi8_QQres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrnQi8_QQres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
@@ -155,13 +155,13 @@ define <32 x i8> @vtrnQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30, i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
ret <32 x i8> %tmp3
}
-define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vtrnQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrnQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -171,15 +171,15 @@ define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
%tmp5 = add <8 x i16> %tmp3, %tmp4
ret <8 x i16> %tmp5
}
-define <16 x i16> @vtrnQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <16 x i16> @vtrnQi16_QQres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrnQi16_QQres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
@@ -188,13 +188,13 @@ define <16 x i16> @vtrnQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
ret <16 x i16> %tmp3
}
-define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vtrnQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrnQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -204,15 +204,15 @@ define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
%tmp5 = add <4 x i32> %tmp3, %tmp4
ret <4 x i32> %tmp5
}
-define <8 x i32> @vtrnQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <8 x i32> @vtrnQi32_QQres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrnQi32_QQres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
@@ -221,13 +221,13 @@ define <8 x i32> @vtrnQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>
ret <8 x i32> %tmp3
}
-define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x float> @vtrnQf(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrnQf:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -237,15 +237,15 @@ define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
%tmp5 = fadd <4 x float> %tmp3, %tmp4
ret <4 x float> %tmp5
}
-define <8 x float> @vtrnQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <8 x float> @vtrnQf_QQres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrnQf_QQres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
@@ -254,14 +254,14 @@ define <8 x float> @vtrnQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>
ret <8 x float> %tmp3
}
-define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vtrni8_undef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrni8_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -270,15 +270,15 @@ define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vadd.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14>
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
%tmp5 = add <8 x i8> %tmp3, %tmp4
ret <8 x i8> %tmp5
}
-define <16 x i8> @vtrni8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <16 x i8> @vtrni8_undef_Qres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrni8_undef_Qres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
@@ -287,13 +287,13 @@ define <16 x i8> @vtrni8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
ret <16 x i8> %tmp3
}
-define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vtrnQi16_undef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrnQi16_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -303,15 +303,15 @@ define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14>
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
%tmp5 = add <8 x i16> %tmp3, %tmp4
ret <8 x i16> %tmp5
}
-define <16 x i16> @vtrnQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <16 x i16> @vtrnQi16_undef_QQres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vtrnQi16_undef_QQres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
@@ -320,18 +320,18 @@ define <16 x i16> @vtrnQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14, i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
ret <16 x i16> %tmp3
}
-define <8 x i16> @vtrn_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) {
+define <8 x i16> @vtrn_lower_shufflemask_undef(ptr %A, ptr %B) {
entry:
; CHECK-LABEL: vtrn_lower_shufflemask_undef
; CHECK: vtrn
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 5, i32 3, i32 7>
ret <8 x i16> %0
}
@@ -357,12 +357,12 @@ define <8 x i8> @vtrn_mismatched_builvector0(<8 x i8> %tr0, <8 x i8> %tr1,
; values do not modify the type (the values form cmp2), but half of them do
; (from the icmp operation).
define <8 x i8> @vtrn_mismatched_builvector1(<8 x i8> %tr0, <8 x i8> %tr1,
- <4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i8> *%cmp2_ptr) {
+ <4 x i32> %cmp0, <4 x i32> %cmp1, ptr %cmp2_ptr) {
; CHECK-LABEL: vtrn_mismatched_builvector1:
; We need to extend the 4 x i8 to 4 x i16 in order to perform the vtrn
; CHECK: vmovl
; CHECK: vbsl
- %cmp2_load = load <4 x i8>, <4 x i8> * %cmp2_ptr, align 4
+ %cmp2_load = load <4 x i8>, ptr %cmp2_ptr, align 4
%cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1>
%c0 = icmp ult <4 x i32> %cmp0, %cmp1
%c = shufflevector <4 x i1> %c0, <4 x i1> %cmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
@@ -372,7 +372,7 @@ define <8 x i8> @vtrn_mismatched_builvector1(<8 x i8> %tr0, <8 x i8> %tr1,
; The shuffle mask is half a vtrn; we duplicate the half to produce the
; full result.
-define void @lower_twice_no_vtrn(<4 x i16>* %A, <4 x i16>* %B, <8 x i16>* %C) {
+define void @lower_twice_no_vtrn(ptr %A, ptr %B, ptr %C) {
entry:
; CHECK-LABEL: lower_twice_no_vtrn:
; CHECK: @ %bb.0:
@@ -382,16 +382,16 @@ entry:
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vst1.64 {d16, d17}, [r2]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 5, i32 3, i32 7, i32 1, i32 5, i32 3, i32 7>
- store <8 x i16> %0, <8 x i16>* %C
+ store <8 x i16> %0, ptr %C
ret void
}
; The shuffle mask is half a vtrn; we duplicate the half to produce the
; full result.
-define void @upper_twice_no_vtrn(<4 x i16>* %A, <4 x i16>* %B, <8 x i16>* %C) {
+define void @upper_twice_no_vtrn(ptr %A, ptr %B, ptr %C) {
entry:
; CHECK-LABEL: upper_twice_no_vtrn:
; CHECK: @ %bb.0:
@@ -401,9 +401,9 @@ entry:
; CHECK-NEXT: vorr d19, d18, d18
; CHECK-NEXT: vst1.64 {d18, d19}, [r2]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 6, i32 0, i32 4, i32 2, i32 6>
- store <8 x i16> %0, <8 x i16>* %C
+ store <8 x i16> %0, ptr %C
ret void
}
diff --git a/llvm/test/CodeGen/ARM/vuzp.ll b/llvm/test/CodeGen/ARM/vuzp.ll
index a5d6a62766276..d54446a431ee9 100644
--- a/llvm/test/CodeGen/ARM/vuzp.ll
+++ b/llvm/test/CodeGen/ARM/vuzp.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vuzpi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -10,15 +10,15 @@ define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vmul.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%tmp5 = mul <8 x i8> %tmp3, %tmp4
ret <8 x i8> %tmp5
}
-define <16 x i8> @vuzpi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <16 x i8> @vuzpi8_Qres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpi8_Qres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [r1]
@@ -27,13 +27,13 @@ define <16 x i8> @vuzpi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
ret <16 x i8> %tmp3
}
-define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vuzpi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -42,15 +42,15 @@ define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vmul.i16 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%tmp5 = mul <4 x i16> %tmp3, %tmp4
ret <4 x i16> %tmp5
}
-define <8 x i16> @vuzpi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <8 x i16> @vuzpi16_Qres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpi16_Qres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [r1]
@@ -59,15 +59,15 @@ define <8 x i16> @vuzpi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
ret <8 x i16> %tmp3
}
; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
-define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vuzpQi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -77,15 +77,15 @@ define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
%tmp5 = add <16 x i8> %tmp3, %tmp4
ret <16 x i8> %tmp5
}
-define <32 x i8> @vuzpQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <32 x i8> @vuzpQi8_QQres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpQi8_QQres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
@@ -94,13 +94,13 @@ define <32 x i8> @vuzpQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
ret <32 x i8> %tmp3
}
-define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vuzpQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -110,15 +110,15 @@ define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%tmp5 = add <8 x i16> %tmp3, %tmp4
ret <8 x i16> %tmp5
}
-define <16 x i16> @vuzpQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <16 x i16> @vuzpQi16_QQres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpQi16_QQres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
@@ -127,13 +127,13 @@ define <16 x i16> @vuzpQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
ret <16 x i16> %tmp3
}
-define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vuzpQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -143,15 +143,15 @@ define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%tmp5 = add <4 x i32> %tmp3, %tmp4
ret <4 x i32> %tmp5
}
-define <8 x i32> @vuzpQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <8 x i32> @vuzpQi32_QQres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpQi32_QQres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
@@ -160,13 +160,13 @@ define <8 x i32> @vuzpQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
ret <8 x i32> %tmp3
}
-define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x float> @vuzpQf(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpQf:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -176,15 +176,15 @@ define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%tmp5 = fadd <4 x float> %tmp3, %tmp4
ret <4 x float> %tmp5
}
-define <8 x float> @vuzpQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <8 x float> @vuzpQf_QQres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpQf_QQres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
@@ -193,15 +193,15 @@ define <8 x float> @vuzpQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
ret <8 x float> %tmp3
}
; Undef shuffle indices should not prevent matching to VUZP:
-define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vuzpi8_undef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpi8_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -210,15 +210,15 @@ define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vmul.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14>
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15>
%tmp5 = mul <8 x i8> %tmp3, %tmp4
ret <8 x i8> %tmp5
}
-define <16 x i8> @vuzpi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <16 x i8> @vuzpi8_undef_Qres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpi8_undef_Qres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [r1]
@@ -227,13 +227,13 @@ define <16 x i8> @vuzpi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15>
ret <16 x i8> %tmp3
}
-define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vuzpQi16_undef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpQi16_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -243,15 +243,15 @@ define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14>
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>
%tmp5 = add <8 x i16> %tmp3, %tmp4
ret <8 x i16> %tmp5
}
-define <16 x i16> @vuzpQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <16 x i16> @vuzpQi16_undef_QQres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vuzpQi16_undef_QQres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
@@ -260,13 +260,13 @@ define <16 x i16> @vuzpQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>
ret <16 x i16> %tmp3
}
-define <8 x i16> @vuzp_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) {
+define <8 x i16> @vuzp_lower_shufflemask_undef(ptr %A, ptr %B) {
; CHECK-LABEL: vuzp_lower_shufflemask_undef:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d17, [r1]
@@ -276,13 +276,13 @@ define <8 x i16> @vuzp_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) {
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
entry:
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 3, i32 5, i32 7>
ret <8 x i16> %0
}
-define <4 x i32> @vuzp_lower_shufflemask_zeroed(<2 x i32>* %A, <2 x i32>* %B) {
+define <4 x i32> @vuzp_lower_shufflemask_zeroed(ptr %A, ptr %B) {
; CHECK-LABEL: vuzp_lower_shufflemask_zeroed:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d18, [r0]
@@ -294,13 +294,13 @@ define <4 x i32> @vuzp_lower_shufflemask_zeroed(<2 x i32>* %A, <2 x i32>* %B) {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
entry:
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 0, i32 1, i32 3>
ret <4 x i32> %0
}
-define void @vuzp_rev_shufflemask_vtrn(<2 x i32>* %A, <2 x i32>* %B, <4 x i32>* %C) {
+define void @vuzp_rev_shufflemask_vtrn(ptr %A, ptr %B, ptr %C) {
; CHECK-LABEL: vuzp_rev_shufflemask_vtrn:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, [r1]
@@ -309,10 +309,10 @@ define void @vuzp_rev_shufflemask_vtrn(<2 x i32>* %A, <2 x i32>* %B, <4 x i32>*
; CHECK-NEXT: vst1.64 {d16, d17}, [r2]
; CHECK-NEXT: mov pc, lr
entry:
- %tmp1 = load <2 x i32>, <2 x i32>* %A
- %tmp2 = load <2 x i32>, <2 x i32>* %B
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = load <2 x i32>, ptr %B
%0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 0, i32 2>
- store <4 x i32> %0, <4 x i32>* %C
+ store <4 x i32> %0, ptr %C
ret void
}
@@ -371,8 +371,8 @@ define <8 x i8> @vuzp_trunc_and_shuffle(<8 x i8> %tr0, <8 x i8> %tr1,
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: pop {r11, lr}
; CHECK-NEXT: mov pc, lr
- <4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i8> *%cmp2_ptr) {
- %cmp2_load = load <4 x i8>, <4 x i8> * %cmp2_ptr, align 4
+ <4 x i32> %cmp0, <4 x i32> %cmp1, ptr %cmp2_ptr) {
+ %cmp2_load = load <4 x i8>, ptr %cmp2_ptr, align 4
%cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1>
%c0 = icmp ult <4 x i32> %cmp0, %cmp1
%c = shufflevector <4 x i1> %c0, <4 x i1> %cmp2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -399,8 +399,8 @@ define <8 x i8> @vuzp_trunc_and_shuffle_undef_right(<8 x i8> %tr0, <8 x i8> %tr1
; CHECK-NEXT: vbsl d16, d18, d17
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- <4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i8> *%cmp2_ptr) {
- %cmp2_load = load <4 x i8>, <4 x i8> * %cmp2_ptr, align 4
+ <4 x i32> %cmp0, <4 x i32> %cmp1, ptr %cmp2_ptr) {
+ %cmp2_load = load <4 x i8>, ptr %cmp2_ptr, align 4
%cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1>
%c0 = icmp ult <4 x i32> %cmp0, %cmp1
%c = shufflevector <4 x i1> %c0, <4 x i1> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -437,8 +437,8 @@ define <8 x i8> @vuzp_trunc_and_shuffle_undef_left(<8 x i8> %tr0, <8 x i8> %tr1,
; CHECK-NEXT: .byte 2 @ 0x2
; CHECK-NEXT: .byte 4 @ 0x4
; CHECK-NEXT: .byte 6 @ 0x6
- <4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i8> *%cmp2_ptr) {
- %cmp2_load = load <4 x i8>, <4 x i8> * %cmp2_ptr, align 4
+ <4 x i32> %cmp0, <4 x i32> %cmp1, ptr %cmp2_ptr) {
+ %cmp2_load = load <4 x i8>, ptr %cmp2_ptr, align 4
%cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1>
%c0 = icmp ult <4 x i32> %cmp0, %cmp1
%c = shufflevector <4 x i1> undef, <4 x i1> %c0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -509,8 +509,8 @@ define <10 x i8> @vuzp_wide_type(<10 x i8> %tr0, <10 x i8> %tr1,
; CHECK-NEXT: .byte 8 @ 0x8
; CHECK-NEXT: .byte 9 @ 0x9
; CHECK-NEXT: .byte 10 @ 0xa
- <5 x i32> %cmp0, <5 x i32> %cmp1, <5 x i8> *%cmp2_ptr) {
- %cmp2_load = load <5 x i8>, <5 x i8> * %cmp2_ptr, align 4
+ <5 x i32> %cmp0, <5 x i32> %cmp1, ptr %cmp2_ptr) {
+ %cmp2_load = load <5 x i8>, ptr %cmp2_ptr, align 4
%cmp2 = trunc <5 x i8> %cmp2_load to <5 x i1>
%c0 = icmp ult <5 x i32> %cmp0, %cmp1
%c = shufflevector <5 x i1> %c0, <5 x i1> %cmp2, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
diff --git a/llvm/test/CodeGen/ARM/vzip.ll b/llvm/test/CodeGen/ARM/vzip.ll
index 71c337ffb60f3..68f00a23da177 100644
--- a/llvm/test/CodeGen/ARM/vzip.ll
+++ b/llvm/test/CodeGen/ARM/vzip.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vzipi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -10,15 +10,15 @@ define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vadd.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
%tmp5 = add <8 x i8> %tmp3, %tmp4
ret <8 x i8> %tmp5
}
-define <16 x i8> @vzipi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <16 x i8> @vzipi8_Qres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipi8_Qres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [r1]
@@ -27,13 +27,13 @@ define <16 x i8> @vzipi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
ret <16 x i8> %tmp3
}
-define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <4 x i16> @vzipi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -42,15 +42,15 @@ define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vadd.i16 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
%tmp5 = add <4 x i16> %tmp3, %tmp4
ret <4 x i16> %tmp5
}
-define <8 x i16> @vzipi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+define <8 x i16> @vzipi16_Qres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipi16_Qres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [r1]
@@ -59,15 +59,15 @@ define <8 x i16> @vzipi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
ret <8 x i16> %tmp3
}
; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
-define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vzipQi8(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -77,15 +77,15 @@ define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
%tmp5 = add <16 x i8> %tmp3, %tmp4
ret <16 x i8> %tmp5
}
-define <32 x i8> @vzipQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <32 x i8> @vzipQi8_QQres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipQi8_QQres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
@@ -94,13 +94,13 @@ define <32 x i8> @vzipQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
ret <32 x i8> %tmp3
}
-define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <8 x i16> @vzipQi16(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -110,15 +110,15 @@ define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
%tmp5 = add <8 x i16> %tmp3, %tmp4
ret <8 x i16> %tmp5
}
-define <16 x i16> @vzipQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+define <16 x i16> @vzipQi16_QQres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipQi16_QQres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
@@ -127,13 +127,13 @@ define <16 x i16> @vzipQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, <8 x i16>* %A
- %tmp2 = load <8 x i16>, <8 x i16>* %B
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = load <8 x i16>, ptr %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
ret <16 x i16> %tmp3
}
-define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <4 x i32> @vzipQi32(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -143,15 +143,15 @@ define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
%tmp5 = add <4 x i32> %tmp3, %tmp4
ret <4 x i32> %tmp5
}
-define <8 x i32> @vzipQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+define <8 x i32> @vzipQi32_QQres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipQi32_QQres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
@@ -160,13 +160,13 @@ define <8 x i32> @vzipQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, <4 x i32>* %A
- %tmp2 = load <4 x i32>, <4 x i32>* %B
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = load <4 x i32>, ptr %B
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
ret <8 x i32> %tmp3
}
-define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <4 x float> @vzipQf(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipQf:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -176,15 +176,15 @@ define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
%tmp5 = fadd <4 x float> %tmp3, %tmp4
ret <4 x float> %tmp5
}
-define <8 x float> @vzipQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind {
+define <8 x float> @vzipQf_QQres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipQf_QQres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
@@ -193,15 +193,15 @@ define <8 x float> @vzipQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <4 x float>, <4 x float>* %A
- %tmp2 = load <4 x float>, <4 x float>* %B
+ %tmp1 = load <4 x float>, ptr %A
+ %tmp2 = load <4 x float>, ptr %B
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
ret <8 x float> %tmp3
}
; Undef shuffle indices should not prevent matching to VZIP:
-define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <8 x i8> @vzipi8_undef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipi8_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
@@ -210,15 +210,15 @@ define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vadd.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11>
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15>
%tmp5 = add <8 x i8> %tmp3, %tmp4
ret <8 x i8> %tmp5
}
-define <16 x i8> @vzipi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+define <16 x i8> @vzipi8_undef_Qres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipi8_undef_Qres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d17, [r1]
@@ -227,13 +227,13 @@ define <16 x i8> @vzipi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, <8 x i8>* %A
- %tmp2 = load <8 x i8>, <8 x i8>* %B
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = load <8 x i8>, ptr %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15>
ret <16 x i8> %tmp3
}
-define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <16 x i8> @vzipQi8_undef(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipQi8_undef:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
@@ -243,15 +243,15 @@ define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31>
%tmp5 = add <16 x i8> %tmp3, %tmp4
ret <16 x i8> %tmp5
}
-define <32 x i8> @vzipQi8_undef_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+define <32 x i8> @vzipQi8_undef_QQres(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vzipQi8_undef_QQres:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
@@ -260,13 +260,13 @@ define <32 x i8> @vzipQi8_undef_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <16 x i8>, <16 x i8>* %A
- %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp1 = load <16 x i8>, ptr %A
+ %tmp2 = load <16 x i8>, ptr %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31>
ret <32 x i8> %tmp3
}
-define <8 x i16> @vzip_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) {
+define <8 x i16> @vzip_lower_shufflemask_undef(ptr %A, ptr %B) {
; CHECK-LABEL: vzip_lower_shufflemask_undef:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d17, [r1]
@@ -276,8 +276,8 @@ define <8 x i16> @vzip_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) {
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
entry:
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 6, i32 3, i32 7>
ret <8 x i16> %0
}
@@ -285,7 +285,7 @@ entry:
; NOTE: The mask here looks like something that could be done with a vzip,
; but which the current handling of two-result vzip can't do - thus ending up
; as a vtrn.
-define <8 x i16> @vzip_lower_shufflemask_undef_rev(<4 x i16>* %A, <4 x i16>* %B) {
+define <8 x i16> @vzip_lower_shufflemask_undef_rev(ptr %A, ptr %B) {
; CHECK-LABEL: vzip_lower_shufflemask_undef_rev:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, [r1]
@@ -295,13 +295,13 @@ define <8 x i16> @vzip_lower_shufflemask_undef_rev(<4 x i16>* %A, <4 x i16>* %B)
; CHECK-NEXT: vmov r2, r3, d19
; CHECK-NEXT: mov pc, lr
entry:
- %tmp1 = load <4 x i16>, <4 x i16>* %A
- %tmp2 = load <4 x i16>, <4 x i16>* %B
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = load <4 x i16>, ptr %B
%0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 4, i32 undef, i32 undef>
ret <8 x i16> %0
}
-define <4 x i32> @vzip_lower_shufflemask_zeroed(<2 x i32>* %A) {
+define <4 x i32> @vzip_lower_shufflemask_zeroed(ptr %A) {
; CHECK-LABEL: vzip_lower_shufflemask_zeroed:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, [r0]
@@ -311,12 +311,12 @@ define <4 x i32> @vzip_lower_shufflemask_zeroed(<2 x i32>* %A) {
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
entry:
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp1, <4 x i32> <i32 0, i32 0, i32 1, i32 0>
ret <4 x i32> %0
}
-define <4 x i32> @vzip_lower_shufflemask_vuzp(<2 x i32>* %A) {
+define <4 x i32> @vzip_lower_shufflemask_vuzp(ptr %A) {
; CHECK-LABEL: vzip_lower_shufflemask_vuzp:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, [r0]
@@ -326,12 +326,12 @@ define <4 x i32> @vzip_lower_shufflemask_vuzp(<2 x i32>* %A) {
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
entry:
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp1, <4 x i32> <i32 0, i32 2, i32 1, i32 0>
ret <4 x i32> %0
}
-define void @vzip_undef_rev_shufflemask_vtrn(<2 x i32>* %A, <4 x i32>* %B) {
+define void @vzip_undef_rev_shufflemask_vtrn(ptr %A, ptr %B) {
; CHECK-LABEL: vzip_undef_rev_shufflemask_vtrn:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldr d16, [r0]
@@ -341,13 +341,13 @@ define void @vzip_undef_rev_shufflemask_vtrn(<2 x i32>* %A, <4 x i32>* %B) {
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
; CHECK-NEXT: mov pc, lr
entry:
- %tmp1 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, ptr %A
%0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 0>
- store <4 x i32> %0, <4 x i32>* %B
+ store <4 x i32> %0, ptr %B
ret void
}
-define void @vzip_vext_factor(<8 x i16>* %A, <4 x i16>* %B) {
+define void @vzip_vext_factor(ptr %A, ptr %B) {
; CHECK-LABEL: vzip_vext_factor:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
@@ -357,13 +357,13 @@ define void @vzip_vext_factor(<8 x i16>* %A, <4 x i16>* %B) {
; CHECK-NEXT: vstr d16, [r1]
; CHECK-NEXT: mov pc, lr
entry:
- %tmp1 = load <8 x i16>, <8 x i16>* %A
+ %tmp1 = load <8 x i16>, ptr %A
%0 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 4, i32 5, i32 3>
- store <4 x i16> %0, <4 x i16>* %B
+ store <4 x i16> %0, ptr %B
ret void
}
-define <8 x i8> @vdup_zip(i8* nocapture readonly %x, i8* nocapture readonly %y) {
+define <8 x i8> @vdup_zip(ptr nocapture readonly %x, ptr nocapture readonly %y) {
; CHECK-LABEL: vdup_zip:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld1.8 {d16[]}, [r1]
@@ -372,10 +372,10 @@ define <8 x i8> @vdup_zip(i8* nocapture readonly %x, i8* nocapture readonly %y)
; CHECK-NEXT: vmov r0, r1, d17
; CHECK-NEXT: mov pc, lr
entry:
- %0 = load i8, i8* %x, align 1
+ %0 = load i8, ptr %x, align 1
%1 = insertelement <8 x i8> undef, i8 %0, i32 0
%lane = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 undef, i32 undef, i32 undef, i32 undef>
- %2 = load i8, i8* %y, align 1
+ %2 = load i8, ptr %y, align 1
%3 = insertelement <8 x i8> undef, i8 %2, i32 0
%lane3 = shufflevector <8 x i8> %3, <8 x i8> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 undef, i32 undef, i32 undef, i32 undef>
%vzip.i = shufflevector <8 x i8> %lane, <8 x i8> %lane3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
diff --git a/llvm/test/CodeGen/ARM/weak2.ll b/llvm/test/CodeGen/ARM/weak2.ll
index a2911d780fef1..2b6099b67d2f9 100644
--- a/llvm/test/CodeGen/ARM/weak2.ll
+++ b/llvm/test/CodeGen/ARM/weak2.ll
@@ -3,8 +3,8 @@
define i32 @f(i32 %a) {
entry:
%tmp2 = icmp eq i32 %a, 0 ; <i1> [#uses=1]
- %t.0 = select i1 %tmp2, i32 (...)* null, i32 (...)* @test_weak ; <i32 (...)*> [#uses=2]
- %tmp5 = icmp eq i32 (...)* %t.0, null ; <i1> [#uses=1]
+ %t.0 = select i1 %tmp2, ptr null, ptr @test_weak ; <ptr> [#uses=2]
+ %tmp5 = icmp eq ptr %t.0, null ; <i1> [#uses=1]
br i1 %tmp5, label %UnifiedReturnBlock, label %cond_true8
cond_true8: ; preds = %entry
diff --git a/llvm/test/CodeGen/ARM/widen-vmovs.ll b/llvm/test/CodeGen/ARM/widen-vmovs.ll
index 2abf8d9701fc8..a91f87703c6eb 100644
--- a/llvm/test/CodeGen/ARM/widen-vmovs.ll
+++ b/llvm/test/CodeGen/ARM/widen-vmovs.ll
@@ -17,7 +17,7 @@ target triple = "thumbv7-apple-ios"
; - Register liveness is verified.
; - The execution domain switch to vorr works across basic blocks.
-define void @Mm(i32 %in, float* %addr) nounwind {
+define void @Mm(i32 %in, ptr %addr) nounwind {
entry:
br label %for.body4
@@ -31,6 +31,6 @@ for.body.i:
br i1 %exitcond.i, label %rInnerproduct.exit, label %for.body.i
rInnerproduct.exit:
- store float %add.i, float* %addr, align 4
+ store float %add.i, ptr %addr, align 4
br label %for.body4
}
diff --git a/llvm/test/CodeGen/ARM/win32-ssp.ll b/llvm/test/CodeGen/ARM/win32-ssp.ll
index 7f446e2de4049..084436f87c8fc 100644
--- a/llvm/test/CodeGen/ARM/win32-ssp.ll
+++ b/llvm/test/CodeGen/ARM/win32-ssp.ll
@@ -1,8 +1,8 @@
; RUN: llc -mtriple=thumbv7-w64-mingw32 < %s -o - | FileCheck --check-prefix=MINGW %s
-declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
-declare dso_local void @other(i8*)
-declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)
+declare void @llvm.lifetime.start.p0(i64, ptr nocapture)
+declare dso_local void @other(ptr)
+declare void @llvm.lifetime.end.p0(i64, ptr nocapture)
define dso_local void @func() sspstrong {
entry:
@@ -19,8 +19,8 @@ entry:
; MINGW: bl __stack_chk_fail
%c = alloca i8, align 1
- call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %c)
- call void @other(i8* nonnull %c)
- call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %c)
+ call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %c)
+ call void @other(ptr nonnull %c)
+ call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %c)
ret void
}
diff --git a/llvm/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll b/llvm/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll
index c49c47a086ff2..1c7fd454f2671 100644
--- a/llvm/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll
+++ b/llvm/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll
@@ -3,19 +3,19 @@
target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv7--linux-gnueabi"
-declare i8* @llvm.returnaddress(i32)
+declare ptr @llvm.returnaddress(i32)
-define i32* @wrong-t2stmia-size-reduction(i32* %addr, i32 %val0, i32 %val1) minsize {
- store i32 %val0, i32* %addr
- %addr1 = getelementptr i32, i32* %addr, i32 1
- %addr2 = getelementptr i32, i32* %addr, i32 2
- %lr = call i8* @llvm.returnaddress(i32 0)
- %lr32 = ptrtoint i8* %lr to i32
- store i32 %val1, i32* %addr1
- store i32 %lr32, i32* %addr2
+define ptr @wrong-t2stmia-size-reduction(ptr %addr, i32 %val0, i32 %val1) minsize {
+ store i32 %val0, ptr %addr
+ %addr1 = getelementptr i32, ptr %addr, i32 1
+ %addr2 = getelementptr i32, ptr %addr, i32 2
+ %lr = call ptr @llvm.returnaddress(i32 0)
+ %lr32 = ptrtoint ptr %lr to i32
+ store i32 %val1, ptr %addr1
+ store i32 %lr32, ptr %addr2
- %addr3 = getelementptr i32, i32* %addr, i32 3
- ret i32* %addr3
+ %addr3 = getelementptr i32, ptr %addr, i32 3
+ ret ptr %addr3
}
; Check that stm writes three registers. The bug caused one of registers (LR,
diff --git a/llvm/test/CodeGen/ARM/zext-logic-shift-load.ll b/llvm/test/CodeGen/ARM/zext-logic-shift-load.ll
index ab6bc7d572aec..73d57cfc82d2f 100644
--- a/llvm/test/CodeGen/ARM/zext-logic-shift-load.ll
+++ b/llvm/test/CodeGen/ARM/zext-logic-shift-load.ll
@@ -1,17 +1,17 @@
; RUN: llc -mtriple=armv7-linux-gnu < %s -o - | FileCheck %s
-define void @test1(i8* %p, i16* %q) {
+define void @test1(ptr %p, ptr %q) {
; CHECK: ldrb
; CHECK-NEXT: mov
; CHECK-NEXT: and
; CHECK-NEXT: strh
; CHECK-NEXT: bx
- %1 = load i8, i8* %p
+ %1 = load i8, ptr %p
%2 = shl i8 %1, 2
%3 = and i8 %2, 12
%4 = zext i8 %3 to i16
- store i16 %4, i16* %q
+ store i16 %4, ptr %q
ret void
}
diff --git a/llvm/test/CodeGen/ARM/zextload_demandedbits.ll b/llvm/test/CodeGen/ARM/zextload_demandedbits.ll
index 80f212e12035d..8519d30b7dabf 100644
--- a/llvm/test/CodeGen/ARM/zextload_demandedbits.ll
+++ b/llvm/test/CodeGen/ARM/zextload_demandedbits.ll
@@ -12,24 +12,23 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-
; CHECK: asr
; CHECK: bl
; CHECK: pop
-define void @quux(%struct.eggs* %arg) {
+define void @quux(ptr %arg) {
bb:
- %tmp1 = getelementptr inbounds %struct.eggs, %struct.eggs* %arg, i32 0, i32 1
- %0 = load i16, i16* %tmp1, align 2
+ %tmp1 = getelementptr inbounds %struct.eggs, ptr %arg, i32 0, i32 1
+ %0 = load i16, ptr %tmp1, align 2
%tobool = icmp eq i16 %0, 0
br i1 %tobool, label %bb16, label %bb3
bb3: ; preds = %bb
- %tmp4 = bitcast i16* %tmp1 to i8*
- %tmp5 = ptrtoint i16* %tmp1 to i32
+ %tmp5 = ptrtoint ptr %tmp1 to i32
%tmp6 = shl i32 %tmp5, 20
%tmp7 = ashr exact i32 %tmp6, 20
- %tmp14 = getelementptr inbounds %struct.barney, %struct.barney* undef, i32 %tmp7
- %tmp15 = tail call i32 @widget(%struct.barney* %tmp14, i8* %tmp4, i32 %tmp7)
+ %tmp14 = getelementptr inbounds %struct.barney, ptr undef, i32 %tmp7
+ %tmp15 = tail call i32 @widget(ptr %tmp14, ptr %tmp1, i32 %tmp7)
br label %bb16
bb16: ; preds = %bb3, %bb
ret void
}
-declare i32 @widget(%struct.barney*, i8*, i32)
+declare i32 @widget(ptr, ptr, i32)
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