[llvm] 45067d1 - [Bitcode] Convert tests to opaque pointers (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 19 02:23:25 PST 2022
Author: Nikita Popov
Date: 2022-12-19T11:23:17+01:00
New Revision: 45067d1a74c8409328332c0d60cfc71601bfc846
URL: https://github.com/llvm/llvm-project/commit/45067d1a74c8409328332c0d60cfc71601bfc846
DIFF: https://github.com/llvm/llvm-project/commit/45067d1a74c8409328332c0d60cfc71601bfc846.diff
LOG: [Bitcode] Convert tests to opaque pointers (NFC)
Added:
Modified:
llvm/test/Bitcode/function-nonzero-address-spaces-types.ll
llvm/test/Bitcode/function-nonzero-address-spaces.ll
llvm/test/Bitcode/thinlto-function-summary-callgraph-cast.ll
llvm/test/Bitcode/upgrade-invariant-group-barrier.ll
llvm/test/Bitcode/upgrade-masked-keep-metadata.ll
llvm/test/Bitcode/upgrade-memory-intrinsics.ll
Removed:
################################################################################
diff --git a/llvm/test/Bitcode/function-nonzero-address-spaces-types.ll b/llvm/test/Bitcode/function-nonzero-address-spaces-types.ll
index 6ef53e5e47f0..3a735cc3dbe3 100644
--- a/llvm/test/Bitcode/function-nonzero-address-spaces-types.ll
+++ b/llvm/test/Bitcode/function-nonzero-address-spaces-types.ll
@@ -4,20 +4,20 @@
; We should get a sensible error for a non-program address call:
; RUN: not llvm-as -data-layout "P39" %s -o /dev/null 2>&1 | FileCheck %s -check-prefix ERR-AS39
-; ERR-AS39: error: '%0' defined with type 'i16 (i16) addrspace(40)*' but expected 'i16 (i16) addrspace(39)*'
+; ERR-AS39: error: '%0' defined with type 'ptr addrspace(40)' but expected 'ptr addrspace(39)'
; And also if we don't set a custom program address space:
; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s -check-prefix ERR-AS0
-; ERR-AS0: error: '%0' defined with type 'i16 (i16) addrspace(40)*' but expected 'i16 (i16)*'
+; ERR-AS0: error: '%0' defined with type 'ptr addrspace(40)' but expected 'ptr'
%fun1 = type i16 (i16)
-%funptr1 = type %fun1 addrspace(40)*
+%funptr1 = type ptr addrspace(40)
@fun_ptr = global %funptr1 @fun
define i16 @fun(i16 %arg) addrspace(40) {
entry:
- %0 = load %funptr1, %funptr1* @fun_ptr
+ %0 = load %funptr1, ptr @fun_ptr
%result = call i16 %0(i16 %arg)
ret i16 %result
}
diff --git a/llvm/test/Bitcode/function-nonzero-address-spaces.ll b/llvm/test/Bitcode/function-nonzero-address-spaces.ll
index 54f6735f50ad..8748d0f42db4 100644
--- a/llvm/test/Bitcode/function-nonzero-address-spaces.ll
+++ b/llvm/test/Bitcode/function-nonzero-address-spaces.ll
@@ -4,26 +4,26 @@
; We should get a sensible error for a non-program address call:
; RUN: not llvm-as -data-layout "P39" %s -o /dev/null 2>&1 | FileCheck %s -check-prefix ERR-AS39
-; ERR-AS39: error: '%fnptr' defined with type 'void (i16) addrspace(40)*' but expected 'void (i16) addrspace(39)*'
+; ERR-AS39: error: '%fnptr' defined with type 'ptr addrspace(40)' but expected 'ptr addrspace(39)'
; And also if we don't set a custom program address space:
; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s -check-prefix ERR-AS0
-; ERR-AS0: error: '%fnptr' defined with type 'void (i16) addrspace(40)*' but expected 'void (i16)*'
+; ERR-AS0: error: '%fnptr' defined with type 'ptr addrspace(40)' but expected 'ptr'
-define void @f_named(i16 %n, void (i16) addrspace(40)* %f) addrspace(40) {
+define void @f_named(i16 %n, ptr addrspace(40) %f) addrspace(40) {
entry:
- %f.addr = alloca void (i16) addrspace(40)*, align 1
- store void (i16) addrspace(40)* %f, void (i16) addrspace(40)** %f.addr
- %fnptr = load void (i16) addrspace(40)*, void (i16) addrspace(40)** %f.addr
+ %f.addr = alloca ptr addrspace(40), align 1
+ store ptr addrspace(40) %f, ptr %f.addr
+ %fnptr = load ptr addrspace(40), ptr %f.addr
call void %fnptr(i16 8)
ret void
}
-define void @f_numbered(i16 %n, void (i16) addrspace(40)* %f) addrspace(40){
+define void @f_numbered(i16 %n, ptr addrspace(40) %f) addrspace(40){
entry:
- %f.addr = alloca void (i16) addrspace(40)*, align 1
- store void (i16) addrspace(40)* %f, void (i16) addrspace(40)** %f.addr
- %0 = load void (i16) addrspace(40)*, void (i16) addrspace(40)** %f.addr
+ %f.addr = alloca ptr addrspace(40), align 1
+ store ptr addrspace(40) %f, ptr %f.addr
+ %0 = load ptr addrspace(40), ptr %f.addr
call void %0(i16 8)
ret void
}
diff --git a/llvm/test/Bitcode/thinlto-function-summary-callgraph-cast.ll b/llvm/test/Bitcode/thinlto-function-summary-callgraph-cast.ll
index a0cd958eeaaa..1926603b8b1f 100644
--- a/llvm/test/Bitcode/thinlto-function-summary-callgraph-cast.ll
+++ b/llvm/test/Bitcode/thinlto-function-summary-callgraph-cast.ll
@@ -7,7 +7,7 @@
; CHECK-NEXT: <VERSION
; CHECK-NEXT: <FLAGS
; "op7" is a call to "callee" function.
-; CHECK-NEXT: <PERMODULE {{.*}} op9=3 op10=[[ALIASID:[0-9]+]]/>
+; CHECK-NEXT: <PERMODULE {{.*}} op7=3 op8=[[ALIASID:[0-9]+]]/>
; "another_caller" has only references but no calls.
; CHECK-NEXT: <PERMODULE {{.*}} op4=3 {{.*}} op9={{[0-9]+}}/>
; CHECK-NEXT: <PERMODULE {{.*}} op0=[[ALIASEEID:[0-9]+]]
@@ -20,20 +20,20 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
define void @caller() {
- call void bitcast (void (...)* @callee to void ()*)()
- call void bitcast (void (...)* @analias to void ()*)()
+ call void @callee()
+ call void @analias()
ret void
}
define void @another_caller() {
; Test calls that aren't handled either as direct or indirect.
- call void select (i1 icmp eq (i32* @global, i32* null), void ()* @f, void ()* @g)()
+ call void select (i1 icmp eq (ptr @global, ptr null), ptr @f, ptr @g)()
ret void
}
declare void @callee(...)
- at analias = alias void (...), bitcast (void ()* @aliasee to void (...)*)
+ at analias = alias void (...), ptr @aliasee
define void @aliasee() {
entry:
diff --git a/llvm/test/Bitcode/upgrade-invariant-group-barrier.ll b/llvm/test/Bitcode/upgrade-invariant-group-barrier.ll
index b9e3c4fb5d6b..f03c3bd565f9 100644
--- a/llvm/test/Bitcode/upgrade-invariant-group-barrier.ll
+++ b/llvm/test/Bitcode/upgrade-invariant-group-barrier.ll
@@ -1,22 +1,19 @@
; RUN: opt -S < %s | FileCheck %s
-; The intrinsic firstly only took i8*, then it was made polimorphic, then
+; The intrinsic firstly only took ptr, then it was made polimorphic, then
; it was renamed to launder.invariant.group
-define void @test(i8* %p1, i16* %p16) {
+define void @test(ptr %p1, ptr %p16) {
; CHECK-LABEL: @test
-; CHECK: %p2 = call i8* @llvm.launder.invariant.group.p0i8(i8* %p1)
-; CHECK: %p3 = call i8* @llvm.launder.invariant.group.p0i8(i8* %p1)
-; CHECK: %p4 = call i16* @llvm.launder.invariant.group.p0i16(i16* %p16)
- %p2 = call i8* @llvm.invariant.group.barrier(i8* %p1)
- %p3 = call i8* @llvm.invariant.group.barrier.p0i8(i8* %p1)
- %p4 = call i16* @llvm.invariant.group.barrier.p0i16(i16* %p16)
+; CHECK: %p2 = call ptr @llvm.launder.invariant.group.p0(ptr %p1)
+; CHECK: %p3 = call ptr @llvm.launder.invariant.group.p0(ptr %p1)
+; CHECK: %p4 = call ptr @llvm.launder.invariant.group.p0(ptr %p16)
+ %p2 = call ptr @llvm.invariant.group.barrier(ptr %p1)
+ %p3 = call ptr @llvm.invariant.group.barrier.p0(ptr %p1)
+ %p4 = call ptr @llvm.invariant.group.barrier.p0(ptr %p16)
ret void
}
; CHECK: Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(inaccessiblemem: readwrite)
-; CHECK: declare i8* @llvm.launder.invariant.group.p0i8(i8*)
-; CHECK: Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(inaccessiblemem: readwrite)
-; CHECK: declare i16* @llvm.launder.invariant.group.p0i16(i16*)
-declare i8* @llvm.invariant.group.barrier(i8*)
-declare i8* @llvm.invariant.group.barrier.p0i8(i8*)
-declare i16* @llvm.invariant.group.barrier.p0i16(i16*)
+; CHECK: declare ptr @llvm.launder.invariant.group.p0(ptr)
+declare ptr @llvm.invariant.group.barrier(ptr)
+declare ptr @llvm.invariant.group.barrier.p0(ptr)
diff --git a/llvm/test/Bitcode/upgrade-masked-keep-metadata.ll b/llvm/test/Bitcode/upgrade-masked-keep-metadata.ll
index f3c52776cacb..0bcdfed80881 100644
--- a/llvm/test/Bitcode/upgrade-masked-keep-metadata.ll
+++ b/llvm/test/Bitcode/upgrade-masked-keep-metadata.ll
@@ -1,77 +1,77 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S < %s | FileCheck %s
-define <4 x i32> @load(<4 x i32>* nocapture readonly %a0) !dbg !8 {
+define <4 x i32> @load(ptr nocapture readonly %a0) !dbg !8 {
; CHECK-LABEL: @load(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[V0:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* [[A0:%.*]], i32 16, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> undef), !dbg [[DBG19:![0-9]+]], !tbaa [[TBAA20:![0-9]+]]
+; CHECK-NEXT: [[V0:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[A0:%.*]], i32 16, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> undef), !dbg [[DBG19:![0-9]+]], !tbaa [[TBAA20:![0-9]+]]
; CHECK-NEXT: ret <4 x i32> [[V0]], !dbg [[DBG23:![0-9]+]]
;
entry:
- %v0 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %a0, i32 16, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> undef), !dbg !19, !tbaa !20
+ %v0 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %a0, i32 16, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> undef), !dbg !19, !tbaa !20
ret <4 x i32> %v0, !dbg !23
}
-define void @store(<4 x i32> %a0, <4 x i32>* nocapture %a1) !dbg !24 {
+define void @store(<4 x i32> %a0, ptr nocapture %a1) !dbg !24 {
; CHECK-LABEL: @store(
; CHECK-NEXT: entry:
-; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[A0:%.*]], <4 x i32>* [[A1:%.*]], i32 16, <4 x i1> <i1 false, i1 true, i1 false, i1 true>), !dbg [[DBG30:![0-9]+]], !tbaa [[TBAA20]]
+; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[A0:%.*]], ptr [[A1:%.*]], i32 16, <4 x i1> <i1 false, i1 true, i1 false, i1 true>), !dbg [[DBG30:![0-9]+]], !tbaa [[TBAA20]]
; CHECK-NEXT: ret void, !dbg [[DBG31:![0-9]+]]
;
entry:
- call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %a0, <4 x i32>* %a1, i32 16, <4 x i1> <i1 false, i1 true, i1 false, i1 true>), !dbg !30, !tbaa !20
+ call void @llvm.masked.store.v4i32.p0(<4 x i32> %a0, ptr %a1, i32 16, <4 x i1> <i1 false, i1 true, i1 false, i1 true>), !dbg !30, !tbaa !20
ret void, !dbg !31
}
-define <4 x i32> @gather(<4 x i32*> %a0) !dbg !32 {
+define <4 x i32> @gather(<4 x ptr> %a0) !dbg !32 {
; CHECK-LABEL: @gather(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[V0:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[A0:%.*]], i32 16, <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i32> undef), !dbg [[DBG35:![0-9]+]], !tbaa [[TBAA20]]
+; CHECK-NEXT: [[V0:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> [[A0:%.*]], i32 16, <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i32> undef), !dbg [[DBG35:![0-9]+]], !tbaa [[TBAA20]]
; CHECK-NEXT: ret <4 x i32> [[V0]], !dbg [[DBG36:![0-9]+]]
;
entry:
- %v0 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %a0, i32 16, <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i32> undef), !dbg !35, !tbaa !20
+ %v0 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %a0, i32 16, <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i32> undef), !dbg !35, !tbaa !20
ret <4 x i32> %v0, !dbg !36
}
-define void @scatter(<4 x i32> %a0, <4 x i32*> %a1) !dbg !37 {
+define void @scatter(<4 x i32> %a0, <4 x ptr> %a1) !dbg !37 {
; CHECK-LABEL: @scatter(
; CHECK-NEXT: entry:
-; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> [[A0:%.*]], <4 x i32*> [[A1:%.*]], i32 16, <4 x i1> <i1 false, i1 true, i1 true, i1 true>), !dbg [[DBG41:![0-9]+]], !tbaa [[TBAA20]]
+; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> [[A0:%.*]], <4 x ptr> [[A1:%.*]], i32 16, <4 x i1> <i1 false, i1 true, i1 true, i1 true>), !dbg [[DBG41:![0-9]+]], !tbaa [[TBAA20]]
; CHECK-NEXT: ret void, !dbg [[DBG42:![0-9]+]]
;
entry:
- call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %a0, <4 x i32*> %a1, i32 16, <4 x i1> <i1 false, i1 true, i1 true, i1 true>), !dbg !41, !tbaa !20
+ call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a0, <4 x ptr> %a1, i32 16, <4 x i1> <i1 false, i1 true, i1 true, i1 true>), !dbg !41, !tbaa !20
ret void, !dbg !42
}
-define <4 x i32> @expandload(i32* nocapture readonly %a0) !dbg !43 {
+define <4 x i32> @expandload(ptr nocapture readonly %a0) !dbg !43 {
; CHECK-LABEL: @expandload(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[V0:%.*]] = call <4 x i32> @llvm.masked.expandload.v4i32(i32* [[A0:%.*]], <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> undef), !dbg [[DBG49:![0-9]+]], !tbaa [[TBAA50:![0-9]+]]
+; CHECK-NEXT: [[V0:%.*]] = call <4 x i32> @llvm.masked.expandload.v4i32(ptr [[A0:%.*]], <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> undef), !dbg [[DBG49:![0-9]+]], !tbaa [[TBAA50:![0-9]+]]
; CHECK-NEXT: ret <4 x i32> [[V0]], !dbg [[DBG52:![0-9]+]]
;
entry:
- %v0 = call <4 x i32> @llvm.masked.expandload.v4i32(i32* %a0, <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> undef), !dbg !49, !tbaa !50
+ %v0 = call <4 x i32> @llvm.masked.expandload.v4i32(ptr %a0, <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> undef), !dbg !49, !tbaa !50
ret <4 x i32> %v0, !dbg !52
}
-define void @compressstore(<4 x i32> %a0, i32* nocapture %a1) !dbg !53 {
+define void @compressstore(<4 x i32> %a0, ptr nocapture %a1) !dbg !53 {
; CHECK-LABEL: @compressstore(
; CHECK-NEXT: entry:
-; CHECK-NEXT: call void @llvm.masked.compressstore.v4i32(<4 x i32> [[A0:%.*]], i32* [[A1:%.*]], <4 x i1> <i1 false, i1 false, i1 true, i1 true>), !dbg [[DBG59:![0-9]+]], !tbaa [[TBAA50]]
+; CHECK-NEXT: call void @llvm.masked.compressstore.v4i32(<4 x i32> [[A0:%.*]], ptr [[A1:%.*]], <4 x i1> <i1 false, i1 false, i1 true, i1 true>), !dbg [[DBG59:![0-9]+]], !tbaa [[TBAA50]]
; CHECK-NEXT: ret void, !dbg [[DBG60:![0-9]+]]
;
entry:
- call void @llvm.masked.compressstore.v4i32(<4 x i32> %a0, i32* %a1, <4 x i1> <i1 false, i1 false, i1 true, i1 true>), !dbg !59, !tbaa !50
+ call void @llvm.masked.compressstore.v4i32(<4 x i32> %a0, ptr %a1, <4 x i1> <i1 false, i1 false, i1 true, i1 true>), !dbg !59, !tbaa !50
ret void, !dbg !60
}
-declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #0
-declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) #1
-declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32 immarg, <4 x i1>, <4 x i32>) #2
-declare void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>, <4 x i32*>, i32 immarg, <4 x i1>) #3
-declare <4 x i32> @llvm.masked.expandload.v4i32(i32*, <4 x i1>, <4 x i32>) #2
-declare void @llvm.masked.compressstore.v4i32(<4 x i32>, i32*, <4 x i1>) #1
+declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) #0
+declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>) #1
+declare <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr>, i32 immarg, <4 x i1>, <4 x i32>) #2
+declare void @llvm.masked.scatter.v4i32.v4p0(<4 x i32>, <4 x ptr>, i32 immarg, <4 x i1>) #3
+declare <4 x i32> @llvm.masked.expandload.v4i32(ptr, <4 x i1>, <4 x i32>) #2
+declare void @llvm.masked.compressstore.v4i32(<4 x i32>, ptr, <4 x i1>) #1
attributes #0 = { argmemonly nofree nosync nounwind readonly willreturn }
attributes #1 = { argmemonly nofree nosync nounwind willreturn writeonly }
diff --git a/llvm/test/Bitcode/upgrade-memory-intrinsics.ll b/llvm/test/Bitcode/upgrade-memory-intrinsics.ll
index 57a41f2f0465..27c8d3668b40 100644
--- a/llvm/test/Bitcode/upgrade-memory-intrinsics.ll
+++ b/llvm/test/Bitcode/upgrade-memory-intrinsics.ll
@@ -4,45 +4,45 @@
; to remove the alignment parameter in favour of align attributes on the pointer args.
; Make sure a non-zero alignment is propagated
-define void @test(i8* %p1, i8* %p2, i8* %p3) {
+define void @test(ptr %p1, ptr %p2, ptr %p3) {
; CHECK-LABEL: @test
-; CHECK: call void @llvm.memset.p0i8.i64(i8* align 4 %p1, i8 55, i64 100, i1 false)
-; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %p1, i8* align 4 %p2, i64 50, i1 false)
-; CHECK: call void @llvm.memmove.p0i8.p0i8.i64(i8* align 4 %p2, i8* align 4 %p3, i64 1000, i1 false)
- call void @llvm.memset.p0i8.i64(i8* %p1, i8 55, i64 100, i32 4, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p1, i8* %p2, i64 50, i32 4, i1 false)
- call void @llvm.memmove.p0i8.p0i8.i64(i8* %p2, i8* %p3, i64 1000, i32 4, i1 false)
+; CHECK: call void @llvm.memset.p0.i64(ptr align 4 %p1, i8 55, i64 100, i1 false)
+; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 4 %p1, ptr align 4 %p2, i64 50, i1 false)
+; CHECK: call void @llvm.memmove.p0.p0.i64(ptr align 4 %p2, ptr align 4 %p3, i64 1000, i1 false)
+ call void @llvm.memset.p0.i64(ptr %p1, i8 55, i64 100, i32 4, i1 false)
+ call void @llvm.memcpy.p0.p0.i64(ptr %p1, ptr %p2, i64 50, i32 4, i1 false)
+ call void @llvm.memmove.p0.p0.i64(ptr %p2, ptr %p3, i64 1000, i32 4, i1 false)
ret void
}
; Make sure that a zero alignment is handled properly
-define void @test2(i8* %p1, i8* %p2, i8* %p3) {
+define void @test2(ptr %p1, ptr %p2, ptr %p3) {
; CHECK-LABEL: @test
-; CHECK: call void @llvm.memset.p0i8.i64(i8* %p1, i8 55, i64 100, i1 false)
-; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p1, i8* %p2, i64 50, i1 false)
-; CHECK: call void @llvm.memmove.p0i8.p0i8.i64(i8* %p2, i8* %p3, i64 1000, i1 false)
- call void @llvm.memset.p0i8.i64(i8* %p1, i8 55, i64 100, i32 0, i1 false)
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p1, i8* %p2, i64 50, i32 0, i1 false)
- call void @llvm.memmove.p0i8.p0i8.i64(i8* %p2, i8* %p3, i64 1000, i32 0, i1 false)
+; CHECK: call void @llvm.memset.p0.i64(ptr %p1, i8 55, i64 100, i1 false)
+; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr %p1, ptr %p2, i64 50, i1 false)
+; CHECK: call void @llvm.memmove.p0.p0.i64(ptr %p2, ptr %p3, i64 1000, i1 false)
+ call void @llvm.memset.p0.i64(ptr %p1, i8 55, i64 100, i32 0, i1 false)
+ call void @llvm.memcpy.p0.p0.i64(ptr %p1, ptr %p2, i64 50, i32 0, i1 false)
+ call void @llvm.memmove.p0.p0.i64(ptr %p2, ptr %p3, i64 1000, i32 0, i1 false)
ret void
}
; Make sure that attributes are not dropped
-define void @test3(i8* %p1, i8* %p2, i8* %p3) {
+define void @test3(ptr %p1, ptr %p2, ptr %p3) {
; CHECK-LABEL: @test
-; CHECK: call void @llvm.memset.p0i8.i64(i8* nonnull align 4 %p1, i8 signext 55, i64 zeroext 100, i1 immarg false)
-; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 4 %p1, i8* readonly align 4 %p2, i64 zeroext 50, i1 immarg false)
-; CHECK: call void @llvm.memmove.p0i8.p0i8.i64(i8* nonnull align 4 %p2, i8* readonly align 4 %p3, i64 zeroext 1000, i1 immarg false)
- call void @llvm.memset.p0i8.i64(i8* nonnull %p1, i8 signext 55, i64 zeroext 100, i32 signext 4, i1 immarg false)
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull %p1, i8* readonly %p2, i64 zeroext 50, i32 signext 4, i1 immarg false)
- call void @llvm.memmove.p0i8.p0i8.i64(i8* nonnull %p2, i8* readonly %p3, i64 zeroext 1000, i32 signext 4, i1 immarg false)
+; CHECK: call void @llvm.memset.p0.i64(ptr nonnull align 4 %p1, i8 signext 55, i64 zeroext 100, i1 immarg false)
+; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr nonnull align 4 %p1, ptr readonly align 4 %p2, i64 zeroext 50, i1 immarg false)
+; CHECK: call void @llvm.memmove.p0.p0.i64(ptr nonnull align 4 %p2, ptr readonly align 4 %p3, i64 zeroext 1000, i1 immarg false)
+ call void @llvm.memset.p0.i64(ptr nonnull %p1, i8 signext 55, i64 zeroext 100, i32 signext 4, i1 immarg false)
+ call void @llvm.memcpy.p0.p0.i64(ptr nonnull %p1, ptr readonly %p2, i64 zeroext 50, i32 signext 4, i1 immarg false)
+ call void @llvm.memmove.p0.p0.i64(ptr nonnull %p2, ptr readonly %p3, i64 zeroext 1000, i32 signext 4, i1 immarg false)
ret void
}
-; CHECK: declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1 immarg)
-; CHECK: declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg)
-; CHECK: declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1 immarg)
-declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i32, i1)
-declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly , i8* nocapture readonly, i64, i32, i1)
-declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1)
+; CHECK: declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg)
+; CHECK: declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg)
+; CHECK: declare void @llvm.memmove.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1 immarg)
+declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i32, i1)
+declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly , ptr nocapture readonly, i64, i32, i1)
+declare void @llvm.memmove.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32, i1)
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