[PATCH] D139394: [RISCV] Add codegen support for RISCV XVentanaCondOps Extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td:52
+def: Pat<(select i64:$rc, (and i64:$rs1, i64:$rs2), i64:$rs1),
+         (OR (AND $rs1, $rs2), (VT_MASKC $rs1, $rc))>;
+def: Pat<(select i64:$rc, i64:$rs1, (and i64:$rs1, i64:$rs2)),
----------------
I think the VT_MASKC and VT_MASKCN are swapped in these patterns?


================
Comment at: llvm/test/CodeGen/RISCV/xventanacondops.ll:197
+; CHECK-NEXT:    and a2, a1, a2
+; CHECK-NEXT:    vt.maskc a0, a1, a0
+; CHECK-NEXT:    or a0, a2, a0
----------------
I believe this corresponds to "Conditional bitwise-and, if non-zero" in the spec which should have this assembly

```
and rd, rs1, rs2
vt.maskcn rtmp, rs1, rc
or rd, rd, rtmp
```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139394/new/

https://reviews.llvm.org/D139394