[llvm] a40ef65 - [Intrinsic] Rename flt.rounds intrinsic to get.rounding
Qiu Chaofan via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 18 23:23:40 PST 2022
Author: Qiu Chaofan
Date: 2022-12-19T15:22:39+08:00
New Revision: a40ef656d812143d24c810c65ebf6b24646837f0
URL: https://github.com/llvm/llvm-project/commit/a40ef656d812143d24c810c65ebf6b24646837f0
DIFF: https://github.com/llvm/llvm-project/commit/a40ef656d812143d24c810c65ebf6b24646837f0.diff
LOG: [Intrinsic] Rename flt.rounds intrinsic to get.rounding
Address the inconsistency between FLT_ROUNDS_ and SET_ROUNDING SDAG
node. Rename FLT_ROUNDS_ to GET_ROUNDING and add llvm.get.rounding
intrinsic to replace flt.rounds.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D139507
Added:
llvm/test/Bitcode/Inputs/auto_upgrade_flt_rounds.bc
llvm/test/Bitcode/auto_upgrade_flt_rounds.test
Modified:
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-msp430.c
clang/test/CodeGen/builtins.c
llvm/docs/LangRef.rst
llvm/include/llvm/CodeGen/ISDOpcodes.h
llvm/include/llvm/IR/Intrinsics.td
llvm/lib/CodeGen/IntrinsicLowering.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
llvm/lib/IR/AutoUpgrade.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.h
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.h
llvm/test/CodeGen/AArch64/arm64-fpcr.ll
llvm/test/CodeGen/AArch64/strict-fp-opt.ll
llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll
llvm/test/CodeGen/ARM/fpscr-intrinsics.ll
llvm/test/CodeGen/ARM/no-fpscr-liveness.ll
llvm/test/CodeGen/MSP430/flt_rounds.ll
llvm/test/CodeGen/PowerPC/frounds.ll
llvm/test/CodeGen/RISCV/flt-rounds.ll
llvm/test/CodeGen/RISCV/fpenv.ll
llvm/test/CodeGen/X86/flt-rounds.ll
Removed:
################################################################################
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 55aa9f6acd0fe..a9f7d501fc902 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -3325,7 +3325,7 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
}
case Builtin::BI__builtin_flt_rounds: {
- Function *F = CGM.getIntrinsic(Intrinsic::flt_rounds);
+ Function *F = CGM.getIntrinsic(Intrinsic::get_rounding);
llvm::Type *ResultType = ConvertType(E->getType());
Value *Result = Builder.CreateCall(F);
diff --git a/clang/test/CodeGen/builtins-msp430.c b/clang/test/CodeGen/builtins-msp430.c
index 8fb409b66646d..c9d7615014b78 100644
--- a/clang/test/CodeGen/builtins-msp430.c
+++ b/clang/test/CodeGen/builtins-msp430.c
@@ -2,7 +2,7 @@
// RUN: %clang_cc1 -triple msp430-unknown-unknown -emit-llvm %s -o - | FileCheck %s
int test_builtin_flt_rounds() {
- // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.flt.rounds()
+ // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.get.rounding()
// CHECK-DAG: [[V1:[%A-Za-z0-9.]+]] = trunc i32 [[V0]] to i16
// CHECK-DAG: ret i16 [[V1]]
return __builtin_flt_rounds();
diff --git a/clang/test/CodeGen/builtins.c b/clang/test/CodeGen/builtins.c
index 9420b26da3290..21e14cc9c08c0 100644
--- a/clang/test/CodeGen/builtins.c
+++ b/clang/test/CodeGen/builtins.c
@@ -277,7 +277,7 @@ void test_float_builtins(__fp16 *H, float F, double D, long double LD) {
// CHECK: and i1
res = __builtin_flt_rounds();
- // CHECK: call i32 @llvm.flt.rounds(
+ // CHECK: call i32 @llvm.get.rounding(
}
// CHECK-LABEL: define{{.*}} void @test_float_builtin_ops
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index c816355bf9fab..2011d17ea3be6 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -24598,7 +24598,7 @@ These functions read or write floating point environment, such as rounding
mode or state of floating point exceptions. Altering the floating point
environment requires special care. See :ref:`Floating Point Environment <floatenv>`.
-'``llvm.flt.rounds``' Intrinsic
+'``llvm.get.rounding``' Intrinsic
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Syntax:
@@ -24606,17 +24606,17 @@ Syntax:
::
- declare i32 @llvm.flt.rounds()
+ declare i32 @llvm.get.rounding()
Overview:
"""""""""
-The '``llvm.flt.rounds``' intrinsic reads the current rounding mode.
+The '``llvm.get.rounding``' intrinsic reads the current rounding mode.
Semantics:
""""""""""
-The '``llvm.flt.rounds``' intrinsic returns the current rounding mode.
+The '``llvm.get.rounding``' intrinsic returns the current rounding mode.
Encoding of the returned values is same as the result of ``FLT_ROUNDS``,
specified by C standard:
@@ -24631,7 +24631,6 @@ specified by C standard:
Other values may be used to represent additional rounding modes, supported by a
target. These values are target-specific.
-
'``llvm.set.rounding``' Intrinsic
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -24651,7 +24650,7 @@ Arguments:
""""""""""
The argument is the required rounding mode. Encoding of rounding mode is
-the same as used by '``llvm.flt.rounds``'.
+the same as used by '``llvm.get.rounding``'.
Semantics:
""""""""""
diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index f4dee09672398..0a02a2cd768f0 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -859,12 +859,11 @@ enum NodeType {
/// 3 Round to -inf
/// 4 Round to nearest, ties to zero
/// Result is rounding mode and chain. Input is a chain.
- /// TODO: Rename this node to GET_ROUNDING.
- FLT_ROUNDS_,
+ GET_ROUNDING,
/// Set rounding mode.
/// The first operand is a chain pointer. The second specifies the required
- /// rounding mode, encoded in the same way as used in '``FLT_ROUNDS_``'.
+ /// rounding mode, encoded in the same way as used in '``GET_ROUNDING``'.
SET_ROUNDING,
/// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index cb21d45f45cd2..7bd27674a80b6 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -755,7 +755,7 @@ def int_objectsize : DefaultAttrsIntrinsic<[llvm_anyint_ty],
//
let IntrProperties = [IntrInaccessibleMemOnly, IntrWillReturn] in {
- def int_flt_rounds : DefaultAttrsIntrinsic<[llvm_i32_ty], []>;
+ def int_get_rounding : DefaultAttrsIntrinsic<[llvm_i32_ty], []>;
def int_set_rounding : DefaultAttrsIntrinsic<[], [llvm_i32_ty]>;
}
diff --git a/llvm/lib/CodeGen/IntrinsicLowering.cpp b/llvm/lib/CodeGen/IntrinsicLowering.cpp
index 808a79d9792a5..61920a0e04ab5 100644
--- a/llvm/lib/CodeGen/IntrinsicLowering.cpp
+++ b/llvm/lib/CodeGen/IntrinsicLowering.cpp
@@ -430,7 +430,7 @@ void IntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
ReplaceFPIntrinsicWithCall(CI, "copysignf", "copysign", "copysignl");
break;
}
- case Intrinsic::flt_rounds:
+ case Intrinsic::get_rounding:
// Lower to "round to the nearest"
if (!CI->getType()->isVoidTy())
CI->replaceAllUsesWith(ConstantInt::get(CI->getType(), 1));
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index cf4c40e648c26..534b3f5ae1a59 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1078,7 +1078,7 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
SimpleFinishLegalizing = false;
break;
case ISD::EXTRACT_ELEMENT:
- case ISD::FLT_ROUNDS_:
+ case ISD::GET_ROUNDING:
case ISD::MERGE_VALUES:
case ISD::EH_RETURN:
case ISD::FRAME_TO_ARGS_OFFSET:
@@ -2741,7 +2741,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
FA, Offset));
break;
}
- case ISD::FLT_ROUNDS_:
+ case ISD::GET_ROUNDING:
Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
Results.push_back(Node->getOperand(0));
break;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index f262b97f27c57..869a537df616b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -153,7 +153,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
Res = PromoteIntRes_FP_TO_FP16_BF16(N);
break;
- case ISD::FLT_ROUNDS_: Res = PromoteIntRes_FLT_ROUNDS(N); break;
+ case ISD::GET_ROUNDING: Res = PromoteIntRes_GET_ROUNDING(N); break;
case ISD::AND:
case ISD::OR:
@@ -730,7 +730,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16_BF16(SDNode *N) {
return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
}
-SDValue DAGTypeLegalizer::PromoteIntRes_FLT_ROUNDS(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteIntRes_GET_ROUNDING(SDNode *N) {
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
SDLoc dl(N);
@@ -2428,7 +2428,7 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
case ISD::CTTZ_ZERO_UNDEF:
case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
- case ISD::FLT_ROUNDS_: ExpandIntRes_FLT_ROUNDS(N, Lo, Hi); break;
+ case ISD::GET_ROUNDING:ExpandIntRes_GET_ROUNDING(N, Lo, Hi); break;
case ISD::STRICT_FP_TO_SINT:
case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
case ISD::STRICT_FP_TO_UINT:
@@ -3388,15 +3388,15 @@ void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
Hi = DAG.getConstant(0, dl, NVT);
}
-void DAGTypeLegalizer::ExpandIntRes_FLT_ROUNDS(SDNode *N, SDValue &Lo,
+void DAGTypeLegalizer::ExpandIntRes_GET_ROUNDING(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDLoc dl(N);
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
unsigned NBitWidth = NVT.getSizeInBits();
- Lo = DAG.getNode(ISD::FLT_ROUNDS_, dl, {NVT, MVT::Other}, N->getOperand(0));
+ Lo = DAG.getNode(ISD::GET_ROUNDING, dl, {NVT, MVT::Other}, N->getOperand(0));
SDValue Chain = Lo.getValue(1);
- // The high part is the sign of Lo, as -1 is a valid value for FLT_ROUNDS
+ // The high part is the sign of Lo, as -1 is a valid value for GET_ROUNDING
Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
DAG.getShiftAmountConstant(NBitWidth - 1, NVT, dl));
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index d2fc382a59a7a..e57a030fe143f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -354,7 +354,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntRes_ADDSUBSHLSAT(SDNode *N);
SDValue PromoteIntRes_MULFIX(SDNode *N);
SDValue PromoteIntRes_DIVFIX(SDNode *N);
- SDValue PromoteIntRes_FLT_ROUNDS(SDNode *N);
+ SDValue PromoteIntRes_GET_ROUNDING(SDNode *N);
SDValue PromoteIntRes_VECREDUCE(SDNode *N);
SDValue PromoteIntRes_VP_REDUCE(SDNode *N);
SDValue PromoteIntRes_ABS(SDNode *N);
@@ -437,7 +437,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void ExpandIntRes_SIGN_EXTEND_INREG (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_TRUNCATE (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_ZERO_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
- void ExpandIntRes_FLT_ROUNDS (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_GET_ROUNDING (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_FP_TO_SINT (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_FP_TO_UINT (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_FP_TO_XINT_SAT (SDNode *N, SDValue &Lo, SDValue &Hi);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 17be6c9b80307..5554973d86a56 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -6826,8 +6826,8 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
case Intrinsic::gcread:
case Intrinsic::gcwrite:
llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
- case Intrinsic::flt_rounds:
- Res = DAG.getNode(ISD::FLT_ROUNDS_, sdl, {MVT::i32, MVT::Other}, getRoot());
+ case Intrinsic::get_rounding:
+ Res = DAG.getNode(ISD::GET_ROUNDING, sdl, {MVT::i32, MVT::Other}, getRoot());
setValue(&I, Res);
DAG.setRoot(Res.getValue(1));
return;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
index 74092d938eb73..15611751af96d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
@@ -422,7 +422,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
return "call_alloc";
// Floating point environment manipulation
- case ISD::FLT_ROUNDS_: return "flt_rounds";
+ case ISD::GET_ROUNDING: return "get_rounding";
case ISD::SET_ROUNDING: return "set_rounding";
// Bit manipulation
diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp
index 9a4e6f7af67a4..d7977766e4765 100644
--- a/llvm/lib/IR/AutoUpgrade.cpp
+++ b/llvm/lib/IR/AutoUpgrade.cpp
@@ -908,6 +908,13 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
}
break;
}
+ case 'f':
+ if (Name.startswith("flt.rounds")) {
+ rename(F);
+ NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::get_rounding);
+ return true;
+ }
+ break;
case 'i':
case 'l': {
bool IsLifetimeStart = Name.startswith("lifetime.start");
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index ae4b90450875c..c0887ec05c028 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -740,7 +740,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
- setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
+ setOperationAction(ISD::GET_ROUNDING, MVT::i32, Custom);
setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
@@ -4468,8 +4468,8 @@ static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
return false;
}
-SDValue AArch64TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
- SelectionDAG &DAG) const {
+SDValue AArch64TargetLowering::LowerGET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
// The rounding mode is in bits 23:22 of the FPSCR.
// The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
// The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
@@ -5934,8 +5934,8 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
return LowerFP_TO_INT_SAT(Op, DAG);
case ISD::FSINCOS:
return LowerFSINCOS(Op, DAG);
- case ISD::FLT_ROUNDS_:
- return LowerFLT_ROUNDS_(Op, DAG);
+ case ISD::GET_ROUNDING:
+ return LowerGET_ROUNDING(Op, DAG);
case ISD::SET_ROUNDING:
return LowerSET_ROUNDING(Op, DAG);
case ISD::MUL:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 2869604815a78..8547fd4e968ea 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1033,7 +1033,7 @@ class AArch64TargetLowering : public TargetLowering {
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 76310611bdcf6..dcc91e4857c27 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1397,7 +1397,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
// Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
// iff target supports vfp2.
setOperationAction(ISD::BITCAST, MVT::i64, Custom);
- setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
+ setOperationAction(ISD::GET_ROUNDING, MVT::i32, Custom);
setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
}
@@ -6372,8 +6372,8 @@ SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
return DAG.getMergeValues(Ops, dl);
}
-SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
- SelectionDAG &DAG) const {
+SDValue ARMTargetLowering::LowerGET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
// The rounding mode is in bits 23:22 of the FPSCR.
// The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
// The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
@@ -10416,7 +10416,7 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::TRUNCATE: return LowerTruncate(Op.getNode(), DAG, Subtarget);
case ISD::SIGN_EXTEND:
case ISD::ZERO_EXTEND: return LowerVectorExtend(Op.getNode(), DAG, Subtarget);
- case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
+ case ISD::GET_ROUNDING: return LowerGET_ROUNDING(Op, DAG);
case ISD::SET_ROUNDING: return LowerSET_ROUNDING(Op, DAG);
case ISD::MUL: return LowerMUL(Op, DAG);
case ISD::SDIV:
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 18ad564e11775..41e66739f571c 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -829,7 +829,7 @@ class VectorType;
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) const;
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index b13d0da227f50..cb49b0a74c8f9 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -419,7 +419,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
if (Subtarget.hasSPE())
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
- setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
+ setOperationAction(ISD::GET_ROUNDING, MVT::i32, Custom);
// If we're enabling GP optimizations, use hardware square root
if (!Subtarget.hasFSQRT() &&
@@ -8752,8 +8752,8 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
-SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
- SelectionDAG &DAG) const {
+SDValue PPCTargetLowering::LowerGET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
SDLoc dl(Op);
/*
The rounding mode is in bits 30:31 of FPSR, and has the following
@@ -8763,7 +8763,7 @@ SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10 Round to +inf
11 Round to -inf
- FLT_ROUNDS, on the other hand, expects the following:
+ GET_ROUNDING, on the other hand, expects the following:
-1 Undefined
0 Round to 0
1 Round to nearest
@@ -11339,7 +11339,7 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::STRICT_SINT_TO_FP:
case ISD::UINT_TO_FP:
case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
- case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
+ case ISD::GET_ROUNDING: return LowerGET_ROUNDING(Op, DAG);
// Lower 64-bit shifts.
case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index d46260eda7ace..b80479427c2e4 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -1285,7 +1285,7 @@ namespace llvm {
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
const SDLoc &dl) const;
SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index be0980f03a452..507ebff9ad4b1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -439,7 +439,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP},
XLenVT, Legal);
- setOperationAction(ISD::FLT_ROUNDS_, XLenVT, Custom);
+ setOperationAction(ISD::GET_ROUNDING, XLenVT, Custom);
setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
}
@@ -4175,7 +4175,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::MSCATTER:
case ISD::VP_SCATTER:
return lowerMaskedScatter(Op, DAG);
- case ISD::FLT_ROUNDS_:
+ case ISD::GET_ROUNDING:
return lowerGET_ROUNDING(Op, DAG);
case ISD::SET_ROUNDING:
return lowerSET_ROUNDING(Op, DAG);
@@ -8028,9 +8028,9 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
if (SDValue V = lowerVPREDUCE(SDValue(N, 0), DAG))
Results.push_back(V);
break;
- case ISD::FLT_ROUNDS_: {
+ case ISD::GET_ROUNDING: {
SDVTList VTs = DAG.getVTList(Subtarget.getXLenVT(), MVT::Other);
- SDValue Res = DAG.getNode(ISD::FLT_ROUNDS_, DL, VTs, N->getOperand(0));
+ SDValue Res = DAG.getNode(ISD::GET_ROUNDING, DL, VTs, N->getOperand(0));
Results.push_back(Res.getValue(0));
Results.push_back(Res.getValue(1));
break;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 16fa4401bb74d..f4e4e81c83a1b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -364,7 +364,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::FREM , MVT::f128 , Expand);
if (!Subtarget.useSoftFloat() && Subtarget.hasX87()) {
- setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
+ setOperationAction(ISD::GET_ROUNDING , MVT::i32 , Custom);
setOperationAction(ISD::SET_ROUNDING , MVT::Other, Custom);
}
@@ -28953,8 +28953,8 @@ SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
}
}
-SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
- SelectionDAG &DAG) const {
+SDValue X86TargetLowering::LowerGET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
/*
The rounding mode is in bits 11:10 of FPSR, and has the following
settings:
@@ -28963,7 +28963,7 @@ SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10 Round to +inf
11 Round to 0
- FLT_ROUNDS, on the other hand, expects the following:
+ GET_ROUNDING, on the other hand, expects the following:
-1 Undefined
0 Round to 0
1 Round to nearest
@@ -32986,7 +32986,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
return lowerEH_SJLJ_SETUP_DISPATCH(Op, DAG);
case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
- case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
+ case ISD::GET_ROUNDING: return LowerGET_ROUNDING(Op, DAG);
case ISD::SET_ROUNDING: return LowerSET_ROUNDING(Op, DAG);
case ISD::CTLZ:
case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ(Op, Subtarget, DAG);
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index d1c0ee469cf46..5268ee7a838e6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -1619,7 +1619,7 @@ namespace llvm {
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerWin64_FP_TO_INT128(SDValue Op, SelectionDAG &DAG,
diff --git a/llvm/test/Bitcode/Inputs/auto_upgrade_flt_rounds.bc b/llvm/test/Bitcode/Inputs/auto_upgrade_flt_rounds.bc
new file mode 100644
index 0000000000000..c7ec98d8886a2
Binary files /dev/null and b/llvm/test/Bitcode/Inputs/auto_upgrade_flt_rounds.bc
diff er
diff --git a/llvm/test/Bitcode/auto_upgrade_flt_rounds.test b/llvm/test/Bitcode/auto_upgrade_flt_rounds.test
new file mode 100644
index 0000000000000..17aa88490bf3e
--- /dev/null
+++ b/llvm/test/Bitcode/auto_upgrade_flt_rounds.test
@@ -0,0 +1,4 @@
+RUN: llvm-dis %p/Inputs/auto_upgrade_flt_rounds.bc -o - | FileCheck %s
+
+CHECK-LABEL: define signext i32 @get_rounds()
+CHECK: tail call i32 @llvm.get.rounding()
diff --git a/llvm/test/CodeGen/AArch64/arm64-fpcr.ll b/llvm/test/CodeGen/AArch64/arm64-fpcr.ll
index 12ee139a7aa27..5e367d1633261 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fpcr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fpcr.ll
@@ -16,8 +16,8 @@ define i32 @GetFltRounds() {
; CHECK: add w8, w8, #1024, lsl #12
; CHECK: ubfx w0, w8, #22, #2
; CHECK: ret
- %1 = tail call i32 @llvm.flt.rounds()
+ %1 = tail call i32 @llvm.get.rounding()
ret i32 %1
}
-declare i32 @llvm.flt.rounds() #0
+declare i32 @llvm.get.rounding() #0
diff --git a/llvm/test/CodeGen/AArch64/strict-fp-opt.ll b/llvm/test/CodeGen/AArch64/strict-fp-opt.ll
index 4bcd2a08ffd7a..f8b76f6c55bd1 100644
--- a/llvm/test/CodeGen/AArch64/strict-fp-opt.ll
+++ b/llvm/test/CodeGen/AArch64/strict-fp-opt.ll
@@ -174,7 +174,7 @@ declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, me
declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata) #0
declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata) #0
declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata) #0
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
declare void @llvm.set.rounding(i32)
attributes #0 = { "strictfp" }
diff --git a/llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll b/llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll
index 9ee205a54a87d..488b8f5e271ee 100644
--- a/llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll
+++ b/llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll
@@ -16,7 +16,7 @@ define hidden void @_strtod_r() nounwind {
br i1 undef, label %4, label %7
; <label>:4 ; preds = %3
- %5 = call i32 @llvm.flt.rounds()
+ %5 = call i32 @llvm.get.rounding()
%6 = icmp eq i32 %5, 1
br i1 %6, label %8, label %7
@@ -33,4 +33,4 @@ define hidden void @_strtod_r() nounwind {
ret void
}
-declare i32 @llvm.flt.rounds() nounwind
+declare i32 @llvm.get.rounding() nounwind
diff --git a/llvm/test/CodeGen/ARM/fpscr-intrinsics.ll b/llvm/test/CodeGen/ARM/fpscr-intrinsics.ll
index 64b97525febfe..5cefc6255b051 100644
--- a/llvm/test/CodeGen/ARM/fpscr-intrinsics.ll
+++ b/llvm/test/CodeGen/ARM/fpscr-intrinsics.ll
@@ -7,7 +7,7 @@
define void @strtod() {
entry:
; CHECK: vmrs r{{[0-9]+}}, fpscr
- %0 = call i32 @llvm.flt.rounds()
+ %0 = call i32 @llvm.get.rounding()
%tobool = icmp ne i32 %0, 0
br i1 %tobool, label %if.then, label %if.end
@@ -41,4 +41,4 @@ declare i32 @llvm.arm.get.fpscr()
declare void @llvm.arm.set.fpscr(i32)
; Function Attrs: nounwind
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
diff --git a/llvm/test/CodeGen/ARM/no-fpscr-liveness.ll b/llvm/test/CodeGen/ARM/no-fpscr-liveness.ll
index 53de6c952fa0e..ee1285587b657 100644
--- a/llvm/test/CodeGen/ARM/no-fpscr-liveness.ll
+++ b/llvm/test/CodeGen/ARM/no-fpscr-liveness.ll
@@ -22,7 +22,7 @@ define i32 @eggs(double* nocapture readnone %arg) {
bb:
%tmp = alloca %struct.wibble, align 4
%tmp1 = bitcast %struct.wibble* %tmp to i8*
- %tmp2 = tail call i32 @llvm.flt.rounds()
+ %tmp2 = tail call i32 @llvm.get.rounding()
%tmp3 = ptrtoint %struct.wibble* %tmp to i32
%tmp4 = sitofp i32 %tmp3 to double
%tmp5 = fmul double %tmp4, 0x0123456789ABCDEF
@@ -47,5 +47,5 @@ bb18: ; preds = %bb16, %bb
ret i32 undef
}
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
declare i32 @zot(...)
diff --git a/llvm/test/CodeGen/MSP430/flt_rounds.ll b/llvm/test/CodeGen/MSP430/flt_rounds.ll
index fb89363d4d0a9..25902a3a422a9 100644
--- a/llvm/test/CodeGen/MSP430/flt_rounds.ll
+++ b/llvm/test/CodeGen/MSP430/flt_rounds.ll
@@ -2,9 +2,9 @@
define i16 @foo() {
entry:
- %0 = call i32 @llvm.flt.rounds()
+ %0 = call i32 @llvm.get.rounding()
%1 = trunc i32 %0 to i16
ret i16 %1
}
-declare i32 @llvm.flt.rounds() nounwind
+declare i32 @llvm.get.rounding() nounwind
diff --git a/llvm/test/CodeGen/PowerPC/frounds.ll b/llvm/test/CodeGen/PowerPC/frounds.ll
index 93c40ee945a36..2bbdbf37e54e9 100644
--- a/llvm/test/CodeGen/PowerPC/frounds.ll
+++ b/llvm/test/CodeGen/PowerPC/frounds.ll
@@ -66,7 +66,7 @@ entry:
%retval = alloca i32 ; <ptr> [#uses=2]
%tmp = alloca i32 ; <ptr> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
- %tmp1 = call i32 @llvm.flt.rounds( ) ; <i32> [#uses=1]
+ %tmp1 = call i32 @llvm.get.rounding( ) ; <i32> [#uses=1]
store i32 %tmp1, ptr %tmp, align 4
%tmp2 = load i32, ptr %tmp, align 4 ; <i32> [#uses=1]
store i32 %tmp2, ptr %retval, align 4
@@ -77,4 +77,4 @@ return: ; preds = %entry
ret i32 %retval3
}
-declare i32 @llvm.flt.rounds() nounwind
+declare i32 @llvm.get.rounding() nounwind
diff --git a/llvm/test/CodeGen/RISCV/flt-rounds.ll b/llvm/test/CodeGen/RISCV/flt-rounds.ll
index eb40c6d32c2e8..4456c36cfb5de 100644
--- a/llvm/test/CodeGen/RISCV/flt-rounds.ll
+++ b/llvm/test/CodeGen/RISCV/flt-rounds.ll
@@ -4,7 +4,7 @@
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
define i32 @test_flt_rounds() nounwind {
; RV32I-LABEL: test_flt_rounds:
@@ -16,6 +16,6 @@ define i32 @test_flt_rounds() nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: ret
- %1 = call i32 @llvm.flt.rounds()
+ %1 = call i32 @llvm.get.rounding()
ret i32 %1
}
diff --git a/llvm/test/CodeGen/RISCV/fpenv.ll b/llvm/test/CodeGen/RISCV/fpenv.ll
index 4866c234a05f7..92888f3a66812 100644
--- a/llvm/test/CodeGen/RISCV/fpenv.ll
+++ b/llvm/test/CodeGen/RISCV/fpenv.ll
@@ -22,7 +22,7 @@ define i32 @func_01() {
; RV64IF-NEXT: srl a0, a1, a0
; RV64IF-NEXT: andi a0, a0, 7
; RV64IF-NEXT: ret
- %rm = call i32 @llvm.flt.rounds()
+ %rm = call i32 @llvm.get.rounding()
ret i32 %rm
}
@@ -122,4 +122,4 @@ define void @func_07() {
}
declare void @llvm.set.rounding(i32)
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
diff --git a/llvm/test/CodeGen/X86/flt-rounds.ll b/llvm/test/CodeGen/X86/flt-rounds.ll
index 6099987d69196..a5908978a5438 100644
--- a/llvm/test/CodeGen/X86/flt-rounds.ll
+++ b/llvm/test/CodeGen/X86/flt-rounds.ll
@@ -3,7 +3,7 @@
; RUN: llc -mtriple=i686-unknown-linux-gnu -mattr=-sse2 -verify-machineinstrs < %s | FileCheck %s --check-prefix=X86
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=X64
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
define i32 @test_flt_rounds() nounwind {
; X86-LABEL: test_flt_rounds:
@@ -31,7 +31,7 @@ define i32 @test_flt_rounds() nounwind {
; X64-NEXT: shrl %cl, %eax
; X64-NEXT: andl $3, %eax
; X64-NEXT: retq
- %1 = call i32 @llvm.flt.rounds()
+ %1 = call i32 @llvm.get.rounding()
ret i32 %1
}
@@ -172,21 +172,21 @@ define i32 @multiple_flt_rounds() nounwind {
; X64-NEXT: retq
entry:
%call = tail call i32 @fesetround(i32 1024)
- %0 = tail call i32 @llvm.flt.rounds()
+ %0 = tail call i32 @llvm.get.rounding()
%cmp = icmp ne i32 %0, 3
%spec.select = zext i1 %cmp to i32
%call1 = tail call i32 @fesetround(i32 0)
- %1 = tail call i32 @llvm.flt.rounds()
+ %1 = tail call i32 @llvm.get.rounding()
%cmp2 = icmp eq i32 %1, 1
%inc4 = select i1 %cmp, i32 2, i32 1
%errs.1 = select i1 %cmp2, i32 %spec.select, i32 %inc4
%call6 = tail call i32 @fesetround(i32 3072)
- %2 = tail call i32 @llvm.flt.rounds()
+ %2 = tail call i32 @llvm.get.rounding()
%cmp7 = icmp ne i32 %2, 0
%inc9 = zext i1 %cmp7 to i32
%spec.select22 = add nuw nsw i32 %errs.1, %inc9
%call11 = tail call i32 @fesetround(i32 2048)
- %3 = tail call i32 @llvm.flt.rounds()
+ %3 = tail call i32 @llvm.get.rounding()
%cmp12 = icmp ne i32 %3, 2
%inc14.neg = sext i1 %cmp12 to i32
%cmp16 = icmp ne i32 %spec.select22, %inc14.neg
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