[llvm] 4d48ccf - [MC] Use `MCRegister` instead of `unsigned` in `MCTargetAsmParser`
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 18 12:12:09 PST 2022
Author: Sergei Barannikov
Date: 2022-12-18T12:12:05-08:00
New Revision: 4d48ccfc88ca5af2f1fc419c87d4e7a8b3be9bd7
URL: https://github.com/llvm/llvm-project/commit/4d48ccfc88ca5af2f1fc419c87d4e7a8b3be9bd7
DIFF: https://github.com/llvm/llvm-project/commit/4d48ccfc88ca5af2f1fc419c87d4e7a8b3be9bd7.diff
LOG: [MC] Use `MCRegister` instead of `unsigned` in `MCTargetAsmParser`
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D140273
Added:
Modified:
llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
llvm/lib/MC/MCParser/AsmParser.cpp
llvm/lib/MC/MCParser/MasmParser.cpp
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
index 2b58208a4ff4d..2853b4c5fcb57 100644
--- a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
+++ b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
@@ -24,6 +24,7 @@ namespace llvm {
class MCContext;
class MCInst;
class MCInstrInfo;
+class MCRegister;
class MCStreamer;
class MCSubtargetInfo;
class MCSymbol;
@@ -377,7 +378,7 @@ class MCTargetAsmParser : public MCAsmParserExtension {
return getParser().parsePrimaryExpr(Res, EndLoc, nullptr);
}
- virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ virtual bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) = 0;
/// tryParseRegister - parse one register if possible
@@ -386,7 +387,7 @@ class MCTargetAsmParser : public MCAsmParserExtension {
/// location, without failing the entire parse if it can't. Must not consume
/// tokens if the parse fails.
virtual OperandMatchResultTy
- tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) = 0;
+ tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) = 0;
/// ParseInstruction - Parse one assembly instruction.
///
diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp
index b99df36c51cf9..f16e109ac739e 100644
--- a/llvm/lib/MC/MCParser/AsmParser.cpp
+++ b/llvm/lib/MC/MCParser/AsmParser.cpp
@@ -4225,10 +4225,10 @@ bool AsmParser::parseDirectiveCFIEndProc() {
/// parse register name or number.
bool AsmParser::parseRegisterOrRegisterNumber(int64_t &Register,
SMLoc DirectiveLoc) {
- unsigned RegNo;
+ MCRegister RegNo;
if (getLexer().isNot(AsmToken::Integer)) {
- if (getTargetParser().ParseRegister(RegNo, DirectiveLoc, DirectiveLoc))
+ if (getTargetParser().parseRegister(RegNo, DirectiveLoc, DirectiveLoc))
return true;
Register = getContext().getRegisterInfo()->getDwarfRegNum(RegNo, true);
} else
diff --git a/llvm/lib/MC/MCParser/MasmParser.cpp b/llvm/lib/MC/MCParser/MasmParser.cpp
index a3882ad18ee94..37dc1a3d6f09f 100644
--- a/llvm/lib/MC/MCParser/MasmParser.cpp
+++ b/llvm/lib/MC/MCParser/MasmParser.cpp
@@ -5536,10 +5536,10 @@ bool MasmParser::parseDirectiveCFIEndProc() {
/// parse register name or number.
bool MasmParser::parseRegisterOrRegisterNumber(int64_t &Register,
SMLoc DirectiveLoc) {
- unsigned RegNo;
+ MCRegister RegNo;
if (getLexer().isNot(AsmToken::Integer)) {
- if (getTargetParser().ParseRegister(RegNo, DirectiveLoc, DirectiveLoc))
+ if (getTargetParser().parseRegister(RegNo, DirectiveLoc, DirectiveLoc))
return true;
Register = getContext().getRegisterInfo()->getDwarfRegNum(RegNo, true);
} else
@@ -6269,10 +6269,10 @@ bool MasmParser::parseDirectiveIfdef(SMLoc DirectiveLoc, bool expect_defined) {
eatToEndOfStatement();
} else {
bool is_defined = false;
- unsigned RegNo;
+ MCRegister Reg;
SMLoc StartLoc, EndLoc;
- is_defined = (getTargetParser().tryParseRegister(
- RegNo, StartLoc, EndLoc) == MatchOperand_Success);
+ is_defined = (getTargetParser().tryParseRegister(Reg, StartLoc, EndLoc) ==
+ MatchOperand_Success);
if (!is_defined) {
StringRef Name;
if (check(parseIdentifier(Name), "expected identifier after 'ifdef'") ||
@@ -6389,9 +6389,9 @@ bool MasmParser::parseDirectiveElseIfdef(SMLoc DirectiveLoc,
eatToEndOfStatement();
} else {
bool is_defined = false;
- unsigned RegNo;
+ MCRegister Reg;
SMLoc StartLoc, EndLoc;
- is_defined = (getTargetParser().tryParseRegister(RegNo, StartLoc, EndLoc) ==
+ is_defined = (getTargetParser().tryParseRegister(Reg, StartLoc, EndLoc) ==
MatchOperand_Success);
if (!is_defined) {
StringRef Name;
@@ -6561,9 +6561,9 @@ bool MasmParser::parseDirectiveErrorIfdef(SMLoc DirectiveLoc,
}
bool IsDefined = false;
- unsigned RegNo;
+ MCRegister Reg;
SMLoc StartLoc, EndLoc;
- IsDefined = (getTargetParser().tryParseRegister(RegNo, StartLoc, EndLoc) ==
+ IsDefined = (getTargetParser().tryParseRegister(Reg, StartLoc, EndLoc) ==
MatchOperand_Success);
if (!IsDefined) {
StringRef Name;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 45690ac76c00c..9c7cd2debb89e 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -241,8 +241,8 @@ class AArch64AsmParser : public MCTargetAsmParser {
/// }
- OperandMatchResultTy tryParseScalarRegister(unsigned &Reg);
- OperandMatchResultTy tryParseVectorRegister(unsigned &Reg, StringRef &Kind,
+ OperandMatchResultTy tryParseScalarRegister(MCRegister &Reg);
+ OperandMatchResultTy tryParseVectorRegister(MCRegister &Reg, StringRef &Kind,
RegKind MatchKind);
OperandMatchResultTy tryParseMatrixRegister(OperandVector &Operands);
OperandMatchResultTy tryParseSVCR(OperandVector &Operands);
@@ -318,8 +318,9 @@ class AArch64AsmParser : public MCTargetAsmParser {
const MCParsedAsmOperand &Op2) const override;
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool ParseDirective(AsmToken DirectiveID) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
@@ -2838,12 +2839,12 @@ static unsigned matchMatrixRegName(StringRef Name) {
.Default(0);
}
-bool AArch64AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool AArch64AsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
return tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success;
}
-OperandMatchResultTy AArch64AsmParser::tryParseRegister(unsigned &RegNo,
+OperandMatchResultTy AArch64AsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
StartLoc = getLoc();
@@ -2922,7 +2923,7 @@ unsigned AArch64AsmParser::getNumRegsForRegKind(RegKind K) {
/// Identifier when called, and if it is a register name the token is eaten and
/// the register is added to the operand list.
OperandMatchResultTy
-AArch64AsmParser::tryParseScalarRegister(unsigned &RegNum) {
+AArch64AsmParser::tryParseScalarRegister(MCRegister &RegNum) {
const AsmToken &Tok = getTok();
if (Tok.isNot(AsmToken::Identifier))
return MatchOperand_NoMatch;
@@ -3111,7 +3112,7 @@ OperandMatchResultTy
AArch64AsmParser::tryParseSyspXzrPair(OperandVector &Operands) {
SMLoc StartLoc = getLoc();
- unsigned RegNum;
+ MCRegister RegNum;
// The case where xzr, xzr is not present is handled by an InstAlias.
@@ -4074,7 +4075,7 @@ bool AArch64AsmParser::tryParseNeonVectorRegister(OperandVector &Operands) {
SMLoc S = getLoc();
// Check for a vector register specifier first.
StringRef Kind;
- unsigned Reg;
+ MCRegister Reg;
OperandMatchResultTy Res =
tryParseVectorRegister(Reg, Kind, RegKind::NeonVector);
if (Res != MatchOperand_Success)
@@ -4127,7 +4128,7 @@ AArch64AsmParser::tryParseVectorIndex(OperandVector &Operands) {
// optional kind specifier. If it is a register specifier, eat the token
// and return it.
OperandMatchResultTy
-AArch64AsmParser::tryParseVectorRegister(unsigned &Reg, StringRef &Kind,
+AArch64AsmParser::tryParseVectorRegister(MCRegister &Reg, StringRef &Kind,
RegKind MatchKind) {
const AsmToken &Tok = getTok();
@@ -4164,7 +4165,7 @@ AArch64AsmParser::tryParseSVEPredicateVector(OperandVector &Operands) {
// Check for a SVE predicate register specifier first.
const SMLoc S = getLoc();
StringRef Kind;
- unsigned RegNum;
+ MCRegister RegNum;
auto Res = tryParseVectorRegister(RegNum, Kind, RK);
if (Res != MatchOperand_Success)
return Res;
@@ -4438,7 +4439,7 @@ AArch64AsmParser::tryParseVectorList(OperandVector &Operands,
return MatchOperand_NoMatch;
// Wrapper around parse function
- auto ParseVector = [this](unsigned &Reg, StringRef &Kind, SMLoc Loc,
+ auto ParseVector = [this](MCRegister &Reg, StringRef &Kind, SMLoc Loc,
bool NoMatchIsError) {
auto RegTok = getTok();
auto ParseRes = tryParseVectorRegister(Reg, Kind, VectorKind);
@@ -4469,7 +4470,7 @@ AArch64AsmParser::tryParseVectorList(OperandVector &Operands,
Lex(); // Eat left bracket token.
StringRef Kind;
- unsigned FirstReg;
+ MCRegister FirstReg;
auto ParseRes = ParseVector(FirstReg, Kind, getLoc(), ExpectMatch);
// Put back the original left bracket if there was no match, so that
@@ -4488,7 +4489,7 @@ AArch64AsmParser::tryParseVectorList(OperandVector &Operands,
SMLoc Loc = getLoc();
StringRef NextKind;
- unsigned Reg;
+ MCRegister Reg;
ParseRes = ParseVector(Reg, NextKind, getLoc(), true);
if (ParseRes != MatchOperand_Success)
return ParseRes;
@@ -4514,7 +4515,7 @@ AArch64AsmParser::tryParseVectorList(OperandVector &Operands,
while (parseOptionalToken(AsmToken::Comma)) {
SMLoc Loc = getLoc();
StringRef NextKind;
- unsigned Reg;
+ MCRegister Reg;
ParseRes = ParseVector(Reg, NextKind, getLoc(), true);
if (ParseRes != MatchOperand_Success)
return ParseRes;
@@ -4580,7 +4581,7 @@ OperandMatchResultTy
AArch64AsmParser::tryParseGPR64sp0Operand(OperandVector &Operands) {
SMLoc StartLoc = getLoc();
- unsigned RegNum;
+ MCRegister RegNum;
OperandMatchResultTy Res = tryParseScalarRegister(RegNum);
if (Res != MatchOperand_Success)
return Res;
@@ -4651,7 +4652,7 @@ OperandMatchResultTy
AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) {
SMLoc StartLoc = getLoc();
- unsigned RegNum;
+ MCRegister RegNum;
OperandMatchResultTy Res = tryParseScalarRegister(RegNum);
if (Res != MatchOperand_Success)
return Res;
@@ -4978,9 +4979,9 @@ bool AArch64AsmParser::parseComma() {
bool AArch64AsmParser::parseRegisterInRange(unsigned &Out, unsigned Base,
unsigned First, unsigned Last) {
- unsigned Reg;
+ MCRegister Reg;
SMLoc Start, End;
- if (check(ParseRegister(Reg, Start, End), getLoc(), "expected register"))
+ if (check(parseRegister(Reg, Start, End), getLoc(), "expected register"))
return true;
// Special handling for FP and LR; they aren't linearly after x28 in
@@ -7153,7 +7154,7 @@ bool AArch64AsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
Lex(); // Eat the '.req' token.
SMLoc SRegLoc = getLoc();
RegKind RegisterKind = RegKind::Scalar;
- unsigned RegNum;
+ MCRegister RegNum;
OperandMatchResultTy ParseRes = tryParseScalarRegister(RegNum);
if (ParseRes != MatchOperand_Success) {
@@ -7503,10 +7504,10 @@ bool AArch64AsmParser::parseDirectiveSEHPACSignLR(SMLoc L) {
/// ::= .seh_save_any_reg_px
bool AArch64AsmParser::parseDirectiveSEHSaveAnyReg(SMLoc L, bool Paired,
bool Writeback) {
- unsigned Reg;
+ MCRegister Reg;
SMLoc Start, End;
int64_t Offset;
- if (check(ParseRegister(Reg, Start, End), getLoc(), "expected register") ||
+ if (check(parseRegister(Reg, Start, End), getLoc(), "expected register") ||
parseComma() || parseImmExpr(Offset))
return true;
@@ -7720,7 +7721,7 @@ AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
return MatchOperand_ParseFail;
}
- unsigned FirstReg;
+ MCRegister FirstReg;
OperandMatchResultTy Res = tryParseScalarRegister(FirstReg);
if (Res != MatchOperand_Success) {
Error(S, "expected first even register of a "
@@ -7758,7 +7759,7 @@ AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
Lex();
SMLoc E = getLoc();
- unsigned SecondReg;
+ MCRegister SecondReg;
Res = tryParseScalarRegister(SecondReg);
if (Res != MatchOperand_Success) {
Error(E, "expected second odd register of a "
@@ -7794,7 +7795,7 @@ OperandMatchResultTy
AArch64AsmParser::tryParseSVEDataVector(OperandVector &Operands) {
const SMLoc S = getLoc();
// Check for a SVE vector register specifier first.
- unsigned RegNum;
+ MCRegister RegNum;
StringRef Kind;
OperandMatchResultTy Res =
@@ -7911,7 +7912,7 @@ OperandMatchResultTy
AArch64AsmParser::tryParseGPR64x8(OperandVector &Operands) {
SMLoc SS = getLoc();
- unsigned XReg;
+ MCRegister XReg;
if (tryParseScalarRegister(XReg) != MatchOperand_Success)
return MatchOperand_NoMatch;
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index e6671b233ce0b..72004dcff3c4c 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1515,10 +1515,11 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
StringRef getMatchedVariantName() const;
std::unique_ptr<AMDGPUOperand> parseRegister(bool RestoreOnFailure = false);
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
+ bool ParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
bool RestoreOnFailure);
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
unsigned checkTargetMatchPredicate(MCInst &Inst) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
@@ -2470,7 +2471,7 @@ static unsigned getSpecialRegForName(StringRef RegName) {
.Default(AMDGPU::NoRegister);
}
-bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool AMDGPUAsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc, bool RestoreOnFailure) {
auto R = parseRegister();
if (!R) return true;
@@ -2481,12 +2482,12 @@ bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
return false;
}
-bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool AMDGPUAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
}
-OperandMatchResultTy AMDGPUAsmParser::tryParseRegister(unsigned &RegNo,
+OperandMatchResultTy AMDGPUAsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
bool Result =
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 21e3cd97215f0..0246ba01ad78f 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -700,8 +700,9 @@ class ARMAsmParser : public MCTargetAsmParser {
}
// Implementation of the MCTargetAsmParser interface:
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
@@ -4060,8 +4061,8 @@ static unsigned MatchRegisterName(StringRef Name);
/// }
-bool ARMAsmParser::ParseRegister(unsigned &RegNo,
- SMLoc &StartLoc, SMLoc &EndLoc) {
+bool ARMAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) {
const AsmToken &Tok = getParser().getTok();
StartLoc = Tok.getLoc();
EndLoc = Tok.getEndLoc();
@@ -4070,10 +4071,10 @@ bool ARMAsmParser::ParseRegister(unsigned &RegNo,
return (RegNo == (unsigned)-1);
}
-OperandMatchResultTy ARMAsmParser::tryParseRegister(unsigned &RegNo,
+OperandMatchResultTy ARMAsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
- if (ParseRegister(RegNo, StartLoc, EndLoc))
+ if (parseRegister(RegNo, StartLoc, EndLoc))
return MatchOperand_NoMatch;
return MatchOperand_Success;
}
@@ -11317,9 +11318,9 @@ bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
MCAsmParser &Parser = getParser();
Parser.Lex(); // Eat the '.req' token.
- unsigned Reg;
+ MCRegister Reg;
SMLoc SRegLoc, ERegLoc;
- if (check(ParseRegister(Reg, SRegLoc, ERegLoc), SRegLoc,
+ if (check(parseRegister(Reg, SRegLoc, ERegLoc), SRegLoc,
"register name expected") ||
parseEOL())
return true;
diff --git a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
index c36185a96835f..5afec10e5a92f 100644
--- a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
+++ b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
@@ -55,8 +55,9 @@ class AVRAsmParser : public MCTargetAsmParser {
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
@@ -600,7 +601,7 @@ OperandMatchResultTy AVRAsmParser::parseMemriOperand(OperandVector &Operands) {
return MatchOperand_Success;
}
-bool AVRAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool AVRAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
StartLoc = Parser.getTok().getLoc();
RegNo = parseRegister(/*RestoreOnFailure=*/false);
@@ -609,7 +610,7 @@ bool AVRAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
return (RegNo == AVR::NoRegister);
}
-OperandMatchResultTy AVRAsmParser::tryParseRegister(unsigned &RegNo,
+OperandMatchResultTy AVRAsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
StartLoc = Parser.getTok().getLoc();
diff --git a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
index 9ba5dee6f2500..137e67bd215b2 100644
--- a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
+++ b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
@@ -39,8 +39,9 @@ class BPFAsmParser : public MCTargetAsmParser {
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
@@ -323,14 +324,14 @@ bool BPFAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
llvm_unreachable("Unknown match type detected!");
}
-bool BPFAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool BPFAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success)
return Error(StartLoc, "invalid register name");
return false;
}
-OperandMatchResultTy BPFAsmParser::tryParseRegister(unsigned &RegNo,
+OperandMatchResultTy BPFAsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
const AsmToken &Tok = getParser().getTok();
diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
index 6aa322bdd3bb5..248bd3130c250 100644
--- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
+++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
@@ -115,8 +115,9 @@ class HexagonAsmParser : public MCTargetAsmParser {
bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
bool ParseDirectiveFalign(unsigned Size, SMLoc L);
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool ParseDirectiveSubsection(SMLoc L);
bool ParseDirectiveComm(bool IsLocal, SMLoc L);
@@ -866,11 +867,11 @@ bool HexagonAsmParser::splitIdentifier(OperandVector &Operands) {
}
bool HexagonAsmParser::parseOperand(OperandVector &Operands) {
- unsigned Register;
+ MCRegister Register;
SMLoc Begin;
SMLoc End;
MCAsmLexer &Lexer = getLexer();
- if (!ParseRegister(Register, Begin, End)) {
+ if (!parseRegister(Register, Begin, End)) {
if (!ErrorMissingParenthesis)
switch (Register) {
default:
@@ -962,12 +963,12 @@ bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious,
return false;
}
-bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool HexagonAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
return tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success;
}
-OperandMatchResultTy HexagonAsmParser::tryParseRegister(unsigned &RegNo,
+OperandMatchResultTy HexagonAsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
MCAsmLexer &Lexer = getLexer();
diff --git a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
index 0d99673371f98..2c7013dd492e0 100644
--- a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
+++ b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
@@ -67,8 +67,9 @@ class LanaiAsmParser : public MCTargetAsmParser {
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
- bool ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) override;
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ bool parseRegister(MCRegister &RegNum, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode,
@@ -717,7 +718,7 @@ LanaiAsmParser::parseRegister(bool RestoreOnFailure) {
return nullptr;
}
-bool LanaiAsmParser::ParseRegister(unsigned &RegNum, SMLoc &StartLoc,
+bool LanaiAsmParser::parseRegister(MCRegister &RegNum, SMLoc &StartLoc,
SMLoc &EndLoc) {
const AsmToken &Tok = getParser().getTok();
StartLoc = Tok.getLoc();
@@ -728,7 +729,7 @@ bool LanaiAsmParser::ParseRegister(unsigned &RegNum, SMLoc &StartLoc,
return (Op == nullptr);
}
-OperandMatchResultTy LanaiAsmParser::tryParseRegister(unsigned &RegNum,
+OperandMatchResultTy LanaiAsmParser::tryParseRegister(MCRegister &RegNum,
SMLoc &StartLoc,
SMLoc &EndLoc) {
const AsmToken &Tok = getParser().getTok();
diff --git a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
index 8806e13d589b9..b27070f717f50 100644
--- a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
+++ b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
@@ -43,8 +43,9 @@ class LoongArchAsmParser : public MCTargetAsmParser {
using InstSeq = SmallVector<Inst>;
/// Parse a register as used in CFI directives.
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
@@ -535,12 +536,12 @@ static bool matchRegisterNameHelper(MCRegister &RegNo, StringRef Name) {
return RegNo == LoongArch::NoRegister;
}
-bool LoongArchAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool LoongArchAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
return Error(getLoc(), "invalid register number");
}
-OperandMatchResultTy LoongArchAsmParser::tryParseRegister(unsigned &RegNo,
+OperandMatchResultTy LoongArchAsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
llvm_unreachable("Unimplemented function.");
diff --git a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
index 0a3d09552535c..f431aae2f23ed 100644
--- a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
+++ b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
@@ -43,9 +43,8 @@ class M68kAsmParser : public MCTargetAsmParser {
const uint64_t &ErrorInfo);
bool missingFeature(const SMLoc &Loc, const uint64_t &ErrorInfo);
bool emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const;
- bool parseRegisterName(unsigned int &RegNo, SMLoc Loc,
- StringRef RegisterName);
- OperandMatchResultTy parseRegister(unsigned int &RegNo);
+ bool parseRegisterName(MCRegister &RegNo, SMLoc Loc, StringRef RegisterName);
+ OperandMatchResultTy parseRegister(MCRegister &RegNo);
// Parser functions.
void eatComma();
@@ -67,8 +66,9 @@ class M68kAsmParser : public MCTargetAsmParser {
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override;
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
@@ -103,8 +103,8 @@ struct M68kMemOp {
// OuterDisp(%OuterReg, %InnerReg.Size * Scale, InnerDisp)
Kind Op;
- unsigned OuterReg;
- unsigned InnerReg;
+ MCRegister OuterReg;
+ MCRegister InnerReg;
const MCExpr *OuterDisp;
const MCExpr *InnerDisp;
uint8_t Size : 4;
@@ -575,7 +575,7 @@ unsigned M68kAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
return Match_InvalidOperand;
}
-bool M68kAsmParser::parseRegisterName(unsigned &RegNo, SMLoc Loc,
+bool M68kAsmParser::parseRegisterName(MCRegister &RegNo, SMLoc Loc,
StringRef RegisterName) {
auto RegisterNameLower = RegisterName.lower();
@@ -624,7 +624,7 @@ bool M68kAsmParser::parseRegisterName(unsigned &RegNo, SMLoc Loc,
return false;
}
-OperandMatchResultTy M68kAsmParser::parseRegister(unsigned &RegNo) {
+OperandMatchResultTy M68kAsmParser::parseRegister(MCRegister &RegNo) {
bool HasPercent = false;
AsmToken PercentToken;
@@ -656,7 +656,7 @@ OperandMatchResultTy M68kAsmParser::parseRegister(unsigned &RegNo) {
return MatchOperand_Success;
}
-bool M68kAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool M68kAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
auto Result = tryParseRegister(RegNo, StartLoc, EndLoc);
if (Result != MatchOperand_Success) {
@@ -666,7 +666,7 @@ bool M68kAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
return false;
}
-OperandMatchResultTy M68kAsmParser::tryParseRegister(unsigned &RegNo,
+OperandMatchResultTy M68kAsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
StartLoc = getLexer().getLoc();
@@ -841,7 +841,7 @@ M68kAsmParser::parseRegOrMoveMask(OperandVector &Operands) {
bool IsFirstRegister =
(MemOp.Op == M68kMemOp::Kind::RegMask) && (MemOp.RegMask == 0);
- unsigned FirstRegister;
+ MCRegister FirstRegister;
auto Result = parseRegister(FirstRegister);
if (IsFirstRegister && (Result == llvm::MatchOperand_NoMatch)) {
return MatchOperand_NoMatch;
@@ -851,7 +851,7 @@ M68kAsmParser::parseRegOrMoveMask(OperandVector &Operands) {
return MatchOperand_ParseFail;
}
- unsigned LastRegister = FirstRegister;
+ MCRegister LastRegister = FirstRegister;
if (getLexer().is(AsmToken::Minus)) {
getLexer().Lex();
Result = parseRegister(LastRegister);
diff --git a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
index 3b936fffae225..1560f14976dda 100644
--- a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
+++ b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
@@ -45,8 +45,9 @@ class MSP430AsmParser : public MCTargetAsmParser {
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
@@ -289,7 +290,7 @@ bool MSP430AsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
static unsigned MatchRegisterName(StringRef Name);
static unsigned MatchRegisterAltName(StringRef Name);
-bool MSP430AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool MSP430AsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
switch (tryParseRegister(RegNo, StartLoc, EndLoc)) {
case MatchOperand_ParseFail:
@@ -303,7 +304,7 @@ bool MSP430AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
llvm_unreachable("unknown match result type");
}
-OperandMatchResultTy MSP430AsmParser::tryParseRegister(unsigned &RegNo,
+OperandMatchResultTy MSP430AsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
if (getLexer().getKind() == AsmToken::Identifier) {
@@ -455,9 +456,9 @@ bool MSP430AsmParser::ParseOperand(OperandVector &Operands) {
default: return true;
case AsmToken::Identifier: {
// try rN
- unsigned RegNo;
+ MCRegister RegNo;
SMLoc StartLoc, EndLoc;
- if (!ParseRegister(RegNo, StartLoc, EndLoc)) {
+ if (!parseRegister(RegNo, StartLoc, EndLoc)) {
Operands.push_back(MSP430Operand::CreateReg(RegNo, StartLoc, EndLoc));
return false;
}
@@ -470,13 +471,13 @@ bool MSP430AsmParser::ParseOperand(OperandVector &Operands) {
const MCExpr *Val;
// Try constexpr[(rN)]
if (!getParser().parseExpression(Val)) {
- unsigned RegNo = MSP430::PC;
+ MCRegister RegNo = MSP430::PC;
SMLoc EndLoc = getParser().getTok().getLoc();
// Try (rN)
if (getLexer().getKind() == AsmToken::LParen) {
getLexer().Lex(); // Eat '('
SMLoc RegStartLoc;
- if (ParseRegister(RegNo, RegStartLoc, EndLoc))
+ if (parseRegister(RegNo, RegStartLoc, EndLoc))
return true;
if (getLexer().getKind() != AsmToken::RParen)
return true;
@@ -506,9 +507,9 @@ bool MSP430AsmParser::ParseOperand(OperandVector &Operands) {
// Try @rN[+]
SMLoc StartLoc = getParser().getTok().getLoc();
getLexer().Lex(); // Eat '@'
- unsigned RegNo;
+ MCRegister RegNo;
SMLoc RegStartLoc, EndLoc;
- if (ParseRegister(RegNo, RegStartLoc, EndLoc))
+ if (parseRegister(RegNo, RegStartLoc, EndLoc))
return true;
if (getLexer().getKind() == AsmToken::Plus) {
Operands.push_back(MSP430Operand::CreatePostIndReg(RegNo, StartLoc, EndLoc));
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 58d356d45dd30..63b6e4cd3ab9e 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -179,8 +179,9 @@ class MipsAsmParser : public MCTargetAsmParser {
bool MatchingInlineAsm) override;
/// Parse a register as used in CFI directives
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool parseParenSuffix(StringRef Name, OperandVector &Operands);
@@ -6398,12 +6399,12 @@ bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
return true;
}
-bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool MipsAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
return tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success;
}
-OperandMatchResultTy MipsAsmParser::tryParseRegister(unsigned &RegNo,
+OperandMatchResultTy MipsAsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index 56fb38d31b13a..6de25b87016bd 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -103,10 +103,11 @@ class PPCAsmParser : public MCTargetAsmParser {
bool isPPC64() const { return IsPPC64; }
- bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal);
+ bool MatchRegisterName(MCRegister &RegNo, int64_t &IntVal);
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
@@ -1248,7 +1249,7 @@ bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
llvm_unreachable("Implement any new match types added!");
}
-bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) {
+bool PPCAsmParser::MatchRegisterName(MCRegister &RegNo, int64_t &IntVal) {
if (getParser().getTok().is(AsmToken::Percent))
getParser().Lex(); // Eat the '%'.
@@ -1307,14 +1308,14 @@ bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) {
return false;
}
-bool PPCAsmParser::
-ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
+bool PPCAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) {
if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success)
return TokError("invalid register name");
return false;
}
-OperandMatchResultTy PPCAsmParser::tryParseRegister(unsigned &RegNo,
+OperandMatchResultTy PPCAsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
const AsmToken &Tok = getParser().getTok();
@@ -1502,7 +1503,7 @@ bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
// Special handling for register names. These are interpreted
// as immediates corresponding to the register number.
case AsmToken::Percent: {
- unsigned RegNo;
+ MCRegister RegNo;
int64_t IntVal;
if (MatchRegisterName(RegNo, IntVal))
return Error(S, "invalid register name");
@@ -1558,7 +1559,7 @@ bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
int64_t IntVal;
switch (getLexer().getKind()) {
case AsmToken::Percent: {
- unsigned RegNo;
+ MCRegister RegNo;
if (MatchRegisterName(RegNo, IntVal))
return Error(S, "invalid register name");
break;
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 90d22a23ade60..ed6a6d1cda049 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -91,8 +91,9 @@ class RISCVAsmParser : public MCTargetAsmParser {
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
@@ -1311,14 +1312,14 @@ static bool matchRegisterNameHelper(bool IsRV32E, MCRegister &RegNo,
return RegNo == RISCV::NoRegister;
}
-bool RISCVAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool RISCVAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success)
return Error(StartLoc, "invalid register name");
return false;
}
-OperandMatchResultTy RISCVAsmParser::tryParseRegister(unsigned &RegNo,
+OperandMatchResultTy RISCVAsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
const AsmToken &Tok = getParser().getTok();
diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 77e9b1d966121..4f94392d4dae7 100644
--- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -70,8 +70,9 @@ class SparcAsmParser : public MCTargetAsmParser {
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
@@ -106,7 +107,7 @@ class SparcAsmParser : public MCTargetAsmParser {
const MCExpr *subExpr);
// returns true if Tok is matched to a register and returns register in RegNo.
- bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
+ bool matchRegisterName(const AsmToken &Tok, MCRegister &RegNo,
unsigned &RegKind);
bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
@@ -693,14 +694,14 @@ bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
llvm_unreachable("Implement any new match types added!");
}
-bool SparcAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool SparcAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success)
return Error(StartLoc, "invalid register name");
return false;
}
-OperandMatchResultTy SparcAsmParser::tryParseRegister(unsigned &RegNo,
+OperandMatchResultTy SparcAsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
const AsmToken &Tok = Parser.getTok();
@@ -1050,7 +1051,8 @@ SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
return MatchOperand_NoMatch;
Parser.Lex(); // eat %
- unsigned RegNo, RegKind;
+ MCRegister RegNo;
+ unsigned RegKind;
if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
return MatchOperand_NoMatch;
@@ -1106,9 +1108,9 @@ SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
switch (getLexer().getKind()) {
default: break;
- case AsmToken::Percent:
+ case AsmToken::Percent: {
Parser.Lex(); // Eat the '%'.
- unsigned RegNo;
+ MCRegister RegNo;
unsigned RegKind;
if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
StringRef name = Parser.getTok().getString();
@@ -1156,6 +1158,7 @@ SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
Op = SparcOperand::CreateImm(EVal, S, E);
}
break;
+ }
case AsmToken::Plus:
case AsmToken::Minus:
@@ -1203,7 +1206,7 @@ SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {
return MatchOperand_Success;
}
-bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
+bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, MCRegister &RegNo,
unsigned &RegKind) {
int64_t intVal = 0;
RegNo = 0;
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index 92186b7538286..4e7985bd4edc7 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -495,10 +495,11 @@ class SystemZAsmParser : public MCTargetAsmParser {
// Override MCTargetAsmParser.
bool ParseDirective(AsmToken DirectiveID) override;
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ bool ParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
bool RestoreOnFailure);
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
@@ -1379,7 +1380,7 @@ bool SystemZAsmParser::ParseGNUAttribute(SMLoc L) {
return true;
}
-bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool SystemZAsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc, bool RestoreOnFailure) {
Register Reg;
if (parseRegister(Reg, RestoreOnFailure))
@@ -1399,12 +1400,12 @@ bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
return false;
}
-bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool SystemZAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
}
-OperandMatchResultTy SystemZAsmParser::tryParseRegister(unsigned &RegNo,
+OperandMatchResultTy SystemZAsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
bool Result =
diff --git a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
index f39be036d21ff..0a72f29659b04 100644
--- a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
+++ b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
@@ -55,9 +55,10 @@ class VEAsmParser : public MCTargetAsmParser {
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
int parseRegisterName(unsigned (*matchFn)(StringRef));
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
@@ -796,7 +797,7 @@ bool VEAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
llvm_unreachable("Implement any new match types added!");
}
-bool VEAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool VEAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success)
return Error(StartLoc, "invalid register name");
@@ -827,8 +828,9 @@ static unsigned MatchRegisterName(StringRef Name);
/// \note Generated by TableGen.
static unsigned MatchRegisterAltName(StringRef Name);
-OperandMatchResultTy
-VEAsmParser::tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
+OperandMatchResultTy VEAsmParser::tryParseRegister(MCRegister &RegNo,
+ SMLoc &StartLoc,
+ SMLoc &EndLoc) {
const AsmToken Tok = Parser.getTok();
StartLoc = Tok.getLoc();
EndLoc = Tok.getEndLoc();
@@ -1246,11 +1248,11 @@ OperandMatchResultTy VEAsmParser::parseMEMOperand(OperandVector &Operands) {
}
const MCExpr *IndexValue = nullptr;
- unsigned IndexReg = 0;
+ MCRegister IndexReg;
switch (getLexer().getKind()) {
default:
- if (ParseRegister(IndexReg, S, E))
+ if (parseRegister(IndexReg, S, E))
return MatchOperand_ParseFail;
break;
@@ -1283,8 +1285,8 @@ OperandMatchResultTy VEAsmParser::parseMEMOperand(OperandVector &Operands) {
break;
}
- unsigned BaseReg = 0;
- if (ParseRegister(BaseReg, S, E))
+ MCRegister BaseReg;
+ if (parseRegister(BaseReg, S, E))
return MatchOperand_ParseFail;
if (!Parser.getTok().is(AsmToken::RParen))
@@ -1313,7 +1315,7 @@ OperandMatchResultTy VEAsmParser::parseMEMAsOperand(OperandVector &Operands) {
// (base)
// base
- unsigned BaseReg = VE::NoRegister;
+ MCRegister BaseReg;
std::unique_ptr<VEOperand> Offset;
switch (getLexer().getKind()) {
default:
@@ -1332,7 +1334,7 @@ OperandMatchResultTy VEAsmParser::parseMEMAsOperand(OperandVector &Operands) {
}
case AsmToken::Percent:
- if (ParseRegister(BaseReg, S, E))
+ if (parseRegister(BaseReg, S, E))
return MatchOperand_NoMatch;
Offset =
VEOperand::CreateImm(MCConstantExpr::create(0, getContext()), S, E);
@@ -1365,13 +1367,13 @@ OperandMatchResultTy VEAsmParser::parseMEMAsOperand(OperandVector &Operands) {
switch (getLexer().getKind()) {
default:
- if (ParseRegister(BaseReg, S, E))
+ if (parseRegister(BaseReg, S, E))
return MatchOperand_ParseFail;
break;
case AsmToken::Comma:
Parser.Lex(); // Eat the ,
- if (ParseRegister(BaseReg, S, E))
+ if (parseRegister(BaseReg, S, E))
return MatchOperand_ParseFail;
break;
@@ -1448,7 +1450,7 @@ OperandMatchResultTy VEAsmParser::parseOperand(OperandVector &Operands,
const AsmToken Tok1 = Parser.getTok();
Parser.Lex(); // Eat the '('.
- unsigned RegNo1;
+ MCRegister RegNo1;
SMLoc S1, E1;
if (tryParseRegister(RegNo1, S1, E1) != MatchOperand_Success) {
getLexer().UnLex(Tok1);
@@ -1459,7 +1461,7 @@ OperandMatchResultTy VEAsmParser::parseOperand(OperandVector &Operands,
return MatchOperand_ParseFail;
Parser.Lex(); // Eat the ','.
- unsigned RegNo2;
+ MCRegister RegNo2;
SMLoc S2, E2;
if (tryParseRegister(RegNo2, S2, E2) != MatchOperand_Success)
return MatchOperand_ParseFail;
@@ -1524,12 +1526,12 @@ VEAsmParser::parseVEAsmOperand(std::unique_ptr<VEOperand> &Op) {
default:
break;
- case AsmToken::Percent:
- unsigned RegNo;
+ case AsmToken::Percent: {
+ MCRegister RegNo;
if (tryParseRegister(RegNo, S, E) == MatchOperand_Success)
Op = VEOperand::CreateReg(RegNo, S, E);
break;
-
+ }
case AsmToken::Minus:
case AsmToken::Integer:
case AsmToken::Dot:
diff --git a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
index 6c74e4429f6fb..9b80c32b77db6 100644
--- a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
+++ b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
@@ -273,11 +273,11 @@ class WebAssemblyAsmParser final : public MCTargetAsmParser {
#include "WebAssemblyGenAsmMatcher.inc"
// TODO: This is required to be implemented, but appears unused.
- bool ParseRegister(unsigned & /*RegNo*/, SMLoc & /*StartLoc*/,
+ bool parseRegister(MCRegister & /*RegNo*/, SMLoc & /*StartLoc*/,
SMLoc & /*EndLoc*/) override {
- llvm_unreachable("ParseRegister is not implemented.");
+ llvm_unreachable("parseRegister is not implemented.");
}
- OperandMatchResultTy tryParseRegister(unsigned & /*RegNo*/,
+ OperandMatchResultTy tryParseRegister(MCRegister & /*RegNo*/,
SMLoc & /*StartLoc*/,
SMLoc & /*EndLoc*/) override {
llvm_unreachable("tryParseRegister is not implemented.");
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index bdf242a37df59..f0e18cc5ef033 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1089,9 +1089,9 @@ class X86AsmParser : public MCTargetAsmParser {
return Parser.Error(L, Msg, Range);
}
- bool MatchRegisterByName(unsigned &RegNo, StringRef RegName, SMLoc StartLoc,
+ bool MatchRegisterByName(MCRegister &RegNo, StringRef RegName, SMLoc StartLoc,
SMLoc EndLoc);
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
+ bool ParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
bool RestoreOnFailure);
std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc);
@@ -1157,7 +1157,7 @@ class X86AsmParser : public MCTargetAsmParser {
bool parseDirectiveFPOEndProc(SMLoc L);
/// SEH directives.
- bool parseSEHRegisterNumber(unsigned RegClassID, unsigned &RegNo);
+ bool parseSEHRegisterNumber(unsigned RegClassID, MCRegister &RegNo);
bool parseDirectiveSEHPushReg(SMLoc);
bool parseDirectiveSEHSetFrame(SMLoc);
bool parseDirectiveSEHSaveReg(SMLoc);
@@ -1268,8 +1268,9 @@ class X86AsmParser : public MCTargetAsmParser {
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
}
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
- OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) override;
+ OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) override;
@@ -1377,7 +1378,7 @@ static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,
return checkScale(Scale, ErrMsg);
}
-bool X86AsmParser::MatchRegisterByName(unsigned &RegNo, StringRef RegName,
+bool X86AsmParser::MatchRegisterByName(MCRegister &RegNo, StringRef RegName,
SMLoc StartLoc, SMLoc EndLoc) {
// If we encounter a %, ignore it. This code handles registers with and
// without the prefix, unprefixed registers can occur in cfi directives.
@@ -1477,7 +1478,7 @@ bool X86AsmParser::MatchRegisterByName(unsigned &RegNo, StringRef RegName,
return false;
}
-bool X86AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool X86AsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc, bool RestoreOnFailure) {
MCAsmParser &Parser = getParser();
MCAsmLexer &Lexer = getLexer();
@@ -1574,12 +1575,12 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
return false;
}
-bool X86AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+bool X86AsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
}
-OperandMatchResultTy X86AsmParser::tryParseRegister(unsigned &RegNo,
+OperandMatchResultTy X86AsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
bool Result =
@@ -1977,7 +1978,7 @@ bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
}
}
// Register, or (MASM only) <register>.<field>
- unsigned Reg;
+ MCRegister Reg;
if (Tok.is(AsmToken::Identifier)) {
if (!ParseRegister(Reg, IdentLoc, End, /*RestoreOnFailure=*/true)) {
if (SM.onRegister(Reg, ErrMsg))
@@ -2528,8 +2529,8 @@ bool X86AsmParser::parseIntelOperand(OperandVector &Operands, StringRef Name) {
return ParseRoundingModeOp(Start, Operands);
// Register operand.
- unsigned RegNo = 0;
- if (Tok.is(AsmToken::Identifier) && !ParseRegister(RegNo, Start, End)) {
+ MCRegister RegNo;
+ if (Tok.is(AsmToken::Identifier) && !parseRegister(RegNo, Start, End)) {
if (RegNo == X86::RIP)
return Error(Start, "rip can only be used as a base register");
// A Register followed by ':' is considered a segment override
@@ -2840,9 +2841,9 @@ bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands) {
SMLoc StartLoc = Z ? consumeToken() : consumedToken;
// Parse an op-mask register mark ({%k<NUM>}), which is now to be
// expected
- unsigned RegNo;
+ MCRegister RegNo;
SMLoc RegLoc;
- if (!ParseRegister(RegNo, RegLoc, StartLoc) &&
+ if (!parseRegister(RegNo, RegLoc, StartLoc) &&
X86MCRegisterClasses[X86::VK1RegClassID].contains(RegNo)) {
if (RegNo == X86::K0)
return Error(RegLoc, "Register k0 can't be used as write mask");
@@ -3070,8 +3071,8 @@ bool X86AsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
(isParsingIntelSyntax() && getTok().is(AsmToken::Identifier) &&
MatchRegisterName(Parser.getTok().getString()))) {
SMLoc StartLoc = Parser.getTok().getLoc();
- unsigned RegNo;
- if (ParseRegister(RegNo, StartLoc, EndLoc))
+ MCRegister RegNo;
+ if (parseRegister(RegNo, StartLoc, EndLoc))
return true;
Res = X86MCExpr::create(RegNo, Parser.getContext());
return false;
@@ -4791,18 +4792,18 @@ bool X86AsmParser::parseDirectiveFPOProc(SMLoc L) {
// .cv_fpo_setframe ebp
bool X86AsmParser::parseDirectiveFPOSetFrame(SMLoc L) {
- unsigned Reg;
+ MCRegister Reg;
SMLoc DummyLoc;
- if (ParseRegister(Reg, DummyLoc, DummyLoc) || parseEOL())
+ if (parseRegister(Reg, DummyLoc, DummyLoc) || parseEOL())
return true;
return getTargetStreamer().emitFPOSetFrame(Reg, L);
}
// .cv_fpo_pushreg ebx
bool X86AsmParser::parseDirectiveFPOPushReg(SMLoc L) {
- unsigned Reg;
+ MCRegister Reg;
SMLoc DummyLoc;
- if (ParseRegister(Reg, DummyLoc, DummyLoc) || parseEOL())
+ if (parseRegister(Reg, DummyLoc, DummyLoc) || parseEOL())
return true;
return getTargetStreamer().emitFPOPushReg(Reg, L);
}
@@ -4842,14 +4843,14 @@ bool X86AsmParser::parseDirectiveFPOEndProc(SMLoc L) {
}
bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID,
- unsigned &RegNo) {
+ MCRegister &RegNo) {
SMLoc startLoc = getLexer().getLoc();
const MCRegisterInfo *MRI = getContext().getRegisterInfo();
// Try parsing the argument as a register first.
if (getLexer().getTok().isNot(AsmToken::Integer)) {
SMLoc endLoc;
- if (ParseRegister(RegNo, startLoc, endLoc))
+ if (parseRegister(RegNo, startLoc, endLoc))
return true;
if (!X86MCRegisterClasses[RegClassID].contains(RegNo)) {
@@ -4882,7 +4883,7 @@ bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID,
}
bool X86AsmParser::parseDirectiveSEHPushReg(SMLoc Loc) {
- unsigned Reg = 0;
+ MCRegister Reg;
if (parseSEHRegisterNumber(X86::GR64RegClassID, Reg))
return true;
@@ -4895,7 +4896,7 @@ bool X86AsmParser::parseDirectiveSEHPushReg(SMLoc Loc) {
}
bool X86AsmParser::parseDirectiveSEHSetFrame(SMLoc Loc) {
- unsigned Reg = 0;
+ MCRegister Reg;
int64_t Off;
if (parseSEHRegisterNumber(X86::GR64RegClassID, Reg))
return true;
@@ -4915,7 +4916,7 @@ bool X86AsmParser::parseDirectiveSEHSetFrame(SMLoc Loc) {
}
bool X86AsmParser::parseDirectiveSEHSaveReg(SMLoc Loc) {
- unsigned Reg = 0;
+ MCRegister Reg;
int64_t Off;
if (parseSEHRegisterNumber(X86::GR64RegClassID, Reg))
return true;
@@ -4935,7 +4936,7 @@ bool X86AsmParser::parseDirectiveSEHSaveReg(SMLoc Loc) {
}
bool X86AsmParser::parseDirectiveSEHSaveXMM(SMLoc Loc) {
- unsigned Reg = 0;
+ MCRegister Reg;
int64_t Off;
if (parseSEHRegisterNumber(X86::VR128XRegClassID, Reg))
return true;
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