[llvm] 9ec5b51 - [InstCombine] add tests for flooring division; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 18 04:10:05 PST 2022
Author: Sanjay Patel
Date: 2022-12-18T06:48:09-05:00
New Revision: 9ec5b512b67013f0b78460061a6c984a709f423f
URL: https://github.com/llvm/llvm-project/commit/9ec5b512b67013f0b78460061a6c984a709f423f
DIFF: https://github.com/llvm/llvm-project/commit/9ec5b512b67013f0b78460061a6c984a709f423f.diff
LOG: [InstCombine] add tests for flooring division; NFC
issue #57741
Added:
Modified:
llvm/test/Transforms/InstCombine/add.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll
index 767944b412ec..3f40ad3d2517 100644
--- a/llvm/test/Transforms/InstCombine/add.ll
+++ b/llvm/test/Transforms/InstCombine/add.ll
@@ -1038,8 +1038,8 @@ define i32 @add_to_sub2(i32 %A, i32 %M) {
; (X | C1) + C2 --> (X | C1) ^ C1 iff (C1 == -C2)
define i32 @test44(i32 %A) {
; CHECK-LABEL: @test44(
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -124
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = and i32 [[A:%.*]], -124
+; CHECK-NEXT: ret i32 [[C]]
;
%B = or i32 %A, 123
%C = add i32 %B, -123
@@ -1049,8 +1049,8 @@ define i32 @test44(i32 %A) {
define i32 @test44_extra_use(i32 %A) {
; CHECK-LABEL: @test44_extra_use(
; CHECK-NEXT: [[B:%.*]] = or i32 [[A:%.*]], 123
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A]], -124
-; CHECK-NEXT: [[D:%.*]] = mul i32 [[B]], [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = and i32 [[A]], -124
+; CHECK-NEXT: [[D:%.*]] = mul i32 [[B]], [[C]]
; CHECK-NEXT: ret i32 [[D]]
;
%B = or i32 %A, 123
@@ -1072,8 +1072,8 @@ define i32 @test44_non_matching(i32 %A) {
define <2 x i32> @test44_vec(<2 x i32> %A) {
; CHECK-LABEL: @test44_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[A:%.*]], <i32 -124, i32 -124>
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = and <2 x i32> [[A:%.*]], <i32 -124, i32 -124>
+; CHECK-NEXT: ret <2 x i32> [[C]]
;
%B = or <2 x i32> %A, <i32 123, i32 123>
%C = add <2 x i32> %B, <i32 -123, i32 -123>
@@ -2457,3 +2457,125 @@ define i9 @sext_zext_not_commute(i4 %x) {
%r = add i9 %znotx, %sx
ret i9 %r
}
+
+; PR57741
+
+define i32 @floor_sdiv(i32 %x) {
+; CHECK-LABEL: @floor_sdiv(
+; CHECK-NEXT: [[D:%.*]] = sdiv i32 [[X:%.*]], 4
+; CHECK-NEXT: [[A:%.*]] = and i32 [[X]], -2147483645
+; CHECK-NEXT: [[I:%.*]] = icmp ugt i32 [[A]], -2147483648
+; CHECK-NEXT: [[S:%.*]] = sext i1 [[I]] to i32
+; CHECK-NEXT: [[R:%.*]] = add nsw i32 [[D]], [[S]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %d = sdiv i32 %x, 4
+ %a = and i32 %x, -2147483645
+ %i = icmp ugt i32 %a, -2147483648
+ %s = sext i1 %i to i32
+ %r = add i32 %d, %s
+ ret i32 %r
+}
+
+define i8 @floor_sdiv_uses(i8 %x) {
+; CHECK-LABEL: @floor_sdiv_uses(
+; CHECK-NEXT: [[D:%.*]] = sdiv i8 [[X:%.*]], 16
+; CHECK-NEXT: call void @use(i8 [[D]])
+; CHECK-NEXT: [[A:%.*]] = and i8 [[X]], -113
+; CHECK-NEXT: call void @use(i8 [[A]])
+; CHECK-NEXT: [[I:%.*]] = icmp ugt i8 [[A]], -128
+; CHECK-NEXT: [[S:%.*]] = sext i1 [[I]] to i8
+; CHECK-NEXT: call void @use(i8 [[S]])
+; CHECK-NEXT: [[R:%.*]] = add nsw i8 [[D]], [[S]]
+; CHECK-NEXT: ret i8 [[R]]
+;
+ %d = sdiv i8 %x, 16
+ call void @use(i8 %d)
+ %a = and i8 %x, 143 ; 128 + 15
+ call void @use(i8 %a)
+ %i = icmp ugt i8 %a, 128
+ %s = sext i1 %i to i8
+ call void @use(i8 %s)
+ %r = add i8 %d, %s
+ ret i8 %r
+}
+
+define i32 @floor_sdiv_wrong_div(i32 %x) {
+; CHECK-LABEL: @floor_sdiv_wrong_div(
+; CHECK-NEXT: [[D:%.*]] = sdiv i32 [[X:%.*]], 8
+; CHECK-NEXT: [[A:%.*]] = and i32 [[X]], -2147483645
+; CHECK-NEXT: [[I:%.*]] = icmp ugt i32 [[A]], -2147483648
+; CHECK-NEXT: [[S:%.*]] = sext i1 [[I]] to i32
+; CHECK-NEXT: [[R:%.*]] = add nsw i32 [[D]], [[S]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %d = sdiv i32 %x, 8
+ %a = and i32 %x, -2147483645
+ %i = icmp ugt i32 %a, -2147483648
+ %s = sext i1 %i to i32
+ %r = add i32 %d, %s
+ ret i32 %r
+}
+
+define i32 @floor_sdiv_wrong_mask(i32 %x) {
+; CHECK-LABEL: @floor_sdiv_wrong_mask(
+; CHECK-NEXT: [[D:%.*]] = sdiv i32 [[X:%.*]], 4
+; CHECK-NEXT: ret i32 [[D]]
+;
+ %d = sdiv i32 %x, 4
+ %a = and i32 %x, 3
+ %i = icmp ugt i32 %a, -2147483648
+ %s = sext i1 %i to i32
+ %r = add i32 %d, %s
+ ret i32 %r
+}
+
+define i32 @floor_sdiv_wrong_cmp(i32 %x) {
+; CHECK-LABEL: @floor_sdiv_wrong_cmp(
+; CHECK-NEXT: [[D:%.*]] = sdiv i32 [[X:%.*]], 8
+; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr i32 [[X]], 31
+; CHECK-NEXT: [[X_LOBIT_NOT:%.*]] = xor i32 [[X_LOBIT]], -1
+; CHECK-NEXT: [[R:%.*]] = add nsw i32 [[D]], [[X_LOBIT_NOT]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %d = sdiv i32 %x, 8
+ %a = and i32 %x, -2147483645
+ %i = icmp ult i32 %a, -2147483648
+ %s = sext i1 %i to i32
+ %r = add i32 %d, %s
+ ret i32 %r
+}
+
+define i32 @floor_sdiv_wrong_ext(i32 %x) {
+; CHECK-LABEL: @floor_sdiv_wrong_ext(
+; CHECK-NEXT: [[D:%.*]] = sdiv i32 [[X:%.*]], 8
+; CHECK-NEXT: [[A:%.*]] = and i32 [[X]], -2147483645
+; CHECK-NEXT: [[I:%.*]] = icmp ugt i32 [[A]], -2147483648
+; CHECK-NEXT: [[S:%.*]] = zext i1 [[I]] to i32
+; CHECK-NEXT: [[R:%.*]] = add nsw i32 [[D]], [[S]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %d = sdiv i32 %x, 8
+ %a = and i32 %x, -2147483645
+ %i = icmp ugt i32 %a, -2147483648
+ %s = zext i1 %i to i32
+ %r = add i32 %d, %s
+ ret i32 %r
+}
+
+define i32 @floor_sdiv_wrong_op(i32 %x, i32 %y) {
+; CHECK-LABEL: @floor_sdiv_wrong_op(
+; CHECK-NEXT: [[D:%.*]] = sdiv i32 [[X:%.*]], 8
+; CHECK-NEXT: [[A:%.*]] = and i32 [[Y:%.*]], -2147483645
+; CHECK-NEXT: [[I:%.*]] = icmp ugt i32 [[A]], -2147483648
+; CHECK-NEXT: [[S:%.*]] = zext i1 [[I]] to i32
+; CHECK-NEXT: [[R:%.*]] = add nsw i32 [[D]], [[S]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %d = sdiv i32 %x, 8
+ %a = and i32 %y, -2147483645
+ %i = icmp ugt i32 %a, -2147483648
+ %s = zext i1 %i to i32
+ %r = add i32 %d, %s
+ ret i32 %r
+}
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