[PATCH] D140245: [PowerPC] Don't crash when disassembling invalid immediate

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai created this revision.
nemanjai added reviewers: PowerPC, rzurob.
Herald added subscribers: shchenz, kbarton, hiraditya.
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There is an assert in the disassembler functions to ensure that the immediate is the appropriate width. However, sometimes what is being disassembled is not instructions but data that happens to have the bit pattern of an existing instruction but invalid operands. It is valid for such things to exist in the `text` section so we don't want to crash when disassembling such a thing.

This patch removes the asserts and produces a disassembler failure for such cases.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140245

Files:
  llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.td
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31-invalid.txt


Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31-invalid.txt
===================================================================
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31-invalid.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31-invalid.txt
@@ -85,3 +85,7 @@
 # pstxv 31, 8589934591(3), 1. However, RA is not zero with R=1
 # CHECK: warning: invalid instruction encoding
 0x04 0x11 0xff 0xff 0xdb 0xe3 0xff 0xff
+
+# xxextractuw 52, 30, 20 (i.e. the immediate 20 is invalid)
+# CHECK: warning: invalid instruction encoding
+0xf2 0x94 0xf2 0x95
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -548,6 +548,7 @@
 def u1imm   : Operand<i32> {
   let PrintMethod = "printU1ImmOperand";
   let ParserMatchClass = PPCU1ImmAsmOperand;
+  let DecoderMethod = "decodeUImmOperand<1>";
   let OperandType = "OPERAND_IMMEDIATE";
 }
 
@@ -558,6 +559,7 @@
 def u2imm   : Operand<i32> {
   let PrintMethod = "printU2ImmOperand";
   let ParserMatchClass = PPCU2ImmAsmOperand;
+  let DecoderMethod = "decodeUImmOperand<2>";
   let OperandType = "OPERAND_IMMEDIATE";
 }
 
@@ -578,6 +580,7 @@
 def u3imm   : Operand<i32> {
   let PrintMethod = "printU3ImmOperand";
   let ParserMatchClass = PPCU3ImmAsmOperand;
+  let DecoderMethod = "decodeUImmOperand<3>";
   let OperandType = "OPERAND_IMMEDIATE";
 }
 
@@ -588,6 +591,7 @@
 def u4imm   : Operand<i32> {
   let PrintMethod = "printU4ImmOperand";
   let ParserMatchClass = PPCU4ImmAsmOperand;
+  let DecoderMethod = "decodeUImmOperand<4>";
   let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCS5ImmAsmOperand : AsmOperandClass {
Index: llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
===================================================================
--- llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -239,7 +239,8 @@
 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
                                       int64_t Address,
                                       const MCDisassembler *Decoder) {
-  assert(isUInt<N>(Imm) && "Invalid immediate");
+  if (!isUInt<N>(Imm))
+    return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
@@ -248,7 +249,8 @@
 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
                                       int64_t Address,
                                       const MCDisassembler *Decoder) {
-  assert(isUInt<N>(Imm) && "Invalid immediate");
+  if (!isUInt<N>(Imm))
+    return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
   return MCDisassembler::Success;
 }


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