[PATCH] D133955: [AArch64][CostModel] Add costs for fixed operations when using fixed vectors over SVE

Fri Dec 16 08:42:35 PST 2022

dtemirbulatov marked 2 inline comments as done.
dtemirbulatov added inline comments.

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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:1929
+  // for a fixed type to be represented upon SVE registers.
+  if (ST->hasSVE() && ST->getMinSVEVectorSizeInBits() &&
+      SrcTy.isFixedLengthVector() && DstTy.isFixedLengthVector() &&
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paulwalker-arm wrote:
> With my suggestion below (the useSVEForFixedLengthVectors one) I'm hoping you don't need these conditions?
In my latest revision, I have code WiderTy.getFixedSizeInBits() / ST->getMinSVEVectorSizeInBits() and I noticed this test:
%v15 = zext <vscale x 2 x i32> %loadnxv2i32 to <vscale x 2 x i64> which was invoked without any SVE flag. Here we encountered scalable type and somehow "ST->hasSVE()" became positive but ST->getMinSVEVectorSizeInBits()  equal to zero and we hit divide by zero.

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  https://reviews.llvm.org/D133955/new/

https://reviews.llvm.org/D133955