[llvm] 5c94fab - [TTI] [AArch64] getMemoryOpCost for ptr types

[Sjoerd Meijer via llvm-commits]

Author: Sjoerd Meijer
Date: 2022-12-16T15:38:17Z
New Revision: 5c94faba0bba628aaa5c1f034ef04acd40f7adb2

URL: https://github.com/llvm/llvm-project/commit/5c94faba0bba628aaa5c1f034ef04acd40f7adb2
DIFF: https://github.com/llvm/llvm-project/commit/5c94faba0bba628aaa5c1f034ef04acd40f7adb2.diff

LOG: [TTI] [AArch64] getMemoryOpCost for ptr types

Opaque ptr types have a size in bits of 0. The legalised type is an i64 or
vector of i64s, which do have a size. Because of this difference in size, target
hook getMemoryOpCost modelled stores of ptr types as extending/truncating
load/stores. Now we just check for opaque ptr types and return the legalised
cost. This makes stores of pointers cheaper, and as a result we now SLP
vectorise the changed test case.

Differential Revision: https://reviews.llvm.org/D140193

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    llvm/test/Analysis/CostModel/AArch64/store-ptr.ll
    llvm/test/Transforms/SLPVectorizer/AArch64/store-ptr.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index eaa303182f5d..ea2d1eb6f940 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -2451,6 +2451,10 @@ InstructionCost AArch64TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Ty,
     return LT.first * 2 * AmortizationCost;
   }
 
+  // Opaque ptr or ptr vector types are i64s and can be lowered to STP/LDPs.
+  if (Ty->isPtrOrPtrVectorTy())
+    return LT.first;
+
   // Check truncating stores and extending loads.
   if (useNeonVector(Ty) &&
       Ty->getScalarSizeInBits() != LT.second.getScalarSizeInBits()) {

diff  --git a/llvm/test/Analysis/CostModel/AArch64/store-ptr.ll b/llvm/test/Analysis/CostModel/AArch64/store-ptr.ll
index 93749c4083ab..eeff62fbc693 100644
--- a/llvm/test/Analysis/CostModel/AArch64/store-ptr.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/store-ptr.ll
@@ -5,9 +5,9 @@
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-v256:32:256-a0:0:32-n32-S32"
 define void @getMemoryOpCost() {
 ; CHECK-LABEL: 'getMemoryOpCost'
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: store <2 x ptr> undef, ptr undef, align 4
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: store <4 x ptr> undef, ptr undef, align 4
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: store <8 x ptr> undef, ptr undef, align 4
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: store <2 x ptr> undef, ptr undef, align 4
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: store <4 x ptr> undef, ptr undef, align 4
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: store <8 x ptr> undef, ptr undef, align 4
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
 ;
 ; SIZE-LABEL: 'getMemoryOpCost'

diff  --git a/llvm/test/Transforms/SLPVectorizer/AArch64/store-ptr.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/store-ptr.ll
index f0f02215fefa..e32e5f82991d 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/store-ptr.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/store-ptr.ll
@@ -23,13 +23,9 @@ define void @copy(ptr nocapture noundef writeonly %x, ptr nocapture noundef read
 ; CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i64>, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA0:![0-9]+]]
 ; CHECK-NEXT:    store <2 x i64> [[TMP0]], ptr [[ARRAYIDX2]], align 8, !tbaa [[TBAA0]]
 ; CHECK-NEXT:    [[C:%.*]] = getelementptr inbounds [[STRUCT_NODE]], ptr [[Y]], i64 [[INDVARS_IV]], i32 2
-; CHECK-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C]], align 8, !tbaa [[TBAA4:![0-9]+]]
 ; CHECK-NEXT:    [[C13:%.*]] = getelementptr inbounds [[STRUCT_NODE]], ptr [[X]], i64 [[INDVARS_IV]], i32 2
-; CHECK-NEXT:    store ptr [[TMP1]], ptr [[C13]], align 8, !tbaa [[TBAA4]]
-; CHECK-NEXT:    [[D:%.*]] = getelementptr inbounds [[STRUCT_NODE]], ptr [[Y]], i64 [[INDVARS_IV]], i32 3
-; CHECK-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[D]], align 8, !tbaa [[TBAA7:![0-9]+]]
-; CHECK-NEXT:    [[D18:%.*]] = getelementptr inbounds [[STRUCT_NODE]], ptr [[X]], i64 [[INDVARS_IV]], i32 3
-; CHECK-NEXT:    store ptr [[TMP2]], ptr [[D18]], align 8, !tbaa [[TBAA7]]
+; CHECK-NEXT:    [[TMP1:%.*]] = load <2 x ptr>, ptr [[C]], align 8, !tbaa [[TBAA4:![0-9]+]]
+; CHECK-NEXT:    store <2 x ptr> [[TMP1]], ptr [[C13]], align 8, !tbaa [[TBAA4]]
 ; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
 ; CHECK-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
 ; CHECK-NEXT:    br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]