[PATCH] D140200: [AArch64][InstCombine] Combine ADD and MUL AArch64 instrinsics to MAD

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:1079
+// Fold (ADD p c (MUL p a b)) -> (MAD p a b c)
+static std::optional<Instruction *> instCombineSVEVectorMAD(InstCombiner &IC,
+                                                            IntrinsicInst &II) {
----------------
This function looks very similar to instCombineSVEVectorFMLA, I think we could combine them. There are some subtle differences though:
* Fast-math flags can only be copied if the type is floating-point.
* MAD is different from MLA in that the result is merged into the multiplicant, not the addend. You could pass a parameter `WriteAddend` that is used like this:
```
  Value *A = II.getOperand(1);
  Value *Mul = II.getOperand(2);
  if (!WriteAddend)
    std::swap(A, Mul);
  if (!match(Mul, m_Intrinsic<Intrinsic::aarch64_sve_mul>(...))
```
* If you pass in the opcode to test for (in this case `Intrinsic::aarch64_sve_mul`) and the result `Intrinsic::aarch64_sve_mad`, then you could generalise this.


================
Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:1499
+    return instCombineSVEVectorAdd(IC, II);
   case Intrinsic::aarch64_sve_fsub:
     return instCombineSVEVectorBinOp(IC, II);
----------------
It would be nice if we could do the same thing for subtracts (fmls/fmsb/mls/msb)


================
Comment at: llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-muladd.ll:110
+  %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
+  %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %c, <vscale x 16 x i8> %1)
+  ret <vscale x 16 x i8> %2
----------------
The result is merged into `%c`, not the multiplicant (`%1`), so this should be resulting in `sve.mla` instead.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140200/new/

https://reviews.llvm.org/D140200