[llvm] 947d4fb - [AArch64] RASv2 Assembly Support
Archibald Elliott via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 16 06:38:20 PST 2022
Author: Archibald Elliott
Date: 2022-12-16T14:37:35Z
New Revision: 947d4fb37336389255950d77760ede81708c5466
URL: https://github.com/llvm/llvm-project/commit/947d4fb37336389255950d77760ede81708c5466
DIFF: https://github.com/llvm/llvm-project/commit/947d4fb37336389255950d77760ede81708c5466.diff
LOG: [AArch64] RASv2 Assembly Support
This feature adds upstream support for FEAT_RASv2 and FEAT_PFAR. Both
are system-register-only, but FEAT_RAS is behind the command-line
extension "+ras", so FEAT_RASv2 is behind "+rasv2".
This patch includes support for ID_AA64MMFR4_EL1. This is an ID system
register so it is not behind any feature flags.
Differential Revision: https://reviews.llvm.org/D139936
Added:
llvm/test/MC/AArch64/armv8.9a-pfar.s
llvm/test/MC/AArch64/armv8.9a-rasv2-error.s
llvm/test/MC/AArch64/armv8.9a-rasv2.s
llvm/test/MC/Disassembler/AArch64/armv8.9a-pfar.txt
llvm/test/MC/Disassembler/AArch64/armv8.9a-rasv2.txt
Modified:
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64SystemOperands.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/test/MC/AArch64/arm64-system-encoding.s
llvm/test/MC/AArch64/armv9a-rme.s
llvm/test/MC/AArch64/basic-a64-diagnostics.s
llvm/test/MC/AArch64/basic-a64-instructions.s
llvm/test/MC/AArch64/directive-arch_extension-negative.s
llvm/test/MC/AArch64/directive-arch_extension.s
llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt
llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
llvm/unittests/Support/TargetParserTest.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def b/llvm/include/llvm/Support/AArch64TargetParser.def
index 2c6b3f0bb5f0d..4ac5d2b99c31c 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -63,7 +63,8 @@ AARCH64_ARCH("armv8.9-a", ARMV8_9A, "+v8.9a",
AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 |
- AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM))
+ AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM |
+ AArch64::AEK_RASv2))
AARCH64_ARCH("armv9-a", ARMV9A, "+v9a",
(AArch64::AEK_CRC | AArch64::AEK_FP |
AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
@@ -88,7 +89,8 @@ AARCH64_ARCH("armv9.4-a", ARMV9_4A, "+v9.4a",
(AArch64::AEK_CRC | AArch64::AEK_FP |
AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
- AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2))
+ AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2 |
+ AArch64::AEK_RASv2))
// For v8-R, we do not enable crypto and align with GCC that enables a more
// minimal set of optional architecture extensions.
AARCH64_ARCH("armv8-r", ARMV8R, "+v8r",
@@ -119,6 +121,7 @@ AARCH64_ARCH_EXT_NAME("fp16", AArch64::AEK_FP16, "+fullfp16",
AARCH64_ARCH_EXT_NAME("fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml")
AARCH64_ARCH_EXT_NAME("profile", AArch64::AEK_PROFILE, "+spe", "-spe")
AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras")
+AARCH64_ARCH_EXT_NAME("rasv2", AArch64::AEK_RASv2, "+rasv2", "-rasv2")
AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve")
AARCH64_ARCH_EXT_NAME("sve2", AArch64::AEK_SVE2, "+sve2", "-sve2")
AARCH64_ARCH_EXT_NAME("sve2-aes", AArch64::AEK_SVE2AES, "+sve2-aes", "-sve2-aes")
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.h b/llvm/include/llvm/Support/AArch64TargetParser.h
index 2779788972eb1..d468dbd116110 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.h
+++ b/llvm/include/llvm/Support/AArch64TargetParser.h
@@ -83,6 +83,7 @@ enum ArchExtKind : uint64_t {
AEK_D128 = 1ULL << 51, // FEAT_D128
AEK_LSE128 = 1ULL << 52, // FEAT_LSE128
AEK_SPECRES2 = 1ULL << 53, // FEAT_SPECRES2
+ AEK_RASv2 = 1ULL << 54, // FEAT_RASv2
};
// clang-format on
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 78958e01c2a7d..23174d26df4f2 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -64,6 +64,10 @@ def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
"Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">;
+def FeatureRASv2 : SubtargetFeature<"rasv2", "HasRASv2", "true",
+ "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)",
+ [FeatureRAS]>;
+
def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
"Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)">;
@@ -589,7 +593,7 @@ def HasV8_8aOps : SubtargetFeature<
def HasV8_9aOps : SubtargetFeature<
"v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions",
[HasV8_8aOps, FeatureCLRBHB, FeaturePRFM_SLC, FeatureSPECRES2,
- FeatureCSSC]>;
+ FeatureCSSC, FeatureRASv2]>;
def HasV9_0aOps : SubtargetFeature<
"v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions",
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 06dd215e71d3d..275ea72e9daf7 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -722,6 +722,7 @@ def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>;
def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>;
def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010>;
def : ROSysReg<"ID_AA64MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b011>;
+def : ROSysReg<"ID_AA64MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b100>;
def : ROSysReg<"MVFR0_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b000>;
def : ROSysReg<"MVFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b001>;
def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>;
@@ -820,10 +821,12 @@ def : RWSysReg<"SCXTNUM_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b111>;
// v9a Realm Management Extension registers
let Requires = [{ {AArch64::FeatureRME} }] in {
-def : RWSysReg<"MFAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b101>;
def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>;
def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>;
}
+// MFAR_EL3 is part of both FEAT_RME and FEAT_PFAR (further below). The latter
+// is unconditional so this register has to be too.
+def : RWSysReg<"MFAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b101>;
// v9a Memory Encryption Contexts Extension registers
let Requires = [{ {AArch64::FeatureMEC} }] in {
@@ -1863,3 +1866,14 @@ def : RWSysReg<"TRCITECR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b011>;
// v8.9a/9.4a SPE Data Source Filtering (FEAT_SPE_FDS)
// Op0 Op1 CRn CRm Op2
def : RWSysReg<"PMSDSFR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b100>;
+
+// v8.9a/9.4a RASv2 (FEAT_RASv2)
+// Op0 Op1 CRn CRm Op2
+let Requires = [{ {AArch64::FeatureRASv2} }] in
+def : ROSysReg<"ERXGSR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b010>;
+
+// v8.9a/9.4a Physical Fault Address (FEAT_PFAR)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"PFAR_EL1", 0b11, 0b000, 0b0110, 0b0000, 0b101>;
+def : RWSysReg<"PFAR_EL12", 0b11, 0b101, 0b0110, 0b0000, 0b101>;
+def : RWSysReg<"PFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b101>;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 90cafd4a0a539..45690ac76c00c 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3637,6 +3637,7 @@ static const struct Extension {
{"fp", {AArch64::FeatureFPARMv8}},
{"simd", {AArch64::FeatureNEON}},
{"ras", {AArch64::FeatureRAS}},
+ {"rasv2", {AArch64::FeatureRASv2}},
{"lse", {AArch64::FeatureLSE}},
{"predres", {AArch64::FeaturePredRes}},
{"predres2", {AArch64::FeatureSPECRES2}},
diff --git a/llvm/test/MC/AArch64/arm64-system-encoding.s b/llvm/test/MC/AArch64/arm64-system-encoding.s
index fc769e221cba4..43e69e2926461 100644
--- a/llvm/test/MC/AArch64/arm64-system-encoding.s
+++ b/llvm/test/MC/AArch64/arm64-system-encoding.s
@@ -338,6 +338,7 @@ foo:
mrs x3, ID_AA64MMFR1_EL1
mrs x3, ID_AA64MMFR2_EL1
mrs x3, ID_AA64MMFR3_EL1
+ mrs x3, ID_AA64MMFR4_EL1
mrs x3, ID_AA64PFR0_EL1
mrs x3, ID_AA64PFR1_EL1
mrs x3, ID_AA64PFR2_EL1
@@ -556,6 +557,7 @@ foo:
; CHECK: mrs x3, ID_AA64MMFR1_EL1 ; encoding: [0x23,0x07,0x38,0xd5]
; CHECK: mrs x3, ID_AA64MMFR2_EL1 ; encoding: [0x43,0x07,0x38,0xd5]
; CHECK: mrs x3, ID_AA64MMFR3_EL1 ; encoding: [0x63,0x07,0x38,0xd5]
+; CHECK: mrs x3, ID_AA64MMFR4_EL1 ; encoding: [0x83,0x07,0x38,0xd5]
; CHECK: mrs x3, ID_AA64PFR0_EL1 ; encoding: [0x03,0x04,0x38,0xd5]
; CHECK: mrs x3, ID_AA64PFR1_EL1 ; encoding: [0x23,0x04,0x38,0xd5]
; CHECK: mrs x3, ID_AA64PFR2_EL1 ; encoding: [0x43,0x04,0x38,0xd5]
diff --git a/llvm/test/MC/AArch64/armv8.9a-pfar.s b/llvm/test/MC/AArch64/armv8.9a-pfar.s
new file mode 100644
index 0000000000000..eff48c78b76f4
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.9a-pfar.s
@@ -0,0 +1,21 @@
+// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s
+
+mrs x0, PFAR_EL1
+// CHECK: mrs x0, PFAR_EL1 // encoding: [0xa0,0x60,0x38,0xd5]
+msr PFAR_EL1, x0
+// CHECK: msr PFAR_EL1, x0 // encoding: [0xa0,0x60,0x18,0xd5]
+
+mrs x0, PFAR_EL2
+// CHECK: mrs x0, PFAR_EL2 // encoding: [0xa0,0x60,0x3c,0xd5]
+msr PFAR_EL2, x0
+// CHECK: msr PFAR_EL2, x0 // encoding: [0xa0,0x60,0x1c,0xd5]
+
+mrs x0, PFAR_EL12
+// CHECK: mrs x0, PFAR_EL12 // encoding: [0xa0,0x60,0x3d,0xd5]
+msr PFAR_EL12, x0
+// CHECK: msr PFAR_EL12, x0 // encoding: [0xa0,0x60,0x1d,0xd5]
+
+mrs x0, MFAR_EL3
+// CHECK: mrs x0, MFAR_EL3 // encoding: [0xa0,0x60,0x3e,0xd5]
+msr MFAR_EL3, x0
+// CHECK: msr MFAR_EL3, x0 // encoding: [0xa0,0x60,0x1e,0xd5]
diff --git a/llvm/test/MC/AArch64/armv8.9a-rasv2-error.s b/llvm/test/MC/AArch64/armv8.9a-rasv2-error.s
new file mode 100644
index 0000000000000..7f5d89d0a460c
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.9a-rasv2-error.s
@@ -0,0 +1,4 @@
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+rasv2 < %s 2>&1| FileCheck %s
+
+msr ERXGSR_EL1, x0
+// CHECK: [[@LINE-1]]:5: error: expected writable system register or pstate
diff --git a/llvm/test/MC/AArch64/armv8.9a-rasv2.s b/llvm/test/MC/AArch64/armv8.9a-rasv2.s
new file mode 100644
index 0000000000000..8caa700aeaf9e
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.9a-rasv2.s
@@ -0,0 +1,9 @@
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+rasv2 < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.9a < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v9.4a < %s | FileCheck %s
+
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RAS %s
+
+mrs x0, ERXGSR_EL1
+// CHECK: mrs x0, ERXGSR_EL1 // encoding: [0x40,0x53,0x38,0xd5]
+// ERROR-NO-RAS: [[@LINE-2]]:9: error: expected readable system register
diff --git a/llvm/test/MC/AArch64/armv9a-rme.s b/llvm/test/MC/AArch64/armv9a-rme.s
index 0a575fa8ae579..29ff1ab700b26 100644
--- a/llvm/test/MC/AArch64/armv9a-rme.s
+++ b/llvm/test/MC/AArch64/armv9a-rme.s
@@ -15,10 +15,10 @@ mrs x0, GPTBR_EL3
// CHECK: mrs x0, MFAR_EL3 // encoding: [0xa0,0x60,0x3e,0xd5]
// CHECK: mrs x0, GPCCR_EL3 // encoding: [0xc0,0x21,0x3e,0xd5]
// CHECK: mrs x0, GPTBR_EL3 // encoding: [0x80,0x21,0x3e,0xd5]
+// CHECK-NO-RME: msr MFAR_EL3, x0 // encoding: [0xa0,0x60,0x1e,0xd5]
// CHECK-NO-RME-ERROR: [[@LINE-12]]:5: error: expected writable system register
// CHECK-NO-RME-ERROR: [[@LINE-12]]:5: error: expected writable system register
-// CHECK-NO-RME-ERROR: [[@LINE-12]]:5: error: expected writable system register
-// CHECK-NO-RME-ERROR: [[@LINE-12]]:9: error: expected readable system register
+// CHECK-NO-RME: mrs x0, MFAR_EL3 // encoding: [0xa0,0x60,0x3e,0xd5]
// CHECK-NO-RME-ERROR: [[@LINE-12]]:9: error: expected readable system register
// CHECK-NO-RME-ERROR: [[@LINE-12]]:9: error: expected readable system register
diff --git a/llvm/test/MC/AArch64/basic-a64-diagnostics.s b/llvm/test/MC/AArch64/basic-a64-diagnostics.s
index b4ebf991281b2..7f040e0838161 100644
--- a/llvm/test/MC/AArch64/basic-a64-diagnostics.s
+++ b/llvm/test/MC/AArch64/basic-a64-diagnostics.s
@@ -3607,6 +3607,7 @@
msr ID_AA64MMFR1_EL1, x12
msr ID_AA64MMFR2_EL1, x12
msr ID_AA64MMFR3_EL1, x12
+ msr ID_AA64MMFR4_EL1, x12
msr PMCEID0_EL0, x12
msr PMCEID1_EL0, x12
msr PMMIR_EL1, x12
@@ -3760,6 +3761,9 @@
// CHECK-ERROR-NEXT: msr ID_AA64MMFR3_EL1, x12
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
+// CHECK-ERROR-NEXT: msr ID_AA64MMFR4_EL1, x12
+// CHECK-ERROR-NEXT: ^
+// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr PMCEID0_EL0, x12
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s
index 207ba3c08b96b..51584abdb8e71 100644
--- a/llvm/test/MC/AArch64/basic-a64-instructions.s
+++ b/llvm/test/MC/AArch64/basic-a64-instructions.s
@@ -4375,6 +4375,7 @@ _func:
mrs x9, ID_AA64MMFR1_EL1
mrs x9, ID_AA64MMFR2_EL1
mrs x9, ID_AA64MMFR3_EL1
+ mrs x9, ID_AA64MMFR4_EL1
mrs x9, SCTLR_EL1
mrs x9, SCTLR_EL2
mrs x9, SCTLR_EL3
@@ -4710,6 +4711,7 @@ _func:
// CHECK: mrs x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}} // encoding: [0x29,0x07,0x38,0xd5]
// CHECK: mrs x9, {{id_aa64mmfr2_el1|ID_AA64MMFR2_EL1}} // encoding: [0x49,0x07,0x38,0xd5]
// CHECK: mrs x9, {{id_aa64mmfr3_el1|ID_AA64MMFR3_EL1}} // encoding: [0x69,0x07,0x38,0xd5]
+// CHECK: mrs x9, {{id_aa64mmfr4_el1|ID_AA64MMFR4_EL1}} // encoding: [0x89,0x07,0x38,0xd5]
// CHECK: mrs x9, {{sctlr_el1|SCTLR_EL1}} // encoding: [0x09,0x10,0x38,0xd5]
// CHECK: mrs x9, {{sctlr_el2|SCTLR_EL2}} // encoding: [0x09,0x10,0x3c,0xd5]
// CHECK: mrs x9, {{sctlr_el3|SCTLR_EL3}} // encoding: [0x09,0x10,0x3e,0xd5]
diff --git a/llvm/test/MC/AArch64/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
index 13588def5f8d8..bf647be7037d5 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
@@ -1,6 +1,6 @@
// RUN: not llvm-mc -triple aarch64 \
// RUN: -mattr=+crc,+sm4,+sha3,+sha2,+aes,+fp,+neon,+ras,+lse,+predres,+ccdp,+mte,+tlb-rmi,+pan-rwv,+ccpp,+rcpc,+ls64,+flagm,+hbc,+mops \
-// RUN: -mattr=+rcpc3,+lse128,+d128,+the \
+// RUN: -mattr=+rcpc3,+lse128,+d128,+the,+rasv2 \
// RUN: -filetype asm -o - %s 2>&1 | FileCheck %s
.arch_extension axp64
@@ -168,3 +168,10 @@ rcwswp x0, x1, [x2]
rcwswp x0, x1, [x2]
// CHECK: [[@LINE-1]]:1: error: instruction requires: the
// CHECK-NEXT: rcwswp x0, x1, [x2]
+
+mrs x0, ERXGSR_EL1
+// CHECK-NOT: [[@LINE-1]]:9: error: expected readable system register
+.arch_extension norasv2
+mrs x0, ERXGSR_EL1
+// CHECK: [[@LINE-1]]:9: error: expected readable system register
+// CHECK-NEXT: mrs x0, ERXGSR_EL1
diff --git a/llvm/test/MC/AArch64/directive-arch_extension.s b/llvm/test/MC/AArch64/directive-arch_extension.s
index 101c48b689380..092c5784f2f4c 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension.s
@@ -104,3 +104,7 @@ sysp #0, c2, c0, #0, x0, x1
rcwcasp x0, x1, x6, x7, [x4]
// CHECK: sysp #0, c2, c0, #0, x0, x1
// CHECK: rcwcasp x0, x1, x6, x7, [x4]
+
+.arch_extension rasv2
+mrs x0, ERXGSR_EL1
+// CHECK: mrs x0, ERXGSR_EL1
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.9a-pfar.txt b/llvm/test/MC/Disassembler/AArch64/armv8.9a-pfar.txt
new file mode 100644
index 0000000000000..8b82ace16f579
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.9a-pfar.txt
@@ -0,0 +1,25 @@
+# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s
+
+[0xa0,0x60,0x38,0xd5]
+# CHECK: mrs x0, PFAR_EL1
+
+[0xa0,0x60,0x18,0xd5]
+# CHECK: msr PFAR_EL1, x0
+
+[0xa0,0x60,0x3c,0xd5]
+# CHECK: mrs x0, PFAR_EL2
+
+[0xa0,0x60,0x1c,0xd5]
+# CHECK: msr PFAR_EL2, x0
+
+[0xa0,0x60,0x3d,0xd5]
+# CHECK: mrs x0, PFAR_EL12
+
+[0xa0,0x60,0x1d,0xd5]
+# CHECK: msr PFAR_EL12, x0
+
+[0xa0,0x60,0x3e,0xd5]
+# CHECK: mrs x0, MFAR_EL3
+
+[0xa0,0x60,0x1e,0xd5]
+# CHECK: msr MFAR_EL3, x0
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.9a-rasv2.txt b/llvm/test/MC/Disassembler/AArch64/armv8.9a-rasv2.txt
new file mode 100644
index 0000000000000..78a5f54fd6bb4
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.9a-rasv2.txt
@@ -0,0 +1,13 @@
+# RUN: llvm-mc -triple aarch64 -disassemble -mattr=+rasv2 < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64 -disassemble -mattr=+v8.9a < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64 -disassemble -mattr=+v9.4a < %s | FileCheck %s
+
+# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s --check-prefix=NO-RAS
+
+[0x40,0x53,0x38,0xd5]
+# CHECK: mrs x0, ERXGSR_EL1
+# NO-RAS: mrs x0, S3_0_C5_C3_2
+
+[0x40,0x53,0x18,0xd5]
+# CHECK: msr S3_0_C5_C3_2, x0
+# NO-RAS: msr S3_0_C5_C3_2, x0
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt b/llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt
index f10a07ce1e8ab..c0bb1a6b76b7c 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt
@@ -7,7 +7,7 @@
# CHECK: mrs x0, MFAR_EL3
# CHECK: mrs x0, GPCCR_EL3
# CHECK: mrs x0, GPTBR_EL3
-# CHECK-NO-RME: mrs x0, S3_6_C6_C0_5
+# CHECK-NO-RME: mrs x0, MFAR_EL3
# CHECK-NO-RME: mrs x0, S3_6_C2_C1_6
# CHECK-NO-RME: mrs x0, S3_6_C2_C1_4
@@ -22,4 +22,4 @@
# CHECK-NO-RME: sys #6, c8, c4, #3
# CHECK-NO-RME: sys #6, c8, c4, #7
# CHECK-NO-RME: sys #6, c8, c1, #4
-# CHECK-NO-RME: sys #6, c8, c7, #4
\ No newline at end of file
+# CHECK-NO-RME: sys #6, c8, c7, #4
diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
index 429950928893a..9b081974b40c7 100644
--- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
+++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -3567,6 +3567,7 @@
# CHECK: mrs x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}}
# CHECK: mrs x9, {{id_aa64mmfr2_el1|ID_AA64MMFR2_EL1}}
# CHECK: mrs x9, {{id_aa64mmfr3_el1|ID_AA64MMFR3_EL1}}
+# CHECK: mrs x9, {{id_aa64mmfr4_el1|ID_AA64MMFR4_EL1}}
# CHECK: mrs x9, {{sctlr_el1|SCTLR_EL1}}
# CHECK: mrs x9, {{sctlr_el2|SCTLR_EL2}}
# CHECK: mrs x9, {{sctlr_el3|SCTLR_EL3}}
@@ -4186,6 +4187,7 @@
0x29 0x7 0x38 0xd5
0x49 0x7 0x38 0xd5
0x69 0x7 0x38 0xd5
+0x89 0x7 0x38 0xd5
0x9 0x10 0x38 0xd5
0x9 0x10 0x3c 0xd5
0x9 0x10 0x3e 0xd5
diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp
index 0161be254562e..2e0be9e45d3a8 100644
--- a/llvm/unittests/Support/TargetParserTest.cpp
+++ b/llvm/unittests/Support/TargetParserTest.cpp
@@ -1608,7 +1608,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1, AArch64::AEK_SME2p1,
AArch64::AEK_B16B16, AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
AArch64::AEK_RCPC3, AArch64::AEK_THE, AArch64::AEK_D128,
- AArch64::AEK_LSE128, AArch64::AEK_SPECRES2,
+ AArch64::AEK_LSE128, AArch64::AEK_SPECRES2, AArch64::AEK_RASv2,
};
std::vector<StringRef> Features;
@@ -1773,6 +1773,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"mops", "nomops", "+mops", "-mops"},
{"pmuv3", "nopmuv3", "+perfmon", "-perfmon"},
{"predres2", "nopredres2", "+specres2", "-specres2"},
+ {"rasv2", "norasv2", "+rasv2", "-rasv2"},
};
for (unsigned i = 0; i < std::size(ArchExt); i++) {
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