[PATCH] D140205: [WebAssembly] Fix crash when selecting 64 bit lane extract operand

[Luke Lau via Phabricator via llvm-commits]

luke created this revision.
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The tablegen patterns on vector_extract only match i32 constants, but
on wasm64 these come in as i64 constants. In certain situations this
would cause crashes whenever it couldn't select an extract_vector_elt
instruction.
Rather than add duplicate patterns for every instruction, this just
canonicalizes the constant to be i32 when lowering.
Fixes PR#57577


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140205

Files:
  llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  llvm/test/CodeGen/WebAssembly/simd-extract64.ll


Index: llvm/test/CodeGen/WebAssembly/simd-extract64.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/WebAssembly/simd-extract64.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -mattr=+simd128 -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals
+
+; Regression test for a crash on wasmm64 when trying to lower extract_vector_elt
+; with a 64 bit constant:
+;
+; t19: i64 = extract_vector_elt t18, Constant:i64<0>
+
+target triple = "wasm64-unknown-unknown"
+
+define void @foo() {
+  store <4 x i32> zeroinitializer, ptr poison, align 16
+  %1 = load <4 x i32>, ptr poison, align 16
+  %2 = extractelement <4 x i32> %1, i32 0
+  %3 = insertelement <2 x i32> undef, i32 %2, i32 0
+  %4 = insertelement <2 x i32> %3, i32 poison, i32 1
+  store <2 x i32> %4, ptr poison, align 8
+  unreachable
+}
Index: llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
===================================================================
--- llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -2245,11 +2245,16 @@
                                                     SelectionDAG &DAG) const {
   // Allow constant lane indices, expand variable lane indices
   SDNode *IdxNode = Op.getOperand(Op.getNumOperands() - 1).getNode();
-  if (isa<ConstantSDNode>(IdxNode) || IdxNode->isUndef())
-    return Op;
-  else
-    // Perform default expansion
-    return SDValue();
+  if (isa<ConstantSDNode>(IdxNode) || IdxNode->isUndef()) {
+    // Ensure the index type is i32 to match the tablegen patterns
+    uint64_t Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
+    SmallVector<SDValue, 3> Ops(Op.getNode()->ops());
+    Ops[Op.getNumOperands() - 1] =
+        DAG.getConstant(Idx, SDLoc(IdxNode), MVT::i32);
+    return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), Ops);
+  }
+  // Perform default expansion
+  return SDValue();
 }
 
 static SDValue unrollVectorShift(SDValue Op, SelectionDAG &DAG) {


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