[PATCH] D138696: [PowerPC] Exploit test data class instruction for isinf/iszero

[ChenZheng via Phabricator via llvm-commits]

shchenz added a comment.

Thanks for working on this, I think it should be workable. However seems adding a new PPCISD would be preferable, like PPCISD::FP_CLASS? You can find same handling in AMDGPU arch FP_CLASS node.
With this new ISD:
1: we can leverage the table-gen to select the instruction.
2: we can do further combine
3: maybe this node can also be used for the fp class intrinsics like `int_ppc_test_data_class_f` and `int_ppc_test_data_class_d`?



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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14145
+      DC_NEG_SUBNORM = 1,
+      DC_POS_SUBNORM = 1 << 1,
+    };
----------------
Can we make these enums be ordered?


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14159
+        else if (APF.isNegZero())
+          Mask = IsAbsolute ? 0 : DC_NEG_ZERO;
+      }
----------------
Any reason we don't handle NAN and denormal inputs?


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  https://reviews.llvm.org/D138696/new/

https://reviews.llvm.org/D138696