[PATCH] D139996: [RISCV] Disable callee-saved register when the register is written by llvm.write_register intrinsic

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

If you're touching registers this way they should be reserved



================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1859
+    MachineRegisterInfo &MRI = MF->getRegInfo();
+    MRI.disableCalleeSavedRegister(Reg);
+    break;
----------------
This is also one of those not-actually serialized in MIR fields


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139996/new/

https://reviews.llvm.org/D139996