[llvm] c09edce - [SelectionDAG] Give all the target specific subclasses of SelectionDAGISel their own pass ID.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 15 15:49:05 PST 2022
Author: Craig Topper
Date: 2022-12-15T15:48:55-08:00
New Revision: c09edce1b3851fa8ae8238b1adf903d491b7bc70
URL: https://github.com/llvm/llvm-project/commit/c09edce1b3851fa8ae8238b1adf903d491b7bc70
DIFF: https://github.com/llvm/llvm-project/commit/c09edce1b3851fa8ae8238b1adf903d491b7bc70.diff
LOG: [SelectionDAG] Give all the target specific subclasses of SelectionDAGISel their own pass ID.
Previously we had a shared ID in SelectionDAGISel. AMDGPU has an
initializePass function for its subclass of SelectionDAGISel. No
other target does.
This causes all target specific SelectionDAGISel passes to be known
as "amdgpu-isel".
I'm not sure what would happen if another target tried to implement
an initializePass function too since the ID is already claimed.
This patch gives all targets their own ID and passes it down to
SelectionDAGISel constructor to MachineFunctionPass's constructor.
Unfortunately, I think this causes most targets to lose
print-before/after-all support for their SelectionDAGISel pass.
And they probably no longer support start/stop-before/after. We
can add initializePass functions to fix this as a follow up. NOTE:
This was probably also broken if the AMDGPU target isn't compiled in.
Step 1 to fixing PR59538.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D140161
Added:
Modified:
llvm/include/llvm/CodeGen/SelectionDAGISel.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
llvm/lib/Target/Mips/MipsISelDAGToDAG.h
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
llvm/lib/Target/VE/VEISelDAGToDAG.cpp
llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index c395452713ad..3730ab026c66 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -62,9 +62,7 @@ class SelectionDAGISel : public MachineFunctionPass {
/// Used to report things like combines and FastISel failures.
std::unique_ptr<OptimizationRemarkEmitter> ORE;
- static char ID;
-
- explicit SelectionDAGISel(TargetMachine &tm,
+ explicit SelectionDAGISel(char &ID, TargetMachine &tm,
CodeGenOpt::Level OL = CodeGenOpt::Default);
~SelectionDAGISel() override;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 8f4709088b40..7e1ca891cd51 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -313,7 +313,8 @@ void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
// SelectionDAGISel code
//===----------------------------------------------------------------------===//
-SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL)
+SelectionDAGISel::SelectionDAGISel(char &ID, TargetMachine &tm,
+ CodeGenOpt::Level OL)
: MachineFunctionPass(ID), TM(tm), FuncInfo(new FunctionLoweringInfo()),
SwiftError(new SwiftErrorValueTracking()),
CurDAG(new SelectionDAG(tm, OL)),
@@ -3815,5 +3816,3 @@ void SelectionDAGISel::CannotYetSelect(SDNode *N) {
}
report_fatal_error(Twine(Msg.str()));
}
-
-char SelectionDAGISel::ID = 0;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 436eff92f24e..0d563b706018 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -43,9 +43,11 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
const AArch64Subtarget *Subtarget;
public:
+ static char ID;
+
explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm,
CodeGenOpt::Level OptLevel)
- : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr) {}
+ : SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr) {}
StringRef getPassName() const override {
return "AArch64 Instruction Selection";
@@ -419,6 +421,8 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
};
} // end anonymous namespace
+char AArch64DAGToDAGISel::ID = 0;
+
/// isIntImmediate - This method tests to see if the node is a constant
/// operand. If so Imm will receive the 32-bit value.
static bool isIntImmediate(const SDNode *N, uint64_t &Imm) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 2361b585ad55..0260c0e44d9a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -119,7 +119,7 @@ FunctionPass *llvm::createAMDGPUISelDag(TargetMachine *TM,
AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(
TargetMachine *TM /*= nullptr*/,
CodeGenOpt::Level OptLevel /*= CodeGenOpt::Default*/)
- : SelectionDAGISel(*TM, OptLevel) {
+ : SelectionDAGISel(ID, *TM, OptLevel) {
EnableLateStructurizeCFG = AMDGPUTargetMachine::EnableLateStructurizeCFG;
}
@@ -3001,3 +3001,5 @@ void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
CurDAG->RemoveDeadNodes();
} while (IsModified);
}
+
+char AMDGPUDAGToDAGISel::ID = 0;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
index 6025a05d4693..84f573ffb23a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
@@ -91,6 +91,8 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
bool fp16SrcZerosHighBits(unsigned Opc) const;
public:
+ static char ID;
+
explicit AMDGPUDAGToDAGISel(TargetMachine *TM = nullptr,
CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
~AMDGPUDAGToDAGISel() override = default;
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index ab8bb810f733..e34d3e9adc3c 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -58,8 +58,10 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
const ARMSubtarget *Subtarget;
public:
+ static char ID;
+
explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOpt::Level OptLevel)
- : SelectionDAGISel(tm, OptLevel) {}
+ : SelectionDAGISel(ID, tm, OptLevel) {}
bool runOnMachineFunction(MachineFunction &MF) override {
// Reset the subtarget each time through.
@@ -360,6 +362,8 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
};
}
+char ARMDAGToDAGISel::ID = 0;
+
/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
/// operand. If so Imm will receive the 32-bit value.
static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
index df364cae671c..6e10590b5621 100644
--- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
@@ -26,8 +26,10 @@ namespace llvm {
/// Lowers LLVM IR (in DAG form) to AVR MC instructions (in DAG form).
class AVRDAGToDAGISel : public SelectionDAGISel {
public:
+ static char ID;
+
AVRDAGToDAGISel(AVRTargetMachine &TM, CodeGenOpt::Level OptLevel)
- : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {}
+ : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {}
StringRef getPassName() const override {
return "AVR DAG->DAG Instruction Selection";
@@ -56,6 +58,8 @@ class AVRDAGToDAGISel : public SelectionDAGISel {
const AVRSubtarget *Subtarget;
};
+char AVRDAGToDAGISel::ID = 0;
+
bool AVRDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
Subtarget = &MF.getSubtarget<AVRSubtarget>();
return SelectionDAGISel::runOnMachineFunction(MF);
@@ -581,3 +585,4 @@ FunctionPass *createAVRISelDag(AVRTargetMachine &TM,
}
} // end of namespace llvm
+
diff --git a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
index eb506d30e526..b0358bed63db 100644
--- a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
+++ b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
@@ -45,8 +45,10 @@ class BPFDAGToDAGISel : public SelectionDAGISel {
const BPFSubtarget *Subtarget;
public:
+ static char ID;
+
explicit BPFDAGToDAGISel(BPFTargetMachine &TM)
- : SelectionDAGISel(TM), Subtarget(nullptr) {}
+ : SelectionDAGISel(ID, TM), Subtarget(nullptr) {}
StringRef getPassName() const override {
return "BPF DAG->DAG Pattern Instruction Selection";
@@ -96,6 +98,8 @@ class BPFDAGToDAGISel : public SelectionDAGISel {
};
} // namespace
+char BPFDAGToDAGISel::ID = 0;
+
// ComplexPattern used on BPF Load/Store instructions
bool BPFDAGToDAGISel::SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
// if Address is FI, get the TargetFrameIndex.
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index c2353577c336..6cda21a371e1 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -63,6 +63,8 @@ FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
}
}
+char HexagonDAGToDAGISel::ID = 0;
+
void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) {
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
index c42bef3147c0..1dd069b2ab2e 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
@@ -31,9 +31,11 @@ class HexagonDAGToDAGISel : public SelectionDAGISel {
const HexagonInstrInfo *HII;
const HexagonRegisterInfo *HRI;
public:
+ static char ID;
+
explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
CodeGenOpt::Level OptLevel)
- : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr),
+ : SelectionDAGISel(ID, tm, OptLevel), HST(nullptr), HII(nullptr),
HRI(nullptr) {}
bool runOnMachineFunction(MachineFunction &MF) override {
diff --git a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
index 45af250b1410..0327951fdefa 100644
--- a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
@@ -47,8 +47,10 @@ namespace {
class LanaiDAGToDAGISel : public SelectionDAGISel {
public:
+ static char ID;
+
explicit LanaiDAGToDAGISel(LanaiTargetMachine &TargetMachine)
- : SelectionDAGISel(TargetMachine) {}
+ : SelectionDAGISel(ID, TargetMachine) {}
bool runOnMachineFunction(MachineFunction &MF) override {
return SelectionDAGISel::runOnMachineFunction(MF);
@@ -98,6 +100,8 @@ bool canBeRepresentedAsSls(const ConstantSDNode &CN) {
} // namespace
+char LanaiDAGToDAGISel::ID = 0;
+
// Helper functions for ComplexPattern used on LanaiInstrInfo
// Used on Lanai Load/Store instructions.
bool LanaiDAGToDAGISel::selectAddrSls(SDValue Addr, SDValue &Offset) {
diff --git a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
index b623730e1574..07661abbb190 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
@@ -90,8 +90,10 @@ namespace {
namespace {
class MSP430DAGToDAGISel : public SelectionDAGISel {
public:
+ static char ID;
+
MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
- : SelectionDAGISel(TM, OptLevel) {}
+ : SelectionDAGISel(ID, TM, OptLevel) {}
private:
StringRef getPassName() const override {
@@ -119,6 +121,8 @@ namespace {
};
} // end anonymous namespace
+char MSP430DAGToDAGISel::ID;
+
/// createMSP430ISelDag - This pass converts a legalized DAG into a
/// MSP430-specific DAG, ready for instruction scheduling.
///
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
index 4fb11faa403e..5d0383f6743d 100644
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -322,3 +322,5 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
}
return true;
}
+
+char MipsDAGToDAGISel::ID = 0;
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
index a768589b374b..e607dbe87ad3 100644
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
@@ -30,8 +30,10 @@ namespace llvm {
class MipsDAGToDAGISel : public SelectionDAGISel {
public:
+ static char ID;
+
explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
- : SelectionDAGISel(TM, OL), Subtarget(nullptr) {}
+ : SelectionDAGISel(ID, TM, OL), Subtarget(nullptr) {}
// Pass Name
StringRef getPassName() const override {
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index 5b6e2cd901aa..1f706ab37cf8 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -35,9 +35,11 @@ FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
return new NVPTXDAGToDAGISel(TM, OptLevel);
}
+char NVPTXDAGToDAGISel::ID = 0;
+
NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
CodeGenOpt::Level OptLevel)
- : SelectionDAGISel(tm, OptLevel), TM(tm) {
+ : SelectionDAGISel(ID, tm, OptLevel), TM(tm) {
doMulWide = (OptLevel > 0);
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
index ce5136016f96..72f1bb2be7ac 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
@@ -38,6 +38,8 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
bool useShortPointers() const;
public:
+ static char ID;
+
explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
CodeGenOpt::Level OptLevel);
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 5386fd720af1..2d9b57bc0036 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -145,8 +145,10 @@ namespace {
unsigned GlobalBaseReg = 0;
public:
+ static char ID;
+
explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOpt::Level OptLevel)
- : SelectionDAGISel(tm, OptLevel), TM(tm) {}
+ : SelectionDAGISel(ID, tm, OptLevel), TM(tm) {}
bool runOnMachineFunction(MachineFunction &MF) override {
// Make sure we re-emit a set of the global base reg if necessary
@@ -445,6 +447,8 @@ namespace {
} // end anonymous namespace
+char PPCDAGToDAGISel::ID = 0;
+
/// getGlobalBaseReg - Output the instructions required to put the
/// base address to use for accessing globals into a register.
///
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 889575244d34..2a73b1e2a132 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2907,3 +2907,5 @@ FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM,
CodeGenOpt::Level OptLevel) {
return new RISCVDAGToDAGISel(TM, OptLevel);
}
+
+char RISCVDAGToDAGISel::ID = 0;
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index 5e45f42c7c91..f5ef5c52a286 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -24,9 +24,11 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
const RISCVSubtarget *Subtarget = nullptr;
public:
+ static char ID;
+
explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine,
CodeGenOpt::Level OptLevel)
- : SelectionDAGISel(TargetMachine, OptLevel) {}
+ : SelectionDAGISel(ID, TargetMachine, OptLevel) {}
StringRef getPassName() const override {
return "RISCV DAG->DAG Pattern Instruction Selection";
diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index c5d0f1de7dfd..af481e70bfd8 100644
--- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -33,7 +33,9 @@ class SparcDAGToDAGISel : public SelectionDAGISel {
/// make the right decision when generating code for
diff erent targets.
const SparcSubtarget *Subtarget = nullptr;
public:
- explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(tm) {}
+ static char ID;
+
+ explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(ID, tm) {}
bool runOnMachineFunction(MachineFunction &MF) override {
Subtarget = &MF.getSubtarget<SparcSubtarget>();
@@ -65,6 +67,8 @@ class SparcDAGToDAGISel : public SelectionDAGISel {
};
} // end anonymous namespace
+char SparcDAGToDAGISel::ID = 0;
+
SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
return CurDAG->getRegister(GlobalBaseReg,
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index d976cd7b3d1b..92d549f83673 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -345,8 +345,10 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
SDValue expandSelectBoolean(SDNode *Node);
public:
+ static char ID;
+
SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
- : SelectionDAGISel(TM, OptLevel) {}
+ : SelectionDAGISel(ID, TM, OptLevel) {}
bool runOnMachineFunction(MachineFunction &MF) override {
const Function &F = MF.getFunction();
@@ -378,6 +380,8 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
};
} // end anonymous namespace
+char SystemZDAGToDAGISel::ID = 0;
+
FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
CodeGenOpt::Level OptLevel) {
return new SystemZDAGToDAGISel(TM, OptLevel);
diff --git a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
index 0301b46b2b51..c7f4fcf1cd22 100644
--- a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
@@ -31,7 +31,9 @@ class VEDAGToDAGISel : public SelectionDAGISel {
const VESubtarget *Subtarget;
public:
- explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(tm) {}
+ static char ID;
+
+ explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(ID, tm) {}
bool runOnMachineFunction(MachineFunction &MF) override {
Subtarget = &MF.getSubtarget<VESubtarget>();
@@ -69,6 +71,8 @@ class VEDAGToDAGISel : public SelectionDAGISel {
};
} // end anonymous namespace
+char VEDAGToDAGISel::ID = 0;
+
bool VEDAGToDAGISel::selectADDRrri(SDValue Addr, SDValue &Base, SDValue &Index,
SDValue &Offset) {
if (Addr.getOpcode() == ISD::FrameIndex)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
index ff3078ce83bc..15c6629efa4d 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
@@ -41,9 +41,11 @@ class WebAssemblyDAGToDAGISel final : public SelectionDAGISel {
const WebAssemblySubtarget *Subtarget;
public:
+ static char ID;
+
WebAssemblyDAGToDAGISel(WebAssemblyTargetMachine &TM,
CodeGenOpt::Level OptLevel)
- : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {}
+ : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {}
StringRef getPassName() const override {
return "WebAssembly Instruction Selection";
@@ -82,6 +84,8 @@ class WebAssemblyDAGToDAGISel final : public SelectionDAGISel {
};
} // end anonymous namespace
+char WebAssemblyDAGToDAGISel::ID;
+
void WebAssemblyDAGToDAGISel::PreprocessISelDAG() {
// Stack objects that should be allocated to locals are hoisted to WebAssembly
// locals when they are first used. However for those without uses, we hoist
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 548dd06559c5..84200ddee946 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -168,8 +168,10 @@ namespace {
bool IndirectTlsSegRefs;
public:
+ static char ID;
+
explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
- : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr),
+ : SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr),
OptForMinSize(false), IndirectTlsSegRefs(false) {}
StringRef getPassName() const override {
@@ -574,6 +576,7 @@ namespace {
};
}
+char X86DAGToDAGISel::ID = 0;
// Returns true if this masked compare can be implemented legally with this
// type.
diff --git a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
index b300697cc5ae..93691141155c 100644
--- a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
@@ -38,8 +38,10 @@ namespace {
class XCoreDAGToDAGISel : public SelectionDAGISel {
public:
+ static char ID;
+
XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel)
- : SelectionDAGISel(TM, OptLevel) {}
+ : SelectionDAGISel(ID, TM, OptLevel) {}
void Select(SDNode *N) override;
bool tryBRIND(SDNode *N);
@@ -76,6 +78,8 @@ namespace {
};
} // end anonymous namespace
+char XCoreDAGToDAGISel::ID = 0;
+
/// createXCoreISelDag - This pass converts a legalized DAG into a
/// XCore-specific DAG, ready for instruction scheduling.
///
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