[PATCH] D139394: [RISCV] Add support for RISCV XVentanaCondOps Extension Patterns

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/select.ll:287
+;
+; CONDOPS-LABEL: select_add_1:
+; CONDOPS:       # %bb.0: # %entry
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craig.topper wrote:
> reames wrote:
> > We should be able to do better here since 0 is the identity constant for the add.
> > 
> > We should be able to lower this as (add (select cond, a, 0), b).  There should only need a single vt.maskc here.
> InstCombine already does that transform before we get to SelectionDAG so it might not be an issue in practice.
Note there are two operations built into the addw. An add and a sign extension.

Doing a peephole on this in isel would require knowing that the promoted version of %b has 33 sign bits so that `addw %b, 0` was equivalent to %b. It doesn't have 33 sign bits because it doesn't have the `signext` attribute.

It would also be valid if we knew the upper bits of the result didn't matter. But we have lost that information by the time we reach isel.

Alternatively, we could rewrite it before type legalization if we thought it was important.


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Comment at: llvm/test/CodeGen/RISCV/select.ll:423
 entry:
   %c = sub i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
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reames wrote:
> Same here with the identity constant observation.
Same issue as the addw above


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  https://reviews.llvm.org/D139394/new/

https://reviews.llvm.org/D139394