[PATCH] D139394: [RISCV] Add support for RISCV XVentanaCondOps Extension Patterns

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

It's not really clear to me that the lowering here is what we want in general.  This is certainly more general than the branchless lowerings previously implemented, but at least in several cases, it looks like the branchless lowerings would be better.  I've also tagged a bunch of non-optimal lowering cases which the current branchless lowerings don't catch.



================
Comment at: llvm/test/CodeGen/RISCV/select.ll:25
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a1, a1, 1
+; CONDOPS-NEXT:    seqz a1, a1
----------------
Using condops in this case appears to be a regression.


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Comment at: llvm/test/CodeGen/RISCV/select.ll:287
+;
+; CONDOPS-LABEL: select_add_1:
+; CONDOPS:       # %bb.0: # %entry
----------------
We should be able to do better here since 0 is the identity constant for the add.

We should be able to lower this as (add (select cond, a, 0), b).  There should only need a single vt.maskc here.


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Comment at: llvm/test/CodeGen/RISCV/select.ll:423
 entry:
   %c = sub i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
----------------
Same here with the identity constant observation.


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Comment at: llvm/test/CodeGen/RISCV/select.ll:549
 entry:
   %c = and i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
----------------
We should be able to:
li t1, 43
vt.maskc t1, t1, t0 // 0 or 43
sub t1, t1, 1 // -1 or 42
and a0, a1, t1 // result


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Comment at: llvm/test/CodeGen/RISCV/select.ll:796
 entry:
   %c = ashr i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
----------------
ashr a, (select cond, %b, 0) would likely be a better expansion.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139394/new/

https://reviews.llvm.org/D139394