[llvm] a33b40d - [NFC][DebugInfo] Autogenerate check lines in assignment-tracking/sroa/*
Robinson, Paul via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 15 10:08:20 PST 2022
Look at the change to the first file, after-inlining.ll.
This patch deleted four CHECK-DAG lines verifying debug-info
metadata, and replaced them with irrelevant checks of instructions.
The automated update can also scramble things in the test making
it much less readable. Look at store.ll, which deleted CHECKs
interleaved with explanatory comments. "This is the one we care
about most" is no longer associated with the check that we actually
do care about most. This makes the test harder to understand,
clearly.
I don't doubt that _some_ of these updates are fine, but this is
not a kneejerk don't-do-that. Some of these tests are materially
worse off than before the patch.
Thanks,
--paulr
> -----Original Message-----
> From: Roman Lebedev <lebedev.ri at gmail.com>
> Sent: Thursday, December 15, 2022 12:54 PM
> To: Robinson, Paul <paul.robinson at sony.com>
> Cc: Roman Lebedev <llvmlistbot at llvm.org>; llvm-commits at lists.llvm.org;
> David Blaikie <dblaikie at gmail.com>; Adrian Prantl <aprantl at apple.com>
> Subject: Re: [llvm] a33b40d - [NFC][DebugInfo] Autogenerate check lines in
> assignment-tracking/sroa/*
> Importance: High
>
> Hi.
> What coverage specifically is being lost here?
>
> Roman
>
> On Thu, Dec 15, 2022 at 8:48 PM Robinson, Paul <paul.robinson at sony.com>
> wrote:
> >
> > Hi Roman,
> >
> > Please revert this. The scripts are incapable of adding the correct
> > checks for debug-info metadata. They are intended for adding checks
> > of IR instructions only. This patch loses coverage.
> >
> > Thanks,
> > --paulr
> >
> > > -----Original Message-----
> > > From: llvm-commits <llvm-commits-bounces at lists.llvm.org> On Behalf Of
> > > Roman Lebedev via llvm-commits
> > > Sent: Thursday, December 15, 2022 10:46 AM
> > > To: llvm-commits at lists.llvm.org
> > > Subject: [llvm] a33b40d - [NFC][DebugInfo] Autogenerate check lines in
> > > assignment-tracking/sroa/*
> > >
> > >
> > > Author: Roman Lebedev
> > > Date: 2022-12-15T18:45:02+03:00
> > > New Revision: a33b40d61c64b95d736f1a0dd537e9087c330304
> > >
> > > URL: https://urldefense.com/v3/__https://github.com/llvm/llvm-
> > >
> project/commit/a33b40d61c64b95d736f1a0dd537e9087c330304__;!!JmoZiZGBv3RvKR
> > > Sx!9KPZBMFLJky0OiOtaS7FN9zDnCuBHEkeYp5Z4NUvm-
> > > yWl3S48O_wFxaBVYc5nPzSFYpD1yOBeP5OfbJRsbxat5YCSqvV$
> > > DIFF: https://urldefense.com/v3/__https://github.com/llvm/llvm-
> > >
> project/commit/a33b40d61c64b95d736f1a0dd537e9087c330304.diff__;!!JmoZiZGBv
> > > 3RvKRSx!9KPZBMFLJky0OiOtaS7FN9zDnCuBHEkeYp5Z4NUvm-
> > > yWl3S48O_wFxaBVYc5nPzSFYpD1yOBeP5OfbJRsbxat2dxuJmz$
> > >
> > > LOG: [NFC][DebugInfo] Autogenerate check lines in assignment-
> > > tracking/sroa/*
> > >
> > > Manual checklines are generally not welcomed in LLVM tests.
> > > They are really brittle, and really hard to update.
> > > *Please* use scripts!
> > >
> > > Added:
> > >
> > >
> > > Modified:
> > > llvm/test/DebugInfo/Generic/assignment-tracking/sroa/after-
> inlining.ll
> > > llvm/test/DebugInfo/Generic/assignment-tracking/sroa/alloca-
> single-
> > > slice.ll
> > > llvm/test/DebugInfo/Generic/assignment-tracking/sroa/complex.ll
> > > llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag-2.ll
> > > llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag.ll
> > > llvm/test/DebugInfo/Generic/assignment-tracking/sroa/id.ll
> > > llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memcpy.ll
> > > llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memmove-to-
> from-
> > > same-alloca.ll
> > > llvm/test/DebugInfo/Generic/assignment-tracking/sroa/rewrite.ll
> > > llvm/test/DebugInfo/Generic/assignment-tracking/sroa/store.ll
> > > llvm/test/DebugInfo/Generic/assignment-tracking/sroa/unspecified-
> var-
> > > size.ll
> > > llvm/test/DebugInfo/Generic/assignment-tracking/sroa/user-
> memcpy.ll
> > > llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-1.ll
> > > llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-2.ll
> > >
> > > Removed:
> > >
> > >
> > >
> > >
> ##########################################################################
> > > ######
> > > diff --git a/llvm/test/DebugInfo/Generic/assignment-
> tracking/sroa/after-
> > > inlining.ll b/llvm/test/DebugInfo/Generic/assignment-
> tracking/sroa/after-
> > > inlining.ll
> > > index 96fed34d8a68c..651f45f8af0c9 100644
> > > --- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/after-
> > > inlining.ll
> > > +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/after-
> > > inlining.ll
> > > @@ -1,3 +1,4 @@
> > > +; NOTE: Assertions have been autogenerated by
> utils/update_test_checks.py
> > > ; RUN: opt %s -S -passes=sroa -o - -experimental-assignment-tracking
> |
> > > FileCheck %s
> > >
> > > ;; Check that SROA preserves the InlinedAt status of new dbg.assign
> > > intriniscs
> > > @@ -28,12 +29,7 @@
> > > ;;
> > > ;; $ clang test.c -Xclang -fexperimental-assignment-tracking -O2 -g
> > >
> > > -; CHECK: call void @llvm.dbg.assign(metadata i1 undef, metadata
> !{{.+}},
> > > metadata !DIExpression(), metadata !{{.+}}, metadata ptr undef,
> metadata
> > > !DIExpression()), !dbg ![[DBG:[0-9]+]]
> > >
> > > -; CHECK-DAG: ![[DBG]] = !DILocation(line: 0, scope: ![[INL_SC:[0-
> 9]+]],
> > > inlinedAt: ![[IA:[0-9]+]])
> > > -; CHECK-DAG: ![[IA]] = distinct !DILocation(line: 21, column: 12,
> scope:
> > > ![[SC:[0-9]+]])
> > > -; CHECK-DAG: ![[SC]] = distinct !DISubprogram(name: "l",
> > > -; CHECK-DAG: ![[INL_SC]] = distinct !DISubprogram(name: "k"
> > >
> > > %struct.c = type { i32, [0 x i32] }
> > >
> > > @@ -45,6 +41,13 @@ declare void @llvm.lifetime.start.p0i8(i64 immarg,
> ptr
> > > nocapture) #2
> > > declare void @llvm.lifetime.end.p0i8(i64 immarg, ptr nocapture) #2
> > >
> > > define dso_local void @l() local_unnamed_addr #4 !dbg !73 {
> > > +; CHECK-LABEL: @l(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META18:![0-9]+]], metadata !DIExpression(), metadata [[META29:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG30:![0-9]+]]
> > > +; CHECK-NEXT: store i32 1, ptr @f, align 4, !dbg [[DBG32:![0-9]+]]
> > > +; CHECK-NEXT: store i32 poison, ptr @e, align 4, !dbg [[DBG42:![0-
> > > 9]+]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG43:![0-9]+]]
> > > +;
> > > entry:
> > > %j.i = alloca %struct.c, align 4, !DIAssignID !74
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !64,
> metadata
> > > !DIExpression(), metadata !74, metadata ptr %j.i, metadata
> > > !DIExpression()) #5, !dbg !75
> > >
> > > diff --git a/llvm/test/DebugInfo/Generic/assignment-
> tracking/sroa/alloca-
> > > single-slice.ll b/llvm/test/DebugInfo/Generic/assignment-
> > > tracking/sroa/alloca-single-slice.ll
> > > index c550489ab4f3e..9d89512a2c57a 100644
> > > --- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/alloca-
> single-
> > > slice.ll
> > > +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/alloca-
> single-
> > > slice.ll
> > > @@ -1,3 +1,4 @@
> > > +; NOTE: Assertions have been autogenerated by
> utils/update_test_checks.py
> > > ; RUN: opt -passes=sroa,verify -S %s -o - -experimental-assignment-
> > > tracking \
> > > ; RUN: | FileCheck %s --implicit-check-not="call void @llvm.dbg"
> > >
> > > @@ -15,9 +16,6 @@
> > > ;; $ clang test.c -Xclang -disable-llvm-passes -O2 -g -c -S -emit-
> llvm -o
> > > - \
> > > ;; | opt -passes=declare-to-assign -S -o -
> > >
> > > -; CHECK: entry:
> > > -; CHECK-NEXT: %a.sroa.0 = alloca i64, align 8, !DIAssignID
> ![[ID_1:[0-
> > > 9]+]]
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef, metadata
> > > ![[VAR:[0-9]+]], metadata !DIExpression(), metadata ![[ID_1]],
> metadata
> > > ptr %a.sroa.0, metadata !DIExpression()), !dbg
> > >
> > > target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-
> > > f80:128-n8:16:32:64-S128"
> > >
> > > @@ -26,6 +24,17 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-
> > > p272:64:64-i64:64-f80:128-n8:16
> > > @c = dso_local global i32 0, align 4, !dbg !0
> > >
> > > define dso_local void @d() !dbg !11 {
> > > +; CHECK-LABEL: @d(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca i64, align 8, !DIAssignID
> !23
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META15:![0-9]+]], metadata !DIExpression(), metadata [[META23:![0-
> 9]+]],
> > > metadata ptr [[A_SROA_0]], metadata !DIExpression()), !dbg
> [[DBG24:![0-
> > > 9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr
> > > [[A_SROA_0]]), !dbg [[DBG25:![0-9]+]]
> > > +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @c, align 4, !dbg
> > > [[DBG26:![0-9]+]]
> > > +; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64, !dbg
> [[DBG26]]
> > > +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8
> > > [[A_SROA_0]], ptr align 1 null, i64 [[CONV]], i1 false), !dbg
> [[DBG27:![0-
> > > 9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr
> > > [[A_SROA_0]]), !dbg [[DBG28:![0-9]+]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG28]]
> > > +;
> > > entry:
> > > %a = alloca %struct.a, align 1, !DIAssignID !23
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !15,
> metadata
> > > !DIExpression(), metadata !23, metadata ptr %a, metadata
> !DIExpression()),
> > > !dbg !24
> > >
> > > diff --git a/llvm/test/DebugInfo/Generic/assignment-
> > > tracking/sroa/complex.ll b/llvm/test/DebugInfo/Generic/assignment-
> > > tracking/sroa/complex.ll
> > > index 106aa4f5e6a77..7e9b1e3bad073 100644
> > > --- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/complex.ll
> > > +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/complex.ll
> > > @@ -1,3 +1,4 @@
> > > +; NOTE: Assertions have been autogenerated by
> utils/update_test_checks.py
> > > ; RUN: opt -passes=sroa -S -o - %s -experimental-assignment-tracking
> |
> > > FileCheck %s
> > > ;
> > > ;; Based on llvm/test/DebugInfo/ARM/sroa-complex.ll
> > > @@ -14,15 +15,20 @@
> > > ;; untouched.
> > >
> > > ;; dbg.assigns for the split (then promoted) stores.
> > > -; CHECK: %c.coerce.fca.0.extract = extractvalue [2 x i64] %c.coerce,
> 0
> > > -; CHECK: %c.coerce.fca.1.extract = extractvalue [2 x i64] %c.coerce,
> 1
> > > -; CHECK: call void @llvm.dbg.assign(metadata i64
> > > %c.coerce.fca.0.extract,{{.+}}, metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 0, 64),{{.+}}, metadata ptr undef,
> > > metadata !DIExpression())
> > > -; CHECK: call void @llvm.dbg.assign(metadata i64
> > > %c.coerce.fca.1.extract,{{.+}}, metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 64, 64),{{.+}}, metadata ptr undef,
> > > {{.+}})
> > >
> > > target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-
> S64"
> > > target triple = "armv7-apple-unknown"
> > >
> > > define dso_local arm_aapcscc void @f([2 x i64] %c.coerce) #0 !dbg !8
> {
> > > +; CHECK-LABEL: @f(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: [[C_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x
> i64]
> > > [[C_COERCE:%.*]], 0
> > > +; CHECK-NEXT: [[C_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x
> i64]
> > > [[C_COERCE]], 1
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64
> > > [[C_COERCE_FCA_0_EXTRACT]], metadata [[META13:![0-9]+]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata [[META14:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG15:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64
> > > [[C_COERCE_FCA_1_EXTRACT]], metadata [[META13]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata [[META16:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG15]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata [2 x i64]
> > > [[C_COERCE]], metadata [[META13]], metadata !DIExpression(), metadata
> > > [[META17:![0-9]+]], metadata ptr undef, metadata !DIExpression()),
> !dbg
> > > [[DBG15]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG18:![0-9]+]]
> > > +;
> > > entry:
> > > %c = alloca { double, double }, align 8, !DIAssignID !14
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !13,
> metadata
> > > !DIExpression(), metadata !14, metadata ptr %c, metadata
> !DIExpression()),
> > > !dbg !15
> > >
> > > diff --git a/llvm/test/DebugInfo/Generic/assignment-
> tracking/sroa/frag-
> > > 2.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag-2.ll
> > > index aa9321e1de7cb..dc153f98c4907 100644
> > > --- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag-2.ll
> > > +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag-2.ll
> > > @@ -1,3 +1,4 @@
> > > +; NOTE: Assertions have been autogenerated by
> utils/update_test_checks.py
> > > ; RUN: opt -passes=sroa -S %s -o - -experimental-assignment-tracking
> |
> > > FileCheck %s
> > >
> > > ;; $ cat test.cpp
> > > @@ -34,15 +35,8 @@
> > > ;; fragment info; that the address-expression remains untouched.
> > >
> > > ;; Check nearby instructions to make sure we're looking in the right
> > > place.
> > > -; CHECK: define dso_local void @_Z1jv()
> > > -; CHECK: call void @_ZN1h1iEv(ptr nonnull sret(%class.B) align 4 %m,
> > >
> > > -; CHECK: store <2 x float> %agg.tmp.sroa.0.0.copyload.i, ptr %4,
> align
> > > 4,{{.+}}!DIAssignID ![[id1:[0-9]+]]
> > > -; CHECK: store <2 x float> %agg.tmp.sroa.2.0.copyload.i, ptr
> > > %n.sroa.4.4..sroa_idx, align 4,{{.+}}!DIAssignID ![[id2:[0-9]+]]
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> > > %agg.tmp.sroa.0.0.copyload.i, metadata ![[var:[0-9]+]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata ![[id1]], metadata
> ptr
> > > %4, metadata !DIExpression()), !dbg
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> > > %agg.tmp.sroa.2.0.copyload.i, metadata ![[var]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata ![[id2]],
> metadata
> > > ptr %n.sroa.4.4..sroa_idx, metadata !DIExpression()), !dbg
> > >
> > > -; CHECK: ret
> > >
> > > %class.B = type { i32, %class.a }
> > > %class.a = type { [4 x float] }
> > > @@ -54,6 +48,22 @@ $_ZN1B1fEv = comdat any
> > >
> > > ; Function Attrs: nofree norecurse nounwind uwtable
> > > define dso_local void @_ZNK1BmlERKS_(ptr noalias nocapture
> sret(%class.B)
> > > align 4 %agg.result, ptr nocapture readonly %this, ptr nocapture
> nonnull
> > > readnone align 4 dereferenceable(20) %0) local_unnamed_addr #0 align 2
> > > !dbg !7 {
> > > +; CHECK-LABEL: @_ZNK1BmlERKS_(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: [[AGG_TMP_SROA_0_0__SROA_IDX:%.*]] = getelementptr
> > > inbounds [[CLASS_B:%.*]], ptr [[THIS:%.*]], i64 0, i32 1, !dbg
> > > [[DBG42:![0-9]+]]
> > > +; CHECK-NEXT: [[AGG_TMP_SROA_0_0__SROA_CAST:%.*]] = bitcast ptr
> > > [[AGG_TMP_SROA_0_0__SROA_IDX]] to ptr, !dbg [[DBG42]]
> > > +; CHECK-NEXT: [[AGG_TMP_SROA_0_0_COPYLOAD:%.*]] = load <2 x
> float>,
> > > ptr [[AGG_TMP_SROA_0_0__SROA_CAST]], align 4, !dbg [[DBG42]]
> > > +; CHECK-NEXT: [[AGG_TMP_SROA_2_0__SROA_IDX2:%.*]] = getelementptr
> > > inbounds [[CLASS_B]], ptr [[THIS]], i64 0, i32 1, i32 0, i64 2, !dbg
> > > [[DBG42]]
> > > +; CHECK-NEXT: [[AGG_TMP_SROA_2_0__SROA_CAST:%.*]] = bitcast ptr
> > > [[AGG_TMP_SROA_2_0__SROA_IDX2]] to ptr, !dbg [[DBG42]]
> > > +; CHECK-NEXT: [[AGG_TMP_SROA_2_0_COPYLOAD:%.*]] = load <2 x
> float>,
> > > ptr [[AGG_TMP_SROA_2_0__SROA_CAST]], align 4, !dbg [[DBG42]]
> > > +; CHECK-NEXT: [[D_SROA_0_0__SROA_IDX_I:%.*]] = getelementptr
> inbounds
> > > [[CLASS_B]], ptr [[AGG_RESULT:%.*]], i64 0, i32 1, !dbg [[DBG43:![0-
> 9]+]]
> > > +; CHECK-NEXT: [[D_SROA_0_0__SROA_CAST_I:%.*]] = bitcast ptr
> > > [[D_SROA_0_0__SROA_IDX_I]] to ptr, !dbg [[DBG43]]
> > > +; CHECK-NEXT: store <2 x float> [[AGG_TMP_SROA_0_0_COPYLOAD]], ptr
> > > [[D_SROA_0_0__SROA_CAST_I]], align 4, !dbg [[DBG43]]
> > > +; CHECK-NEXT: [[D_SROA_2_0__SROA_IDX2_I:%.*]] = getelementptr
> inbounds
> > > [[CLASS_B]], ptr [[AGG_RESULT]], i64 0, i32 1, i32 0, i64 2, !dbg
> > > [[DBG43]]
> > > +; CHECK-NEXT: [[D_SROA_2_0__SROA_CAST_I:%.*]] = bitcast ptr
> > > [[D_SROA_2_0__SROA_IDX2_I]] to ptr, !dbg [[DBG43]]
> > > +; CHECK-NEXT: store <2 x float> [[AGG_TMP_SROA_2_0_COPYLOAD]], ptr
> > > [[D_SROA_2_0__SROA_CAST_I]], align 4, !dbg [[DBG43]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG50:![0-9]+]]
> > > +;
> > > entry:
> > > %agg.tmp.sroa.0.0..sroa_idx = getelementptr inbounds %class.B, ptr
> > > %this, i64 0, i32 1, !dbg !42
> > > %agg.tmp.sroa.0.0..sroa_cast = bitcast ptr
> %agg.tmp.sroa.0.0..sroa_idx
> > > to ptr, !dbg !42
> > > @@ -75,6 +85,16 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(ptr noalias
> > > nocapture writeonly, ptr noa
> > >
> > > ; Function Attrs: nounwind uwtable
> > > define linkonce_odr dso_local void @_ZN1BC2E1a(ptr %this, <2 x float>
> > > %d.coerce0, <2 x float> %d.coerce1) unnamed_addr #2 comdat align 2
> !dbg
> > > !48 {
> > > +; CHECK-LABEL: @_ZN1BC2E1a(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: [[D_SROA_0_0__SROA_IDX:%.*]] = getelementptr
> inbounds
> > > [[CLASS_B:%.*]], ptr [[THIS:%.*]], i64 0, i32 1, !dbg [[DBG51:![0-
> 9]+]]
> > > +; CHECK-NEXT: [[D_SROA_0_0__SROA_CAST:%.*]] = bitcast ptr
> > > [[D_SROA_0_0__SROA_IDX]] to ptr, !dbg [[DBG51]]
> > > +; CHECK-NEXT: store <2 x float> [[D_COERCE0:%.*]], ptr
> > > [[D_SROA_0_0__SROA_CAST]], align 4, !dbg [[DBG51]]
> > > +; CHECK-NEXT: [[D_SROA_2_0__SROA_IDX2:%.*]] = getelementptr
> inbounds
> > > [[CLASS_B]], ptr [[THIS]], i64 0, i32 1, i32 0, i64 2, !dbg [[DBG51]]
> > > +; CHECK-NEXT: [[D_SROA_2_0__SROA_CAST:%.*]] = bitcast ptr
> > > [[D_SROA_2_0__SROA_IDX2]] to ptr, !dbg [[DBG51]]
> > > +; CHECK-NEXT: store <2 x float> [[D_COERCE1:%.*]], ptr
> > > [[D_SROA_2_0__SROA_CAST]], align 4, !dbg [[DBG51]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG52:![0-9]+]]
> > > +;
> > > entry:
> > > %d.sroa.0.0..sroa_idx = getelementptr inbounds %class.B, ptr %this,
> i64
> > > 0, i32 1, !dbg !55
> > > %d.sroa.0.0..sroa_cast = bitcast ptr %d.sroa.0.0..sroa_idx to ptr,
> !dbg
> > > !55
> > > @@ -90,6 +110,52 @@ declare void @llvm.dbg.assign(metadata, metadata,
> > > metadata, metadata, metadata,
> > >
> > > ; Function Attrs: uwtable
> > > define dso_local void @_Z1jv() local_unnamed_addr #4 !dbg !57 {
> > > +; CHECK-LABEL: @_Z1jv(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: [[CONVEXBODY:%.*]] = alloca [[CLASS_H:%.*]], align
> 1,
> > > !DIAssignID !69
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META57:![0-9]+]], metadata !DIExpression(), metadata [[META69:![0-
> 9]+]],
> > > metadata ptr [[CONVEXBODY]], metadata !DIExpression()), !dbg
> [[DBG70:![0-
> > > 9]+]]
> > > +; CHECK-NEXT: [[K:%.*]] = alloca [[CLASS_H]], align 1, !DIAssignID
> !71
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META64:![0-9]+]], metadata !DIExpression(), metadata [[META71:![0-
> 9]+]],
> > > metadata ptr [[K]], metadata !DIExpression()), !dbg [[DBG70]]
> > > +; CHECK-NEXT: [[L:%.*]] = alloca [[CLASS_B:%.*]], align 4,
> !DIAssignID
> > > !72
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META65:![0-9]+]], metadata !DIExpression(), metadata [[META72:![0-
> 9]+]],
> > > metadata ptr [[L]], metadata !DIExpression()), !dbg [[DBG70]]
> > > +; CHECK-NEXT: [[M:%.*]] = alloca [[CLASS_B]], align 4, !DIAssignID
> !73
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META66:![0-9]+]], metadata !DIExpression(), metadata [[META73:![0-
> 9]+]],
> > > metadata ptr [[M]], metadata !DIExpression()), !dbg [[DBG70]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META67:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0,
> 32),
> > > metadata [[META74:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG70]]
> > > +; CHECK-NEXT: [[O:%.*]] = alloca [[CLASS_A:%.*]], align 4,
> !DIAssignID
> > > !75
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META68:![0-9]+]], metadata !DIExpression(), metadata [[META75:![0-
> 9]+]],
> > > metadata ptr [[O]], metadata !DIExpression()), !dbg [[DBG70]]
> > > +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_H]],
> ptr
> > > [[CONVEXBODY]], i64 0, i32 0, !dbg [[DBG76:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr nonnull
> > > [[TMP0]]), !dbg [[DBG76]]
> > > +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_H]],
> ptr
> > > [[K]], i64 0, i32 0, !dbg [[DBG76]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr nonnull
> > > [[TMP1]]), !dbg [[DBG76]]
> > > +; CHECK-NEXT: [[TMP2:%.*]] = bitcast ptr [[L]] to ptr, !dbg
> > > [[DBG77:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 20, ptr
> nonnull
> > > [[TMP2]]), !dbg [[DBG77]]
> > > +; CHECK-NEXT: call void @_ZN1h1iEv(ptr nonnull sret([[CLASS_B]])
> align
> > > 4 [[L]], ptr nonnull [[K]]), !dbg [[DBG78:![0-9]+]]
> > > +; CHECK-NEXT: [[TMP3:%.*]] = bitcast ptr [[M]] to ptr, !dbg
> [[DBG77]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 20, ptr
> nonnull
> > > [[TMP3]]), !dbg [[DBG77]]
> > > +; CHECK-NEXT: call void @_ZN1h1iEv(ptr nonnull sret([[CLASS_B]])
> align
> > > 4 [[M]], ptr nonnull [[CONVEXBODY]]), !dbg [[DBG79:![0-9]+]]
> > > +; CHECK-NEXT: [[AGG_TMP_SROA_0_0__SROA_IDX_I:%.*]] = getelementptr
> > > inbounds [[CLASS_B]], ptr [[L]], i64 0, i32 1, !dbg [[DBG80:![0-9]+]]
> > > +; CHECK-NEXT: [[AGG_TMP_SROA_0_0__SROA_CAST_I:%.*]] = bitcast ptr
> > > [[AGG_TMP_SROA_0_0__SROA_IDX_I]] to ptr, !dbg [[DBG80]]
> > > +; CHECK-NEXT: [[AGG_TMP_SROA_0_0_COPYLOAD_I:%.*]] = load <2 x
> float>,
> > > ptr [[AGG_TMP_SROA_0_0__SROA_CAST_I]], align 4, !dbg [[DBG80]]
> > > +; CHECK-NEXT: [[AGG_TMP_SROA_2_0__SROA_IDX2_I:%.*]] =
> getelementptr
> > > inbounds [[CLASS_B]], ptr [[L]], i64 0, i32 1, i32 0, i64 2, !dbg
> > > [[DBG80]]
> > > +; CHECK-NEXT: [[AGG_TMP_SROA_2_0__SROA_CAST_I:%.*]] = bitcast ptr
> > > [[AGG_TMP_SROA_2_0__SROA_IDX2_I]] to ptr, !dbg [[DBG80]]
> > > +; CHECK-NEXT: [[AGG_TMP_SROA_2_0_COPYLOAD_I:%.*]] = load <2 x
> float>,
> > > ptr [[AGG_TMP_SROA_2_0__SROA_CAST_I]], align 4, !dbg [[DBG80]]
> > > +; CHECK-NEXT: call void @llvm.dbg.value(metadata <2 x float>
> > > [[AGG_TMP_SROA_0_0_COPYLOAD_I]], metadata [[META67]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 32, 64)), !dbg [[DBG70]]
> > > +; CHECK-NEXT: call void @llvm.dbg.value(metadata <2 x float>
> > > [[AGG_TMP_SROA_2_0_COPYLOAD_I]], metadata [[META67]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 96, 64)), !dbg [[DBG70]]
> > > +; CHECK-NEXT: [[TMP4:%.*]] = bitcast ptr [[O]] to ptr, !dbg
> > > [[DBG82:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr
> nonnull
> > > [[TMP4]]), !dbg [[DBG82]]
> > > +; CHECK-NEXT: store <2 x float> [[AGG_TMP_SROA_0_0_COPYLOAD_I]],
> ptr
> > > [[TMP4]], align 4, !dbg [[DBG83:![0-9]+]], !DIAssignID !84
> > > +; CHECK-NEXT: [[N_SROA_4_4__SROA_IDX:%.*]] = getelementptr
> inbounds
> > > i8, ptr [[TMP4]], i64 8, !dbg [[DBG83]]
> > > +; CHECK-NEXT: store <2 x float> [[AGG_TMP_SROA_2_0_COPYLOAD_I]],
> ptr
> > > [[N_SROA_4_4__SROA_IDX]], align 4, !dbg [[DBG83]], !DIAssignID !85
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> > > [[AGG_TMP_SROA_0_0_COPYLOAD_I]], metadata [[META68]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata [[META84:![0-
> 9]+]],
> > > metadata ptr [[TMP4]], metadata !DIExpression()), !dbg [[DBG70]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> > > [[AGG_TMP_SROA_2_0_COPYLOAD_I]], metadata [[META68]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata [[META85:![0-
> 9]+]],
> > > metadata ptr [[N_SROA_4_4__SROA_IDX]], metadata !DIExpression()), !dbg
> > > [[DBG70]]
> > > +; CHECK-NEXT: call void @_ZN1a1cEv(ptr nonnull [[O]]), !dbg
> > > [[DBG86:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull
> > > [[TMP4]]), !dbg [[DBG87:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 20, ptr nonnull
> > > [[TMP3]]), !dbg [[DBG87]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 20, ptr nonnull
> > > [[TMP2]]), !dbg [[DBG87]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr nonnull
> > > [[TMP1]]), !dbg [[DBG87]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr nonnull
> > > [[TMP0]]), !dbg [[DBG87]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG87]]
> > > +;
> > > entry:
> > > %convexbody = alloca %class.h, align 1, !DIAssignID !73
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !61,
> metadata
> > > !DIExpression(), metadata !73, metadata ptr %convexbody, metadata
> > > !DIExpression()), !dbg !74
> > > @@ -148,6 +214,11 @@ declare dso_local void @_ZN1h1iEv(ptr
> sret(%class.B)
> > > align 4, ptr) local_unnamed
> > >
> > > ; Function Attrs: nounwind uwtable
> > > define linkonce_odr dso_local nonnull align 4 dereferenceable(16) ptr
> > > @_ZN1B1fEv(ptr %this) local_unnamed_addr #6 comdat align 2 !dbg !93 {
> > > +; CHECK-LABEL: @_ZN1B1fEv(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: [[E:%.*]] = getelementptr inbounds [[CLASS_B:%.*]],
> ptr
> > > [[THIS:%.*]], i64 0, i32 1, !dbg [[DBG91:![0-9]+]]
> > > +; CHECK-NEXT: ret ptr [[E]], !dbg [[DBG92:![0-9]+]]
> > > +;
> > > entry:
> > > %e = getelementptr inbounds %class.B, ptr %this, i64 0, i32 1, !dbg
> > > !101
> > > ret ptr %e, !dbg !102
> > >
> > > diff --git a/llvm/test/DebugInfo/Generic/assignment-
> tracking/sroa/frag.ll
> > > b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag.ll
> > > index 18010c6a283e6..add2e1443e8d4 100644
> > > --- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag.ll
> > > +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag.ll
> > > @@ -1,3 +1,4 @@
> > > +; NOTE: Assertions have been autogenerated by
> utils/update_test_checks.py
> > > ; RUN: opt %s -S -passes=sroa -o - -experimental-assignment-tracking
> |
> > > FileCheck %s
> > >
> > > ;; $ cat test.cpp
> > > @@ -18,16 +19,21 @@
> > > ;; fragment(320, 64). Ensure that only the value-expression gets
> fragment
> > > info;
> > > ;; that the address-expression remains untouched.
> > >
> > > -; CHECK: %call = call
> > > -; CHECK-NEXT: %0 = extractvalue { <2 x float>, <2 x float> } %call, 0
> > > -; CHECK-NEXT: %1 = extractvalue { <2 x float>, <2 x float> } %call, 1
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float> %0,
> > > metadata ![[var:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment,
> 256,
> > > 64),{{.+}},{{.+}}undef, metadata !DIExpression()), !dbg
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float> %1,
> > > metadata ![[var]], metadata !DIExpression(DW_OP_LLVM_fragment, 320,
> > > 64),{{.+}},{{.+}}undef, metadata !DIExpression()), !dbg
> > >
> > > %class.c = type { [4 x float] }
> > >
> > > ; Function Attrs: uwtable
> > > define dso_local void @_Z1dv() #0 !dbg !7 {
> > > +; CHECK-LABEL: @_Z1dv(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0,
> 256),
> > > metadata [[META22:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG23:![0-9]+]]
> > > +; CHECK-NEXT: [[CALL:%.*]] = call { <2 x float>, <2 x float> }
> > > @_Z3fn1v(), !dbg [[DBG24:![0-9]+]]
> > > +; CHECK-NEXT: [[TMP0:%.*]] = extractvalue { <2 x float>, <2 x
> float> }
> > > [[CALL]], 0, !dbg [[DBG24]]
> > > +; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <2 x float>, <2 x
> float> }
> > > [[CALL]], 1, !dbg [[DBG24]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> > > [[TMP0]], metadata [[META11]], metadata
> !DIExpression(DW_OP_LLVM_fragment,
> > > 256, 64), metadata [[META25:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG23]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> > > [[TMP1]], metadata [[META11]], metadata
> !DIExpression(DW_OP_LLVM_fragment,
> > > 320, 64), metadata [[META26:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG23]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG27:![0-9]+]]
> > > +;
> > > entry:
> > > %a = alloca [3 x %class.c], align 16, !DIAssignID !22
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !11,
> metadata
> > > !DIExpression(), metadata !22, metadata ptr %a, metadata
> !DIExpression()),
> > > !dbg !23
> > >
> > > diff --git a/llvm/test/DebugInfo/Generic/assignment-
> tracking/sroa/id.ll
> > > b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/id.ll
> > > index 0fab6f0727583..afa1b831fe8ff 100644
> > > --- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/id.ll
> > > +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/id.ll
> > > @@ -1,3 +1,4 @@
> > > +; NOTE: Assertions have been autogenerated by
> utils/update_test_checks.py
> > > ; RUN: opt -passes=sroa -S %s -o - -experimental-assignment-tracking
> |
> > > FileCheck %s
> > >
> > > ;; Check that multiple dbg.assign intrinsics linked to a store that
> is
> > > getting
> > > @@ -24,17 +25,9 @@
> > > ;; }
> > > ;;
> > > ;; Generated by grabbing IR before sroa in:
> > > -;; $ clang++ -O2 -g -c test.cpp -Xclang -fexperimental-assignment-
> > > tracking
> > > +;; $ clang++ -O2 -g -c test.cpp -Xclang -fexperimental-assignment-
> > > tracking
> > >
> > > -; CHECK: if.then:
> > > -; CHECK-NEXT: %1 = load float
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata float %storemerge,
> > > metadata ![[var:[0-9]+]], metadata !DIExpression(), metadata ![[id:[0-
> > > 9]+]], metadata ptr undef, metadata !DIExpression()), !dbg ![[dbg:[0-
> 9]+]]
> > >
> > > -; CHECK: if.else:
> > > -; CHECK-NEXT: %2 = load float
> > > -; CHECK-NEXT: %3 = load float
> > > -; CHECK-NEXT: %div = fdiv float
> > > -; CHECK: call void @llvm.dbg.assign(metadata float %storemerge,
> metadata
> > > ![[var]], metadata !DIExpression(), metadata ![[id]], metadata ptr
> undef,
> > > metadata !DIExpression()), !dbg ![[dbg]]
> > >
> > > %class.a = type { i8 }
> > >
> > > @@ -46,6 +39,32 @@ $_ZN1aC2EiRf = comdat any
> > >
> > > ; Function Attrs: nounwind readonly uwtable
> > > define dso_local void @_Z1fv() local_unnamed_addr #0 !dbg !16 {
> > > +; CHECK-LABEL: @_Z1fv(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @c, align 4, !dbg
> > > [[DBG21:![0-9]+]]
> > > +; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP0]], 0, !dbg
> > > [[DBG21]]
> > > +; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[IF_ELSE:%.*]], label
> > > [[IF_THEN:%.*]], !dbg [[DBG23:![0-9]+]]
> > > +; CHECK: if.then:
> > > +; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr @b, align 4, !dbg
> > > [[DBG24:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata float
> > > [[STOREMERGE:%.*]], metadata [[META20:![0-9]+]], metadata
> !DIExpression(),
> > > metadata [[META25:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG26:![0-9]+]]
> > > +; CHECK-NEXT: br label [[IF_END:%.*]], !dbg [[DBG27:![0-9]+]]
> > > +; CHECK: if.else:
> > > +; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr @b, align 4, !dbg
> > > [[DBG28:![0-9]+]]
> > > +; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr @d, align 4, !dbg
> > > [[DBG29:![0-9]+]]
> > > +; CHECK-NEXT: [[DIV:%.*]] = fdiv float [[TMP2]], [[TMP3]], !dbg
> > > [[DBG30:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata float
> > > [[STOREMERGE]], metadata [[META20]], metadata !DIExpression(),
> metadata
> > > [[META25]], metadata ptr undef, metadata !DIExpression()), !dbg
> [[DBG26]]
> > > +; CHECK-NEXT: br label [[IF_END]]
> > > +; CHECK: if.end:
> > > +; CHECK-NEXT: [[STOREMERGE]] = phi float [ [[DIV]], [[IF_ELSE]] ],
> [
> > > [[TMP1]], [[IF_THEN]] ], !dbg [[DBG31:![0-9]+]]
> > > +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @c, align 4, !dbg
> > > [[DBG32:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META33:![0-9]+]], metadata !DIExpression(), metadata [[META46:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG47:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META43:![0-9]+]], metadata !DIExpression(), metadata [[META49:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG47]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META44:![0-9]+]], metadata !DIExpression(), metadata [[META50:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG47]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata ptr undef,
> metadata
> > > [[META33]], metadata !DIExpression(), metadata [[META51:![0-9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG47]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32 [[TMP4]],
> > > metadata [[META43]], metadata !DIExpression(), metadata [[META52:![0-
> > > 9]+]], metadata ptr undef, metadata !DIExpression()), !dbg [[DBG47]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata ptr undef,
> metadata
> > > [[META44]], metadata !DIExpression(), metadata [[META53:![0-9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG47]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG54:![0-9]+]]
> > > +;
> > > entry:
> > > %e = alloca float, align 4, !DIAssignID !21
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !20,
> metadata
> > > !DIExpression(), metadata !21, metadata ptr %e, metadata
> !DIExpression()),
> > > !dbg !22
> > > @@ -87,6 +106,16 @@ declare void @llvm.lifetime.start.p0i8(i64 immarg,
> ptr
> > > nocapture) #1
> > >
> > > ; Function Attrs: nounwind uwtable
> > > define linkonce_odr dso_local void @_ZN1aC2EiRf(ptr %this, i32 %0,
> ptr
> > > nonnull align 4 dereferenceable(4) %1) unnamed_addr #2 comdat align 2
> !dbg
> > > !42 {
> > > +; CHECK-LABEL: @_ZN1aC2EiRf(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META33]], metadata !DIExpression(), metadata [[META55:![0-9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG56:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META43]], metadata !DIExpression(), metadata [[META57:![0-9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG56]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META44]], metadata !DIExpression(), metadata [[META58:![0-9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG56]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata ptr
> [[THIS:%.*]],
> > > metadata [[META33]], metadata !DIExpression(), metadata [[META59:![0-
> > > 9]+]], metadata ptr undef, metadata !DIExpression()), !dbg [[DBG56]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32
> [[TMP0:%.*]],
> > > metadata [[META43]], metadata !DIExpression(), metadata [[META60:![0-
> > > 9]+]], metadata ptr undef, metadata !DIExpression()), !dbg [[DBG56]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata ptr
> [[TMP1:%.*]],
> > > metadata [[META44]], metadata !DIExpression(), metadata [[META61:![0-
> > > 9]+]], metadata ptr undef, metadata !DIExpression()), !dbg [[DBG56]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG62:![0-9]+]]
> > > +;
> > > entry:
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !41,
> metadata
> > > !DIExpression(), metadata !63, metadata ptr undef, metadata
> > > !DIExpression()), !dbg !64
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !51,
> metadata
> > > !DIExpression(), metadata !65, metadata ptr undef, metadata
> > > !DIExpression()), !dbg !64
> > >
> > > diff --git a/llvm/test/DebugInfo/Generic/assignment-
> > > tracking/sroa/memcpy.ll b/llvm/test/DebugInfo/Generic/assignment-
> > > tracking/sroa/memcpy.ll
> > > index f310456cc60a8..9bba4495375be 100644
> > > --- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memcpy.ll
> > > +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memcpy.ll
> > > @@ -1,3 +1,4 @@
> > > +; NOTE: Assertions have been autogenerated by
> utils/update_test_checks.py
> > > ; RUN: opt -passes=sroa,verify -S %s -o - -experimental-assignment-
> > > tracking \
> > > ; RUN: | FileCheck %s --implicit-check-not="call void @llvm.dbg"
> > >
> > > @@ -24,23 +25,12 @@
> > > ;; -Xclang -disable-llvm-passes -O2 -g -c -S -emit-llvm -o -
> > >
> > > ;; Split alloca.
> > > -; CHECK: entry:
> > > -; CHECK-NEXT: %To.sroa.0 = alloca { i32, i32, i32 }, align 8,
> !DIAssignID
> > > ![[ID_1:[0-9]+]]
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata {{.+}} undef,
> metadata
> > > ![[TO:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 96),
> > > metadata ![[ID_1]], metadata ptr %To.sroa.0, metadata
> !DIExpression()),
> > > !dbg
> > >
> > > -; CHECK-NEXT: %To.sroa.4 = alloca { i32, i32, i32 }, align 8,
> !DIAssignID
> > > ![[ID_3:[0-9]+]]
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata {{.+}} undef,
> metadata
> > > ![[TO]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96),
> metadata
> > > ![[ID_3]], metadata ptr %To.sroa.4, metadata !DIExpression()), !dbg
> > >
> > > ;; Split memcpy.
> > > -; CHECK: call void @llvm.memcpy{{.*}}(ptr align 8 %To.sroa.0, ptr
> align 4
> > > @From, i64 12, i1 false),{{.*}}!DIAssignID ![[ID_4:[0-9]+]]
> > > ;; This slice has been split and is promoted.
> > > -; CHECK: %To.sroa.3.0.copyload = load i32, ptr getelementptr inbounds
> > > (i8, ptr @From, i64 12)
> > > -; CHECK: call void @llvm.memcpy{{.*}}(ptr align 8 %To.sroa.4, ptr
> align 4
> > > getelementptr inbounds (i8, ptr @From, i64 16), i64 12, i1
> > > false){{.*}}!DIAssignID ![[ID_6:[0-9]+]]
> > >
> > > ;; Intrinsics for the splits above.
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata {{.+}} undef,
> metadata
> > > ![[TO]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 96), metadata
> > > ![[ID_4]], metadata ptr %To.sroa.0, metadata !DIExpression()), !dbg
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32
> > > %To.sroa.3.0.copyload, metadata ![[TO]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 96, 32), metadata !{{.+}}, metadata
> ptr
> > > undef, metadata !DIExpression()), !dbg
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata {{.+}} undef,
> metadata
> > > ![[TO]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96),
> metadata
> > > ![[ID_6]], metadata ptr %To.sroa.4, metadata !DIExpression()), !dbg
> > >
> > > target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-
> > > f80:128-n8:16:32:64-S128"
> > >
> > > @@ -50,6 +40,24 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-
> > > p272:64:64-i64:64-f80:128-n8:16
> > >
> > > ; Function Attrs: nounwind uwtable mustprogress
> > > define dso_local i32 @_Z7examplev() #0 !dbg !20 {
> > > +; CHECK-LABEL: @_Z7examplev(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: [[TO_SROA_0:%.*]] = alloca { i32, i32, i32 }, align
> 8,
> > > !DIAssignID !25
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META24:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0,
> 96),
> > > metadata [[META25:![0-9]+]], metadata ptr [[TO_SROA_0]], metadata
> > > !DIExpression()), !dbg [[DBG26:![0-9]+]]
> > > +; CHECK-NEXT: [[TO_SROA_4:%.*]] = alloca { i32, i32, i32 }, align
> 8,
> > > !DIAssignID !27
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META24]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96),
> metadata
> > > [[META27:![0-9]+]], metadata ptr [[TO_SROA_4]], metadata
> !DIExpression()),
> > > !dbg [[DBG26]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 12, ptr
> > > [[TO_SROA_0]]), !dbg [[DBG28:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 12, ptr
> > > [[TO_SROA_4]]), !dbg [[DBG28]]
> > > +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8
> > > [[TO_SROA_0]], ptr align 4 @From, i64 12, i1 false), !dbg [[DBG29:![0-
> > > 9]+]], !DIAssignID !30
> > > +; CHECK-NEXT: [[TO_SROA_3_0_COPYLOAD:%.*]] = load i32, ptr
> > > getelementptr inbounds (i8, ptr @From, i64 12), align 4, !dbg
> [[DBG29]]
> > > +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8
> > > [[TO_SROA_4]], ptr align 4 getelementptr inbounds (i8, ptr @From, i64
> 16),
> > > i64 12, i1 false), !dbg [[DBG29]], !DIAssignID !31
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META24]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 96),
> metadata
> > > [[META30:![0-9]+]], metadata ptr [[TO_SROA_0]], metadata
> !DIExpression()),
> > > !dbg [[DBG29]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32
> > > [[TO_SROA_3_0_COPYLOAD]], metadata [[META24]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 96, 32), metadata [[META32:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG29]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META24]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96),
> metadata
> > > [[META31:![0-9]+]], metadata ptr [[TO_SROA_4]], metadata
> !DIExpression()),
> > > !dbg [[DBG29]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 12, ptr
> > > [[TO_SROA_0]]), !dbg [[DBG33:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 12, ptr
> > > [[TO_SROA_4]]), !dbg [[DBG33]]
> > > +; CHECK-NEXT: ret i32 [[TO_SROA_3_0_COPYLOAD]], !dbg [[DBG34:![0-
> 9]+]]
> > > +;
> > > entry:
> > > %To = alloca %struct.LargeStruct, align 4, !DIAssignID !25
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !24,
> metadata
> > > !DIExpression(), metadata !25, metadata ptr %To, metadata
> > > !DIExpression()), !dbg !26
> > >
> > > diff --git a/llvm/test/DebugInfo/Generic/assignment-
> > > tracking/sroa/memmove-to-from-same-alloca.ll
> > > b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memmove-to-
> from-
> > > same-alloca.ll
> > > index 766e338aab5d7..0af17a37fdd4f 100644
> > > --- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memmove-to-
> > > from-same-alloca.ll
> > > +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memmove-to-
> > > from-same-alloca.ll
> > > @@ -1,3 +1,4 @@
> > > +; NOTE: Assertions have been autogenerated by
> utils/update_test_checks.py
> > > ; RUN: opt %s -passes=sroa -o - -S -experimental-assignment-tracking
> \
> > > ; RUN: | FileCheck %s
> > >
> > > @@ -6,7 +7,7 @@
> > > ;; __attribute__((nodebug)) int Cond;
> > > ;; __attribute__((nodebug)) Blob *C;
> > > ;; __attribute__((nodebug)) void call(int);
> > > -;;
> > > +;;
> > > ;; void f() {
> > > ;; int A[16];
> > > ;; __attribute__ ((nodebug)) int B[16];
> > > @@ -14,7 +15,7 @@
> > > ;; __builtin_memmove(&A[0], &Glob, sizeof(Blob));
> > > ;; call(0);
> > > ;; // B[8:14) <- Glob
> > > -;; __builtin_memmove(&B[8], &Glob, sizeof(Blob));
> > > +;; __builtin_memmove(&B[8], &Glob, sizeof(Blob));
> > > ;; call(A[0]);
> > > ;; // A[8:14) <- A[0:6)
> > > ;; __builtin_memmove(&A[8], &A[0], sizeof(Blob));
> > > @@ -24,9 +25,9 @@
> > > ;; __builtin_memmove(C, &A[8], sizeof(Blob));
> > > ;; else
> > > ;; // C <- B[8:14)
> > > -;; __builtin_memmove(C, &B[8], sizeof(Blob));
> > > +;; __builtin_memmove(C, &B[8], sizeof(Blob));
> > > ;; }
> > > -;;
> > > +;;
> > > ;; using:
> > > ;; clang test.cpp -emit-llvm -S -g -O2 -Xclang -disable-llvm-passes
> -o
> > > - \
> > > ;; | opt -passes=declare-to-assign -o test.ll - -S
> > > @@ -38,14 +39,9 @@
> > > ;; memcpy. Check that the dbg.assign address and fragment are correct
> and
> > > ;; ensure the DIAssignID still links it to the memmove(/memcpy).
> > >
> > > -; CHECK: %A.sroa.0.sroa.5 = alloca [5 x i32]
> > > -; CHECK: llvm.memcpy{{.*}}(ptr align 4 %A.sroa.0.sroa.5, ptr align 4
> > > getelementptr inbounds (i8, ptr @Glob, i64 4), i64 20, i1
> > > false){{.*}}!DIAssignID ![[ID:[0-9]+]]
> > > ;; Here's the dbg.assign for element 0 - it's not important for the
> test.
> > > -; CHECK-NEXT:
> llvm.dbg.assign({{.*}}!DIExpression(DW_OP_LLVM_fragment, 0,
> > > 32){{.*}})
> > > ;; This is the dbg.assign we care about:
> > > -; CHECK-NEXT: llvm.dbg.assign(metadata i1 undef, metadata ![[VAR:[0-
> > > 9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 32, 160), metadata
> > > ![[ID]], metadata ptr %A.sroa.0.sroa.5, metadata !DIExpression())
> > >
> > > -; CHECK: ![[VAR]] = !DILocalVariable(name: "A"
> > >
> > > source_filename = "test.cpp"
> > > target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-
> > > f80:128-n8:16:32:64-S128"
> > > @@ -59,6 +55,50 @@ target triple = "x86_64-unknown-linux-gnu"
> > >
> > > ; Function Attrs: mustprogress uwtable
> > > define dso_local void @_Z1fv() #0 !dbg !9 {
> > > +; CHECK-LABEL: @_Z1fv(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: [[A_SROA_0_SROA_5:%.*]] = alloca [5 x i32], align 4,
> > > !DIAssignID !18
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META13:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 32,
> 160),
> > > metadata [[META18:![0-9]+]], metadata ptr [[A_SROA_0_SROA_5]],
> metadata
> > > !DIExpression()), !dbg [[DBG19:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META13]], metadata !DIExpression(DW_OP_LLVM_fragment, 192, 64),
> metadata
> > > [[META20:![0-9]+]], metadata ptr undef, metadata !DIExpression()),
> !dbg
> > > [[DBG19]]
> > > +; CHECK-NEXT: [[A_SROA_51_SROA_5:%.*]] = alloca [5 x i32], align
> 4,
> > > !DIAssignID !21
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META13]], metadata !DIExpression(DW_OP_LLVM_fragment, 288, 160),
> > > metadata [[META21:![0-9]+]], metadata ptr [[A_SROA_51_SROA_5]],
> metadata
> > > !DIExpression()), !dbg [[DBG19]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META13]], metadata !DIExpression(DW_OP_LLVM_fragment, 448, 64),
> metadata
> > > [[META22:![0-9]+]], metadata ptr undef, metadata !DIExpression()),
> !dbg
> > > [[DBG19]]
> > > +; CHECK-NEXT: [[B:%.*]] = alloca [16 x i32], align 16
> > > +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 20, ptr
> > > [[A_SROA_0_SROA_5]]), !dbg [[DBG23:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 20, ptr
> > > [[A_SROA_51_SROA_5]]), !dbg [[DBG23]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 64, ptr
> [[B]]),
> > > !dbg [[DBG24:![0-9]+]]
> > > +; CHECK-NEXT: [[A_SROA_0_SROA_0_0_COPYLOAD:%.*]] = load i32, ptr
> > > @Glob, align 4, !dbg [[DBG25:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4
> > > [[A_SROA_0_SROA_5]], ptr align 4 getelementptr inbounds (i8, ptr
> @Glob,
> > > i64 4), i64 20, i1 false), !dbg [[DBG25]], !DIAssignID !26
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32
> > > [[A_SROA_0_SROA_0_0_COPYLOAD]], metadata [[META13]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 0, 32), metadata [[META27:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG19]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META13]], metadata !DIExpression(DW_OP_LLVM_fragment, 32, 160),
> metadata
> > > [[META26:![0-9]+]], metadata ptr [[A_SROA_0_SROA_5]], metadata
> > > !DIExpression()), !dbg [[DBG19]]
> > > +; CHECK-NEXT: call void @_Z4calli(i32 noundef 0), !dbg
> [[DBG28:![0-
> > > 9]+]]
> > > +; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [16 x
> i32],
> > > ptr [[B]], i64 0, i64 8, !dbg [[DBG29:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.memmove.p0.p0.i64(ptr align 16
> > > [[ARRAYIDX1]], ptr align 4 @Glob, i64 24, i1 false), !dbg [[DBG30:![0-
> > > 9]+]]
> > > +; CHECK-NEXT: call void @_Z4calli(i32 noundef
> > > [[A_SROA_0_SROA_0_0_COPYLOAD]]), !dbg [[DBG31:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4
> > > [[A_SROA_51_SROA_5]], ptr align 4 [[A_SROA_0_SROA_5]], i64 20, i1
> false),
> > > !dbg [[DBG32:![0-9]+]], !DIAssignID !33
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32
> > > [[A_SROA_0_SROA_0_0_COPYLOAD]], metadata [[META13]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 256, 32), metadata [[META34:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG19]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META13]], metadata !DIExpression(DW_OP_LLVM_fragment, 288, 160),
> > > metadata [[META33:![0-9]+]], metadata ptr [[A_SROA_51_SROA_5]],
> metadata
> > > !DIExpression()), !dbg [[DBG19]]
> > > +; CHECK-NEXT: call void @_Z4calli(i32 noundef
> > > [[A_SROA_0_SROA_0_0_COPYLOAD]]), !dbg [[DBG35:![0-9]+]]
> > > +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @Cond, align 4, !dbg
> > > [[DBG36:![0-9]+]]
> > > +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0, !dbg
> [[DBG36]]
> > > +; CHECK-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label
> > > [[IF_ELSE:%.*]], !dbg [[DBG38:![0-9]+]]
> > > +; CHECK: if.then:
> > > +; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr @C, align 8, !dbg
> > > [[DBG39:![0-9]+]]
> > > +; CHECK-NEXT: store i32 [[A_SROA_0_SROA_0_0_COPYLOAD]], ptr
> [[TMP1]],
> > > align 4, !dbg [[DBG40:![0-9]+]]
> > > +; CHECK-NEXT: [[A_SROA_51_SROA_5_0__SROA_IDX:%.*]] = getelementptr
> > > inbounds i8, ptr [[TMP1]], i64 4, !dbg [[DBG40]]
> > > +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4
> > > [[A_SROA_51_SROA_5_0__SROA_IDX]], ptr align 4 [[A_SROA_51_SROA_5]],
> i64
> > > 20, i1 false), !dbg [[DBG40]]
> > > +; CHECK-NEXT: br label [[IF_END:%.*]], !dbg [[DBG40]]
> > > +; CHECK: if.else:
> > > +; CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr @C, align 8, !dbg
> > > [[DBG41:![0-9]+]]
> > > +; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [16 x
> i32],
> > > ptr [[B]], i64 0, i64 8, !dbg [[DBG42:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.memmove.p0.p0.i64(ptr align 4
> [[TMP2]],
> > > ptr align 16 [[ARRAYIDX7]], i64 24, i1 false), !dbg [[DBG43:![0-9]+]]
> > > +; CHECK-NEXT: br label [[IF_END]]
> > > +; CHECK: if.end:
> > > +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 64, ptr [[B]]),
> !dbg
> > > [[DBG44:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 20, ptr
> > > [[A_SROA_0_SROA_5]]), !dbg [[DBG44]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 20, ptr
> > > [[A_SROA_51_SROA_5]]), !dbg [[DBG44]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG44]]
> > > +;
> > > entry:
> > > %A = alloca [16 x i32], align 16, !DIAssignID !18
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !13,
> metadata
> > > !DIExpression(), metadata !18, metadata ptr %A, metadata
> !DIExpression()),
> > > !dbg !19
> > >
> > > diff --git a/llvm/test/DebugInfo/Generic/assignment-
> > > tracking/sroa/rewrite.ll b/llvm/test/DebugInfo/Generic/assignment-
> > > tracking/sroa/rewrite.ll
> > > index 001693a4aecdf..ed4fb93e96ea5 100644
> > > --- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/rewrite.ll
> > > +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/rewrite.ll
> > > @@ -1,3 +1,4 @@
> > > +; NOTE: Assertions have been autogenerated by
> utils/update_test_checks.py
> > > ; RUN: opt -passes=sroa,verify -S %s -experimental-assignment-
> tracking -o
> > > - \
> > > ; RUN: | FileCheck %s --implicit-check-not="call void @llvm.dbg"
> > >
> > > @@ -22,27 +23,15 @@
> > > ;; }
> > > ;; $ clang test.cpp -Xclang -disable-llvm-passes -O2 -g -c -S -emit-
> llvm
> > > -o -
> > >
> > > -; CHECK: entry:
> > > -; CHECK-NEXT: %S.sroa.0 = alloca { i32, i32, i32 }, align 8,
> > > !DIAssignID ![[ID_1:[0-9]+]]
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > ![[VAR:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 96),
> > > metadata ![[ID_1]], metadata ptr %S.sroa.0, metadata !DIExpression()),
> > > !dbg
> > >
> > > ;; The middle slice has been promoted, so the alloca has gone away.
> > >
> > > -; CHECK-NEXT: %S.sroa.5 = alloca { i32, i32, i32 }, align 8,
> > > !DIAssignID ![[ID_3:[0-9]+]]
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96),
> metadata
> > > ![[ID_3]], metadata ptr %S.sroa.5, metadata !DIExpression()), !dbg
> > >
> > > ;; The memset has been sliced up (middle slice removed).
> > > -; CHECK: call void @llvm.memset{{.*}}(ptr align 8 %S.sroa.0, i8 0,
> i64
> > > 12, i1 false), !dbg !{{.+}}, !DIAssignID ![[ID_5:[0-9]+]]
> > > -; CHECK: call void @llvm.memset{{.*}}(ptr align 8 %S.sroa.5, i8 0,
> i64
> > > 12, i1 false), !dbg !{{.+}}, !DIAssignID ![[ID_6:[0-9]+]]
> > >
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i8 0, metadata
> > > ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 96), metadata
> > > ![[ID_5]], metadata ptr %S.sroa.0, metadata !DIExpression()), !dbg
> > > ;; Check the middle slice (no memset) gets a correct dbg.assign.
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32 0, metadata
> > > ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 96, 32),
> metadata
> > > !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i8 0, metadata
> > > ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96),
> metadata
> > > ![[ID_6]], metadata ptr %S.sroa.5, metadata !DIExpression()), !dbg
> > >
> > > ;; mem2reg promotes the load/store to the middle slice created by
> SROA:
> > > -; CHECK-NEXT: %0 = load i32, ptr @Glob, align 4, !dbg !{{.+}}
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32 %0, metadata
> > > ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 96, 32),
> metadata
> > > ![[ID_4:[0-9]+]], metadata ptr undef, metadata !DIExpression()), !dbg
> > >
> > > target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-
> > > f80:128-n8:16:32:64-S128"
> > >
> > > @@ -53,6 +42,25 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-
> > > p272:64:64-i64:64-f80:128-n8:16
> > >
> > > ; Function Attrs: nounwind uwtable mustprogress
> > > define dso_local i32 @_Z7examplev() #0 !dbg !14 {
> > > +; CHECK-LABEL: @_Z7examplev(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: [[S_SROA_0:%.*]] = alloca { i32, i32, i32 }, align
> 8,
> > > !DIAssignID !28
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META18:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0,
> 96),
> > > metadata [[META28:![0-9]+]], metadata ptr [[S_SROA_0]], metadata
> > > !DIExpression()), !dbg [[DBG29:![0-9]+]]
> > > +; CHECK-NEXT: [[S_SROA_5:%.*]] = alloca { i32, i32, i32 }, align
> 8,
> > > !DIAssignID !30
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META18]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96),
> metadata
> > > [[META30:![0-9]+]], metadata ptr [[S_SROA_5]], metadata
> !DIExpression()),
> > > !dbg [[DBG29]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 12, ptr
> > > [[S_SROA_0]]), !dbg [[DBG31:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 12, ptr
> > > [[S_SROA_5]]), !dbg [[DBG31]]
> > > +; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8
> [[S_SROA_0]],
> > > i8 0, i64 12, i1 false), !dbg [[DBG32:![0-9]+]], !DIAssignID !33
> > > +; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8
> [[S_SROA_5]],
> > > i8 0, i64 12, i1 false), !dbg [[DBG32]], !DIAssignID !34
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i8 0, metadata
> > > [[META18]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 96),
> metadata
> > > [[META33:![0-9]+]], metadata ptr [[S_SROA_0]], metadata
> !DIExpression()),
> > > !dbg [[DBG32]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32 0, metadata
> > > [[META18]], metadata !DIExpression(DW_OP_LLVM_fragment, 96, 32),
> metadata
> > > [[META35:![0-9]+]], metadata ptr undef, metadata !DIExpression()),
> !dbg
> > > [[DBG32]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i8 0, metadata
> > > [[META18]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96),
> metadata
> > > [[META34:![0-9]+]], metadata ptr [[S_SROA_5]], metadata
> !DIExpression()),
> > > !dbg [[DBG32]]
> > > +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @Glob, align 4, !dbg
> > > [[DBG36:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32 [[TMP0]],
> > > metadata [[META18]], metadata !DIExpression(DW_OP_LLVM_fragment, 96,
> 32),
> > > metadata [[META37:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG38:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 12, ptr
> > > [[S_SROA_0]]), !dbg [[DBG39:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 12, ptr
> > > [[S_SROA_5]]), !dbg [[DBG39]]
> > > +; CHECK-NEXT: ret i32 [[TMP0]], !dbg [[DBG40:![0-9]+]]
> > > +;
> > > entry:
> > > %S = alloca %struct.LargeStruct, align 4, !DIAssignID !28
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !18,
> metadata
> > > !DIExpression(), metadata !28, metadata ptr %S, metadata
> !DIExpression()),
> > > !dbg !29
> > >
> > > diff --git a/llvm/test/DebugInfo/Generic/assignment-
> > > tracking/sroa/store.ll b/llvm/test/DebugInfo/Generic/assignment-
> > > tracking/sroa/store.ll
> > > index c29cf488ce8b9..ef48d054ad01c 100644
> > > --- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/store.ll
> > > +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/store.ll
> > > @@ -1,3 +1,4 @@
> > > +; NOTE: Assertions have been autogenerated by
> utils/update_test_checks.py
> > > ; RUN: opt -passes=sroa,verify -S %s -o - -experimental-assignment-
> > > tracking \
> > > ; RUN: | FileCheck %s --implicit-check-not="call void @llvm.dbg"
> > >
> > > @@ -25,28 +26,16 @@
> > > ;; $ clang test.cpp -Xclang -disable-llvm-passes -O2 -g -c -S -emit-
> llvm
> > > -o - \
> > > ;; | opt -passes=declare-to-assign -S -o -
> > >
> > > -; CHECK: entry:
> > > -; CHECK-NEXT: %S.sroa.0 = alloca { i32, i32, i32 }, align 8,
> > > !DIAssignID ![[ID_1:[0-9]+]]
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > ![[VAR:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 96),
> > > metadata ![[ID_1]], metadata ptr %S.sroa.0, metadata !DIExpression()),
> > > !dbg
> > >
> > > -; CHECK-NEXT: %S.sroa.6 = alloca { i32, i32, i32 }, align 8,
> > > !DIAssignID ![[ID_3:[0-9]+]]
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96),
> metadata
> > > ![[ID_3]], metadata ptr %S.sroa.6, metadata !DIExpression()), !dbg
> > >
> > > ;; The memset has been split into [0, 96)[96, 128)[128, 224) bit
> slices.
> > > The
> > > ;; memset for the middle slice has been removed.
> > > -; CHECK: call void @llvm.memset{{.*}}(ptr align 8 %S.sroa.0, i8 0,
> i64
> > > 12, i1 false), !dbg !{{.+}}, !DIAssignID ![[ID_4:[0-9]+]]
> > > -; CHECK-NEXT: call void @llvm.memset{{.*}}(ptr align 8 %S.sroa.6, i8
> 0,
> > > i64 12, i1 false), !dbg !{{.+}}, !DIAssignID ![[ID_5:[0-9]+]]
> > >
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i8 0, metadata
> > > ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 96), metadata
> > > ![[ID_4]], metadata ptr %S.sroa.0, metadata !DIExpression()), !dbg
> > > ;; This is the one we care about most in this test: check that a
> memset-
> > > >store
> > > ;; gets a correct dbg.assign.
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32 0, metadata
> > > ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 96, 32),
> metadata
> > > !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i8 0, metadata
> > > ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96),
> metadata
> > > ![[ID_5]], metadata ptr %S.sroa.6, metadata !DIExpression()), !dbg
> > >
> > > ;; The load from global+store becomes a load.
> > > ;; FIXME: In reality it is actually stored again later on.
> > > -; CHECK-NEXT: %0 = load i32, ptr @Glob, align 4, !dbg !{{.+}}
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32 %0, metadata
> > > ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 96, 32),
> metadata
> > > !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg !
> > >
> > >
> > > target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-
> > > f80:128-n8:16:32:64-S128"
> > > @@ -58,6 +47,33 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-
> > > p272:64:64-i64:64-f80:128-n8:16
> > >
> > > ; Function Attrs: uwtable mustprogress
> > > define dso_local i32 @_Z7examplev() #0 !dbg !14 {
> > > +; CHECK-LABEL: @_Z7examplev(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: [[S_SROA_0:%.*]] = alloca { i32, i32, i32 }, align
> 8,
> > > !DIAssignID !28
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META18:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0,
> 96),
> > > metadata [[META28:![0-9]+]], metadata ptr [[S_SROA_0]], metadata
> > > !DIExpression()), !dbg [[DBG29:![0-9]+]]
> > > +; CHECK-NEXT: [[S_SROA_6:%.*]] = alloca { i32, i32, i32 }, align
> 8,
> > > !DIAssignID !30
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META18]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96),
> metadata
> > > [[META30:![0-9]+]], metadata ptr [[S_SROA_6]], metadata
> !DIExpression()),
> > > !dbg [[DBG29]]
> > > +; CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_LARGESTRUCT:%.*]],
> > > align 8
> > > +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 12, ptr
> > > [[S_SROA_0]]), !dbg [[DBG31:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 12, ptr
> > > [[S_SROA_6]]), !dbg [[DBG31]]
> > > +; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8
> [[S_SROA_0]],
> > > i8 0, i64 12, i1 false), !dbg [[DBG32:![0-9]+]], !DIAssignID !33
> > > +; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8
> [[S_SROA_6]],
> > > i8 0, i64 12, i1 false), !dbg [[DBG32]], !DIAssignID !34
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i8 0, metadata
> > > [[META18]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 96),
> metadata
> > > [[META33:![0-9]+]], metadata ptr [[S_SROA_0]], metadata
> !DIExpression()),
> > > !dbg [[DBG32]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32 0, metadata
> > > [[META18]], metadata !DIExpression(DW_OP_LLVM_fragment, 96, 32),
> metadata
> > > [[META35:![0-9]+]], metadata ptr undef, metadata !DIExpression()),
> !dbg
> > > [[DBG32]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i8 0, metadata
> > > [[META18]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96),
> metadata
> > > [[META34:![0-9]+]], metadata ptr [[S_SROA_6]], metadata
> !DIExpression()),
> > > !dbg [[DBG32]]
> > > +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @Glob, align 4, !dbg
> > > [[DBG36:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32 [[TMP0]],
> > > metadata [[META18]], metadata !DIExpression(DW_OP_LLVM_fragment, 96,
> 32),
> > > metadata [[META37:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG38:![0-9]+]]
> > > +; CHECK-NEXT: [[TMP1:%.*]] = bitcast ptr [[AGG_TMP]] to ptr, !dbg
> > > [[DBG39:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4
> [[TMP1]],
> > > ptr align 8 [[S_SROA_0]], i64 12, i1 false), !dbg [[DBG39]]
> > > +; CHECK-NEXT: [[S_SROA_4_0__SROA_IDX:%.*]] = getelementptr
> inbounds
> > > i8, ptr [[TMP1]], i64 12, !dbg [[DBG39]]
> > > +; CHECK-NEXT: store i32 [[TMP0]], ptr [[S_SROA_4_0__SROA_IDX]],
> align
> > > 4, !dbg [[DBG39]]
> > > +; CHECK-NEXT: [[S_SROA_6_0__SROA_IDX:%.*]] = getelementptr
> inbounds
> > > i8, ptr [[TMP1]], i64 16, !dbg [[DBG39]]
> > > +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4
> > > [[S_SROA_6_0__SROA_IDX]], ptr align 8 [[S_SROA_6]], i64 12, i1 false),
> > > !dbg [[DBG39]]
> > > +; CHECK-NEXT: [[CALL:%.*]] = call i32 @_Z3use11LargeStruct(ptr
> > > byval([[STRUCT_LARGESTRUCT]]) align 8 [[AGG_TMP]]), !dbg [[DBG40:![0-
> 9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 12, ptr
> > > [[S_SROA_0]]), !dbg [[DBG41:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 12, ptr
> > > [[S_SROA_6]]), !dbg [[DBG41]]
> > > +; CHECK-NEXT: ret i32 [[TMP0]], !dbg [[DBG42:![0-9]+]]
> > > +;
> > > entry:
> > > %S = alloca %struct.LargeStruct, align 4, !DIAssignID !28
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !18,
> metadata
> > > !DIExpression(), metadata !28, metadata ptr %S, metadata
> !DIExpression()),
> > > !dbg !29
> > >
> > > diff --git a/llvm/test/DebugInfo/Generic/assignment-
> > > tracking/sroa/unspecified-var-size.ll
> > > b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/unspecified-
> var-
> > > size.ll
> > > index 6234e6c6b1d05..cc2c8a30f723a 100644
> > > --- a/llvm/test/DebugInfo/Generic/assignment-
> tracking/sroa/unspecified-
> > > var-size.ll
> > > +++ b/llvm/test/DebugInfo/Generic/assignment-
> tracking/sroa/unspecified-
> > > var-size.ll
> > > @@ -1,3 +1,4 @@
> > > +; NOTE: Assertions have been autogenerated by
> utils/update_test_checks.py
> > > ; RUN: opt -S %s -passes=sroa -o - -experimental-assignment-tracking
> |
> > > FileCheck %s
> > >
> > > ;; $ cat test.cpp
> > > @@ -7,10 +8,14 @@
> > > ;; Check that migrateDebugInfo doesn't crash when encountering an
> alloca
> > > for a
> > > ;; variable with a type of unspecified size (e.g.
> > > DW_TAG_unspecified_type).
> > >
> > > -; CHECK: @llvm.dbg.assign(metadata ptr %0,{{.+}}, metadata
> > > !DIExpression(),{{.+}}, metadata ptr undef, {{.+}})
> > > ;; There should be no new fragment and the value component should
> remain
> > > as %0.
> > >
> > > define dso_local void @_Z3funDn(ptr %0) #0 !dbg !14 {
> > > +; CHECK-LABEL: @_Z3funDn(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata ptr
> [[TMP0:%.*]],
> > > metadata [[META21:![0-9]+]], metadata !DIExpression(), metadata
> > > [[META22:![0-9]+]], metadata ptr undef, metadata !DIExpression()),
> !dbg
> > > [[DBG23:![0-9]+]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG24:![0-9]+]]
> > > +;
> > > entry:
> > > %.addr = alloca i8*, align 8, !DIAssignID !22
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !21,
> metadata
> > > !DIExpression(), metadata !22, metadata ptr %.addr, metadata
> > > !DIExpression()), !dbg !23
> > >
> > > diff --git a/llvm/test/DebugInfo/Generic/assignment-
> tracking/sroa/user-
> > > memcpy.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/user-
> > > memcpy.ll
> > > index d8b6d76456d80..2d5df04825d23 100644
> > > --- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/user-
> memcpy.ll
> > > +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/user-
> memcpy.ll
> > > @@ -1,3 +1,4 @@
> > > +; NOTE: Assertions have been autogenerated by
> utils/update_test_checks.py
> > > ; RUN: opt -passes=sroa -S %s -o - -experimental-assignment-tracking
> \
> > > ; RUN: | FileCheck %s --implicit-check-not="call void @llvm.dbg"
> > >
> > > @@ -19,39 +20,24 @@
> > > ;; $ clang++ -c -O2 -g test.cpp -o - -Xclang -disable-llvm-passes -S
> -
> > > emit-llvm \
> > > ;; | opt -passes=declare-to-assign -S -o -
> > >
> > > -; CHECK: entry:
> > > ;; Allocas have been promoted - the linked dbg.assigns have been
> removed.
> > >
> > > ;; | V3i point = {0, 0, 0};
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 0, metadata
> > > ![[point:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64),
> > > metadata !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 0, metadata
> > > ![[point]], metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64),
> metadata
> > > !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 0, metadata
> > > ![[point]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 64),
> metadata
> > > !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg
> > >
> > > ;; point.z = 5000;
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 5000, metadata
> > > ![[point]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 64),
> metadata
> > > !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg
> > >
> > > ;; | V3i other = {10, 9, 8};
> > > ;; other is global const:
> > > ;; local.other.x = global.other.x
> > > ;; local.other.y = global.other.y
> > > ;; local.other.z = global.other.z
> > > -; CHECK-NEXT: %other.sroa.0.0.copyload = load i64, ptr
> > > @__const._Z3funv.other
> > > -; CHECK-NEXT: %other.sroa.4.0.copyload = load i64, ptr getelementptr
> > > inbounds (i8, ptr @__const._Z3funv.other, i64 8)
> > > -; CHECK-NEXT: %other.sroa.5.0.copyload = load i64, ptr getelementptr
> > > inbounds (i8, ptr @__const._Z3funv.other, i64 16)
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64
> > > %other.sroa.0.0.copyload, metadata ![[other:[0-9]+]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata !{{.+}}, metadata
> ptr
> > > undef, metadata !DIExpression()), !dbg
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64
> > > %other.sroa.4.0.copyload, metadata ![[other]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata !{{.+}}, metadata
> ptr
> > > undef, metadata !DIExpression()), !dbg
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64
> > > %other.sroa.5.0.copyload, metadata ![[other]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 128, 64), metadata !{{.+}},
> metadata
> > > ptr undef, metadata !DIExpression()), !dbg
> > >
> > > ;; | std::memcpy(&point.y, &other.x, sizeof(long) * 2);
> > > ;; other is now 3 scalars:
> > > ;; point.y = other.x
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64
> > > %other.sroa.0.0.copyload, metadata ![[point]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata !{{.+}}, metadata
> ptr
> > > undef, metadata !DIExpression()), !dbg
> > > ;;
> > > ;; point.z = other.y
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64
> > > %other.sroa.4.0.copyload, metadata ![[point]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 128, 64), metadata !{{.+}},
> metadata
> > > ptr undef, metadata !DIExpression()), !dbg
> > >
> > > -; CHECK: ![[point]] = !DILocalVariable(name: "point",
> > > -; CHECK: ![[other]] = !DILocalVariable(name: "other",
> > >
> > > source_filename = "test.cpp"
> > > target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-
> > > f80:128-n8:16:32:64-S128"
> > > @@ -63,6 +49,22 @@ target triple = "x86_64-unknown-linux-gnu"
> > >
> > > ; Function Attrs: nounwind uwtable mustprogress
> > > define dso_local void @_Z3funv() !dbg !100 {
> > > +; CHECK-LABEL: @_Z3funv(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 0, metadata
> > > [[META104:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0,
> 64),
> > > metadata [[META112:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG113:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 0, metadata
> > > [[META104]], metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64),
> metadata
> > > [[META114:![0-9]+]], metadata ptr undef, metadata !DIExpression()),
> !dbg
> > > [[DBG113]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 0, metadata
> > > [[META104]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 64),
> > > metadata [[META115:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG113]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 5000,
> metadata
> > > [[META104]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 64),
> > > metadata [[META116:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG117:![0-9]+]]
> > > +; CHECK-NEXT: [[OTHER_SROA_0_0_COPYLOAD:%.*]] = load i64, ptr
> > > @__const._Z3funv.other, align 8, !dbg [[DBG118:![0-9]+]]
> > > +; CHECK-NEXT: [[OTHER_SROA_4_0_COPYLOAD:%.*]] = load i64, ptr
> > > getelementptr inbounds (i8, ptr @__const._Z3funv.other, i64 8), align
> 8,
> > > !dbg [[DBG118]]
> > > +; CHECK-NEXT: [[OTHER_SROA_5_0_COPYLOAD:%.*]] = load i64, ptr
> > > getelementptr inbounds (i8, ptr @__const._Z3funv.other, i64 16), align
> 8,
> > > !dbg [[DBG118]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64
> > > [[OTHER_SROA_0_0_COPYLOAD]], metadata [[META111:![0-9]+]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata [[META119:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG118]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64
> > > [[OTHER_SROA_4_0_COPYLOAD]], metadata [[META111]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata [[META120:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG118]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64
> > > [[OTHER_SROA_5_0_COPYLOAD]], metadata [[META111]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 128, 64), metadata [[META121:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG118]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64
> > > [[OTHER_SROA_0_0_COPYLOAD]], metadata [[META104]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata [[META122:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG123:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64
> > > [[OTHER_SROA_4_0_COPYLOAD]], metadata [[META104]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 128, 64), metadata [[META124:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG123]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG125:![0-9]+]]
> > > +;
> > > entry:
> > > %point = alloca %struct.V3i, align 8, !DIAssignID !112
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !104,
> metadata
> > > !DIExpression(), metadata !112, metadata ptr %point, metadata
> > > !DIExpression()), !dbg !113
> > >
> > > diff --git a/llvm/test/DebugInfo/Generic/assignment-
> tracking/sroa/vec-
> > > 1.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-1.ll
> > > index 3d83e18afdf6e..ceedabd5a52fd 100644
> > > --- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-1.ll
> > > +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-1.ll
> > > @@ -1,3 +1,4 @@
> > > +; NOTE: Assertions have been autogenerated by
> utils/update_test_checks.py
> > > ; RUN: opt %s -S -passes=sroa -o - -experimental-assignment-tracking
> |
> > > FileCheck %s
> > >
> > > ;; Ensure that only the value-expression gets fragment info; that the
> > > @@ -16,17 +17,22 @@
> > > ;; Generated by grabbing IR before sroa in:
> > > ;; $ clang++ -O2 -g -c test.cpp -Xclang -fexperimental-assignment-
> > > tracking
> > >
> > > -; CHECK: %call = call
> > > -; CHECK-NEXT: %0 = extractvalue { <2 x float>, <2 x float> } %call, 0
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float> %0,
> > > metadata ![[var:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment,
> 0,
> > > 64), metadata ![[id1:[0-9]+]],{{.+}} undef, metadata !DIExpression()),
> > > !dbg
> > > -; CHECK-NEXT: %1 = extractvalue { <2 x float>, <2 x float> } %call, 1
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float> %1,
> > > metadata ![[var]], metadata !DIExpression(DW_OP_LLVM_fragment, 64,
> 64),
> > > metadata ![[id2:[0-9]+]], {{.+}} undef, metadata !DIExpression()),
> !dbg
> > >
> > > %class.c = type { i8 }
> > > %class.a = type { [4 x float] }
> > >
> > > ; Function Attrs: uwtable
> > > define dso_local void @_ZNK1c1dEv(ptr %this) #0 align 2 !dbg !7 {
> > > +; CHECK-LABEL: @_ZNK1c1dEv(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata ptr
> [[THIS:%.*]],
> > > metadata [[META26:![0-9]+]], metadata !DIExpression(), metadata
> > > [[META29:![0-9]+]], metadata ptr undef, metadata !DIExpression()),
> !dbg
> > > [[DBG30:![0-9]+]]
> > > +; CHECK-NEXT: [[CALL:%.*]] = call { <2 x float>, <2 x float> }
> > > @_ZNK1c5m_fn1Ev(ptr [[THIS]]), !dbg [[DBG31:![0-9]+]]
> > > +; CHECK-NEXT: [[TMP0:%.*]] = extractvalue { <2 x float>, <2 x
> float> }
> > > [[CALL]], 0, !dbg [[DBG31]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> > > [[TMP0]], metadata [[META28:![0-9]+]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata [[META32:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG30]]
> > > +; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <2 x float>, <2 x
> float> }
> > > [[CALL]], 1, !dbg [[DBG31]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> > > [[TMP1]], metadata [[META28]], metadata
> !DIExpression(DW_OP_LLVM_fragment,
> > > 64, 64), metadata [[META33:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG30]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG34:![0-9]+]]
> > > +;
> > > entry:
> > > %this.addr = alloca ptr, align 8, !DIAssignID !29
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !26,
> metadata
> > > !DIExpression(), metadata !29, metadata ptr %this.addr, metadata
> > > !DIExpression()), !dbg !30
> > >
> > > diff --git a/llvm/test/DebugInfo/Generic/assignment-
> tracking/sroa/vec-
> > > 2.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-2.ll
> > > index e04a5a9b58e0c..e6d37c80ed0dd 100644
> > > --- a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-2.ll
> > > +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-2.ll
> > > @@ -1,3 +1,4 @@
> > > +; NOTE: Assertions have been autogenerated by
> utils/update_test_checks.py
> > > ; RUN: opt %s -S -passes=sroa -o - -experimental-assignment-tracking
> |
> > > FileCheck %s
> > >
> > > ;; $ cat test.cpp
> > > @@ -26,12 +27,7 @@
> > > ;; dbg.assign/DIExpression. Ensure that only the value-expression
> gets
> > > fragment
> > > ;; info; that the address-expression remains untouched.
> > >
> > > -; CHECK: %i.sroa.4.12.vec.insert = insertelement <2 x float>
> > > %i.sroa.4.0.vec.insert, float %2, i32 1, !dbg
> > > ;; There's a few dbg intrinsics we're not interested in testing
> wedged in
> > > here.
> > > -; CHECK-NEXT: dbg.value
> > > -; CHECK-NEXT: dbg.assign
> > > -; CHECK-NEXT: dbg.assign
> > > -; CHECK-NEXT: call void @llvm.dbg.assign(metadata float %2,{{.+}},
> > > metadata !DIExpression(DW_OP_LLVM_fragment, 96, 32),{{.+}}, metadata
> ptr
> > > undef, metadata !DIExpression()), !dbg
> > >
> > > %class.d = type { %class.a }
> > > %class.a = type { [4 x float] }
> > > @@ -44,6 +40,35 @@ $_ZN1dC2Ev = comdat any
> > >
> > > ; Function Attrs: uwtable
> > > define dso_local void @_Z1gv() local_unnamed_addr #0 !dbg !11 {
> > > +; CHECK-LABEL: @_Z1gv(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META15:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0,
> 64),
> > > metadata [[META32:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG33:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META15]], metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64),
> metadata
> > > [[META34:![0-9]+]], metadata ptr undef, metadata !DIExpression()),
> !dbg
> > > [[DBG33]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META30:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0,
> 64),
> > > metadata [[META35:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG33]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META30]], metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64),
> metadata
> > > [[META36:![0-9]+]], metadata ptr undef, metadata !DIExpression()),
> !dbg
> > > [[DBG33]]
> > > +; CHECK-NEXT: [[CALL:%.*]] = call { <2 x float>, <2 x float> }
> > > @_Z1fv(), !dbg [[DBG37:![0-9]+]]
> > > +; CHECK-NEXT: [[TMP0:%.*]] = extractvalue { <2 x float>, <2 x
> float> }
> > > [[CALL]], 0, !dbg [[DBG37]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> > > [[TMP0]], metadata [[META15]], metadata
> !DIExpression(DW_OP_LLVM_fragment,
> > > 0, 64), metadata [[META38:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG33]]
> > > +; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <2 x float>, <2 x
> float> }
> > > [[CALL]], 1, !dbg [[DBG37]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> > > [[TMP1]], metadata [[META15]], metadata
> !DIExpression(DW_OP_LLVM_fragment,
> > > 64, 64), metadata [[META39:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG33]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> > > [[TMP0]], metadata [[META30]], metadata
> !DIExpression(DW_OP_LLVM_fragment,
> > > 0, 64), metadata [[META40:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG33]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> > > [[TMP1]], metadata [[META30]], metadata
> !DIExpression(DW_OP_LLVM_fragment,
> > > 64, 64), metadata [[META41:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG33]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> > > [[TMP0]], metadata [[META31:![0-9]+]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata [[META42:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG33]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> > > [[TMP1]], metadata [[META31]], metadata
> !DIExpression(DW_OP_LLVM_fragment,
> > > 64, 64), metadata [[META43:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG33]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META44:![0-9]+]], metadata !DIExpression(), metadata [[META48:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG49:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata ptr undef,
> metadata
> > > [[META44]], metadata !DIExpression(), metadata [[META51:![0-9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG49]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META52:![0-9]+]], metadata !DIExpression(), metadata [[META55:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG56:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata ptr undef,
> metadata
> > > [[META52]], metadata !DIExpression(), metadata [[META58:![0-9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG56]]
> > > +; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr @c, align 4, !dbg
> > > [[DBG59:![0-9]+]]
> > > +; CHECK-NEXT: [[I_SROA_4_0_VEC_INSERT:%.*]] = insertelement <2 x
> > > float> [[TMP1]], float undef, i32 0, !dbg [[DBG61:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.value(metadata <2 x float>
> > > [[I_SROA_4_0_VEC_INSERT]], metadata [[META31]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 64, 64)), !dbg [[DBG33]]
> > > +; CHECK-NEXT: [[I_SROA_4_12_VEC_INSERT:%.*]] = insertelement <2 x
> > > float> [[I_SROA_4_0_VEC_INSERT]], float [[TMP2]], i32 1, !dbg
> [[DBG61]]
> > > +; CHECK-NEXT: call void @llvm.dbg.value(metadata <2 x float>
> > > [[I_SROA_4_12_VEC_INSERT]], metadata [[META31]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 64, 64)), !dbg [[DBG33]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> undef,
> > > metadata [[META31]], metadata !DIExpression(DW_OP_LLVM_fragment, 0,
> 64),
> > > metadata [[META62:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG33]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float>
> > > [[I_SROA_4_0_VEC_INSERT]], metadata [[META31]], metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 64, 32), metadata [[META63:![0-
> 9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG33]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata float [[TMP2]],
> > > metadata [[META31]], metadata !DIExpression(DW_OP_LLVM_fragment, 96,
> 32),
> > > metadata [[META64:![0-9]+]], metadata ptr undef, metadata
> > > !DIExpression()), !dbg [[DBG33]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG65:![0-9]+]]
> > > +;
> > > entry:
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !15,
> metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata !32, metadata ptr
> > > undef, metadata !DIExpression()), !dbg !33
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !15,
> metadata
> > > !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata !34, metadata ptr
> > > undef, metadata !DIExpression()), !dbg !33
> > > @@ -94,6 +119,12 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(ptr
> noalias
> > > nocapture writeonly, ptr noa
> > >
> > > ; Function Attrs: nounwind uwtable
> > > define linkonce_odr dso_local void @_ZN1d1eEv(ptr %this)
> > > local_unnamed_addr #3 comdat align 2 !dbg !48 {
> > > +; CHECK-LABEL: @_ZN1d1eEv(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META44]], metadata !DIExpression(), metadata [[META69:![0-9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG70:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata ptr
> [[THIS:%.*]],
> > > metadata [[META44]], metadata !DIExpression(), metadata [[META71:![0-
> > > 9]+]], metadata ptr undef, metadata !DIExpression()), !dbg [[DBG70]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG72:![0-9]+]]
> > > +;
> > > entry:
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !47,
> metadata
> > > !DIExpression(), metadata !78, metadata ptr undef, metadata
> > > !DIExpression()), !dbg !79
> > > call void @llvm.dbg.assign(metadata ptr %this, metadata !47,
> metadata
> > > !DIExpression(), metadata !80, metadata ptr undef, metadata
> > > !DIExpression()), !dbg !79
> > > @@ -102,6 +133,15 @@ entry:
> > >
> > > ; Function Attrs: nounwind uwtable
> > > define linkonce_odr dso_local void @_ZN1dC2Ev(ptr %this) unnamed_addr
> #3
> > > comdat align 2 !dbg !57 {
> > > +; CHECK-LABEL: @_ZN1dC2Ev(
> > > +; CHECK-NEXT: entry:
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef,
> metadata
> > > [[META52]], metadata !DIExpression(), metadata [[META73:![0-9]+]],
> > > metadata ptr undef, metadata !DIExpression()), !dbg [[DBG74:![0-9]+]]
> > > +; CHECK-NEXT: call void @llvm.dbg.assign(metadata ptr
> [[THIS:%.*]],
> > > metadata [[META52]], metadata !DIExpression(), metadata [[META75:![0-
> > > 9]+]], metadata ptr undef, metadata !DIExpression()), !dbg [[DBG74]]
> > > +; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @c, align 4, !dbg
> > > [[DBG76:![0-9]+]]
> > > +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds
> > > [[CLASS_D:%.*]], ptr [[THIS]], i64 0, i32 0, i32 0, i64 3, !dbg
> > > [[DBG77:![0-9]+]]
> > > +; CHECK-NEXT: store float [[TMP0]], ptr [[ARRAYIDX]], align 4,
> !dbg
> > > [[DBG78:![0-9]+]]
> > > +; CHECK-NEXT: ret void, !dbg [[DBG79:![0-9]+]]
> > > +;
> > > entry:
> > > call void @llvm.dbg.assign(metadata i1 undef, metadata !56,
> metadata
> > > !DIExpression(), metadata !82, metadata ptr undef, metadata
> > > !DIExpression()), !dbg !83
> > > call void @llvm.dbg.assign(metadata ptr %this, metadata !56,
> metadata
> > > !DIExpression(), metadata !84, metadata ptr undef, metadata
> > > !DIExpression()), !dbg !83
> > >
> > >
> > >
> > > _______________________________________________
> > > llvm-commits mailing list
> > > llvm-commits at lists.llvm.org
> > > https://urldefense.com/v3/__https://lists.llvm.org/cgi-
> > > bin/mailman/listinfo/llvm-
> > >
> commits__;!!JmoZiZGBv3RvKRSx!9KPZBMFLJky0OiOtaS7FN9zDnCuBHEkeYp5Z4NUvm-
> > > yWl3S48O_wFxaBVYc5nPzSFYpD1yOBeP5OfbJRsbxat8hj9giO$
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