[llvm] 5ebdd83 - [PowerPC] Simplify PPCSubtarget
Kai Nacke via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 15 07:09:48 PST 2022
Author: Kai Nacke
Date: 2022-12-15T15:09:30Z
New Revision: 5ebdd838fb9c35d1dcc823aaddb1daec10af09e5
URL: https://github.com/llvm/llvm-project/commit/5ebdd838fb9c35d1dcc823aaddb1daec10af09e5
DIFF: https://github.com/llvm/llvm-project/commit/5ebdd838fb9c35d1dcc823aaddb1daec10af09e5.diff
LOG: [PowerPC] Simplify PPCSubtarget
The flags, initialization of the flags, and the getter methods for
features defined in PPC.td can be generated by TableGen.
Reviewed By: shchenz
Differential Revision: https://reviews.llvm.org/D140028
Added:
Modified:
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 53f930bebce7..d05723461103 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -55,6 +55,8 @@ def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">;
def DirectivePwrFuture
: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
+// Specifies that the selected CPU supports 64-bit instructions, regardless of
+// whether we are in 32-bit or 64-bit mode.
def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
"Enable 64-bit instructions">;
def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">;
@@ -63,8 +65,14 @@ def FeatureModernAIXAs
"AIX system assembler is modern enough to support new mnes">;
def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
"Enable floating-point instructions">;
+
+// Specifies that we are in 64-bit mode or that we should use 64-bit registers
+// in 32-bit mode when possible. Requires Feature64Bit to be enabled.
def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
"Enable 64-bit registers usage for ppc32 [beta]">;
+
+// Specify if we should store and manipulate i1 values in the individual
+// condition register bits.
def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
"Use condition-register bits individually">;
def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true",
@@ -133,7 +141,7 @@ def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
[FeatureBookE]>;
def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true",
"Enable E500/E500mc instructions">;
-def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true",
+def FeatureSecurePlt : SubtargetFeature<"secure-plt","IsSecurePlt", "true",
"Enable secure plt mode">;
def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
"Enable PPC 4xx instructions">;
@@ -172,7 +180,7 @@ def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
"Always use indirect calls">;
def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
"Enable Hardware Transactional Memory instructions">;
-def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true",
+def FeatureMFTB : SubtargetFeature<"", "IsFeatureMFTB", "true",
"Implement mftb using the mfspr instruction">;
def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
"Target supports instruction fusion">;
@@ -246,7 +254,7 @@ def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
"POPCNTD_Slow",
"Has slow popcnt[dw] instructions">;
-def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
+def DeprecatedDST : SubtargetFeature<"", "IsDeprecatedDST", "true",
"Treat vector data stream cache control instructions as deprecated">;
def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06",
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
index 599629c6fb2b..08993690dbc3 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -71,88 +71,6 @@ PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
void PPCSubtarget::initializeEnvironment() {
StackAlignment = Align(16);
CPUDirective = PPC::DIR_NONE;
- HasMFOCRF = false;
- Has64BitSupport = false;
- Use64BitRegs = false;
- UseCRBits = false;
- HasHardFloat = false;
- HasAltivec = false;
- HasSPE = false;
- HasEFPU2 = false;
- HasFPU = false;
- HasVSX = false;
- NeedsTwoConstNR = false;
- HasP8Vector = false;
- HasP8Altivec = false;
- HasP8Crypto = false;
- HasP9Vector = false;
- HasP9Altivec = false;
- HasMMA = false;
- HasROPProtect = false;
- HasPrivileged = false;
- HasP10Vector = false;
- HasPrefixInstrs = false;
- HasPCRelativeMemops = false;
- HasFCPSGN = false;
- HasFSQRT = false;
- HasFRE = false;
- HasFRES = false;
- HasFRSQRTE = false;
- HasFRSQRTES = false;
- HasRecipPrec = false;
- HasSTFIWX = false;
- HasLFIWAX = false;
- HasFPRND = false;
- HasFPCVT = false;
- HasISEL = false;
- HasBPERMD = false;
- HasExtDiv = false;
- HasCMPB = false;
- HasLDBRX = false;
- IsBookE = false;
- HasOnlyMSYNC = false;
- IsPPC4xx = false;
- IsPPC6xx = false;
- IsE500 = false;
- FeatureMFTB = false;
- AllowsUnalignedFPAccess = false;
- DeprecatedDST = false;
- HasICBT = false;
- HasInvariantFunctionDescriptors = false;
- HasPartwordAtomics = false;
- HasQuadwordAtomics = false;
- HasDirectMove = false;
- HasHTM = false;
- HasFloat128 = false;
- HasFusion = false;
- HasStoreFusion = false;
- HasAddiLoadFusion = false;
- HasAddisLoadFusion = false;
- HasArithAddFusion = false;
- HasAddLogicalFusion = false;
- HasLogicalAddFusion = false;
- HasLogicalFusion = false;
- HasSha3Fusion = false;
- HasCompareFusion = false;
- HasWideImmFusion = false;
- HasZeroMoveFusion = false;
- HasBack2BackFusion = false;
- IsISA2_06 = false;
- IsISA2_07 = false;
- IsISA3_0 = false;
- IsISA3_1 = false;
- IsISAFuture = false;
- UseLongCalls = false;
- SecurePlt = false;
- VectorsUseTwoUnits = false;
- UsePPCPreRASchedStrategy = false;
- UsePPCPostRASchedStrategy = false;
- PairedVectorMemops = false;
- PredictableSelectIsExpensive = false;
- HasFastMFLR = false;
- HasModernAIXAs = false;
- IsAIX = false;
-
HasPOPCNTD = POPCNTD_Unavailable;
}
@@ -183,7 +101,7 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) ||
TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() ||
TargetTriple.isMusl())
- SecurePlt = true;
+ IsSecurePlt = true;
if (HasSPE && IsPPC64)
report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h
index 6df96312670d..007ffd5c0235 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -87,90 +87,16 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
/// Selected instruction itineraries (one entry per itinerary class.)
InstrItineraryData InstrItins;
+// Bool members corresponding to the SubtargetFeatures defined in tablegen.
+#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
+ bool ATTRIBUTE = DEFAULT;
+#include "PPCGenSubtargetInfo.inc"
+
/// Which cpu directive was used.
unsigned CPUDirective;
- /// Used by the ISel to turn in optimizations for POWER4-derived architectures
- bool HasMFOCRF;
- bool Has64BitSupport;
- bool Use64BitRegs;
- bool UseCRBits;
- bool HasHardFloat;
bool IsPPC64;
- bool HasAltivec;
- bool HasFPU;
- bool HasSPE;
- bool HasEFPU2;
- bool HasVSX;
- bool NeedsTwoConstNR;
- bool HasP8Vector;
- bool HasP8Altivec;
- bool HasP8Crypto;
- bool HasP9Vector;
- bool HasP9Altivec;
- bool HasP10Vector;
- bool HasPrefixInstrs;
- bool HasPCRelativeMemops;
- bool HasMMA;
- bool HasROPProtect;
- bool HasPrivileged;
- bool HasFCPSGN;
- bool HasFSQRT;
- bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
- bool HasRecipPrec;
- bool HasSTFIWX;
- bool HasLFIWAX;
- bool HasFPRND;
- bool HasFPCVT;
- bool HasISEL;
- bool HasBPERMD;
- bool HasExtDiv;
- bool HasCMPB;
- bool HasLDBRX;
- bool IsBookE;
- bool HasOnlyMSYNC;
- bool IsE500;
- bool IsPPC4xx;
- bool IsPPC6xx;
- bool FeatureMFTB;
- bool AllowsUnalignedFPAccess;
- bool DeprecatedDST;
bool IsLittleEndian;
- bool HasICBT;
- bool HasInvariantFunctionDescriptors;
- bool HasPartwordAtomics;
- bool HasQuadwordAtomics;
- bool HasDirectMove;
- bool HasHTM;
- bool HasFloat128;
- bool HasFusion;
- bool HasStoreFusion;
- bool HasAddiLoadFusion;
- bool HasAddisLoadFusion;
- bool HasArithAddFusion;
- bool HasAddLogicalFusion;
- bool HasLogicalAddFusion;
- bool HasLogicalFusion;
- bool HasSha3Fusion;
- bool HasCompareFusion;
- bool HasWideImmFusion;
- bool HasZeroMoveFusion;
- bool HasBack2BackFusion;
- bool IsISA2_06;
- bool IsISA2_07;
- bool IsISA3_0;
- bool IsISA3_1;
- bool IsISAFuture;
- bool UseLongCalls;
- bool SecurePlt;
- bool VectorsUseTwoUnits;
- bool UsePPCPreRASchedStrategy;
- bool UsePPCPostRASchedStrategy;
- bool PairedVectorMemops;
- bool PredictableSelectIsExpensive;
- bool HasFastMFLR;
- bool HasModernAIXAs;
- bool IsAIX;
POPCNTDKind HasPOPCNTD;
@@ -240,9 +166,6 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
///
bool isPPC64() const;
- /// has64BitSupport - Return true if the selected CPU supports 64-bit
- /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
- bool has64BitSupport() const { return Has64BitSupport; }
// useSoftFloat - Return true if soft-float option is turned on.
bool useSoftFloat() const {
if (isAIXABI() && !HasHardFloat)
@@ -250,74 +173,13 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
return !HasHardFloat;
}
- /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
- /// registers in 32-bit mode when possible. This can only true if
- /// has64BitSupport() returns true.
- bool use64BitRegs() const { return Use64BitRegs; }
-
- /// useCRBits - Return true if we should store and manipulate i1 values in
- /// the individual condition register bits.
- bool useCRBits() const { return UseCRBits; }
-
// isLittleEndian - True if generating little-endian code
bool isLittleEndian() const { return IsLittleEndian; }
- // Specific obvious features.
- bool hasFCPSGN() const { return HasFCPSGN; }
- bool hasFSQRT() const { return HasFSQRT; }
- bool hasFRE() const { return HasFRE; }
- bool hasFRES() const { return HasFRES; }
- bool hasFRSQRTE() const { return HasFRSQRTE; }
- bool hasFRSQRTES() const { return HasFRSQRTES; }
- bool hasRecipPrec() const { return HasRecipPrec; }
- bool hasSTFIWX() const { return HasSTFIWX; }
- bool hasLFIWAX() const { return HasLFIWAX; }
- bool hasFPRND() const { return HasFPRND; }
- bool hasFPCVT() const { return HasFPCVT; }
- bool hasAltivec() const { return HasAltivec; }
- bool hasSPE() const { return HasSPE; }
- bool hasEFPU2() const { return HasEFPU2; }
- bool hasFPU() const { return HasFPU; }
- bool hasVSX() const { return HasVSX; }
- bool needsTwoConstNR() const { return NeedsTwoConstNR; }
- bool hasP8Vector() const { return HasP8Vector; }
- bool hasP8Altivec() const { return HasP8Altivec; }
- bool hasP8Crypto() const { return HasP8Crypto; }
- bool hasP9Vector() const { return HasP9Vector; }
- bool hasP9Altivec() const { return HasP9Altivec; }
- bool hasP10Vector() const { return HasP10Vector; }
- bool hasPrefixInstrs() const { return HasPrefixInstrs; }
- bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
- bool hasMMA() const { return HasMMA; }
- bool hasROPProtect() const { return HasROPProtect; }
- bool hasPrivileged() const { return HasPrivileged; }
- bool pairedVectorMemops() const { return PairedVectorMemops; }
- bool hasMFOCRF() const { return HasMFOCRF; }
- bool hasISEL() const { return HasISEL; }
- bool hasBPERMD() const { return HasBPERMD; }
- bool hasExtDiv() const { return HasExtDiv; }
- bool hasCMPB() const { return HasCMPB; }
- bool hasLDBRX() const { return HasLDBRX; }
- bool isBookE() const { return IsBookE; }
- bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
- bool isPPC4xx() const { return IsPPC4xx; }
- bool isPPC6xx() const { return IsPPC6xx; }
- bool isSecurePlt() const {return SecurePlt; }
- bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
- bool isE500() const { return IsE500; }
- bool isFeatureMFTB() const { return FeatureMFTB; }
- bool allowsUnalignedFPAccess() const { return AllowsUnalignedFPAccess; }
- bool isDeprecatedDST() const { return DeprecatedDST; }
- bool hasICBT() const { return HasICBT; }
- bool hasInvariantFunctionDescriptors() const {
- return HasInvariantFunctionDescriptors;
- }
- bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
- bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
- bool hasPartwordAtomics() const { return HasPartwordAtomics; }
- bool hasQuadwordAtomics() const { return HasQuadwordAtomics; }
- bool hasDirectMove() const { return HasDirectMove; }
- bool hasFastMFLR() const { return HasFastMFLR; }
+// Getters for SubtargetFeatures defined in tablegen.
+#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
+ bool GETTER() const { return ATTRIBUTE; }
+#include "PPCGenSubtargetInfo.inc"
Align getPlatformStackAlignment() const {
return Align(16);
@@ -333,27 +195,6 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
return isAIXABI() ? 220 : 0;
}
- bool hasHTM() const { return HasHTM; }
- bool hasFloat128() const { return HasFloat128; }
- bool isISA2_06() const { return IsISA2_06; }
- bool isISA2_07() const { return IsISA2_07; }
- bool isISA3_0() const { return IsISA3_0; }
- bool isISA3_1() const { return IsISA3_1; }
- bool isISAFuture() const { return IsISAFuture; }
- bool useLongCalls() const { return UseLongCalls; }
- bool hasFusion() const { return HasFusion; }
- bool hasStoreFusion() const { return HasStoreFusion; }
- bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
- bool hasAddisLoadFusion() const { return HasAddisLoadFusion; }
- bool hasArithAddFusion() const { return HasArithAddFusion; }
- bool hasAddLogicalFusion() const { return HasAddLogicalFusion; }
- bool hasLogicalAddFusion() const { return HasLogicalAddFusion; }
- bool hasLogicalFusion() const { return HasLogicalFusion; }
- bool hasCompareFusion() const { return HasCompareFusion; }
- bool hasWideImmFusion() const { return HasWideImmFusion; }
- bool hasSha3Fusion() const { return HasSha3Fusion; }
- bool hasZeroMoveFusion() const { return HasZeroMoveFusion; }
- bool hasBack2BackFusion() const { return HasBack2BackFusion; }
bool needsSwapsForVSXMemOps() const {
return hasVSX() && isLittleEndian() && !hasP9Vector();
}
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