[PATCH] D137937: [TableGen] Represent IntrHasSideEffects using inaccessiblemem read+write

[Nikita Popov via Phabricator via llvm-commits]

nikic added a comment.

In D137937#3938649 <https://reviews.llvm.org/D137937#3938649>, @jdoerfert wrote:

> Opened https://github.com/llvm/llvm-project/issues/59076. For now, to move this ahead, we need to remove nomem from all AMDGPU barriers. https://github.com/llvm/llvm-project/blob/3c36de55f5e60dee8f1bc04bd201f6dd762b3423/llvm/include/llvm/IR/IntrinsicsAMDGPU.td#L220

So I tried this, but it doesn't seem to be that simple. There's the diff: https://gist.github.com/nikic/507f6ee3276e66d76b0d4a0c2b9ad7ce

Notably, if we make the barrier read/write in IR, we also need to set mayLoad/mayStore in DAG, and this impact scheduling. I don't know enough about AMDGPU to really interpret those changes, but it looks like we were scheduling at least some loads across a barrier?


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