[PATCH] D139394: [RISCV] Add support for RISCV XVentanaCondops Extension Patterns

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/xventanacondops.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops -stop-after finalize-isel < %s | FileCheck %s -check-prefix=RV64
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kconsul wrote:
> jrtc27 wrote:
> > ... why MIR, just do asm like a normal CodeGen test
> I have implemented changes in RISCV backend so that llc generates these instructions for the select pattern. So to test those patterns we would need MIR right ? 
Normally you just test the asm output like you’re doing now


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  https://reviews.llvm.org/D139394/new/

https://reviews.llvm.org/D139394