[PATCH] D139394: [RISCV] Add support for RISCV XVentanaCondops Extension

[Kautuk Consul via Phabricator via llvm-commits]

kconsul added a comment.

In D139394#3995937 <https://reviews.llvm.org/D139394#3995937>, @jrtc27 wrote:

> Subject and first line of the description should be clear it's about code generation. As it stands it still sounds like you're adding MC support.

I have changed the description to state that I am adding support for xventanacondops patterns.



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Comment at: llvm/test/CodeGen/RISCV/xventanacondops.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops -stop-after finalize-isel < %s | FileCheck %s -check-prefix=RV64
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jrtc27 wrote:
> ... why MIR, just do asm like a normal CodeGen test
I have implemented changes in RISCV backend so that llc generates these instructions for the select pattern. So to test those patterns we would need MIR right ? 


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139394/new/

https://reviews.llvm.org/D139394