[PATCH] D140046: [PowerPC] Fix up memory ordering after combining BV to a load

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai created this revision.
nemanjai added reviewers: lebedev.ri, PowerPC.
Herald added subscribers: shchenz, kbarton, hiraditya.
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The combiner for BUILD_VECTOR that merges consecutive loads into a wide load had two issues:

- It didn't check that the input loads all have the same input chain
- It didn't update nodes that are chained to the original loads to be chained to the new load

This caused issues with bootstrap when 3c4d2a03968ccf5889bacffe02d6fa2443b0260f <https://reviews.llvm.org/rG3c4d2a03968ccf5889bacffe02d6fa2443b0260f> was committed. This patch fixes the issue so it can unblock this commit.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140046

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/build-vector-to-ld-chain.ll

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