[llvm] 1c7c737 - [Hexagon] Handle rounding beyond low 32 bits

[Krzysztof Parzyszek via llvm-commits]

Author: Krzysztof Parzyszek
Date: 2022-12-14T10:25:34-08:00
New Revision: 1c7c7377cb5e12b7bc90d075fc7c79acf48d155a

URL: https://github.com/llvm/llvm-project/commit/1c7c7377cb5e12b7bc90d075fc7c79acf48d155a
DIFF: https://github.com/llvm/llvm-project/commit/1c7c7377cb5e12b7bc90d075fc7c79acf48d155a.diff

LOG: [Hexagon] Handle rounding beyond low 32 bits

Added: 
    llvm/test/CodeGen/Hexagon/autohvx/qmul-add-over-32-bit.ll

Modified: 
    llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
index 3644316c58bc8..7975fdd0fe3dd 100644
--- a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
@@ -1278,11 +1278,11 @@ auto HvxIdioms::matchFxpMul(Instruction &In) const -> std::optional<FxpOp> {
   // Check if there is rounding added.
   const APInt *C = nullptr;
   if (Value * T; Op.Frac > 0 && match(Exp, m_Add(m_Value(T), m_APInt(C)))) {
-    unsigned CV = C->getZExtValue();
-    if (CV != 0 && !isPowerOf2_32(CV))
+    uint64_t CV = C->getZExtValue();
+    if (CV != 0 && !isPowerOf2_64(CV))
       return std::nullopt;
     if (CV != 0)
-      Op.RoundAt = Log2_32(CV);
+      Op.RoundAt = Log2_64(CV);
     Exp = T;
   }
 

diff  --git a/llvm/test/CodeGen/Hexagon/autohvx/qmul-add-over-32-bit.ll b/llvm/test/CodeGen/Hexagon/autohvx/qmul-add-over-32-bit.ll
new file mode 100644
index 0000000000000..866db19355bcf
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/autohvx/qmul-add-over-32-bit.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Make sure the add isn't dropped.
+; CHECK: vadd{{.*}}:carry
+
+target triple = "hexagon"
+
+define <32 x i32> @f0(<32 x i32> %a0) #0 {
+b0:
+  %v0 = sext <32 x i32> %a0 to <32 x i64>
+  %v1 = mul nsw <32 x i64> %v0, <i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240>
+  %v2 = add nsw <32 x i64> %v1, <i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296>
+  %v3 = ashr <32 x i64> %v2, <i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33>
+  %v4 = trunc <32 x i64> %v3 to <32 x i32>
+  ret <32 x i32> %v4
+}
+
+attributes #0 = { noinline "target-cpu"="hexagonv68" "target-features"="+hvxv68,+hvx-length128b,+hvx-qfloat,-hvx-ieee-fp,-packets" }