[PATCH] D140027: [RISCV] Avoid generate large LMUL vmv.s.x or fvmv.s.f

[Philip Reames via Phabricator via llvm-commits]

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This is a follow up to patch discussion on D139656 <https://reviews.llvm.org/D139656>.  As noted there, M2 <https://reviews.llvm.org/M2>/M4/M8 versions of these instructions don't actually exist, and using them results in overly constrained register allocation.

In that review, we'd talked about moving towards a variant of the instructions which ignored LMUL.  I decided to see what happened if we just stopped generating the high LMUL variants, and the results are surprisingly neutral.  I only see one minor thing which looks like a real regression among all the churn.  I think this is worth doing now to loosen register allocation constraints, and avoid digging our hole around these instructions deeper while thinking about the right model change.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140027

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll

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