[PATCH] D139550: [DAGCombine] Fix always true condition in combineShiftToMULH

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.
This revision is now accepted and ready to land.

LGTM with a couple of minors - cheers!



================
Comment at: llvm/test/CodeGen/AMDGPU/dagcomb-mullohi.ll:149
+
+define i32 @mul_one_bit_hi_hi_u32_ashr(i32 %arg, i32 %arg1, i32* %arg2) {
+; CHECK-LABEL: mul_one_bit_hi_hi_u32_ashr:
----------------
mul_one_bit_hi_hi_u32_lshr_ashr ?


================
Comment at: llvm/test/CodeGen/AMDGPU/dagcomb-mullohi.ll:169
+}
\ No newline at end of file

----------------
add newline


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139550/new/

https://reviews.llvm.org/D139550