[llvm] c86a878 - [RISCV] Add Syntacore SCR1 CPU model
Anton Afanasyev via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 14 00:49:55 PST 2022
Author: Dmitrii Petrov
Date: 2022-12-14T11:45:44+03:00
New Revision: c86a878e8995d54a5b950098e81f0d3bf153aded
URL: https://github.com/llvm/llvm-project/commit/c86a878e8995d54a5b950098e81f0d3bf153aded
DIFF: https://github.com/llvm/llvm-project/commit/c86a878e8995d54a5b950098e81f0d3bf153aded.diff
LOG: [RISCV] Add Syntacore SCR1 CPU model
SCR1 is available at https://github.com/syntacore/scr1
'syntacore-scr1-base' corresponds to SCR1_CFG_RV32IC_BASE,
'syntacore-scr1-max' corresponds to SCR1_CFG_RV32IMC_MAX.
SCR1_CFG_RV32EC_MIN is RV32EC, which is currently unsupported.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D139302
Added:
llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
Modified:
clang/test/Driver/riscv-cpus.c
clang/test/Misc/target-invalid-cpu-note.c
llvm/include/llvm/Support/RISCVTargetParser.def
llvm/lib/Target/RISCV/RISCV.td
Removed:
################################################################################
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 32d8569fe06fb..eb05569f8bc1d 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -7,6 +7,16 @@
// MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64"
// MCPU-ROCKET64: "-target-feature" "+64bit"
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-base | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-BASE %s
+// MCPU-SYNTACORE-SCR1-BASE: "-target-cpu" "syntacore-scr1-base"
+// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c" "-target-feature" "-64bit"
+// MCPU-SYNTACORE-SCR1-BASE: "-target-abi" "ilp32"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-max | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-MAX %s
+// MCPU-SYNTACORE-SCR1-MAX: "-target-cpu" "syntacore-scr1-max"
+// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+m" "-target-feature" "+c" "-target-feature" "-64bit"
+// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
+
// We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=native | FileCheck -check-prefix=MCPU-NATIVE %s
// MCPU-NATIVE-NOT: "-target-cpu" "native"
@@ -17,6 +27,12 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket-rv64 | FileCheck -check-prefix=MTUNE-ROCKET64 %s
// MTUNE-ROCKET64: "-tune-cpu" "rocket-rv64"
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-base | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-BASE %s
+// MTUNE-SYNTACORE-SCR1-BASE: "-tune-cpu" "syntacore-scr1-base"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s
+// MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max"
+
// Check mtune alias CPU has resolved to the right CPU according XLEN.
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s
// MTUNE-GENERIC-32: "-tune-cpu" "generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index a8e6dcf9fad02..2d49d370eff26 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -81,7 +81,7 @@
// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
// RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76{{$}}
+// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max{{$}}
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
@@ -89,7 +89,7 @@
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}}
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
diff --git a/llvm/include/llvm/Support/RISCVTargetParser.def b/llvm/include/llvm/Support/RISCVTargetParser.def
index a02e1cc4ed31f..6d65ac1c398e7 100644
--- a/llvm/include/llvm/Support/RISCVTargetParser.def
+++ b/llvm/include/llvm/Support/RISCVTargetParser.def
@@ -19,6 +19,8 @@ PROC(SIFIVE_S54, {"sifive-s54"}, FK_64BIT, {"rv64gc"})
PROC(SIFIVE_S76, {"sifive-s76"}, FK_64BIT, {"rv64gc"})
PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
+PROC(SYNTACORE_SCR1_BASE, {"syntacore-scr1-base"}, FK_NONE, {"rv32ic"})
+PROC(SYNTACORE_SCR1_MAX, {"syntacore-scr1-max"}, FK_NONE, {"rv32imc"})
#undef PROC
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index fd0dd8a759ca7..2ba00bd7b7b72 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -547,6 +547,7 @@ include "RISCVInstrInfo.td"
include "GISel/RISCVRegisterBanks.td"
include "RISCVSchedRocket.td"
include "RISCVSchedSiFive7.td"
+include "RISCVSchedSyntacoreSCR1.td"
//===----------------------------------------------------------------------===//
// RISC-V processors supported.
@@ -638,6 +639,14 @@ def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit,
FeatureStdExtC],
[TuneSiFive7]>;
+def : ProcessorModel<"syntacore-scr1-base", SyntacoreSCR1Model,
+ [Feature32Bit, FeatureStdExtC],
+ [TuneNoDefaultUnroll]>;
+
+def : ProcessorModel<"syntacore-scr1-max", SyntacoreSCR1Model,
+ [Feature32Bit, FeatureStdExtM, FeatureStdExtC],
+ [TuneNoDefaultUnroll]>;
+
//===----------------------------------------------------------------------===//
// Define the RISC-V target.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
new file mode 100644
index 0000000000000..1c6b44beea7a9
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
@@ -0,0 +1,207 @@
+//==- RISCVSchedSyntacoreSCR1.td - Syntacore SCR1 Scheduling Definitions --------*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+
+// SCR1: https://github.com/syntacore/scr1
+
+// This model covers SYNTACORE_SCR1_CFG_RV32IMC_MAX configuration (syntacore-scr1-max).
+// SYNTACORE_SCR1_CFG_RV32IC_BASE (syntacore-scr1-base) configuration has essentially
+// same scheduling characteristics.
+
+// SCR1 is single-issue in-order processor
+def SyntacoreSCR1Model : SchedMachineModel {
+ let MicroOpBufferSize = 0;
+ let IssueWidth = 1;
+ let LoadLatency = 2;
+ let MispredictPenalty = 3;
+ let CompleteModel = 0;
+ let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
+ HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
+ HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
+ HasVInstructions];
+}
+
+let SchedModel = SyntacoreSCR1Model in {
+
+let BufferSize = 0 in {
+def SCR1_ALU : ProcResource<1>;
+def SCR1_LSU : ProcResource<1>;
+def SCR1_MUL : ProcResource<1>;
+def SCR1_DIV : ProcResource<1>;
+def SCR1_CFU : ProcResource<1>;
+}
+
+// Branching
+def : WriteRes<WriteJmp, [SCR1_CFU]>;
+def : WriteRes<WriteJal, [SCR1_CFU]>;
+def : WriteRes<WriteJalr, [SCR1_CFU]>;
+def : WriteRes<WriteJmpReg, [SCR1_CFU]>;
+
+// Integer arithmetic and logic
+def : WriteRes<WriteIALU32, [SCR1_ALU]>;
+def : WriteRes<WriteIALU, [SCR1_ALU]>;
+def : WriteRes<WriteShiftImm32, [SCR1_ALU]>;
+def : WriteRes<WriteShiftImm, [SCR1_ALU]>;
+def : WriteRes<WriteShiftReg32, [SCR1_ALU]>;
+def : WriteRes<WriteShiftReg, [SCR1_ALU]>;
+
+// Integer multiplication: single-cycle multiplier in SCR1_CFG_RV32IMC_MAX
+def : WriteRes<WriteIMul, [SCR1_MUL]>;
+def : WriteRes<WriteIMul32, [SCR1_MUL]>;
+
+// Integer division: latency 33, inverse throughput 33
+let Latency = 33, ResourceCycles = [33] in {
+def : WriteRes<WriteIDiv32, [SCR1_DIV]>;
+def : WriteRes<WriteIDiv, [SCR1_DIV]>;
+}
+
+// Load/store instructions on SCR1 have latency 2 and inverse throughput 2
+// (SCR1_CFG_RV32IMC_MAX includes TCM)
+let Latency = 2, ResourceCycles=[2] in {
+// Memory
+def : WriteRes<WriteSTB, [SCR1_LSU]>;
+def : WriteRes<WriteSTH, [SCR1_LSU]>;
+def : WriteRes<WriteSTW, [SCR1_LSU]>;
+def : WriteRes<WriteSTD, [SCR1_LSU]>;
+def : WriteRes<WriteLDB, [SCR1_LSU]>;
+def : WriteRes<WriteLDH, [SCR1_LSU]>;
+def : WriteRes<WriteLDW, [SCR1_LSU]>;
+def : WriteRes<WriteLDD, [SCR1_LSU]>;
+}
+
+let Unsupported = true in {
+// Atomic memory
+def : WriteRes<WriteAtomicW, [SCR1_LSU]>;
+def : WriteRes<WriteAtomicD, [SCR1_LSU]>;
+def : WriteRes<WriteAtomicLDW, [SCR1_LSU]>;
+def : WriteRes<WriteAtomicLDD, [SCR1_LSU]>;
+def : WriteRes<WriteAtomicSTW, [SCR1_LSU]>;
+def : WriteRes<WriteAtomicSTD, [SCR1_LSU]>;
+
+// FP load/store
+def : WriteRes<WriteFST32, [SCR1_LSU]>;
+def : WriteRes<WriteFST64, [SCR1_LSU]>;
+def : WriteRes<WriteFLD32, [SCR1_LSU]>;
+def : WriteRes<WriteFLD64, [SCR1_LSU]>;
+
+// FP instructions
+def : WriteRes<WriteFAdd32, []>;
+def : WriteRes<WriteFSGNJ32, []>;
+def : WriteRes<WriteFMinMax32, []>;
+def : WriteRes<WriteFAdd64, []>;
+def : WriteRes<WriteFSGNJ64, []>;
+def : WriteRes<WriteFMinMax64, []>;
+def : WriteRes<WriteFCvtI32ToF32, []>;
+def : WriteRes<WriteFCvtI32ToF64, []>;
+def : WriteRes<WriteFCvtI64ToF32, []>;
+def : WriteRes<WriteFCvtI64ToF64, []>;
+def : WriteRes<WriteFCvtF32ToI32, []>;
+def : WriteRes<WriteFCvtF32ToI64, []>;
+def : WriteRes<WriteFCvtF64ToI32, []>;
+def : WriteRes<WriteFCvtF64ToI64, []>;
+def : WriteRes<WriteFCvtF32ToF64, []>;
+def : WriteRes<WriteFCvtF64ToF32, []>;
+def : WriteRes<WriteFClass32, []>;
+def : WriteRes<WriteFClass64, []>;
+def : WriteRes<WriteFCmp32, []>;
+def : WriteRes<WriteFCmp64, []>;
+def : WriteRes<WriteFMovF32ToI32, []>;
+def : WriteRes<WriteFMovI32ToF32, []>;
+def : WriteRes<WriteFMovF64ToI64, []>;
+def : WriteRes<WriteFMovI64ToF64, []>;
+def : WriteRes<WriteFMul32, []>;
+def : WriteRes<WriteFMA32, []>;
+def : WriteRes<WriteFMul64, []>;
+def : WriteRes<WriteFMA64, []>;
+def : WriteRes<WriteFDiv32, []>;
+def : WriteRes<WriteFDiv64, []>;
+def : WriteRes<WriteFSqrt32, []>;
+def : WriteRes<WriteFSqrt64, []>;
+
+def : WriteRes<WriteSFB, []>;
+}
+
+// Others
+def : WriteRes<WriteCSR, []>;
+def : WriteRes<WriteNop, []>;
+
+def : InstRW<[WriteIALU], (instrs COPY)>;
+
+//===----------------------------------------------------------------------===//
+// Bypasses (none)
+def : ReadAdvance<ReadJmp, 0>;
+def : ReadAdvance<ReadJalr, 0>;
+def : ReadAdvance<ReadCSR, 0>;
+def : ReadAdvance<ReadStoreData, 0>;
+def : ReadAdvance<ReadMemBase, 0>;
+def : ReadAdvance<ReadIALU, 0>;
+def : ReadAdvance<ReadIALU32, 0>;
+def : ReadAdvance<ReadShiftImm, 0>;
+def : ReadAdvance<ReadShiftImm32, 0>;
+def : ReadAdvance<ReadShiftReg, 0>;
+def : ReadAdvance<ReadShiftReg32, 0>;
+def : ReadAdvance<ReadIDiv, 0>;
+def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIMul, 0>;
+def : ReadAdvance<ReadIMul32, 0>;
+def : ReadAdvance<ReadAtomicWA, 0>;
+def : ReadAdvance<ReadAtomicWD, 0>;
+def : ReadAdvance<ReadAtomicDA, 0>;
+def : ReadAdvance<ReadAtomicDD, 0>;
+def : ReadAdvance<ReadAtomicLDW, 0>;
+def : ReadAdvance<ReadAtomicLDD, 0>;
+def : ReadAdvance<ReadAtomicSTW, 0>;
+def : ReadAdvance<ReadAtomicSTD, 0>;
+def : ReadAdvance<ReadFStoreData, 0>;
+def : ReadAdvance<ReadFMemBase, 0>;
+def : ReadAdvance<ReadFAdd32, 0>;
+def : ReadAdvance<ReadFAdd64, 0>;
+def : ReadAdvance<ReadFMul32, 0>;
+def : ReadAdvance<ReadFMul64, 0>;
+def : ReadAdvance<ReadFMA32, 0>;
+def : ReadAdvance<ReadFMA64, 0>;
+def : ReadAdvance<ReadFDiv32, 0>;
+def : ReadAdvance<ReadFDiv64, 0>;
+def : ReadAdvance<ReadFSqrt32, 0>;
+def : ReadAdvance<ReadFSqrt64, 0>;
+def : ReadAdvance<ReadFCmp32, 0>;
+def : ReadAdvance<ReadFCmp64, 0>;
+def : ReadAdvance<ReadFSGNJ32, 0>;
+def : ReadAdvance<ReadFSGNJ64, 0>;
+def : ReadAdvance<ReadFMinMax32, 0>;
+def : ReadAdvance<ReadFMinMax64, 0>;
+def : ReadAdvance<ReadFCvtF32ToI32, 0>;
+def : ReadAdvance<ReadFCvtF32ToI64, 0>;
+def : ReadAdvance<ReadFCvtF64ToI32, 0>;
+def : ReadAdvance<ReadFCvtF64ToI64, 0>;
+def : ReadAdvance<ReadFCvtI32ToF32, 0>;
+def : ReadAdvance<ReadFCvtI32ToF64, 0>;
+def : ReadAdvance<ReadFCvtI64ToF32, 0>;
+def : ReadAdvance<ReadFCvtI64ToF64, 0>;
+def : ReadAdvance<ReadFCvtF32ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF32, 0>;
+def : ReadAdvance<ReadFMovF32ToI32, 0>;
+def : ReadAdvance<ReadFMovI32ToF32, 0>;
+def : ReadAdvance<ReadFMovF64ToI64, 0>;
+def : ReadAdvance<ReadFMovI64ToF64, 0>;
+def : ReadAdvance<ReadFClass32, 0>;
+def : ReadAdvance<ReadFClass64, 0>;
+def : ReadAdvance<ReadSFB, 0>;
+
+//===----------------------------------------------------------------------===//
+// Unsupported extensions
+defm : UnsupportedSchedV;
+defm : UnsupportedSchedZba;
+defm : UnsupportedSchedZbb;
+defm : UnsupportedSchedZbc;
+defm : UnsupportedSchedZbs;
+defm : UnsupportedSchedZbkb;
+defm : UnsupportedSchedZbkx;
+defm : UnsupportedSchedZfh;
+}
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