[PATCH] D129735: [RISCV] Add new pass to transform undef to pseudo for vector values.

[Piyou Chen via Phabricator via llvm-commits]

BeMg updated this revision to Diff 482694.
BeMg added a comment.

1. unsigned -> Register
2. use const std::vector<MachineInstr *> & instead of call by value


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
  llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber-vrm4.mir
  llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber_vrm8.mir
  llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
  llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll

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