[PATCH] D139462: [RISCV][CodeGen][SelectionDAG] Recursively check hasAllNBitUsers for logical machine opcodes

[Nitin John Raj via Phabricator via llvm-commits]

nitinjohnraj updated this revision to Diff 482656.
nitinjohnraj added a comment.

Formatting fixed


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139462/new/

https://reviews.llvm.org/D139462

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
  llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/float-convert.ll
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/rem.ll
  llvm/test/CodeGen/RISCV/rotl-rotr.ll
  llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
  llvm/test/CodeGen/RISCV/rv64zbb.ll
  llvm/test/CodeGen/RISCV/rv64zbkb.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
  llvm/test/CodeGen/RISCV/select-binop-identity.ll
  llvm/test/CodeGen/RISCV/sextw-removal.ll
  llvm/test/CodeGen/RISCV/srem-lkk.ll
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
  llvm/test/CodeGen/RISCV/unaligned-load-store.ll
  llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll

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