[llvm] b34bfc6 - [SPARC] Add GNU syntax extensions of WRPR instruction
Brad Smith via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 13 15:03:02 PST 2022
Author: Koakuma
Date: 2022-12-13T18:02:18-05:00
New Revision: b34bfc603cbf44dc6718e592fa9fcc6bfabcce39
URL: https://github.com/llvm/llvm-project/commit/b34bfc603cbf44dc6718e592fa9fcc6bfabcce39
DIFF: https://github.com/llvm/llvm-project/commit/b34bfc603cbf44dc6718e592fa9fcc6bfabcce39.diff
LOG: [SPARC] Add GNU syntax extensions of WRPR instruction
Add two GNU extension forms of wrpr:
wrpr %reg, %rd -> wrpr %reg, %g0, %rd
wrpr imm, %rd -> wrpr %g0, imm, %rd
Note: since the semantics of wrpr %rs1, %rs2/imm, %rd is %rd <- (%rs1 xor %rs2/imm),
in case (1) it technically doesn't matter whether the %g0 is placed as the first or
second operand, however, I'm placing it as the second operand to match the encoding
of GNU as.
This fixes the wrpr instruction part of bug #40792
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D139535
Added:
Modified:
llvm/lib/Target/Sparc/SparcInstrAliases.td
llvm/test/MC/Sparc/sparcv9-instructions.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td b/llvm/lib/Target/Sparc/SparcInstrAliases.td
index 4344ba221a660..f10021321406c 100644
--- a/llvm/lib/Target/Sparc/SparcInstrAliases.td
+++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td
@@ -516,6 +516,14 @@ def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
def : InstAlias<"pwr $rs2, %psr", (PWRPSRrr G0, IntRegs:$rs2), 0>;
def : InstAlias<"pwr $simm13, %psr", (PWRPSRri G0, i32imm:$simm13), 0>;
+// wrpr %reg, %rd -> wrpr %reg, %g0, %rd
+// wrpr imm, %rd -> wrpr %g0, imm, %rd
+// Nonstandard GNU extensions.
+let Predicates = [HasV9] in {
+ def : InstAlias<"wrpr $rs1, $rd", (WRPRrr PRRegs:$rd, IntRegs:$rs1, G0), 0>;
+ def : InstAlias<"wrpr $simm13, $rd", (WRPRri PRRegs:$rd, G0, i32imm:$simm13), 0>;
+}
+
// flush -> flush %g0
def : InstAlias<"flush", (FLUSH), 0>;
diff --git a/llvm/test/MC/Sparc/sparcv9-instructions.s b/llvm/test/MC/Sparc/sparcv9-instructions.s
index 7b130de93b8d6..a60d6281a17ed 100644
--- a/llvm/test/MC/Sparc/sparcv9-instructions.s
+++ b/llvm/test/MC/Sparc/sparcv9-instructions.s
@@ -233,6 +233,128 @@
! V9: wrpr %g6, 255, %wstate ! encoding: [0x9d,0x91,0xa0,0xff]
wrpr %g6,255,%wstate
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr %i6,%tpc
+ ! V9: wrpr %fp, %g0, %tpc ! encoding: [0x81,0x97,0x80,0x00]
+ wrpr %i6,%tpc
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr %i6,%tnpc
+ ! V9: wrpr %fp, %g0, %tnpc ! encoding: [0x83,0x97,0x80,0x00]
+ wrpr %i6,%tnpc
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr %i6,%tstate
+ ! V9: wrpr %fp, %g0, %tstate ! encoding: [0x85,0x97,0x80,0x00]
+ wrpr %i6,%tstate
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr %i6,%tt
+ ! V9: wrpr %fp, %g0, %tt ! encoding: [0x87,0x97,0x80,0x00]
+ wrpr %i6,%tt
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr %i6,%tick
+ ! V9: wrpr %fp, %g0, %tick ! encoding: [0x89,0x97,0x80,0x00]
+ wrpr %i6,%tick
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr %i6,%tba
+ ! V9: wrpr %fp, %g0, %tba ! encoding: [0x8b,0x97,0x80,0x00]
+ wrpr %i6,%tba
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr %i6,%pstate
+ ! V9: wrpr %fp, %g0, %pstate ! encoding: [0x8d,0x97,0x80,0x00]
+ wrpr %i6,%pstate
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr %i6,%tl
+ ! V9: wrpr %fp, %g0, %tl ! encoding: [0x8f,0x97,0x80,0x00]
+ wrpr %i6,%tl
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr %i6,%pil
+ ! V9: wrpr %fp, %g0, %pil ! encoding: [0x91,0x97,0x80,0x00]
+ wrpr %i6,%pil
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr %i6,%cwp
+ ! V9: wrpr %fp, %g0, %cwp ! encoding: [0x93,0x97,0x80,0x00]
+ wrpr %i6,%cwp
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr %i6,%cansave
+ ! V9: wrpr %fp, %g0, %cansave ! encoding: [0x95,0x97,0x80,0x00]
+ wrpr %i6,%cansave
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr %i6,%canrestore
+ ! V9: wrpr %fp, %g0, %canrestore ! encoding: [0x97,0x97,0x80,0x00]
+ wrpr %i6,%canrestore
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr %i6,%cleanwin
+ ! V9: wrpr %fp, %g0, %cleanwin ! encoding: [0x99,0x97,0x80,0x00]
+ wrpr %i6,%cleanwin
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr %i6,%otherwin
+ ! V9: wrpr %fp, %g0, %otherwin ! encoding: [0x9b,0x97,0x80,0x00]
+ wrpr %i6,%otherwin
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr %i6,%wstate
+ ! V9: wrpr %fp, %g0, %wstate ! encoding: [0x9d,0x97,0x80,0x00]
+ wrpr %i6,%wstate
+
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr 255,%tpc
+ ! V9: wrpr %g0, 255, %tpc ! encoding: [0x81,0x90,0x20,0xff]
+ wrpr 255,%tpc
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr 255,%tnpc
+ ! V9: wrpr %g0, 255, %tnpc ! encoding: [0x83,0x90,0x20,0xff]
+ wrpr 255,%tnpc
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr 255,%tstate
+ ! V9: wrpr %g0, 255, %tstate ! encoding: [0x85,0x90,0x20,0xff]
+ wrpr 255,%tstate
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr 255,%tt
+ ! V9: wrpr %g0, 255, %tt ! encoding: [0x87,0x90,0x20,0xff]
+ wrpr 255,%tt
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr 255,%tick
+ ! V9: wrpr %g0, 255, %tick ! encoding: [0x89,0x90,0x20,0xff]
+ wrpr 255,%tick
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr 255,%tba
+ ! V9: wrpr %g0, 255, %tba ! encoding: [0x8b,0x90,0x20,0xff]
+ wrpr 255,%tba
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr 255,%pstate
+ ! V9: wrpr %g0, 255, %pstate ! encoding: [0x8d,0x90,0x20,0xff]
+ wrpr 255,%pstate
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr 255,%tl
+ ! V9: wrpr %g0, 255, %tl ! encoding: [0x8f,0x90,0x20,0xff]
+ wrpr 255,%tl
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr 255,%pil
+ ! V9: wrpr %g0, 255, %pil ! encoding: [0x91,0x90,0x20,0xff]
+ wrpr 255,%pil
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr 255,%cwp
+ ! V9: wrpr %g0, 255, %cwp ! encoding: [0x93,0x90,0x20,0xff]
+ wrpr 255,%cwp
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr 255,%cansave
+ ! V9: wrpr %g0, 255, %cansave ! encoding: [0x95,0x90,0x20,0xff]
+ wrpr 255,%cansave
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr 255,%canrestore
+ ! V9: wrpr %g0, 255, %canrestore ! encoding: [0x97,0x90,0x20,0xff]
+ wrpr 255,%canrestore
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr 255,%cleanwin
+ ! V9: wrpr %g0, 255, %cleanwin ! encoding: [0x99,0x90,0x20,0xff]
+ wrpr 255,%cleanwin
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr 255,%otherwin
+ ! V9: wrpr %g0, 255, %otherwin ! encoding: [0x9b,0x90,0x20,0xff]
+ wrpr 255,%otherwin
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: wrpr 255,%wstate
+ ! V9: wrpr %g0, 255, %wstate ! encoding: [0x9d,0x90,0x20,0xff]
+ wrpr 255,%wstate
+
! V8: error: instruction requires a CPU feature not currently enabled
! V8-NEXT: rdpr %tpc,%i5
! V9: rdpr %tpc, %i5 ! encoding: [0xbb,0x50,0x00,0x00]
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