[PATCH] D132190: [AArch64][GlobalISel] Legalize G_SHUFFLE_VECTOR with different lengths

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added inline comments.
This revision is now accepted and ready to land.


================
Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:4995
+
+    SmallVector<Register, 8> Elts(MaskNumElts);
+    for (unsigned I = 0; I < MaskNumElts; ++I) {
----------------
Maybe use small size 16?


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Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:5000
+                        DestEltTy, Shuffle,
+                        MIRBuilder.buildConstant(LLT::scalar(64), I))
+                    .getReg(0);
----------------
If we don't have a MIRBuilder helper to create an extract with a constant index already, there should be one


================
Comment at: llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir:435
+
+...
----------------
Some odd number of element cases would be nice


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132190/new/

https://reviews.llvm.org/D132190