[PATCH] D139948: [RISCV][WIP] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 13 08:58:03 PST 2022
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h:79
+ bool hasAllNBitUsers(SDNode *Node, unsigned Bits,
+ const unsigned Depth = 0) const;
bool hasAllHUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 16); }
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This appears to be the code from D139462. This should not be part of this diff.
================
Comment at: llvm/test/CodeGen/RISCV/add-before-shl.ll:33
-;
-; RV32C-LABEL: add_small_const:
-; RV32C: # %bb.0:
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Something weird happened here. Why are these lines removed?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D139948/new/
https://reviews.llvm.org/D139948
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