[PATCH] D139398: [AMDGPU] Add bf16 storage support
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 13 07:07:40 PST 2022
arsenm accepted this revision.
arsenm added a comment.
This revision is now accepted and ready to land.
LGTM. with nits The lower could handle the vector case easily, but it didn't before either
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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:2915
+ SDValue Op = Node->getOperand(0);
+ if (Op.getValueType() == MVT::bf16)
+ Op = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32,
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Braces
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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:2944
+ // not supported on the target and was softened to i16 for storage.
+ if (Node->getValueType(0) == MVT::bf16)
+ Op = DAG.getNode(ISD::BITCAST, dl, MVT::bf16,
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Braces
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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:2948
+ else {
+ assert(Node->getValueType(0).isScalarInteger());
+ Op = DAG.getAnyExtOrTrunc(Op, dl, Node->getValueType(0));
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Don't see the point of this assert, should work fine for vectors
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D139398/new/
https://reviews.llvm.org/D139398
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