[PATCH] D129735: [RISCV] Add new pass to transform undef to pseudo for vector values.

[Piyou Chen via Phabricator via llvm-commits]

BeMg added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll:28
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT:    vloxseg2ei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxseg2ei32.v v16, (a0), v8
 ; CHECK-NEXT:    csrr a0, vlenb
----------------
craig.topper wrote:
> Are we treating insert_subreg for segment load tuples the same as inserting a small LMUL into a wider LMUL?
This pass doesn't consider segment load as instruction that assign sub-register. 

The following Insert_subreg work like put %5:vrm2 into %6:vrm4
```
%1:vrm4 = IMPLICIT_DEF
%5:vrm2 = PseudoVLE32_V_M2 killed %4, 0, 5 /* e32 */
%6:vrm4 = INSERT_SUBREG %1, %5, %subreg.sub_vrm2_0
```

Do we should treat vloxseg2ei32 as INSERT_SUBREG in this patch?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735