[llvm] 190eb50 - [AMDGPU][GFX908][DOC][NFC] Update assembler syntax description
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 13 03:15:08 PST 2022
Author: Dmitry Preobrazhensky
Date: 2022-12-13T14:12:09+03:00
New Revision: 190eb50c8bb4bc5640f8f71461dcb5d2fbd527aa
URL: https://github.com/llvm/llvm-project/commit/190eb50c8bb4bc5640f8f71461dcb5d2fbd527aa
DIFF: https://github.com/llvm/llvm-project/commit/190eb50c8bb4bc5640f8f71461dcb5d2fbd527aa.diff
LOG: [AMDGPU][GFX908][DOC][NFC] Update assembler syntax description
Summary of changes:
- Enable VOP3 variants of dot2c/dot4c/dot8c instructions (https://reviews.llvm.org/D138494).
- Enable abs and neg modifiers for v_dot2c_f32_f16_dpp.
- Minor corrections and improvements.
Added:
llvm/docs/AMDGPU/gfx908_m_28b494.rst
llvm/docs/AMDGPU/gfx908_m_c141fc.rst
llvm/docs/AMDGPU/gfx908_src_7c8695.rst
Modified:
llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst
llvm/docs/AMDGPU/gfx908_fx_operand.rst
llvm/docs/AMDGPU/gfx908_srsrc.rst
llvm/docs/AMDGPU/gfx908_type_deviation.rst
Removed:
llvm/docs/AMDGPU/gfx908_m_254bcb.rst
llvm/docs/AMDGPU/gfx908_m_f5d306.rst
llvm/docs/AMDGPU/gfx908_src_58d119.rst
################################################################################
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst
index be0ae0360ca5f..53fe42ed6eec1 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst
@@ -17,7 +17,7 @@ Introduction
This document describes the syntax of *instructions specific to gfx908*.
-For a description of other gfx908 instructions see :doc:`Syntax of Core GFX9 Instructions<AMDGPUAsmGFX9>`.
+For a description of other gfx908 instructions, see :doc:`Syntax of Core GFX9 Instructions<AMDGPUAsmGFX9>`.
Notation
========
@@ -58,32 +58,36 @@ VOP2
.. parsed-literal::
- **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_dot2c_f32_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`
- v_dot2c_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_dot2c_i32_i16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`
- v_dot2c_i32_i16_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_dot4c_i32_i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`
- v_dot4c_i32_i8_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_dot8c_i32_i4 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`
- v_dot8c_i32_i4_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`
- v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_pk_fmac_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`
- v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`
- v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
- v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_dot2c_f32_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`
+ v_dot2c_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_dot2c_i32_i16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`
+ v_dot2c_i32_i16_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_dot4c_i32_i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`
+ v_dot4c_i32_i8_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_dot8c_i32_i4 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`
+ v_dot8c_i32_i4_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`
+ v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_pk_fmac_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`
+ v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>`
+ v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_6802ce>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_28b494>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_28b494>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
VOP3
----
.. parsed-literal::
- **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_fmac_f32_e64 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_xnor_b32_e64 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_dot2c_f32_f16_e64 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_dot2c_i32_i16_e64 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot4c_i32_i8_e64 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`i8x4<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot8c_i32_i4_e64 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fmac_f32_e64 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_xnor_b32_e64 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`
VOP3P
-----
@@ -93,7 +97,7 @@ VOP3P
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
v_accvgpr_read_b32 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx908_vsrc_1027ca>`
- v_accvgpr_write_b32 :ref:`vdst<amdgpu_synid_gfx908_vdst_78dd0a>`, :ref:`src<amdgpu_synid_gfx908_src_58d119>`
+ v_accvgpr_write_b32 :ref:`vdst<amdgpu_synid_gfx908_vdst_78dd0a>`, :ref:`src<amdgpu_synid_gfx908_src_7c8695>`
v_dot2_f32_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`f16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot2_i32_i16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_955b45>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d95796>`::ref:`i16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`i32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot2_u32_u16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_955b45>`::ref:`u16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d95796>`::ref:`u16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`u32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
@@ -101,9 +105,9 @@ VOP3P
v_dot4_u32_u8 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`u8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`u8x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`u32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot8_i32_i4 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`i4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`i32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
v_dot8_u32_u4 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`u4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`u4x8<amdgpu_synid_gfx908_type_deviation>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`u32<amdgpu_synid_gfx908_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
- v_fma_mix_f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_fma_mixhi_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_fma_mixlo_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_f5d306>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mix_f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mixhi_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mixlo_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_4e78e6>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src1<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>`, :ref:`src2<amdgpu_synid_gfx908_src_d578c4>`::ref:`m<amdgpu_synid_gfx908_m_c141fc>`::ref:`fx<amdgpu_synid_gfx908_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
v_mfma_f32_16x16x16f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_bcee7a>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_f3d248>`::ref:`f32x4<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_16x16x1f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_0c4ef8>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_2d4632>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
v_mfma_f32_16x16x2bf16 :ref:`vdst<amdgpu_synid_gfx908_vdst_0c4ef8>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx908_vsrc_be4895>`::ref:`bf16x2<amdgpu_synid_gfx908_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx908_vsrc_2d4632>`::ref:`f32x16<amdgpu_synid_gfx908_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
@@ -131,13 +135,13 @@ VOP3P
:hidden:
gfx908_fx_operand
- gfx908_m_254bcb
- gfx908_m_f5d306
+ gfx908_m_28b494
+ gfx908_m_c141fc
gfx908_saddr
gfx908_soffset
gfx908_src_4e78e6
- gfx908_src_58d119
gfx908_src_73ab34
+ gfx908_src_7c8695
gfx908_src_955b45
gfx908_src_d578c4
gfx908_src_d95796
diff --git a/llvm/docs/AMDGPU/gfx908_fx_operand.rst b/llvm/docs/AMDGPU/gfx908_fx_operand.rst
index 4eb9a8f94387f..bef1de8453ea6 100644
--- a/llvm/docs/AMDGPU/gfx908_fx_operand.rst
+++ b/llvm/docs/AMDGPU/gfx908_fx_operand.rst
@@ -10,7 +10,7 @@
FX Operand
==========
-This is an *f32* or *f16* operand depending on instruction modifiers:
+This is a *f32* or *f16* operand depending on instruction modifiers:
* Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
-* Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
+* Location of the 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
diff --git a/llvm/docs/AMDGPU/gfx908_m_254bcb.rst b/llvm/docs/AMDGPU/gfx908_m_28b494.rst
similarity index 69%
rename from llvm/docs/AMDGPU/gfx908_m_254bcb.rst
rename to llvm/docs/AMDGPU/gfx908_m_28b494.rst
index cb0ae72099ac4..17286bd82de03 100644
--- a/llvm/docs/AMDGPU/gfx908_m_254bcb.rst
+++ b/llvm/docs/AMDGPU/gfx908_m_28b494.rst
@@ -5,9 +5,9 @@
* *
**************************************************
-.. _amdgpu_synid_gfx908_m_254bcb:
+.. _amdgpu_synid_gfx908_m_28b494:
m
=
-This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
+This operand may be used with an integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
diff --git a/llvm/docs/AMDGPU/gfx908_m_f5d306.rst b/llvm/docs/AMDGPU/gfx908_m_c141fc.rst
similarity index 77%
rename from llvm/docs/AMDGPU/gfx908_m_f5d306.rst
rename to llvm/docs/AMDGPU/gfx908_m_c141fc.rst
index 77c14811fc960..e47f77d3c17e8 100644
--- a/llvm/docs/AMDGPU/gfx908_m_f5d306.rst
+++ b/llvm/docs/AMDGPU/gfx908_m_c141fc.rst
@@ -5,9 +5,9 @@
* *
**************************************************
-.. _amdgpu_synid_gfx908_m_f5d306:
+.. _amdgpu_synid_gfx908_m_c141fc:
m
=
-This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
+This operand may be used with floating-point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
diff --git a/llvm/docs/AMDGPU/gfx908_src_58d119.rst b/llvm/docs/AMDGPU/gfx908_src_7c8695.rst
similarity index 63%
rename from llvm/docs/AMDGPU/gfx908_src_58d119.rst
rename to llvm/docs/AMDGPU/gfx908_src_7c8695.rst
index 6a966e16205ee..b5c29a2eaf979 100644
--- a/llvm/docs/AMDGPU/gfx908_src_58d119.rst
+++ b/llvm/docs/AMDGPU/gfx908_src_7c8695.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx908_src_58d119:
+.. _amdgpu_synid_gfx908_src_7c8695:
src
===
@@ -14,4 +14,4 @@ Instruction input.
*Size:* 1 dword.
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`fconst<amdgpu_synid_fconst>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx908_srsrc.rst b/llvm/docs/AMDGPU/gfx908_srsrc.rst
index 359b18e007fd5..a8e4a8cc3a594 100644
--- a/llvm/docs/AMDGPU/gfx908_srsrc.rst
+++ b/llvm/docs/AMDGPU/gfx908_srsrc.rst
@@ -10,7 +10,7 @@
srsrc
=====
-Buffer resource constant which defines the address and characteristics of the buffer in memory.
+Buffer resource constant, which defines the address and characteristics of the buffer in memory.
*Size:* 4 dwords.
diff --git a/llvm/docs/AMDGPU/gfx908_type_deviation.rst b/llvm/docs/AMDGPU/gfx908_type_deviation.rst
index f285d08b30304..1dd044a7f53fa 100644
--- a/llvm/docs/AMDGPU/gfx908_type_deviation.rst
+++ b/llvm/docs/AMDGPU/gfx908_type_deviation.rst
@@ -10,4 +10,4 @@
Type Deviation
==============
-*Type* of this operand
diff ers from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_mnemo>`. This tag specifies actual operand *type*.
+The *type* of this operand
diff ers from the *type* :ref:`implied by the opcode<amdgpu_syn_instruction_mnemo>`. This tag specifies the actual operand *type*.
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