[llvm] cc42640 - [AMDGPU][GFX7][DOC][NFC] Update assembler syntax description
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 13 02:51:02 PST 2022
Author: Dmitry Preobrazhensky
Date: 2022-12-13T13:50:40+03:00
New Revision: cc426402bed6b576086357f36b21879bfe365939
URL: https://github.com/llvm/llvm-project/commit/cc426402bed6b576086357f36b21879bfe365939
DIFF: https://github.com/llvm/llvm-project/commit/cc426402bed6b576086357f36b21879bfe365939.diff
LOG: [AMDGPU][GFX7][DOC][NFC] Update assembler syntax description
Summary of changes:
- Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205).
- Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783).
- Enable abs and neg modifiers for v_cndmask_b32_e64.
- Minor corrections and improvements.
Added:
llvm/docs/AMDGPU/gfx7_imm16_0533c2.rst
llvm/docs/AMDGPU/gfx7_imm16_169952.rst
llvm/docs/AMDGPU/gfx7_sbase_b0aa25.rst
llvm/docs/AMDGPU/gfx7_soffset_67d76d.rst
llvm/docs/AMDGPU/gfx7_srsrc_80eef6.rst
llvm/docs/AMDGPU/gfx7_vaddr_887f26.rst
llvm/docs/AMDGPU/gfx7_vdata_2d6239.rst
llvm/docs/AMDGPU/gfx7_vdata_4b260e.rst
llvm/docs/AMDGPU/gfx7_vdata_84fab6.rst
llvm/docs/AMDGPU/gfx7_vdata_aa5a53.rst
llvm/docs/AMDGPU/gfx7_vdata_ad559c.rst
llvm/docs/AMDGPU/gfx7_vdst_1f3009.rst
llvm/docs/AMDGPU/gfx7_vdst_709347.rst
llvm/docs/AMDGPU/gfx7_vdst_81a6ed.rst
llvm/docs/AMDGPU/gfx7_vdst_d71f1c.rst
llvm/docs/AMDGPU/gfx7_vdst_dd8a32.rst
llvm/docs/AMDGPU/gfx7_vdst_dfa6da.rst
llvm/docs/AMDGPU/gfx7_vsrc_ba3116.rst
Modified:
llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst
llvm/docs/AMDGPU/gfx7_hwreg.rst
llvm/docs/AMDGPU/gfx7_label.rst
llvm/docs/AMDGPU/gfx7_m.rst
llvm/docs/AMDGPU/gfx7_msg.rst
llvm/docs/AMDGPU/gfx7_tgt.rst
llvm/docs/AMDGPU/gfx7_type_deviation.rst
llvm/docs/AMDGPU/gfx7_waitcnt.rst
Removed:
llvm/docs/AMDGPU/gfx7_imm16_73139a.rst
llvm/docs/AMDGPU/gfx7_imm16_a04fb3.rst
llvm/docs/AMDGPU/gfx7_sbase_010ce0.rst
llvm/docs/AMDGPU/gfx7_soffset_1bad09.rst
llvm/docs/AMDGPU/gfx7_srsrc_e73d16.rst
llvm/docs/AMDGPU/gfx7_vaddr_e9b690.rst
llvm/docs/AMDGPU/gfx7_vdata_325b78.rst
llvm/docs/AMDGPU/gfx7_vdata_4d8ecf.rst
llvm/docs/AMDGPU/gfx7_vdata_87fb90.rst
llvm/docs/AMDGPU/gfx7_vdata_b2a787.rst
llvm/docs/AMDGPU/gfx7_vdata_c61803.rst
llvm/docs/AMDGPU/gfx7_vdst_0c25a6.rst
llvm/docs/AMDGPU/gfx7_vdst_3d7dcf.rst
llvm/docs/AMDGPU/gfx7_vdst_5d50a1.rst
llvm/docs/AMDGPU/gfx7_vsrc_533a4e.rst
################################################################################
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst
index 355623c313359..6c28480ac0223 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst
@@ -183,7 +183,7 @@ EXP
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- exp :ref:`tgt<amdgpu_synid_gfx7_tgt>`, :ref:`vsrc0<amdgpu_synid_gfx7_vsrc_533a4e>`, :ref:`vsrc1<amdgpu_synid_gfx7_vsrc_533a4e>`, :ref:`vsrc2<amdgpu_synid_gfx7_vsrc_533a4e>`, :ref:`vsrc3<amdgpu_synid_gfx7_vsrc_533a4e>` :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
+ exp :ref:`tgt<amdgpu_synid_gfx7_tgt>`, :ref:`vsrc0<amdgpu_synid_gfx7_vsrc_ba3116>`, :ref:`vsrc1<amdgpu_synid_gfx7_vsrc_ba3116>`, :ref:`vsrc2<amdgpu_synid_gfx7_vsrc_ba3116>`, :ref:`vsrc3<amdgpu_synid_gfx7_vsrc_ba3116>` :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
FLAT
----
@@ -246,98 +246,98 @@ MIMG
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- image_atomic_add :ref:`vdata<amdgpu_synid_gfx7_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_and :ref:`vdata<amdgpu_synid_gfx7_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx7_vdata_4d8ecf>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_dec :ref:`vdata<amdgpu_synid_gfx7_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx7_vdata_4d8ecf>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_fmax :ref:`vdata<amdgpu_synid_gfx7_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_fmin :ref:`vdata<amdgpu_synid_gfx7_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_inc :ref:`vdata<amdgpu_synid_gfx7_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_or :ref:`vdata<amdgpu_synid_gfx7_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_smax :ref:`vdata<amdgpu_synid_gfx7_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_smin :ref:`vdata<amdgpu_synid_gfx7_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_sub :ref:`vdata<amdgpu_synid_gfx7_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_swap :ref:`vdata<amdgpu_synid_gfx7_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_umax :ref:`vdata<amdgpu_synid_gfx7_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_umin :ref:`vdata<amdgpu_synid_gfx7_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_atomic_xor :ref:`vdata<amdgpu_synid_gfx7_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4 :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_b :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_b_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_b_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_b_o :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_c :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_c_b :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_c_b_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_c_b_o :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_c_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_c_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_c_l :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_c_l_o :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_c_lz :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_c_lz_o :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_c_o :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_l :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_l_o :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_lz :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_lz_o :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_gather4_o :ref:`vdst<amdgpu_synid_gfx7_vdst_0c25a6>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_get_lod :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_get_resinfo :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load_mip :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load_mip_pck :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load_pck :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_load_pck_sgn :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_b :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_b_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_b_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_b_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_b :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_b_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_b_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_cd :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_cd_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_cd_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_d :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_d_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_d_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_d_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_l :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_l_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_lz :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_lz_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_c_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_cd :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_cd_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_cd_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_cd_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_d :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_d_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_d_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_d_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_l :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_l_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_lz :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_lz_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_sample_o :ref:`vdst<amdgpu_synid_gfx7_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_store :ref:`vdata<amdgpu_synid_gfx7_vdata_c08393>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_store_mip :ref:`vdata<amdgpu_synid_gfx7_vdata_c08393>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_store_mip_pck :ref:`vdata<amdgpu_synid_gfx7_vdata_c08393>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
- image_store_pck :ref:`vdata<amdgpu_synid_gfx7_vdata_c08393>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_e9b690>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_add :ref:`vdata<amdgpu_synid_gfx7_vdata_aa5a53>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_and :ref:`vdata<amdgpu_synid_gfx7_vdata_aa5a53>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx7_vdata_84fab6>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_dec :ref:`vdata<amdgpu_synid_gfx7_vdata_aa5a53>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx7_vdata_84fab6>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_fmax :ref:`vdata<amdgpu_synid_gfx7_vdata_aa5a53>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_fmin :ref:`vdata<amdgpu_synid_gfx7_vdata_aa5a53>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_inc :ref:`vdata<amdgpu_synid_gfx7_vdata_aa5a53>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_or :ref:`vdata<amdgpu_synid_gfx7_vdata_aa5a53>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_smax :ref:`vdata<amdgpu_synid_gfx7_vdata_aa5a53>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_smin :ref:`vdata<amdgpu_synid_gfx7_vdata_aa5a53>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_sub :ref:`vdata<amdgpu_synid_gfx7_vdata_aa5a53>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_swap :ref:`vdata<amdgpu_synid_gfx7_vdata_aa5a53>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_umax :ref:`vdata<amdgpu_synid_gfx7_vdata_aa5a53>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_umin :ref:`vdata<amdgpu_synid_gfx7_vdata_aa5a53>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_xor :ref:`vdata<amdgpu_synid_gfx7_vdata_aa5a53>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4 :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_b :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_b_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_b_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_b_o :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_b :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_b_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_b_o :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_l :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_l_o :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_lz :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_lz_o :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_o :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_l :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_l_o :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_lz :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_lz_o :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_o :ref:`vdst<amdgpu_synid_gfx7_vdst_1f3009>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_get_lod :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_get_resinfo :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_mip :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_mip_pck :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_pck :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_pck_sgn :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_b :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_b_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_b_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_b_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_b :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_b_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_b_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_cd :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_cd_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_cd_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_d :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_d_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_d_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_d_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_l :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_l_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_lz :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_lz_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_cd :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_cd_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_cd_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_cd_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_d :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_d_cl :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_d_cl_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_d_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_l :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_l_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_lz :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_lz_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_o :ref:`vdst<amdgpu_synid_gfx7_vdst_dfa6da>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx7_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_store :ref:`vdata<amdgpu_synid_gfx7_vdata_c08393>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_store_mip :ref:`vdata<amdgpu_synid_gfx7_vdata_c08393>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_store_mip_pck :ref:`vdata<amdgpu_synid_gfx7_vdata_c08393>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_store_pck :ref:`vdata<amdgpu_synid_gfx7_vdata_c08393>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_887f26>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
MTBUF
-----
@@ -346,14 +346,14 @@ MTBUF
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- tbuffer_load_format_x :ref:`vdst<amdgpu_synid_gfx7_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx7_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx7_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx7_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_x :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx7_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx7_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx7_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_x :ref:`vdst<amdgpu_synid_gfx7_vdst_709347>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx7_vdst_d71f1c>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx7_vdst_81a6ed>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx7_vdst_dd8a32>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_x :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx7_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx7_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx7_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
MUBUF
-----
@@ -361,61 +361,61 @@ MUBUF
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- buffer_atomic_add :ref:`vdata<amdgpu_synid_gfx7_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_and :ref:`vdata<amdgpu_synid_gfx7_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`b32x2<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_87fb90>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`b64x2<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_dec :ref:`vdata<amdgpu_synid_gfx7_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`f32x2<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fcmpswap_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_87fb90>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`f64x2<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fmax :ref:`vdata<amdgpu_synid_gfx7_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`f32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fmax_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`f64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fmin :ref:`vdata<amdgpu_synid_gfx7_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`f32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fmin_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`f64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_inc :ref:`vdata<amdgpu_synid_gfx7_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_or :ref:`vdata<amdgpu_synid_gfx7_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smax :ref:`vdata<amdgpu_synid_gfx7_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`i32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`i64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smin :ref:`vdata<amdgpu_synid_gfx7_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`i32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`i64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_sub :ref:`vdata<amdgpu_synid_gfx7_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_swap :ref:`vdata<amdgpu_synid_gfx7_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umax :ref:`vdata<amdgpu_synid_gfx7_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umin :ref:`vdata<amdgpu_synid_gfx7_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_xor :ref:`vdata<amdgpu_synid_gfx7_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_dword :ref:`vdst<amdgpu_synid_gfx7_vdst_875645>`::ref:`opt<amdgpu_synid_gfx7_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx7_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx7_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx7_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_x :ref:`vdst<amdgpu_synid_gfx7_vdst_875645>`::ref:`opt<amdgpu_synid_gfx7_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx7_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx7_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx7_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_load_sbyte :ref:`vdst<amdgpu_synid_gfx7_vdst_875645>`::ref:`opt<amdgpu_synid_gfx7_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_sshort :ref:`vdst<amdgpu_synid_gfx7_vdst_875645>`::ref:`opt<amdgpu_synid_gfx7_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_ubyte :ref:`vdst<amdgpu_synid_gfx7_vdst_875645>`::ref:`opt<amdgpu_synid_gfx7_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_ushort :ref:`vdst<amdgpu_synid_gfx7_vdst_875645>`::ref:`opt<amdgpu_synid_gfx7_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_store_byte :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dword :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx2 :ref:`vdata<amdgpu_synid_gfx7_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx3 :ref:`vdata<amdgpu_synid_gfx7_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx4 :ref:`vdata<amdgpu_synid_gfx7_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_x :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx7_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx7_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx7_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_short :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ buffer_atomic_add :ref:`vdata<amdgpu_synid_gfx7_vdata_ad559c>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and :ref:`vdata<amdgpu_synid_gfx7_vdata_ad559c>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`b32x2<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_2d6239>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`b64x2<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec :ref:`vdata<amdgpu_synid_gfx7_vdata_ad559c>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`f32x2<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fcmpswap_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_2d6239>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`f64x2<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmax :ref:`vdata<amdgpu_synid_gfx7_vdata_ad559c>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`f32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmax_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`f64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmin :ref:`vdata<amdgpu_synid_gfx7_vdata_ad559c>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`f32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmin_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`f64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc :ref:`vdata<amdgpu_synid_gfx7_vdata_ad559c>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or :ref:`vdata<amdgpu_synid_gfx7_vdata_ad559c>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax :ref:`vdata<amdgpu_synid_gfx7_vdata_ad559c>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`i32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`i64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin :ref:`vdata<amdgpu_synid_gfx7_vdata_ad559c>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`i32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`i64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub :ref:`vdata<amdgpu_synid_gfx7_vdata_ad559c>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap :ref:`vdata<amdgpu_synid_gfx7_vdata_ad559c>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax :ref:`vdata<amdgpu_synid_gfx7_vdata_ad559c>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin :ref:`vdata<amdgpu_synid_gfx7_vdata_ad559c>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u32<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`::ref:`u64<amdgpu_synid_gfx7_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor :ref:`vdata<amdgpu_synid_gfx7_vdata_ad559c>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid_gfx7_vdata_4b260e>`::ref:`dst<amdgpu_synid_gfx7_dst>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_dword :ref:`vdst<amdgpu_synid_gfx7_vdst_875645>`::ref:`opt<amdgpu_synid_gfx7_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`tfe<amdgpu_synid_tfe>`
+ buffer_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx7_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>`
+ buffer_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx7_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>`
+ buffer_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx7_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>`
+ buffer_load_format_x :ref:`vdst<amdgpu_synid_gfx7_vdst_875645>`::ref:`opt<amdgpu_synid_gfx7_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`tfe<amdgpu_synid_tfe>`
+ buffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx7_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>`
+ buffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx7_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>`
+ buffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx7_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>`
+ buffer_load_sbyte :ref:`vdst<amdgpu_synid_gfx7_vdst_875645>`::ref:`opt<amdgpu_synid_gfx7_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`tfe<amdgpu_synid_tfe>`
+ buffer_load_sshort :ref:`vdst<amdgpu_synid_gfx7_vdst_875645>`::ref:`opt<amdgpu_synid_gfx7_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`tfe<amdgpu_synid_tfe>`
+ buffer_load_ubyte :ref:`vdst<amdgpu_synid_gfx7_vdst_875645>`::ref:`opt<amdgpu_synid_gfx7_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`tfe<amdgpu_synid_tfe>`
+ buffer_load_ushort :ref:`vdst<amdgpu_synid_gfx7_vdst_875645>`::ref:`opt<amdgpu_synid_gfx7_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`tfe<amdgpu_synid_tfe>`
+ buffer_store_byte :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dword :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx2 :ref:`vdata<amdgpu_synid_gfx7_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx3 :ref:`vdata<amdgpu_synid_gfx7_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx4 :ref:`vdata<amdgpu_synid_gfx7_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_x :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx7_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx7_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx7_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_short :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_da1f09>`, :ref:`srsrc<amdgpu_synid_gfx7_srsrc_80eef6>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_48c95e>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_wbinvl1
buffer_wbinvl1_vol
@@ -426,18 +426,18 @@ SMRD
**INSTRUCTION** **DST** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- s_buffer_load_dword :ref:`sdst<amdgpu_synid_gfx7_sdst_2a1d2e>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_1bad09>`
- s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx7_sdst_313759>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_1bad09>`
- s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx7_sdst_9172f3>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_1bad09>`
- s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx7_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_1bad09>`
- s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx7_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_1bad09>`
+ s_buffer_load_dword :ref:`sdst<amdgpu_synid_gfx7_sdst_2a1d2e>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_b0aa25>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_67d76d>`
+ s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx7_sdst_313759>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_b0aa25>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_67d76d>`
+ s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx7_sdst_9172f3>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_b0aa25>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_67d76d>`
+ s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx7_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_b0aa25>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_67d76d>`
+ s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx7_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_b0aa25>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_67d76d>`
s_dcache_inv
s_dcache_inv_vol
- s_load_dword :ref:`sdst<amdgpu_synid_gfx7_sdst_2a1d2e>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_382fdf>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_1bad09>`
- s_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx7_sdst_313759>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_382fdf>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_1bad09>`
- s_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx7_sdst_9172f3>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_382fdf>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_1bad09>`
- s_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx7_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_382fdf>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_1bad09>`
- s_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx7_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_382fdf>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_1bad09>`
+ s_load_dword :ref:`sdst<amdgpu_synid_gfx7_sdst_2a1d2e>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_382fdf>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_67d76d>`
+ s_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx7_sdst_313759>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_382fdf>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_67d76d>`
+ s_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx7_sdst_9172f3>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_382fdf>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_67d76d>`
+ s_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx7_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_382fdf>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_67d76d>`
+ s_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx7_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx7_sbase_382fdf>`, :ref:`soffset<amdgpu_synid_gfx7_soffset_67d76d>`
s_memtime :ref:`sdst<amdgpu_synid_gfx7_sdst_9172f3>`::ref:`b64<amdgpu_synid_gfx7_type_deviation>`
SOP1
@@ -579,24 +579,24 @@ SOPK
**INSTRUCTION** **DST** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- s_addk_i32 :ref:`sdst<amdgpu_synid_gfx7_sdst_6cc8e9>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
+ s_addk_i32 :ref:`sdst<amdgpu_synid_gfx7_sdst_6cc8e9>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
s_cbranch_i_fork :ref:`ssrc<amdgpu_synid_gfx7_ssrc_c5f5de>`, :ref:`label<amdgpu_synid_gfx7_label>`
- s_cmovk_i32 :ref:`sdst<amdgpu_synid_gfx7_sdst_6cc8e9>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
- s_cmpk_eq_i32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
- s_cmpk_eq_u32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_a04fb3>`
- s_cmpk_ge_i32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
- s_cmpk_ge_u32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_a04fb3>`
- s_cmpk_gt_i32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
- s_cmpk_gt_u32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_a04fb3>`
- s_cmpk_le_i32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
- s_cmpk_le_u32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_a04fb3>`
- s_cmpk_lg_i32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
- s_cmpk_lg_u32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_a04fb3>`
- s_cmpk_lt_i32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
- s_cmpk_lt_u32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_a04fb3>`
+ s_cmovk_i32 :ref:`sdst<amdgpu_synid_gfx7_sdst_6cc8e9>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
+ s_cmpk_eq_i32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
+ s_cmpk_eq_u32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_169952>`
+ s_cmpk_ge_i32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
+ s_cmpk_ge_u32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_169952>`
+ s_cmpk_gt_i32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
+ s_cmpk_gt_u32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_169952>`
+ s_cmpk_le_i32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
+ s_cmpk_le_u32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_169952>`
+ s_cmpk_lg_i32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
+ s_cmpk_lg_u32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_169952>`
+ s_cmpk_lt_i32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
+ s_cmpk_lt_u32 :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_169952>`
s_getreg_b32 :ref:`sdst<amdgpu_synid_gfx7_sdst_6cc8e9>`, :ref:`hwreg<amdgpu_synid_gfx7_hwreg>`
- s_movk_i32 :ref:`sdst<amdgpu_synid_gfx7_sdst_6cc8e9>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
- s_mulk_i32 :ref:`sdst<amdgpu_synid_gfx7_sdst_6cc8e9>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
+ s_movk_i32 :ref:`sdst<amdgpu_synid_gfx7_sdst_6cc8e9>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
+ s_mulk_i32 :ref:`sdst<amdgpu_synid_gfx7_sdst_6cc8e9>`, :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
s_setreg_b32 :ref:`hwreg<amdgpu_synid_gfx7_hwreg>`, :ref:`ssrc<amdgpu_synid_gfx7_ssrc_a778e3>`
s_setreg_imm32_b32 :ref:`hwreg<amdgpu_synid_gfx7_hwreg>`, :ref:`simm32<amdgpu_synid_gfx7_simm32_a3e80c>`
@@ -619,18 +619,18 @@ SOPP
s_cbranch_scc1 :ref:`label<amdgpu_synid_gfx7_label>`
s_cbranch_vccnz :ref:`label<amdgpu_synid_gfx7_label>`
s_cbranch_vccz :ref:`label<amdgpu_synid_gfx7_label>`
- s_decperflevel :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
+ s_decperflevel :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
s_endpgm
s_icache_inv
- s_incperflevel :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
- s_nop :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
+ s_incperflevel :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
+ s_nop :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
s_sendmsg :ref:`msg<amdgpu_synid_gfx7_msg>`
s_sendmsghalt :ref:`msg<amdgpu_synid_gfx7_msg>`
- s_sethalt :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
- s_setkill :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
- s_setprio :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
- s_sleep :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
- s_trap :ref:`imm16<amdgpu_synid_gfx7_imm16_73139a>`
+ s_sethalt :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
+ s_setkill :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
+ s_setprio :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
+ s_sleep :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
+ s_trap :ref:`imm16<amdgpu_synid_gfx7_imm16_0533c2>`
s_ttracedata
s_waitcnt :ref:`waitcnt<amdgpu_synid_gfx7_waitcnt>`
@@ -996,7 +996,7 @@ VOP3
v_cmpx_tru_f64_e64 :ref:`sdst<amdgpu_synid_gfx7_sdst_9172f3>`, :ref:`src0<amdgpu_synid_gfx7_src_3865f6>`::ref:`m<amdgpu_synid_gfx7_m>`, :ref:`src1<amdgpu_synid_gfx7_src_3865f6>`::ref:`m<amdgpu_synid_gfx7_m>`
v_cmpx_u_f32_e64 :ref:`sdst<amdgpu_synid_gfx7_sdst_9172f3>`, :ref:`src0<amdgpu_synid_gfx7_src_d56c56>`::ref:`m<amdgpu_synid_gfx7_m>`, :ref:`src1<amdgpu_synid_gfx7_src_8e54a0>`::ref:`m<amdgpu_synid_gfx7_m>`
v_cmpx_u_f64_e64 :ref:`sdst<amdgpu_synid_gfx7_sdst_9172f3>`, :ref:`src0<amdgpu_synid_gfx7_src_3865f6>`::ref:`m<amdgpu_synid_gfx7_m>`, :ref:`src1<amdgpu_synid_gfx7_src_3865f6>`::ref:`m<amdgpu_synid_gfx7_m>`
- v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx7_src_d56c56>`, :ref:`src1<amdgpu_synid_gfx7_src_8e54a0>`, :ref:`ssrc2<amdgpu_synid_gfx7_ssrc_bdc010>`
+ v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx7_src_d56c56>`::ref:`m<amdgpu_synid_gfx7_m>`, :ref:`src1<amdgpu_synid_gfx7_src_8e54a0>`::ref:`m<amdgpu_synid_gfx7_m>`, :ref:`ssrc2<amdgpu_synid_gfx7_ssrc_bdc010>`
v_cos_f32_e64 :ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx7_src_d56c56>`::ref:`m<amdgpu_synid_gfx7_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_cubeid_f32 :ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx7_src_d56c56>`::ref:`m<amdgpu_synid_gfx7_m>`, :ref:`src1<amdgpu_synid_gfx7_src_8e54a0>`::ref:`m<amdgpu_synid_gfx7_m>`, :ref:`src2<amdgpu_synid_gfx7_src_8e54a0>`::ref:`m<amdgpu_synid_gfx7_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_cubema_f32 :ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx7_src_d56c56>`::ref:`m<amdgpu_synid_gfx7_m>`, :ref:`src1<amdgpu_synid_gfx7_src_8e54a0>`::ref:`m<amdgpu_synid_gfx7_m>`, :ref:`src2<amdgpu_synid_gfx7_src_8e54a0>`::ref:`m<amdgpu_synid_gfx7_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
@@ -1354,16 +1354,16 @@ VOPC
gfx7_attr
gfx7_dst
gfx7_hwreg
- gfx7_imm16_73139a
- gfx7_imm16_a04fb3
+ gfx7_imm16_0533c2
+ gfx7_imm16_169952
gfx7_label
gfx7_m
gfx7_msg
gfx7_opt_0d447d
gfx7_opt_847aed
gfx7_param
- gfx7_sbase_010ce0
gfx7_sbase_382fdf
+ gfx7_sbase_b0aa25
gfx7_sdst_0804b1
gfx7_sdst_2a1d2e
gfx7_sdst_313759
@@ -1374,8 +1374,8 @@ VOPC
gfx7_sdst_e3bd3f
gfx7_simm32_6f0844
gfx7_simm32_a3e80c
- gfx7_soffset_1bad09
gfx7_soffset_48c95e
+ gfx7_soffset_67d76d
gfx7_src_1f730e
gfx7_src_3865f6
gfx7_src_3e3a6b
@@ -1387,8 +1387,8 @@ VOPC
gfx7_src_d48e27
gfx7_src_d56c56
gfx7_src_fa88a6
+ gfx7_srsrc_80eef6
gfx7_srsrc_cf7132
- gfx7_srsrc_e73d16
gfx7_ssamp
gfx7_ssrc_19a078
gfx7_ssrc_2e8313
@@ -1403,40 +1403,43 @@ VOPC
gfx7_ssrc_fdbed3
gfx7_tgt
gfx7_type_deviation
+ gfx7_vaddr_887f26
gfx7_vaddr_9f7133
gfx7_vaddr_da1f09
- gfx7_vaddr_e9b690
gfx7_vaddr_f20ee4
gfx7_vcc
gfx7_vdata0_6802ce
gfx7_vdata0_fd235e
gfx7_vdata1_6802ce
gfx7_vdata1_fd235e
- gfx7_vdata_325b78
- gfx7_vdata_4d8ecf
+ gfx7_vdata_2d6239
+ gfx7_vdata_4b260e
gfx7_vdata_56f215
gfx7_vdata_6802ce
- gfx7_vdata_87fb90
- gfx7_vdata_b2a787
+ gfx7_vdata_84fab6
+ gfx7_vdata_aa5a53
+ gfx7_vdata_ad559c
gfx7_vdata_c08393
- gfx7_vdata_c61803
gfx7_vdata_e016a1
gfx7_vdata_fd235e
- gfx7_vdst_0c25a6
- gfx7_vdst_3d7dcf
+ gfx7_vdst_1f3009
gfx7_vdst_463513
gfx7_vdst_48e42f
- gfx7_vdst_5d50a1
gfx7_vdst_69a144
+ gfx7_vdst_709347
+ gfx7_vdst_81a6ed
gfx7_vdst_875645
gfx7_vdst_89680f
gfx7_vdst_a49b76
gfx7_vdst_bdb32f
gfx7_vdst_d0dc43
+ gfx7_vdst_d71f1c
gfx7_vdst_d7c57e
+ gfx7_vdst_dd8a32
+ gfx7_vdst_dfa6da
gfx7_vdst_f47754
- gfx7_vsrc_533a4e
gfx7_vsrc_6802ce
+ gfx7_vsrc_ba3116
gfx7_vsrc_e016a1
gfx7_vsrc_fd235e
gfx7_waitcnt
diff --git a/llvm/docs/AMDGPU/gfx7_hwreg.rst b/llvm/docs/AMDGPU/gfx7_hwreg.rst
index d365376535167..726e32ee5591d 100644
--- a/llvm/docs/AMDGPU/gfx7_hwreg.rst
+++ b/llvm/docs/AMDGPU/gfx7_hwreg.rst
@@ -24,27 +24,27 @@ The bits of this operand have the following meaning:
This operand may be specified as one of the following:
-* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
-* An *hwreg* value described below.
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 0xFFFF.
+* An *hwreg* value which is described below.
- ==================================== ============================================================================
+ ==================================== ===============================================================================
Hwreg Value Syntax Description
- ==================================== ============================================================================
- hwreg({0..63}) All bits of a register indicated by its *id*.
- hwreg(<*name*>) All bits of a register indicated by its *name*.
- hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
- hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
- ==================================== ============================================================================
+ ==================================== ===============================================================================
+ hwreg({0..63}) All bits of a register indicated by the register *id*.
+ hwreg(<*name*>) All bits of a register indicated by the register *name*.
+ hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by the register *id*, first bit *offset* and *size*.
+ hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by the register *name*, first bit *offset* and *size*.
+ ==================================== ===============================================================================
Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
-Defined register *names* include:
+Predefined register *names* include:
============================== ==========================================
Name Description
============================== ==========================================
- HW_REG_MODE Shader writeable mode bits.
+ HW_REG_MODE Shader writable mode bits.
HW_REG_STATUS Shader read-only status.
HW_REG_TRAPSTS Trap status.
HW_REG_HW_ID Id of wave, simd, compute unit, etc.
diff --git a/llvm/docs/AMDGPU/gfx7_imm16_a04fb3.rst b/llvm/docs/AMDGPU/gfx7_imm16_0533c2.rst
similarity index 83%
rename from llvm/docs/AMDGPU/gfx7_imm16_a04fb3.rst
rename to llvm/docs/AMDGPU/gfx7_imm16_0533c2.rst
index 0857c9caf2aba..f2d61cb9a66a8 100644
--- a/llvm/docs/AMDGPU/gfx7_imm16_a04fb3.rst
+++ b/llvm/docs/AMDGPU/gfx7_imm16_0533c2.rst
@@ -5,9 +5,9 @@
* *
**************************************************
-.. _amdgpu_synid_gfx7_imm16_a04fb3:
+.. _amdgpu_synid_gfx7_imm16_0533c2:
imm16
=====
-An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from -32768 to 65535.
diff --git a/llvm/docs/AMDGPU/gfx7_imm16_73139a.rst b/llvm/docs/AMDGPU/gfx7_imm16_169952.rst
similarity index 84%
rename from llvm/docs/AMDGPU/gfx7_imm16_73139a.rst
rename to llvm/docs/AMDGPU/gfx7_imm16_169952.rst
index 6b8eb6846267f..ba386fdb515bf 100644
--- a/llvm/docs/AMDGPU/gfx7_imm16_73139a.rst
+++ b/llvm/docs/AMDGPU/gfx7_imm16_169952.rst
@@ -5,9 +5,9 @@
* *
**************************************************
-.. _amdgpu_synid_gfx7_imm16_73139a:
+.. _amdgpu_synid_gfx7_imm16_169952:
imm16
=====
-An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 65535.
diff --git a/llvm/docs/AMDGPU/gfx7_label.rst b/llvm/docs/AMDGPU/gfx7_label.rst
index 3804a54ee5d81..d52940730b65c 100644
--- a/llvm/docs/AMDGPU/gfx7_label.rst
+++ b/llvm/docs/AMDGPU/gfx7_label.rst
@@ -10,11 +10,11 @@
label
=====
-A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
+A branch target, which is a 16-bit signed integer treated as a PC-relative dword offset.
This operand may be specified as one of the following:
-* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from -32768 to 65535.
* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
Examples:
diff --git a/llvm/docs/AMDGPU/gfx7_m.rst b/llvm/docs/AMDGPU/gfx7_m.rst
index 293fa5a42e97e..ff17b5f1adcf6 100644
--- a/llvm/docs/AMDGPU/gfx7_m.rst
+++ b/llvm/docs/AMDGPU/gfx7_m.rst
@@ -10,4 +10,4 @@
m
=
-This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
+This operand may be used with floating-point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
diff --git a/llvm/docs/AMDGPU/gfx7_msg.rst b/llvm/docs/AMDGPU/gfx7_msg.rst
index 58db37680c49a..29b4a6365af6a 100644
--- a/llvm/docs/AMDGPU/gfx7_msg.rst
+++ b/llvm/docs/AMDGPU/gfx7_msg.rst
@@ -24,8 +24,8 @@ A 16-bit message code. The bits of this operand have the following meaning:
This operand may be specified as one of the following:
-* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
-* A *sendmsg* value described below.
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 0xFFFF.
+* A *sendmsg* value which is described below.
==================================== ====================================================
Sendmsg Value Syntax Description
@@ -40,7 +40,7 @@ This operand may be specified as one of the following:
*Op* may be specified using operation *name* or operation *id*.
-Stream *id* is an integer in the range 0..3.
+Stream *id* is an integer in the range from 0 to 3.
Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
@@ -67,7 +67,7 @@ Each message type supports specific operations:
*Sendmsg* arguments are validated depending on how *type* value is specified:
* If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above.
-* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table).
+* If message *type* is specified as a number, each argument must not exceed the corresponding value range (see the first table).
Examples:
diff --git a/llvm/docs/AMDGPU/gfx7_sbase_010ce0.rst b/llvm/docs/AMDGPU/gfx7_sbase_b0aa25.rst
similarity index 83%
rename from llvm/docs/AMDGPU/gfx7_sbase_010ce0.rst
rename to llvm/docs/AMDGPU/gfx7_sbase_b0aa25.rst
index 338f2dcab9a93..84cbc83b7bb95 100644
--- a/llvm/docs/AMDGPU/gfx7_sbase_010ce0.rst
+++ b/llvm/docs/AMDGPU/gfx7_sbase_b0aa25.rst
@@ -5,12 +5,12 @@
* *
**************************************************
-.. _amdgpu_synid_gfx7_sbase_010ce0:
+.. _amdgpu_synid_gfx7_sbase_b0aa25:
sbase
=====
-A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
+A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size, and a stride.
*Size:* 4 dwords.
diff --git a/llvm/docs/AMDGPU/gfx7_soffset_1bad09.rst b/llvm/docs/AMDGPU/gfx7_soffset_67d76d.rst
similarity index 87%
rename from llvm/docs/AMDGPU/gfx7_soffset_1bad09.rst
rename to llvm/docs/AMDGPU/gfx7_soffset_67d76d.rst
index 929cbf18450c0..ef9b6e924b7a3 100644
--- a/llvm/docs/AMDGPU/gfx7_soffset_1bad09.rst
+++ b/llvm/docs/AMDGPU/gfx7_soffset_67d76d.rst
@@ -5,12 +5,12 @@
* *
**************************************************
-.. _amdgpu_synid_gfx7_soffset_1bad09:
+.. _amdgpu_synid_gfx7_soffset_67d76d:
soffset
=======
-An unsigned offset added to the base address to get memory address.
+An unsigned offset, which is added to the base address to get the memory address.
* If offset is specified as a register, it supplies an unsigned byte offset but 2 lsb's are ignored.
* If offset is specified as an :ref:`uimm32<amdgpu_synid_uimm32>`, it supplies a 32-bit unsigned byte offset but 2 lsb's are ignored.
diff --git a/llvm/docs/AMDGPU/gfx7_srsrc_e73d16.rst b/llvm/docs/AMDGPU/gfx7_srsrc_80eef6.rst
similarity index 74%
rename from llvm/docs/AMDGPU/gfx7_srsrc_e73d16.rst
rename to llvm/docs/AMDGPU/gfx7_srsrc_80eef6.rst
index eccb5d2ed6c12..708e71bfe7ca9 100644
--- a/llvm/docs/AMDGPU/gfx7_srsrc_e73d16.rst
+++ b/llvm/docs/AMDGPU/gfx7_srsrc_80eef6.rst
@@ -5,12 +5,12 @@
* *
**************************************************
-.. _amdgpu_synid_gfx7_srsrc_e73d16:
+.. _amdgpu_synid_gfx7_srsrc_80eef6:
srsrc
=====
-Buffer resource constant which defines the address and characteristics of the buffer in memory.
+Buffer resource constant, which defines the address and characteristics of the buffer in memory.
*Size:* 4 dwords.
diff --git a/llvm/docs/AMDGPU/gfx7_tgt.rst b/llvm/docs/AMDGPU/gfx7_tgt.rst
index a8ae43f512438..d9681853ebd12 100644
--- a/llvm/docs/AMDGPU/gfx7_tgt.rst
+++ b/llvm/docs/AMDGPU/gfx7_tgt.rst
@@ -21,3 +21,10 @@ An export target:
mrtz Copy pixel depth (Z) data.
null Copy nothing.
================== ===================================
+
+Examples:
+
+.. parsed-literal::
+
+ exp pos3 v1, v2, v3, v4
+ exp mrt0 v1, v2, v3, v4
diff --git a/llvm/docs/AMDGPU/gfx7_type_deviation.rst b/llvm/docs/AMDGPU/gfx7_type_deviation.rst
index 876d13df7e4bd..e6edb31d99ea7 100644
--- a/llvm/docs/AMDGPU/gfx7_type_deviation.rst
+++ b/llvm/docs/AMDGPU/gfx7_type_deviation.rst
@@ -10,4 +10,4 @@
Type Deviation
==============
-*Type* of this operand
diff ers from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_mnemo>`. This tag specifies actual operand *type*.
+The *type* of this operand
diff ers from the *type* :ref:`implied by the opcode<amdgpu_syn_instruction_mnemo>`. This tag specifies the actual operand *type*.
diff --git a/llvm/docs/AMDGPU/gfx7_vaddr_e9b690.rst b/llvm/docs/AMDGPU/gfx7_vaddr_887f26.rst
similarity index 54%
rename from llvm/docs/AMDGPU/gfx7_vaddr_e9b690.rst
rename to llvm/docs/AMDGPU/gfx7_vaddr_887f26.rst
index 3c6ec6d75167f..5ece30ab221f7 100644
--- a/llvm/docs/AMDGPU/gfx7_vaddr_e9b690.rst
+++ b/llvm/docs/AMDGPU/gfx7_vaddr_887f26.rst
@@ -5,17 +5,15 @@
* *
**************************************************
-.. _amdgpu_synid_gfx7_vaddr_e9b690:
+.. _amdgpu_synid_gfx7_vaddr_887f26:
vaddr
=====
Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
-*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode and specific image being handled.
+*Size:* 1-12 dwords. Actual size depends on opcode and specific image being handled.
- Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
-
- Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
+ Note. Image format and dimensions are encoded in the image resource constant, but not in the instruction.
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx7_vdata_c61803.rst b/llvm/docs/AMDGPU/gfx7_vdata_2d6239.rst
similarity index 74%
rename from llvm/docs/AMDGPU/gfx7_vdata_c61803.rst
rename to llvm/docs/AMDGPU/gfx7_vdata_2d6239.rst
index 7842b8e66a4c6..e51b248f2ddf1 100644
--- a/llvm/docs/AMDGPU/gfx7_vdata_c61803.rst
+++ b/llvm/docs/AMDGPU/gfx7_vdata_2d6239.rst
@@ -5,17 +5,17 @@
* *
**************************************************
-.. _amdgpu_synid_gfx7_vdata_c61803:
+.. _amdgpu_synid_gfx7_vdata_2d6239:
vdata
=====
Input data for an atomic instruction.
-Optionally may serve as an output data:
+Optionally, this operand may be used to store output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+*Size:* 4 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx7_vdata_87fb90.rst b/llvm/docs/AMDGPU/gfx7_vdata_4b260e.rst
similarity index 74%
rename from llvm/docs/AMDGPU/gfx7_vdata_87fb90.rst
rename to llvm/docs/AMDGPU/gfx7_vdata_4b260e.rst
index 489860be7ef2e..b019f24a318c9 100644
--- a/llvm/docs/AMDGPU/gfx7_vdata_87fb90.rst
+++ b/llvm/docs/AMDGPU/gfx7_vdata_4b260e.rst
@@ -5,17 +5,17 @@
* *
**************************************************
-.. _amdgpu_synid_gfx7_vdata_87fb90:
+.. _amdgpu_synid_gfx7_vdata_4b260e:
vdata
=====
Input data for an atomic instruction.
-Optionally may serve as an output data:
+Optionally, this operand may be used to store output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+*Size:* 2 dwords.
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx7_vdata_4d8ecf.rst b/llvm/docs/AMDGPU/gfx7_vdata_84fab6.rst
similarity index 73%
rename from llvm/docs/AMDGPU/gfx7_vdata_4d8ecf.rst
rename to llvm/docs/AMDGPU/gfx7_vdata_84fab6.rst
index 944f1861e6f74..facf9b6eef03b 100644
--- a/llvm/docs/AMDGPU/gfx7_vdata_4d8ecf.rst
+++ b/llvm/docs/AMDGPU/gfx7_vdata_84fab6.rst
@@ -5,22 +5,22 @@
* *
**************************************************
-.. _amdgpu_synid_gfx7_vdata_4d8ecf:
+.. _amdgpu_synid_gfx7_vdata_84fab6:
vdata
=====
Input data for an atomic instruction.
-Optionally may serve as an output data:
+Optionally, this operand may be used to store output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
-* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
- Note: the surface data format is indicated in the image resource constant but not in the instruction.
+
+ Note: the surface data format is indicated in the image resource constant, but not in the instruction.
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx7_vdata_325b78.rst b/llvm/docs/AMDGPU/gfx7_vdata_aa5a53.rst
similarity index 73%
rename from llvm/docs/AMDGPU/gfx7_vdata_325b78.rst
rename to llvm/docs/AMDGPU/gfx7_vdata_aa5a53.rst
index 225ea408f5545..b341a7296a0be 100644
--- a/llvm/docs/AMDGPU/gfx7_vdata_325b78.rst
+++ b/llvm/docs/AMDGPU/gfx7_vdata_aa5a53.rst
@@ -5,22 +5,22 @@
* *
**************************************************
-.. _amdgpu_synid_gfx7_vdata_325b78:
+.. _amdgpu_synid_gfx7_vdata_aa5a53:
vdata
=====
Input data for an atomic instruction.
-Optionally may serve as an output data:
+Optionally, this operand may be used to store output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
-* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
- Note: the surface data format is indicated in the image resource constant but not in the instruction.
+
+ Note: the surface data format is indicated in the image resource constant, but not in the instruction.
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx7_vdata_b2a787.rst b/llvm/docs/AMDGPU/gfx7_vdata_ad559c.rst
similarity index 74%
rename from llvm/docs/AMDGPU/gfx7_vdata_b2a787.rst
rename to llvm/docs/AMDGPU/gfx7_vdata_ad559c.rst
index fca927c1f221d..9ab8277586fb6 100644
--- a/llvm/docs/AMDGPU/gfx7_vdata_b2a787.rst
+++ b/llvm/docs/AMDGPU/gfx7_vdata_ad559c.rst
@@ -5,17 +5,17 @@
* *
**************************************************
-.. _amdgpu_synid_gfx7_vdata_b2a787:
+.. _amdgpu_synid_gfx7_vdata_ad559c:
vdata
=====
Input data for an atomic instruction.
-Optionally may serve as an output data:
+Optionally, this operand may be used to store output data:
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx7_vdst_0c25a6.rst b/llvm/docs/AMDGPU/gfx7_vdst_1f3009.rst
similarity index 83%
rename from llvm/docs/AMDGPU/gfx7_vdst_0c25a6.rst
rename to llvm/docs/AMDGPU/gfx7_vdst_1f3009.rst
index 284b247211fea..141e2863be831 100644
--- a/llvm/docs/AMDGPU/gfx7_vdst_0c25a6.rst
+++ b/llvm/docs/AMDGPU/gfx7_vdst_1f3009.rst
@@ -5,12 +5,12 @@
* *
**************************************************
-.. _amdgpu_synid_gfx7_vdst_0c25a6:
+.. _amdgpu_synid_gfx7_vdst_1f3009:
vdst
====
-Image data to load by an *image_gather4* instruction.
+Image data to be loaded by an *image_gather4* instruction.
*Size:* 4 data elements by default. Each data element occupies 1 dword. :ref:`tfe<amdgpu_synid_tfe>` adds one more dword if specified.
diff --git a/llvm/docs/AMDGPU/gfx7_vdst_5d50a1.rst b/llvm/docs/AMDGPU/gfx7_vdst_709347.rst
similarity index 76%
rename from llvm/docs/AMDGPU/gfx7_vdst_5d50a1.rst
rename to llvm/docs/AMDGPU/gfx7_vdst_709347.rst
index c6dc1704cbb25..9f7f40d890757 100644
--- a/llvm/docs/AMDGPU/gfx7_vdst_5d50a1.rst
+++ b/llvm/docs/AMDGPU/gfx7_vdst_709347.rst
@@ -5,13 +5,13 @@
* *
**************************************************
-.. _amdgpu_synid_gfx7_vdst_5d50a1:
+.. _amdgpu_synid_gfx7_vdst_709347:
vdst
====
Instruction output: data read from a memory buffer.
-*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx7_vdst_81a6ed.rst b/llvm/docs/AMDGPU/gfx7_vdst_81a6ed.rst
new file mode 100644
index 0000000000000..e129f9e365085
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_vdst_81a6ed.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx7_vdst_81a6ed:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx7_vdst_d71f1c.rst b/llvm/docs/AMDGPU/gfx7_vdst_d71f1c.rst
new file mode 100644
index 0000000000000..66e4f2baf33fa
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_vdst_d71f1c.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx7_vdst_d71f1c:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx7_vdst_dd8a32.rst b/llvm/docs/AMDGPU/gfx7_vdst_dd8a32.rst
new file mode 100644
index 0000000000000..af48cd92cb289
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_vdst_dd8a32.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx7_vdst_dd8a32:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx7_vdst_3d7dcf.rst b/llvm/docs/AMDGPU/gfx7_vdst_dfa6da.rst
similarity index 87%
rename from llvm/docs/AMDGPU/gfx7_vdst_3d7dcf.rst
rename to llvm/docs/AMDGPU/gfx7_vdst_dfa6da.rst
index 07338f34c6bba..2fb8750192729 100644
--- a/llvm/docs/AMDGPU/gfx7_vdst_3d7dcf.rst
+++ b/llvm/docs/AMDGPU/gfx7_vdst_dfa6da.rst
@@ -5,12 +5,12 @@
* *
**************************************************
-.. _amdgpu_synid_gfx7_vdst_3d7dcf:
+.. _amdgpu_synid_gfx7_vdst_dfa6da:
vdst
====
-Image data to load by an image instruction.
+Image data to be loaded by an image instruction.
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
diff --git a/llvm/docs/AMDGPU/gfx7_vsrc_533a4e.rst b/llvm/docs/AMDGPU/gfx7_vsrc_ba3116.rst
similarity index 79%
rename from llvm/docs/AMDGPU/gfx7_vsrc_533a4e.rst
rename to llvm/docs/AMDGPU/gfx7_vsrc_ba3116.rst
index 8008b886f95d9..a342f01faa453 100644
--- a/llvm/docs/AMDGPU/gfx7_vsrc_533a4e.rst
+++ b/llvm/docs/AMDGPU/gfx7_vsrc_ba3116.rst
@@ -5,14 +5,14 @@
* *
**************************************************
-.. _amdgpu_synid_gfx7_vsrc_533a4e:
+.. _amdgpu_synid_gfx7_vsrc_ba3116:
vsrc
====
Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
-:ref:`compr<amdgpu_synid_compr>` modifier indicates use of compressed (16-bit) data. This limits number of source operands from 4 to 2:
+The :ref:`compr<amdgpu_synid_compr>` modifier indicates the use of compressed (16-bit) data, thus decreasing the number of source operands from 4 to 2:
* src0 and src1 must specify the first register (or :ref:`off<amdgpu_synid_off>`).
* src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
diff --git a/llvm/docs/AMDGPU/gfx7_waitcnt.rst b/llvm/docs/AMDGPU/gfx7_waitcnt.rst
index 03253d7d82087..29a412789ca8c 100644
--- a/llvm/docs/AMDGPU/gfx7_waitcnt.rst
+++ b/llvm/docs/AMDGPU/gfx7_waitcnt.rst
@@ -24,7 +24,7 @@ The bits of this operand have the following meaning:
This operand may be specified as one of the following:
-* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 0xFFFF.
* A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below.
====================== ======================================================================
@@ -38,7 +38,8 @@ This operand may be specified as one of the following:
lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
====================== ======================================================================
-These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators.
+These values may be specified in any order. Spaces, ampersands, and commas may be used as optional separators.
+If some values are omitted, the corresponding fields will default to their maximum value.
*N* is either an
:ref:`integer number<amdgpu_synid_integer_number>` or an
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