[llvm] d4fd275 - [NFC][PowerPC] Add tests for 64-bit constants that require 5 instructions to materialize.

[via llvm-commits]

Author: esmeyi
Date: 2022-12-13T02:44:49-05:00
New Revision: d4fd2758962cfbb0367ace6ca0b72fbb70529d77

URL: https://github.com/llvm/llvm-project/commit/d4fd2758962cfbb0367ace6ca0b72fbb70529d77
DIFF: https://github.com/llvm/llvm-project/commit/d4fd2758962cfbb0367ace6ca0b72fbb70529d77.diff

LOG: [NFC][PowerPC] Add tests for 64-bit constants that require 5 instructions to materialize.

Differential Revision: https://reviews.llvm.org/D139914

Added: 
    

Modified: 
    llvm/test/CodeGen/PowerPC/constants-i64.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/PowerPC/constants-i64.ll b/llvm/test/CodeGen/PowerPC/constants-i64.ll
index 130586e5076d..423836b57cf3 100644
--- a/llvm/test/CodeGen/PowerPC/constants-i64.ll
+++ b/llvm/test/CodeGen/PowerPC/constants-i64.ll
@@ -375,4 +375,30 @@ entry:
   ret i64 11174473921
 }
 
+define i64 @imm19() {
+; CHECK-LABEL: imm19:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  lis 3, -13105
+; CHECK-NEXT:  ori 3, 3, 52479
+; CHECK-NEXT:  rldic 3, 3, 32, 0
+; CHECK-NEXT:  oris 3, 3, 52431
+; CHECK-NEXT:  ori 3, 3, 291
+; CHECK-NEXT:  blr
+entry:
+  ret i64 14758239902941249827 ;0xCCCFCCFFCCCF0123
+}
+
+define i64 @imm20() {
+; CHECK-LABEL: imm20:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  lis 3, -13057
+; CHECK-NEXT:  ori 3, 3, 52479
+; CHECK-NEXT:  rldic 3, 3, 32, 0
+; CHECK-NEXT:  oris 3, 3, 291
+; CHECK-NEXT:  ori 3, 3, 52479
+; CHECK-NEXT:  blr
+entry:
+  ret i64 14771750698406366463 ;0xCCFFCCFF0123CCFF
+}
+
 attributes #0 = { nounwind readnone }