[PATCH] D139874: [AMDGPU] Lower VGPR to physical SGPR COPY to S_MOV_B32 if VGPR contains the compile time constant

[Alexander via Phabricator via llvm-commits]

alex-t created this revision.
alex-t added reviewers: JonChesterfield, arsenm, rampitec.
Herald added subscribers: kosarev, foad, kerbowa, hiraditya, tpr, dstuttard, yaxunl, jvesely, kzhuravl.
Herald added a project: All.
alex-t requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

Sometimes we have a constant value loaded to VGPR. In case we further
need to rematrerialize it in the physical scalar register we may avoid VGPR to
SGPR copy replacing it with S_MOV_B32.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139874

Files:
  llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp


Index: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -845,6 +845,18 @@
               TII->get(AMDGPU::V_READFIRSTLANE_B32), TmpReg)
           .add(MI.getOperand(1));
       MI.getOperand(1).setReg(TmpReg);
+    } else {
+      MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
+      if (DefMI && DefMI->isMoveImmediate()) {
+        MachineOperand SrcConst = DefMI->getOperand(1);
+        assert(SrcConst.isImm() && "Operand should be immediate");
+        Register TmpReg =
+          MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
+        BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
+              TII->get(AMDGPU::S_MOV_B32), TmpReg)
+              .addImm(SrcConst.getImm());
+        MI.getOperand(1).setReg(TmpReg);
+      }
     }
     return true;
   }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D139874.482226.patch
Type: text/x-patch
Size: 939 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221212/442d792a/attachment.bin>