[PATCH] D139873: [RISCV] Add support for the vscale_range attribute.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: reames, frasercrmck, rogfer01, kito-cheng, arcbbb.
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This is based on @frasercrmck's D107290 <https://reviews.llvm.org/D107290>. I had to make modifications
to support -riscv-v-vector-bits-min=-1. At least some of the clang
portion of D107290 <https://reviews.llvm.org/D107290> has already been committed.

This uses vscale_range for min/max vector width unless the command
line overrides are used.

As a follow up, I plan to add a max or exact VLEN option to clang
to control the vscale_range. This will eliminate many of the reasons
for users to use the overrides through the -mllvm interface.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139873

Files:
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll
  llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
  llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll

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